1 ;; Predicate definitions for ARM and Thumb
2 ;; Copyright (C) 2004-2013 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_predicate "s_register_operand"
22 (match_code "reg,subreg")
24 if (GET_CODE (op) == SUBREG)
26 /* We don't consider registers whose class is NO_REGS
27 to be a register operand. */
28 /* XXX might have to check for lo regs only for thumb ??? */
30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
34 (define_predicate "imm_for_neon_inv_logic_operand"
35 (match_code "const_vector")
38 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
41 (define_predicate "neon_inv_logic_op2"
42 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
43 (match_operand 0 "s_register_operand")))
45 (define_predicate "imm_for_neon_logic_operand"
46 (match_code "const_vector")
49 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
52 (define_predicate "neon_logic_op2"
53 (ior (match_operand 0 "imm_for_neon_logic_operand")
54 (match_operand 0 "s_register_operand")))
57 (define_predicate "arm_hard_register_operand"
60 return REGNO (op) < FIRST_PSEUDO_REGISTER;
64 (define_predicate "low_register_operand"
65 (and (match_code "reg")
66 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
68 ;; A low register or const_int.
69 (define_predicate "low_reg_or_int_operand"
70 (ior (match_code "const_int")
71 (match_operand 0 "low_register_operand")))
73 ;; Any core register, or any pseudo. */
74 (define_predicate "arm_general_register_operand"
75 (match_code "reg,subreg")
77 if (GET_CODE (op) == SUBREG)
81 && (REGNO (op) <= LAST_ARM_REGNUM
82 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
85 (define_predicate "vfp_register_operand"
86 (match_code "reg,subreg")
88 if (GET_CODE (op) == SUBREG)
91 /* We don't consider registers whose class is NO_REGS
92 to be a register operand. */
94 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
95 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
96 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
98 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
101 (define_predicate "zero_operand"
102 (and (match_code "const_int,const_double,const_vector")
103 (match_test "op == CONST0_RTX (mode)")))
105 ;; Match a register, or zero in the appropriate mode.
106 (define_predicate "reg_or_zero_operand"
107 (ior (match_operand 0 "s_register_operand")
108 (match_operand 0 "zero_operand")))
110 (define_special_predicate "subreg_lowpart_operator"
111 (and (match_code "subreg")
112 (match_test "subreg_lowpart_p (op)")))
114 ;; Reg, subreg(reg) or const_int.
115 (define_predicate "reg_or_int_operand"
116 (ior (match_code "const_int")
117 (match_operand 0 "s_register_operand")))
119 (define_predicate "arm_immediate_operand"
120 (and (match_code "const_int")
121 (match_test "const_ok_for_arm (INTVAL (op))")))
123 ;; A constant value which fits into two instructions, each taking
124 ;; an arithmetic constant operand for one of the words.
125 (define_predicate "arm_immediate_di_operand"
126 (and (match_code "const_int,const_double")
127 (match_test "arm_const_double_by_immediates (op)")))
129 (define_predicate "arm_neg_immediate_operand"
130 (and (match_code "const_int")
131 (match_test "const_ok_for_arm (-INTVAL (op))")))
133 (define_predicate "arm_not_immediate_operand"
134 (and (match_code "const_int")
135 (match_test "const_ok_for_arm (~INTVAL (op))")))
137 (define_predicate "const0_operand"
138 (and (match_code "const_int")
139 (match_test "INTVAL (op) == 0")))
141 ;; Something valid on the RHS of an ARM data-processing instruction
142 (define_predicate "arm_rhs_operand"
143 (ior (match_operand 0 "s_register_operand")
144 (match_operand 0 "arm_immediate_operand")))
146 (define_predicate "arm_rhsm_operand"
147 (ior (match_operand 0 "arm_rhs_operand")
148 (match_operand 0 "memory_operand")))
150 ;; This doesn't have to do much because the constant is already checked
151 ;; in the shift_operator predicate.
152 (define_predicate "shift_amount_operand"
153 (ior (and (match_test "TARGET_ARM")
154 (match_operand 0 "s_register_operand"))
155 (match_operand 0 "const_int_operand")))
157 (define_predicate "const_neon_scalar_shift_amount_operand"
158 (and (match_code "const_int")
159 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode)
160 && ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0")))
162 (define_predicate "ldrd_strd_offset_operand"
163 (and (match_operand 0 "const_int_operand")
164 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))")))
166 (define_predicate "arm_add_operand"
167 (ior (match_operand 0 "arm_rhs_operand")
168 (match_operand 0 "arm_neg_immediate_operand")))
170 (define_predicate "arm_anddi_operand_neon"
171 (ior (match_operand 0 "s_register_operand")
172 (and (match_code "const_int")
173 (match_test "const_ok_for_dimode_op (INTVAL (op), AND)"))
174 (match_operand 0 "neon_inv_logic_op2")))
176 (define_predicate "arm_iordi_operand_neon"
177 (ior (match_operand 0 "s_register_operand")
178 (and (match_code "const_int")
179 (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)"))
180 (match_operand 0 "neon_logic_op2")))
182 (define_predicate "arm_xordi_operand"
183 (ior (match_operand 0 "s_register_operand")
184 (and (match_code "const_int")
185 (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)"))))
187 (define_predicate "arm_adddi_operand"
188 (ior (match_operand 0 "s_register_operand")
189 (and (match_code "const_int")
190 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)"))))
192 (define_predicate "arm_addimm_operand"
193 (ior (match_operand 0 "arm_immediate_operand")
194 (match_operand 0 "arm_neg_immediate_operand")))
196 (define_predicate "arm_not_operand"
197 (ior (match_operand 0 "arm_rhs_operand")
198 (match_operand 0 "arm_not_immediate_operand")))
200 (define_predicate "arm_di_operand"
201 (ior (match_operand 0 "s_register_operand")
202 (match_operand 0 "arm_immediate_di_operand")))
204 ;; True if the operand is a memory reference which contains an
205 ;; offsettable address.
206 (define_predicate "offsettable_memory_operand"
207 (and (match_code "mem")
209 "offsettable_address_p (reload_completed | reload_in_progress,
210 mode, XEXP (op, 0))")))
212 ;; True if the operand is a memory operand that does not have an
213 ;; automodified base register (and thus will not generate output reloads).
214 (define_predicate "call_memory_operand"
215 (and (match_code "mem")
216 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
218 (match_operand 0 "memory_operand"))))
220 (define_predicate "arm_reload_memory_operand"
221 (and (match_code "mem,reg,subreg")
222 (match_test "(!CONSTANT_P (op)
223 && (true_regnum(op) == -1
225 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
227 (define_predicate "vfp_compare_operand"
228 (ior (match_operand 0 "s_register_operand")
229 (and (match_code "const_double")
230 (match_test "arm_const_double_rtx (op)"))))
232 (define_predicate "arm_float_compare_operand"
233 (if_then_else (match_test "TARGET_VFP")
234 (match_operand 0 "vfp_compare_operand")
235 (match_operand 0 "s_register_operand")))
237 ;; True for valid index operands.
238 (define_predicate "index_operand"
239 (ior (match_operand 0 "s_register_operand")
240 (and (match_operand 0 "immediate_operand")
241 (match_test "(!CONST_INT_P (op)
242 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
244 ;; True for operators that can be combined with a shift in ARM state.
245 (define_special_predicate "shiftable_operator"
246 (and (match_code "plus,minus,ior,xor,and")
247 (match_test "mode == GET_MODE (op)")))
249 (define_special_predicate "shiftable_operator_strict_it"
250 (and (match_code "plus,and")
251 (match_test "mode == GET_MODE (op)")))
253 ;; True for logical binary operators.
254 (define_special_predicate "logical_binary_operator"
255 (and (match_code "ior,xor,and")
256 (match_test "mode == GET_MODE (op)")))
258 ;; True for commutative operators
259 (define_special_predicate "commutative_binary_operator"
260 (and (match_code "ior,xor,and,plus")
261 (match_test "mode == GET_MODE (op)")))
263 ;; True for shift operators.
265 ;; * mult is only permitted with a constant shift amount
266 ;; * patterns that permit register shift amounts only in ARM mode use
267 ;; shift_amount_operand, patterns that always allow registers do not,
268 ;; so we don't have to worry about that sort of thing here.
269 (define_special_predicate "shift_operator"
270 (and (ior (ior (and (match_code "mult")
271 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
272 (and (match_code "rotate")
273 (match_test "CONST_INT_P (XEXP (op, 1))
274 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
275 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
276 (match_test "!CONST_INT_P (XEXP (op, 1))
277 || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
278 (match_test "mode == GET_MODE (op)")))
280 ;; True for shift operators which can be used with saturation instructions.
281 (define_special_predicate "sat_shift_operator"
282 (and (ior (and (match_code "mult")
283 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
284 (and (match_code "ashift,ashiftrt")
285 (match_test "CONST_INT_P (XEXP (op, 1))
286 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
287 (match_test "mode == GET_MODE (op)")))
289 ;; True for MULT, to identify which variant of shift_operator is in use.
290 (define_special_predicate "mult_operator"
293 ;; True for operators that have 16-bit thumb variants. */
294 (define_special_predicate "thumb_16bit_operator"
295 (match_code "plus,minus,and,ior,xor"))
298 (define_special_predicate "equality_operator"
299 (match_code "eq,ne"))
301 ;; True for integer comparisons and, if FP is active, for comparisons
302 ;; other than LTGT or UNEQ.
303 (define_special_predicate "expandable_comparison_operator"
304 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
305 unordered,ordered,unlt,unle,unge,ungt"))
307 ;; Likewise, but only accept comparisons that are directly supported
308 ;; by ARM condition codes.
309 (define_special_predicate "arm_comparison_operator"
310 (and (match_operand 0 "expandable_comparison_operator")
311 (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
313 (define_special_predicate "lt_ge_comparison_operator"
314 (match_code "lt,ge"))
316 ;; The vsel instruction only accepts the ARM condition codes listed below.
317 (define_special_predicate "arm_vsel_comparison_operator"
318 (and (match_operand 0 "expandable_comparison_operator")
319 (match_test "maybe_get_arm_condition_code (op) == ARM_GE
320 || maybe_get_arm_condition_code (op) == ARM_GT
321 || maybe_get_arm_condition_code (op) == ARM_EQ
322 || maybe_get_arm_condition_code (op) == ARM_VS
323 || maybe_get_arm_condition_code (op) == ARM_LT
324 || maybe_get_arm_condition_code (op) == ARM_LE
325 || maybe_get_arm_condition_code (op) == ARM_NE
326 || maybe_get_arm_condition_code (op) == ARM_VC")))
328 (define_special_predicate "arm_cond_move_operator"
329 (if_then_else (match_test "arm_restrict_it")
330 (and (match_test "TARGET_FPU_ARMV8")
331 (match_operand 0 "arm_vsel_comparison_operator"))
332 (match_operand 0 "expandable_comparison_operator")))
334 (define_special_predicate "noov_comparison_operator"
335 (match_code "lt,ge,eq,ne"))
337 (define_special_predicate "minmax_operator"
338 (and (match_code "smin,smax,umin,umax")
339 (match_test "mode == GET_MODE (op)")))
341 (define_special_predicate "cc_register"
342 (and (match_code "reg")
343 (and (match_test "REGNO (op) == CC_REGNUM")
344 (ior (match_test "mode == GET_MODE (op)")
345 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
347 (define_special_predicate "dominant_cc_register"
350 if (mode == VOIDmode)
352 mode = GET_MODE (op);
354 if (GET_MODE_CLASS (mode) != MODE_CC)
358 return (cc_register (op, mode)
359 && (mode == CC_DNEmode
360 || mode == CC_DEQmode
361 || mode == CC_DLEmode
362 || mode == CC_DLTmode
363 || mode == CC_DGEmode
364 || mode == CC_DGTmode
365 || mode == CC_DLEUmode
366 || mode == CC_DLTUmode
367 || mode == CC_DGEUmode
368 || mode == CC_DGTUmode));
371 (define_special_predicate "arm_extendqisi_mem_op"
372 (and (match_operand 0 "memory_operand")
373 (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
377 : memory_address_p (QImode, XEXP (op, 0))")))
379 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
380 (ior (match_operand 0 "arm_extendqisi_mem_op")
381 (match_operand 0 "s_register_operand")))
383 (define_predicate "power_of_two_operand"
384 (match_code "const_int")
386 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
388 return value != 0 && (value & (value - 1)) == 0;
391 (define_predicate "nonimmediate_di_operand"
392 (match_code "reg,subreg,mem")
394 if (s_register_operand (op, mode))
397 if (GET_CODE (op) == SUBREG)
398 op = SUBREG_REG (op);
400 return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
403 (define_predicate "di_operand"
404 (ior (match_code "const_int,const_double")
405 (and (match_code "reg,subreg,mem")
406 (match_operand 0 "nonimmediate_di_operand"))))
408 (define_predicate "nonimmediate_soft_df_operand"
409 (match_code "reg,subreg,mem")
411 if (s_register_operand (op, mode))
414 if (GET_CODE (op) == SUBREG)
415 op = SUBREG_REG (op);
417 return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
420 (define_predicate "soft_df_operand"
421 (ior (match_code "const_double")
422 (and (match_code "reg,subreg,mem")
423 (match_operand 0 "nonimmediate_soft_df_operand"))))
425 (define_special_predicate "load_multiple_operation"
426 (match_code "parallel")
428 return ldm_stm_operation_p (op, /*load=*/true, SImode,
429 /*consecutive=*/false,
430 /*return_pc=*/false);
433 (define_special_predicate "store_multiple_operation"
434 (match_code "parallel")
436 return ldm_stm_operation_p (op, /*load=*/false, SImode,
437 /*consecutive=*/false,
438 /*return_pc=*/false);
441 (define_special_predicate "pop_multiple_return"
442 (match_code "parallel")
444 return ldm_stm_operation_p (op, /*load=*/true, SImode,
445 /*consecutive=*/false,
449 (define_special_predicate "pop_multiple_fp"
450 (match_code "parallel")
452 return ldm_stm_operation_p (op, /*load=*/true, DFmode,
453 /*consecutive=*/true,
454 /*return_pc=*/false);
457 (define_special_predicate "multi_register_push"
458 (match_code "parallel")
460 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
461 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
462 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
468 (define_predicate "push_mult_memory_operand"
471 /* ??? Given how PUSH_MULT is generated in the prologues, is there
472 any point in testing for thumb1 specially? All of the variants
473 use the same form. */
476 /* ??? No attempt is made to represent STMIA, or validate that
477 the stack adjustment matches the register count. This is
478 true of the ARM/Thumb2 path as well. */
479 rtx x = XEXP (op, 0);
480 if (GET_CODE (x) != PRE_MODIFY)
482 if (XEXP (x, 0) != stack_pointer_rtx)
485 if (GET_CODE (x) != PLUS)
487 if (XEXP (x, 0) != stack_pointer_rtx)
489 return CONST_INT_P (XEXP (x, 1));
492 /* ARM and Thumb2 handle pre-modify in their legitimate_address. */
493 return memory_operand (op, mode);
496 ;;-------------------------------------------------------------------------
501 (define_predicate "thumb1_cmp_operand"
502 (ior (and (match_code "reg,subreg")
503 (match_operand 0 "s_register_operand"))
504 (and (match_code "const_int")
505 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
507 (define_predicate "thumb1_cmpneg_operand"
508 (and (match_code "const_int")
509 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
511 ;; Return TRUE if a result can be stored in OP without clobbering the
512 ;; condition code register. Prior to reload we only accept a
513 ;; register. After reload we have to be able to handle memory as
514 ;; well, since a pseudo may not get a hard reg and reload cannot
515 ;; handle output-reloads on jump insns.
517 ;; We could possibly handle mem before reload as well, but that might
518 ;; complicate things with the need to handle increment
520 (define_predicate "thumb_cbrch_target_operand"
521 (and (match_code "reg,subreg,mem")
522 (ior (match_operand 0 "s_register_operand")
523 (and (match_test "reload_in_progress || reload_completed")
524 (match_operand 0 "memory_operand")))))
526 ;;-------------------------------------------------------------------------
531 (define_predicate "imm_or_reg_operand"
532 (ior (match_operand 0 "immediate_operand")
533 (match_operand 0 "register_operand")))
537 (define_predicate "const_multiple_of_8_operand"
538 (match_code "const_int")
540 unsigned HOST_WIDE_INT val = INTVAL (op);
541 return (val & 7) == 0;
544 (define_predicate "imm_for_neon_mov_operand"
545 (match_code "const_vector,const_int")
547 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
550 (define_predicate "imm_for_neon_lshift_operand"
551 (match_code "const_vector")
553 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
556 (define_predicate "imm_for_neon_rshift_operand"
557 (match_code "const_vector")
559 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
562 (define_predicate "imm_lshift_or_reg_neon"
563 (ior (match_operand 0 "s_register_operand")
564 (match_operand 0 "imm_for_neon_lshift_operand")))
566 (define_predicate "imm_rshift_or_reg_neon"
567 (ior (match_operand 0 "s_register_operand")
568 (match_operand 0 "imm_for_neon_rshift_operand")))
570 ;; Predicates for named expanders that overlap multiple ISAs.
572 (define_predicate "cmpdi_operand"
573 (and (match_test "TARGET_32BIT")
574 (match_operand 0 "arm_di_operand")))
576 ;; True if the operand is memory reference suitable for a ldrex/strex.
577 (define_predicate "arm_sync_memory_operand"
578 (and (match_operand 0 "memory_operand")
579 (match_code "reg" "0")))
581 ;; Predicates for parallel expanders based on mode.
582 (define_special_predicate "vect_par_constant_high"
583 (match_code "parallel")
585 HOST_WIDE_INT count = XVECLEN (op, 0);
587 int base = GET_MODE_NUNITS (mode);
590 || (count != base/2))
593 if (!VECTOR_MODE_P (mode))
596 for (i = 0; i < count; i++)
598 rtx elt = XVECEXP (op, 0, i);
601 if (!CONST_INT_P (elt))
605 if (val != (base/2) + i)
611 (define_special_predicate "vect_par_constant_low"
612 (match_code "parallel")
614 HOST_WIDE_INT count = XVECLEN (op, 0);
616 int base = GET_MODE_NUNITS (mode);
619 || (count != base/2))
622 if (!VECTOR_MODE_P (mode))
625 for (i = 0; i < count; i++)
627 rtx elt = XVECEXP (op, 0, i);
630 if (!CONST_INT_P (elt))
640 (define_predicate "const_double_vcvt_power_of_two_reciprocal"
641 (and (match_code "const_double")
642 (match_test "TARGET_32BIT && TARGET_VFP
643 && vfp3_const_double_for_fract_bits (op)")))
645 (define_predicate "neon_struct_operand"
646 (and (match_code "mem")
647 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
649 (define_predicate "neon_struct_or_register_operand"
650 (ior (match_operand 0 "neon_struct_operand")
651 (match_operand 0 "s_register_operand")))
653 (define_special_predicate "add_operator"
656 (define_predicate "mem_noofs_operand"
657 (and (match_code "mem")
658 (match_code "reg" "0")))
660 (define_predicate "call_insn_operand"
661 (ior (match_code "symbol_ref")
662 (match_operand 0 "s_register_operand")))