1 ;; ARM Cortex-M4 pipeline description
2 ;; Copyright (C) 2010-2013 Free Software Foundation, Inc.
3 ;; Contributed by CodeSourcery.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_automaton "cortex_m4")
23 ;; We model the pipelining of LDR instructions by using two artificial units.
25 (define_cpu_unit "cortex_m4_a" "cortex_m4")
27 (define_cpu_unit "cortex_m4_b" "cortex_m4")
29 (define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b")
31 ;; ALU and multiply is one cycle.
32 (define_insn_reservation "cortex_m4_alu" 1
33 (and (eq_attr "tune" "cortexm4")
34 (ior (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,\
35 arlo_shift,arlo_shift_reg,\
36 mov_imm,mov_reg,mov_shift,mov_shift_reg,\
37 mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")
38 (ior (eq_attr "mul32" "yes")
39 (eq_attr "mul64" "yes"))))
42 ;; Byte, half-word and word load is two cycles.
43 (define_insn_reservation "cortex_m4_load1" 2
44 (and (eq_attr "tune" "cortexm4")
45 (eq_attr "type" "load_byte,load1"))
46 "cortex_m4_a, cortex_m4_b")
48 ;; str rx, [ry, #imm] is always one cycle.
49 (define_insn_reservation "cortex_m4_store1_1" 1
50 (and (and (eq_attr "tune" "cortexm4")
51 (eq_attr "type" "store1"))
52 (match_test "arm_address_offset_is_imm (insn)"))
55 ;; Other byte, half-word and word load is two cycles.
56 (define_insn_reservation "cortex_m4_store1_2" 2
57 (and (and (eq_attr "tune" "cortexm4")
58 (eq_attr "type" "store1"))
59 (not (match_test "arm_address_offset_is_imm (insn)")))
62 (define_insn_reservation "cortex_m4_load2" 3
63 (and (eq_attr "tune" "cortexm4")
64 (eq_attr "type" "load2"))
67 (define_insn_reservation "cortex_m4_store2" 3
68 (and (eq_attr "tune" "cortexm4")
69 (eq_attr "type" "store2"))
72 (define_insn_reservation "cortex_m4_load3" 4
73 (and (eq_attr "tune" "cortexm4")
74 (eq_attr "type" "load3"))
77 (define_insn_reservation "cortex_m4_store3" 4
78 (and (eq_attr "tune" "cortexm4")
79 (eq_attr "type" "store3"))
82 (define_insn_reservation "cortex_m4_load4" 5
83 (and (eq_attr "tune" "cortexm4")
84 (eq_attr "type" "load4"))
87 (define_insn_reservation "cortex_m4_store4" 5
88 (and (eq_attr "tune" "cortexm4")
89 (eq_attr "type" "store4"))
92 ;; If the address of load or store depends on the result of the preceding
93 ;; instruction, the latency is increased by one.
95 (define_bypass 2 "cortex_m4_alu"
97 "arm_early_load_addr_dep")
99 (define_bypass 2 "cortex_m4_alu"
100 "cortex_m4_store1_1,cortex_m4_store1_2"
101 "arm_early_store_addr_dep")
103 (define_insn_reservation "cortex_m4_branch" 3
104 (and (eq_attr "tune" "cortexm4")
105 (eq_attr "type" "branch"))
108 (define_insn_reservation "cortex_m4_call" 3
109 (and (eq_attr "tune" "cortexm4")
110 (eq_attr "type" "call"))
113 (define_insn_reservation "cortex_m4_block" 1
114 (and (eq_attr "tune" "cortexm4")
115 (eq_attr "type" "block"))