1 ;; ARM Cortex-A8 scheduling description.
2 ;; Copyright (C) 2007-2013 Free Software Foundation, Inc.
3 ;; Contributed by CodeSourcery.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_automaton "cortex_a8")
23 ;; Only one load/store instruction can be issued per cycle
24 ;; (although reservation of this unit is only required for single
25 ;; loads and stores -- see below).
26 (define_cpu_unit "cortex_a8_issue_ls" "cortex_a8")
28 ;; Only one branch instruction can be issued per cycle.
29 (define_cpu_unit "cortex_a8_issue_branch" "cortex_a8")
31 ;; The two ALU pipelines.
32 (define_cpu_unit "cortex_a8_alu0" "cortex_a8")
33 (define_cpu_unit "cortex_a8_alu1" "cortex_a8")
35 ;; The usual flow of an instruction through the pipelines.
36 (define_reservation "cortex_a8_default"
37 "cortex_a8_alu0|cortex_a8_alu1")
39 ;; The flow of a branch instruction through the pipelines.
40 (define_reservation "cortex_a8_branch"
41 "(cortex_a8_alu0+cortex_a8_issue_branch)|\
42 (cortex_a8_alu1+cortex_a8_issue_branch)")
44 ;; The flow of a load or store instruction through the pipeline in
45 ;; the case where that instruction consists of only one micro-op...
46 (define_reservation "cortex_a8_load_store_1"
47 "(cortex_a8_alu0+cortex_a8_issue_ls)|\
48 (cortex_a8_alu1+cortex_a8_issue_ls)")
50 ;; ...and in the case of two micro-ops. Dual issue is altogether forbidden
51 ;; during the issue cycle of the first micro-op. (Instead of modelling
52 ;; a separate issue unit, we instead reserve alu0 and alu1 to
53 ;; prevent any other instructions from being issued upon that first cycle.)
54 ;; Even though the load/store pipeline is usually available in either
55 ;; ALU pipe, multi-cycle instructions always issue in pipeline 0.
56 (define_reservation "cortex_a8_load_store_2"
57 "cortex_a8_alu0+cortex_a8_alu1+cortex_a8_issue_ls,\
58 cortex_a8_alu0+cortex_a8_issue_ls")
60 ;; The flow of a single-cycle multiplication.
61 (define_reservation "cortex_a8_multiply"
64 ;; The flow of a multiplication instruction that gets decomposed into
65 ;; two micro-ops. The two micro-ops will be issued to pipeline 0 on
66 ;; successive cycles. Dual issue cannot happen at the same time as the
67 ;; first of the micro-ops.
68 (define_reservation "cortex_a8_multiply_2"
69 "cortex_a8_alu0+cortex_a8_alu1,\
72 ;; Similarly, the flow of a multiplication instruction that gets
73 ;; decomposed into three micro-ops. Dual issue cannot occur except on
74 ;; the cycle upon which the third micro-op is issued.
75 (define_reservation "cortex_a8_multiply_3"
76 "cortex_a8_alu0+cortex_a8_alu1,\
77 cortex_a8_alu0+cortex_a8_alu1,\
80 ;; The model given here assumes that all instructions are unconditional.
82 ;; Data processing instructions, but not move instructions.
84 ;; We include CLZ with these since it has the same execution pattern
85 ;; (source read in E2 and destination available at the end of that cycle).
86 (define_insn_reservation "cortex_a8_alu" 2
87 (and (eq_attr "tune" "cortexa8")
88 (ior (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
89 (eq_attr "neon_type" "none"))
90 (eq_attr "type" "clz")))
93 (define_insn_reservation "cortex_a8_alu_shift" 2
94 (and (eq_attr "tune" "cortexa8")
95 (eq_attr "type" "extend,arlo_shift"))
98 (define_insn_reservation "cortex_a8_alu_shift_reg" 2
99 (and (eq_attr "tune" "cortexa8")
100 (eq_attr "type" "arlo_shift_reg"))
103 ;; Move instructions.
105 (define_insn_reservation "cortex_a8_mov" 1
106 (and (eq_attr "tune" "cortexa8")
107 (eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\
108 mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
111 ;; Exceptions to the default latencies for data processing instructions.
113 ;; A move followed by an ALU instruction with no early dep.
114 ;; (Such a pair can be issued in parallel, hence latency zero.)
115 (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu")
116 (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu_shift"
117 "arm_no_early_alu_shift_dep")
118 (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu_shift_reg"
119 "arm_no_early_alu_shift_value_dep")
121 ;; An ALU instruction followed by an ALU instruction with no early dep.
122 (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg"
124 (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg"
125 "cortex_a8_alu_shift"
126 "arm_no_early_alu_shift_dep")
127 (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg"
128 "cortex_a8_alu_shift_reg"
129 "arm_no_early_alu_shift_value_dep")
131 ;; Multiplication instructions. These are categorized according to their
132 ;; reservation behavior and the need below to distinguish certain
133 ;; varieties for bypasses. Results are available at the E5 stage
134 ;; (but some of these are multi-cycle instructions which explains the
137 (define_insn_reservation "cortex_a8_mul" 6
138 (and (eq_attr "tune" "cortexa8")
139 (eq_attr "type" "mul,smulxy,smmul"))
140 "cortex_a8_multiply_2")
142 (define_insn_reservation "cortex_a8_mla" 6
143 (and (eq_attr "tune" "cortexa8")
144 (eq_attr "type" "mla,smlaxy,smlawy,smmla,smlad,smlsd"))
145 "cortex_a8_multiply_2")
147 (define_insn_reservation "cortex_a8_mull" 7
148 (and (eq_attr "tune" "cortexa8")
149 (eq_attr "type" "smull,umull,smlal,umlal,umaal,smlalxy"))
150 "cortex_a8_multiply_3")
152 (define_insn_reservation "cortex_a8_smulwy" 5
153 (and (eq_attr "tune" "cortexa8")
154 (eq_attr "type" "smulwy,smuad,smusd"))
155 "cortex_a8_multiply")
157 ;; smlald and smlsld are multiply-accumulate instructions but do not
158 ;; received bypassed data from other multiplication results; thus, they
159 ;; cannot go in cortex_a8_mla above. (See below for bypass details.)
160 (define_insn_reservation "cortex_a8_smlald" 6
161 (and (eq_attr "tune" "cortexa8")
162 (eq_attr "type" "smlald,smlsld"))
163 "cortex_a8_multiply_2")
165 ;; A multiply with a single-register result or an MLA, followed by an
166 ;; MLA with an accumulator dependency, has its result forwarded so two
167 ;; such instructions can issue back-to-back.
168 (define_bypass 1 "cortex_a8_mul,cortex_a8_mla,cortex_a8_smulwy"
170 "arm_mac_accumulator_is_mul_result")
172 ;; A multiply followed by an ALU instruction needing the multiply
173 ;; result only at E2 has lower latency than one needing it at E1.
174 (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\
175 cortex_a8_smulwy,cortex_a8_smlald"
177 (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\
178 cortex_a8_smulwy,cortex_a8_smlald"
179 "cortex_a8_alu_shift"
180 "arm_no_early_alu_shift_dep")
181 (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\
182 cortex_a8_smulwy,cortex_a8_smlald"
183 "cortex_a8_alu_shift_reg"
184 "arm_no_early_alu_shift_value_dep")
186 ;; Load instructions.
187 ;; The presence of any register writeback is ignored here.
189 ;; A load result has latency 3 unless the dependent instruction has
190 ;; no early dep, in which case it is only latency two.
191 ;; We assume 64-bit alignment for doubleword loads.
192 (define_insn_reservation "cortex_a8_load1_2" 3
193 (and (eq_attr "tune" "cortexa8")
194 (eq_attr "type" "load1,load2,load_byte"))
195 "cortex_a8_load_store_1")
197 (define_bypass 2 "cortex_a8_load1_2"
199 (define_bypass 2 "cortex_a8_load1_2"
200 "cortex_a8_alu_shift"
201 "arm_no_early_alu_shift_dep")
202 (define_bypass 2 "cortex_a8_load1_2"
203 "cortex_a8_alu_shift_reg"
204 "arm_no_early_alu_shift_value_dep")
206 ;; We do not currently model the fact that loads with scaled register
207 ;; offsets that are not LSL #2 have an extra cycle latency (they issue
208 ;; as two micro-ops).
210 ;; A load multiple of three registers is usually issued as two micro-ops.
211 ;; The first register will be available at E3 of the first iteration,
212 ;; the second at E3 of the second iteration, and the third at E4 of
213 ;; the second iteration. A load multiple of four registers is usually
214 ;; issued as two micro-ops.
215 (define_insn_reservation "cortex_a8_load3_4" 5
216 (and (eq_attr "tune" "cortexa8")
217 (eq_attr "type" "load3,load4"))
218 "cortex_a8_load_store_2")
220 (define_bypass 4 "cortex_a8_load3_4"
222 (define_bypass 4 "cortex_a8_load3_4"
223 "cortex_a8_alu_shift"
224 "arm_no_early_alu_shift_dep")
225 (define_bypass 4 "cortex_a8_load3_4"
226 "cortex_a8_alu_shift_reg"
227 "arm_no_early_alu_shift_value_dep")
229 ;; Store instructions.
230 ;; Writeback is again ignored.
232 (define_insn_reservation "cortex_a8_store1_2" 0
233 (and (eq_attr "tune" "cortexa8")
234 (eq_attr "type" "store1,store2"))
235 "cortex_a8_load_store_1")
237 (define_insn_reservation "cortex_a8_store3_4" 0
238 (and (eq_attr "tune" "cortexa8")
239 (eq_attr "type" "store3,store4"))
240 "cortex_a8_load_store_2")
242 ;; An ALU instruction acting as a producer for a store instruction
243 ;; that only uses the result as the value to be stored (as opposed to
244 ;; using it to calculate the address) has latency zero; the store
245 ;; reads the value to be stored at the start of E3 and the ALU insn
246 ;; writes it at the end of E2. Move instructions actually produce the
247 ;; result at the end of E1, but since we don't have delay slots, the
248 ;; scheduling behavior will be the same.
249 (define_bypass 0 "cortex_a8_alu,cortex_a8_alu_shift,\
250 cortex_a8_alu_shift_reg,cortex_a8_mov"
251 "cortex_a8_store1_2,cortex_a8_store3_4"
252 "arm_no_early_store_addr_dep")
254 ;; Branch instructions
256 (define_insn_reservation "cortex_a8_branch" 0
257 (and (eq_attr "tune" "cortexa8")
258 (eq_attr "type" "branch"))
261 ;; Call latencies are not predictable. A semi-arbitrary very large
262 ;; number is used as "positive infinity" so that everything should be
263 ;; finished by the time of return.
264 (define_insn_reservation "cortex_a8_call" 32
265 (and (eq_attr "tune" "cortexa8")
266 (eq_attr "type" "call"))
267 "cortex_a8_issue_branch")
269 ;; NEON (including VFP) instructions.
271 (include "cortex-a8-neon.md")