1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
96 #ifndef ACCUMULATE_OUTGOING_ARGS
97 #define ACCUMULATE_OUTGOING_ARGS 0
100 /* Supply a default definition for PUSH_ARGS. */
103 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
109 /* It is not safe to use ordinary gen_lowpart in combine.
110 Use gen_lowpart_for_combine instead. See comments there. */
111 #define gen_lowpart dont_use_gen_lowpart_you_dummy
113 /* Number of attempts to combine instructions in this function. */
115 static int combine_attempts
;
117 /* Number of attempts that got as far as substitution in this function. */
119 static int combine_merges
;
121 /* Number of instructions combined with added SETs in this function. */
123 static int combine_extras
;
125 /* Number of instructions combined in this function. */
127 static int combine_successes
;
129 /* Totals over entire compilation. */
131 static int total_attempts
, total_merges
, total_extras
, total_successes
;
134 /* Vector mapping INSN_UIDs to cuids.
135 The cuids are like uids but increase monotonically always.
136 Combine always uses cuids so that it can compare them.
137 But actually renumbering the uids, which we used to do,
138 proves to be a bad idea because it makes it hard to compare
139 the dumps produced by earlier passes with those from later passes. */
141 static int *uid_cuid
;
142 static int max_uid_cuid
;
144 /* Get the cuid of an insn. */
146 #define INSN_CUID(INSN) \
147 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
149 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
150 BITS_PER_WORD would invoke undefined behavior. Work around it. */
152 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
153 (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
155 /* Maximum register number, which is the size of the tables below. */
157 static unsigned int combine_max_regno
;
159 /* Record last point of death of (hard or pseudo) register n. */
161 static rtx
*reg_last_death
;
163 /* Record last point of modification of (hard or pseudo) register n. */
165 static rtx
*reg_last_set
;
167 /* Record the cuid of the last insn that invalidated memory
168 (anything that writes memory, and subroutine calls, but not pushes). */
170 static int mem_last_set
;
172 /* Record the cuid of the last CALL_INSN
173 so we can tell whether a potential combination crosses any calls. */
175 static int last_call_cuid
;
177 /* When `subst' is called, this is the insn that is being modified
178 (by combining in a previous insn). The PATTERN of this insn
179 is still the old pattern partially modified and it should not be
180 looked at, but this may be used to examine the successors of the insn
181 to judge whether a simplification is valid. */
183 static rtx subst_insn
;
185 /* This is an insn that belongs before subst_insn, but is not currently
186 on the insn chain. */
188 static rtx subst_prev_insn
;
190 /* This is the lowest CUID that `subst' is currently dealing with.
191 get_last_value will not return a value if the register was set at or
192 after this CUID. If not for this mechanism, we could get confused if
193 I2 or I1 in try_combine were an insn that used the old value of a register
194 to obtain a new value. In that case, we might erroneously get the
195 new value of the register when we wanted the old one. */
197 static int subst_low_cuid
;
199 /* This contains any hard registers that are used in newpat; reg_dead_at_p
200 must consider all these registers to be always live. */
202 static HARD_REG_SET newpat_used_regs
;
204 /* This is an insn to which a LOG_LINKS entry has been added. If this
205 insn is the earlier than I2 or I3, combine should rescan starting at
208 static rtx added_links_insn
;
210 /* Basic block number of the block in which we are performing combines. */
211 static int this_basic_block
;
213 /* A bitmap indicating which blocks had registers go dead at entry.
214 After combine, we'll need to re-do global life analysis with
215 those blocks as starting points. */
216 static sbitmap refresh_blocks
;
217 static int need_refresh
;
219 /* The next group of arrays allows the recording of the last value assigned
220 to (hard or pseudo) register n. We use this information to see if a
221 operation being processed is redundant given a prior operation performed
222 on the register. For example, an `and' with a constant is redundant if
223 all the zero bits are already known to be turned off.
225 We use an approach similar to that used by cse, but change it in the
228 (1) We do not want to reinitialize at each label.
229 (2) It is useful, but not critical, to know the actual value assigned
230 to a register. Often just its form is helpful.
232 Therefore, we maintain the following arrays:
234 reg_last_set_value the last value assigned
235 reg_last_set_label records the value of label_tick when the
236 register was assigned
237 reg_last_set_table_tick records the value of label_tick when a
238 value using the register is assigned
239 reg_last_set_invalid set to non-zero when it is not valid
240 to use the value of this register in some
243 To understand the usage of these tables, it is important to understand
244 the distinction between the value in reg_last_set_value being valid
245 and the register being validly contained in some other expression in the
248 Entry I in reg_last_set_value is valid if it is non-zero, and either
249 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
251 Register I may validly appear in any expression returned for the value
252 of another register if reg_n_sets[i] is 1. It may also appear in the
253 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
254 reg_last_set_invalid[j] is zero.
256 If an expression is found in the table containing a register which may
257 not validly appear in an expression, the register is replaced by
258 something that won't match, (clobber (const_int 0)).
260 reg_last_set_invalid[i] is set non-zero when register I is being assigned
261 to and reg_last_set_table_tick[i] == label_tick. */
263 /* Record last value assigned to (hard or pseudo) register n. */
265 static rtx
*reg_last_set_value
;
267 /* Record the value of label_tick when the value for register n is placed in
268 reg_last_set_value[n]. */
270 static int *reg_last_set_label
;
272 /* Record the value of label_tick when an expression involving register n
273 is placed in reg_last_set_value. */
275 static int *reg_last_set_table_tick
;
277 /* Set non-zero if references to register n in expressions should not be
280 static char *reg_last_set_invalid
;
282 /* Incremented for each label. */
284 static int label_tick
;
286 /* Some registers that are set more than once and used in more than one
287 basic block are nevertheless always set in similar ways. For example,
288 a QImode register may be loaded from memory in two places on a machine
289 where byte loads zero extend.
291 We record in the following array what we know about the nonzero
292 bits of a register, specifically which bits are known to be zero.
294 If an entry is zero, it means that we don't know anything special. */
296 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
298 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
299 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
301 static enum machine_mode nonzero_bits_mode
;
303 /* Nonzero if we know that a register has some leading bits that are always
304 equal to the sign bit. */
306 static unsigned char *reg_sign_bit_copies
;
308 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
309 It is zero while computing them and after combine has completed. This
310 former test prevents propagating values based on previously set values,
311 which can be incorrect if a variable is modified in a loop. */
313 static int nonzero_sign_valid
;
315 /* These arrays are maintained in parallel with reg_last_set_value
316 and are used to store the mode in which the register was last set,
317 the bits that were known to be zero when it was last set, and the
318 number of sign bits copies it was known to have when it was last set. */
320 static enum machine_mode
*reg_last_set_mode
;
321 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
322 static char *reg_last_set_sign_bit_copies
;
324 /* Record one modification to rtl structure
325 to be undone by storing old_contents into *where.
326 is_int is 1 if the contents are an int. */
332 union {rtx r
; unsigned int i
;} old_contents
;
333 union {rtx
*r
; unsigned int *i
;} where
;
336 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
337 num_undo says how many are currently recorded.
339 other_insn is nonzero if we have modified some other insn in the process
340 of working on subst_insn. It must be verified too.
342 previous_undos is the value of undobuf.undos when we started processing
343 this substitution. This will prevent gen_rtx_combine from re-used a piece
344 from the previous expression. Doing so can produce circular rtl
351 struct undo
*previous_undos
;
355 static struct undobuf undobuf
;
357 /* Number of times the pseudo being substituted for
358 was found and replaced. */
360 static int n_occurrences
;
362 static void do_SUBST
PARAMS ((rtx
*, rtx
));
363 static void do_SUBST_INT
PARAMS ((unsigned int *,
365 static void init_reg_last_arrays
PARAMS ((void));
366 static void setup_incoming_promotions
PARAMS ((void));
367 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
368 static int cant_combine_insn_p
PARAMS ((rtx
));
369 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
370 static int sets_function_arg_p
PARAMS ((rtx
));
371 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
372 static int contains_muldiv
PARAMS ((rtx
));
373 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
374 static void undo_all
PARAMS ((void));
375 static void undo_commit
PARAMS ((void));
376 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
377 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
378 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
379 static rtx simplify_if_then_else
PARAMS ((rtx
));
380 static rtx simplify_set
PARAMS ((rtx
));
381 static rtx simplify_logical
PARAMS ((rtx
, int));
382 static rtx expand_compound_operation
PARAMS ((rtx
));
383 static rtx expand_field_assignment
PARAMS ((rtx
));
384 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
385 rtx
, unsigned HOST_WIDE_INT
, int,
387 static rtx extract_left_shift
PARAMS ((rtx
, int));
388 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
389 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
390 unsigned HOST_WIDE_INT
*));
391 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
392 unsigned HOST_WIDE_INT
, rtx
, int));
393 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
394 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
395 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
396 static rtx make_field_assignment
PARAMS ((rtx
));
397 static rtx apply_distributive_law
PARAMS ((rtx
));
398 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
399 unsigned HOST_WIDE_INT
));
400 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
401 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
402 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
403 enum rtx_code
, HOST_WIDE_INT
,
404 enum machine_mode
, int *));
405 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
407 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
408 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
409 static rtx gen_rtx_combine
PARAMS ((enum rtx_code code
, enum machine_mode mode
,
411 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
413 static rtx gen_unary
PARAMS ((enum rtx_code
, enum machine_mode
,
414 enum machine_mode
, rtx
));
415 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
416 static void update_table_tick
PARAMS ((rtx
));
417 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
418 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
419 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
420 static void record_dead_and_set_regs
PARAMS ((rtx
));
421 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
422 static rtx get_last_value
PARAMS ((rtx
));
423 static int use_crosses_set_p
PARAMS ((rtx
, int));
424 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
425 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
426 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
427 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
428 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
429 static void distribute_links
PARAMS ((rtx
));
430 static void mark_used_regs_combine
PARAMS ((rtx
));
431 static int insn_cuid
PARAMS ((rtx
));
432 static void record_promoted_value
PARAMS ((rtx
, rtx
));
433 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
434 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
436 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
437 insn. The substitution can be undone by undo_all. If INTO is already
438 set to NEWVAL, do not record this change. Because computing NEWVAL might
439 also call SUBST, we have to compute it before we put anything into
443 do_SUBST (into
, newval
)
449 if (oldval
== newval
)
453 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
455 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
459 buf
->old_contents
.r
= oldval
;
462 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
465 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
467 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
468 for the value of a HOST_WIDE_INT value (including CONST_INT) is
472 do_SUBST_INT (into
, newval
)
473 unsigned int *into
, newval
;
476 unsigned int oldval
= *into
;
478 if (oldval
== newval
)
482 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
484 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
488 buf
->old_contents
.i
= oldval
;
491 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
494 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
496 /* Main entry point for combiner. F is the first insn of the function.
497 NREGS is the first unused pseudo-reg number.
499 Return non-zero if the combiner has turned an indirect jump
500 instruction into a direct jump. */
502 combine_instructions (f
, nregs
)
506 register rtx insn
, next
;
511 register rtx links
, nextlinks
;
513 int new_direct_jump_p
= 0;
515 combine_attempts
= 0;
518 combine_successes
= 0;
520 combine_max_regno
= nregs
;
522 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
523 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
525 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
527 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
528 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
530 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
531 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
532 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
534 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
535 reg_last_set_nonzero_bits
536 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
537 reg_last_set_sign_bit_copies
538 = (char *) xmalloc (nregs
* sizeof (char));
540 init_reg_last_arrays ();
542 init_recog_no_volatile ();
544 /* Compute maximum uid value so uid_cuid can be allocated. */
546 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
547 if (INSN_UID (insn
) > i
)
550 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
553 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
555 /* Don't use reg_nonzero_bits when computing it. This can cause problems
556 when, for example, we have j <<= 1 in a loop. */
558 nonzero_sign_valid
= 0;
560 /* Compute the mapping from uids to cuids.
561 Cuids are numbers assigned to insns, like uids,
562 except that cuids increase monotonically through the code.
564 Scan all SETs and see if we can deduce anything about what
565 bits are known to be zero for some registers and how many copies
566 of the sign bit are known to exist for those registers.
568 Also set any known values so that we can use it while searching
569 for what bits are known to be set. */
573 /* We need to initialize it here, because record_dead_and_set_regs may call
575 subst_prev_insn
= NULL_RTX
;
577 setup_incoming_promotions ();
579 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
580 sbitmap_zero (refresh_blocks
);
583 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
585 uid_cuid
[INSN_UID (insn
)] = ++i
;
591 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
593 record_dead_and_set_regs (insn
);
596 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
597 if (REG_NOTE_KIND (links
) == REG_INC
)
598 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
603 if (GET_CODE (insn
) == CODE_LABEL
)
607 nonzero_sign_valid
= 1;
609 /* Now scan all the insns in forward order. */
611 this_basic_block
= -1;
615 init_reg_last_arrays ();
616 setup_incoming_promotions ();
618 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
622 /* If INSN starts a new basic block, update our basic block number. */
623 if (this_basic_block
+ 1 < n_basic_blocks
624 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
627 if (GET_CODE (insn
) == CODE_LABEL
)
630 else if (INSN_P (insn
))
632 /* See if we know about function return values before this
633 insn based upon SUBREG flags. */
634 check_promoted_subreg (insn
, PATTERN (insn
));
636 /* Try this insn with each insn it links back to. */
638 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
639 if ((next
= try_combine (insn
, XEXP (links
, 0),
640 NULL_RTX
, &new_direct_jump_p
)) != 0)
643 /* Try each sequence of three linked insns ending with this one. */
645 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
647 rtx link
= XEXP (links
, 0);
649 /* If the linked insn has been replaced by a note, then there
650 is no point in persuing this chain any further. */
651 if (GET_CODE (link
) == NOTE
)
654 for (nextlinks
= LOG_LINKS (link
);
656 nextlinks
= XEXP (nextlinks
, 1))
657 if ((next
= try_combine (insn
, XEXP (links
, 0),
659 &new_direct_jump_p
)) != 0)
664 /* Try to combine a jump insn that uses CC0
665 with a preceding insn that sets CC0, and maybe with its
666 logical predecessor as well.
667 This is how we make decrement-and-branch insns.
668 We need this special code because data flow connections
669 via CC0 do not get entered in LOG_LINKS. */
671 if (GET_CODE (insn
) == JUMP_INSN
672 && (prev
= prev_nonnote_insn (insn
)) != 0
673 && GET_CODE (prev
) == INSN
674 && sets_cc0_p (PATTERN (prev
)))
676 if ((next
= try_combine (insn
, prev
,
677 NULL_RTX
, &new_direct_jump_p
)) != 0)
680 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
681 nextlinks
= XEXP (nextlinks
, 1))
682 if ((next
= try_combine (insn
, prev
,
684 &new_direct_jump_p
)) != 0)
688 /* Do the same for an insn that explicitly references CC0. */
689 if (GET_CODE (insn
) == INSN
690 && (prev
= prev_nonnote_insn (insn
)) != 0
691 && GET_CODE (prev
) == INSN
692 && sets_cc0_p (PATTERN (prev
))
693 && GET_CODE (PATTERN (insn
)) == SET
694 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
696 if ((next
= try_combine (insn
, prev
,
697 NULL_RTX
, &new_direct_jump_p
)) != 0)
700 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
701 nextlinks
= XEXP (nextlinks
, 1))
702 if ((next
= try_combine (insn
, prev
,
704 &new_direct_jump_p
)) != 0)
708 /* Finally, see if any of the insns that this insn links to
709 explicitly references CC0. If so, try this insn, that insn,
710 and its predecessor if it sets CC0. */
711 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
712 if (GET_CODE (XEXP (links
, 0)) == INSN
713 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
714 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
715 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
716 && GET_CODE (prev
) == INSN
717 && sets_cc0_p (PATTERN (prev
))
718 && (next
= try_combine (insn
, XEXP (links
, 0),
719 prev
, &new_direct_jump_p
)) != 0)
723 /* Try combining an insn with two different insns whose results it
725 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
726 for (nextlinks
= XEXP (links
, 1); nextlinks
;
727 nextlinks
= XEXP (nextlinks
, 1))
728 if ((next
= try_combine (insn
, XEXP (links
, 0),
730 &new_direct_jump_p
)) != 0)
733 if (GET_CODE (insn
) != NOTE
)
734 record_dead_and_set_regs (insn
);
743 compute_bb_for_insn (get_max_uid ());
744 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
749 sbitmap_free (refresh_blocks
);
750 free (reg_nonzero_bits
);
751 free (reg_sign_bit_copies
);
752 free (reg_last_death
);
754 free (reg_last_set_value
);
755 free (reg_last_set_table_tick
);
756 free (reg_last_set_label
);
757 free (reg_last_set_invalid
);
758 free (reg_last_set_mode
);
759 free (reg_last_set_nonzero_bits
);
760 free (reg_last_set_sign_bit_copies
);
764 struct undo
*undo
, *next
;
765 for (undo
= undobuf
.frees
; undo
; undo
= next
)
773 total_attempts
+= combine_attempts
;
774 total_merges
+= combine_merges
;
775 total_extras
+= combine_extras
;
776 total_successes
+= combine_successes
;
778 nonzero_sign_valid
= 0;
780 /* Make recognizer allow volatile MEMs again. */
783 return new_direct_jump_p
;
786 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
789 init_reg_last_arrays ()
791 unsigned int nregs
= combine_max_regno
;
793 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
794 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
795 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
796 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
797 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
798 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
799 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
800 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
801 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
804 /* Set up any promoted values for incoming argument registers. */
807 setup_incoming_promotions ()
809 #ifdef PROMOTE_FUNCTION_ARGS
812 enum machine_mode mode
;
814 rtx first
= get_insns ();
816 #ifndef OUTGOING_REGNO
817 #define OUTGOING_REGNO(N) N
819 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
820 /* Check whether this register can hold an incoming pointer
821 argument. FUNCTION_ARG_REGNO_P tests outgoing register
822 numbers, so translate if necessary due to register windows. */
823 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
824 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
827 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
830 gen_rtx_CLOBBER (mode
, const0_rtx
)));
835 /* Called via note_stores. If X is a pseudo that is narrower than
836 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
838 If we are setting only a portion of X and we can't figure out what
839 portion, assume all bits will be used since we don't know what will
842 Similarly, set how many bits of X are known to be copies of the sign bit
843 at all locations in the function. This is the smallest number implied
847 set_nonzero_bits_and_sign_copies (x
, set
, data
)
850 void *data ATTRIBUTE_UNUSED
;
854 if (GET_CODE (x
) == REG
855 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
856 /* If this register is undefined at the start of the file, we can't
857 say what its contents were. */
858 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
859 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
861 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
863 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
864 reg_sign_bit_copies
[REGNO (x
)] = 1;
868 /* If this is a complex assignment, see if we can convert it into a
869 simple assignment. */
870 set
= expand_field_assignment (set
);
872 /* If this is a simple assignment, or we have a paradoxical SUBREG,
873 set what we know about X. */
875 if (SET_DEST (set
) == x
876 || (GET_CODE (SET_DEST (set
)) == SUBREG
877 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
878 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
879 && SUBREG_REG (SET_DEST (set
)) == x
))
881 rtx src
= SET_SRC (set
);
883 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
884 /* If X is narrower than a word and SRC is a non-negative
885 constant that would appear negative in the mode of X,
886 sign-extend it for use in reg_nonzero_bits because some
887 machines (maybe most) will actually do the sign-extension
888 and this is the conservative approach.
890 ??? For 2.5, try to tighten up the MD files in this regard
891 instead of this kludge. */
893 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
894 && GET_CODE (src
) == CONST_INT
896 && 0 != (INTVAL (src
)
898 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
899 src
= GEN_INT (INTVAL (src
)
900 | ((HOST_WIDE_INT
) (-1)
901 << GET_MODE_BITSIZE (GET_MODE (x
))));
904 reg_nonzero_bits
[REGNO (x
)]
905 |= nonzero_bits (src
, nonzero_bits_mode
);
906 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
907 if (reg_sign_bit_copies
[REGNO (x
)] == 0
908 || reg_sign_bit_copies
[REGNO (x
)] > num
)
909 reg_sign_bit_copies
[REGNO (x
)] = num
;
913 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
914 reg_sign_bit_copies
[REGNO (x
)] = 1;
919 /* See if INSN can be combined into I3. PRED and SUCC are optionally
920 insns that were previously combined into I3 or that will be combined
921 into the merger of INSN and I3.
923 Return 0 if the combination is not allowed for any reason.
925 If the combination is allowed, *PDEST will be set to the single
926 destination of INSN and *PSRC to the single source, and this function
930 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
933 rtx pred ATTRIBUTE_UNUSED
;
938 rtx set
= 0, src
, dest
;
943 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
944 && next_active_insn (succ
) == i3
)
945 : next_active_insn (insn
) == i3
);
947 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
948 or a PARALLEL consisting of such a SET and CLOBBERs.
950 If INSN has CLOBBER parallel parts, ignore them for our processing.
951 By definition, these happen during the execution of the insn. When it
952 is merged with another insn, all bets are off. If they are, in fact,
953 needed and aren't also supplied in I3, they may be added by
954 recog_for_combine. Otherwise, it won't match.
956 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
959 Get the source and destination of INSN. If more than one, can't
962 if (GET_CODE (PATTERN (insn
)) == SET
)
963 set
= PATTERN (insn
);
964 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
965 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
967 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
969 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
971 switch (GET_CODE (elt
))
973 /* This is important to combine floating point insns
976 /* Combining an isolated USE doesn't make sense.
977 We depend here on combinable_i3_pat to reject them. */
978 /* The code below this loop only verifies that the inputs of
979 the SET in INSN do not change. We call reg_set_between_p
980 to verify that the REG in the USE does not change betweeen
982 If the USE in INSN was for a pseudo register, the matching
983 insn pattern will likely match any register; combining this
984 with any other USE would only be safe if we knew that the
985 used registers have identical values, or if there was
986 something to tell them apart, e.g. different modes. For
987 now, we forgo such compilcated tests and simply disallow
988 combining of USES of pseudo registers with any other USE. */
989 if (GET_CODE (XEXP (elt
, 0)) == REG
990 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
992 rtx i3pat
= PATTERN (i3
);
993 int i
= XVECLEN (i3pat
, 0) - 1;
994 unsigned int regno
= REGNO (XEXP (elt
, 0));
998 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1000 if (GET_CODE (i3elt
) == USE
1001 && GET_CODE (XEXP (i3elt
, 0)) == REG
1002 && (REGNO (XEXP (i3elt
, 0)) == regno
1003 ? reg_set_between_p (XEXP (elt
, 0),
1004 PREV_INSN (insn
), i3
)
1005 : regno
>= FIRST_PSEUDO_REGISTER
))
1012 /* We can ignore CLOBBERs. */
1017 /* Ignore SETs whose result isn't used but not those that
1018 have side-effects. */
1019 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1020 && ! side_effects_p (elt
))
1023 /* If we have already found a SET, this is a second one and
1024 so we cannot combine with this insn. */
1032 /* Anything else means we can't combine. */
1038 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1039 so don't do anything with it. */
1040 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1049 set
= expand_field_assignment (set
);
1050 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1052 /* Don't eliminate a store in the stack pointer. */
1053 if (dest
== stack_pointer_rtx
1054 /* If we couldn't eliminate a field assignment, we can't combine. */
1055 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1056 /* Don't combine with an insn that sets a register to itself if it has
1057 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1058 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1059 /* Can't merge an ASM_OPERANDS. */
1060 || GET_CODE (src
) == ASM_OPERANDS
1061 /* Can't merge a function call. */
1062 || GET_CODE (src
) == CALL
1063 /* Don't eliminate a function call argument. */
1064 || (GET_CODE (i3
) == CALL_INSN
1065 && (find_reg_fusage (i3
, USE
, dest
)
1066 || (GET_CODE (dest
) == REG
1067 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1068 && global_regs
[REGNO (dest
)])))
1069 /* Don't substitute into an incremented register. */
1070 || FIND_REG_INC_NOTE (i3
, dest
)
1071 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1073 /* Don't combine the end of a libcall into anything. */
1074 /* ??? This gives worse code, and appears to be unnecessary, since no
1075 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1076 use REG_RETVAL notes for noconflict blocks, but other code here
1077 makes sure that those insns don't disappear. */
1078 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1080 /* Make sure that DEST is not used after SUCC but before I3. */
1081 || (succ
&& ! all_adjacent
1082 && reg_used_between_p (dest
, succ
, i3
))
1083 /* Make sure that the value that is to be substituted for the register
1084 does not use any registers whose values alter in between. However,
1085 If the insns are adjacent, a use can't cross a set even though we
1086 think it might (this can happen for a sequence of insns each setting
1087 the same destination; reg_last_set of that register might point to
1088 a NOTE). If INSN has a REG_EQUIV note, the register is always
1089 equivalent to the memory so the substitution is valid even if there
1090 are intervening stores. Also, don't move a volatile asm or
1091 UNSPEC_VOLATILE across any other insns. */
1093 && (((GET_CODE (src
) != MEM
1094 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1095 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1096 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1097 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1098 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1099 better register allocation by not doing the combine. */
1100 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1101 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1102 /* Don't combine across a CALL_INSN, because that would possibly
1103 change whether the life span of some REGs crosses calls or not,
1104 and it is a pain to update that information.
1105 Exception: if source is a constant, moving it later can't hurt.
1106 Accept that special case, because it helps -fforce-addr a lot. */
1107 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1110 /* DEST must either be a REG or CC0. */
1111 if (GET_CODE (dest
) == REG
)
1113 /* If register alignment is being enforced for multi-word items in all
1114 cases except for parameters, it is possible to have a register copy
1115 insn referencing a hard register that is not allowed to contain the
1116 mode being copied and which would not be valid as an operand of most
1117 insns. Eliminate this problem by not combining with such an insn.
1119 Also, on some machines we don't want to extend the life of a hard
1122 if (GET_CODE (src
) == REG
1123 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1124 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1125 /* Don't extend the life of a hard register unless it is
1126 user variable (if we have few registers) or it can't
1127 fit into the desired register (meaning something special
1129 Also avoid substituting a return register into I3, because
1130 reload can't handle a conflict with constraints of other
1132 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1133 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1136 else if (GET_CODE (dest
) != CC0
)
1139 /* Don't substitute for a register intended as a clobberable operand.
1140 Similarly, don't substitute an expression containing a register that
1141 will be clobbered in I3. */
1142 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1143 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1144 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1145 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1147 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1150 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1151 or not), reject, unless nothing volatile comes between it and I3 */
1153 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1155 /* Make sure succ doesn't contain a volatile reference. */
1156 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1159 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1160 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1164 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1165 to be an explicit register variable, and was chosen for a reason. */
1167 if (GET_CODE (src
) == ASM_OPERANDS
1168 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1171 /* If there are any volatile insns between INSN and I3, reject, because
1172 they might affect machine state. */
1174 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1175 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1178 /* If INSN or I2 contains an autoincrement or autodecrement,
1179 make sure that register is not used between there and I3,
1180 and not already used in I3 either.
1181 Also insist that I3 not be a jump; if it were one
1182 and the incremented register were spilled, we would lose. */
1185 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1186 if (REG_NOTE_KIND (link
) == REG_INC
1187 && (GET_CODE (i3
) == JUMP_INSN
1188 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1189 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1194 /* Don't combine an insn that follows a CC0-setting insn.
1195 An insn that uses CC0 must not be separated from the one that sets it.
1196 We do, however, allow I2 to follow a CC0-setting insn if that insn
1197 is passed as I1; in that case it will be deleted also.
1198 We also allow combining in this case if all the insns are adjacent
1199 because that would leave the two CC0 insns adjacent as well.
1200 It would be more logical to test whether CC0 occurs inside I1 or I2,
1201 but that would be much slower, and this ought to be equivalent. */
1203 p
= prev_nonnote_insn (insn
);
1204 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1209 /* If we get here, we have passed all the tests and the combination is
1218 /* Check if PAT is an insn - or a part of it - used to set up an
1219 argument for a function in a hard register. */
1222 sets_function_arg_p (pat
)
1228 switch (GET_CODE (pat
))
1231 return sets_function_arg_p (PATTERN (pat
));
1234 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1235 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1241 inner_dest
= SET_DEST (pat
);
1242 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1243 || GET_CODE (inner_dest
) == SUBREG
1244 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1245 inner_dest
= XEXP (inner_dest
, 0);
1247 return (GET_CODE (inner_dest
) == REG
1248 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1249 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1258 /* LOC is the location within I3 that contains its pattern or the component
1259 of a PARALLEL of the pattern. We validate that it is valid for combining.
1261 One problem is if I3 modifies its output, as opposed to replacing it
1262 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1263 so would produce an insn that is not equivalent to the original insns.
1267 (set (reg:DI 101) (reg:DI 100))
1268 (set (subreg:SI (reg:DI 101) 0) <foo>)
1270 This is NOT equivalent to:
1272 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1273 (set (reg:DI 101) (reg:DI 100))])
1275 Not only does this modify 100 (in which case it might still be valid
1276 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1278 We can also run into a problem if I2 sets a register that I1
1279 uses and I1 gets directly substituted into I3 (not via I2). In that
1280 case, we would be getting the wrong value of I2DEST into I3, so we
1281 must reject the combination. This case occurs when I2 and I1 both
1282 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1283 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1284 of a SET must prevent combination from occurring.
1286 Before doing the above check, we first try to expand a field assignment
1287 into a set of logical operations.
1289 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1290 we place a register that is both set and used within I3. If more than one
1291 such register is detected, we fail.
1293 Return 1 if the combination is valid, zero otherwise. */
1296 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1302 rtx
*pi3dest_killed
;
1306 if (GET_CODE (x
) == SET
)
1308 rtx set
= expand_field_assignment (x
);
1309 rtx dest
= SET_DEST (set
);
1310 rtx src
= SET_SRC (set
);
1311 rtx inner_dest
= dest
;
1314 rtx inner_src
= src
;
1319 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1320 || GET_CODE (inner_dest
) == SUBREG
1321 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1322 inner_dest
= XEXP (inner_dest
, 0);
1324 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1327 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1328 || GET_CODE (inner_src
) == SUBREG
1329 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1330 inner_src
= XEXP (inner_src
, 0);
1332 /* If it is better that two different modes keep two different pseudos,
1333 avoid combining them. This avoids producing the following pattern
1335 (set (subreg:SI (reg/v:QI 21) 0)
1336 (lshiftrt:SI (reg/v:SI 20)
1338 If that were made, reload could not handle the pair of
1339 reg 20/21, since it would try to get any GENERAL_REGS
1340 but some of them don't handle QImode. */
1342 if (rtx_equal_p (inner_src
, i2dest
)
1343 && GET_CODE (inner_dest
) == REG
1344 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1348 /* Check for the case where I3 modifies its output, as
1350 if ((inner_dest
!= dest
1351 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1352 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1354 /* This is the same test done in can_combine_p except we can't test
1355 all_adjacent; we don't have to, since this instruction will stay
1356 in place, thus we are not considering increasing the lifetime of
1359 Also, if this insn sets a function argument, combining it with
1360 something that might need a spill could clobber a previous
1361 function argument; the all_adjacent test in can_combine_p also
1362 checks this; here, we do a more specific test for this case. */
1364 || (GET_CODE (inner_dest
) == REG
1365 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1366 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1367 GET_MODE (inner_dest
))))
1368 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1371 /* If DEST is used in I3, it is being killed in this insn,
1372 so record that for later.
1373 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1374 STACK_POINTER_REGNUM, since these are always considered to be
1375 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1376 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1377 && reg_referenced_p (dest
, PATTERN (i3
))
1378 && REGNO (dest
) != FRAME_POINTER_REGNUM
1379 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1380 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1382 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1383 && (REGNO (dest
) != ARG_POINTER_REGNUM
1384 || ! fixed_regs
[REGNO (dest
)])
1386 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1388 if (*pi3dest_killed
)
1391 *pi3dest_killed
= dest
;
1395 else if (GET_CODE (x
) == PARALLEL
)
1399 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1400 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1401 i1_not_in_src
, pi3dest_killed
))
1408 /* Return 1 if X is an arithmetic expression that contains a multiplication
1409 and division. We don't count multiplications by powers of two here. */
1415 switch (GET_CODE (x
))
1417 case MOD
: case DIV
: case UMOD
: case UDIV
:
1421 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1422 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1424 switch (GET_RTX_CLASS (GET_CODE (x
)))
1426 case 'c': case '<': case '2':
1427 return contains_muldiv (XEXP (x
, 0))
1428 || contains_muldiv (XEXP (x
, 1));
1431 return contains_muldiv (XEXP (x
, 0));
1439 /* Determine whether INSN can be used in a combination. Return nonzero if
1440 not. This is used in try_combine to detect early some cases where we
1441 can't perform combinations. */
1444 cant_combine_insn_p (insn
)
1450 /* If this isn't really an insn, we can't do anything.
1451 This can occur when flow deletes an insn that it has merged into an
1452 auto-increment address. */
1453 if (! INSN_P (insn
))
1456 /* Never combine loads and stores involving hard regs. The register
1457 allocator can usually handle such reg-reg moves by tying. If we allow
1458 the combiner to make substitutions of hard regs, we risk aborting in
1459 reload on machines that have SMALL_REGISTER_CLASSES.
1460 As an exception, we allow combinations involving fixed regs; these are
1461 not available to the register allocator so there's no risk involved. */
1463 set
= single_set (insn
);
1466 src
= SET_SRC (set
);
1467 dest
= SET_DEST (set
);
1468 if (GET_CODE (src
) == SUBREG
)
1469 src
= SUBREG_REG (src
);
1470 if (GET_CODE (dest
) == SUBREG
)
1471 dest
= SUBREG_REG (dest
);
1472 if (REG_P (src
) && REG_P (dest
)
1473 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1474 && ! fixed_regs
[REGNO (src
)])
1475 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1476 && ! fixed_regs
[REGNO (dest
)])))
1482 /* Try to combine the insns I1 and I2 into I3.
1483 Here I1 and I2 appear earlier than I3.
1484 I1 can be zero; then we combine just I2 into I3.
1486 It we are combining three insns and the resulting insn is not recognized,
1487 try splitting it into two insns. If that happens, I2 and I3 are retained
1488 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1491 Return 0 if the combination does not work. Then nothing is changed.
1492 If we did the combination, return the insn at which combine should
1495 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1496 new direct jump instruction. */
1499 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1500 register rtx i3
, i2
, i1
;
1501 register int *new_direct_jump_p
;
1503 /* New patterns for I3 and I2, respectively. */
1504 rtx newpat
, newi2pat
= 0;
1505 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1506 int added_sets_1
, added_sets_2
;
1507 /* Total number of SETs to put into I3. */
1509 /* Nonzero is I2's body now appears in I3. */
1511 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1512 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1513 /* Contains I3 if the destination of I3 is used in its source, which means
1514 that the old life of I3 is being killed. If that usage is placed into
1515 I2 and not in I3, a REG_DEAD note must be made. */
1516 rtx i3dest_killed
= 0;
1517 /* SET_DEST and SET_SRC of I2 and I1. */
1518 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1519 /* PATTERN (I2), or a copy of it in certain cases. */
1521 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1522 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1523 int i1_feeds_i3
= 0;
1524 /* Notes that must be added to REG_NOTES in I3 and I2. */
1525 rtx new_i3_notes
, new_i2_notes
;
1526 /* Notes that we substituted I3 into I2 instead of the normal case. */
1527 int i3_subst_into_i2
= 0;
1528 /* Notes that I1, I2 or I3 is a MULT operation. */
1536 /* Exit early if one of the insns involved can't be used for
1538 if (cant_combine_insn_p (i3
)
1539 || cant_combine_insn_p (i2
)
1540 || (i1
&& cant_combine_insn_p (i1
))
1541 /* We also can't do anything if I3 has a
1542 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1545 /* ??? This gives worse code, and appears to be unnecessary, since no
1546 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1547 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1553 undobuf
.other_insn
= 0;
1555 /* Reset the hard register usage information. */
1556 CLEAR_HARD_REG_SET (newpat_used_regs
);
1558 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1559 code below, set I1 to be the earlier of the two insns. */
1560 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1561 temp
= i1
, i1
= i2
, i2
= temp
;
1563 added_links_insn
= 0;
1565 /* First check for one important special-case that the code below will
1566 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1567 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1568 we may be able to replace that destination with the destination of I3.
1569 This occurs in the common code where we compute both a quotient and
1570 remainder into a structure, in which case we want to do the computation
1571 directly into the structure to avoid register-register copies.
1573 Note that this case handles both multiple sets in I2 and also
1574 cases where I2 has a number of CLOBBER or PARALLELs.
1576 We make very conservative checks below and only try to handle the
1577 most common cases of this. For example, we only handle the case
1578 where I2 and I3 are adjacent to avoid making difficult register
1581 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1582 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1583 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1584 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1585 && GET_CODE (PATTERN (i2
)) == PARALLEL
1586 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1587 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1588 below would need to check what is inside (and reg_overlap_mentioned_p
1589 doesn't support those codes anyway). Don't allow those destinations;
1590 the resulting insn isn't likely to be recognized anyway. */
1591 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1592 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1593 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1594 SET_DEST (PATTERN (i3
)))
1595 && next_real_insn (i2
) == i3
)
1597 rtx p2
= PATTERN (i2
);
1599 /* Make sure that the destination of I3,
1600 which we are going to substitute into one output of I2,
1601 is not used within another output of I2. We must avoid making this:
1602 (parallel [(set (mem (reg 69)) ...)
1603 (set (reg 69) ...)])
1604 which is not well-defined as to order of actions.
1605 (Besides, reload can't handle output reloads for this.)
1607 The problem can also happen if the dest of I3 is a memory ref,
1608 if another dest in I2 is an indirect memory ref. */
1609 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1610 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1611 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1612 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1613 SET_DEST (XVECEXP (p2
, 0, i
))))
1616 if (i
== XVECLEN (p2
, 0))
1617 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1618 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1619 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1620 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1625 subst_low_cuid
= INSN_CUID (i2
);
1627 added_sets_2
= added_sets_1
= 0;
1628 i2dest
= SET_SRC (PATTERN (i3
));
1630 /* Replace the dest in I2 with our dest and make the resulting
1631 insn the new pattern for I3. Then skip to where we
1632 validate the pattern. Everything was set up above. */
1633 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1634 SET_DEST (PATTERN (i3
)));
1637 i3_subst_into_i2
= 1;
1638 goto validate_replacement
;
1642 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1643 one of those words to another constant, merge them by making a new
1646 && (temp
= single_set (i2
)) != 0
1647 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1648 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1649 && GET_CODE (SET_DEST (temp
)) == REG
1650 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1651 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1652 && GET_CODE (PATTERN (i3
)) == SET
1653 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1654 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1655 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1656 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1657 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1659 HOST_WIDE_INT lo
, hi
;
1661 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1662 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1665 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1666 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1669 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1671 /* We don't handle the case of the target word being wider
1672 than a host wide int. */
1673 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1676 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1677 lo
|= INTVAL (SET_SRC (PATTERN (i3
)));
1679 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1680 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1681 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1683 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1684 >> (HOST_BITS_PER_WIDE_INT
- 1));
1686 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1687 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1688 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1689 (INTVAL (SET_SRC (PATTERN (i3
)))));
1691 hi
= lo
< 0 ? -1 : 0;
1694 /* We don't handle the case of the higher word not fitting
1695 entirely in either hi or lo. */
1700 subst_low_cuid
= INSN_CUID (i2
);
1701 added_sets_2
= added_sets_1
= 0;
1702 i2dest
= SET_DEST (temp
);
1704 SUBST (SET_SRC (temp
),
1705 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1707 newpat
= PATTERN (i2
);
1708 goto validate_replacement
;
1712 /* If we have no I1 and I2 looks like:
1713 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1715 make up a dummy I1 that is
1718 (set (reg:CC X) (compare:CC Y (const_int 0)))
1720 (We can ignore any trailing CLOBBERs.)
1722 This undoes a previous combination and allows us to match a branch-and-
1725 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1726 && XVECLEN (PATTERN (i2
), 0) >= 2
1727 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1728 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1730 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1731 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1732 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1733 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1734 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1735 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1737 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1738 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1743 /* We make I1 with the same INSN_UID as I2. This gives it
1744 the same INSN_CUID for value tracking. Our fake I1 will
1745 never appear in the insn stream so giving it the same INSN_UID
1746 as I2 will not cause a problem. */
1748 subst_prev_insn
= i1
1749 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1750 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1753 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1754 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1755 SET_DEST (PATTERN (i1
)));
1760 /* Verify that I2 and I1 are valid for combining. */
1761 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1762 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1768 /* Record whether I2DEST is used in I2SRC and similarly for the other
1769 cases. Knowing this will help in register status updating below. */
1770 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1771 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1772 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1774 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1776 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1778 /* Ensure that I3's pattern can be the destination of combines. */
1779 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1780 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1787 /* See if any of the insns is a MULT operation. Unless one is, we will
1788 reject a combination that is, since it must be slower. Be conservative
1790 if (GET_CODE (i2src
) == MULT
1791 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1792 || (GET_CODE (PATTERN (i3
)) == SET
1793 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1796 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1797 We used to do this EXCEPT in one case: I3 has a post-inc in an
1798 output operand. However, that exception can give rise to insns like
1800 which is a famous insn on the PDP-11 where the value of r3 used as the
1801 source was model-dependent. Avoid this sort of thing. */
1804 if (!(GET_CODE (PATTERN (i3
)) == SET
1805 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1806 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1807 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1808 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1809 /* It's not the exception. */
1812 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1813 if (REG_NOTE_KIND (link
) == REG_INC
1814 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1816 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1823 /* See if the SETs in I1 or I2 need to be kept around in the merged
1824 instruction: whenever the value set there is still needed past I3.
1825 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1827 For the SET in I1, we have two cases: If I1 and I2 independently
1828 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1829 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1830 in I1 needs to be kept around unless I1DEST dies or is set in either
1831 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1832 I1DEST. If so, we know I1 feeds into I2. */
1834 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1837 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1838 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1840 /* If the set in I2 needs to be kept around, we must make a copy of
1841 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1842 PATTERN (I2), we are only substituting for the original I1DEST, not into
1843 an already-substituted copy. This also prevents making self-referential
1844 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1847 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1848 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1852 i2pat
= copy_rtx (i2pat
);
1856 /* Substitute in the latest insn for the regs set by the earlier ones. */
1858 maxreg
= max_reg_num ();
1862 /* It is possible that the source of I2 or I1 may be performing an
1863 unneeded operation, such as a ZERO_EXTEND of something that is known
1864 to have the high part zero. Handle that case by letting subst look at
1865 the innermost one of them.
1867 Another way to do this would be to have a function that tries to
1868 simplify a single insn instead of merging two or more insns. We don't
1869 do this because of the potential of infinite loops and because
1870 of the potential extra memory required. However, doing it the way
1871 we are is a bit of a kludge and doesn't catch all cases.
1873 But only do this if -fexpensive-optimizations since it slows things down
1874 and doesn't usually win. */
1876 if (flag_expensive_optimizations
)
1878 /* Pass pc_rtx so no substitutions are done, just simplifications.
1879 The cases that we are interested in here do not involve the few
1880 cases were is_replaced is checked. */
1883 subst_low_cuid
= INSN_CUID (i1
);
1884 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1888 subst_low_cuid
= INSN_CUID (i2
);
1889 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1892 undobuf
.previous_undos
= undobuf
.undos
;
1896 /* Many machines that don't use CC0 have insns that can both perform an
1897 arithmetic operation and set the condition code. These operations will
1898 be represented as a PARALLEL with the first element of the vector
1899 being a COMPARE of an arithmetic operation with the constant zero.
1900 The second element of the vector will set some pseudo to the result
1901 of the same arithmetic operation. If we simplify the COMPARE, we won't
1902 match such a pattern and so will generate an extra insn. Here we test
1903 for this case, where both the comparison and the operation result are
1904 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1905 I2SRC. Later we will make the PARALLEL that contains I2. */
1907 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1908 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1909 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1910 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1912 #ifdef EXTRA_CC_MODES
1914 enum machine_mode compare_mode
;
1917 newpat
= PATTERN (i3
);
1918 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1922 #ifdef EXTRA_CC_MODES
1923 /* See if a COMPARE with the operand we substituted in should be done
1924 with the mode that is currently being used. If not, do the same
1925 processing we do in `subst' for a SET; namely, if the destination
1926 is used only once, try to replace it with a register of the proper
1927 mode and also replace the COMPARE. */
1928 if (undobuf
.other_insn
== 0
1929 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1930 &undobuf
.other_insn
))
1931 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1933 != GET_MODE (SET_DEST (newpat
))))
1935 unsigned int regno
= REGNO (SET_DEST (newpat
));
1936 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1938 if (regno
< FIRST_PSEUDO_REGISTER
1939 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1940 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1942 if (regno
>= FIRST_PSEUDO_REGISTER
)
1943 SUBST (regno_reg_rtx
[regno
], new_dest
);
1945 SUBST (SET_DEST (newpat
), new_dest
);
1946 SUBST (XEXP (*cc_use
, 0), new_dest
);
1947 SUBST (SET_SRC (newpat
),
1948 gen_rtx_combine (COMPARE
, compare_mode
,
1949 i2src
, const0_rtx
));
1952 undobuf
.other_insn
= 0;
1959 n_occurrences
= 0; /* `subst' counts here */
1961 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1962 need to make a unique copy of I2SRC each time we substitute it
1963 to avoid self-referential rtl. */
1965 subst_low_cuid
= INSN_CUID (i2
);
1966 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1967 ! i1_feeds_i3
&& i1dest_in_i1src
);
1968 undobuf
.previous_undos
= undobuf
.undos
;
1970 /* Record whether i2's body now appears within i3's body. */
1971 i2_is_used
= n_occurrences
;
1974 /* If we already got a failure, don't try to do more. Otherwise,
1975 try to substitute in I1 if we have it. */
1977 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1979 /* Before we can do this substitution, we must redo the test done
1980 above (see detailed comments there) that ensures that I1DEST
1981 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1983 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1991 subst_low_cuid
= INSN_CUID (i1
);
1992 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1993 undobuf
.previous_undos
= undobuf
.undos
;
1996 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1997 to count all the ways that I2SRC and I1SRC can be used. */
1998 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1999 && i2_is_used
+ added_sets_2
> 1)
2000 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2001 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2003 /* Fail if we tried to make a new register (we used to abort, but there's
2004 really no reason to). */
2005 || max_reg_num () != maxreg
2006 /* Fail if we couldn't do something and have a CLOBBER. */
2007 || GET_CODE (newpat
) == CLOBBER
2008 /* Fail if this new pattern is a MULT and we didn't have one before
2009 at the outer level. */
2010 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2017 /* If the actions of the earlier insns must be kept
2018 in addition to substituting them into the latest one,
2019 we must make a new PARALLEL for the latest insn
2020 to hold additional the SETs. */
2022 if (added_sets_1
|| added_sets_2
)
2026 if (GET_CODE (newpat
) == PARALLEL
)
2028 rtvec old
= XVEC (newpat
, 0);
2029 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2030 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2031 bcopy ((char *) &old
->elem
[0], (char *) XVEC (newpat
, 0)->elem
,
2032 sizeof (old
->elem
[0]) * old
->num_elem
);
2037 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2038 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2039 XVECEXP (newpat
, 0, 0) = old
;
2043 XVECEXP (newpat
, 0, --total_sets
)
2044 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2045 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2049 /* If there is no I1, use I2's body as is. We used to also not do
2050 the subst call below if I2 was substituted into I3,
2051 but that could lose a simplification. */
2053 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2055 /* See comment where i2pat is assigned. */
2056 XVECEXP (newpat
, 0, --total_sets
)
2057 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2061 /* We come here when we are replacing a destination in I2 with the
2062 destination of I3. */
2063 validate_replacement
:
2065 /* Note which hard regs this insn has as inputs. */
2066 mark_used_regs_combine (newpat
);
2068 /* Is the result of combination a valid instruction? */
2069 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2071 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2072 the second SET's destination is a register that is unused. In that case,
2073 we just need the first SET. This can occur when simplifying a divmod
2074 insn. We *must* test for this case here because the code below that
2075 splits two independent SETs doesn't handle this case correctly when it
2076 updates the register status. Also check the case where the first
2077 SET's destination is unused. That would not cause incorrect code, but
2078 does cause an unneeded insn to remain. */
2080 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2081 && XVECLEN (newpat
, 0) == 2
2082 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2083 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2084 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2085 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2086 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2087 && asm_noperands (newpat
) < 0)
2089 newpat
= XVECEXP (newpat
, 0, 0);
2090 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2093 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2094 && XVECLEN (newpat
, 0) == 2
2095 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2096 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2097 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2098 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2099 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2100 && asm_noperands (newpat
) < 0)
2102 newpat
= XVECEXP (newpat
, 0, 1);
2103 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2106 /* If we were combining three insns and the result is a simple SET
2107 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2108 insns. There are two ways to do this. It can be split using a
2109 machine-specific method (like when you have an addition of a large
2110 constant) or by combine in the function find_split_point. */
2112 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2113 && asm_noperands (newpat
) < 0)
2115 rtx m_split
, *split
;
2116 rtx ni2dest
= i2dest
;
2118 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2119 use I2DEST as a scratch register will help. In the latter case,
2120 convert I2DEST to the mode of the source of NEWPAT if we can. */
2122 m_split
= split_insns (newpat
, i3
);
2124 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2125 inputs of NEWPAT. */
2127 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2128 possible to try that as a scratch reg. This would require adding
2129 more code to make it work though. */
2131 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2133 /* If I2DEST is a hard register or the only use of a pseudo,
2134 we can change its mode. */
2135 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2136 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2137 && GET_CODE (i2dest
) == REG
2138 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2139 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2140 && ! REG_USERVAR_P (i2dest
))))
2141 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2144 m_split
= split_insns (gen_rtx_PARALLEL
2146 gen_rtvec (2, newpat
,
2147 gen_rtx_CLOBBER (VOIDmode
,
2150 /* If the split with the mode-changed register didn't work, try
2151 the original register. */
2152 if (! m_split
&& ni2dest
!= i2dest
)
2155 m_split
= split_insns (gen_rtx_PARALLEL
2157 gen_rtvec (2, newpat
,
2158 gen_rtx_CLOBBER (VOIDmode
,
2164 if (m_split
&& GET_CODE (m_split
) != SEQUENCE
)
2166 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2167 if (insn_code_number
>= 0)
2170 else if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2171 && XVECLEN (m_split
, 0) == 2
2172 && (next_real_insn (i2
) == i3
2173 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2177 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2178 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2180 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2181 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2183 /* In case we changed the mode of I2DEST, replace it in the
2184 pseudo-register table here. We can't do it above in case this
2185 code doesn't get executed and we do a split the other way. */
2187 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2188 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2190 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2192 /* If I2 or I3 has multiple SETs, we won't know how to track
2193 register status, so don't use these insns. If I2's destination
2194 is used between I2 and I3, we also can't use these insns. */
2196 if (i2_code_number
>= 0 && i2set
&& i3set
2197 && (next_real_insn (i2
) == i3
2198 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2199 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2201 if (insn_code_number
>= 0)
2204 /* It is possible that both insns now set the destination of I3.
2205 If so, we must show an extra use of it. */
2207 if (insn_code_number
>= 0)
2209 rtx new_i3_dest
= SET_DEST (i3set
);
2210 rtx new_i2_dest
= SET_DEST (i2set
);
2212 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2213 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2214 || GET_CODE (new_i3_dest
) == SUBREG
)
2215 new_i3_dest
= XEXP (new_i3_dest
, 0);
2217 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2218 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2219 || GET_CODE (new_i2_dest
) == SUBREG
)
2220 new_i2_dest
= XEXP (new_i2_dest
, 0);
2222 if (GET_CODE (new_i3_dest
) == REG
2223 && GET_CODE (new_i2_dest
) == REG
2224 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2225 REG_N_SETS (REGNO (new_i2_dest
))++;
2229 /* If we can split it and use I2DEST, go ahead and see if that
2230 helps things be recognized. Verify that none of the registers
2231 are set between I2 and I3. */
2232 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2234 && GET_CODE (i2dest
) == REG
2236 /* We need I2DEST in the proper mode. If it is a hard register
2237 or the only use of a pseudo, we can change its mode. */
2238 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2239 || GET_MODE (*split
) == VOIDmode
2240 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2241 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2242 && ! REG_USERVAR_P (i2dest
)))
2243 && (next_real_insn (i2
) == i3
2244 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2245 /* We can't overwrite I2DEST if its value is still used by
2247 && ! reg_referenced_p (i2dest
, newpat
))
2249 rtx newdest
= i2dest
;
2250 enum rtx_code split_code
= GET_CODE (*split
);
2251 enum machine_mode split_mode
= GET_MODE (*split
);
2253 /* Get NEWDEST as a register in the proper mode. We have already
2254 validated that we can do this. */
2255 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2257 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2259 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2260 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2263 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2264 an ASHIFT. This can occur if it was inside a PLUS and hence
2265 appeared to be a memory address. This is a kludge. */
2266 if (split_code
== MULT
2267 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2268 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2270 SUBST (*split
, gen_rtx_combine (ASHIFT
, split_mode
,
2271 XEXP (*split
, 0), GEN_INT (i
)));
2272 /* Update split_code because we may not have a multiply
2274 split_code
= GET_CODE (*split
);
2277 #ifdef INSN_SCHEDULING
2278 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2279 be written as a ZERO_EXTEND. */
2280 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2281 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, split_mode
,
2285 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
2286 SUBST (*split
, newdest
);
2287 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2289 /* If the split point was a MULT and we didn't have one before,
2290 don't use one now. */
2291 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2292 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2296 /* Check for a case where we loaded from memory in a narrow mode and
2297 then sign extended it, but we need both registers. In that case,
2298 we have a PARALLEL with both loads from the same memory location.
2299 We can split this into a load from memory followed by a register-register
2300 copy. This saves at least one insn, more if register allocation can
2303 We cannot do this if the destination of the second assignment is
2304 a register that we have already assumed is zero-extended. Similarly
2305 for a SUBREG of such a register. */
2307 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2308 && GET_CODE (newpat
) == PARALLEL
2309 && XVECLEN (newpat
, 0) == 2
2310 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2311 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2312 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2313 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2314 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2315 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2317 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2318 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2319 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2320 (GET_CODE (temp
) == REG
2321 && reg_nonzero_bits
[REGNO (temp
)] != 0
2322 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2323 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2324 && (reg_nonzero_bits
[REGNO (temp
)]
2325 != GET_MODE_MASK (word_mode
))))
2326 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2327 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2328 (GET_CODE (temp
) == REG
2329 && reg_nonzero_bits
[REGNO (temp
)] != 0
2330 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2331 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2332 && (reg_nonzero_bits
[REGNO (temp
)]
2333 != GET_MODE_MASK (word_mode
)))))
2334 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2335 SET_SRC (XVECEXP (newpat
, 0, 1)))
2336 && ! find_reg_note (i3
, REG_UNUSED
,
2337 SET_DEST (XVECEXP (newpat
, 0, 0))))
2341 newi2pat
= XVECEXP (newpat
, 0, 0);
2342 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2343 newpat
= XVECEXP (newpat
, 0, 1);
2344 SUBST (SET_SRC (newpat
),
2345 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2346 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2348 if (i2_code_number
>= 0)
2349 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2351 if (insn_code_number
>= 0)
2356 /* If we will be able to accept this, we have made a change to the
2357 destination of I3. This can invalidate a LOG_LINKS pointing
2358 to I3. No other part of combine.c makes such a transformation.
2360 The new I3 will have a destination that was previously the
2361 destination of I1 or I2 and which was used in i2 or I3. Call
2362 distribute_links to make a LOG_LINK from the next use of
2363 that destination. */
2365 PATTERN (i3
) = newpat
;
2366 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2368 /* I3 now uses what used to be its destination and which is
2369 now I2's destination. That means we need a LOG_LINK from
2370 I3 to I2. But we used to have one, so we still will.
2372 However, some later insn might be using I2's dest and have
2373 a LOG_LINK pointing at I3. We must remove this link.
2374 The simplest way to remove the link is to point it at I1,
2375 which we know will be a NOTE. */
2377 for (insn
= NEXT_INSN (i3
);
2378 insn
&& (this_basic_block
== n_basic_blocks
- 1
2379 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2380 insn
= NEXT_INSN (insn
))
2382 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2384 for (link
= LOG_LINKS (insn
); link
;
2385 link
= XEXP (link
, 1))
2386 if (XEXP (link
, 0) == i3
)
2387 XEXP (link
, 0) = i1
;
2395 /* Similarly, check for a case where we have a PARALLEL of two independent
2396 SETs but we started with three insns. In this case, we can do the sets
2397 as two separate insns. This case occurs when some SET allows two
2398 other insns to combine, but the destination of that SET is still live. */
2400 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2401 && GET_CODE (newpat
) == PARALLEL
2402 && XVECLEN (newpat
, 0) == 2
2403 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2404 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2405 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2406 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2407 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2408 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2409 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2411 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2412 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2413 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2414 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2415 XVECEXP (newpat
, 0, 0))
2416 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2417 XVECEXP (newpat
, 0, 1))
2418 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2419 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2421 /* Normally, it doesn't matter which of the two is done first,
2422 but it does if one references cc0. In that case, it has to
2425 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2427 newi2pat
= XVECEXP (newpat
, 0, 0);
2428 newpat
= XVECEXP (newpat
, 0, 1);
2433 newi2pat
= XVECEXP (newpat
, 0, 1);
2434 newpat
= XVECEXP (newpat
, 0, 0);
2437 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2439 if (i2_code_number
>= 0)
2440 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2443 /* If it still isn't recognized, fail and change things back the way they
2445 if ((insn_code_number
< 0
2446 /* Is the result a reasonable ASM_OPERANDS? */
2447 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2453 /* If we had to change another insn, make sure it is valid also. */
2454 if (undobuf
.other_insn
)
2456 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2457 rtx new_other_notes
;
2460 CLEAR_HARD_REG_SET (newpat_used_regs
);
2462 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2465 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2471 PATTERN (undobuf
.other_insn
) = other_pat
;
2473 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2474 are still valid. Then add any non-duplicate notes added by
2475 recog_for_combine. */
2476 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2478 next
= XEXP (note
, 1);
2480 if (REG_NOTE_KIND (note
) == REG_UNUSED
2481 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2483 if (GET_CODE (XEXP (note
, 0)) == REG
)
2484 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2486 remove_note (undobuf
.other_insn
, note
);
2490 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2491 if (GET_CODE (XEXP (note
, 0)) == REG
)
2492 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2494 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2495 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2498 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2499 they are adjacent to each other or not. */
2501 rtx p
= prev_nonnote_insn (i3
);
2502 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2503 && sets_cc0_p (newi2pat
))
2511 /* We now know that we can do this combination. Merge the insns and
2512 update the status of registers and LOG_LINKS. */
2515 rtx i3notes
, i2notes
, i1notes
= 0;
2516 rtx i3links
, i2links
, i1links
= 0;
2519 /* Compute which registers we expect to eliminate. newi2pat may be setting
2520 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2521 same as i3dest, in which case newi2pat may be setting i1dest. */
2522 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2523 || i2dest_in_i2src
|| i2dest_in_i1src
2525 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2526 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2529 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2531 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2532 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2534 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2536 /* Ensure that we do not have something that should not be shared but
2537 occurs multiple times in the new insns. Check this by first
2538 resetting all the `used' flags and then copying anything is shared. */
2540 reset_used_flags (i3notes
);
2541 reset_used_flags (i2notes
);
2542 reset_used_flags (i1notes
);
2543 reset_used_flags (newpat
);
2544 reset_used_flags (newi2pat
);
2545 if (undobuf
.other_insn
)
2546 reset_used_flags (PATTERN (undobuf
.other_insn
));
2548 i3notes
= copy_rtx_if_shared (i3notes
);
2549 i2notes
= copy_rtx_if_shared (i2notes
);
2550 i1notes
= copy_rtx_if_shared (i1notes
);
2551 newpat
= copy_rtx_if_shared (newpat
);
2552 newi2pat
= copy_rtx_if_shared (newi2pat
);
2553 if (undobuf
.other_insn
)
2554 reset_used_flags (PATTERN (undobuf
.other_insn
));
2556 INSN_CODE (i3
) = insn_code_number
;
2557 PATTERN (i3
) = newpat
;
2558 if (undobuf
.other_insn
)
2559 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2561 /* We had one special case above where I2 had more than one set and
2562 we replaced a destination of one of those sets with the destination
2563 of I3. In that case, we have to update LOG_LINKS of insns later
2564 in this basic block. Note that this (expensive) case is rare.
2566 Also, in this case, we must pretend that all REG_NOTEs for I2
2567 actually came from I3, so that REG_UNUSED notes from I2 will be
2568 properly handled. */
2570 if (i3_subst_into_i2
)
2572 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2573 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2574 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2575 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2576 && ! find_reg_note (i2
, REG_UNUSED
,
2577 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2578 for (temp
= NEXT_INSN (i2
);
2579 temp
&& (this_basic_block
== n_basic_blocks
- 1
2580 || BLOCK_HEAD (this_basic_block
) != temp
);
2581 temp
= NEXT_INSN (temp
))
2582 if (temp
!= i3
&& INSN_P (temp
))
2583 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2584 if (XEXP (link
, 0) == i2
)
2585 XEXP (link
, 0) = i3
;
2590 while (XEXP (link
, 1))
2591 link
= XEXP (link
, 1);
2592 XEXP (link
, 1) = i2notes
;
2606 INSN_CODE (i2
) = i2_code_number
;
2607 PATTERN (i2
) = newi2pat
;
2611 PUT_CODE (i2
, NOTE
);
2612 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2613 NOTE_SOURCE_FILE (i2
) = 0;
2620 PUT_CODE (i1
, NOTE
);
2621 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2622 NOTE_SOURCE_FILE (i1
) = 0;
2625 /* Get death notes for everything that is now used in either I3 or
2626 I2 and used to die in a previous insn. If we built two new
2627 patterns, move from I1 to I2 then I2 to I3 so that we get the
2628 proper movement on registers that I2 modifies. */
2632 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2633 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2636 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2639 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2641 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2644 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2647 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2650 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2653 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2654 know these are REG_UNUSED and want them to go to the desired insn,
2655 so we always pass it as i3. We have not counted the notes in
2656 reg_n_deaths yet, so we need to do so now. */
2658 if (newi2pat
&& new_i2_notes
)
2660 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2661 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2662 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2664 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2669 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2670 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2671 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2673 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2676 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2677 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2678 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2679 in that case, it might delete I2. Similarly for I2 and I1.
2680 Show an additional death due to the REG_DEAD note we make here. If
2681 we discard it in distribute_notes, we will decrement it again. */
2685 if (GET_CODE (i3dest_killed
) == REG
)
2686 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2688 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2689 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2691 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2693 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2695 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2699 if (i2dest_in_i2src
)
2701 if (GET_CODE (i2dest
) == REG
)
2702 REG_N_DEATHS (REGNO (i2dest
))++;
2704 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2705 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2706 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2708 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2709 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2710 NULL_RTX
, NULL_RTX
);
2713 if (i1dest_in_i1src
)
2715 if (GET_CODE (i1dest
) == REG
)
2716 REG_N_DEATHS (REGNO (i1dest
))++;
2718 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2719 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2720 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2722 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2723 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2724 NULL_RTX
, NULL_RTX
);
2727 distribute_links (i3links
);
2728 distribute_links (i2links
);
2729 distribute_links (i1links
);
2731 if (GET_CODE (i2dest
) == REG
)
2734 rtx i2_insn
= 0, i2_val
= 0, set
;
2736 /* The insn that used to set this register doesn't exist, and
2737 this life of the register may not exist either. See if one of
2738 I3's links points to an insn that sets I2DEST. If it does,
2739 that is now the last known value for I2DEST. If we don't update
2740 this and I2 set the register to a value that depended on its old
2741 contents, we will get confused. If this insn is used, thing
2742 will be set correctly in combine_instructions. */
2744 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2745 if ((set
= single_set (XEXP (link
, 0))) != 0
2746 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2747 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2749 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2751 /* If the reg formerly set in I2 died only once and that was in I3,
2752 zero its use count so it won't make `reload' do any work. */
2754 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2755 && ! i2dest_in_i2src
)
2757 regno
= REGNO (i2dest
);
2758 REG_N_SETS (regno
)--;
2762 if (i1
&& GET_CODE (i1dest
) == REG
)
2765 rtx i1_insn
= 0, i1_val
= 0, set
;
2767 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2768 if ((set
= single_set (XEXP (link
, 0))) != 0
2769 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2770 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2772 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2774 regno
= REGNO (i1dest
);
2775 if (! added_sets_1
&& ! i1dest_in_i1src
)
2776 REG_N_SETS (regno
)--;
2779 /* Update reg_nonzero_bits et al for any changes that may have been made
2780 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2781 important. Because newi2pat can affect nonzero_bits of newpat */
2783 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2784 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2786 /* Set new_direct_jump_p if a new return or simple jump instruction
2789 If I3 is now an unconditional jump, ensure that it has a
2790 BARRIER following it since it may have initially been a
2791 conditional jump. It may also be the last nonnote insn. */
2793 if (GET_CODE (newpat
) == RETURN
|| any_uncondjump_p (i3
))
2795 *new_direct_jump_p
= 1;
2797 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2798 || GET_CODE (temp
) != BARRIER
)
2799 emit_barrier_after (i3
);
2803 combine_successes
++;
2806 /* Clear this here, so that subsequent get_last_value calls are not
2808 subst_prev_insn
= NULL_RTX
;
2810 if (added_links_insn
2811 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2812 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2813 return added_links_insn
;
2815 return newi2pat
? i2
: i3
;
2818 /* Undo all the modifications recorded in undobuf. */
2823 struct undo
*undo
, *next
;
2825 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2829 *undo
->where
.i
= undo
->old_contents
.i
;
2831 *undo
->where
.r
= undo
->old_contents
.r
;
2833 undo
->next
= undobuf
.frees
;
2834 undobuf
.frees
= undo
;
2837 undobuf
.undos
= undobuf
.previous_undos
= 0;
2839 /* Clear this here, so that subsequent get_last_value calls are not
2841 subst_prev_insn
= NULL_RTX
;
2844 /* We've committed to accepting the changes we made. Move all
2845 of the undos to the free list. */
2850 struct undo
*undo
, *next
;
2852 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2855 undo
->next
= undobuf
.frees
;
2856 undobuf
.frees
= undo
;
2858 undobuf
.undos
= undobuf
.previous_undos
= 0;
2862 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2863 where we have an arithmetic expression and return that point. LOC will
2866 try_combine will call this function to see if an insn can be split into
2870 find_split_point (loc
, insn
)
2875 enum rtx_code code
= GET_CODE (x
);
2877 unsigned HOST_WIDE_INT len
= 0;
2878 HOST_WIDE_INT pos
= 0;
2880 rtx inner
= NULL_RTX
;
2882 /* First special-case some codes. */
2886 #ifdef INSN_SCHEDULING
2887 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2889 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2892 return find_split_point (&SUBREG_REG (x
), insn
);
2896 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2897 using LO_SUM and HIGH. */
2898 if (GET_CODE (XEXP (x
, 0)) == CONST
2899 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2902 gen_rtx_combine (LO_SUM
, Pmode
,
2903 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
2905 return &XEXP (XEXP (x
, 0), 0);
2909 /* If we have a PLUS whose second operand is a constant and the
2910 address is not valid, perhaps will can split it up using
2911 the machine-specific way to split large constants. We use
2912 the first pseudo-reg (one of the virtual regs) as a placeholder;
2913 it will not remain in the result. */
2914 if (GET_CODE (XEXP (x
, 0)) == PLUS
2915 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2916 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2918 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2919 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2922 /* This should have produced two insns, each of which sets our
2923 placeholder. If the source of the second is a valid address,
2924 we can make put both sources together and make a split point
2927 if (seq
&& XVECLEN (seq
, 0) == 2
2928 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2929 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2930 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2931 && ! reg_mentioned_p (reg
,
2932 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2933 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2934 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2935 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2936 && memory_address_p (GET_MODE (x
),
2937 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2939 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2940 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2942 /* Replace the placeholder in SRC2 with SRC1. If we can
2943 find where in SRC2 it was placed, that can become our
2944 split point and we can replace this address with SRC2.
2945 Just try two obvious places. */
2947 src2
= replace_rtx (src2
, reg
, src1
);
2949 if (XEXP (src2
, 0) == src1
)
2950 split
= &XEXP (src2
, 0);
2951 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2952 && XEXP (XEXP (src2
, 0), 0) == src1
)
2953 split
= &XEXP (XEXP (src2
, 0), 0);
2957 SUBST (XEXP (x
, 0), src2
);
2962 /* If that didn't work, perhaps the first operand is complex and
2963 needs to be computed separately, so make a split point there.
2964 This will occur on machines that just support REG + CONST
2965 and have a constant moved through some previous computation. */
2967 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2968 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2969 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2971 return &XEXP (XEXP (x
, 0), 0);
2977 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2978 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2979 we need to put the operand into a register. So split at that
2982 if (SET_DEST (x
) == cc0_rtx
2983 && GET_CODE (SET_SRC (x
)) != COMPARE
2984 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2985 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2986 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2987 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2988 return &SET_SRC (x
);
2991 /* See if we can split SET_SRC as it stands. */
2992 split
= find_split_point (&SET_SRC (x
), insn
);
2993 if (split
&& split
!= &SET_SRC (x
))
2996 /* See if we can split SET_DEST as it stands. */
2997 split
= find_split_point (&SET_DEST (x
), insn
);
2998 if (split
&& split
!= &SET_DEST (x
))
3001 /* See if this is a bitfield assignment with everything constant. If
3002 so, this is an IOR of an AND, so split it into that. */
3003 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3004 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3005 <= HOST_BITS_PER_WIDE_INT
)
3006 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3007 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3008 && GET_CODE (SET_SRC (x
)) == CONST_INT
3009 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3010 + INTVAL (XEXP (SET_DEST (x
), 2)))
3011 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3012 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3014 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3015 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3016 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3017 rtx dest
= XEXP (SET_DEST (x
), 0);
3018 enum machine_mode mode
= GET_MODE (dest
);
3019 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3021 if (BITS_BIG_ENDIAN
)
3022 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3026 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3029 gen_binary (IOR
, mode
,
3030 gen_binary (AND
, mode
, dest
,
3031 GEN_INT (~(mask
<< pos
)
3032 & GET_MODE_MASK (mode
))),
3033 GEN_INT (src
<< pos
)));
3035 SUBST (SET_DEST (x
), dest
);
3037 split
= find_split_point (&SET_SRC (x
), insn
);
3038 if (split
&& split
!= &SET_SRC (x
))
3042 /* Otherwise, see if this is an operation that we can split into two.
3043 If so, try to split that. */
3044 code
= GET_CODE (SET_SRC (x
));
3049 /* If we are AND'ing with a large constant that is only a single
3050 bit and the result is only being used in a context where we
3051 need to know if it is zero or non-zero, replace it with a bit
3052 extraction. This will avoid the large constant, which might
3053 have taken more than one insn to make. If the constant were
3054 not a valid argument to the AND but took only one insn to make,
3055 this is no worse, but if it took more than one insn, it will
3058 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3059 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3060 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3061 && GET_CODE (SET_DEST (x
)) == REG
3062 && (split
= find_single_use (SET_DEST (x
), insn
, NULL_PTR
)) != 0
3063 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3064 && XEXP (*split
, 0) == SET_DEST (x
)
3065 && XEXP (*split
, 1) == const0_rtx
)
3067 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3068 XEXP (SET_SRC (x
), 0),
3069 pos
, NULL_RTX
, 1, 1, 0, 0);
3070 if (extraction
!= 0)
3072 SUBST (SET_SRC (x
), extraction
);
3073 return find_split_point (loc
, insn
);
3079 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3080 is known to be on, this can be converted into a NEG of a shift. */
3081 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3082 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3083 && 1 <= (pos
= exact_log2
3084 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3085 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3087 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3090 gen_rtx_combine (NEG
, mode
,
3091 gen_rtx_combine (LSHIFTRT
, mode
,
3092 XEXP (SET_SRC (x
), 0),
3095 split
= find_split_point (&SET_SRC (x
), insn
);
3096 if (split
&& split
!= &SET_SRC (x
))
3102 inner
= XEXP (SET_SRC (x
), 0);
3104 /* We can't optimize if either mode is a partial integer
3105 mode as we don't know how many bits are significant
3107 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3108 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3112 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3118 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3119 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3121 inner
= XEXP (SET_SRC (x
), 0);
3122 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3123 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3125 if (BITS_BIG_ENDIAN
)
3126 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3127 unsignedp
= (code
== ZERO_EXTRACT
);
3135 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3137 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3139 /* For unsigned, we have a choice of a shift followed by an
3140 AND or two shifts. Use two shifts for field sizes where the
3141 constant might be too large. We assume here that we can
3142 always at least get 8-bit constants in an AND insn, which is
3143 true for every current RISC. */
3145 if (unsignedp
&& len
<= 8)
3150 gen_rtx_combine (LSHIFTRT
, mode
,
3151 gen_lowpart_for_combine (mode
, inner
),
3153 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3155 split
= find_split_point (&SET_SRC (x
), insn
);
3156 if (split
&& split
!= &SET_SRC (x
))
3163 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3164 gen_rtx_combine (ASHIFT
, mode
,
3165 gen_lowpart_for_combine (mode
, inner
),
3166 GEN_INT (GET_MODE_BITSIZE (mode
)
3168 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3170 split
= find_split_point (&SET_SRC (x
), insn
);
3171 if (split
&& split
!= &SET_SRC (x
))
3176 /* See if this is a simple operation with a constant as the second
3177 operand. It might be that this constant is out of range and hence
3178 could be used as a split point. */
3179 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3180 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3181 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3182 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3183 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3184 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3185 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3187 return &XEXP (SET_SRC (x
), 1);
3189 /* Finally, see if this is a simple operation with its first operand
3190 not in a register. The operation might require this operand in a
3191 register, so return it as a split point. We can always do this
3192 because if the first operand were another operation, we would have
3193 already found it as a split point. */
3194 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3195 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3196 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3197 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3198 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3199 return &XEXP (SET_SRC (x
), 0);
3205 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3206 it is better to write this as (not (ior A B)) so we can split it.
3207 Similarly for IOR. */
3208 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3211 gen_rtx_combine (NOT
, GET_MODE (x
),
3212 gen_rtx_combine (code
== IOR
? AND
: IOR
,
3214 XEXP (XEXP (x
, 0), 0),
3215 XEXP (XEXP (x
, 1), 0))));
3216 return find_split_point (loc
, insn
);
3219 /* Many RISC machines have a large set of logical insns. If the
3220 second operand is a NOT, put it first so we will try to split the
3221 other operand first. */
3222 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3224 rtx tem
= XEXP (x
, 0);
3225 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3226 SUBST (XEXP (x
, 1), tem
);
3234 /* Otherwise, select our actions depending on our rtx class. */
3235 switch (GET_RTX_CLASS (code
))
3237 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3239 split
= find_split_point (&XEXP (x
, 2), insn
);
3242 /* ... fall through ... */
3246 split
= find_split_point (&XEXP (x
, 1), insn
);
3249 /* ... fall through ... */
3251 /* Some machines have (and (shift ...) ...) insns. If X is not
3252 an AND, but XEXP (X, 0) is, use it as our split point. */
3253 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3254 return &XEXP (x
, 0);
3256 split
= find_split_point (&XEXP (x
, 0), insn
);
3262 /* Otherwise, we don't have a split point. */
3266 /* Throughout X, replace FROM with TO, and return the result.
3267 The result is TO if X is FROM;
3268 otherwise the result is X, but its contents may have been modified.
3269 If they were modified, a record was made in undobuf so that
3270 undo_all will (among other things) return X to its original state.
3272 If the number of changes necessary is too much to record to undo,
3273 the excess changes are not made, so the result is invalid.
3274 The changes already made can still be undone.
3275 undobuf.num_undo is incremented for such changes, so by testing that
3276 the caller can tell whether the result is valid.
3278 `n_occurrences' is incremented each time FROM is replaced.
3280 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3282 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3283 by copying if `n_occurrences' is non-zero. */
3286 subst (x
, from
, to
, in_dest
, unique_copy
)
3287 register rtx x
, from
, to
;
3291 register enum rtx_code code
= GET_CODE (x
);
3292 enum machine_mode op0_mode
= VOIDmode
;
3293 register const char *fmt
;
3294 register int len
, i
;
3297 /* Two expressions are equal if they are identical copies of a shared
3298 RTX or if they are both registers with the same register number
3301 #define COMBINE_RTX_EQUAL_P(X,Y) \
3303 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3304 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3306 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3309 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3312 /* If X and FROM are the same register but different modes, they will
3313 not have been seen as equal above. However, flow.c will make a
3314 LOG_LINKS entry for that case. If we do nothing, we will try to
3315 rerecognize our original insn and, when it succeeds, we will
3316 delete the feeding insn, which is incorrect.
3318 So force this insn not to match in this (rare) case. */
3319 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3320 && REGNO (x
) == REGNO (from
))
3321 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3323 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3324 of which may contain things that can be combined. */
3325 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3328 /* It is possible to have a subexpression appear twice in the insn.
3329 Suppose that FROM is a register that appears within TO.
3330 Then, after that subexpression has been scanned once by `subst',
3331 the second time it is scanned, TO may be found. If we were
3332 to scan TO here, we would find FROM within it and create a
3333 self-referent rtl structure which is completely wrong. */
3334 if (COMBINE_RTX_EQUAL_P (x
, to
))
3337 /* Parallel asm_operands need special attention because all of the
3338 inputs are shared across the arms. Furthermore, unsharing the
3339 rtl results in recognition failures. Failure to handle this case
3340 specially can result in circular rtl.
3342 Solve this by doing a normal pass across the first entry of the
3343 parallel, and only processing the SET_DESTs of the subsequent
3346 if (code
== PARALLEL
3347 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3348 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3350 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3352 /* If this substitution failed, this whole thing fails. */
3353 if (GET_CODE (new) == CLOBBER
3354 && XEXP (new, 0) == const0_rtx
)
3357 SUBST (XVECEXP (x
, 0, 0), new);
3359 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3361 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3363 if (GET_CODE (dest
) != REG
3364 && GET_CODE (dest
) != CC0
3365 && GET_CODE (dest
) != PC
)
3367 new = subst (dest
, from
, to
, 0, unique_copy
);
3369 /* If this substitution failed, this whole thing fails. */
3370 if (GET_CODE (new) == CLOBBER
3371 && XEXP (new, 0) == const0_rtx
)
3374 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3380 len
= GET_RTX_LENGTH (code
);
3381 fmt
= GET_RTX_FORMAT (code
);
3383 /* We don't need to process a SET_DEST that is a register, CC0,
3384 or PC, so set up to skip this common case. All other cases
3385 where we want to suppress replacing something inside a
3386 SET_SRC are handled via the IN_DEST operand. */
3388 && (GET_CODE (SET_DEST (x
)) == REG
3389 || GET_CODE (SET_DEST (x
)) == CC0
3390 || GET_CODE (SET_DEST (x
)) == PC
))
3393 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3396 op0_mode
= GET_MODE (XEXP (x
, 0));
3398 for (i
= 0; i
< len
; i
++)
3403 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3405 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3407 new = (unique_copy
&& n_occurrences
3408 ? copy_rtx (to
) : to
);
3413 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3416 /* If this substitution failed, this whole thing
3418 if (GET_CODE (new) == CLOBBER
3419 && XEXP (new, 0) == const0_rtx
)
3423 SUBST (XVECEXP (x
, i
, j
), new);
3426 else if (fmt
[i
] == 'e')
3428 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3430 /* In general, don't install a subreg involving two
3431 modes not tieable. It can worsen register
3432 allocation, and can even make invalid reload
3433 insns, since the reg inside may need to be copied
3434 from in the outside mode, and that may be invalid
3435 if it is an fp reg copied in integer mode.
3437 We allow two exceptions to this: It is valid if
3438 it is inside another SUBREG and the mode of that
3439 SUBREG and the mode of the inside of TO is
3440 tieable and it is valid if X is a SET that copies
3443 if (GET_CODE (to
) == SUBREG
3444 && ! MODES_TIEABLE_P (GET_MODE (to
),
3445 GET_MODE (SUBREG_REG (to
)))
3446 && ! (code
== SUBREG
3447 && MODES_TIEABLE_P (GET_MODE (x
),
3448 GET_MODE (SUBREG_REG (to
))))
3450 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3453 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3455 #ifdef CLASS_CANNOT_CHANGE_MODE
3457 && GET_CODE (to
) == REG
3458 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3459 && (TEST_HARD_REG_BIT
3460 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3462 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3464 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3467 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3471 /* If we are in a SET_DEST, suppress most cases unless we
3472 have gone inside a MEM, in which case we want to
3473 simplify the address. We assume here that things that
3474 are actually part of the destination have their inner
3475 parts in the first expression. This is true for SUBREG,
3476 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3477 things aside from REG and MEM that should appear in a
3479 new = subst (XEXP (x
, i
), from
, to
,
3481 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3482 || code
== ZERO_EXTRACT
))
3484 && i
== 0), unique_copy
);
3486 /* If we found that we will have to reject this combination,
3487 indicate that by returning the CLOBBER ourselves, rather than
3488 an expression containing it. This will speed things up as
3489 well as prevent accidents where two CLOBBERs are considered
3490 to be equal, thus producing an incorrect simplification. */
3492 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3495 SUBST (XEXP (x
, i
), new);
3500 /* Try to simplify X. If the simplification changed the code, it is likely
3501 that further simplification will help, so loop, but limit the number
3502 of repetitions that will be performed. */
3504 for (i
= 0; i
< 4; i
++)
3506 /* If X is sufficiently simple, don't bother trying to do anything
3508 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3509 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3511 if (GET_CODE (x
) == code
)
3514 code
= GET_CODE (x
);
3516 /* We no longer know the original mode of operand 0 since we
3517 have changed the form of X) */
3518 op0_mode
= VOIDmode
;
3524 /* Simplify X, a piece of RTL. We just operate on the expression at the
3525 outer level; call `subst' to simplify recursively. Return the new
3528 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3529 will be the iteration even if an expression with a code different from
3530 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3533 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3535 enum machine_mode op0_mode
;
3539 enum rtx_code code
= GET_CODE (x
);
3540 enum machine_mode mode
= GET_MODE (x
);
3545 /* If this is a commutative operation, put a constant last and a complex
3546 expression first. We don't need to do this for comparisons here. */
3547 if (GET_RTX_CLASS (code
) == 'c'
3548 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3549 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
3550 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
3551 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3552 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
3553 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
3556 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3557 SUBST (XEXP (x
, 1), temp
);
3560 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3561 sign extension of a PLUS with a constant, reverse the order of the sign
3562 extension and the addition. Note that this not the same as the original
3563 code, but overflow is undefined for signed values. Also note that the
3564 PLUS will have been partially moved "inside" the sign-extension, so that
3565 the first operand of X will really look like:
3566 (ashiftrt (plus (ashift A C4) C5) C4).
3568 (plus (ashiftrt (ashift A C4) C2) C4)
3569 and replace the first operand of X with that expression. Later parts
3570 of this function may simplify the expression further.
3572 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3573 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3574 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3576 We do this to simplify address expressions. */
3578 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3579 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3580 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3581 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3582 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3583 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3584 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3585 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3586 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3587 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3588 XEXP (XEXP (x
, 0), 1))) != 0)
3591 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3592 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3593 INTVAL (XEXP (XEXP (x
, 0), 1)));
3595 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3596 INTVAL (XEXP (XEXP (x
, 0), 1)));
3598 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3601 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3602 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3603 things. Check for cases where both arms are testing the same
3606 Don't do anything if all operands are very simple. */
3608 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3609 || GET_RTX_CLASS (code
) == '<')
3610 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3611 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3612 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3614 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3615 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3616 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3618 || (GET_RTX_CLASS (code
) == '1'
3619 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3620 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3621 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3624 rtx cond
, true_rtx
, false_rtx
;
3626 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3628 /* If everything is a comparison, what we have is highly unlikely
3629 to be simpler, so don't use it. */
3630 && ! (GET_RTX_CLASS (code
) == '<'
3631 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3632 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3634 rtx cop1
= const0_rtx
;
3635 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3637 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3640 /* Simplify the alternative arms; this may collapse the true and
3641 false arms to store-flag values. */
3642 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3643 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3645 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3646 is unlikely to be simpler. */
3647 if (general_operand (true_rtx
, VOIDmode
)
3648 && general_operand (false_rtx
, VOIDmode
))
3650 /* Restarting if we generate a store-flag expression will cause
3651 us to loop. Just drop through in this case. */
3653 /* If the result values are STORE_FLAG_VALUE and zero, we can
3654 just make the comparison operation. */
3655 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3656 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3657 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
)
3658 x
= gen_binary (reverse_condition (cond_code
),
3661 /* Likewise, we can make the negate of a comparison operation
3662 if the result values are - STORE_FLAG_VALUE and zero. */
3663 else if (GET_CODE (true_rtx
) == CONST_INT
3664 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3665 && false_rtx
== const0_rtx
)
3666 x
= gen_unary (NEG
, mode
, mode
,
3667 gen_binary (cond_code
, mode
, cond
, cop1
));
3668 else if (GET_CODE (false_rtx
) == CONST_INT
3669 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3670 && true_rtx
== const0_rtx
)
3671 x
= gen_unary (NEG
, mode
, mode
,
3672 gen_binary (reverse_condition (cond_code
),
3675 return gen_rtx_IF_THEN_ELSE (mode
,
3676 gen_binary (cond_code
, VOIDmode
,
3678 true_rtx
, false_rtx
);
3680 code
= GET_CODE (x
);
3681 op0_mode
= VOIDmode
;
3686 /* Try to fold this expression in case we have constants that weren't
3689 switch (GET_RTX_CLASS (code
))
3692 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3696 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3697 if (cmp_mode
== VOIDmode
)
3699 cmp_mode
= GET_MODE (XEXP (x
, 1));
3700 if (cmp_mode
== VOIDmode
)
3701 cmp_mode
= op0_mode
;
3703 temp
= simplify_relational_operation (code
, cmp_mode
,
3704 XEXP (x
, 0), XEXP (x
, 1));
3706 #ifdef FLOAT_STORE_FLAG_VALUE
3707 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3709 if (temp
== const0_rtx
)
3710 temp
= CONST0_RTX (mode
);
3712 temp
= immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode
), mode
);
3718 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3722 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3723 XEXP (x
, 1), XEXP (x
, 2));
3728 x
= temp
, code
= GET_CODE (temp
);
3730 /* First see if we can apply the inverse distributive law. */
3731 if (code
== PLUS
|| code
== MINUS
3732 || code
== AND
|| code
== IOR
|| code
== XOR
)
3734 x
= apply_distributive_law (x
);
3735 code
= GET_CODE (x
);
3738 /* If CODE is an associative operation not otherwise handled, see if we
3739 can associate some operands. This can win if they are constants or
3740 if they are logically related (i.e. (a & b) & a. */
3741 if ((code
== PLUS
|| code
== MINUS
3742 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3743 || code
== DIV
|| code
== UDIV
3744 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3745 && INTEGRAL_MODE_P (mode
))
3747 if (GET_CODE (XEXP (x
, 0)) == code
)
3749 rtx other
= XEXP (XEXP (x
, 0), 0);
3750 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3751 rtx inner_op1
= XEXP (x
, 1);
3754 /* Make sure we pass the constant operand if any as the second
3755 one if this is a commutative operation. */
3756 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3758 rtx tem
= inner_op0
;
3759 inner_op0
= inner_op1
;
3762 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3763 : code
== DIV
? MULT
3764 : code
== UDIV
? MULT
3766 mode
, inner_op0
, inner_op1
);
3768 /* For commutative operations, try the other pair if that one
3770 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3772 other
= XEXP (XEXP (x
, 0), 1);
3773 inner
= simplify_binary_operation (code
, mode
,
3774 XEXP (XEXP (x
, 0), 0),
3779 return gen_binary (code
, mode
, other
, inner
);
3783 /* A little bit of algebraic simplification here. */
3787 /* Ensure that our address has any ASHIFTs converted to MULT in case
3788 address-recognizing predicates are called later. */
3789 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3790 SUBST (XEXP (x
, 0), temp
);
3794 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3795 is paradoxical. If we can't do that safely, then it becomes
3796 something nonsensical so that this combination won't take place. */
3798 if (GET_CODE (SUBREG_REG (x
)) == MEM
3799 && (GET_MODE_SIZE (mode
)
3800 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3802 rtx inner
= SUBREG_REG (x
);
3803 int endian_offset
= 0;
3804 /* Don't change the mode of the MEM
3805 if that would change the meaning of the address. */
3806 if (MEM_VOLATILE_P (SUBREG_REG (x
))
3807 || mode_dependent_address_p (XEXP (inner
, 0)))
3808 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3810 if (BYTES_BIG_ENDIAN
)
3812 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3813 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
3814 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
3815 endian_offset
-= (UNITS_PER_WORD
3816 - GET_MODE_SIZE (GET_MODE (inner
)));
3818 /* Note if the plus_constant doesn't make a valid address
3819 then this combination won't be accepted. */
3820 x
= gen_rtx_MEM (mode
,
3821 plus_constant (XEXP (inner
, 0),
3822 (SUBREG_WORD (x
) * UNITS_PER_WORD
3824 MEM_COPY_ATTRIBUTES (x
, inner
);
3828 /* If we are in a SET_DEST, these other cases can't apply. */
3832 /* Changing mode twice with SUBREG => just change it once,
3833 or not at all if changing back to starting mode. */
3834 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
3836 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
3837 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
3838 return SUBREG_REG (SUBREG_REG (x
));
3840 SUBST_INT (SUBREG_WORD (x
),
3841 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
3842 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
3845 /* SUBREG of a hard register => just change the register number
3846 and/or mode. If the hard register is not valid in that mode,
3847 suppress this combination. If the hard register is the stack,
3848 frame, or argument pointer, leave this as a SUBREG. */
3850 if (GET_CODE (SUBREG_REG (x
)) == REG
3851 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
3852 && REGNO (SUBREG_REG (x
)) != FRAME_POINTER_REGNUM
3853 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3854 && REGNO (SUBREG_REG (x
)) != HARD_FRAME_POINTER_REGNUM
3856 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3857 && REGNO (SUBREG_REG (x
)) != ARG_POINTER_REGNUM
3859 && REGNO (SUBREG_REG (x
)) != STACK_POINTER_REGNUM
)
3861 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
3863 return gen_rtx_REG (mode
,
3864 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
3866 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3869 /* For a constant, try to pick up the part we want. Handle a full
3870 word and low-order part. Only do this if we are narrowing
3871 the constant; if it is being widened, we have no idea what
3872 the extra bits will have been set to. */
3874 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
3875 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
3876 && GET_MODE_SIZE (op0_mode
) > UNITS_PER_WORD
3877 && GET_MODE_CLASS (mode
) == MODE_INT
)
3879 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
3885 /* If we want a subreg of a constant, at offset 0,
3886 take the low bits. On a little-endian machine, that's
3887 always valid. On a big-endian machine, it's valid
3888 only if the constant's mode fits in one word. Note that we
3889 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3890 if (CONSTANT_P (SUBREG_REG (x
))
3891 && ((GET_MODE_SIZE (op0_mode
) <= UNITS_PER_WORD
3892 || ! WORDS_BIG_ENDIAN
)
3893 ? SUBREG_WORD (x
) == 0
3895 == ((GET_MODE_SIZE (op0_mode
)
3896 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
3898 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (op0_mode
)
3899 && (! WORDS_BIG_ENDIAN
3900 || GET_MODE_BITSIZE (op0_mode
) <= BITS_PER_WORD
))
3901 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3903 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3904 since we are saying that the high bits don't matter. */
3905 if (CONSTANT_P (SUBREG_REG (x
)) && GET_MODE (SUBREG_REG (x
)) == VOIDmode
3906 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (op0_mode
))
3908 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
3909 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
3910 return operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
), 0, mode
);
3911 return SUBREG_REG (x
);
3914 /* Note that we cannot do any narrowing for non-constants since
3915 we might have been counting on using the fact that some bits were
3916 zero. We now do this in the SET. */
3921 /* (not (plus X -1)) can become (neg X). */
3922 if (GET_CODE (XEXP (x
, 0)) == PLUS
3923 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3924 return gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
3926 /* Similarly, (not (neg X)) is (plus X -1). */
3927 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3928 return gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3931 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3932 if (GET_CODE (XEXP (x
, 0)) == XOR
3933 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3934 && (temp
= simplify_unary_operation (NOT
, mode
,
3935 XEXP (XEXP (x
, 0), 1),
3937 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3939 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3940 other than 1, but that is not valid. We could do a similar
3941 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3942 but this doesn't seem common enough to bother with. */
3943 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3944 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3945 return gen_rtx_ROTATE (mode
, gen_unary (NOT
, mode
, mode
, const1_rtx
),
3946 XEXP (XEXP (x
, 0), 1));
3948 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3949 && subreg_lowpart_p (XEXP (x
, 0))
3950 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3951 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3952 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3953 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3955 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3957 x
= gen_rtx_ROTATE (inner_mode
,
3958 gen_unary (NOT
, inner_mode
, inner_mode
,
3960 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3961 return gen_lowpart_for_combine (mode
, x
);
3964 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3965 reversing the comparison code if valid. */
3966 if (STORE_FLAG_VALUE
== -1
3967 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3968 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3969 XEXP (XEXP (x
, 0), 1))))
3972 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3973 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3974 perform the above simplification. */
3976 if (STORE_FLAG_VALUE
== -1
3977 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3978 && XEXP (x
, 1) == const1_rtx
3979 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3980 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3981 return gen_rtx_combine (GE
, mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3983 /* Apply De Morgan's laws to reduce number of patterns for machines
3984 with negating logical insns (and-not, nand, etc.). If result has
3985 only one NOT, put it first, since that is how the patterns are
3988 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3990 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3991 enum machine_mode op_mode
;
3993 op_mode
= GET_MODE (in1
);
3994 in1
= gen_unary (NOT
, op_mode
, op_mode
, in1
);
3996 op_mode
= GET_MODE (in2
);
3997 if (op_mode
== VOIDmode
)
3999 in2
= gen_unary (NOT
, op_mode
, op_mode
, in2
);
4001 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4004 in2
= in1
; in1
= tem
;
4007 return gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4013 /* (neg (plus X 1)) can become (not X). */
4014 if (GET_CODE (XEXP (x
, 0)) == PLUS
4015 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
4016 return gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
4018 /* Similarly, (neg (not X)) is (plus X 1). */
4019 if (GET_CODE (XEXP (x
, 0)) == NOT
)
4020 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
4022 /* (neg (minus X Y)) can become (minus Y X). */
4023 if (GET_CODE (XEXP (x
, 0)) == MINUS
4024 && (! FLOAT_MODE_P (mode
)
4025 /* x-y != -(y-x) with IEEE floating point. */
4026 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4027 || flag_unsafe_math_optimizations
))
4028 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
4029 XEXP (XEXP (x
, 0), 0));
4031 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4032 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
4033 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4034 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
4036 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4037 if we can then eliminate the NEG (e.g.,
4038 if the operand is a constant). */
4040 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
4042 temp
= simplify_unary_operation (NEG
, mode
,
4043 XEXP (XEXP (x
, 0), 0), mode
);
4046 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
4051 temp
= expand_compound_operation (XEXP (x
, 0));
4053 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4054 replaced by (lshiftrt X C). This will convert
4055 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4057 if (GET_CODE (temp
) == ASHIFTRT
4058 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4059 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4060 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4061 INTVAL (XEXP (temp
, 1)));
4063 /* If X has only a single bit that might be nonzero, say, bit I, convert
4064 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4065 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4066 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4067 or a SUBREG of one since we'd be making the expression more
4068 complex if it was just a register. */
4070 if (GET_CODE (temp
) != REG
4071 && ! (GET_CODE (temp
) == SUBREG
4072 && GET_CODE (SUBREG_REG (temp
)) == REG
)
4073 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4075 rtx temp1
= simplify_shift_const
4076 (NULL_RTX
, ASHIFTRT
, mode
,
4077 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4078 GET_MODE_BITSIZE (mode
) - 1 - i
),
4079 GET_MODE_BITSIZE (mode
) - 1 - i
);
4081 /* If all we did was surround TEMP with the two shifts, we
4082 haven't improved anything, so don't use it. Otherwise,
4083 we are better off with TEMP1. */
4084 if (GET_CODE (temp1
) != ASHIFTRT
4085 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4086 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4092 /* We can't handle truncation to a partial integer mode here
4093 because we don't know the real bitsize of the partial
4095 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4098 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4099 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4100 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4102 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4103 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4105 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4106 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4107 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4108 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4109 return XEXP (XEXP (x
, 0), 0);
4111 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4112 (OP:SI foo:SI) if OP is NEG or ABS. */
4113 if ((GET_CODE (XEXP (x
, 0)) == ABS
4114 || GET_CODE (XEXP (x
, 0)) == NEG
)
4115 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4116 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4117 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4118 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
4119 XEXP (XEXP (XEXP (x
, 0), 0), 0));
4121 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4123 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4124 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4125 && subreg_lowpart_p (XEXP (x
, 0)))
4126 return SUBREG_REG (XEXP (x
, 0));
4128 /* If we know that the value is already truncated, we can
4129 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4130 is nonzero for the corresponding modes. But don't do this
4131 for an (LSHIFTRT (MULT ...)) since this will cause problems
4132 with the umulXi3_highpart patterns. */
4133 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4134 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4135 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4136 >= GET_MODE_BITSIZE (mode
) + 1
4137 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4138 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4139 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4141 /* A truncate of a comparison can be replaced with a subreg if
4142 STORE_FLAG_VALUE permits. This is like the previous test,
4143 but it works even if the comparison is done in a mode larger
4144 than HOST_BITS_PER_WIDE_INT. */
4145 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4146 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4147 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4148 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4150 /* Similarly, a truncate of a register whose value is a
4151 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4153 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4154 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4155 && (temp
= get_last_value (XEXP (x
, 0)))
4156 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4157 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4161 case FLOAT_TRUNCATE
:
4162 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4163 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4164 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4165 return XEXP (XEXP (x
, 0), 0);
4167 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4168 (OP:SF foo:SF) if OP is NEG or ABS. */
4169 if ((GET_CODE (XEXP (x
, 0)) == ABS
4170 || GET_CODE (XEXP (x
, 0)) == NEG
)
4171 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4172 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4173 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
4174 XEXP (XEXP (XEXP (x
, 0), 0), 0));
4176 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4177 is (float_truncate:SF x). */
4178 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4179 && subreg_lowpart_p (XEXP (x
, 0))
4180 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4181 return SUBREG_REG (XEXP (x
, 0));
4186 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4187 using cc0, in which case we want to leave it as a COMPARE
4188 so we can distinguish it from a register-register-copy. */
4189 if (XEXP (x
, 1) == const0_rtx
)
4192 /* In IEEE floating point, x-0 is not the same as x. */
4193 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4194 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
4195 || flag_unsafe_math_optimizations
)
4196 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4202 /* (const (const X)) can become (const X). Do it this way rather than
4203 returning the inner CONST since CONST can be shared with a
4205 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4206 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4211 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4212 can add in an offset. find_split_point will split this address up
4213 again if it doesn't match. */
4214 if (GET_CODE (XEXP (x
, 0)) == HIGH
4215 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4221 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4222 outermost. That's because that's the way indexed addresses are
4223 supposed to appear. This code used to check many more cases, but
4224 they are now checked elsewhere. */
4225 if (GET_CODE (XEXP (x
, 0)) == PLUS
4226 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4227 return gen_binary (PLUS
, mode
,
4228 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4230 XEXP (XEXP (x
, 0), 1));
4232 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4233 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4234 bit-field and can be replaced by either a sign_extend or a
4235 sign_extract. The `and' may be a zero_extend and the two
4236 <c>, -<c> constants may be reversed. */
4237 if (GET_CODE (XEXP (x
, 0)) == XOR
4238 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4239 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4240 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4241 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4242 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4243 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4244 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4245 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4246 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4247 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4248 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4249 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4250 == (unsigned int) i
+ 1))))
4251 return simplify_shift_const
4252 (NULL_RTX
, ASHIFTRT
, mode
,
4253 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4254 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4255 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4256 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4258 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4259 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4260 is 1. This produces better code than the alternative immediately
4262 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4263 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4264 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4265 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4266 XEXP (XEXP (x
, 0), 0),
4267 XEXP (XEXP (x
, 0), 1))))
4269 gen_unary (NEG
, mode
, mode
, reversed
);
4271 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4272 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4273 the bitsize of the mode - 1. This allows simplification of
4274 "a = (b & 8) == 0;" */
4275 if (XEXP (x
, 1) == constm1_rtx
4276 && GET_CODE (XEXP (x
, 0)) != REG
4277 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4278 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4279 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4280 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4281 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4282 gen_rtx_combine (XOR
, mode
,
4283 XEXP (x
, 0), const1_rtx
),
4284 GET_MODE_BITSIZE (mode
) - 1),
4285 GET_MODE_BITSIZE (mode
) - 1);
4287 /* If we are adding two things that have no bits in common, convert
4288 the addition into an IOR. This will often be further simplified,
4289 for example in cases like ((a & 1) + (a & 2)), which can
4292 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4293 && (nonzero_bits (XEXP (x
, 0), mode
)
4294 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4296 /* Try to simplify the expression further. */
4297 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4298 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4300 /* If we could, great. If not, do not go ahead with the IOR
4301 replacement, since PLUS appears in many special purpose
4302 address arithmetic instructions. */
4303 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4309 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4310 by reversing the comparison code if valid. */
4311 if (STORE_FLAG_VALUE
== 1
4312 && XEXP (x
, 0) == const1_rtx
4313 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4314 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4315 XEXP (XEXP (x
, 1), 0),
4316 XEXP (XEXP (x
, 1), 1))))
4319 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4320 (and <foo> (const_int pow2-1)) */
4321 if (GET_CODE (XEXP (x
, 1)) == AND
4322 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4323 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4324 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4325 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4326 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4328 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4330 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4331 return gen_binary (MINUS
, mode
,
4332 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4333 XEXP (XEXP (x
, 1), 0)),
4334 XEXP (XEXP (x
, 1), 1));
4338 /* If we have (mult (plus A B) C), apply the distributive law and then
4339 the inverse distributive law to see if things simplify. This
4340 occurs mostly in addresses, often when unrolling loops. */
4342 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4344 x
= apply_distributive_law
4345 (gen_binary (PLUS
, mode
,
4346 gen_binary (MULT
, mode
,
4347 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4348 gen_binary (MULT
, mode
,
4349 XEXP (XEXP (x
, 0), 1),
4350 copy_rtx (XEXP (x
, 1)))));
4352 if (GET_CODE (x
) != MULT
)
4358 /* If this is a divide by a power of two, treat it as a shift if
4359 its first operand is a shift. */
4360 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4361 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4362 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4363 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4364 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4365 || GET_CODE (XEXP (x
, 0)) == ROTATE
4366 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4367 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4371 case GT
: case GTU
: case GE
: case GEU
:
4372 case LT
: case LTU
: case LE
: case LEU
:
4373 case UNEQ
: case LTGT
:
4374 case UNGT
: case UNGE
:
4375 case UNLT
: case UNLE
:
4376 case UNORDERED
: case ORDERED
:
4377 /* If the first operand is a condition code, we can't do anything
4379 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4380 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4382 && XEXP (x
, 0) != cc0_rtx
4386 rtx op0
= XEXP (x
, 0);
4387 rtx op1
= XEXP (x
, 1);
4388 enum rtx_code new_code
;
4390 if (GET_CODE (op0
) == COMPARE
)
4391 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4393 /* Simplify our comparison, if possible. */
4394 new_code
= simplify_comparison (code
, &op0
, &op1
);
4396 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4397 if only the low-order bit is possibly nonzero in X (such as when
4398 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4399 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4400 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4403 Remove any ZERO_EXTRACT we made when thinking this was a
4404 comparison. It may now be simpler to use, e.g., an AND. If a
4405 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4406 the call to make_compound_operation in the SET case. */
4408 if (STORE_FLAG_VALUE
== 1
4409 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4410 && op1
== const0_rtx
4411 && mode
== GET_MODE (op0
)
4412 && nonzero_bits (op0
, mode
) == 1)
4413 return gen_lowpart_for_combine (mode
,
4414 expand_compound_operation (op0
));
4416 else if (STORE_FLAG_VALUE
== 1
4417 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4418 && op1
== const0_rtx
4419 && mode
== GET_MODE (op0
)
4420 && (num_sign_bit_copies (op0
, mode
)
4421 == GET_MODE_BITSIZE (mode
)))
4423 op0
= expand_compound_operation (op0
);
4424 return gen_unary (NEG
, mode
, mode
,
4425 gen_lowpart_for_combine (mode
, op0
));
4428 else if (STORE_FLAG_VALUE
== 1
4429 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4430 && op1
== const0_rtx
4431 && mode
== GET_MODE (op0
)
4432 && nonzero_bits (op0
, mode
) == 1)
4434 op0
= expand_compound_operation (op0
);
4435 return gen_binary (XOR
, mode
,
4436 gen_lowpart_for_combine (mode
, op0
),
4440 else if (STORE_FLAG_VALUE
== 1
4441 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4442 && op1
== const0_rtx
4443 && mode
== GET_MODE (op0
)
4444 && (num_sign_bit_copies (op0
, mode
)
4445 == GET_MODE_BITSIZE (mode
)))
4447 op0
= expand_compound_operation (op0
);
4448 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4451 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4453 if (STORE_FLAG_VALUE
== -1
4454 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4455 && op1
== const0_rtx
4456 && (num_sign_bit_copies (op0
, mode
)
4457 == GET_MODE_BITSIZE (mode
)))
4458 return gen_lowpart_for_combine (mode
,
4459 expand_compound_operation (op0
));
4461 else if (STORE_FLAG_VALUE
== -1
4462 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4463 && op1
== const0_rtx
4464 && mode
== GET_MODE (op0
)
4465 && nonzero_bits (op0
, mode
) == 1)
4467 op0
= expand_compound_operation (op0
);
4468 return gen_unary (NEG
, mode
, mode
,
4469 gen_lowpart_for_combine (mode
, op0
));
4472 else if (STORE_FLAG_VALUE
== -1
4473 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4474 && op1
== const0_rtx
4475 && mode
== GET_MODE (op0
)
4476 && (num_sign_bit_copies (op0
, mode
)
4477 == GET_MODE_BITSIZE (mode
)))
4479 op0
= expand_compound_operation (op0
);
4480 return gen_unary (NOT
, mode
, mode
,
4481 gen_lowpart_for_combine (mode
, op0
));
4484 /* If X is 0/1, (eq X 0) is X-1. */
4485 else if (STORE_FLAG_VALUE
== -1
4486 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4487 && op1
== const0_rtx
4488 && mode
== GET_MODE (op0
)
4489 && nonzero_bits (op0
, mode
) == 1)
4491 op0
= expand_compound_operation (op0
);
4492 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4495 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4496 one bit that might be nonzero, we can convert (ne x 0) to
4497 (ashift x c) where C puts the bit in the sign bit. Remove any
4498 AND with STORE_FLAG_VALUE when we are done, since we are only
4499 going to test the sign bit. */
4500 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4501 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4502 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4503 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4504 && op1
== const0_rtx
4505 && mode
== GET_MODE (op0
)
4506 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4508 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4509 expand_compound_operation (op0
),
4510 GET_MODE_BITSIZE (mode
) - 1 - i
);
4511 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4517 /* If the code changed, return a whole new comparison. */
4518 if (new_code
!= code
)
4519 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
4521 /* Otherwise, keep this operation, but maybe change its operands.
4522 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4523 SUBST (XEXP (x
, 0), op0
);
4524 SUBST (XEXP (x
, 1), op1
);
4529 return simplify_if_then_else (x
);
4535 /* If we are processing SET_DEST, we are done. */
4539 return expand_compound_operation (x
);
4542 return simplify_set (x
);
4547 return simplify_logical (x
, last
);
4550 /* (abs (neg <foo>)) -> (abs <foo>) */
4551 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4552 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4554 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4556 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4559 /* If operand is something known to be positive, ignore the ABS. */
4560 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4561 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4562 <= HOST_BITS_PER_WIDE_INT
)
4563 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4564 & ((HOST_WIDE_INT
) 1
4565 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4569 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4570 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4571 return gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
4576 /* (ffs (*_extend <X>)) = (ffs <X>) */
4577 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4578 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4579 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4583 /* (float (sign_extend <X>)) = (float <X>). */
4584 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4585 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4593 /* If this is a shift by a constant amount, simplify it. */
4594 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4595 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4596 INTVAL (XEXP (x
, 1)));
4598 #ifdef SHIFT_COUNT_TRUNCATED
4599 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4601 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4603 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4612 rtx op0
= XEXP (x
, 0);
4613 rtx op1
= XEXP (x
, 1);
4616 if (GET_CODE (op1
) != PARALLEL
)
4618 len
= XVECLEN (op1
, 0);
4620 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4621 && GET_CODE (op0
) == VEC_CONCAT
)
4623 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4625 /* Try to find the element in the VEC_CONCAT. */
4628 if (GET_MODE (op0
) == GET_MODE (x
))
4630 if (GET_CODE (op0
) == VEC_CONCAT
)
4632 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4633 if (op0_size
< offset
)
4634 op0
= XEXP (op0
, 0);
4638 op0
= XEXP (op0
, 1);
4656 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4659 simplify_if_then_else (x
)
4662 enum machine_mode mode
= GET_MODE (x
);
4663 rtx cond
= XEXP (x
, 0);
4664 rtx true_rtx
= XEXP (x
, 1);
4665 rtx false_rtx
= XEXP (x
, 2);
4666 enum rtx_code true_code
= GET_CODE (cond
);
4667 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4670 enum rtx_code false_code
;
4673 /* Simplify storing of the truth value. */
4674 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4675 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4677 /* Also when the truth value has to be reversed. */
4679 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4680 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4684 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4685 in it is being compared against certain values. Get the true and false
4686 comparisons and see if that says anything about the value of each arm. */
4689 && ((false_code
= combine_reversed_comparison_code (cond
))
4691 && GET_CODE (XEXP (cond
, 0)) == REG
)
4694 rtx from
= XEXP (cond
, 0);
4695 rtx true_val
= XEXP (cond
, 1);
4696 rtx false_val
= true_val
;
4699 /* If FALSE_CODE is EQ, swap the codes and arms. */
4701 if (false_code
== EQ
)
4703 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4704 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4707 /* If we are comparing against zero and the expression being tested has
4708 only a single bit that might be nonzero, that is its value when it is
4709 not equal to zero. Similarly if it is known to be -1 or 0. */
4711 if (true_code
== EQ
&& true_val
== const0_rtx
4712 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4713 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4714 else if (true_code
== EQ
&& true_val
== const0_rtx
4715 && (num_sign_bit_copies (from
, GET_MODE (from
))
4716 == GET_MODE_BITSIZE (GET_MODE (from
))))
4717 false_code
= EQ
, false_val
= constm1_rtx
;
4719 /* Now simplify an arm if we know the value of the register in the
4720 branch and it is used in the arm. Be careful due to the potential
4721 of locally-shared RTL. */
4723 if (reg_mentioned_p (from
, true_rtx
))
4724 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4726 pc_rtx
, pc_rtx
, 0, 0);
4727 if (reg_mentioned_p (from
, false_rtx
))
4728 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4730 pc_rtx
, pc_rtx
, 0, 0);
4732 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4733 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4735 true_rtx
= XEXP (x
, 1);
4736 false_rtx
= XEXP (x
, 2);
4737 true_code
= GET_CODE (cond
);
4740 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4741 reversed, do so to avoid needing two sets of patterns for
4742 subtract-and-branch insns. Similarly if we have a constant in the true
4743 arm, the false arm is the same as the first operand of the comparison, or
4744 the false arm is more complicated than the true arm. */
4747 && combine_reversed_comparison_code (cond
) != UNKNOWN
4748 && (true_rtx
== pc_rtx
4749 || (CONSTANT_P (true_rtx
)
4750 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4751 || true_rtx
== const0_rtx
4752 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4753 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4754 || (GET_CODE (true_rtx
) == SUBREG
4755 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4756 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4757 || reg_mentioned_p (true_rtx
, false_rtx
)
4758 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4760 true_code
= reversed_comparison_code (cond
, NULL
);
4762 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4765 SUBST (XEXP (x
, 1), false_rtx
);
4766 SUBST (XEXP (x
, 2), true_rtx
);
4768 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4771 /* It is possible that the conditional has been simplified out. */
4772 true_code
= GET_CODE (cond
);
4773 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4776 /* If the two arms are identical, we don't need the comparison. */
4778 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4781 /* Convert a == b ? b : a to "a". */
4782 if (true_code
== EQ
&& ! side_effects_p (cond
)
4783 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4784 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4785 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4787 else if (true_code
== NE
&& ! side_effects_p (cond
)
4788 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4789 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4790 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4793 /* Look for cases where we have (abs x) or (neg (abs X)). */
4795 if (GET_MODE_CLASS (mode
) == MODE_INT
4796 && GET_CODE (false_rtx
) == NEG
4797 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4799 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4800 && ! side_effects_p (true_rtx
))
4805 return gen_unary (ABS
, mode
, mode
, true_rtx
);
4808 return gen_unary (NEG
, mode
, mode
,
4809 gen_unary (ABS
, mode
, mode
, true_rtx
));
4814 /* Look for MIN or MAX. */
4816 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4818 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4819 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4820 && ! side_effects_p (cond
))
4825 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4828 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4831 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4834 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4839 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4840 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4841 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4842 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4843 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4844 neither 1 or -1, but it isn't worth checking for. */
4846 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4847 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4849 rtx t
= make_compound_operation (true_rtx
, SET
);
4850 rtx f
= make_compound_operation (false_rtx
, SET
);
4851 rtx cond_op0
= XEXP (cond
, 0);
4852 rtx cond_op1
= XEXP (cond
, 1);
4853 enum rtx_code op
= NIL
, extend_op
= NIL
;
4854 enum machine_mode m
= mode
;
4855 rtx z
= 0, c1
= NULL_RTX
;
4857 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4858 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4859 || GET_CODE (t
) == ASHIFT
4860 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4861 && rtx_equal_p (XEXP (t
, 0), f
))
4862 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4864 /* If an identity-zero op is commutative, check whether there
4865 would be a match if we swapped the operands. */
4866 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4867 || GET_CODE (t
) == XOR
)
4868 && rtx_equal_p (XEXP (t
, 1), f
))
4869 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4870 else if (GET_CODE (t
) == SIGN_EXTEND
4871 && (GET_CODE (XEXP (t
, 0)) == PLUS
4872 || GET_CODE (XEXP (t
, 0)) == MINUS
4873 || GET_CODE (XEXP (t
, 0)) == IOR
4874 || GET_CODE (XEXP (t
, 0)) == XOR
4875 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4876 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4877 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4878 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4879 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4880 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4881 && (num_sign_bit_copies (f
, GET_MODE (f
))
4882 > (GET_MODE_BITSIZE (mode
)
4883 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4885 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4886 extend_op
= SIGN_EXTEND
;
4887 m
= GET_MODE (XEXP (t
, 0));
4889 else if (GET_CODE (t
) == SIGN_EXTEND
4890 && (GET_CODE (XEXP (t
, 0)) == PLUS
4891 || GET_CODE (XEXP (t
, 0)) == IOR
4892 || GET_CODE (XEXP (t
, 0)) == XOR
)
4893 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4894 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4895 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4896 && (num_sign_bit_copies (f
, GET_MODE (f
))
4897 > (GET_MODE_BITSIZE (mode
)
4898 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4900 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4901 extend_op
= SIGN_EXTEND
;
4902 m
= GET_MODE (XEXP (t
, 0));
4904 else if (GET_CODE (t
) == ZERO_EXTEND
4905 && (GET_CODE (XEXP (t
, 0)) == PLUS
4906 || GET_CODE (XEXP (t
, 0)) == MINUS
4907 || GET_CODE (XEXP (t
, 0)) == IOR
4908 || GET_CODE (XEXP (t
, 0)) == XOR
4909 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4910 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4911 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4912 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4913 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4914 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4915 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4916 && ((nonzero_bits (f
, GET_MODE (f
))
4917 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4920 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4921 extend_op
= ZERO_EXTEND
;
4922 m
= GET_MODE (XEXP (t
, 0));
4924 else if (GET_CODE (t
) == ZERO_EXTEND
4925 && (GET_CODE (XEXP (t
, 0)) == PLUS
4926 || GET_CODE (XEXP (t
, 0)) == IOR
4927 || GET_CODE (XEXP (t
, 0)) == XOR
)
4928 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4929 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4930 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4931 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4932 && ((nonzero_bits (f
, GET_MODE (f
))
4933 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4936 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4937 extend_op
= ZERO_EXTEND
;
4938 m
= GET_MODE (XEXP (t
, 0));
4943 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4944 pc_rtx
, pc_rtx
, 0, 0);
4945 temp
= gen_binary (MULT
, m
, temp
,
4946 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4947 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4948 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4950 if (extend_op
!= NIL
)
4951 temp
= gen_unary (extend_op
, mode
, m
, temp
);
4957 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4958 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4959 negation of a single bit, we can convert this operation to a shift. We
4960 can actually do this more generally, but it doesn't seem worth it. */
4962 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4963 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4964 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4965 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4966 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4967 == GET_MODE_BITSIZE (mode
))
4968 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4970 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4971 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4976 /* Simplify X, a SET expression. Return the new expression. */
4982 rtx src
= SET_SRC (x
);
4983 rtx dest
= SET_DEST (x
);
4984 enum machine_mode mode
4985 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4989 /* (set (pc) (return)) gets written as (return). */
4990 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4993 /* Now that we know for sure which bits of SRC we are using, see if we can
4994 simplify the expression for the object knowing that we only need the
4997 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4999 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5000 SUBST (SET_SRC (x
), src
);
5003 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5004 the comparison result and try to simplify it unless we already have used
5005 undobuf.other_insn. */
5006 if ((GET_CODE (src
) == COMPARE
5011 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5012 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5013 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
5014 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5016 enum rtx_code old_code
= GET_CODE (*cc_use
);
5017 enum rtx_code new_code
;
5019 int other_changed
= 0;
5020 enum machine_mode compare_mode
= GET_MODE (dest
);
5022 if (GET_CODE (src
) == COMPARE
)
5023 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5025 op0
= src
, op1
= const0_rtx
;
5027 /* Simplify our comparison, if possible. */
5028 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5030 #ifdef EXTRA_CC_MODES
5031 /* If this machine has CC modes other than CCmode, check to see if we
5032 need to use a different CC mode here. */
5033 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5034 #endif /* EXTRA_CC_MODES */
5036 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5037 /* If the mode changed, we have to change SET_DEST, the mode in the
5038 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5039 a hard register, just build new versions with the proper mode. If it
5040 is a pseudo, we lose unless it is only time we set the pseudo, in
5041 which case we can safely change its mode. */
5042 if (compare_mode
!= GET_MODE (dest
))
5044 unsigned int regno
= REGNO (dest
);
5045 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5047 if (regno
< FIRST_PSEUDO_REGISTER
5048 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5050 if (regno
>= FIRST_PSEUDO_REGISTER
)
5051 SUBST (regno_reg_rtx
[regno
], new_dest
);
5053 SUBST (SET_DEST (x
), new_dest
);
5054 SUBST (XEXP (*cc_use
, 0), new_dest
);
5062 /* If the code changed, we have to build a new comparison in
5063 undobuf.other_insn. */
5064 if (new_code
!= old_code
)
5066 unsigned HOST_WIDE_INT mask
;
5068 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
5071 /* If the only change we made was to change an EQ into an NE or
5072 vice versa, OP0 has only one bit that might be nonzero, and OP1
5073 is zero, check if changing the user of the condition code will
5074 produce a valid insn. If it won't, we can keep the original code
5075 in that insn by surrounding our operation with an XOR. */
5077 if (((old_code
== NE
&& new_code
== EQ
)
5078 || (old_code
== EQ
&& new_code
== NE
))
5079 && ! other_changed
&& op1
== const0_rtx
5080 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5081 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5083 rtx pat
= PATTERN (other_insn
), note
= 0;
5085 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5086 && ! check_asm_operands (pat
)))
5088 PUT_CODE (*cc_use
, old_code
);
5091 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5099 undobuf
.other_insn
= other_insn
;
5102 /* If we are now comparing against zero, change our source if
5103 needed. If we do not use cc0, we always have a COMPARE. */
5104 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5106 SUBST (SET_SRC (x
), op0
);
5112 /* Otherwise, if we didn't previously have a COMPARE in the
5113 correct mode, we need one. */
5114 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5117 gen_rtx_combine (COMPARE
, compare_mode
, op0
, op1
));
5122 /* Otherwise, update the COMPARE if needed. */
5123 SUBST (XEXP (src
, 0), op0
);
5124 SUBST (XEXP (src
, 1), op1
);
5129 /* Get SET_SRC in a form where we have placed back any
5130 compound expressions. Then do the checks below. */
5131 src
= make_compound_operation (src
, SET
);
5132 SUBST (SET_SRC (x
), src
);
5135 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5136 and X being a REG or (subreg (reg)), we may be able to convert this to
5137 (set (subreg:m2 x) (op)).
5139 We can always do this if M1 is narrower than M2 because that means that
5140 we only care about the low bits of the result.
5142 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5143 perform a narrower operation than requested since the high-order bits will
5144 be undefined. On machine where it is defined, this transformation is safe
5145 as long as M1 and M2 have the same number of words. */
5147 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5148 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5149 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5151 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5152 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5153 #ifndef WORD_REGISTER_OPERATIONS
5154 && (GET_MODE_SIZE (GET_MODE (src
))
5155 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5157 #ifdef CLASS_CANNOT_CHANGE_MODE
5158 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5159 && (TEST_HARD_REG_BIT
5160 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5162 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5163 GET_MODE (SUBREG_REG (src
))))
5165 && (GET_CODE (dest
) == REG
5166 || (GET_CODE (dest
) == SUBREG
5167 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5169 SUBST (SET_DEST (x
),
5170 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5172 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5174 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5177 #ifdef LOAD_EXTEND_OP
5178 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5179 would require a paradoxical subreg. Replace the subreg with a
5180 zero_extend to avoid the reload that would otherwise be required. */
5182 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5183 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5184 && SUBREG_WORD (src
) == 0
5185 && (GET_MODE_SIZE (GET_MODE (src
))
5186 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5187 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5190 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5191 GET_MODE (src
), XEXP (src
, 0)));
5197 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5198 are comparing an item known to be 0 or -1 against 0, use a logical
5199 operation instead. Check for one of the arms being an IOR of the other
5200 arm with some value. We compute three terms to be IOR'ed together. In
5201 practice, at most two will be nonzero. Then we do the IOR's. */
5203 if (GET_CODE (dest
) != PC
5204 && GET_CODE (src
) == IF_THEN_ELSE
5205 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5206 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5207 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5208 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5209 #ifdef HAVE_conditional_move
5210 && ! can_conditionally_move_p (GET_MODE (src
))
5212 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5213 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5214 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5215 && ! side_effects_p (src
))
5217 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5218 ? XEXP (src
, 1) : XEXP (src
, 2));
5219 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5220 ? XEXP (src
, 2) : XEXP (src
, 1));
5221 rtx term1
= const0_rtx
, term2
, term3
;
5223 if (GET_CODE (true_rtx
) == IOR
5224 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5225 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 1), false_rtx
= const0_rtx
;
5226 else if (GET_CODE (true_rtx
) == IOR
5227 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5228 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 0), false_rtx
= const0_rtx
;
5229 else if (GET_CODE (false_rtx
) == IOR
5230 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5231 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 1), true_rtx
= const0_rtx
;
5232 else if (GET_CODE (false_rtx
) == IOR
5233 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5234 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 0), true_rtx
= const0_rtx
;
5236 term2
= gen_binary (AND
, GET_MODE (src
),
5237 XEXP (XEXP (src
, 0), 0), true_rtx
);
5238 term3
= gen_binary (AND
, GET_MODE (src
),
5239 gen_unary (NOT
, GET_MODE (src
), GET_MODE (src
),
5240 XEXP (XEXP (src
, 0), 0)),
5244 gen_binary (IOR
, GET_MODE (src
),
5245 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5251 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5252 whole thing fail. */
5253 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5255 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5258 /* Convert this into a field assignment operation, if possible. */
5259 return make_field_assignment (x
);
5262 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5263 result. LAST is nonzero if this is the last retry. */
5266 simplify_logical (x
, last
)
5270 enum machine_mode mode
= GET_MODE (x
);
5271 rtx op0
= XEXP (x
, 0);
5272 rtx op1
= XEXP (x
, 1);
5275 switch (GET_CODE (x
))
5278 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5279 insn (and may simplify more). */
5280 if (GET_CODE (op0
) == XOR
5281 && rtx_equal_p (XEXP (op0
, 0), op1
)
5282 && ! side_effects_p (op1
))
5283 x
= gen_binary (AND
, mode
,
5284 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)), op1
);
5286 if (GET_CODE (op0
) == XOR
5287 && rtx_equal_p (XEXP (op0
, 1), op1
)
5288 && ! side_effects_p (op1
))
5289 x
= gen_binary (AND
, mode
,
5290 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)), op1
);
5292 /* Similarly for (~(A ^ B)) & A. */
5293 if (GET_CODE (op0
) == NOT
5294 && GET_CODE (XEXP (op0
, 0)) == XOR
5295 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5296 && ! side_effects_p (op1
))
5297 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5299 if (GET_CODE (op0
) == NOT
5300 && GET_CODE (XEXP (op0
, 0)) == XOR
5301 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5302 && ! side_effects_p (op1
))
5303 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5305 /* We can call simplify_and_const_int only if we don't lose
5306 any (sign) bits when converting INTVAL (op1) to
5307 "unsigned HOST_WIDE_INT". */
5308 if (GET_CODE (op1
) == CONST_INT
5309 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5310 || INTVAL (op1
) > 0))
5312 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5314 /* If we have (ior (and (X C1) C2)) and the next restart would be
5315 the last, simplify this by making C1 as small as possible
5318 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5319 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5320 && GET_CODE (op1
) == CONST_INT
)
5321 return gen_binary (IOR
, mode
,
5322 gen_binary (AND
, mode
, XEXP (op0
, 0),
5323 GEN_INT (INTVAL (XEXP (op0
, 1))
5324 & ~INTVAL (op1
))), op1
);
5326 if (GET_CODE (x
) != AND
)
5329 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5330 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5331 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5334 /* Convert (A | B) & A to A. */
5335 if (GET_CODE (op0
) == IOR
5336 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5337 || rtx_equal_p (XEXP (op0
, 1), op1
))
5338 && ! side_effects_p (XEXP (op0
, 0))
5339 && ! side_effects_p (XEXP (op0
, 1)))
5342 /* In the following group of tests (and those in case IOR below),
5343 we start with some combination of logical operations and apply
5344 the distributive law followed by the inverse distributive law.
5345 Most of the time, this results in no change. However, if some of
5346 the operands are the same or inverses of each other, simplifications
5349 For example, (and (ior A B) (not B)) can occur as the result of
5350 expanding a bit field assignment. When we apply the distributive
5351 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5352 which then simplifies to (and (A (not B))).
5354 If we have (and (ior A B) C), apply the distributive law and then
5355 the inverse distributive law to see if things simplify. */
5357 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5359 x
= apply_distributive_law
5360 (gen_binary (GET_CODE (op0
), mode
,
5361 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5362 gen_binary (AND
, mode
, XEXP (op0
, 1),
5364 if (GET_CODE (x
) != AND
)
5368 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5369 return apply_distributive_law
5370 (gen_binary (GET_CODE (op1
), mode
,
5371 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5372 gen_binary (AND
, mode
, XEXP (op1
, 1),
5375 /* Similarly, taking advantage of the fact that
5376 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5378 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5379 return apply_distributive_law
5380 (gen_binary (XOR
, mode
,
5381 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5382 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5385 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5386 return apply_distributive_law
5387 (gen_binary (XOR
, mode
,
5388 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5389 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5393 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5394 if (GET_CODE (op1
) == CONST_INT
5395 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5396 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5399 /* Convert (A & B) | A to A. */
5400 if (GET_CODE (op0
) == AND
5401 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5402 || rtx_equal_p (XEXP (op0
, 1), op1
))
5403 && ! side_effects_p (XEXP (op0
, 0))
5404 && ! side_effects_p (XEXP (op0
, 1)))
5407 /* If we have (ior (and A B) C), apply the distributive law and then
5408 the inverse distributive law to see if things simplify. */
5410 if (GET_CODE (op0
) == AND
)
5412 x
= apply_distributive_law
5413 (gen_binary (AND
, mode
,
5414 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5415 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5418 if (GET_CODE (x
) != IOR
)
5422 if (GET_CODE (op1
) == AND
)
5424 x
= apply_distributive_law
5425 (gen_binary (AND
, mode
,
5426 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5427 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5430 if (GET_CODE (x
) != IOR
)
5434 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5435 mode size to (rotate A CX). */
5437 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5438 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5439 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5440 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5441 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5442 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5443 == GET_MODE_BITSIZE (mode
)))
5444 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5445 (GET_CODE (op0
) == ASHIFT
5446 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5448 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5449 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5450 does not affect any of the bits in OP1, it can really be done
5451 as a PLUS and we can associate. We do this by seeing if OP1
5452 can be safely shifted left C bits. */
5453 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5454 && GET_CODE (XEXP (op0
, 0)) == PLUS
5455 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5456 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5457 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5459 int count
= INTVAL (XEXP (op0
, 1));
5460 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5462 if (mask
>> count
== INTVAL (op1
)
5463 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5465 SUBST (XEXP (XEXP (op0
, 0), 1),
5466 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5473 /* If we are XORing two things that have no bits in common,
5474 convert them into an IOR. This helps to detect rotation encoded
5475 using those methods and possibly other simplifications. */
5477 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5478 && (nonzero_bits (op0
, mode
)
5479 & nonzero_bits (op1
, mode
)) == 0)
5480 return (gen_binary (IOR
, mode
, op0
, op1
));
5482 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5483 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5486 int num_negated
= 0;
5488 if (GET_CODE (op0
) == NOT
)
5489 num_negated
++, op0
= XEXP (op0
, 0);
5490 if (GET_CODE (op1
) == NOT
)
5491 num_negated
++, op1
= XEXP (op1
, 0);
5493 if (num_negated
== 2)
5495 SUBST (XEXP (x
, 0), op0
);
5496 SUBST (XEXP (x
, 1), op1
);
5498 else if (num_negated
== 1)
5499 return gen_unary (NOT
, mode
, mode
, gen_binary (XOR
, mode
, op0
, op1
));
5502 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5503 correspond to a machine insn or result in further simplifications
5504 if B is a constant. */
5506 if (GET_CODE (op0
) == AND
5507 && rtx_equal_p (XEXP (op0
, 1), op1
)
5508 && ! side_effects_p (op1
))
5509 return gen_binary (AND
, mode
,
5510 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)),
5513 else if (GET_CODE (op0
) == AND
5514 && rtx_equal_p (XEXP (op0
, 0), op1
)
5515 && ! side_effects_p (op1
))
5516 return gen_binary (AND
, mode
,
5517 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)),
5520 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5521 comparison if STORE_FLAG_VALUE is 1. */
5522 if (STORE_FLAG_VALUE
== 1
5523 && op1
== const1_rtx
5524 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5525 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5529 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5530 is (lt foo (const_int 0)), so we can perform the above
5531 simplification if STORE_FLAG_VALUE is 1. */
5533 if (STORE_FLAG_VALUE
== 1
5534 && op1
== const1_rtx
5535 && GET_CODE (op0
) == LSHIFTRT
5536 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5537 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5538 return gen_rtx_combine (GE
, mode
, XEXP (op0
, 0), const0_rtx
);
5540 /* (xor (comparison foo bar) (const_int sign-bit))
5541 when STORE_FLAG_VALUE is the sign bit. */
5542 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5543 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5544 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5545 && op1
== const_true_rtx
5546 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5547 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5560 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5561 operations" because they can be replaced with two more basic operations.
5562 ZERO_EXTEND is also considered "compound" because it can be replaced with
5563 an AND operation, which is simpler, though only one operation.
5565 The function expand_compound_operation is called with an rtx expression
5566 and will convert it to the appropriate shifts and AND operations,
5567 simplifying at each stage.
5569 The function make_compound_operation is called to convert an expression
5570 consisting of shifts and ANDs into the equivalent compound expression.
5571 It is the inverse of this function, loosely speaking. */
5574 expand_compound_operation (x
)
5577 unsigned HOST_WIDE_INT pos
= 0, len
;
5579 unsigned int modewidth
;
5582 switch (GET_CODE (x
))
5587 /* We can't necessarily use a const_int for a multiword mode;
5588 it depends on implicitly extending the value.
5589 Since we don't know the right way to extend it,
5590 we can't tell whether the implicit way is right.
5592 Even for a mode that is no wider than a const_int,
5593 we can't win, because we need to sign extend one of its bits through
5594 the rest of it, and we don't know which bit. */
5595 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5598 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5599 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5600 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5601 reloaded. If not for that, MEM's would very rarely be safe.
5603 Reject MODEs bigger than a word, because we might not be able
5604 to reference a two-register group starting with an arbitrary register
5605 (and currently gen_lowpart might crash for a SUBREG). */
5607 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5610 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5611 /* If the inner object has VOIDmode (the only way this can happen
5612 is if it is a ASM_OPERANDS), we can't do anything since we don't
5613 know how much masking to do. */
5622 /* If the operand is a CLOBBER, just return it. */
5623 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5626 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5627 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5628 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5631 len
= INTVAL (XEXP (x
, 1));
5632 pos
= INTVAL (XEXP (x
, 2));
5634 /* If this goes outside the object being extracted, replace the object
5635 with a (use (mem ...)) construct that only combine understands
5636 and is used only for this purpose. */
5637 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5638 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5640 if (BITS_BIG_ENDIAN
)
5641 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5648 /* Convert sign extension to zero extension, if we know that the high
5649 bit is not set, as this is easier to optimize. It will be converted
5650 back to cheaper alternative in make_extraction. */
5651 if (GET_CODE (x
) == SIGN_EXTEND
5652 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5653 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5654 & ~(((unsigned HOST_WIDE_INT
)
5655 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5659 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5660 return expand_compound_operation (temp
);
5663 /* We can optimize some special cases of ZERO_EXTEND. */
5664 if (GET_CODE (x
) == ZERO_EXTEND
)
5666 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5667 know that the last value didn't have any inappropriate bits
5669 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5670 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5671 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5672 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5673 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5674 return XEXP (XEXP (x
, 0), 0);
5676 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5677 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5678 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5679 && subreg_lowpart_p (XEXP (x
, 0))
5680 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5681 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5682 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5683 return SUBREG_REG (XEXP (x
, 0));
5685 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5686 is a comparison and STORE_FLAG_VALUE permits. This is like
5687 the first case, but it works even when GET_MODE (x) is larger
5688 than HOST_WIDE_INT. */
5689 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5690 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5691 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5692 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5693 <= HOST_BITS_PER_WIDE_INT
)
5694 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5695 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5696 return XEXP (XEXP (x
, 0), 0);
5698 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5699 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5700 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5701 && subreg_lowpart_p (XEXP (x
, 0))
5702 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5703 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5704 <= HOST_BITS_PER_WIDE_INT
)
5705 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5706 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5707 return SUBREG_REG (XEXP (x
, 0));
5711 /* If we reach here, we want to return a pair of shifts. The inner
5712 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5713 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5714 logical depending on the value of UNSIGNEDP.
5716 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5717 converted into an AND of a shift.
5719 We must check for the case where the left shift would have a negative
5720 count. This can happen in a case like (x >> 31) & 255 on machines
5721 that can't shift by a constant. On those machines, we would first
5722 combine the shift with the AND to produce a variable-position
5723 extraction. Then the constant of 31 would be substituted in to produce
5724 a such a position. */
5726 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5727 if (modewidth
+ len
>= pos
)
5728 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5730 simplify_shift_const (NULL_RTX
, ASHIFT
,
5733 modewidth
- pos
- len
),
5736 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5737 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5738 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5741 ((HOST_WIDE_INT
) 1 << len
) - 1);
5743 /* Any other cases we can't handle. */
5746 /* If we couldn't do this for some reason, return the original
5748 if (GET_CODE (tem
) == CLOBBER
)
5754 /* X is a SET which contains an assignment of one object into
5755 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5756 or certain SUBREGS). If possible, convert it into a series of
5759 We half-heartedly support variable positions, but do not at all
5760 support variable lengths. */
5763 expand_field_assignment (x
)
5767 rtx pos
; /* Always counts from low bit. */
5770 enum machine_mode compute_mode
;
5772 /* Loop until we find something we can't simplify. */
5775 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5776 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5778 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5779 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5780 pos
= GEN_INT (BITS_PER_WORD
* SUBREG_WORD (XEXP (SET_DEST (x
), 0)));
5782 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5783 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5785 inner
= XEXP (SET_DEST (x
), 0);
5786 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5787 pos
= XEXP (SET_DEST (x
), 2);
5789 /* If the position is constant and spans the width of INNER,
5790 surround INNER with a USE to indicate this. */
5791 if (GET_CODE (pos
) == CONST_INT
5792 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5793 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5795 if (BITS_BIG_ENDIAN
)
5797 if (GET_CODE (pos
) == CONST_INT
)
5798 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5800 else if (GET_CODE (pos
) == MINUS
5801 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5802 && (INTVAL (XEXP (pos
, 1))
5803 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5804 /* If position is ADJUST - X, new position is X. */
5805 pos
= XEXP (pos
, 0);
5807 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5808 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5814 /* A SUBREG between two modes that occupy the same numbers of words
5815 can be done by moving the SUBREG to the source. */
5816 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5817 /* We need SUBREGs to compute nonzero_bits properly. */
5818 && nonzero_sign_valid
5819 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5820 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5821 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5822 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5824 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5825 gen_lowpart_for_combine
5826 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5833 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5834 inner
= SUBREG_REG (inner
);
5836 compute_mode
= GET_MODE (inner
);
5838 /* Don't attempt bitwise arithmetic on non-integral modes. */
5839 if (! INTEGRAL_MODE_P (compute_mode
))
5841 enum machine_mode imode
;
5843 /* Something is probably seriously wrong if this matches. */
5844 if (! FLOAT_MODE_P (compute_mode
))
5847 /* Try to find an integral mode to pun with. */
5848 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5849 if (imode
== BLKmode
)
5852 compute_mode
= imode
;
5853 inner
= gen_lowpart_for_combine (imode
, inner
);
5856 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5857 if (len
< HOST_BITS_PER_WIDE_INT
)
5858 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5862 /* Now compute the equivalent expression. Make a copy of INNER
5863 for the SET_DEST in case it is a MEM into which we will substitute;
5864 we don't want shared RTL in that case. */
5866 (VOIDmode
, copy_rtx (inner
),
5867 gen_binary (IOR
, compute_mode
,
5868 gen_binary (AND
, compute_mode
,
5869 gen_unary (NOT
, compute_mode
,
5875 gen_binary (ASHIFT
, compute_mode
,
5876 gen_binary (AND
, compute_mode
,
5877 gen_lowpart_for_combine
5878 (compute_mode
, SET_SRC (x
)),
5886 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5887 it is an RTX that represents a variable starting position; otherwise,
5888 POS is the (constant) starting bit position (counted from the LSB).
5890 INNER may be a USE. This will occur when we started with a bitfield
5891 that went outside the boundary of the object in memory, which is
5892 allowed on most machines. To isolate this case, we produce a USE
5893 whose mode is wide enough and surround the MEM with it. The only
5894 code that understands the USE is this routine. If it is not removed,
5895 it will cause the resulting insn not to match.
5897 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5900 IN_DEST is non-zero if this is a reference in the destination of a
5901 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5902 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5905 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5906 ZERO_EXTRACT should be built even for bits starting at bit 0.
5908 MODE is the desired mode of the result (if IN_DEST == 0).
5910 The result is an RTX for the extraction or NULL_RTX if the target
5914 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5915 unsignedp
, in_dest
, in_compare
)
5916 enum machine_mode mode
;
5920 unsigned HOST_WIDE_INT len
;
5922 int in_dest
, in_compare
;
5924 /* This mode describes the size of the storage area
5925 to fetch the overall value from. Within that, we
5926 ignore the POS lowest bits, etc. */
5927 enum machine_mode is_mode
= GET_MODE (inner
);
5928 enum machine_mode inner_mode
;
5929 enum machine_mode wanted_inner_mode
= byte_mode
;
5930 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5931 enum machine_mode pos_mode
= word_mode
;
5932 enum machine_mode extraction_mode
= word_mode
;
5933 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5936 rtx orig_pos_rtx
= pos_rtx
;
5937 HOST_WIDE_INT orig_pos
;
5939 /* Get some information about INNER and get the innermost object. */
5940 if (GET_CODE (inner
) == USE
)
5941 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5942 /* We don't need to adjust the position because we set up the USE
5943 to pretend that it was a full-word object. */
5944 spans_byte
= 1, inner
= XEXP (inner
, 0);
5945 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5947 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5948 consider just the QI as the memory to extract from.
5949 The subreg adds or removes high bits; its mode is
5950 irrelevant to the meaning of this extraction,
5951 since POS and LEN count from the lsb. */
5952 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5953 is_mode
= GET_MODE (SUBREG_REG (inner
));
5954 inner
= SUBREG_REG (inner
);
5957 inner_mode
= GET_MODE (inner
);
5959 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5960 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5962 /* See if this can be done without an extraction. We never can if the
5963 width of the field is not the same as that of some integer mode. For
5964 registers, we can only avoid the extraction if the position is at the
5965 low-order bit and this is either not in the destination or we have the
5966 appropriate STRICT_LOW_PART operation available.
5968 For MEM, we can avoid an extract if the field starts on an appropriate
5969 boundary and we can change the mode of the memory reference. However,
5970 we cannot directly access the MEM if we have a USE and the underlying
5971 MEM is not TMODE. This combination means that MEM was being used in a
5972 context where bits outside its mode were being referenced; that is only
5973 valid in bit-field insns. */
5975 if (tmode
!= BLKmode
5976 && ! (spans_byte
&& inner_mode
!= tmode
)
5977 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5978 && GET_CODE (inner
) != MEM
5980 || (GET_CODE (inner
) == REG
5981 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
5982 != CODE_FOR_nothing
))))
5983 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5985 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5986 : BITS_PER_UNIT
)) == 0
5987 /* We can't do this if we are widening INNER_MODE (it
5988 may not be aligned, for one thing). */
5989 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5990 && (inner_mode
== tmode
5991 || (! mode_dependent_address_p (XEXP (inner
, 0))
5992 && ! MEM_VOLATILE_P (inner
))))))
5994 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5995 field. If the original and current mode are the same, we need not
5996 adjust the offset. Otherwise, we do if bytes big endian.
5998 If INNER is not a MEM, get a piece consisting of just the field
5999 of interest (in this case POS % BITS_PER_WORD must be 0). */
6001 if (GET_CODE (inner
) == MEM
)
6004 /* POS counts from lsb, but make OFFSET count in memory order. */
6005 if (BYTES_BIG_ENDIAN
)
6006 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6008 offset
= pos
/ BITS_PER_UNIT
;
6010 new = gen_rtx_MEM (tmode
, plus_constant (XEXP (inner
, 0), offset
));
6011 MEM_COPY_ATTRIBUTES (new, inner
);
6013 else if (GET_CODE (inner
) == REG
)
6015 /* We can't call gen_lowpart_for_combine here since we always want
6016 a SUBREG and it would sometimes return a new hard register. */
6017 if (tmode
!= inner_mode
)
6018 new = gen_rtx_SUBREG (tmode
, inner
,
6020 && (GET_MODE_SIZE (inner_mode
)
6022 ? (((GET_MODE_SIZE (inner_mode
)
6023 - GET_MODE_SIZE (tmode
))
6025 - pos
/ BITS_PER_WORD
)
6026 : pos
/ BITS_PER_WORD
));
6031 new = force_to_mode (inner
, tmode
,
6032 len
>= HOST_BITS_PER_WIDE_INT
6033 ? ~(unsigned HOST_WIDE_INT
) 0
6034 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6037 /* If this extraction is going into the destination of a SET,
6038 make a STRICT_LOW_PART unless we made a MEM. */
6041 return (GET_CODE (new) == MEM
? new
6042 : (GET_CODE (new) != SUBREG
6043 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6044 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
6049 /* If we know that no extraneous bits are set, and that the high
6050 bit is not set, convert the extraction to the cheaper of
6051 sign and zero extension, that are equivalent in these cases. */
6052 if (flag_expensive_optimizations
6053 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6054 && ((nonzero_bits (new, tmode
)
6055 & ~(((unsigned HOST_WIDE_INT
)
6056 GET_MODE_MASK (tmode
))
6060 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6061 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6063 /* Prefer ZERO_EXTENSION, since it gives more information to
6065 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6070 /* Otherwise, sign- or zero-extend unless we already are in the
6073 return (gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6077 /* Unless this is a COMPARE or we have a funny memory reference,
6078 don't do anything with zero-extending field extracts starting at
6079 the low-order bit since they are simple AND operations. */
6080 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6081 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6084 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6085 we would be spanning bytes or if the position is not a constant and the
6086 length is not 1. In all other cases, we would only be going outside
6087 our object in cases when an original shift would have been
6089 if (! spans_byte
&& GET_CODE (inner
) == MEM
6090 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6091 || (pos_rtx
!= 0 && len
!= 1)))
6094 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6095 and the mode for the result. */
6099 wanted_inner_reg_mode
6100 = insn_data
[(int) CODE_FOR_insv
].operand
[0].mode
;
6101 if (wanted_inner_reg_mode
== VOIDmode
)
6102 wanted_inner_reg_mode
= word_mode
;
6104 pos_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[2].mode
;
6105 if (pos_mode
== VOIDmode
)
6106 pos_mode
= word_mode
;
6108 extraction_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
6109 if (extraction_mode
== VOIDmode
)
6110 extraction_mode
= word_mode
;
6115 if (! in_dest
&& unsignedp
)
6117 wanted_inner_reg_mode
6118 = insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
6119 if (wanted_inner_reg_mode
== VOIDmode
)
6120 wanted_inner_reg_mode
= word_mode
;
6122 pos_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[3].mode
;
6123 if (pos_mode
== VOIDmode
)
6124 pos_mode
= word_mode
;
6126 extraction_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
6127 if (extraction_mode
== VOIDmode
)
6128 extraction_mode
= word_mode
;
6133 if (! in_dest
&& ! unsignedp
)
6135 wanted_inner_reg_mode
6136 = insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
6137 if (wanted_inner_reg_mode
== VOIDmode
)
6138 wanted_inner_reg_mode
= word_mode
;
6140 pos_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[3].mode
;
6141 if (pos_mode
== VOIDmode
)
6142 pos_mode
= word_mode
;
6144 extraction_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
6145 if (extraction_mode
== VOIDmode
)
6146 extraction_mode
= word_mode
;
6150 /* Never narrow an object, since that might not be safe. */
6152 if (mode
!= VOIDmode
6153 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6154 extraction_mode
= mode
;
6156 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6157 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6158 pos_mode
= GET_MODE (pos_rtx
);
6160 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6161 if we have to change the mode of memory and cannot, the desired mode is
6163 if (GET_CODE (inner
) != MEM
)
6164 wanted_inner_mode
= wanted_inner_reg_mode
;
6165 else if (inner_mode
!= wanted_inner_mode
6166 && (mode_dependent_address_p (XEXP (inner
, 0))
6167 || MEM_VOLATILE_P (inner
)))
6168 wanted_inner_mode
= extraction_mode
;
6172 if (BITS_BIG_ENDIAN
)
6174 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6175 BITS_BIG_ENDIAN style. If position is constant, compute new
6176 position. Otherwise, build subtraction.
6177 Note that POS is relative to the mode of the original argument.
6178 If it's a MEM we need to recompute POS relative to that.
6179 However, if we're extracting from (or inserting into) a register,
6180 we want to recompute POS relative to wanted_inner_mode. */
6181 int width
= (GET_CODE (inner
) == MEM
6182 ? GET_MODE_BITSIZE (is_mode
)
6183 : GET_MODE_BITSIZE (wanted_inner_mode
));
6186 pos
= width
- len
- pos
;
6189 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
6190 GEN_INT (width
- len
), pos_rtx
);
6191 /* POS may be less than 0 now, but we check for that below.
6192 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6195 /* If INNER has a wider mode, make it smaller. If this is a constant
6196 extract, try to adjust the byte to point to the byte containing
6198 if (wanted_inner_mode
!= VOIDmode
6199 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6200 && ((GET_CODE (inner
) == MEM
6201 && (inner_mode
== wanted_inner_mode
6202 || (! mode_dependent_address_p (XEXP (inner
, 0))
6203 && ! MEM_VOLATILE_P (inner
))))))
6207 /* The computations below will be correct if the machine is big
6208 endian in both bits and bytes or little endian in bits and bytes.
6209 If it is mixed, we must adjust. */
6211 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6212 adjust OFFSET to compensate. */
6213 if (BYTES_BIG_ENDIAN
6215 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6216 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6218 /* If this is a constant position, we can move to the desired byte. */
6221 offset
+= pos
/ BITS_PER_UNIT
;
6222 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6225 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6227 && is_mode
!= wanted_inner_mode
)
6228 offset
= (GET_MODE_SIZE (is_mode
)
6229 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6231 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6233 rtx newmem
= gen_rtx_MEM (wanted_inner_mode
,
6234 plus_constant (XEXP (inner
, 0), offset
));
6236 MEM_COPY_ATTRIBUTES (newmem
, inner
);
6241 /* If INNER is not memory, we can always get it into the proper mode. If we
6242 are changing its mode, POS must be a constant and smaller than the size
6244 else if (GET_CODE (inner
) != MEM
)
6246 if (GET_MODE (inner
) != wanted_inner_mode
6248 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6251 inner
= force_to_mode (inner
, wanted_inner_mode
,
6253 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6254 ? ~(unsigned HOST_WIDE_INT
) 0
6255 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6260 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6261 have to zero extend. Otherwise, we can just use a SUBREG. */
6263 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6265 rtx temp
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
6267 /* If we know that no extraneous bits are set, and that the high
6268 bit is not set, convert extraction to cheaper one - eighter
6269 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6271 if (flag_expensive_optimizations
6272 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6273 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6274 & ~(((unsigned HOST_WIDE_INT
)
6275 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6279 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6281 /* Prefer ZERO_EXTENSION, since it gives more information to
6283 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6288 else if (pos_rtx
!= 0
6289 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6290 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6292 /* Make POS_RTX unless we already have it and it is correct. If we don't
6293 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6295 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6296 pos_rtx
= orig_pos_rtx
;
6298 else if (pos_rtx
== 0)
6299 pos_rtx
= GEN_INT (pos
);
6301 /* Make the required operation. See if we can use existing rtx. */
6302 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6303 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6305 new = gen_lowpart_for_combine (mode
, new);
6310 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6311 with any other operations in X. Return X without that shift if so. */
6314 extract_left_shift (x
, count
)
6318 enum rtx_code code
= GET_CODE (x
);
6319 enum machine_mode mode
= GET_MODE (x
);
6325 /* This is the shift itself. If it is wide enough, we will return
6326 either the value being shifted if the shift count is equal to
6327 COUNT or a shift for the difference. */
6328 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6329 && INTVAL (XEXP (x
, 1)) >= count
)
6330 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6331 INTVAL (XEXP (x
, 1)) - count
);
6335 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6336 return gen_unary (code
, mode
, mode
, tem
);
6340 case PLUS
: case IOR
: case XOR
: case AND
:
6341 /* If we can safely shift this constant and we find the inner shift,
6342 make a new operation. */
6343 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6344 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6345 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6346 return gen_binary (code
, mode
, tem
,
6347 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6358 /* Look at the expression rooted at X. Look for expressions
6359 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6360 Form these expressions.
6362 Return the new rtx, usually just X.
6364 Also, for machines like the Vax that don't have logical shift insns,
6365 try to convert logical to arithmetic shift operations in cases where
6366 they are equivalent. This undoes the canonicalizations to logical
6367 shifts done elsewhere.
6369 We try, as much as possible, to re-use rtl expressions to save memory.
6371 IN_CODE says what kind of expression we are processing. Normally, it is
6372 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6373 being kludges), it is MEM. When processing the arguments of a comparison
6374 or a COMPARE against zero, it is COMPARE. */
6377 make_compound_operation (x
, in_code
)
6379 enum rtx_code in_code
;
6381 enum rtx_code code
= GET_CODE (x
);
6382 enum machine_mode mode
= GET_MODE (x
);
6383 int mode_width
= GET_MODE_BITSIZE (mode
);
6385 enum rtx_code next_code
;
6391 /* Select the code to be used in recursive calls. Once we are inside an
6392 address, we stay there. If we have a comparison, set to COMPARE,
6393 but once inside, go back to our default of SET. */
6395 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6396 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6397 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6398 : in_code
== COMPARE
? SET
: in_code
);
6400 /* Process depending on the code of this operation. If NEW is set
6401 non-zero, it will be returned. */
6406 /* Convert shifts by constants into multiplications if inside
6408 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6409 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6410 && INTVAL (XEXP (x
, 1)) >= 0)
6412 new = make_compound_operation (XEXP (x
, 0), next_code
);
6413 new = gen_rtx_combine (MULT
, mode
, new,
6414 GEN_INT ((HOST_WIDE_INT
) 1
6415 << INTVAL (XEXP (x
, 1))));
6420 /* If the second operand is not a constant, we can't do anything
6422 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6425 /* If the constant is a power of two minus one and the first operand
6426 is a logical right shift, make an extraction. */
6427 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6428 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6430 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6431 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6432 0, in_code
== COMPARE
);
6435 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6436 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6437 && subreg_lowpart_p (XEXP (x
, 0))
6438 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6439 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6441 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6443 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6444 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6445 0, in_code
== COMPARE
);
6447 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6448 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6449 || GET_CODE (XEXP (x
, 0)) == IOR
)
6450 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6451 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6452 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6454 /* Apply the distributive law, and then try to make extractions. */
6455 new = gen_rtx_combine (GET_CODE (XEXP (x
, 0)), mode
,
6456 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6458 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6460 new = make_compound_operation (new, in_code
);
6463 /* If we are have (and (rotate X C) M) and C is larger than the number
6464 of bits in M, this is an extraction. */
6466 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6467 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6468 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6469 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6471 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6472 new = make_extraction (mode
, new,
6473 (GET_MODE_BITSIZE (mode
)
6474 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6475 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6478 /* On machines without logical shifts, if the operand of the AND is
6479 a logical shift and our mask turns off all the propagated sign
6480 bits, we can replace the logical shift with an arithmetic shift. */
6481 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6482 && (lshr_optab
->handlers
[(int) mode
].insn_code
6483 == CODE_FOR_nothing
)
6484 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6485 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6486 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6487 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6488 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6490 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6492 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6493 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6495 gen_rtx_combine (ASHIFTRT
, mode
,
6496 make_compound_operation (XEXP (XEXP (x
, 0), 0),
6498 XEXP (XEXP (x
, 0), 1)));
6501 /* If the constant is one less than a power of two, this might be
6502 representable by an extraction even if no shift is present.
6503 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6504 we are in a COMPARE. */
6505 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6506 new = make_extraction (mode
,
6507 make_compound_operation (XEXP (x
, 0),
6509 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6511 /* If we are in a comparison and this is an AND with a power of two,
6512 convert this into the appropriate bit extract. */
6513 else if (in_code
== COMPARE
6514 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6515 new = make_extraction (mode
,
6516 make_compound_operation (XEXP (x
, 0),
6518 i
, NULL_RTX
, 1, 1, 0, 1);
6523 /* If the sign bit is known to be zero, replace this with an
6524 arithmetic shift. */
6525 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
6526 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6527 && mode_width
<= HOST_BITS_PER_WIDE_INT
6528 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6530 new = gen_rtx_combine (ASHIFTRT
, mode
,
6531 make_compound_operation (XEXP (x
, 0),
6537 /* ... fall through ... */
6543 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6544 this is a SIGN_EXTRACT. */
6545 if (GET_CODE (rhs
) == CONST_INT
6546 && GET_CODE (lhs
) == ASHIFT
6547 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6548 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6550 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6551 new = make_extraction (mode
, new,
6552 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6553 NULL_RTX
, mode_width
- INTVAL (rhs
),
6554 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6558 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6559 If so, try to merge the shifts into a SIGN_EXTEND. We could
6560 also do this for some cases of SIGN_EXTRACT, but it doesn't
6561 seem worth the effort; the case checked for occurs on Alpha. */
6563 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6564 && ! (GET_CODE (lhs
) == SUBREG
6565 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6566 && GET_CODE (rhs
) == CONST_INT
6567 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6568 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6569 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6570 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6571 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6576 /* Call ourselves recursively on the inner expression. If we are
6577 narrowing the object and it has a different RTL code from
6578 what it originally did, do this SUBREG as a force_to_mode. */
6580 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6581 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6582 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6583 && subreg_lowpart_p (x
))
6585 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6588 /* If we have something other than a SUBREG, we might have
6589 done an expansion, so rerun outselves. */
6590 if (GET_CODE (newer
) != SUBREG
)
6591 newer
= make_compound_operation (newer
, in_code
);
6596 /* If this is a paradoxical subreg, and the new code is a sign or
6597 zero extension, omit the subreg and widen the extension. If it
6598 is a regular subreg, we can still get rid of the subreg by not
6599 widening so much, or in fact removing the extension entirely. */
6600 if ((GET_CODE (tem
) == SIGN_EXTEND
6601 || GET_CODE (tem
) == ZERO_EXTEND
)
6602 && subreg_lowpart_p (x
))
6604 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6605 || (GET_MODE_SIZE (mode
) >
6606 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6607 tem
= gen_rtx_combine (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6609 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6620 x
= gen_lowpart_for_combine (mode
, new);
6621 code
= GET_CODE (x
);
6624 /* Now recursively process each operand of this operation. */
6625 fmt
= GET_RTX_FORMAT (code
);
6626 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6629 new = make_compound_operation (XEXP (x
, i
), next_code
);
6630 SUBST (XEXP (x
, i
), new);
6636 /* Given M see if it is a value that would select a field of bits
6637 within an item, but not the entire word. Return -1 if not.
6638 Otherwise, return the starting position of the field, where 0 is the
6641 *PLEN is set to the length of the field. */
6644 get_pos_from_mask (m
, plen
)
6645 unsigned HOST_WIDE_INT m
;
6646 unsigned HOST_WIDE_INT
*plen
;
6648 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6649 int pos
= exact_log2 (m
& -m
);
6655 /* Now shift off the low-order zero bits and see if we have a power of
6657 len
= exact_log2 ((m
>> pos
) + 1);
6666 /* See if X can be simplified knowing that we will only refer to it in
6667 MODE and will only refer to those bits that are nonzero in MASK.
6668 If other bits are being computed or if masking operations are done
6669 that select a superset of the bits in MASK, they can sometimes be
6672 Return a possibly simplified expression, but always convert X to
6673 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6675 Also, if REG is non-zero and X is a register equal in value to REG,
6678 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6679 are all off in X. This is used when X will be complemented, by either
6680 NOT, NEG, or XOR. */
6683 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6685 enum machine_mode mode
;
6686 unsigned HOST_WIDE_INT mask
;
6690 enum rtx_code code
= GET_CODE (x
);
6691 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6692 enum machine_mode op_mode
;
6693 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6696 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6697 code below will do the wrong thing since the mode of such an
6698 expression is VOIDmode.
6700 Also do nothing if X is a CLOBBER; this can happen if X was
6701 the return value from a call to gen_lowpart_for_combine. */
6702 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6705 /* We want to perform the operation is its present mode unless we know
6706 that the operation is valid in MODE, in which case we do the operation
6708 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6709 && code_to_optab
[(int) code
] != 0
6710 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
6711 != CODE_FOR_nothing
))
6712 ? mode
: GET_MODE (x
));
6714 /* It is not valid to do a right-shift in a narrower mode
6715 than the one it came in with. */
6716 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6717 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6718 op_mode
= GET_MODE (x
);
6720 /* Truncate MASK to fit OP_MODE. */
6722 mask
&= GET_MODE_MASK (op_mode
);
6724 /* When we have an arithmetic operation, or a shift whose count we
6725 do not know, we need to assume that all bit the up to the highest-order
6726 bit in MASK will be needed. This is how we form such a mask. */
6728 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6729 ? GET_MODE_MASK (op_mode
)
6730 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6733 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6735 /* Determine what bits of X are guaranteed to be (non)zero. */
6736 nonzero
= nonzero_bits (x
, mode
);
6738 /* If none of the bits in X are needed, return a zero. */
6739 if (! just_select
&& (nonzero
& mask
) == 0)
6742 /* If X is a CONST_INT, return a new one. Do this here since the
6743 test below will fail. */
6744 if (GET_CODE (x
) == CONST_INT
)
6746 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6747 int width
= GET_MODE_BITSIZE (mode
);
6749 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6750 number, sign extend it. */
6751 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6752 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6753 cval
|= (HOST_WIDE_INT
) -1 << width
;
6755 return GEN_INT (cval
);
6758 /* If X is narrower than MODE and we want all the bits in X's mode, just
6759 get X in the proper mode. */
6760 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6761 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6762 return gen_lowpart_for_combine (mode
, x
);
6764 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6765 MASK are already known to be zero in X, we need not do anything. */
6766 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6772 /* If X is a (clobber (const_int)), return it since we know we are
6773 generating something that won't match. */
6777 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6778 spanned the boundary of the MEM. If we are now masking so it is
6779 within that boundary, we don't need the USE any more. */
6780 if (! BITS_BIG_ENDIAN
6781 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6782 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6789 x
= expand_compound_operation (x
);
6790 if (GET_CODE (x
) != code
)
6791 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6795 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6796 || rtx_equal_p (reg
, get_last_value (x
))))
6801 if (subreg_lowpart_p (x
)
6802 /* We can ignore the effect of this SUBREG if it narrows the mode or
6803 if the constant masks to zero all the bits the mode doesn't
6805 && ((GET_MODE_SIZE (GET_MODE (x
))
6806 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6808 & GET_MODE_MASK (GET_MODE (x
))
6809 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6810 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6814 /* If this is an AND with a constant, convert it into an AND
6815 whose constant is the AND of that constant with MASK. If it
6816 remains an AND of MASK, delete it since it is redundant. */
6818 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6820 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6821 mask
& INTVAL (XEXP (x
, 1)));
6823 /* If X is still an AND, see if it is an AND with a mask that
6824 is just some low-order bits. If so, and it is MASK, we don't
6827 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6828 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6831 /* If it remains an AND, try making another AND with the bits
6832 in the mode mask that aren't in MASK turned on. If the
6833 constant in the AND is wide enough, this might make a
6834 cheaper constant. */
6836 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6837 && GET_MODE_MASK (GET_MODE (x
)) != mask
6838 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6840 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6841 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6842 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6845 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6846 number, sign extend it. */
6847 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6848 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6849 cval
|= (HOST_WIDE_INT
) -1 << width
;
6851 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6852 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6862 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6863 low-order bits (as in an alignment operation) and FOO is already
6864 aligned to that boundary, mask C1 to that boundary as well.
6865 This may eliminate that PLUS and, later, the AND. */
6868 unsigned int width
= GET_MODE_BITSIZE (mode
);
6869 unsigned HOST_WIDE_INT smask
= mask
;
6871 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6872 number, sign extend it. */
6874 if (width
< HOST_BITS_PER_WIDE_INT
6875 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6876 smask
|= (HOST_WIDE_INT
) -1 << width
;
6878 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6879 && exact_log2 (- smask
) >= 0)
6883 && (XEXP (x
, 0) == stack_pointer_rtx
6884 || XEXP (x
, 0) == frame_pointer_rtx
))
6886 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6887 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6889 sp_mask
&= ~(sp_alignment
- 1);
6890 if ((sp_mask
& ~smask
) == 0
6891 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~smask
) != 0)
6892 return force_to_mode (plus_constant (XEXP (x
, 0),
6893 ((INTVAL (XEXP (x
, 1)) -
6894 STACK_BIAS
) & smask
)
6896 mode
, smask
, reg
, next_select
);
6899 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6900 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6901 return force_to_mode (plus_constant (XEXP (x
, 0),
6902 (INTVAL (XEXP (x
, 1))
6904 mode
, smask
, reg
, next_select
);
6908 /* ... fall through ... */
6911 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6912 most significant bit in MASK since carries from those bits will
6913 affect the bits we are interested in. */
6918 /* If X is (minus C Y) where C's least set bit is larger than any bit
6919 in the mask, then we may replace with (neg Y). */
6920 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6921 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6922 & -INTVAL (XEXP (x
, 0))))
6925 x
= gen_unary (NEG
, GET_MODE (x
), GET_MODE (x
), XEXP (x
, 1));
6926 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6929 /* Similarly, if C contains every bit in the mask, then we may
6930 replace with (not Y). */
6931 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6932 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6933 == INTVAL (XEXP (x
, 0))))
6935 x
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), XEXP (x
, 1));
6936 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6944 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6945 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6946 operation which may be a bitfield extraction. Ensure that the
6947 constant we form is not wider than the mode of X. */
6949 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6950 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6951 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6952 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6953 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6954 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6955 + floor_log2 (INTVAL (XEXP (x
, 1))))
6956 < GET_MODE_BITSIZE (GET_MODE (x
)))
6957 && (INTVAL (XEXP (x
, 1))
6958 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6960 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6961 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6962 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6963 XEXP (XEXP (x
, 0), 0), temp
);
6964 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6965 XEXP (XEXP (x
, 0), 1));
6966 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6970 /* For most binary operations, just propagate into the operation and
6971 change the mode if we have an operation of that mode. */
6973 op0
= gen_lowpart_for_combine (op_mode
,
6974 force_to_mode (XEXP (x
, 0), mode
, mask
,
6976 op1
= gen_lowpart_for_combine (op_mode
,
6977 force_to_mode (XEXP (x
, 1), mode
, mask
,
6980 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6981 MASK since OP1 might have been sign-extended but we never want
6982 to turn on extra bits, since combine might have previously relied
6983 on them being off. */
6984 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
6985 && (INTVAL (op1
) & mask
) != 0)
6986 op1
= GEN_INT (INTVAL (op1
) & mask
);
6988 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6989 x
= gen_binary (code
, op_mode
, op0
, op1
);
6993 /* For left shifts, do the same, but just for the first operand.
6994 However, we cannot do anything with shifts where we cannot
6995 guarantee that the counts are smaller than the size of the mode
6996 because such a count will have a different meaning in a
6999 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7000 && INTVAL (XEXP (x
, 1)) >= 0
7001 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7002 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7003 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7004 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7007 /* If the shift count is a constant and we can do arithmetic in
7008 the mode of the shift, refine which bits we need. Otherwise, use the
7009 conservative form of the mask. */
7010 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7011 && INTVAL (XEXP (x
, 1)) >= 0
7012 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7013 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7014 mask
>>= INTVAL (XEXP (x
, 1));
7018 op0
= gen_lowpart_for_combine (op_mode
,
7019 force_to_mode (XEXP (x
, 0), op_mode
,
7020 mask
, reg
, next_select
));
7022 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7023 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7027 /* Here we can only do something if the shift count is a constant,
7028 this shift constant is valid for the host, and we can do arithmetic
7031 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7032 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7033 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7035 rtx inner
= XEXP (x
, 0);
7036 unsigned HOST_WIDE_INT inner_mask
;
7038 /* Select the mask of the bits we need for the shift operand. */
7039 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7041 /* We can only change the mode of the shift if we can do arithmetic
7042 in the mode of the shift and INNER_MASK is no wider than the
7043 width of OP_MODE. */
7044 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7045 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7046 op_mode
= GET_MODE (x
);
7048 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7050 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7051 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7054 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7055 shift and AND produces only copies of the sign bit (C2 is one less
7056 than a power of two), we can do this with just a shift. */
7058 if (GET_CODE (x
) == LSHIFTRT
7059 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7060 /* The shift puts one of the sign bit copies in the least significant
7062 && ((INTVAL (XEXP (x
, 1))
7063 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7064 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7065 && exact_log2 (mask
+ 1) >= 0
7066 /* Number of bits left after the shift must be more than the mask
7068 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7069 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7070 /* Must be more sign bit copies than the mask needs. */
7071 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7072 >= exact_log2 (mask
+ 1)))
7073 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7074 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7075 - exact_log2 (mask
+ 1)));
7080 /* If we are just looking for the sign bit, we don't need this shift at
7081 all, even if it has a variable count. */
7082 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7083 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7084 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7085 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7087 /* If this is a shift by a constant, get a mask that contains those bits
7088 that are not copies of the sign bit. We then have two cases: If
7089 MASK only includes those bits, this can be a logical shift, which may
7090 allow simplifications. If MASK is a single-bit field not within
7091 those bits, we are requesting a copy of the sign bit and hence can
7092 shift the sign bit to the appropriate location. */
7094 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7095 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7099 /* If the considered data is wider then HOST_WIDE_INT, we can't
7100 represent a mask for all its bits in a single scalar.
7101 But we only care about the lower bits, so calculate these. */
7103 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7105 nonzero
= ~(HOST_WIDE_INT
) 0;
7107 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7108 is the number of bits a full-width mask would have set.
7109 We need only shift if these are fewer than nonzero can
7110 hold. If not, we must keep all bits set in nonzero. */
7112 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7113 < HOST_BITS_PER_WIDE_INT
)
7114 nonzero
>>= INTVAL (XEXP (x
, 1))
7115 + HOST_BITS_PER_WIDE_INT
7116 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7120 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7121 nonzero
>>= INTVAL (XEXP (x
, 1));
7124 if ((mask
& ~nonzero
) == 0
7125 || (i
= exact_log2 (mask
)) >= 0)
7127 x
= simplify_shift_const
7128 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7129 i
< 0 ? INTVAL (XEXP (x
, 1))
7130 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7132 if (GET_CODE (x
) != ASHIFTRT
)
7133 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7137 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7138 even if the shift count isn't a constant. */
7140 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7144 /* If this is a zero- or sign-extension operation that just affects bits
7145 we don't care about, remove it. Be sure the call above returned
7146 something that is still a shift. */
7148 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7149 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7150 && INTVAL (XEXP (x
, 1)) >= 0
7151 && (INTVAL (XEXP (x
, 1))
7152 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7153 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7154 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7155 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7156 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7163 /* If the shift count is constant and we can do computations
7164 in the mode of X, compute where the bits we care about are.
7165 Otherwise, we can't do anything. Don't change the mode of
7166 the shift or propagate MODE into the shift, though. */
7167 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7168 && INTVAL (XEXP (x
, 1)) >= 0)
7170 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7171 GET_MODE (x
), GEN_INT (mask
),
7173 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7175 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7176 INTVAL (temp
), reg
, next_select
));
7181 /* If we just want the low-order bit, the NEG isn't needed since it
7182 won't change the low-order bit. */
7184 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7186 /* We need any bits less significant than the most significant bit in
7187 MASK since carries from those bits will affect the bits we are
7193 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7194 same as the XOR case above. Ensure that the constant we form is not
7195 wider than the mode of X. */
7197 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7198 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7199 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7200 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7201 < GET_MODE_BITSIZE (GET_MODE (x
)))
7202 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7204 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7205 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7206 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7208 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7211 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7212 use the full mask inside the NOT. */
7216 op0
= gen_lowpart_for_combine (op_mode
,
7217 force_to_mode (XEXP (x
, 0), mode
, mask
,
7219 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7220 x
= gen_unary (code
, op_mode
, op_mode
, op0
);
7224 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7225 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7226 which is equal to STORE_FLAG_VALUE. */
7227 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7228 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7229 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7230 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7235 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7236 written in a narrower mode. We play it safe and do not do so. */
7239 gen_lowpart_for_combine (GET_MODE (x
),
7240 force_to_mode (XEXP (x
, 1), mode
,
7241 mask
, reg
, next_select
)));
7243 gen_lowpart_for_combine (GET_MODE (x
),
7244 force_to_mode (XEXP (x
, 2), mode
,
7245 mask
, reg
,next_select
)));
7252 /* Ensure we return a value of the proper mode. */
7253 return gen_lowpart_for_combine (mode
, x
);
7256 /* Return nonzero if X is an expression that has one of two values depending on
7257 whether some other value is zero or nonzero. In that case, we return the
7258 value that is being tested, *PTRUE is set to the value if the rtx being
7259 returned has a nonzero value, and *PFALSE is set to the other alternative.
7261 If we return zero, we set *PTRUE and *PFALSE to X. */
7264 if_then_else_cond (x
, ptrue
, pfalse
)
7266 rtx
*ptrue
, *pfalse
;
7268 enum machine_mode mode
= GET_MODE (x
);
7269 enum rtx_code code
= GET_CODE (x
);
7270 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7271 unsigned HOST_WIDE_INT nz
;
7273 /* If we are comparing a value against zero, we are done. */
7274 if ((code
== NE
|| code
== EQ
)
7275 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7277 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7278 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7282 /* If this is a unary operation whose operand has one of two values, apply
7283 our opcode to compute those values. */
7284 else if (GET_RTX_CLASS (code
) == '1'
7285 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7287 *ptrue
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), true0
);
7288 *pfalse
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), false0
);
7292 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7293 make can't possibly match and would suppress other optimizations. */
7294 else if (code
== COMPARE
)
7297 /* If this is a binary operation, see if either side has only one of two
7298 values. If either one does or if both do and they are conditional on
7299 the same value, compute the new true and false values. */
7300 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7301 || GET_RTX_CLASS (code
) == '<')
7303 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7304 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7306 if ((cond0
!= 0 || cond1
!= 0)
7307 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7309 /* If if_then_else_cond returned zero, then true/false are the
7310 same rtl. We must copy one of them to prevent invalid rtl
7313 true0
= copy_rtx (true0
);
7314 else if (cond1
== 0)
7315 true1
= copy_rtx (true1
);
7317 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7318 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7319 return cond0
? cond0
: cond1
;
7322 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7323 operands is zero when the other is non-zero, and vice-versa,
7324 and STORE_FLAG_VALUE is 1 or -1. */
7326 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7327 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7329 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7331 rtx op0
= XEXP (XEXP (x
, 0), 1);
7332 rtx op1
= XEXP (XEXP (x
, 1), 1);
7334 cond0
= XEXP (XEXP (x
, 0), 0);
7335 cond1
= XEXP (XEXP (x
, 1), 0);
7337 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7338 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7339 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7340 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7341 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7342 || ((swap_condition (GET_CODE (cond0
))
7343 == combine_reversed_comparison_code (cond1
))
7344 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7345 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7346 && ! side_effects_p (x
))
7348 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7349 *pfalse
= gen_binary (MULT
, mode
,
7351 ? gen_unary (NEG
, mode
, mode
, op1
) : op1
),
7357 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7359 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7360 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7361 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7363 cond0
= XEXP (XEXP (x
, 0), 0);
7364 cond1
= XEXP (XEXP (x
, 1), 0);
7366 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7367 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7368 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7369 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7370 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7371 || ((swap_condition (GET_CODE (cond0
))
7372 == combine_reversed_comparison_code (cond1
))
7373 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7374 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7375 && ! side_effects_p (x
))
7377 *ptrue
= *pfalse
= const0_rtx
;
7383 else if (code
== IF_THEN_ELSE
)
7385 /* If we have IF_THEN_ELSE already, extract the condition and
7386 canonicalize it if it is NE or EQ. */
7387 cond0
= XEXP (x
, 0);
7388 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7389 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7390 return XEXP (cond0
, 0);
7391 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7393 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7394 return XEXP (cond0
, 0);
7400 /* If X is a normal SUBREG with both inner and outer modes integral,
7401 we can narrow both the true and false values of the inner expression,
7402 if there is a condition. */
7403 else if (code
== SUBREG
&& GET_MODE_CLASS (mode
) == MODE_INT
7404 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_INT
7405 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
7406 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7409 if ((GET_CODE (SUBREG_REG (x
)) == REG
7410 || GET_CODE (SUBREG_REG (x
)) == MEM
7411 || CONSTANT_P (SUBREG_REG (x
)))
7412 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
7413 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
7415 true0
= operand_subword (true0
, SUBREG_WORD (x
), 0,
7416 GET_MODE (SUBREG_REG (x
)));
7417 false0
= operand_subword (false0
, SUBREG_WORD (x
), 0,
7418 GET_MODE (SUBREG_REG (x
)));
7420 *ptrue
= force_to_mode (true0
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
7422 = force_to_mode (false0
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
7427 /* If X is a constant, this isn't special and will cause confusions
7428 if we treat it as such. Likewise if it is equivalent to a constant. */
7429 else if (CONSTANT_P (x
)
7430 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7433 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7434 will be least confusing to the rest of the compiler. */
7435 else if (mode
== BImode
)
7437 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7441 /* If X is known to be either 0 or -1, those are the true and
7442 false values when testing X. */
7443 else if (x
== constm1_rtx
|| x
== const0_rtx
7444 || (mode
!= VOIDmode
7445 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7447 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7451 /* Likewise for 0 or a single bit. */
7452 else if (mode
!= VOIDmode
7453 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7454 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7456 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7460 /* Otherwise fail; show no condition with true and false values the same. */
7461 *ptrue
= *pfalse
= x
;
7465 /* Return the value of expression X given the fact that condition COND
7466 is known to be true when applied to REG as its first operand and VAL
7467 as its second. X is known to not be shared and so can be modified in
7470 We only handle the simplest cases, and specifically those cases that
7471 arise with IF_THEN_ELSE expressions. */
7474 known_cond (x
, cond
, reg
, val
)
7479 enum rtx_code code
= GET_CODE (x
);
7484 if (side_effects_p (x
))
7487 if (cond
== EQ
&& rtx_equal_p (x
, reg
) && !FLOAT_MODE_P (cond
))
7489 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7492 /* If X is (abs REG) and we know something about REG's relationship
7493 with zero, we may be able to simplify this. */
7495 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7498 case GE
: case GT
: case EQ
:
7501 return gen_unary (NEG
, GET_MODE (XEXP (x
, 0)), GET_MODE (XEXP (x
, 0)),
7507 /* The only other cases we handle are MIN, MAX, and comparisons if the
7508 operands are the same as REG and VAL. */
7510 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7512 if (rtx_equal_p (XEXP (x
, 0), val
))
7513 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7515 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7517 if (GET_RTX_CLASS (code
) == '<')
7519 if (comparison_dominates_p (cond
, code
))
7520 return const_true_rtx
;
7522 code
= combine_reversed_comparison_code (x
);
7524 && comparison_dominates_p (cond
, code
))
7529 else if (code
== SMAX
|| code
== SMIN
7530 || code
== UMIN
|| code
== UMAX
)
7532 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7534 /* Do not reverse the condition when it is NE or EQ.
7535 This is because we cannot conclude anything about
7536 the value of 'SMAX (x, y)' when x is not equal to y,
7537 but we can when x equals y. */
7538 if ((code
== SMAX
|| code
== UMAX
)
7539 && ! (cond
== EQ
|| cond
== NE
))
7540 cond
= reverse_condition (cond
);
7545 return unsignedp
? x
: XEXP (x
, 1);
7547 return unsignedp
? x
: XEXP (x
, 0);
7549 return unsignedp
? XEXP (x
, 1) : x
;
7551 return unsignedp
? XEXP (x
, 0) : x
;
7559 fmt
= GET_RTX_FORMAT (code
);
7560 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7563 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7564 else if (fmt
[i
] == 'E')
7565 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7566 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7573 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7574 assignment as a field assignment. */
7577 rtx_equal_for_field_assignment_p (x
, y
)
7581 if (x
== y
|| rtx_equal_p (x
, y
))
7584 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7587 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7588 Note that all SUBREGs of MEM are paradoxical; otherwise they
7589 would have been rewritten. */
7590 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7591 && GET_CODE (SUBREG_REG (y
)) == MEM
7592 && rtx_equal_p (SUBREG_REG (y
),
7593 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7596 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7597 && GET_CODE (SUBREG_REG (x
)) == MEM
7598 && rtx_equal_p (SUBREG_REG (x
),
7599 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7602 /* We used to see if get_last_value of X and Y were the same but that's
7603 not correct. In one direction, we'll cause the assignment to have
7604 the wrong destination and in the case, we'll import a register into this
7605 insn that might have already have been dead. So fail if none of the
7606 above cases are true. */
7610 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7611 Return that assignment if so.
7613 We only handle the most common cases. */
7616 make_field_assignment (x
)
7619 rtx dest
= SET_DEST (x
);
7620 rtx src
= SET_SRC (x
);
7625 unsigned HOST_WIDE_INT len
;
7627 enum machine_mode mode
;
7629 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7630 a clear of a one-bit field. We will have changed it to
7631 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7634 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7635 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7636 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7637 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7639 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7642 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7646 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7647 && subreg_lowpart_p (XEXP (src
, 0))
7648 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7649 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7650 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7651 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7652 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7654 assign
= make_extraction (VOIDmode
, dest
, 0,
7655 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7658 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7662 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7664 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7665 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7666 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7668 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7671 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7675 /* The other case we handle is assignments into a constant-position
7676 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7677 a mask that has all one bits except for a group of zero bits and
7678 OTHER is known to have zeros where C1 has ones, this is such an
7679 assignment. Compute the position and length from C1. Shift OTHER
7680 to the appropriate position, force it to the required mode, and
7681 make the extraction. Check for the AND in both operands. */
7683 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7686 rhs
= expand_compound_operation (XEXP (src
, 0));
7687 lhs
= expand_compound_operation (XEXP (src
, 1));
7689 if (GET_CODE (rhs
) == AND
7690 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7691 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7692 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7693 else if (GET_CODE (lhs
) == AND
7694 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7695 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7696 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7700 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7701 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7702 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7703 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7706 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7710 /* The mode to use for the source is the mode of the assignment, or of
7711 what is inside a possible STRICT_LOW_PART. */
7712 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7713 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7715 /* Shift OTHER right POS places and make it the source, restricting it
7716 to the proper length and mode. */
7718 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7719 GET_MODE (src
), other
, pos
),
7721 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7722 ? ~(unsigned HOST_WIDE_INT
) 0
7723 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7726 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
7729 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7733 apply_distributive_law (x
)
7736 enum rtx_code code
= GET_CODE (x
);
7737 rtx lhs
, rhs
, other
;
7739 enum rtx_code inner_code
;
7741 /* Distributivity is not true for floating point.
7742 It can change the value. So don't do it.
7743 -- rms and moshier@world.std.com. */
7744 if (FLOAT_MODE_P (GET_MODE (x
)))
7747 /* The outer operation can only be one of the following: */
7748 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7749 && code
!= PLUS
&& code
!= MINUS
)
7752 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7754 /* If either operand is a primitive we can't do anything, so get out
7756 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7757 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7760 lhs
= expand_compound_operation (lhs
);
7761 rhs
= expand_compound_operation (rhs
);
7762 inner_code
= GET_CODE (lhs
);
7763 if (inner_code
!= GET_CODE (rhs
))
7766 /* See if the inner and outer operations distribute. */
7773 /* These all distribute except over PLUS. */
7774 if (code
== PLUS
|| code
== MINUS
)
7779 if (code
!= PLUS
&& code
!= MINUS
)
7784 /* This is also a multiply, so it distributes over everything. */
7788 /* Non-paradoxical SUBREGs distributes over all operations, provided
7789 the inner modes and word numbers are the same, this is an extraction
7790 of a low-order part, we don't convert an fp operation to int or
7791 vice versa, and we would not be converting a single-word
7792 operation into a multi-word operation. The latter test is not
7793 required, but it prevents generating unneeded multi-word operations.
7794 Some of the previous tests are redundant given the latter test, but
7795 are retained because they are required for correctness.
7797 We produce the result slightly differently in this case. */
7799 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7800 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
7801 || ! subreg_lowpart_p (lhs
)
7802 || (GET_MODE_CLASS (GET_MODE (lhs
))
7803 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7804 || (GET_MODE_SIZE (GET_MODE (lhs
))
7805 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7806 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7809 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7810 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7811 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7817 /* Set LHS and RHS to the inner operands (A and B in the example
7818 above) and set OTHER to the common operand (C in the example).
7819 These is only one way to do this unless the inner operation is
7821 if (GET_RTX_CLASS (inner_code
) == 'c'
7822 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7823 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7824 else if (GET_RTX_CLASS (inner_code
) == 'c'
7825 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7826 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7827 else if (GET_RTX_CLASS (inner_code
) == 'c'
7828 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7829 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7830 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7831 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7835 /* Form the new inner operation, seeing if it simplifies first. */
7836 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7838 /* There is one exception to the general way of distributing:
7839 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7840 if (code
== XOR
&& inner_code
== IOR
)
7843 other
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), other
);
7846 /* We may be able to continuing distributing the result, so call
7847 ourselves recursively on the inner operation before forming the
7848 outer operation, which we return. */
7849 return gen_binary (inner_code
, GET_MODE (x
),
7850 apply_distributive_law (tem
), other
);
7853 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7856 Return an equivalent form, if different from X. Otherwise, return X. If
7857 X is zero, we are to always construct the equivalent form. */
7860 simplify_and_const_int (x
, mode
, varop
, constop
)
7862 enum machine_mode mode
;
7864 unsigned HOST_WIDE_INT constop
;
7866 unsigned HOST_WIDE_INT nonzero
;
7869 /* Simplify VAROP knowing that we will be only looking at some of the
7871 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7873 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7874 CONST_INT, we are done. */
7875 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7878 /* See what bits may be nonzero in VAROP. Unlike the general case of
7879 a call to nonzero_bits, here we don't care about bits outside
7882 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7883 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7885 /* Turn off all bits in the constant that are known to already be zero.
7886 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7887 which is tested below. */
7891 /* If we don't have any bits left, return zero. */
7895 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7896 a power of two, we can replace this with a ASHIFT. */
7897 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7898 && (i
= exact_log2 (constop
)) >= 0)
7899 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7901 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7902 or XOR, then try to apply the distributive law. This may eliminate
7903 operations if either branch can be simplified because of the AND.
7904 It may also make some cases more complex, but those cases probably
7905 won't match a pattern either with or without this. */
7907 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7909 gen_lowpart_for_combine
7911 apply_distributive_law
7912 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7913 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7914 XEXP (varop
, 0), constop
),
7915 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7916 XEXP (varop
, 1), constop
))));
7918 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7919 if we already had one (just check for the simplest cases). */
7920 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7921 && GET_MODE (XEXP (x
, 0)) == mode
7922 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7923 varop
= XEXP (x
, 0);
7925 varop
= gen_lowpart_for_combine (mode
, varop
);
7927 /* If we can't make the SUBREG, try to return what we were given. */
7928 if (GET_CODE (varop
) == CLOBBER
)
7929 return x
? x
: varop
;
7931 /* If we are only masking insignificant bits, return VAROP. */
7932 if (constop
== nonzero
)
7935 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7936 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7937 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7941 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7942 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7943 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7945 SUBST (XEXP (x
, 0), varop
);
7951 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7952 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7953 is less useful. We can't allow both, because that results in exponential
7954 run time recursion. There is a nullstone testcase that triggered
7955 this. This macro avoids accidental uses of num_sign_bit_copies. */
7956 #define num_sign_bit_copies()
7958 /* Given an expression, X, compute which bits in X can be non-zero.
7959 We don't care about bits outside of those defined in MODE.
7961 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7962 a shift, AND, or zero_extract, we can do better. */
7964 static unsigned HOST_WIDE_INT
7965 nonzero_bits (x
, mode
)
7967 enum machine_mode mode
;
7969 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
7970 unsigned HOST_WIDE_INT inner_nz
;
7972 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
7975 /* For floating-point values, assume all bits are needed. */
7976 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
7979 /* If X is wider than MODE, use its mode instead. */
7980 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
7982 mode
= GET_MODE (x
);
7983 nonzero
= GET_MODE_MASK (mode
);
7984 mode_width
= GET_MODE_BITSIZE (mode
);
7987 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
7988 /* Our only callers in this case look for single bit values. So
7989 just return the mode mask. Those tests will then be false. */
7992 #ifndef WORD_REGISTER_OPERATIONS
7993 /* If MODE is wider than X, but both are a single word for both the host
7994 and target machines, we can compute this from which bits of the
7995 object might be nonzero in its own mode, taking into account the fact
7996 that on many CISC machines, accessing an object in a wider mode
7997 causes the high-order bits to become undefined. So they are
7998 not known to be zero. */
8000 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8001 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8002 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8003 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8005 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
8006 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8011 code
= GET_CODE (x
);
8015 #ifdef POINTERS_EXTEND_UNSIGNED
8016 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8017 all the bits above ptr_mode are known to be zero. */
8018 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8020 nonzero
&= GET_MODE_MASK (ptr_mode
);
8023 #ifdef STACK_BOUNDARY
8024 /* If this is the stack pointer, we may know something about its
8025 alignment. If PUSH_ROUNDING is defined, it is possible for the
8026 stack to be momentarily aligned only to that amount, so we pick
8027 the least alignment. */
8029 /* We can't check for arg_pointer_rtx here, because it is not
8030 guaranteed to have as much alignment as the stack pointer.
8031 In particular, in the Irix6 n64 ABI, the stack has 128 bit
8032 alignment but the argument pointer has only 64 bit alignment. */
8034 if ((x
== frame_pointer_rtx
8035 || x
== stack_pointer_rtx
8036 || x
== hard_frame_pointer_rtx
8037 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
8038 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
8044 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8046 #ifdef PUSH_ROUNDING
8047 if (REGNO (x
) == STACK_POINTER_REGNUM
&& PUSH_ARGS
)
8048 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
8051 /* We must return here, otherwise we may get a worse result from
8052 one of the choices below. There is nothing useful below as
8053 far as the stack pointer is concerned. */
8054 return nonzero
&= ~(sp_alignment
- 1);
8058 /* If X is a register whose nonzero bits value is current, use it.
8059 Otherwise, if X is a register whose value we can find, use that
8060 value. Otherwise, use the previously-computed global nonzero bits
8061 for this register. */
8063 if (reg_last_set_value
[REGNO (x
)] != 0
8064 && reg_last_set_mode
[REGNO (x
)] == mode
8065 && (reg_last_set_label
[REGNO (x
)] == label_tick
8066 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8067 && REG_N_SETS (REGNO (x
)) == 1
8068 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8070 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8071 return reg_last_set_nonzero_bits
[REGNO (x
)];
8073 tem
= get_last_value (x
);
8077 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8078 /* If X is narrower than MODE and TEM is a non-negative
8079 constant that would appear negative in the mode of X,
8080 sign-extend it for use in reg_nonzero_bits because some
8081 machines (maybe most) will actually do the sign-extension
8082 and this is the conservative approach.
8084 ??? For 2.5, try to tighten up the MD files in this regard
8085 instead of this kludge. */
8087 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8088 && GET_CODE (tem
) == CONST_INT
8090 && 0 != (INTVAL (tem
)
8091 & ((HOST_WIDE_INT
) 1
8092 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8093 tem
= GEN_INT (INTVAL (tem
)
8094 | ((HOST_WIDE_INT
) (-1)
8095 << GET_MODE_BITSIZE (GET_MODE (x
))));
8097 return nonzero_bits (tem
, mode
);
8099 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8100 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
8105 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8106 /* If X is negative in MODE, sign-extend the value. */
8107 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8108 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8109 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8115 #ifdef LOAD_EXTEND_OP
8116 /* In many, if not most, RISC machines, reading a byte from memory
8117 zeros the rest of the register. Noticing that fact saves a lot
8118 of extra zero-extends. */
8119 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8120 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8125 case UNEQ
: case LTGT
:
8126 case GT
: case GTU
: case UNGT
:
8127 case LT
: case LTU
: case UNLT
:
8128 case GE
: case GEU
: case UNGE
:
8129 case LE
: case LEU
: case UNLE
:
8130 case UNORDERED
: case ORDERED
:
8132 /* If this produces an integer result, we know which bits are set.
8133 Code here used to clear bits outside the mode of X, but that is
8136 if (GET_MODE_CLASS (mode
) == MODE_INT
8137 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8138 nonzero
= STORE_FLAG_VALUE
;
8143 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8144 and num_sign_bit_copies. */
8145 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8146 == GET_MODE_BITSIZE (GET_MODE (x
)))
8150 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8151 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8156 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8157 and num_sign_bit_copies. */
8158 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8159 == GET_MODE_BITSIZE (GET_MODE (x
)))
8165 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8169 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8170 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8171 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8175 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8176 Otherwise, show all the bits in the outer mode but not the inner
8178 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8179 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8181 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8183 & (((HOST_WIDE_INT
) 1
8184 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8185 inner_nz
|= (GET_MODE_MASK (mode
)
8186 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8189 nonzero
&= inner_nz
;
8193 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8194 & nonzero_bits (XEXP (x
, 1), mode
));
8198 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8199 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8200 | nonzero_bits (XEXP (x
, 1), mode
));
8203 case PLUS
: case MINUS
:
8205 case DIV
: case UDIV
:
8206 case MOD
: case UMOD
:
8207 /* We can apply the rules of arithmetic to compute the number of
8208 high- and low-order zero bits of these operations. We start by
8209 computing the width (position of the highest-order non-zero bit)
8210 and the number of low-order zero bits for each value. */
8212 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8213 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8214 int width0
= floor_log2 (nz0
) + 1;
8215 int width1
= floor_log2 (nz1
) + 1;
8216 int low0
= floor_log2 (nz0
& -nz0
);
8217 int low1
= floor_log2 (nz1
& -nz1
);
8218 HOST_WIDE_INT op0_maybe_minusp
8219 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8220 HOST_WIDE_INT op1_maybe_minusp
8221 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8222 unsigned int result_width
= mode_width
;
8230 && (XEXP (x
, 0) == stack_pointer_rtx
8231 || XEXP (x
, 0) == frame_pointer_rtx
)
8232 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8234 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8236 nz0
= (GET_MODE_MASK (mode
) & ~(sp_alignment
- 1));
8237 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
8238 width0
= floor_log2 (nz0
) + 1;
8239 width1
= floor_log2 (nz1
) + 1;
8240 low0
= floor_log2 (nz0
& -nz0
);
8241 low1
= floor_log2 (nz1
& -nz1
);
8244 result_width
= MAX (width0
, width1
) + 1;
8245 result_low
= MIN (low0
, low1
);
8248 result_low
= MIN (low0
, low1
);
8251 result_width
= width0
+ width1
;
8252 result_low
= low0
+ low1
;
8255 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8256 result_width
= width0
;
8259 result_width
= width0
;
8262 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8263 result_width
= MIN (width0
, width1
);
8264 result_low
= MIN (low0
, low1
);
8267 result_width
= MIN (width0
, width1
);
8268 result_low
= MIN (low0
, low1
);
8274 if (result_width
< mode_width
)
8275 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8278 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8280 #ifdef POINTERS_EXTEND_UNSIGNED
8281 /* If pointers extend unsigned and this is an addition or subtraction
8282 to a pointer in Pmode, all the bits above ptr_mode are known to be
8284 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8285 && (code
== PLUS
|| code
== MINUS
)
8286 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8287 nonzero
&= GET_MODE_MASK (ptr_mode
);
8293 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8294 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8295 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8299 /* If this is a SUBREG formed for a promoted variable that has
8300 been zero-extended, we know that at least the high-order bits
8301 are zero, though others might be too. */
8303 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
8304 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8305 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8307 /* If the inner mode is a single word for both the host and target
8308 machines, we can compute this from which bits of the inner
8309 object might be nonzero. */
8310 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8311 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8312 <= HOST_BITS_PER_WIDE_INT
))
8314 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8316 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8317 /* If this is a typical RISC machine, we only have to worry
8318 about the way loads are extended. */
8319 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8321 & (((unsigned HOST_WIDE_INT
) 1
8322 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8324 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8327 /* On many CISC machines, accessing an object in a wider mode
8328 causes the high-order bits to become undefined. So they are
8329 not known to be zero. */
8330 if (GET_MODE_SIZE (GET_MODE (x
))
8331 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8332 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8333 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8342 /* The nonzero bits are in two classes: any bits within MODE
8343 that aren't in GET_MODE (x) are always significant. The rest of the
8344 nonzero bits are those that are significant in the operand of
8345 the shift when shifted the appropriate number of bits. This
8346 shows that high-order bits are cleared by the right shift and
8347 low-order bits by left shifts. */
8348 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8349 && INTVAL (XEXP (x
, 1)) >= 0
8350 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8352 enum machine_mode inner_mode
= GET_MODE (x
);
8353 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8354 int count
= INTVAL (XEXP (x
, 1));
8355 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8356 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8357 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8358 unsigned HOST_WIDE_INT outer
= 0;
8360 if (mode_width
> width
)
8361 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8363 if (code
== LSHIFTRT
)
8365 else if (code
== ASHIFTRT
)
8369 /* If the sign bit may have been nonzero before the shift, we
8370 need to mark all the places it could have been copied to
8371 by the shift as possibly nonzero. */
8372 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8373 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8375 else if (code
== ASHIFT
)
8378 inner
= ((inner
<< (count
% width
)
8379 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8381 nonzero
&= (outer
| inner
);
8386 /* This is at most the number of bits in the mode. */
8387 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8391 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8392 | nonzero_bits (XEXP (x
, 2), mode
));
8402 /* See the macro definition above. */
8403 #undef num_sign_bit_copies
8405 /* Return the number of bits at the high-order end of X that are known to
8406 be equal to the sign bit. X will be used in mode MODE; if MODE is
8407 VOIDmode, X will be used in its own mode. The returned value will always
8408 be between 1 and the number of bits in MODE. */
8411 num_sign_bit_copies (x
, mode
)
8413 enum machine_mode mode
;
8415 enum rtx_code code
= GET_CODE (x
);
8416 unsigned int bitwidth
;
8417 int num0
, num1
, result
;
8418 unsigned HOST_WIDE_INT nonzero
;
8421 /* If we weren't given a mode, use the mode of X. If the mode is still
8422 VOIDmode, we don't know anything. Likewise if one of the modes is
8425 if (mode
== VOIDmode
)
8426 mode
= GET_MODE (x
);
8428 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8431 bitwidth
= GET_MODE_BITSIZE (mode
);
8433 /* For a smaller object, just ignore the high bits. */
8434 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8436 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8438 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8441 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8443 #ifndef WORD_REGISTER_OPERATIONS
8444 /* If this machine does not do all register operations on the entire
8445 register and MODE is wider than the mode of X, we can say nothing
8446 at all about the high-order bits. */
8449 /* Likewise on machines that do, if the mode of the object is smaller
8450 than a word and loads of that size don't sign extend, we can say
8451 nothing about the high order bits. */
8452 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8453 #ifdef LOAD_EXTEND_OP
8454 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8465 #ifdef POINTERS_EXTEND_UNSIGNED
8466 /* If pointers extend signed and this is a pointer in Pmode, say that
8467 all the bits above ptr_mode are known to be sign bit copies. */
8468 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8470 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8473 if (reg_last_set_value
[REGNO (x
)] != 0
8474 && reg_last_set_mode
[REGNO (x
)] == mode
8475 && (reg_last_set_label
[REGNO (x
)] == label_tick
8476 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8477 && REG_N_SETS (REGNO (x
)) == 1
8478 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8480 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8481 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8483 tem
= get_last_value (x
);
8485 return num_sign_bit_copies (tem
, mode
);
8487 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8488 return reg_sign_bit_copies
[REGNO (x
)];
8492 #ifdef LOAD_EXTEND_OP
8493 /* Some RISC machines sign-extend all loads of smaller than a word. */
8494 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8495 return MAX (1, ((int) bitwidth
8496 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8501 /* If the constant is negative, take its 1's complement and remask.
8502 Then see how many zero bits we have. */
8503 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8504 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8505 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8506 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8508 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8511 /* If this is a SUBREG for a promoted object that is sign-extended
8512 and we are looking at it in a wider mode, we know that at least the
8513 high-order bits are known to be sign bit copies. */
8515 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8517 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8518 return MAX ((int) bitwidth
8519 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8523 /* For a smaller object, just ignore the high bits. */
8524 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8526 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8527 return MAX (1, (num0
8528 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8532 #ifdef WORD_REGISTER_OPERATIONS
8533 #ifdef LOAD_EXTEND_OP
8534 /* For paradoxical SUBREGs on machines where all register operations
8535 affect the entire register, just look inside. Note that we are
8536 passing MODE to the recursive call, so the number of sign bit copies
8537 will remain relative to that mode, not the inner mode. */
8539 /* This works only if loads sign extend. Otherwise, if we get a
8540 reload for the inner part, it may be loaded from the stack, and
8541 then we lose all sign bit copies that existed before the store
8544 if ((GET_MODE_SIZE (GET_MODE (x
))
8545 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8546 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8547 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8553 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8554 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8558 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8559 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8562 /* For a smaller object, just ignore the high bits. */
8563 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8564 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8568 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8570 case ROTATE
: case ROTATERT
:
8571 /* If we are rotating left by a number of bits less than the number
8572 of sign bit copies, we can just subtract that amount from the
8574 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8575 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
8577 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8578 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8579 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8584 /* In general, this subtracts one sign bit copy. But if the value
8585 is known to be positive, the number of sign bit copies is the
8586 same as that of the input. Finally, if the input has just one bit
8587 that might be nonzero, all the bits are copies of the sign bit. */
8588 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8589 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8590 return num0
> 1 ? num0
- 1 : 1;
8592 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8597 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8602 case IOR
: case AND
: case XOR
:
8603 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8604 /* Logical operations will preserve the number of sign-bit copies.
8605 MIN and MAX operations always return one of the operands. */
8606 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8607 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8608 return MIN (num0
, num1
);
8610 case PLUS
: case MINUS
:
8611 /* For addition and subtraction, we can have a 1-bit carry. However,
8612 if we are subtracting 1 from a positive number, there will not
8613 be such a carry. Furthermore, if the positive number is known to
8614 be 0 or 1, we know the result is either -1 or 0. */
8616 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8617 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8619 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8620 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8621 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8622 : bitwidth
- floor_log2 (nonzero
) - 1);
8625 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8626 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8627 result
= MAX (1, MIN (num0
, num1
) - 1);
8629 #ifdef POINTERS_EXTEND_UNSIGNED
8630 /* If pointers extend signed and this is an addition or subtraction
8631 to a pointer in Pmode, all the bits above ptr_mode are known to be
8633 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8634 && (code
== PLUS
|| code
== MINUS
)
8635 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8636 result
= MAX ((GET_MODE_BITSIZE (Pmode
)
8637 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8643 /* The number of bits of the product is the sum of the number of
8644 bits of both terms. However, unless one of the terms if known
8645 to be positive, we must allow for an additional bit since negating
8646 a negative number can remove one sign bit copy. */
8648 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8649 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8651 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8653 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8654 || (((nonzero_bits (XEXP (x
, 0), mode
)
8655 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8656 && ((nonzero_bits (XEXP (x
, 1), mode
)
8657 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8660 return MAX (1, result
);
8663 /* The result must be <= the first operand. If the first operand
8664 has the high bit set, we know nothing about the number of sign
8666 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8668 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8669 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8672 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8675 /* The result must be <= the scond operand. */
8676 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8679 /* Similar to unsigned division, except that we have to worry about
8680 the case where the divisor is negative, in which case we have
8682 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8684 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8685 || (nonzero_bits (XEXP (x
, 1), mode
)
8686 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8692 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8694 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8695 || (nonzero_bits (XEXP (x
, 1), mode
)
8696 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8702 /* Shifts by a constant add to the number of bits equal to the
8704 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8705 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8706 && INTVAL (XEXP (x
, 1)) > 0)
8707 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8712 /* Left shifts destroy copies. */
8713 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8714 || INTVAL (XEXP (x
, 1)) < 0
8715 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
8718 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8719 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8722 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8723 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8724 return MIN (num0
, num1
);
8726 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8727 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8728 case GEU
: case GTU
: case LEU
: case LTU
:
8729 case UNORDERED
: case ORDERED
:
8730 /* If the constant is negative, take its 1's complement and remask.
8731 Then see how many zero bits we have. */
8732 nonzero
= STORE_FLAG_VALUE
;
8733 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8734 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8735 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8737 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8744 /* If we haven't been able to figure it out by one of the above rules,
8745 see if some of the high-order bits are known to be zero. If so,
8746 count those bits and return one less than that amount. If we can't
8747 safely compute the mask for this mode, always return BITWIDTH. */
8749 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8752 nonzero
= nonzero_bits (x
, mode
);
8753 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8754 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8757 /* Return the number of "extended" bits there are in X, when interpreted
8758 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8759 unsigned quantities, this is the number of high-order zero bits.
8760 For signed quantities, this is the number of copies of the sign bit
8761 minus 1. In both case, this function returns the number of "spare"
8762 bits. For example, if two quantities for which this function returns
8763 at least 1 are added, the addition is known not to overflow.
8765 This function will always return 0 unless called during combine, which
8766 implies that it must be called from a define_split. */
8769 extended_count (x
, mode
, unsignedp
)
8771 enum machine_mode mode
;
8774 if (nonzero_sign_valid
== 0)
8778 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8779 ? (GET_MODE_BITSIZE (mode
) - 1
8780 - floor_log2 (nonzero_bits (x
, mode
)))
8782 : num_sign_bit_copies (x
, mode
) - 1);
8785 /* This function is called from `simplify_shift_const' to merge two
8786 outer operations. Specifically, we have already found that we need
8787 to perform operation *POP0 with constant *PCONST0 at the outermost
8788 position. We would now like to also perform OP1 with constant CONST1
8789 (with *POP0 being done last).
8791 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8792 the resulting operation. *PCOMP_P is set to 1 if we would need to
8793 complement the innermost operand, otherwise it is unchanged.
8795 MODE is the mode in which the operation will be done. No bits outside
8796 the width of this mode matter. It is assumed that the width of this mode
8797 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8799 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8800 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8801 result is simply *PCONST0.
8803 If the resulting operation cannot be expressed as one operation, we
8804 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8807 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8808 enum rtx_code
*pop0
;
8809 HOST_WIDE_INT
*pconst0
;
8811 HOST_WIDE_INT const1
;
8812 enum machine_mode mode
;
8815 enum rtx_code op0
= *pop0
;
8816 HOST_WIDE_INT const0
= *pconst0
;
8818 const0
&= GET_MODE_MASK (mode
);
8819 const1
&= GET_MODE_MASK (mode
);
8821 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8825 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8828 if (op1
== NIL
|| op0
== SET
)
8831 else if (op0
== NIL
)
8832 op0
= op1
, const0
= const1
;
8834 else if (op0
== op1
)
8858 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8859 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8862 /* If the two constants aren't the same, we can't do anything. The
8863 remaining six cases can all be done. */
8864 else if (const0
!= const1
)
8872 /* (a & b) | b == b */
8874 else /* op1 == XOR */
8875 /* (a ^ b) | b == a | b */
8881 /* (a & b) ^ b == (~a) & b */
8882 op0
= AND
, *pcomp_p
= 1;
8883 else /* op1 == IOR */
8884 /* (a | b) ^ b == a & ~b */
8885 op0
= AND
, *pconst0
= ~const0
;
8890 /* (a | b) & b == b */
8892 else /* op1 == XOR */
8893 /* (a ^ b) & b) == (~a) & b */
8900 /* Check for NO-OP cases. */
8901 const0
&= GET_MODE_MASK (mode
);
8903 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8905 else if (const0
== 0 && op0
== AND
)
8907 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8911 /* ??? Slightly redundant with the above mask, but not entirely.
8912 Moving this above means we'd have to sign-extend the mode mask
8913 for the final test. */
8914 const0
= trunc_int_for_mode (const0
, mode
);
8922 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8923 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8924 that we started with.
8926 The shift is normally computed in the widest mode we find in VAROP, as
8927 long as it isn't a different number of words than RESULT_MODE. Exceptions
8928 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8931 simplify_shift_const (x
, code
, result_mode
, varop
, input_count
)
8934 enum machine_mode result_mode
;
8938 enum rtx_code orig_code
= code
;
8939 int orig_count
= input_count
;
8942 enum machine_mode mode
= result_mode
;
8943 enum machine_mode shift_mode
, tmode
;
8944 unsigned int mode_words
8945 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8946 /* We form (outer_op (code varop count) (outer_const)). */
8947 enum rtx_code outer_op
= NIL
;
8948 HOST_WIDE_INT outer_const
= 0;
8950 int complement_p
= 0;
8953 /* If we were given an invalid count, don't do anything except exactly
8954 what was requested. */
8956 if (input_count
< 0 || input_count
> (int) GET_MODE_BITSIZE (mode
))
8961 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (input_count
));
8964 count
= input_count
;
8966 /* Make sure and truncate the "natural" shift on the way in. We don't
8967 want to do this inside the loop as it makes it more difficult to
8969 #ifdef SHIFT_COUNT_TRUNCATED
8970 if (SHIFT_COUNT_TRUNCATED
)
8971 count
%= GET_MODE_BITSIZE (mode
);
8974 /* Unless one of the branches of the `if' in this loop does a `continue',
8975 we will `break' the loop after the `if'. */
8979 /* If we have an operand of (clobber (const_int 0)), just return that
8981 if (GET_CODE (varop
) == CLOBBER
)
8984 /* If we discovered we had to complement VAROP, leave. Making a NOT
8985 here would cause an infinite loop. */
8989 /* Convert ROTATERT to ROTATE. */
8990 if (code
== ROTATERT
)
8991 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
8993 /* We need to determine what mode we will do the shift in. If the
8994 shift is a right shift or a ROTATE, we must always do it in the mode
8995 it was originally done in. Otherwise, we can do it in MODE, the
8996 widest mode encountered. */
8998 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8999 ? result_mode
: mode
);
9001 /* Handle cases where the count is greater than the size of the mode
9002 minus 1. For ASHIFT, use the size minus one as the count (this can
9003 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9004 take the count modulo the size. For other shifts, the result is
9007 Since these shifts are being produced by the compiler by combining
9008 multiple operations, each of which are defined, we know what the
9009 result is supposed to be. */
9011 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
9013 if (code
== ASHIFTRT
)
9014 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9015 else if (code
== ROTATE
|| code
== ROTATERT
)
9016 count
%= GET_MODE_BITSIZE (shift_mode
);
9019 /* We can't simply return zero because there may be an
9027 /* An arithmetic right shift of a quantity known to be -1 or 0
9029 if (code
== ASHIFTRT
9030 && (num_sign_bit_copies (varop
, shift_mode
)
9031 == GET_MODE_BITSIZE (shift_mode
)))
9037 /* If we are doing an arithmetic right shift and discarding all but
9038 the sign bit copies, this is equivalent to doing a shift by the
9039 bitsize minus one. Convert it into that shift because it will often
9040 allow other simplifications. */
9042 if (code
== ASHIFTRT
9043 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9044 >= GET_MODE_BITSIZE (shift_mode
)))
9045 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9047 /* We simplify the tests below and elsewhere by converting
9048 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9049 `make_compound_operation' will convert it to a ASHIFTRT for
9050 those machines (such as Vax) that don't have a LSHIFTRT. */
9051 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9053 && ((nonzero_bits (varop
, shift_mode
)
9054 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9058 switch (GET_CODE (varop
))
9064 new = expand_compound_operation (varop
);
9073 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9074 minus the width of a smaller mode, we can do this with a
9075 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9076 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9077 && ! mode_dependent_address_p (XEXP (varop
, 0))
9078 && ! MEM_VOLATILE_P (varop
)
9079 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9080 MODE_INT
, 1)) != BLKmode
)
9082 if (BYTES_BIG_ENDIAN
)
9083 new = gen_rtx_MEM (tmode
, XEXP (varop
, 0));
9085 new = gen_rtx_MEM (tmode
,
9086 plus_constant (XEXP (varop
, 0),
9087 count
/ BITS_PER_UNIT
));
9089 MEM_COPY_ATTRIBUTES (new, varop
);
9090 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
9091 : ZERO_EXTEND
, mode
, new);
9098 /* Similar to the case above, except that we can only do this if
9099 the resulting mode is the same as that of the underlying
9100 MEM and adjust the address depending on the *bits* endianness
9101 because of the way that bit-field extract insns are defined. */
9102 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9103 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9104 MODE_INT
, 1)) != BLKmode
9105 && tmode
== GET_MODE (XEXP (varop
, 0)))
9107 if (BITS_BIG_ENDIAN
)
9108 new = XEXP (varop
, 0);
9111 new = copy_rtx (XEXP (varop
, 0));
9112 SUBST (XEXP (new, 0),
9113 plus_constant (XEXP (new, 0),
9114 count
/ BITS_PER_UNIT
));
9117 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
9118 : ZERO_EXTEND
, mode
, new);
9125 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9126 the same number of words as what we've seen so far. Then store
9127 the widest mode in MODE. */
9128 if (subreg_lowpart_p (varop
)
9129 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9130 > GET_MODE_SIZE (GET_MODE (varop
)))
9131 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9132 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9135 varop
= SUBREG_REG (varop
);
9136 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9137 mode
= GET_MODE (varop
);
9143 /* Some machines use MULT instead of ASHIFT because MULT
9144 is cheaper. But it is still better on those machines to
9145 merge two shifts into one. */
9146 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9147 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9150 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9151 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9157 /* Similar, for when divides are cheaper. */
9158 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9159 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9162 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9163 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9169 /* If we are extracting just the sign bit of an arithmetic
9170 right shift, that shift is not needed. However, the sign
9171 bit of a wider mode may be different from what would be
9172 interpreted as the sign bit in a narrower mode, so, if
9173 the result is narrower, don't discard the shift. */
9174 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9175 && (GET_MODE_BITSIZE (result_mode
)
9176 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9178 varop
= XEXP (varop
, 0);
9182 /* ... fall through ... */
9187 /* Here we have two nested shifts. The result is usually the
9188 AND of a new shift with a mask. We compute the result below. */
9189 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9190 && INTVAL (XEXP (varop
, 1)) >= 0
9191 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9192 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9193 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9195 enum rtx_code first_code
= GET_CODE (varop
);
9196 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9197 unsigned HOST_WIDE_INT mask
;
9200 /* We have one common special case. We can't do any merging if
9201 the inner code is an ASHIFTRT of a smaller mode. However, if
9202 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9203 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9204 we can convert it to
9205 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9206 This simplifies certain SIGN_EXTEND operations. */
9207 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9208 && (GET_MODE_BITSIZE (result_mode
)
9209 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
9211 /* C3 has the low-order C1 bits zero. */
9213 mask
= (GET_MODE_MASK (mode
)
9214 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9216 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9217 XEXP (varop
, 0), mask
);
9218 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9220 count
= first_count
;
9225 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9226 than C1 high-order bits equal to the sign bit, we can convert
9227 this to either an ASHIFT or a ASHIFTRT depending on the
9230 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9232 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9233 && GET_MODE (varop
) == shift_mode
9234 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9237 varop
= XEXP (varop
, 0);
9239 signed_count
= count
- first_count
;
9240 if (signed_count
< 0)
9241 count
= -signed_count
, code
= ASHIFT
;
9243 count
= signed_count
;
9248 /* There are some cases we can't do. If CODE is ASHIFTRT,
9249 we can only do this if FIRST_CODE is also ASHIFTRT.
9251 We can't do the case when CODE is ROTATE and FIRST_CODE is
9254 If the mode of this shift is not the mode of the outer shift,
9255 we can't do this if either shift is a right shift or ROTATE.
9257 Finally, we can't do any of these if the mode is too wide
9258 unless the codes are the same.
9260 Handle the case where the shift codes are the same
9263 if (code
== first_code
)
9265 if (GET_MODE (varop
) != result_mode
9266 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9270 count
+= first_count
;
9271 varop
= XEXP (varop
, 0);
9275 if (code
== ASHIFTRT
9276 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9277 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9278 || (GET_MODE (varop
) != result_mode
9279 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9280 || first_code
== ROTATE
9281 || code
== ROTATE
)))
9284 /* To compute the mask to apply after the shift, shift the
9285 nonzero bits of the inner shift the same way the
9286 outer shift will. */
9288 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9291 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9294 /* Give up if we can't compute an outer operation to use. */
9296 || GET_CODE (mask_rtx
) != CONST_INT
9297 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9299 result_mode
, &complement_p
))
9302 /* If the shifts are in the same direction, we add the
9303 counts. Otherwise, we subtract them. */
9304 signed_count
= count
;
9305 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9306 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9307 signed_count
+= first_count
;
9309 signed_count
-= first_count
;
9311 /* If COUNT is positive, the new shift is usually CODE,
9312 except for the two exceptions below, in which case it is
9313 FIRST_CODE. If the count is negative, FIRST_CODE should
9315 if (signed_count
> 0
9316 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9317 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9318 code
= first_code
, count
= signed_count
;
9319 else if (signed_count
< 0)
9320 code
= first_code
, count
= -signed_count
;
9322 count
= signed_count
;
9324 varop
= XEXP (varop
, 0);
9328 /* If we have (A << B << C) for any shift, we can convert this to
9329 (A << C << B). This wins if A is a constant. Only try this if
9330 B is not a constant. */
9332 else if (GET_CODE (varop
) == code
9333 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9335 = simplify_binary_operation (code
, mode
,
9339 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
9346 /* Make this fit the case below. */
9347 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
9348 GEN_INT (GET_MODE_MASK (mode
)));
9354 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9355 with C the size of VAROP - 1 and the shift is logical if
9356 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9357 we have an (le X 0) operation. If we have an arithmetic shift
9358 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9359 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9361 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9362 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9363 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9364 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9365 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9366 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9369 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
9372 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9373 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9378 /* If we have (shift (logical)), move the logical to the outside
9379 to allow it to possibly combine with another logical and the
9380 shift to combine with another shift. This also canonicalizes to
9381 what a ZERO_EXTRACT looks like. Also, some machines have
9382 (and (shift)) insns. */
9384 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9385 && (new = simplify_binary_operation (code
, result_mode
,
9387 GEN_INT (count
))) != 0
9388 && GET_CODE (new) == CONST_INT
9389 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9390 INTVAL (new), result_mode
, &complement_p
))
9392 varop
= XEXP (varop
, 0);
9396 /* If we can't do that, try to simplify the shift in each arm of the
9397 logical expression, make a new logical expression, and apply
9398 the inverse distributive law. */
9400 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9401 XEXP (varop
, 0), count
);
9402 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9403 XEXP (varop
, 1), count
);
9405 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9406 varop
= apply_distributive_law (varop
);
9413 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9414 says that the sign bit can be tested, FOO has mode MODE, C is
9415 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9416 that may be nonzero. */
9417 if (code
== LSHIFTRT
9418 && XEXP (varop
, 1) == const0_rtx
9419 && GET_MODE (XEXP (varop
, 0)) == result_mode
9420 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9421 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9422 && ((STORE_FLAG_VALUE
9423 & ((HOST_WIDE_INT
) 1
9424 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9425 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9426 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9427 (HOST_WIDE_INT
) 1, result_mode
,
9430 varop
= XEXP (varop
, 0);
9437 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9438 than the number of bits in the mode is equivalent to A. */
9439 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9440 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9442 varop
= XEXP (varop
, 0);
9447 /* NEG commutes with ASHIFT since it is multiplication. Move the
9448 NEG outside to allow shifts to combine. */
9450 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9451 (HOST_WIDE_INT
) 0, result_mode
,
9454 varop
= XEXP (varop
, 0);
9460 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9461 is one less than the number of bits in the mode is
9462 equivalent to (xor A 1). */
9463 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9464 && XEXP (varop
, 1) == constm1_rtx
9465 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9466 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9467 (HOST_WIDE_INT
) 1, result_mode
,
9471 varop
= XEXP (varop
, 0);
9475 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9476 that might be nonzero in BAR are those being shifted out and those
9477 bits are known zero in FOO, we can replace the PLUS with FOO.
9478 Similarly in the other operand order. This code occurs when
9479 we are computing the size of a variable-size array. */
9481 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9482 && count
< HOST_BITS_PER_WIDE_INT
9483 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9484 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9485 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9487 varop
= XEXP (varop
, 0);
9490 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9491 && count
< HOST_BITS_PER_WIDE_INT
9492 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9493 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9495 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9496 & nonzero_bits (XEXP (varop
, 1),
9499 varop
= XEXP (varop
, 1);
9503 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9505 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9506 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9508 GEN_INT (count
))) != 0
9509 && GET_CODE (new) == CONST_INT
9510 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9511 INTVAL (new), result_mode
, &complement_p
))
9513 varop
= XEXP (varop
, 0);
9519 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9520 with C the size of VAROP - 1 and the shift is logical if
9521 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9522 we have a (gt X 0) operation. If the shift is arithmetic with
9523 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9524 we have a (neg (gt X 0)) operation. */
9526 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9527 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9528 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9529 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9530 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9531 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9532 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9535 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
9538 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9539 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9546 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9547 if the truncate does not affect the value. */
9548 if (code
== LSHIFTRT
9549 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9550 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9551 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9552 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9553 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9555 rtx varop_inner
= XEXP (varop
, 0);
9558 = gen_rtx_combine (LSHIFTRT
, GET_MODE (varop_inner
),
9559 XEXP (varop_inner
, 0),
9561 + INTVAL (XEXP (varop_inner
, 1))));
9562 varop
= gen_rtx_combine (TRUNCATE
, GET_MODE (varop
),
9576 /* We need to determine what mode to do the shift in. If the shift is
9577 a right shift or ROTATE, we must always do it in the mode it was
9578 originally done in. Otherwise, we can do it in MODE, the widest mode
9579 encountered. The code we care about is that of the shift that will
9580 actually be done, not the shift that was originally requested. */
9582 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9583 ? result_mode
: mode
);
9585 /* We have now finished analyzing the shift. The result should be
9586 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9587 OUTER_OP is non-NIL, it is an operation that needs to be applied
9588 to the result of the shift. OUTER_CONST is the relevant constant,
9589 but we must turn off all bits turned off in the shift.
9591 If we were passed a value for X, see if we can use any pieces of
9592 it. If not, make new rtx. */
9594 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9595 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9596 && INTVAL (XEXP (x
, 1)) == count
)
9597 const_rtx
= XEXP (x
, 1);
9599 const_rtx
= GEN_INT (count
);
9601 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9602 && GET_MODE (XEXP (x
, 0)) == shift_mode
9603 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9604 varop
= XEXP (x
, 0);
9605 else if (GET_MODE (varop
) != shift_mode
)
9606 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9608 /* If we can't make the SUBREG, try to return what we were given. */
9609 if (GET_CODE (varop
) == CLOBBER
)
9610 return x
? x
: varop
;
9612 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9617 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9618 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
9620 SUBST (XEXP (x
, 0), varop
);
9621 SUBST (XEXP (x
, 1), const_rtx
);
9624 /* If we have an outer operation and we just made a shift, it is
9625 possible that we could have simplified the shift were it not
9626 for the outer operation. So try to do the simplification
9629 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9630 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9631 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9632 INTVAL (XEXP (x
, 1)));
9634 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9635 turn off all the bits that the shift would have turned off. */
9636 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9637 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9638 GET_MODE_MASK (result_mode
) >> orig_count
);
9640 /* Do the remainder of the processing in RESULT_MODE. */
9641 x
= gen_lowpart_for_combine (result_mode
, x
);
9643 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9646 x
= gen_unary (NOT
, result_mode
, result_mode
, x
);
9648 if (outer_op
!= NIL
)
9650 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9651 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9653 if (outer_op
== AND
)
9654 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9655 else if (outer_op
== SET
)
9656 /* This means that we have determined that the result is
9657 equivalent to a constant. This should be rare. */
9658 x
= GEN_INT (outer_const
);
9659 else if (GET_RTX_CLASS (outer_op
) == '1')
9660 x
= gen_unary (outer_op
, result_mode
, result_mode
, x
);
9662 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9668 /* Like recog, but we receive the address of a pointer to a new pattern.
9669 We try to match the rtx that the pointer points to.
9670 If that fails, we may try to modify or replace the pattern,
9671 storing the replacement into the same pointer object.
9673 Modifications include deletion or addition of CLOBBERs.
9675 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9676 the CLOBBERs are placed.
9678 The value is the final insn code from the pattern ultimately matched,
9682 recog_for_combine (pnewpat
, insn
, pnotes
)
9687 register rtx pat
= *pnewpat
;
9688 int insn_code_number
;
9689 int num_clobbers_to_add
= 0;
9694 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9695 we use to indicate that something didn't match. If we find such a
9696 thing, force rejection. */
9697 if (GET_CODE (pat
) == PARALLEL
)
9698 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9699 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9700 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9703 /* Remove the old notes prior to trying to recognize the new pattern. */
9704 old_notes
= REG_NOTES (insn
);
9705 REG_NOTES (insn
) = 0;
9707 /* Is the result of combination a valid instruction? */
9708 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9710 /* If it isn't, there is the possibility that we previously had an insn
9711 that clobbered some register as a side effect, but the combined
9712 insn doesn't need to do that. So try once more without the clobbers
9713 unless this represents an ASM insn. */
9715 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9716 && GET_CODE (pat
) == PARALLEL
)
9720 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9721 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9724 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9728 SUBST_INT (XVECLEN (pat
, 0), pos
);
9731 pat
= XVECEXP (pat
, 0, 0);
9733 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9736 REG_NOTES (insn
) = old_notes
;
9738 /* If we had any clobbers to add, make a new pattern than contains
9739 them. Then check to make sure that all of them are dead. */
9740 if (num_clobbers_to_add
)
9742 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9743 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9745 + num_clobbers_to_add
)
9746 : num_clobbers_to_add
+ 1));
9748 if (GET_CODE (pat
) == PARALLEL
)
9749 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9750 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9752 XVECEXP (newpat
, 0, 0) = pat
;
9754 add_clobbers (newpat
, insn_code_number
);
9756 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9757 i
< XVECLEN (newpat
, 0); i
++)
9759 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9760 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9762 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9763 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9771 return insn_code_number
;
9774 /* Like gen_lowpart but for use by combine. In combine it is not possible
9775 to create any new pseudoregs. However, it is safe to create
9776 invalid memory addresses, because combine will try to recognize
9777 them and all they will do is make the combine attempt fail.
9779 If for some reason this cannot do its job, an rtx
9780 (clobber (const_int 0)) is returned.
9781 An insn containing that will not be recognized. */
9786 gen_lowpart_for_combine (mode
, x
)
9787 enum machine_mode mode
;
9792 if (GET_MODE (x
) == mode
)
9795 /* We can only support MODE being wider than a word if X is a
9796 constant integer or has a mode the same size. */
9798 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9799 && ! ((GET_MODE (x
) == VOIDmode
9800 && (GET_CODE (x
) == CONST_INT
9801 || GET_CODE (x
) == CONST_DOUBLE
))
9802 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9803 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9805 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9806 won't know what to do. So we will strip off the SUBREG here and
9807 process normally. */
9808 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9811 if (GET_MODE (x
) == mode
)
9815 result
= gen_lowpart_common (mode
, x
);
9816 #ifdef CLASS_CANNOT_CHANGE_MODE
9818 && GET_CODE (result
) == SUBREG
9819 && GET_CODE (SUBREG_REG (result
)) == REG
9820 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9821 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9822 GET_MODE (SUBREG_REG (result
))))
9823 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9829 if (GET_CODE (x
) == MEM
)
9831 register int offset
= 0;
9834 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9836 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9837 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9839 /* If we want to refer to something bigger than the original memref,
9840 generate a perverse subreg instead. That will force a reload
9841 of the original memref X. */
9842 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9843 return gen_rtx_SUBREG (mode
, x
, 0);
9845 if (WORDS_BIG_ENDIAN
)
9846 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9847 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9849 if (BYTES_BIG_ENDIAN
)
9851 /* Adjust the address so that the address-after-the-data is
9853 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9854 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9856 new = gen_rtx_MEM (mode
, plus_constant (XEXP (x
, 0), offset
));
9857 MEM_COPY_ATTRIBUTES (new, x
);
9861 /* If X is a comparison operator, rewrite it in a new mode. This
9862 probably won't match, but may allow further simplifications. */
9863 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9864 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9866 /* If we couldn't simplify X any other way, just enclose it in a
9867 SUBREG. Normally, this SUBREG won't match, but some patterns may
9868 include an explicit SUBREG or we may simplify it further in combine. */
9873 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
9874 word
= ((GET_MODE_SIZE (GET_MODE (x
))
9875 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
9877 return gen_rtx_SUBREG (mode
, x
, word
);
9881 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9882 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9884 If the identical expression was previously in the insn (in the undobuf),
9885 it will be returned. Only if it is not found will a new expression
9890 gen_rtx_combine
VPARAMS ((enum rtx_code code
, enum machine_mode mode
, ...))
9892 #ifndef ANSI_PROTOTYPES
9894 enum machine_mode mode
;
9906 #ifndef ANSI_PROTOTYPES
9907 code
= va_arg (p
, enum rtx_code
);
9908 mode
= va_arg (p
, enum machine_mode
);
9911 n_args
= GET_RTX_LENGTH (code
);
9912 fmt
= GET_RTX_FORMAT (code
);
9914 if (n_args
== 0 || n_args
> 3)
9917 /* Get each arg and verify that it is supposed to be an expression. */
9918 for (j
= 0; j
< n_args
; j
++)
9923 args
[j
] = va_arg (p
, rtx
);
9928 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9929 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9930 rt
= rtx_alloc (code
);
9931 PUT_MODE (rt
, mode
);
9932 XEXP (rt
, 0) = args
[0];
9935 XEXP (rt
, 1) = args
[1];
9937 XEXP (rt
, 2) = args
[2];
9942 /* These routines make binary and unary operations by first seeing if they
9943 fold; if not, a new expression is allocated. */
9946 gen_binary (code
, mode
, op0
, op1
)
9948 enum machine_mode mode
;
9954 if (GET_RTX_CLASS (code
) == 'c'
9955 && (GET_CODE (op0
) == CONST_INT
9956 || (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)))
9957 tem
= op0
, op0
= op1
, op1
= tem
;
9959 if (GET_RTX_CLASS (code
) == '<')
9961 enum machine_mode op_mode
= GET_MODE (op0
);
9963 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9964 just (REL_OP X Y). */
9965 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9967 op1
= XEXP (op0
, 1);
9968 op0
= XEXP (op0
, 0);
9969 op_mode
= GET_MODE (op0
);
9972 if (op_mode
== VOIDmode
)
9973 op_mode
= GET_MODE (op1
);
9974 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9977 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9982 /* Put complex operands first and constants second. */
9983 if (GET_RTX_CLASS (code
) == 'c'
9984 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
9985 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
9986 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
9987 || (GET_CODE (op0
) == SUBREG
9988 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
9989 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
9990 return gen_rtx_combine (code
, mode
, op1
, op0
);
9992 /* If we are turning off bits already known off in OP0, we need not do
9994 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9995 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9996 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9999 return gen_rtx_combine (code
, mode
, op0
, op1
);
10003 gen_unary (code
, mode
, op0_mode
, op0
)
10004 enum rtx_code code
;
10005 enum machine_mode mode
, op0_mode
;
10008 rtx result
= simplify_unary_operation (code
, mode
, op0
, op0_mode
);
10013 return gen_rtx_combine (code
, mode
, op0
);
10016 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10017 comparison code that will be tested.
10019 The result is a possibly different comparison code to use. *POP0 and
10020 *POP1 may be updated.
10022 It is possible that we might detect that a comparison is either always
10023 true or always false. However, we do not perform general constant
10024 folding in combine, so this knowledge isn't useful. Such tautologies
10025 should have been detected earlier. Hence we ignore all such cases. */
10027 static enum rtx_code
10028 simplify_comparison (code
, pop0
, pop1
)
10029 enum rtx_code code
;
10037 enum machine_mode mode
, tmode
;
10039 /* Try a few ways of applying the same transformation to both operands. */
10042 #ifndef WORD_REGISTER_OPERATIONS
10043 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10044 so check specially. */
10045 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10046 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10047 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10048 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10049 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10050 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10051 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10052 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10053 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10054 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
10055 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10056 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
10057 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
10058 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
10059 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
10060 && (INTVAL (XEXP (op0
, 1))
10061 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10062 - (GET_MODE_BITSIZE
10063 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10065 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10066 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10070 /* If both operands are the same constant shift, see if we can ignore the
10071 shift. We can if the shift is a rotate or if the bits shifted out of
10072 this shift are known to be zero for both inputs and if the type of
10073 comparison is compatible with the shift. */
10074 if (GET_CODE (op0
) == GET_CODE (op1
)
10075 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10076 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10077 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10078 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10079 || (GET_CODE (op0
) == ASHIFTRT
10080 && (code
!= GTU
&& code
!= LTU
10081 && code
!= GEU
&& code
!= GEU
)))
10082 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10083 && INTVAL (XEXP (op0
, 1)) >= 0
10084 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10085 && XEXP (op0
, 1) == XEXP (op1
, 1))
10087 enum machine_mode mode
= GET_MODE (op0
);
10088 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10089 int shift_count
= INTVAL (XEXP (op0
, 1));
10091 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10092 mask
&= (mask
>> shift_count
) << shift_count
;
10093 else if (GET_CODE (op0
) == ASHIFT
)
10094 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10096 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10097 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10098 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10103 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10104 SUBREGs are of the same mode, and, in both cases, the AND would
10105 be redundant if the comparison was done in the narrower mode,
10106 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10107 and the operand's possibly nonzero bits are 0xffffff01; in that case
10108 if we only care about QImode, we don't need the AND). This case
10109 occurs if the output mode of an scc insn is not SImode and
10110 STORE_FLAG_VALUE == 1 (e.g., the 386).
10112 Similarly, check for a case where the AND's are ZERO_EXTEND
10113 operations from some narrower mode even though a SUBREG is not
10116 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10117 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10118 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10120 rtx inner_op0
= XEXP (op0
, 0);
10121 rtx inner_op1
= XEXP (op1
, 0);
10122 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10123 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10126 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10127 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10128 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10129 && (GET_MODE (SUBREG_REG (inner_op0
))
10130 == GET_MODE (SUBREG_REG (inner_op1
)))
10131 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10132 <= HOST_BITS_PER_WIDE_INT
)
10133 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10134 GET_MODE (SUBREG_REG (inner_op0
)))))
10135 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10136 GET_MODE (SUBREG_REG (inner_op1
))))))
10138 op0
= SUBREG_REG (inner_op0
);
10139 op1
= SUBREG_REG (inner_op1
);
10141 /* The resulting comparison is always unsigned since we masked
10142 off the original sign bit. */
10143 code
= unsigned_condition (code
);
10149 for (tmode
= GET_CLASS_NARROWEST_MODE
10150 (GET_MODE_CLASS (GET_MODE (op0
)));
10151 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10152 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10154 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10155 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10156 code
= unsigned_condition (code
);
10165 /* If both operands are NOT, we can strip off the outer operation
10166 and adjust the comparison code for swapped operands; similarly for
10167 NEG, except that this must be an equality comparison. */
10168 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10169 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10170 && (code
== EQ
|| code
== NE
)))
10171 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10177 /* If the first operand is a constant, swap the operands and adjust the
10178 comparison code appropriately, but don't do this if the second operand
10179 is already a constant integer. */
10180 if (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
10182 tem
= op0
, op0
= op1
, op1
= tem
;
10183 code
= swap_condition (code
);
10186 /* We now enter a loop during which we will try to simplify the comparison.
10187 For the most part, we only are concerned with comparisons with zero,
10188 but some things may really be comparisons with zero but not start
10189 out looking that way. */
10191 while (GET_CODE (op1
) == CONST_INT
)
10193 enum machine_mode mode
= GET_MODE (op0
);
10194 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10195 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10196 int equality_comparison_p
;
10197 int sign_bit_comparison_p
;
10198 int unsigned_comparison_p
;
10199 HOST_WIDE_INT const_op
;
10201 /* We only want to handle integral modes. This catches VOIDmode,
10202 CCmode, and the floating-point modes. An exception is that we
10203 can handle VOIDmode if OP0 is a COMPARE or a comparison
10206 if (GET_MODE_CLASS (mode
) != MODE_INT
10207 && ! (mode
== VOIDmode
10208 && (GET_CODE (op0
) == COMPARE
10209 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10212 /* Get the constant we are comparing against and turn off all bits
10213 not on in our mode. */
10214 const_op
= trunc_int_for_mode (INTVAL (op1
), mode
);
10216 /* If we are comparing against a constant power of two and the value
10217 being compared can only have that single bit nonzero (e.g., it was
10218 `and'ed with that bit), we can replace this with a comparison
10221 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10222 || code
== LT
|| code
== LTU
)
10223 && mode_width
<= HOST_BITS_PER_WIDE_INT
10224 && exact_log2 (const_op
) >= 0
10225 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10227 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10228 op1
= const0_rtx
, const_op
= 0;
10231 /* Similarly, if we are comparing a value known to be either -1 or
10232 0 with -1, change it to the opposite comparison against zero. */
10235 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10236 || code
== GEU
|| code
== LTU
)
10237 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10239 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10240 op1
= const0_rtx
, const_op
= 0;
10243 /* Do some canonicalizations based on the comparison code. We prefer
10244 comparisons against zero and then prefer equality comparisons.
10245 If we can reduce the size of a constant, we will do that too. */
10250 /* < C is equivalent to <= (C - 1) */
10254 op1
= GEN_INT (const_op
);
10256 /* ... fall through to LE case below. */
10262 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10266 op1
= GEN_INT (const_op
);
10270 /* If we are doing a <= 0 comparison on a value known to have
10271 a zero sign bit, we can replace this with == 0. */
10272 else if (const_op
== 0
10273 && mode_width
<= HOST_BITS_PER_WIDE_INT
10274 && (nonzero_bits (op0
, mode
)
10275 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10280 /* >= C is equivalent to > (C - 1). */
10284 op1
= GEN_INT (const_op
);
10286 /* ... fall through to GT below. */
10292 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10296 op1
= GEN_INT (const_op
);
10300 /* If we are doing a > 0 comparison on a value known to have
10301 a zero sign bit, we can replace this with != 0. */
10302 else if (const_op
== 0
10303 && mode_width
<= HOST_BITS_PER_WIDE_INT
10304 && (nonzero_bits (op0
, mode
)
10305 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10310 /* < C is equivalent to <= (C - 1). */
10314 op1
= GEN_INT (const_op
);
10316 /* ... fall through ... */
10319 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10320 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10321 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10323 const_op
= 0, op1
= const0_rtx
;
10331 /* unsigned <= 0 is equivalent to == 0 */
10335 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10336 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10337 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10339 const_op
= 0, op1
= const0_rtx
;
10345 /* >= C is equivalent to < (C - 1). */
10349 op1
= GEN_INT (const_op
);
10351 /* ... fall through ... */
10354 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10355 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10356 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10358 const_op
= 0, op1
= const0_rtx
;
10366 /* unsigned > 0 is equivalent to != 0 */
10370 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10371 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10372 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10374 const_op
= 0, op1
= const0_rtx
;
10383 /* Compute some predicates to simplify code below. */
10385 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10386 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10387 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10390 /* If this is a sign bit comparison and we can do arithmetic in
10391 MODE, say that we will only be needing the sign bit of OP0. */
10392 if (sign_bit_comparison_p
10393 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10394 op0
= force_to_mode (op0
, mode
,
10396 << (GET_MODE_BITSIZE (mode
) - 1)),
10399 /* Now try cases based on the opcode of OP0. If none of the cases
10400 does a "continue", we exit this loop immediately after the
10403 switch (GET_CODE (op0
))
10406 /* If we are extracting a single bit from a variable position in
10407 a constant that has only a single bit set and are comparing it
10408 with zero, we can convert this into an equality comparison
10409 between the position and the location of the single bit. */
10411 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10412 && XEXP (op0
, 1) == const1_rtx
10413 && equality_comparison_p
&& const_op
== 0
10414 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10416 if (BITS_BIG_ENDIAN
)
10419 mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
10420 if (mode
== VOIDmode
)
10422 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10424 i
= BITS_PER_WORD
- 1 - i
;
10428 op0
= XEXP (op0
, 2);
10432 /* Result is nonzero iff shift count is equal to I. */
10433 code
= reverse_condition (code
);
10437 /* ... fall through ... */
10440 tem
= expand_compound_operation (op0
);
10449 /* If testing for equality, we can take the NOT of the constant. */
10450 if (equality_comparison_p
10451 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10453 op0
= XEXP (op0
, 0);
10458 /* If just looking at the sign bit, reverse the sense of the
10460 if (sign_bit_comparison_p
)
10462 op0
= XEXP (op0
, 0);
10463 code
= (code
== GE
? LT
: GE
);
10469 /* If testing for equality, we can take the NEG of the constant. */
10470 if (equality_comparison_p
10471 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10473 op0
= XEXP (op0
, 0);
10478 /* The remaining cases only apply to comparisons with zero. */
10482 /* When X is ABS or is known positive,
10483 (neg X) is < 0 if and only if X != 0. */
10485 if (sign_bit_comparison_p
10486 && (GET_CODE (XEXP (op0
, 0)) == ABS
10487 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10488 && (nonzero_bits (XEXP (op0
, 0), mode
)
10489 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10491 op0
= XEXP (op0
, 0);
10492 code
= (code
== LT
? NE
: EQ
);
10496 /* If we have NEG of something whose two high-order bits are the
10497 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10498 if (num_sign_bit_copies (op0
, mode
) >= 2)
10500 op0
= XEXP (op0
, 0);
10501 code
= swap_condition (code
);
10507 /* If we are testing equality and our count is a constant, we
10508 can perform the inverse operation on our RHS. */
10509 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10510 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10511 op1
, XEXP (op0
, 1))) != 0)
10513 op0
= XEXP (op0
, 0);
10518 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10519 a particular bit. Convert it to an AND of a constant of that
10520 bit. This will be converted into a ZERO_EXTRACT. */
10521 if (const_op
== 0 && sign_bit_comparison_p
10522 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10523 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10525 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10528 - INTVAL (XEXP (op0
, 1)))));
10529 code
= (code
== LT
? NE
: EQ
);
10533 /* Fall through. */
10536 /* ABS is ignorable inside an equality comparison with zero. */
10537 if (const_op
== 0 && equality_comparison_p
)
10539 op0
= XEXP (op0
, 0);
10545 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10546 to (compare FOO CONST) if CONST fits in FOO's mode and we
10547 are either testing inequality or have an unsigned comparison
10548 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10549 if (! unsigned_comparison_p
10550 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10551 <= HOST_BITS_PER_WIDE_INT
)
10552 && ((unsigned HOST_WIDE_INT
) const_op
10553 < (((unsigned HOST_WIDE_INT
) 1
10554 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10556 op0
= XEXP (op0
, 0);
10562 /* Check for the case where we are comparing A - C1 with C2,
10563 both constants are smaller than 1/2 the maximum positive
10564 value in MODE, and the comparison is equality or unsigned.
10565 In that case, if A is either zero-extended to MODE or has
10566 sufficient sign bits so that the high-order bit in MODE
10567 is a copy of the sign in the inner mode, we can prove that it is
10568 safe to do the operation in the wider mode. This simplifies
10569 many range checks. */
10571 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10572 && subreg_lowpart_p (op0
)
10573 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10574 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10575 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10576 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10577 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10578 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10579 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10580 GET_MODE (SUBREG_REG (op0
)))
10581 & ~GET_MODE_MASK (mode
))
10582 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10583 GET_MODE (SUBREG_REG (op0
)))
10584 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10585 - GET_MODE_BITSIZE (mode
)))))
10587 op0
= SUBREG_REG (op0
);
10591 /* If the inner mode is narrower and we are extracting the low part,
10592 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10593 if (subreg_lowpart_p (op0
)
10594 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10595 /* Fall through */ ;
10599 /* ... fall through ... */
10602 if ((unsigned_comparison_p
|| equality_comparison_p
)
10603 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10604 <= HOST_BITS_PER_WIDE_INT
)
10605 && ((unsigned HOST_WIDE_INT
) const_op
10606 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10608 op0
= XEXP (op0
, 0);
10614 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10615 this for equality comparisons due to pathological cases involving
10617 if (equality_comparison_p
10618 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10619 op1
, XEXP (op0
, 1))))
10621 op0
= XEXP (op0
, 0);
10626 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10627 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10628 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10630 op0
= XEXP (XEXP (op0
, 0), 0);
10631 code
= (code
== LT
? EQ
: NE
);
10637 /* We used to optimize signed comparisons against zero, but that
10638 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10639 arrive here as equality comparisons, or (GEU, LTU) are
10640 optimized away. No need to special-case them. */
10642 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10643 (eq B (minus A C)), whichever simplifies. We can only do
10644 this for equality comparisons due to pathological cases involving
10646 if (equality_comparison_p
10647 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10648 XEXP (op0
, 1), op1
)))
10650 op0
= XEXP (op0
, 0);
10655 if (equality_comparison_p
10656 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10657 XEXP (op0
, 0), op1
)))
10659 op0
= XEXP (op0
, 1);
10664 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10665 of bits in X minus 1, is one iff X > 0. */
10666 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10667 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10668 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10669 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10671 op0
= XEXP (op0
, 1);
10672 code
= (code
== GE
? LE
: GT
);
10678 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10679 if C is zero or B is a constant. */
10680 if (equality_comparison_p
10681 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10682 XEXP (op0
, 1), op1
)))
10684 op0
= XEXP (op0
, 0);
10691 case UNEQ
: case LTGT
:
10692 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10693 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10694 case UNORDERED
: case ORDERED
:
10695 /* We can't do anything if OP0 is a condition code value, rather
10696 than an actual data value. */
10699 || XEXP (op0
, 0) == cc0_rtx
10701 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10704 /* Get the two operands being compared. */
10705 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10706 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10708 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10710 /* Check for the cases where we simply want the result of the
10711 earlier test or the opposite of that result. */
10712 if (code
== NE
|| code
== EQ
10713 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10714 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10715 && (STORE_FLAG_VALUE
10716 & (((HOST_WIDE_INT
) 1
10717 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10718 && (code
== LT
|| code
== GE
)))
10720 enum rtx_code new_code
;
10721 if (code
== LT
|| code
== NE
)
10722 new_code
= GET_CODE (op0
);
10724 new_code
= combine_reversed_comparison_code (op0
);
10726 if (new_code
!= UNKNOWN
)
10737 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10739 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10740 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10741 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10743 op0
= XEXP (op0
, 1);
10744 code
= (code
== GE
? GT
: LE
);
10750 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10751 will be converted to a ZERO_EXTRACT later. */
10752 if (const_op
== 0 && equality_comparison_p
10753 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10754 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10756 op0
= simplify_and_const_int
10757 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10759 XEXP (XEXP (op0
, 0), 1)),
10760 (HOST_WIDE_INT
) 1);
10764 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10765 zero and X is a comparison and C1 and C2 describe only bits set
10766 in STORE_FLAG_VALUE, we can compare with X. */
10767 if (const_op
== 0 && equality_comparison_p
10768 && mode_width
<= HOST_BITS_PER_WIDE_INT
10769 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10770 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10771 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10772 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10773 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10775 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10776 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10777 if ((~STORE_FLAG_VALUE
& mask
) == 0
10778 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10779 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10780 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10782 op0
= XEXP (XEXP (op0
, 0), 0);
10787 /* If we are doing an equality comparison of an AND of a bit equal
10788 to the sign bit, replace this with a LT or GE comparison of
10789 the underlying value. */
10790 if (equality_comparison_p
10792 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10793 && mode_width
<= HOST_BITS_PER_WIDE_INT
10794 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10795 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10797 op0
= XEXP (op0
, 0);
10798 code
= (code
== EQ
? GE
: LT
);
10802 /* If this AND operation is really a ZERO_EXTEND from a narrower
10803 mode, the constant fits within that mode, and this is either an
10804 equality or unsigned comparison, try to do this comparison in
10805 the narrower mode. */
10806 if ((equality_comparison_p
|| unsigned_comparison_p
)
10807 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10808 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10809 & GET_MODE_MASK (mode
))
10811 && const_op
>> i
== 0
10812 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10814 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10818 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10819 in both M1 and M2 and the SUBREG is either paradoxical or
10820 represents the low part, permute the SUBREG and the AND and
10822 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10824 #ifdef WORD_REGISTER_OPERATIONS
10826 > (GET_MODE_BITSIZE
10827 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10828 && mode_width
<= BITS_PER_WORD
)
10831 <= (GET_MODE_BITSIZE
10832 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10833 && subreg_lowpart_p (XEXP (op0
, 0))))
10834 #ifndef WORD_REGISTER_OPERATIONS
10835 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10836 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10837 As originally written the upper bits have a defined value
10838 due to the AND operation. However, if we commute the AND
10839 inside the SUBREG then they no longer have defined values
10840 and the meaning of the code has been changed. */
10841 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10842 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10844 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10845 && mode_width
<= HOST_BITS_PER_WIDE_INT
10846 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10847 <= HOST_BITS_PER_WIDE_INT
)
10848 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10849 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10850 & INTVAL (XEXP (op0
, 1)))
10851 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10852 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10853 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10857 = gen_lowpart_for_combine
10859 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10860 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10864 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10865 (eq (and (lshiftrt X) 1) 0). */
10866 if (const_op
== 0 && equality_comparison_p
10867 && XEXP (op0
, 1) == const1_rtx
10868 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10869 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10871 op0
= simplify_and_const_int
10872 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10873 XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10874 XEXP (XEXP (op0
, 0), 1)),
10875 (HOST_WIDE_INT
) 1);
10876 code
= (code
== NE
? EQ
: NE
);
10882 /* If we have (compare (ashift FOO N) (const_int C)) and
10883 the high order N bits of FOO (N+1 if an inequality comparison)
10884 are known to be zero, we can do this by comparing FOO with C
10885 shifted right N bits so long as the low-order N bits of C are
10887 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10888 && INTVAL (XEXP (op0
, 1)) >= 0
10889 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10890 < HOST_BITS_PER_WIDE_INT
)
10892 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10893 && mode_width
<= HOST_BITS_PER_WIDE_INT
10894 && (nonzero_bits (XEXP (op0
, 0), mode
)
10895 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10896 + ! equality_comparison_p
))) == 0)
10898 /* We must perform a logical shift, not an arithmetic one,
10899 as we want the top N bits of C to be zero. */
10900 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10902 temp
>>= INTVAL (XEXP (op0
, 1));
10903 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10904 op0
= XEXP (op0
, 0);
10908 /* If we are doing a sign bit comparison, it means we are testing
10909 a particular bit. Convert it to the appropriate AND. */
10910 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10911 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10913 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10916 - INTVAL (XEXP (op0
, 1)))));
10917 code
= (code
== LT
? NE
: EQ
);
10921 /* If this an equality comparison with zero and we are shifting
10922 the low bit to the sign bit, we can convert this to an AND of the
10924 if (const_op
== 0 && equality_comparison_p
10925 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10926 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10928 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10929 (HOST_WIDE_INT
) 1);
10935 /* If this is an equality comparison with zero, we can do this
10936 as a logical shift, which might be much simpler. */
10937 if (equality_comparison_p
&& const_op
== 0
10938 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10940 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10942 INTVAL (XEXP (op0
, 1)));
10946 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10947 do the comparison in a narrower mode. */
10948 if (! unsigned_comparison_p
10949 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10950 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10951 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10952 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10953 MODE_INT
, 1)) != BLKmode
10954 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10955 || ((unsigned HOST_WIDE_INT
) -const_op
10956 <= GET_MODE_MASK (tmode
))))
10958 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10962 /* Likewise if OP0 is a PLUS of a sign extension with a
10963 constant, which is usually represented with the PLUS
10964 between the shifts. */
10965 if (! unsigned_comparison_p
10966 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10967 && GET_CODE (XEXP (op0
, 0)) == PLUS
10968 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10969 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10970 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10971 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10972 MODE_INT
, 1)) != BLKmode
10973 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10974 || ((unsigned HOST_WIDE_INT
) -const_op
10975 <= GET_MODE_MASK (tmode
))))
10977 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10978 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10979 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10982 op0
= gen_binary (PLUS
, tmode
,
10983 gen_lowpart_for_combine (tmode
, inner
),
10988 /* ... fall through ... */
10990 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10991 the low order N bits of FOO are known to be zero, we can do this
10992 by comparing FOO with C shifted left N bits so long as no
10993 overflow occurs. */
10994 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10995 && INTVAL (XEXP (op0
, 1)) >= 0
10996 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10997 && mode_width
<= HOST_BITS_PER_WIDE_INT
10998 && (nonzero_bits (XEXP (op0
, 0), mode
)
10999 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11001 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
11004 const_op
<<= INTVAL (XEXP (op0
, 1));
11005 op1
= GEN_INT (const_op
);
11006 op0
= XEXP (op0
, 0);
11010 /* If we are using this shift to extract just the sign bit, we
11011 can replace this with an LT or GE comparison. */
11013 && (equality_comparison_p
|| sign_bit_comparison_p
)
11014 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11015 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11017 op0
= XEXP (op0
, 0);
11018 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11030 /* Now make any compound operations involved in this comparison. Then,
11031 check for an outmost SUBREG on OP0 that is not doing anything or is
11032 paradoxical. The latter case can only occur when it is known that the
11033 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
11034 We can never remove a SUBREG for a non-equality comparison because the
11035 sign bit is in a different place in the underlying object. */
11037 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11038 op1
= make_compound_operation (op1
, SET
);
11040 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11041 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11042 && (code
== NE
|| code
== EQ
)
11043 && ((GET_MODE_SIZE (GET_MODE (op0
))
11044 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
11046 op0
= SUBREG_REG (op0
);
11047 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11050 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11051 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11052 && (code
== NE
|| code
== EQ
)
11053 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11054 <= HOST_BITS_PER_WIDE_INT
)
11055 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
11056 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0
11057 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
11059 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11060 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0))
11061 op0
= SUBREG_REG (op0
), op1
= tem
;
11063 /* We now do the opposite procedure: Some machines don't have compare
11064 insns in all modes. If OP0's mode is an integer mode smaller than a
11065 word and we can't do a compare in that mode, see if there is a larger
11066 mode for which we can do the compare. There are a number of cases in
11067 which we can use the wider mode. */
11069 mode
= GET_MODE (op0
);
11070 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11071 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11072 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
11073 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11075 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11076 tmode
= GET_MODE_WIDER_MODE (tmode
))
11077 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
11079 /* If the only nonzero bits in OP0 and OP1 are those in the
11080 narrower mode and this is an equality or unsigned comparison,
11081 we can use the wider mode. Similarly for sign-extended
11082 values, in which case it is true for all comparisons. */
11083 if (((code
== EQ
|| code
== NE
11084 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
11085 && (nonzero_bits (op0
, tmode
) & ~GET_MODE_MASK (mode
)) == 0
11086 && (nonzero_bits (op1
, tmode
) & ~GET_MODE_MASK (mode
)) == 0)
11087 || ((num_sign_bit_copies (op0
, tmode
)
11088 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
11089 && (num_sign_bit_copies (op1
, tmode
)
11090 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
11092 /* If OP0 is an AND and we don't have an AND in MODE either,
11093 make a new AND in the proper mode. */
11094 if (GET_CODE (op0
) == AND
11095 && (add_optab
->handlers
[(int) mode
].insn_code
11096 == CODE_FOR_nothing
))
11097 op0
= gen_binary (AND
, tmode
,
11098 gen_lowpart_for_combine (tmode
,
11100 gen_lowpart_for_combine (tmode
,
11103 op0
= gen_lowpart_for_combine (tmode
, op0
);
11104 op1
= gen_lowpart_for_combine (tmode
, op1
);
11108 /* If this is a test for negative, we can make an explicit
11109 test of the sign bit. */
11111 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11112 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11114 op0
= gen_binary (AND
, tmode
,
11115 gen_lowpart_for_combine (tmode
, op0
),
11116 GEN_INT ((HOST_WIDE_INT
) 1
11117 << (GET_MODE_BITSIZE (mode
) - 1)));
11118 code
= (code
== LT
) ? NE
: EQ
;
11123 #ifdef CANONICALIZE_COMPARISON
11124 /* If this machine only supports a subset of valid comparisons, see if we
11125 can convert an unsupported one into a supported one. */
11126 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11135 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11136 searching backward. */
11137 static enum rtx_code
11138 combine_reversed_comparison_code (exp
)
11141 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11144 if (code1
!= UNKNOWN
11145 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11147 /* Otherwise try and find where the condition codes were last set and
11149 x
= get_last_value (XEXP (exp
, 0));
11150 if (!x
|| GET_CODE (x
) != COMPARE
)
11152 return reversed_comparison_code_parts (GET_CODE (exp
),
11153 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11155 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11156 Return NULL_RTX in case we fail to do the reversal. */
11158 reversed_comparison (exp
, mode
, op0
, op1
)
11160 enum machine_mode mode
;
11162 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11163 if (reversed_code
== UNKNOWN
)
11166 return gen_binary (reversed_code
, mode
, op0
, op1
);
11169 /* Utility function for following routine. Called when X is part of a value
11170 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11171 for each register mentioned. Similar to mention_regs in cse.c */
11174 update_table_tick (x
)
11177 register enum rtx_code code
= GET_CODE (x
);
11178 register const char *fmt
= GET_RTX_FORMAT (code
);
11183 unsigned int regno
= REGNO (x
);
11184 unsigned int endregno
11185 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11186 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11189 for (r
= regno
; r
< endregno
; r
++)
11190 reg_last_set_table_tick
[r
] = label_tick
;
11195 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11196 /* Note that we can't have an "E" in values stored; see
11197 get_last_value_validate. */
11199 update_table_tick (XEXP (x
, i
));
11202 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11203 are saying that the register is clobbered and we no longer know its
11204 value. If INSN is zero, don't update reg_last_set; this is only permitted
11205 with VALUE also zero and is used to invalidate the register. */
11208 record_value_for_reg (reg
, insn
, value
)
11213 unsigned int regno
= REGNO (reg
);
11214 unsigned int endregno
11215 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11216 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11219 /* If VALUE contains REG and we have a previous value for REG, substitute
11220 the previous value. */
11221 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11225 /* Set things up so get_last_value is allowed to see anything set up to
11227 subst_low_cuid
= INSN_CUID (insn
);
11228 tem
= get_last_value (reg
);
11230 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11231 it isn't going to be useful and will take a lot of time to process,
11232 so just use the CLOBBER. */
11236 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11237 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11238 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11239 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11240 tem
= XEXP (tem
, 0);
11242 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11246 /* For each register modified, show we don't know its value, that
11247 we don't know about its bitwise content, that its value has been
11248 updated, and that we don't know the location of the death of the
11250 for (i
= regno
; i
< endregno
; i
++)
11253 reg_last_set
[i
] = insn
;
11255 reg_last_set_value
[i
] = 0;
11256 reg_last_set_mode
[i
] = 0;
11257 reg_last_set_nonzero_bits
[i
] = 0;
11258 reg_last_set_sign_bit_copies
[i
] = 0;
11259 reg_last_death
[i
] = 0;
11262 /* Mark registers that are being referenced in this value. */
11264 update_table_tick (value
);
11266 /* Now update the status of each register being set.
11267 If someone is using this register in this block, set this register
11268 to invalid since we will get confused between the two lives in this
11269 basic block. This makes using this register always invalid. In cse, we
11270 scan the table to invalidate all entries using this register, but this
11271 is too much work for us. */
11273 for (i
= regno
; i
< endregno
; i
++)
11275 reg_last_set_label
[i
] = label_tick
;
11276 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11277 reg_last_set_invalid
[i
] = 1;
11279 reg_last_set_invalid
[i
] = 0;
11282 /* The value being assigned might refer to X (like in "x++;"). In that
11283 case, we must replace it with (clobber (const_int 0)) to prevent
11285 if (value
&& ! get_last_value_validate (&value
, insn
,
11286 reg_last_set_label
[regno
], 0))
11288 value
= copy_rtx (value
);
11289 if (! get_last_value_validate (&value
, insn
,
11290 reg_last_set_label
[regno
], 1))
11294 /* For the main register being modified, update the value, the mode, the
11295 nonzero bits, and the number of sign bit copies. */
11297 reg_last_set_value
[regno
] = value
;
11301 subst_low_cuid
= INSN_CUID (insn
);
11302 reg_last_set_mode
[regno
] = GET_MODE (reg
);
11303 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
11304 reg_last_set_sign_bit_copies
[regno
]
11305 = num_sign_bit_copies (value
, GET_MODE (reg
));
11309 /* Called via note_stores from record_dead_and_set_regs to handle one
11310 SET or CLOBBER in an insn. DATA is the instruction in which the
11311 set is occurring. */
11314 record_dead_and_set_regs_1 (dest
, setter
, data
)
11318 rtx record_dead_insn
= (rtx
) data
;
11320 if (GET_CODE (dest
) == SUBREG
)
11321 dest
= SUBREG_REG (dest
);
11323 if (GET_CODE (dest
) == REG
)
11325 /* If we are setting the whole register, we know its value. Otherwise
11326 show that we don't know the value. We can handle SUBREG in
11328 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11329 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11330 else if (GET_CODE (setter
) == SET
11331 && GET_CODE (SET_DEST (setter
)) == SUBREG
11332 && SUBREG_REG (SET_DEST (setter
)) == dest
11333 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11334 && subreg_lowpart_p (SET_DEST (setter
)))
11335 record_value_for_reg (dest
, record_dead_insn
,
11336 gen_lowpart_for_combine (GET_MODE (dest
),
11337 SET_SRC (setter
)));
11339 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11341 else if (GET_CODE (dest
) == MEM
11342 /* Ignore pushes, they clobber nothing. */
11343 && ! push_operand (dest
, GET_MODE (dest
)))
11344 mem_last_set
= INSN_CUID (record_dead_insn
);
11347 /* Update the records of when each REG was most recently set or killed
11348 for the things done by INSN. This is the last thing done in processing
11349 INSN in the combiner loop.
11351 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11352 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11353 and also the similar information mem_last_set (which insn most recently
11354 modified memory) and last_call_cuid (which insn was the most recent
11355 subroutine call). */
11358 record_dead_and_set_regs (insn
)
11364 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11366 if (REG_NOTE_KIND (link
) == REG_DEAD
11367 && GET_CODE (XEXP (link
, 0)) == REG
)
11369 unsigned int regno
= REGNO (XEXP (link
, 0));
11370 unsigned int endregno
11371 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11372 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11375 for (i
= regno
; i
< endregno
; i
++)
11376 reg_last_death
[i
] = insn
;
11378 else if (REG_NOTE_KIND (link
) == REG_INC
)
11379 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11382 if (GET_CODE (insn
) == CALL_INSN
)
11384 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11385 if (call_used_regs
[i
])
11387 reg_last_set_value
[i
] = 0;
11388 reg_last_set_mode
[i
] = 0;
11389 reg_last_set_nonzero_bits
[i
] = 0;
11390 reg_last_set_sign_bit_copies
[i
] = 0;
11391 reg_last_death
[i
] = 0;
11394 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11397 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11400 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11401 register present in the SUBREG, so for each such SUBREG go back and
11402 adjust nonzero and sign bit information of the registers that are
11403 known to have some zero/sign bits set.
11405 This is needed because when combine blows the SUBREGs away, the
11406 information on zero/sign bits is lost and further combines can be
11407 missed because of that. */
11410 record_promoted_value (insn
, subreg
)
11415 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11416 enum machine_mode mode
= GET_MODE (subreg
);
11418 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11421 for (links
= LOG_LINKS (insn
); links
;)
11423 insn
= XEXP (links
, 0);
11424 set
= single_set (insn
);
11426 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11427 || REGNO (SET_DEST (set
)) != regno
11428 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11430 links
= XEXP (links
, 1);
11434 if (reg_last_set
[regno
] == insn
)
11436 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
11437 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11440 if (GET_CODE (SET_SRC (set
)) == REG
)
11442 regno
= REGNO (SET_SRC (set
));
11443 links
= LOG_LINKS (insn
);
11450 /* Scan X for promoted SUBREGs. For each one found,
11451 note what it implies to the registers used in it. */
11454 check_promoted_subreg (insn
, x
)
11458 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11459 && GET_CODE (SUBREG_REG (x
)) == REG
)
11460 record_promoted_value (insn
, x
);
11463 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11466 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11470 check_promoted_subreg (insn
, XEXP (x
, i
));
11474 if (XVEC (x
, i
) != 0)
11475 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11476 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11482 /* Utility routine for the following function. Verify that all the registers
11483 mentioned in *LOC are valid when *LOC was part of a value set when
11484 label_tick == TICK. Return 0 if some are not.
11486 If REPLACE is non-zero, replace the invalid reference with
11487 (clobber (const_int 0)) and return 1. This replacement is useful because
11488 we often can get useful information about the form of a value (e.g., if
11489 it was produced by a shift that always produces -1 or 0) even though
11490 we don't know exactly what registers it was produced from. */
11493 get_last_value_validate (loc
, insn
, tick
, replace
)
11500 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11501 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11504 if (GET_CODE (x
) == REG
)
11506 unsigned int regno
= REGNO (x
);
11507 unsigned int endregno
11508 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11509 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11512 for (j
= regno
; j
< endregno
; j
++)
11513 if (reg_last_set_invalid
[j
]
11514 /* If this is a pseudo-register that was only set once and not
11515 live at the beginning of the function, it is always valid. */
11516 || (! (regno
>= FIRST_PSEUDO_REGISTER
11517 && REG_N_SETS (regno
) == 1
11518 && (! REGNO_REG_SET_P
11519 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))
11520 && reg_last_set_label
[j
] > tick
))
11523 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11529 /* If this is a memory reference, make sure that there were
11530 no stores after it that might have clobbered the value. We don't
11531 have alias info, so we assume any store invalidates it. */
11532 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11533 && INSN_CUID (insn
) <= mem_last_set
)
11536 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11540 for (i
= 0; i
< len
; i
++)
11542 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11543 /* Don't bother with these. They shouldn't occur anyway. */
11547 /* If we haven't found a reason for it to be invalid, it is valid. */
11551 /* Get the last value assigned to X, if known. Some registers
11552 in the value may be replaced with (clobber (const_int 0)) if their value
11553 is known longer known reliably. */
11559 unsigned int regno
;
11562 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11563 then convert it to the desired mode. If this is a paradoxical SUBREG,
11564 we cannot predict what values the "extra" bits might have. */
11565 if (GET_CODE (x
) == SUBREG
11566 && subreg_lowpart_p (x
)
11567 && (GET_MODE_SIZE (GET_MODE (x
))
11568 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11569 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11570 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11572 if (GET_CODE (x
) != REG
)
11576 value
= reg_last_set_value
[regno
];
11578 /* If we don't have a value, or if it isn't for this basic block and
11579 it's either a hard register, set more than once, or it's a live
11580 at the beginning of the function, return 0.
11582 Because if it's not live at the beginnning of the function then the reg
11583 is always set before being used (is never used without being set).
11584 And, if it's set only once, and it's always set before use, then all
11585 uses must have the same last value, even if it's not from this basic
11589 || (reg_last_set_label
[regno
] != label_tick
11590 && (regno
< FIRST_PSEUDO_REGISTER
11591 || REG_N_SETS (regno
) != 1
11592 || (REGNO_REG_SET_P
11593 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))))
11596 /* If the value was set in a later insn than the ones we are processing,
11597 we can't use it even if the register was only set once. */
11598 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11601 /* If the value has all its registers valid, return it. */
11602 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11603 reg_last_set_label
[regno
], 0))
11606 /* Otherwise, make a copy and replace any invalid register with
11607 (clobber (const_int 0)). If that fails for some reason, return 0. */
11609 value
= copy_rtx (value
);
11610 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11611 reg_last_set_label
[regno
], 1))
11617 /* Return nonzero if expression X refers to a REG or to memory
11618 that is set in an instruction more recent than FROM_CUID. */
11621 use_crosses_set_p (x
, from_cuid
)
11625 register const char *fmt
;
11627 register enum rtx_code code
= GET_CODE (x
);
11631 unsigned int regno
= REGNO (x
);
11632 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11633 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11635 #ifdef PUSH_ROUNDING
11636 /* Don't allow uses of the stack pointer to be moved,
11637 because we don't know whether the move crosses a push insn. */
11638 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11641 for (; regno
< endreg
; regno
++)
11642 if (reg_last_set
[regno
]
11643 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11648 if (code
== MEM
&& mem_last_set
> from_cuid
)
11651 fmt
= GET_RTX_FORMAT (code
);
11653 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11658 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11659 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11662 else if (fmt
[i
] == 'e'
11663 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11669 /* Define three variables used for communication between the following
11672 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11673 static int reg_dead_flag
;
11675 /* Function called via note_stores from reg_dead_at_p.
11677 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11678 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11681 reg_dead_at_p_1 (dest
, x
, data
)
11684 void *data ATTRIBUTE_UNUSED
;
11686 unsigned int regno
, endregno
;
11688 if (GET_CODE (dest
) != REG
)
11691 regno
= REGNO (dest
);
11692 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11693 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11695 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11696 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11699 /* Return non-zero if REG is known to be dead at INSN.
11701 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11702 referencing REG, it is dead. If we hit a SET referencing REG, it is
11703 live. Otherwise, see if it is live or dead at the start of the basic
11704 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11705 must be assumed to be always live. */
11708 reg_dead_at_p (reg
, insn
)
11715 /* Set variables for reg_dead_at_p_1. */
11716 reg_dead_regno
= REGNO (reg
);
11717 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11718 ? HARD_REGNO_NREGS (reg_dead_regno
,
11724 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11725 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11727 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11728 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11732 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11733 beginning of function. */
11734 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11735 insn
= prev_nonnote_insn (insn
))
11737 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11739 return reg_dead_flag
== 1 ? 1 : 0;
11741 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11745 /* Get the basic block number that we were in. */
11750 for (block
= 0; block
< n_basic_blocks
; block
++)
11751 if (insn
== BLOCK_HEAD (block
))
11754 if (block
== n_basic_blocks
)
11758 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11759 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11765 /* Note hard registers in X that are used. This code is similar to
11766 that in flow.c, but much simpler since we don't care about pseudos. */
11769 mark_used_regs_combine (x
)
11772 RTX_CODE code
= GET_CODE (x
);
11773 unsigned int regno
;
11785 case ADDR_DIFF_VEC
:
11788 /* CC0 must die in the insn after it is set, so we don't need to take
11789 special note of it here. */
11795 /* If we are clobbering a MEM, mark any hard registers inside the
11796 address as used. */
11797 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11798 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11803 /* A hard reg in a wide mode may really be multiple registers.
11804 If so, mark all of them just like the first. */
11805 if (regno
< FIRST_PSEUDO_REGISTER
)
11807 unsigned int endregno
, r
;
11809 /* None of this applies to the stack, frame or arg pointers */
11810 if (regno
== STACK_POINTER_REGNUM
11811 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11812 || regno
== HARD_FRAME_POINTER_REGNUM
11814 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11815 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11817 || regno
== FRAME_POINTER_REGNUM
)
11820 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11821 for (r
= regno
; r
< endregno
; r
++)
11822 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11828 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11830 register rtx testreg
= SET_DEST (x
);
11832 while (GET_CODE (testreg
) == SUBREG
11833 || GET_CODE (testreg
) == ZERO_EXTRACT
11834 || GET_CODE (testreg
) == SIGN_EXTRACT
11835 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11836 testreg
= XEXP (testreg
, 0);
11838 if (GET_CODE (testreg
) == MEM
)
11839 mark_used_regs_combine (XEXP (testreg
, 0));
11841 mark_used_regs_combine (SET_SRC (x
));
11849 /* Recursively scan the operands of this expression. */
11852 register const char *fmt
= GET_RTX_FORMAT (code
);
11854 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11857 mark_used_regs_combine (XEXP (x
, i
));
11858 else if (fmt
[i
] == 'E')
11862 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11863 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11869 /* Remove register number REGNO from the dead registers list of INSN.
11871 Return the note used to record the death, if there was one. */
11874 remove_death (regno
, insn
)
11875 unsigned int regno
;
11878 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11882 REG_N_DEATHS (regno
)--;
11883 remove_note (insn
, note
);
11889 /* For each register (hardware or pseudo) used within expression X, if its
11890 death is in an instruction with cuid between FROM_CUID (inclusive) and
11891 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11892 list headed by PNOTES.
11894 That said, don't move registers killed by maybe_kill_insn.
11896 This is done when X is being merged by combination into TO_INSN. These
11897 notes will then be distributed as needed. */
11900 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11902 rtx maybe_kill_insn
;
11907 register const char *fmt
;
11908 register int len
, i
;
11909 register enum rtx_code code
= GET_CODE (x
);
11913 unsigned int regno
= REGNO (x
);
11914 register rtx where_dead
= reg_last_death
[regno
];
11915 register rtx before_dead
, after_dead
;
11917 /* Don't move the register if it gets killed in between from and to */
11918 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11919 && ! reg_referenced_p (x
, maybe_kill_insn
))
11922 /* WHERE_DEAD could be a USE insn made by combine, so first we
11923 make sure that we have insns with valid INSN_CUID values. */
11924 before_dead
= where_dead
;
11925 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11926 before_dead
= PREV_INSN (before_dead
);
11928 after_dead
= where_dead
;
11929 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11930 after_dead
= NEXT_INSN (after_dead
);
11932 if (before_dead
&& after_dead
11933 && INSN_CUID (before_dead
) >= from_cuid
11934 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11935 || (where_dead
!= after_dead
11936 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11938 rtx note
= remove_death (regno
, where_dead
);
11940 /* It is possible for the call above to return 0. This can occur
11941 when reg_last_death points to I2 or I1 that we combined with.
11942 In that case make a new note.
11944 We must also check for the case where X is a hard register
11945 and NOTE is a death note for a range of hard registers
11946 including X. In that case, we must put REG_DEAD notes for
11947 the remaining registers in place of NOTE. */
11949 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11950 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11951 > GET_MODE_SIZE (GET_MODE (x
))))
11953 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11954 unsigned int deadend
11955 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11956 GET_MODE (XEXP (note
, 0))));
11957 unsigned int ourend
11958 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11961 for (i
= deadregno
; i
< deadend
; i
++)
11962 if (i
< regno
|| i
>= ourend
)
11963 REG_NOTES (where_dead
)
11964 = gen_rtx_EXPR_LIST (REG_DEAD
,
11965 gen_rtx_REG (reg_raw_mode
[i
], i
),
11966 REG_NOTES (where_dead
));
11969 /* If we didn't find any note, or if we found a REG_DEAD note that
11970 covers only part of the given reg, and we have a multi-reg hard
11971 register, then to be safe we must check for REG_DEAD notes
11972 for each register other than the first. They could have
11973 their own REG_DEAD notes lying around. */
11974 else if ((note
== 0
11976 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11977 < GET_MODE_SIZE (GET_MODE (x
)))))
11978 && regno
< FIRST_PSEUDO_REGISTER
11979 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11981 unsigned int ourend
11982 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11983 unsigned int i
, offset
;
11987 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11991 for (i
= regno
+ offset
; i
< ourend
; i
++)
11992 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11993 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11996 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11998 XEXP (note
, 1) = *pnotes
;
12002 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12004 REG_N_DEATHS (regno
)++;
12010 else if (GET_CODE (x
) == SET
)
12012 rtx dest
= SET_DEST (x
);
12014 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12016 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12017 that accesses one word of a multi-word item, some
12018 piece of everything register in the expression is used by
12019 this insn, so remove any old death. */
12021 if (GET_CODE (dest
) == ZERO_EXTRACT
12022 || GET_CODE (dest
) == STRICT_LOW_PART
12023 || (GET_CODE (dest
) == SUBREG
12024 && (((GET_MODE_SIZE (GET_MODE (dest
))
12025 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12026 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12027 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12029 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12033 /* If this is some other SUBREG, we know it replaces the entire
12034 value, so use that as the destination. */
12035 if (GET_CODE (dest
) == SUBREG
)
12036 dest
= SUBREG_REG (dest
);
12038 /* If this is a MEM, adjust deaths of anything used in the address.
12039 For a REG (the only other possibility), the entire value is
12040 being replaced so the old value is not used in this insn. */
12042 if (GET_CODE (dest
) == MEM
)
12043 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12048 else if (GET_CODE (x
) == CLOBBER
)
12051 len
= GET_RTX_LENGTH (code
);
12052 fmt
= GET_RTX_FORMAT (code
);
12054 for (i
= 0; i
< len
; i
++)
12059 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12060 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12063 else if (fmt
[i
] == 'e')
12064 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12068 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12069 pattern of an insn. X must be a REG. */
12072 reg_bitfield_target_p (x
, body
)
12078 if (GET_CODE (body
) == SET
)
12080 rtx dest
= SET_DEST (body
);
12082 unsigned int regno
, tregno
, endregno
, endtregno
;
12084 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12085 target
= XEXP (dest
, 0);
12086 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12087 target
= SUBREG_REG (XEXP (dest
, 0));
12091 if (GET_CODE (target
) == SUBREG
)
12092 target
= SUBREG_REG (target
);
12094 if (GET_CODE (target
) != REG
)
12097 tregno
= REGNO (target
), regno
= REGNO (x
);
12098 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12099 return target
== x
;
12101 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12102 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12104 return endregno
> tregno
&& regno
< endtregno
;
12107 else if (GET_CODE (body
) == PARALLEL
)
12108 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12109 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12115 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12116 as appropriate. I3 and I2 are the insns resulting from the combination
12117 insns including FROM (I2 may be zero).
12119 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12120 not need REG_DEAD notes because they are being substituted for. This
12121 saves searching in the most common cases.
12123 Each note in the list is either ignored or placed on some insns, depending
12124 on the type of note. */
12127 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
12131 rtx elim_i2
, elim_i1
;
12133 rtx note
, next_note
;
12136 for (note
= notes
; note
; note
= next_note
)
12138 rtx place
= 0, place2
= 0;
12140 /* If this NOTE references a pseudo register, ensure it references
12141 the latest copy of that register. */
12142 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12143 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12144 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12146 next_note
= XEXP (note
, 1);
12147 switch (REG_NOTE_KIND (note
))
12150 case REG_EXEC_COUNT
:
12151 /* Doesn't matter much where we put this, as long as it's somewhere.
12152 It is preferable to keep these notes on branches, which is most
12153 likely to be i3. */
12157 case REG_NON_LOCAL_GOTO
:
12158 if (GET_CODE (i3
) == JUMP_INSN
)
12160 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12166 case REG_EH_REGION
:
12167 case REG_EH_RETHROW
:
12169 /* These notes must remain with the call. It should not be
12170 possible for both I2 and I3 to be a call. */
12171 if (GET_CODE (i3
) == CALL_INSN
)
12173 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12180 /* Any clobbers for i3 may still exist, and so we must process
12181 REG_UNUSED notes from that insn.
12183 Any clobbers from i2 or i1 can only exist if they were added by
12184 recog_for_combine. In that case, recog_for_combine created the
12185 necessary REG_UNUSED notes. Trying to keep any original
12186 REG_UNUSED notes from these insns can cause incorrect output
12187 if it is for the same register as the original i3 dest.
12188 In that case, we will notice that the register is set in i3,
12189 and then add a REG_UNUSED note for the destination of i3, which
12190 is wrong. However, it is possible to have REG_UNUSED notes from
12191 i2 or i1 for register which were both used and clobbered, so
12192 we keep notes from i2 or i1 if they will turn into REG_DEAD
12195 /* If this register is set or clobbered in I3, put the note there
12196 unless there is one already. */
12197 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12199 if (from_insn
!= i3
)
12202 if (! (GET_CODE (XEXP (note
, 0)) == REG
12203 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12204 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12207 /* Otherwise, if this register is used by I3, then this register
12208 now dies here, so we must put a REG_DEAD note here unless there
12210 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12211 && ! (GET_CODE (XEXP (note
, 0)) == REG
12212 ? find_regno_note (i3
, REG_DEAD
,
12213 REGNO (XEXP (note
, 0)))
12214 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12216 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12224 /* These notes say something about results of an insn. We can
12225 only support them if they used to be on I3 in which case they
12226 remain on I3. Otherwise they are ignored.
12228 If the note refers to an expression that is not a constant, we
12229 must also ignore the note since we cannot tell whether the
12230 equivalence is still true. It might be possible to do
12231 slightly better than this (we only have a problem if I2DEST
12232 or I1DEST is present in the expression), but it doesn't
12233 seem worth the trouble. */
12235 if (from_insn
== i3
12236 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12241 case REG_NO_CONFLICT
:
12242 /* These notes say something about how a register is used. They must
12243 be present on any use of the register in I2 or I3. */
12244 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12247 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12257 /* This can show up in several ways -- either directly in the
12258 pattern, or hidden off in the constant pool with (or without?)
12259 a REG_EQUAL note. */
12260 /* ??? Ignore the without-reg_equal-note problem for now. */
12261 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12262 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12263 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12264 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12268 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12269 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12270 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12271 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12282 /* These notes say something about the value of a register prior
12283 to the execution of an insn. It is too much trouble to see
12284 if the note is still correct in all situations. It is better
12285 to simply delete it. */
12289 /* If the insn previously containing this note still exists,
12290 put it back where it was. Otherwise move it to the previous
12291 insn. Adjust the corresponding REG_LIBCALL note. */
12292 if (GET_CODE (from_insn
) != NOTE
)
12296 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12297 place
= prev_real_insn (from_insn
);
12299 XEXP (tem
, 0) = place
;
12300 /* If we're deleting the last remaining instruction of a
12301 libcall sequence, don't add the notes. */
12302 else if (XEXP (note
, 0) == from_insn
)
12308 /* This is handled similarly to REG_RETVAL. */
12309 if (GET_CODE (from_insn
) != NOTE
)
12313 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12314 place
= next_real_insn (from_insn
);
12316 XEXP (tem
, 0) = place
;
12317 /* If we're deleting the last remaining instruction of a
12318 libcall sequence, don't add the notes. */
12319 else if (XEXP (note
, 0) == from_insn
)
12325 /* If the register is used as an input in I3, it dies there.
12326 Similarly for I2, if it is non-zero and adjacent to I3.
12328 If the register is not used as an input in either I3 or I2
12329 and it is not one of the registers we were supposed to eliminate,
12330 there are two possibilities. We might have a non-adjacent I2
12331 or we might have somehow eliminated an additional register
12332 from a computation. For example, we might have had A & B where
12333 we discover that B will always be zero. In this case we will
12334 eliminate the reference to A.
12336 In both cases, we must search to see if we can find a previous
12337 use of A and put the death note there. */
12340 && GET_CODE (from_insn
) == CALL_INSN
12341 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12343 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12345 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12346 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12349 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12350 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12355 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12357 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12359 if (! INSN_P (tem
))
12361 if (tem
== bb
->head
)
12366 /* If the register is being set at TEM, see if that is all
12367 TEM is doing. If so, delete TEM. Otherwise, make this
12368 into a REG_UNUSED note instead. */
12369 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12371 rtx set
= single_set (tem
);
12372 rtx inner_dest
= 0;
12374 rtx cc0_setter
= NULL_RTX
;
12378 for (inner_dest
= SET_DEST (set
);
12379 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12380 || GET_CODE (inner_dest
) == SUBREG
12381 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12382 inner_dest
= XEXP (inner_dest
, 0))
12385 /* Verify that it was the set, and not a clobber that
12386 modified the register.
12388 CC0 targets must be careful to maintain setter/user
12389 pairs. If we cannot delete the setter due to side
12390 effects, mark the user with an UNUSED note instead
12393 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12394 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12396 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12397 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12398 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12402 /* Move the notes and links of TEM elsewhere.
12403 This might delete other dead insns recursively.
12404 First set the pattern to something that won't use
12407 PATTERN (tem
) = pc_rtx
;
12409 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12410 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12411 distribute_links (LOG_LINKS (tem
));
12413 PUT_CODE (tem
, NOTE
);
12414 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12415 NOTE_SOURCE_FILE (tem
) = 0;
12418 /* Delete the setter too. */
12421 PATTERN (cc0_setter
) = pc_rtx
;
12423 distribute_notes (REG_NOTES (cc0_setter
),
12424 cc0_setter
, cc0_setter
,
12425 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12426 distribute_links (LOG_LINKS (cc0_setter
));
12428 PUT_CODE (cc0_setter
, NOTE
);
12429 NOTE_LINE_NUMBER (cc0_setter
)
12430 = NOTE_INSN_DELETED
;
12431 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12435 /* If the register is both set and used here, put the
12436 REG_DEAD note here, but place a REG_UNUSED note
12437 here too unless there already is one. */
12438 else if (reg_referenced_p (XEXP (note
, 0),
12443 if (! find_regno_note (tem
, REG_UNUSED
,
12444 REGNO (XEXP (note
, 0))))
12446 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12451 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12453 /* If there isn't already a REG_UNUSED note, put one
12455 if (! find_regno_note (tem
, REG_UNUSED
,
12456 REGNO (XEXP (note
, 0))))
12461 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12462 || (GET_CODE (tem
) == CALL_INSN
12463 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12467 /* If we are doing a 3->2 combination, and we have a
12468 register which formerly died in i3 and was not used
12469 by i2, which now no longer dies in i3 and is used in
12470 i2 but does not die in i2, and place is between i2
12471 and i3, then we may need to move a link from place to
12473 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12474 && INSN_CUID (place
) > INSN_CUID (i2
)
12476 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12477 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12479 rtx links
= LOG_LINKS (place
);
12480 LOG_LINKS (place
) = 0;
12481 distribute_links (links
);
12486 if (tem
== bb
->head
)
12490 /* We haven't found an insn for the death note and it
12491 is still a REG_DEAD note, but we have hit the beginning
12492 of the block. If the existing life info says the reg
12493 was dead, there's nothing left to do. Otherwise, we'll
12494 need to do a global life update after combine. */
12495 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12496 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12497 REGNO (XEXP (note
, 0))))
12499 SET_BIT (refresh_blocks
, this_basic_block
);
12504 /* If the register is set or already dead at PLACE, we needn't do
12505 anything with this note if it is still a REG_DEAD note.
12506 We can here if it is set at all, not if is it totally replace,
12507 which is what `dead_or_set_p' checks, so also check for it being
12510 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12512 unsigned int regno
= REGNO (XEXP (note
, 0));
12514 if (dead_or_set_p (place
, XEXP (note
, 0))
12515 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12517 /* Unless the register previously died in PLACE, clear
12518 reg_last_death. [I no longer understand why this is
12520 if (reg_last_death
[regno
] != place
)
12521 reg_last_death
[regno
] = 0;
12525 reg_last_death
[regno
] = place
;
12527 /* If this is a death note for a hard reg that is occupying
12528 multiple registers, ensure that we are still using all
12529 parts of the object. If we find a piece of the object
12530 that is unused, we must arrange for an appropriate REG_DEAD
12531 note to be added for it. However, we can't just emit a USE
12532 and tag the note to it, since the register might actually
12533 be dead; so we recourse, and the recursive call then finds
12534 the previous insn that used this register. */
12536 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12537 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12539 unsigned int endregno
12540 = regno
+ HARD_REGNO_NREGS (regno
,
12541 GET_MODE (XEXP (note
, 0)));
12545 for (i
= regno
; i
< endregno
; i
++)
12546 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12547 && ! find_regno_fusage (place
, USE
, i
))
12548 || dead_or_set_regno_p (place
, i
))
12553 /* Put only REG_DEAD notes for pieces that are
12554 not already dead or set. */
12556 for (i
= regno
; i
< endregno
;
12557 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12559 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12560 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12562 if (! dead_or_set_p (place
, piece
)
12563 && ! reg_bitfield_target_p (piece
,
12567 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12569 distribute_notes (new_note
, place
, place
,
12570 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12572 else if (! refers_to_regno_p (i
, i
+ 1,
12573 PATTERN (place
), 0)
12574 && ! find_regno_fusage (place
, USE
, i
))
12575 for (tem
= PREV_INSN (place
); ;
12576 tem
= PREV_INSN (tem
))
12578 if (! INSN_P (tem
))
12580 if (tem
== bb
->head
)
12582 SET_BIT (refresh_blocks
,
12589 if (dead_or_set_p (tem
, piece
)
12590 || reg_bitfield_target_p (piece
,
12594 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12609 /* Any other notes should not be present at this point in the
12616 XEXP (note
, 1) = REG_NOTES (place
);
12617 REG_NOTES (place
) = note
;
12619 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12620 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12621 && GET_CODE (XEXP (note
, 0)) == REG
)
12622 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12626 if ((REG_NOTE_KIND (note
) == REG_DEAD
12627 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12628 && GET_CODE (XEXP (note
, 0)) == REG
)
12629 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12631 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12632 REG_NOTE_KIND (note
),
12634 REG_NOTES (place2
));
12639 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12640 I3, I2, and I1 to new locations. This is also called in one case to
12641 add a link pointing at I3 when I3's destination is changed. */
12644 distribute_links (links
)
12647 rtx link
, next_link
;
12649 for (link
= links
; link
; link
= next_link
)
12655 next_link
= XEXP (link
, 1);
12657 /* If the insn that this link points to is a NOTE or isn't a single
12658 set, ignore it. In the latter case, it isn't clear what we
12659 can do other than ignore the link, since we can't tell which
12660 register it was for. Such links wouldn't be used by combine
12663 It is not possible for the destination of the target of the link to
12664 have been changed by combine. The only potential of this is if we
12665 replace I3, I2, and I1 by I3 and I2. But in that case the
12666 destination of I2 also remains unchanged. */
12668 if (GET_CODE (XEXP (link
, 0)) == NOTE
12669 || (set
= single_set (XEXP (link
, 0))) == 0)
12672 reg
= SET_DEST (set
);
12673 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12674 || GET_CODE (reg
) == SIGN_EXTRACT
12675 || GET_CODE (reg
) == STRICT_LOW_PART
)
12676 reg
= XEXP (reg
, 0);
12678 /* A LOG_LINK is defined as being placed on the first insn that uses
12679 a register and points to the insn that sets the register. Start
12680 searching at the next insn after the target of the link and stop
12681 when we reach a set of the register or the end of the basic block.
12683 Note that this correctly handles the link that used to point from
12684 I3 to I2. Also note that not much searching is typically done here
12685 since most links don't point very far away. */
12687 for (insn
= NEXT_INSN (XEXP (link
, 0));
12688 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12689 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12690 insn
= NEXT_INSN (insn
))
12691 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12693 if (reg_referenced_p (reg
, PATTERN (insn
)))
12697 else if (GET_CODE (insn
) == CALL_INSN
12698 && find_reg_fusage (insn
, USE
, reg
))
12704 /* If we found a place to put the link, place it there unless there
12705 is already a link to the same insn as LINK at that point. */
12711 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12712 if (XEXP (link2
, 0) == XEXP (link
, 0))
12717 XEXP (link
, 1) = LOG_LINKS (place
);
12718 LOG_LINKS (place
) = link
;
12720 /* Set added_links_insn to the earliest insn we added a
12722 if (added_links_insn
== 0
12723 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12724 added_links_insn
= place
;
12730 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12736 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12737 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12738 insn
= NEXT_INSN (insn
);
12740 if (INSN_UID (insn
) > max_uid_cuid
)
12743 return INSN_CUID (insn
);
12747 dump_combine_stats (file
)
12752 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12753 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12757 dump_combine_total_stats (file
)
12762 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12763 total_attempts
, total_merges
, total_extras
, total_successes
);