| blob | e5ca5eb0ad77ad47b52f70c1b8af98da83251e2c |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
68 /* This file should be included last. */
71 /* Defined for convenience. */
72 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
74 /* Classifies an address.
76 ADDRESS_REG_IMM
77 A simple base register plus immediate offset.
79 ADDRESS_REG_WB
80 A base register indexed by immediate offset with writeback.
82 ADDRESS_REG_REG
83 A base register indexed by (optionally scaled) register.
85 ADDRESS_REG_UXTW
86 A base register indexed by (optionally scaled) zero-extended register.
88 ADDRESS_REG_SXTW
89 A base register indexed by (optionally scaled) sign-extended register.
91 ADDRESS_LO_SUM
92 A LO_SUM rtx with a base register and "LO12" symbol relocation.
94 ADDRESS_SYMBOLIC:
95 A constant symbolic address, in pc-relative literal pool. */
98 ADDRESS_REG_IMM,
99 ADDRESS_REG_WB,
100 ADDRESS_REG_REG,
101 ADDRESS_REG_UXTW,
102 ADDRESS_REG_SXTW,
103 ADDRESS_LO_SUM,
104 ADDRESS_SYMBOLIC
105 };
109 rtx base;
110 rtx offset;
113 };
115 struct simd_immediate_info
116 {
117 rtx value;
122 };
124 /* The current code model. */
127 #ifdef HAVE_AS_TLS
128 #undef TARGET_HAVE_TLS
129 #define TARGET_HAVE_TLS 1
130 #endif
134 const_tree,
145 /* Major revision number of the ARM Architecture implemented by the target. */
148 /* The processor for which instructions should be scheduled. */
151 /* Mask to specify which instruction scheduling options should be used. */
154 /* Global flag for PC relative loads. */
157 /* Support for command line parsing of boolean flags in the tuning
158 structures. */
159 struct aarch64_flag_desc
160 {
163 };
165 #define AARCH64_FUSION_PAIR(name, internal_name) \
166 { name, AARCH64_FUSE_##internal_name },
168 {
173 };
175 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
176 { name, AARCH64_EXTRA_TUNE_##internal_name },
178 {
183 };
185 /* Tuning parameters. */
188 {
189 {
194 },
201 };
204 {
205 {
210 },
217 };
220 {
221 {
226 },
233 };
236 {
237 {
242 },
249 };
252 {
253 {
258 },
265 };
268 {
269 {
274 },
281 };
284 {
286 /* Avoid the use of slow int<->fp moves for spilling by setting
287 their cost higher than memmov_cost. */
291 };
294 {
296 /* Avoid the use of slow int<->fp moves for spilling by setting
297 their cost higher than memmov_cost. */
301 };
304 {
306 /* Avoid the use of slow int<->fp moves for spilling by setting
307 their cost higher than memmov_cost. */
311 };
314 {
316 /* Avoid the use of slow int<->fp moves for spilling by setting
317 their cost higher than memmov_cost (actual, 4 and 9). */
321 };
324 {
329 };
332 {
334 /* Avoid the use of slow int<->fp moves for spilling by setting
335 their cost higher than memmov_cost. */
339 };
342 {
344 /* Avoid the use of int<->fp moves for spilling. */
348 };
351 {
353 /* Avoid the use of int<->fp moves for spilling. */
357 };
359 /* Generic costs for vector insn classes. */
361 {
375 };
377 /* ThunderX costs for vector insn classes. */
379 {
393 };
395 /* Generic costs for vector insn classes. */
397 {
411 };
414 {
428 };
430 /* Generic costs for vector insn classes. */
432 {
446 };
448 /* Costs for vector insn classes for Vulcan. */
450 {
464 };
466 /* Generic costs for branch instructions. */
468 {
471 };
473 /* Branch costs for Cortex-A57. */
475 {
478 };
480 /* Branch costs for Vulcan. */
482 {
485 };
487 /* Generic approximation modes. */
489 {
492 AARCH64_APPROX_NONE /* recip_sqrt */
493 };
495 /* Approximation modes for Exynos M1. */
497 {
500 AARCH64_APPROX_ALL /* recip_sqrt */
501 };
503 /* Approximation modes for X-Gene 1. */
505 {
508 AARCH64_APPROX_ALL /* recip_sqrt */
509 };
512 {
534 };
537 {
560 };
563 {
586 };
589 {
612 };
615 {
638 };
641 {
664 };
667 {
689 };
692 {
714 };
717 {
739 };
742 {
765 };
768 {
790 };
792 /* Support for fine-grained override of the tuning structures. */
793 struct aarch64_tuning_override_function
794 {
797 };
802 static const struct aarch64_tuning_override_function
803 aarch64_tuning_override_functions[] =
804 {
808 };
810 /* A processor implementing AArch64. */
811 struct processor
812 {
820 };
822 /* Architectures implementing AArch64. */
824 {
825 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
826 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
829 };
831 /* Processor cores implementing AArch64. */
833 {
834 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
835 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
836 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
837 FLAGS, &COSTS##_tunings},
842 };
845 /* Target specification. These are populated by the -march, -mtune, -mcpu
846 handling code or by target attributes. */
851 /* The current tuning set. */
854 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
856 /* An ISA extension in the co-processor and main instruction set space. */
857 struct aarch64_option_extension
858 {
862 };
865 {
869 }
870 aarch64_cc;
872 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
874 /* The condition codes of the processor, and the inverse function. */
876 {
879 };
881 /* Generate code to enable conditional branches in functions over 1 MiB. */
885 {
902 }
904 void
906 {
910 else
912 }
914 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
915 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
916 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
917 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
918 cost (in this case the best class is the lowest cost one). Using ALL_REGS
919 irrespectively of its cost results in bad allocations with many redundant
920 int<->FP moves which are expensive on various cores.
921 To avoid this we don't allow ALL_REGS as the allocno class, but force a
922 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
923 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
924 Otherwise set the allocno class depending on the mode.
925 The result of this is that it is no longer inefficient to have a higher
926 memory move cost than the register move cost.
927 */
929 static reg_class_t
931 reg_class_t best_class)
932 {
943 }
945 static unsigned int
947 {
951 }
953 static int
956 {
964 }
966 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
967 unsigned
969 {
977 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
978 equivalent DWARF register. */
980 }
982 /* Return TRUE if MODE is any of the large INT modes. */
983 static bool
985 {
987 }
989 /* Return TRUE if MODE is any of the vector modes. */
990 static bool
992 {
995 }
997 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
998 static bool
1001 {
1009 }
1011 /* Implement HARD_REGNO_NREGS. */
1013 int
1015 {
1017 {
1023 }
1025 }
1027 /* Implement HARD_REGNO_MODE_OK. */
1029 int
1031 {
1036 /* The purpose of comparing with ptr_mode is to support the
1037 global register variable associated with the stack pointer
1038 register via the syntax of asm ("wsp") in ILP32. */
1048 {
1050 return
1052 else
1054 }
1057 }
1059 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1060 machine_mode
1062 machine_mode mode)
1063 {
1064 /* Handle modes that fit within single registers. */
1066 {
1069 else
1071 }
1072 /* Fall back to generic for multi-reg and very large modes. */
1073 else
1075 }
1077 /* Return true if calls to DECL should be treated as
1078 long-calls (ie called via a register). */
1079 static bool
1081 {
1083 }
1085 /* Return true if calls to symbol-ref SYM should be treated as
1086 long-calls (ie called via a register). */
1087 bool
1089 {
1091 }
1093 /* Return true if calls to symbol-ref SYM should not go through
1094 plt stubs. */
1096 bool
1098 {
1102 && decl
1103 && (!flag_plt
1109 }
1111 /* Return true if the offsets to a zero/sign-extract operation
1112 represent an expression that matches an extend operation. The
1113 operands represent the paramters from
1115 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1116 bool
1118 rtx extract_imm)
1119 {
1136 }
1138 /* Emit an insn that's a simple single-set. Both the operands must be
1139 known to be valid. */
1142 {
1144 }
1146 /* X and Y are two things to compare using CODE. Emit the compare insn and
1147 return the rtx for register 0 in the proper mode. */
1148 rtx
1150 {
1156 }
1158 /* Build the SYMBOL_REF for __tls_get_addr. */
1162 rtx
1164 {
1168 }
1170 /* Return the TLS model to use for ADDR. */
1172 static enum tls_model
1174 {
1179 {
1183 }
1188 }
1190 /* We'll allow lo_sum's in addresses in our legitimate addresses
1191 so that combine would take care of combining addresses where
1192 necessary, but for generation purposes, we'll generate the address
1193 as :
1194 RTL Absolute
1195 tmp = hi (symbol_ref); adrp x1, foo
1196 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1197 nop
1199 PIC TLS
1200 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1201 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1202 bl __tls_get_addr
1203 nop
1205 Load TLS symbol, depending on TLS mechanism and TLS access model.
1207 Global Dynamic - Traditional TLS:
1208 adrp tmp, :tlsgd:imm
1209 add dest, tmp, #:tlsgd_lo12:imm
1210 bl __tls_get_addr
1212 Global Dynamic - TLS Descriptors:
1213 adrp dest, :tlsdesc:imm
1214 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1215 add dest, dest, #:tlsdesc_lo12:imm
1216 blr tmp
1217 mrs tp, tpidr_el0
1218 add dest, dest, tp
1220 Initial Exec:
1221 mrs tp, tpidr_el0
1222 adrp tmp, :gottprel:imm
1223 ldr dest, [tmp, #:gottprel_lo12:imm]
1224 add dest, dest, tp
1226 Local Exec:
1227 mrs tp, tpidr_el0
1228 add t0, tp, #:tprel_hi12:imm, lsl #12
1229 add t0, t0, #:tprel_lo12_nc:imm
1230 */
1232 static void
1235 {
1237 {
1239 {
1240 /* In ILP32, the mode of dest can be either SImode or DImode. */
1252 }
1259 {
1262 rtx insn;
1263 rtx mem;
1265 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1266 here before rtl expand. Tree IVOPT will generate rtl pattern to
1267 decide rtx costs, in which case pic_offset_table_rtx is not
1268 initialized. For that case no need to generate the first adrp
1269 instruction as the final cost for global variable access is
1270 one instruction. */
1272 {
1273 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1274 using the page base as GOT base, the first page may be wasted,
1275 in the worst scenario, there is only 28K space for GOT).
1277 The generate instruction sequence for accessing global variable
1278 is:
1280 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1282 Only one instruction needed. But we must initialize
1283 pic_offset_table_rtx properly. We generate initialize insn for
1284 every global access, and allow CSE to remove all redundant.
1286 The final instruction sequences will look like the following
1287 for multiply global variables access.
1289 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1291 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1292 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1293 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1294 ... */
1302 }
1305 {
1308 else
1312 }
1313 else
1314 {
1319 }
1321 /* The operand is expected to be MEM. Whenever the related insn
1322 pattern changed, above code which calculate mem should be
1323 updated. */
1329 }
1332 {
1333 /* In ILP32, the mode of dest can be either SImode or DImode,
1334 while the got entry is always of SImode size. The mode of
1335 dest depends on how dest is used: if dest is assigned to a
1336 pointer (e.g. in the memory), it has SImode; it may have
1337 DImode if dest is dereferenced to access the memeory.
1338 This is why we have to handle three different ldr_got_small
1339 patterns here (two patterns for ILP32). */
1341 rtx insn;
1342 rtx mem;
1351 {
1354 else
1358 }
1359 else
1360 {
1365 }
1372 }
1375 {
1387 }
1390 {
1393 rtx tp;
1397 /* In ILP32, the got entry is always of SImode size. Unlike
1398 small GOT, the dest is fixed at reg 0. */
1401 else
1411 }
1414 {
1415 /* In ILP32, the mode of dest can be either SImode or DImode,
1416 while the got entry is always of SImode size. The mode of
1417 dest depends on how dest is used: if dest is assigned to a
1418 pointer (e.g. in the memory), it has SImode; it may have
1419 DImode if dest is dereferenced to access the memeory.
1420 This is why we have to handle three different tlsie_small
1421 patterns here (two patterns for ILP32). */
1427 {
1430 else
1431 {
1434 }
1435 }
1436 else
1437 {
1440 }
1445 }
1451 {
1459 {
1482 }
1486 }
1493 {
1498 {
1501 else
1502 {
1505 }
1506 }
1507 else
1508 {
1511 }
1515 }
1519 }
1520 }
1522 /* Emit a move from SRC to DEST. Assume that the move expanders can
1523 handle all moves if !can_create_pseudo_p (). The distinction is
1524 important because, unlike emit_move_insn, the move expanders know
1525 how to force Pmode objects into the constant pool even when the
1526 constant pool address is not itself legitimate. */
1527 static rtx
1529 {
1533 }
1535 /* Split a 128-bit move operation into two 64-bit move operations,
1536 taking care to handle partial overlap of register to register
1537 copies. Special cases are needed when moving between GP regs and
1538 FP regs. SRC can be a register, constant or memory; DST a register
1539 or memory. If either operand is memory it must not have any side
1540 effects. */
1541 void
1543 {
1554 {
1558 /* Handle FP <-> GP regs. */
1560 {
1565 {
1568 }
1569 else
1570 {
1573 }
1575 }
1577 {
1582 {
1585 }
1586 else
1587 {
1590 }
1592 }
1593 }
1600 /* At most one pairing may overlap. */
1602 {
1605 }
1606 else
1607 {
1610 }
1611 }
1613 bool
1615 {
1618 }
1620 /* Split a complex SIMD combine. */
1622 void
1624 {
1631 {
1635 {
1659 }
1663 }
1664 }
1666 /* Split a complex SIMD move. */
1668 void
1670 {
1677 {
1683 {
1707 }
1711 }
1712 }
1714 bool
1717 {
1721 }
1724 static rtx
1726 {
1729 else
1730 {
1733 }
1734 }
1737 static rtx
1739 {
1741 {
1742 rtx high;
1743 /* Load the full offset into a register. This
1744 might be improvable in the future. */
1750 }
1752 }
1754 static int
1756 machine_mode mode)
1757 {
1766 {
1770 }
1773 {
1775 {
1780 else
1783 }
1785 }
1787 /* Remaining cases are all for DImode. */
1796 {
1797 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1798 For a 64-bit bitmask try whether changing 16 bits to all ones or
1799 zeroes creates a valid bitmask. To check any repeated bitmask,
1800 try using 16 bits from the other 32-bit half of val. */
1803 {
1814 }
1816 {
1818 {
1822 }
1824 }
1825 }
1827 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1828 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1829 otherwise skip zero bits. */
1841 {
1847 num_insns ++;
1848 }
1851 }
1854 void
1856 {
1861 /* Check on what type of symbol it is. */
1865 {
1869 /* If we have (const (plus symbol offset)), separate out the offset
1870 before we start classifying the symbol. */
1875 {
1879 {
1885 }
1890 /* If we aren't generating PC relative literals, then
1891 we need to expand the literal pool access carefully.
1892 This is something that needs to be done in a number
1893 of places, so could well live as a separate function. */
1895 {
1900 }
1917 {
1923 }
1924 /* FALLTHRU */
1937 }
1938 }
1941 {
1944 else
1945 {
1949 }
1952 }
1955 }
1957 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
1958 temporary value if necessary. FRAME_RELATED_P should be true if
1959 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
1960 to the generated instructions. If SCRATCHREG is known to hold
1961 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
1962 immediate again.
1964 Since this function may be used to adjust the stack pointer, we must
1965 ensure that it cannot cause transient stack deallocation (for example
1966 by first incrementing SP and then decrementing when adjusting by a
1967 large immediate). */
1969 static void
1973 {
1981 /* Single instruction adjustment. */
1983 {
1987 }
1989 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
1990 Only do this if mdelta is not a 16-bit move as adjusting using a move
1991 is better. */
1993 {
2002 }
2004 /* Emit a move immediate if required and an addition/subtraction. */
2011 {
2015 }
2016 }
2020 HOST_WIDE_INT delta)
2021 {
2023 }
2027 {
2030 }
2034 {
2037 }
2039 static bool
2041 tree exp ATTRIBUTE_UNUSED)
2042 {
2043 /* Currently, always true. */
2045 }
2047 /* Implement TARGET_PASS_BY_REFERENCE. */
2049 static bool
2051 machine_mode mode,
2052 const_tree type,
2054 {
2055 HOST_WIDE_INT size;
2056 machine_mode dummymode;
2059 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2063 /* Aggregates are passed by reference based on their size. */
2065 {
2067 }
2069 /* Variable sized arguments are always returned by reference. */
2073 /* Can this be a candidate to be passed in fp/simd register(s)? */
2076 NULL))
2079 /* Arguments which are variable sized or larger than 2 registers are
2080 passed by reference unless they are a homogenous floating point
2081 aggregate. */
2083 }
2085 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2086 static bool
2088 {
2089 machine_mode dummy_mode;
2092 /* Never happens in little-endian mode. */
2096 /* Only composite types smaller than or equal to 16 bytes can
2097 be potentially returned in registers. */
2103 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2104 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2105 is always passed/returned in the least significant bits of fp/simd
2106 register(s). */
2112 }
2114 /* Implement TARGET_FUNCTION_VALUE.
2115 Define how to find the value returned by a function. */
2117 static rtx
2120 {
2121 machine_mode mode;
2124 machine_mode ag_mode;
2131 {
2135 {
2138 }
2139 }
2143 {
2145 {
2148 }
2149 else
2150 {
2152 rtx par;
2156 {
2161 }
2163 }
2164 }
2165 else
2167 }
2169 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2170 Return true if REGNO is the number of a hard register in which the values
2171 of called function may come back. */
2173 static bool
2175 {
2176 /* Maximum of 16 bytes can be returned in the general registers. Examples
2177 of 16-byte return values are: 128-bit integers and 16-byte small
2178 structures (excluding homogeneous floating-point aggregates). */
2182 /* Up to four fp/simd registers can return a function value, e.g. a
2183 homogeneous floating-point aggregate having four members. */
2188 }
2190 /* Implement TARGET_RETURN_IN_MEMORY.
2192 If the type T of the result of a function is such that
2193 void func (T arg)
2194 would require that arg be passed as a value in a register (or set of
2195 registers) according to the parameter passing rules, then the result
2196 is returned in the same registers as would be used for such an
2197 argument. */
2199 static bool
2201 {
2202 HOST_WIDE_INT size;
2203 machine_mode ag_mode;
2209 /* Simple scalar types always returned in registers. */
2213 type,
2216 NULL))
2219 /* Types larger than 2 registers returned in memory. */
2222 }
2224 static bool
2227 {
2230 type,
2232 nregs,
2233 NULL);
2234 }
2236 /* Given MODE and TYPE of a function argument, return the alignment in
2237 bits. The idea is to suppress any stronger alignment requested by
2238 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2239 This is a helper function for local use only. */
2241 static unsigned int
2243 {
2263 }
2265 /* Layout a function argument according to the AAPCS64 rules. The rule
2266 numbers refer to the rule numbers in the AAPCS64. */
2268 static void
2270 const_tree type,
2272 {
2276 HOST_WIDE_INT size;
2278 /* We need to do this once per argument. */
2284 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2285 size
2287 UNITS_PER_WORD);
2291 mode,
2292 type,
2295 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2296 The following code thus handles passing by SIMD/FP registers first. */
2300 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2301 and homogenous short-vector aggregates (HVA). */
2303 {
2308 {
2311 {
2314 }
2315 else
2316 {
2317 rtx par;
2321 {
2324 tmp = gen_rtx_EXPR_LIST
2328 }
2330 }
2332 }
2333 else
2334 {
2335 /* C.3 NSRN is set to 8. */
2338 }
2339 }
2344 /* C6 - C9. though the sign and zero extension semantics are
2345 handled elsewhere. This is the case where the argument fits
2346 entirely general registers. */
2348 {
2353 /* C.8 if the argument has an alignment of 16 then the NGRN is
2354 rounded up to the next even number. */
2356 {
2359 }
2360 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2361 A reg is still generated for it, but the caller should be smart
2362 enough not to use it. */
2364 {
2366 }
2367 else
2368 {
2369 rtx par;
2374 {
2379 }
2381 }
2385 }
2387 /* C.11 */
2390 /* The argument is passed on stack; record the needed number of words for
2391 this argument and align the total size if necessary. */
2392 on_stack:
2398 }
2400 /* Implement TARGET_FUNCTION_ARG. */
2402 static rtx
2405 {
2414 }
2416 void
2418 const_tree fntype ATTRIBUTE_UNUSED,
2419 rtx libname ATTRIBUTE_UNUSED,
2420 const_tree fndecl ATTRIBUTE_UNUSED,
2422 {
2436 {
2443 }
2445 }
2447 static void
2449 machine_mode mode,
2450 const_tree type,
2452 {
2455 {
2465 }
2466 }
2468 bool
2470 {
2473 }
2475 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2476 PARM_BOUNDARY bits of alignment, but will be given anything up
2477 to STACK_BOUNDARY bits if the type requires it. This makes sure
2478 that both before and after the layout of each argument, the Next
2479 Stacked Argument Address (NSAA) will have a minimum alignment of
2480 8 bytes. */
2482 static unsigned int
2484 {
2492 }
2494 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2496 Return true if an argument passed on the stack should be padded upwards,
2497 i.e. if the least-significant byte of the stack slot has useful data.
2499 Small aggregate types are placed in the lowest memory address.
2501 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2503 bool
2505 {
2506 /* On little-endian targets, the least significant byte of every stack
2507 argument is passed at the lowest byte address of the stack slot. */
2511 /* Otherwise, integral, floating-point and pointer types are padded downward:
2512 the least significant byte of a stack argument is passed at the highest
2513 byte address of the stack slot. */
2520 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2522 }
2524 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2526 It specifies padding for the last (may also be the only)
2527 element of a block move between registers and memory. If
2528 assuming the block is in the memory, padding upward means that
2529 the last element is padded after its highest significant byte,
2530 while in downward padding, the last element is padded at the
2531 its least significant byte side.
2533 Small aggregates and small complex types are always padded
2534 upwards.
2536 We don't need to worry about homogeneous floating-point or
2537 short-vector aggregates; their move is not affected by the
2538 padding direction determined here. Regardless of endianness,
2539 each element of such an aggregate is put in the least
2540 significant bits of a fp/simd register.
2542 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2543 register has useful data, and return the opposite if the most
2544 significant byte does. */
2546 bool
2549 {
2551 /* Small composite types are always padded upward. */
2553 {
2558 }
2560 /* Otherwise, use the default padding. */
2562 }
2564 static machine_mode
2566 {
2568 }
2570 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2572 /* We use the 12-bit shifted immediate arithmetic instructions so values
2573 must be multiple of (1 << 12), i.e. 4096. */
2574 #define ARITH_FACTOR 4096
2576 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2577 #error Cannot use simple address calculation for stack probing
2578 #endif
2580 /* The pair of scratch registers used for stack probing. */
2581 #define PROBE_STACK_FIRST_REG 9
2582 #define PROBE_STACK_SECOND_REG 10
2584 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2585 inclusive. These are offsets from the current stack pointer. */
2587 static void
2589 {
2592 /* See the same assertion on PROBE_INTERVAL above. */
2595 /* See if we have a constant small number of probes to generate. If so,
2596 that's the easy case. */
2598 {
2605 }
2607 /* The run-time loop is made up of 8 insns in the generic case while the
2608 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2610 {
2615 stack_pointer_rtx,
2619 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2620 it exceeds SIZE. If only two probes are needed, this will not
2621 generate any code. Then probe at FIRST + SIZE. */
2623 {
2627 }
2631 {
2636 }
2637 else
2639 }
2641 /* Otherwise, do the same as above, but in a loop. Note that we must be
2642 extra careful with variables wrapping around because we might be at
2643 the very top (or the very bottom) of the address space and we have
2644 to be able to handle this case properly; in particular, we use an
2645 equality test for the loop condition. */
2646 else
2647 {
2650 /* Step 1: round SIZE to the previous multiple of the interval. */
2655 /* Step 2: compute initial and final value of the loop counter. */
2657 /* TEST_ADDR = SP + FIRST. */
2661 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2667 /* Step 3: the loop
2669 do
2670 {
2671 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2672 probe at TEST_ADDR
2673 }
2674 while (TEST_ADDR != LAST_ADDR)
2676 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2677 until it is equal to ROUNDED_SIZE. */
2681 else
2685 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2686 that SIZE is equal to ROUNDED_SIZE. */
2689 {
2693 {
2698 }
2699 else
2701 }
2702 }
2704 /* Make sure nothing is scheduled before we are done. */
2706 }
2708 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2709 absolute addresses. */
2713 {
2720 /* Loop. */
2723 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2728 /* Probe at TEST_ADDR. */
2731 /* Test if TEST_ADDR == LAST_ADDR. */
2735 /* Branch. */
2741 }
2743 static bool
2745 {
2746 /* In aarch64_override_options_after_change
2747 flag_omit_leaf_frame_pointer turns off the frame pointer by
2748 default. Turn it back on now if we've not got a leaf
2749 function. */
2755 }
2757 /* Mark the registers that need to be saved by the callee and calculate
2758 the size of the callee-saved registers area and frame record (both FP
2759 and LR may be omitted). */
2760 static void
2762 {
2769 #define SLOT_NOT_REQUIRED (-2)
2770 #define SLOT_REQUIRED (-1)
2775 /* First mark all the registers that really need to be saved... */
2782 /* ... that includes the eh data registers (if needed)... */
2788 /* ... and any callee saved register that dataflow says is live. */
2798 {
2801 }
2804 {
2805 /* FP and LR are placed in the linkage record. */
2811 }
2813 /* Now assign stack slots for them. */
2816 {
2823 }
2831 {
2832 /* If there is an alignment gap between integer and fp callee-saves,
2833 allocate the last fp register to it if possible. */
2835 {
2838 }
2847 }
2853 HOST_WIDE_INT varargs_and_saved_regs_size
2880 {
2881 /* Simple, small frame with no outgoing arguments:
2882 stp reg1, reg2, [sp, -frame_size]!
2883 stp reg3, reg4, [sp, 16] */
2885 }
2890 {
2891 /* Frame with small outgoing arguments:
2892 sub sp, sp, frame_size
2893 stp reg1, reg2, [sp, outgoing_args_size]
2894 stp reg3, reg4, [sp, outgoing_args_size + 16] */
2898 }
2900 {
2901 /* Frame with large outgoing arguments but a small local area:
2902 stp reg1, reg2, [sp, -hard_fp_offset]!
2903 stp reg3, reg4, [sp, 16]
2904 sub sp, sp, outgoing_args_size */
2908 }
2911 {
2912 /* Frame with large local area and outgoing arguments (this pushes the
2913 callee-saves first, followed by the locals and outgoing area):
2914 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
2915 stp reg3, reg4, [sp, 16]
2916 sub sp, sp, frame_size - varargs_and_saved_regs_size */
2922 }
2923 else
2924 {
2925 /* Frame with large local area and outgoing arguments using frame pointer:
2926 sub sp, sp, hard_fp_offset
2927 stp x29, x30, [sp, 0]
2928 add x29, sp, 0
2929 stp reg3, reg4, [sp, 16]
2930 sub sp, sp, outgoing_args_size */
2934 }
2937 }
2939 /* Return true if the register REGNO is saved on entry to
2940 the current function. */
2942 static bool
2944 {
2946 }
2948 /* Return the next register up from REGNO up to LIMIT for the callee
2949 to save. */
2951 static unsigned
2953 {
2955 regno ++;
2957 }
2959 /* Push the register number REGNO of mode MODE to the stack with write-back
2960 adjusting the stack by ADJUSTMENT. */
2962 static void
2964 HOST_WIDE_INT adjustment)
2965 {
2976 }
2978 /* Generate and return an instruction to store the pair of registers
2979 REG and REG2 of mode MODE to location BASE with write-back adjusting
2980 the stack location BASE by ADJUSTMENT. */
2982 static rtx
2984 HOST_WIDE_INT adjustment)
2985 {
2987 {
2998 }
2999 }
3001 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3002 stack pointer by ADJUSTMENT. */
3004 static void
3006 {
3021 }
3023 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3024 adjusting it by ADJUSTMENT afterwards. */
3026 static rtx
3028 HOST_WIDE_INT adjustment)
3029 {
3031 {
3040 }
3041 }
3043 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3044 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3045 into CFI_OPS. */
3047 static void
3050 {
3057 {
3061 }
3062 else
3063 {
3068 }
3069 }
3071 /* Generate and return a store pair instruction of mode MODE to store
3072 register REG1 to MEM1 and register REG2 to MEM2. */
3074 static rtx
3076 rtx reg2)
3077 {
3079 {
3088 }
3089 }
3091 /* Generate and regurn a load pair isntruction of mode MODE to load register
3092 REG1 from MEM1 and register REG2 from MEM2. */
3094 static rtx
3096 rtx mem2)
3097 {
3099 {
3108 }
3109 }
3111 /* Emit code to save the callee-saved registers from register number START
3112 to LIMIT to the stack at the location starting at offset START_OFFSET,
3113 skipping any write-back candidates if SKIP_WB is true. */
3115 static void
3118 {
3128 {
3130 HOST_WIDE_INT offset;
3140 offset));
3148 {
3150 rtx mem2;
3154 offset));
3156 reg2));
3158 /* The first part of a frame-related parallel insn is
3159 always assumed to be relevant to the frame
3160 calculations; subsequent parts, are only
3161 frame-related if explicitly marked. */
3164 }
3165 else
3169 }
3170 }
3172 /* Emit code to restore the callee registers of mode MODE from register
3173 number START up to and including LIMIT. Restore from the stack offset
3174 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3175 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3177 static void
3181 {
3187 HOST_WIDE_INT offset;
3192 {
3209 {
3211 rtx mem2;
3219 }
3220 else
3223 }
3224 }
3226 /* AArch64 stack frames generated by this compiler look like:
3228 +-------------------------------+
3229 | |
3230 | incoming stack arguments |
3231 | |
3232 +-------------------------------+
3233 | | <-- incoming stack pointer (aligned)
3234 | callee-allocated save area |
3235 | for register varargs |
3236 | |
3237 +-------------------------------+
3238 | local variables | <-- frame_pointer_rtx
3239 | |
3240 +-------------------------------+
3241 | padding0 | \
3242 +-------------------------------+ |
3243 | callee-saved registers | | frame.saved_regs_size
3244 +-------------------------------+ |
3245 | LR' | |
3246 +-------------------------------+ |
3247 | FP' | / <- hard_frame_pointer_rtx (aligned)
3248 +-------------------------------+
3249 | dynamic allocation |
3250 +-------------------------------+
3251 | padding |
3252 +-------------------------------+
3253 | outgoing stack arguments | <-- arg_pointer
3254 | |
3255 +-------------------------------+
3256 | | <-- stack_pointer_rtx (aligned)
3258 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3259 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3260 unchanged. */
3262 /* Generate the prologue instructions for entry into a function.
3263 Establish the stack frame by decreasing the stack pointer with a
3264 properly calculated size and, if necessary, create a frame record
3265 filled with the values of LR and previous frame pointer. The
3266 current FP is also set up if it is in use. */
3268 void
3270 {
3286 {
3288 {
3292 }
3295 }
3303 {
3308 stack_pointer_rtx,
3312 }
3319 }
3321 /* Return TRUE if we can use a simple_return insn.
3323 This function checks whether the callee saved stack is empty, which
3324 means no restore actions are need. The pro_and_epilogue will use
3325 this to check whether shrink-wrapping opt is feasible. */
3327 bool
3329 {
3339 }
3341 /* Generate the epilogue instructions for returning from a function.
3342 This is almost exactly the reverse of the prolog sequence, except
3343 that we need to insert barriers to avoid scheduling loads that read
3344 from a deallocated stack, and we optimize the unwind records by
3345 emitting them all together if possible. */
3346 void
3348 {
3360 /* We need to add memory barrier to prevent read from deallocated stack. */
3364 /* Emit a barrier to prevent loads from a deallocated stack. */
3366 {
3369 }
3371 /* Restore the stack pointer from the frame pointer if it may not
3372 be the same as the stack pointer. */
3374 {
3376 hard_frame_pointer_rtx,
3378 /* If writeback is used when restoring callee-saves, the CFA
3379 is restored on the instruction doing the writeback. */
3381 }
3382 else
3397 {
3398 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3404 }
3409 {
3410 /* Emit delayed restores and reset the CFA to be SP. */
3415 }
3417 /* Stack adjustment for exception handler. */
3419 {
3420 /* We need to unwind the stack by the offset computed by
3421 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3422 to be SP; letting the CFA move during this adjustment
3423 is just as correct as retaining the CFA from the body
3424 of the function. Therefore, do nothing special. */
3426 }
3431 }
3433 /* Return the place to copy the exception unwinding return address to.
3434 This will probably be a stack slot, but could (in theory be the
3435 return register). */
3436 rtx
3438 {
3439 HOST_WIDE_INT fp_offset;
3449 /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can
3450 result in a store to save LR introduced by builtin_eh_return () being
3451 incorrectly deleted because the alias is not detected.
3452 So in the calculation of the address to copy the exception unwinding
3453 return address to, we note 2 cases.
3454 If FP is needed and the fp_offset is 0, it means that SP = FP and hence
3455 we return a SP-relative location since all the addresses are SP-relative
3456 in this case. This prevents the store from being optimized away.
3457 If the fp_offset is not 0, then the addresses will be FP-relative and
3458 therefore we return a FP-relative location. */
3461 {
3465 else
3468 }
3470 /* If FP is not needed, we calculate the location of LR, which would be
3471 at the top of the saved registers block. */
3475 stack_pointer_rtx,
3476 fp_offset
3479 }
3481 /* Output code to add DELTA to the first argument, and then jump
3482 to FUNCTION. Used for C++ multiple inheritance. */
3483 static void
3485 HOST_WIDE_INT delta,
3486 HOST_WIDE_INT vcall_offset,
3487 tree function)
3488 {
3489 /* The this pointer is always in x0. Note that this differs from
3490 Arm where the this pointer maybe bumped to r1 if r0 is required
3491 to return a pointer to an aggregate. On AArch64 a result value
3492 pointer will be in x8. */
3502 else
3503 {
3512 {
3516 else
3518 }
3522 else
3529 else
3530 {
3532 Pmode);
3534 }
3538 else
3544 }
3546 /* Generate a tail call to the target function. */
3548 {
3551 }
3563 /* Stop pretending to be a post-reload pass. */
3565 }
3567 static bool
3569 {
3574 {
3578 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3579 TLS offsets, not real symbol references. */
3582 }
3584 }
3587 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3588 a left shift of 0 or 12 bits. */
3589 bool
3591 {
3594 );
3595 }
3598 /* Return true if val is an immediate that can be loaded into a
3599 register by a MOVZ instruction. */
3600 static bool
3602 {
3604 {
3608 }
3609 else
3610 {
3611 /* Ignore sign extension. */
3613 }
3616 }
3618 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
3621 {
3627 };
3630 /* Return true if val is a valid bitmask immediate. */
3632 bool
3634 {
3638 /* Check for a single sequence of one bits and return quickly if so.
3639 The special cases of all ones and all zeroes returns false. */
3646 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
3650 /* Invert if the immediate doesn't start with a zero bit - this means we
3651 only need to search for sequences of one bits. */
3655 /* Find the first set bit and set tmp to val with the first sequence of one
3656 bits removed. Return success if there is a single sequence of ones. */
3663 /* Find the next set bit and compute the difference in bit position. */
3668 /* Check the bit position difference is a power of 2, and that the first
3669 sequence of one bits fits within 'bits' bits. */
3673 /* Check the sequence of one bits is repeated 64/bits times. */
3675 }
3678 /* Return true if val is an immediate that can be loaded into a
3679 register in a single instruction. */
3680 bool
3682 {
3686 }
3688 static bool
3690 {
3698 {
3702 else
3703 /* Avoid generating a 64-bit relocation in ILP32; leave
3704 to aarch64_expand_mov_immediate to handle it properly. */
3706 }
3709 }
3711 /* Implement TARGET_CASE_VALUES_THRESHOLD.
3712 The expansion for a table switch is quite expensive due to the number
3713 of instructions, the table lookup and hard to predict indirect jump.
3714 When optimizing for speed, and -O3 enabled, use the per-core tuning if
3715 set, otherwise use tables for > 16 cases as a tradeoff between size and
3716 performance. When optimizing for size, use the default setting. */
3718 static unsigned int
3720 {
3721 /* Use the specified limit for the number of cases before using jump
3722 tables at higher optimization levels. */
3726 else
3728 }
3730 /* Return true if register REGNO is a valid index register.
3731 STRICT_P is true if REG_OK_STRICT is in effect. */
3733 bool
3735 {
3737 {
3745 }
3747 }
3749 /* Return true if register REGNO is a valid base register for mode MODE.
3750 STRICT_P is true if REG_OK_STRICT is in effect. */
3752 bool
3754 {
3756 {
3764 }
3766 /* The fake registers will be eliminated to either the stack or
3767 hard frame pointer, both of which are usually valid base registers.
3768 Reload deals with the cases where the eliminated form isn't valid. */
3773 }
3775 /* Return true if X is a valid base register for mode MODE.
3776 STRICT_P is true if REG_OK_STRICT is in effect. */
3778 static bool
3780 {
3785 }
3787 /* Return true if address offset is a valid index. If it is, fill in INFO
3788 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
3790 static bool
3793 {
3795 rtx index;
3798 /* (reg:P) */
3801 {
3805 }
3806 /* (sign_extend:DI (reg:SI)) */
3811 {
3816 }
3817 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
3824 {
3829 }
3830 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
3837 {
3842 }
3843 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
3850 {
3858 }
3859 /* (and:DI (mult:DI (reg:DI) (const_int scale))
3860 (const_int 0xffffffff<<shift)) */
3867 {
3873 }
3874 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
3881 {
3889 }
3890 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
3891 (const_int 0xffffffff<<shift)) */
3898 {
3904 }
3905 /* (mult:P (reg:P) (const_int scale)) */
3910 {
3914 }
3915 /* (ashift:P (reg:P) (const_int shift)) */
3920 {
3924 }
3925 else
3936 {
3941 }
3944 }
3946 bool
3948 {
3952 }
3956 HOST_WIDE_INT offset)
3957 {
3959 }
3963 {
3967 }
3969 /* Return true if MODE is one of the modes for which we
3970 support LDP/STP operations. */
3972 static bool
3974 {
3979 }
3981 /* Return true if REGNO is a virtual pointer register, or an eliminable
3982 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
3983 include stack_pointer or hard_frame_pointer. */
3984 static bool
3986 {
3991 }
3993 /* Return true if X is a valid address for machine mode MODE. If it is,
3994 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
3995 effect. OUTER_CODE is PARALLEL for a load/store pair. */
3997 static bool
4001 {
4005 /* On BE, we use load/store pair for all large int mode load/stores. */
4007 || (BYTES_BIG_ENDIAN
4011 !load_store_pair_p
4015 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4016 REG addressing. */
4022 {
4038 {
4044 }
4049 {
4056 /* TImode and TFmode values are allowed in both pairs of X
4057 registers and individual Q registers. The available
4058 address modes are:
4059 X,X: 7-bit signed scaled offset
4060 Q: 9-bit signed offset
4061 We conservatively require an offset representable in either mode.
4062 When performing the check for pairs of X registers i.e. LDP/STP
4063 pass down DImode since that is the natural size of the LDP/STP
4064 instruction memory accesses. */
4069 /* A 7bit offset check because OImode will emit a ldp/stp
4070 instruction (only big endian will get here).
4071 For ldp/stp instructions, the offset is scaled for the size of a
4072 single element of the pair. */
4076 /* Three 9/12 bit offsets checks because CImode will emit three
4077 ldr/str instructions (only big endian will get here). */
4084 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4085 instructions (only big endian will get here). */
4094 else
4097 }
4100 {
4101 /* Look for base + (scaled/extended) index register. */
4104 {
4107 }
4110 {
4113 }
4114 }
4135 {
4136 HOST_WIDE_INT offset;
4140 /* TImode and TFmode values are allowed in both pairs of X
4141 registers and individual Q registers. The available
4142 address modes are:
4143 X,X: 7-bit signed scaled offset
4144 Q: 9-bit signed offset
4145 We conservatively require an offset representable in either mode.
4146 */
4154 else
4156 }
4162 /* load literal: pc-relative constant pool entry. Only supported
4163 for SI mode or larger. */
4167 {
4175 }
4184 {
4189 {
4190 /* The symbol and offset must be aligned to the access size. */
4197 {
4201 }
4207 else
4216 }
4217 }
4222 }
4223 }
4225 bool
4227 {
4228 rtx offset;
4232 }
4234 /* Classify the base of symbolic expression X. */
4236 enum aarch64_symbol_type
4238 {
4239 rtx offset;
4243 }
4246 /* Return TRUE if X is a legitimate address for accessing memory in
4247 mode MODE. */
4248 static bool
4250 {
4254 }
4256 /* Return TRUE if X is a legitimate address for accessing memory in
4257 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4258 pair operation. */
4259 bool
4262 {
4266 }
4268 /* Split an out-of-range address displacement into a base and offset.
4269 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4270 to increase opportunities for sharing the base address of different sizes.
4271 For TI/TFmode and unaligned accesses use a 256-byte range. */
4272 static bool
4274 {
4284 }
4286 /* Return TRUE if rtx X is immediate constant 0.0 */
4287 bool
4289 {
4296 }
4298 /* Return the fixed registers used for condition codes. */
4300 static bool
4302 {
4306 }
4308 /* Emit call insn with PAT and do aarch64-specific handling. */
4310 void
4312 {
4318 }
4320 machine_mode
4322 {
4323 /* All floating point compares return CCFP if it is an equality
4324 comparison, and CCFPE otherwise. */
4326 {
4328 {
4349 }
4350 }
4352 /* Equality comparisons of short modes against zero can be performed
4353 using the TST instruction with the appropriate bitmask. */
4359 /* Similarly, comparisons of zero_extends from shorter modes can
4360 be performed using an ANDS with an immediate mask. */
4376 /* A compare with a shifted operand. Because of canonicalization,
4377 the comparison will have to be swapped when we emit the assembly
4378 code. */
4386 /* Similarly for a negated operand, but we can only do this for
4387 equalities. */
4394 /* A test for unsigned overflow. */
4401 /* For everything else, return CCmode. */
4403 }
4405 static int
4408 int
4410 {
4417 }
4419 static int
4421 {
4423 {
4427 {
4441 }
4446 {
4458 }
4463 {
4475 }
4480 {
4486 }
4491 {
4495 }
4500 {
4504 }
4509 }
4512 }
4514 bool
4516 HOST_WIDE_INT minval,
4517 HOST_WIDE_INT maxval)
4518 {
4519 HOST_WIDE_INT firstval;
4536 }
4538 bool
4540 {
4542 }
4545 /* N Z C V. */
4546 #define AARCH64_CC_V 1
4547 #define AARCH64_CC_C (1 << 1)
4548 #define AARCH64_CC_Z (1 << 2)
4549 #define AARCH64_CC_N (1 << 3)
4551 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
4553 {
4570 };
4572 static void
4574 {
4576 {
4577 /* An integer or symbol address without a preceding # sign. */
4580 {
4592 {
4595 }
4596 /* Fall through. */
4600 }
4604 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4605 {
4610 {
4613 }
4616 {
4629 }
4630 }
4634 {
4637 /* Print N such that 2^N == X. */
4639 {
4642 }
4645 }
4649 /* Print the number of non-zero bits in X (a const_int). */
4651 {
4654 }
4660 /* Print the higher numbered register of a pair (TImode) of regs. */
4662 {
4665 }
4672 {
4674 /* Print a condition (eq, ne, etc) or its inverse. */
4676 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
4678 {
4682 }
4685 {
4688 }
4695 }
4703 /* Print a scalar FP/SIMD register name. */
4705 {
4706 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4708 }
4716 /* Print the first FP/SIMD register name in a list. */
4718 {
4719 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4721 }
4726 /* Print a scalar FP/SIMD register name + 1. */
4728 {
4729 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4731 }
4736 /* Print bottom 16 bits of integer constant in hex. */
4738 {
4741 }
4747 /* Print a general register name or the zero register (32-bit or
4748 64-bit). */
4751 {
4754 }
4757 {
4760 }
4763 {
4766 }
4768 /* Fall through */
4771 /* Print a normal operand, if it's a general register, then we
4772 assume DImode. */
4774 {
4777 }
4780 {
4801 {
4804 HOST_WIDE_INT_MIN,
4805 HOST_WIDE_INT_MAX));
4807 }
4809 {
4811 }
4812 else
4817 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
4818 be getting CONST_DOUBLEs holding integers. */
4821 {
4824 }
4826 {
4827 #define buf_size 20
4835 #undef buf_size
4836 }
4842 }
4850 {
4877 }
4883 {
4918 }
4925 {
4931 }
4936 {
4937 HOST_WIDE_INT cond_code;
4938 /* Print nzcv. */
4941 {
4944 }
4949 }
4955 }
4956 }
4958 static void
4960 {
4965 {
4969 else
4978 else
4987 else
4996 else
5003 {
5030 }
5041 }
5044 }
5046 bool
5048 {
5055 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5056 referencing instruction, but they are constant offsets, not
5057 symbols. */
5063 {
5065 {
5071 }
5074 }
5077 }
5079 /* Implement REGNO_REG_CLASS. */
5081 enum reg_class
5083 {
5098 }
5100 static rtx
5102 {
5103 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5104 where mask is selected by alignment and size of the offset.
5105 We try to pick as large a range for the offset as possible to
5106 maximize the chance of a CSE. However, for aligned addresses
5107 we limit the range to 4k so that structures with different sized
5108 elements are likely to use the same base. We need to be careful
5109 not to split a CONST for some forms of address expression, otherwise
5110 it will generate sub-optimal code. */
5113 {
5119 {
5123 /* Force any scaling into a temp for CSE. */
5127 /* Let the pointer register be in op0. */
5131 /* If the pointer is virtual or frame related, then we know that
5132 virtual register instantiation or register elimination is going
5133 to apply a second constant. We want the two constants folded
5134 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5136 {
5140 }
5142 /* Otherwise, in order to encourage CSE (and thence loop strength
5143 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5147 }
5149 /* Does it look like we'll need a load/store-pair operation? */
5150 HOST_WIDE_INT base_offset;
5155 /* For offsets aren't a multiple of the access size, the limit is
5156 -256...255. */
5158 {
5161 /* BLKmode typically uses LDP of X-registers. */
5164 }
5165 /* Small negative offsets are supported. */
5168 /* Use 12-bit offset by access size. */
5169 else
5173 {
5177 }
5178 }
5181 }
5183 /* Return the reload icode required for a constant pool in mode. */
5184 static enum insn_code
5186 {
5188 {
5224 }
5227 }
5228 static reg_class_t
5230 reg_class_t rclass,
5231 machine_mode mode,
5233 {
5235 /* If we have to disable direct literal pool loads and stores because the
5236 function is too big, then we need a scratch register. */
5241 {
5244 }
5246 /* Without the TARGET_SIMD instructions we cannot move a Q register
5247 to a Q register directly. We need a scratch. */
5251 {
5257 }
5259 /* A TFmode or TImode memory access should be handled via an FP_REGS
5260 because AArch64 has richer addressing modes for LDR/STR instructions
5261 than LDP/STP instructions. */
5270 }
5272 static bool
5274 {
5275 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5276 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5279 {
5291 }
5292 else
5293 {
5294 /* If we decided that we didn't need a leaf frame pointer but then used
5295 LR in the function, then we'll want a frame pointer after all, so
5296 prevent this elimination to ensure a frame pointer is used. */
5298 && flag_omit_leaf_frame_pointer
5301 }
5304 }
5306 HOST_WIDE_INT
5308 {
5312 {
5319 }
5322 {
5326 }
5329 }
5331 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5332 previous frame. */
5334 rtx
5336 {
5340 }
5343 static void
5345 {
5347 {
5350 }
5351 else
5352 {
5355 }
5360 }
5362 static void
5364 {
5368 /* Don't need to copy the trailing D-words, we fill those in below. */
5380 /* XXX We should really define a "clear_cache" pattern and use
5381 gen_clear_cache(). */
5386 ptr_mode);
5387 }
5389 static unsigned char
5391 {
5393 {
5400 return
5412 }
5414 }
5416 static reg_class_t
5418 {
5423 {
5429 }
5431 /* If it's an integer immediate that MOVI can't handle, then
5432 FP_REGS is not an option, so we return NO_REGS instead. */
5437 /* Register eliminiation can result in a request for
5438 SP+constant->FP_REGS. We cannot support such operations which
5439 use SP as source and an FP_REG as destination, so reject out
5440 right now. */
5442 {
5445 /* Look through a possible SUBREG introduced by ILP32. */
5451 POINTER_REGS));
5453 }
5456 }
5458 void
5460 {
5462 }
5464 static void
5466 {
5469 else
5470 {
5478 }
5479 }
5481 static void
5483 {
5486 else
5487 {
5495 }
5496 }
5500 {
5506 {
5507 {
5510 },
5511 {
5514 },
5515 {
5518 },
5519 /* We assume that DImode is only generated when not optimizing and
5520 that we don't really need 64-bit address offsets. That would
5521 imply an object file with 8GB of code in a single function! */
5522 {
5525 }
5526 };
5534 /* Need to implement table size reduction, by chaning the code below. */
5544 }
5547 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5548 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5549 operator. */
5551 int
5553 {
5555 {
5558 {
5562 }
5563 }
5565 }
5567 /* Constant pools are per function only when PC relative
5568 literal loads are true or we are in the large memory
5569 model. */
5573 {
5576 }
5578 static bool
5580 {
5581 /* Fixme:: In an ideal world this would work similar
5582 to the logic in aarch64_select_rtx_section but this
5583 breaks bootstrap in gcc go. For now we workaround
5584 this by returning false here. */
5586 }
5588 /* Select appropriate section for constants depending
5589 on where we place literal pools. */
5593 rtx x,
5595 {
5600 }
5602 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
5603 void
5605 HOST_WIDE_INT offset)
5606 {
5607 /* When using per-function literal pools, we must ensure that any code
5608 section is aligned to the minimal instruction length, lest we get
5609 errors from the assembler re "unaligned instructions". */
5612 }
5614 /* Costs. */
5616 /* Helper function for rtx cost calculation. Strip a shift expression
5617 from X. Returns the inner operand if successful, or the original
5618 expression on failure. */
5619 static rtx
5621 {
5624 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5625 we can convert both to ROR during final output. */
5640 }
5642 /* Helper function for rtx cost calculation. Strip an extend
5643 expression from X. Returns the inner operand if successful, or the
5644 original expression on failure. We deal with a number of possible
5645 canonicalization variations here. */
5646 static rtx
5648 {
5651 /* Zero and sign extraction of a widened value. */
5659 /* It can also be represented (for zero-extend) as an AND with an
5660 immediate. */
5669 /* Now handle extended register, as this may also have an optional
5670 left shift by 1..4. */
5684 }
5686 /* Return true iff CODE is a shift supported in combination
5687 with arithmetic instructions. */
5689 static bool
5691 {
5693 }
5695 /* Helper function for rtx cost calculation. Calculate the cost of
5696 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
5697 Return the calculated cost of the expression, recursing manually in to
5698 operands where needed. */
5700 static int
5702 {
5718 /* Integer multiply/fma. */
5720 {
5721 /* The multiply will be canonicalized as a shift, cost it as such. */
5725 {
5729 {
5731 {
5733 /* ARITH + shift-by-register. */
5736 /* ARITH + extended register. We don't have a cost field
5737 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
5739 else
5740 /* ARITH + shift-by-immediate. */
5742 }
5743 else
5744 /* LSL (immediate). */
5747 }
5748 /* Strip extends as we will have costed them in the case above. */
5755 }
5757 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
5758 compound and let the below cases handle it. After all, MNEG is a
5759 special-case alias of MSUB. */
5761 {
5764 }
5766 /* Integer multiplies or FMAs have zero/sign extending variants. */
5771 {
5776 {
5778 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
5780 else
5781 /* MUL/SMULL/UMULL. */
5783 }
5786 }
5788 /* This is either an integer multiply or a MADD. In both cases
5789 we want to recurse and cost the operands. */
5794 {
5796 /* MADD/MSUB. */
5798 else
5799 /* MUL. */
5801 }
5804 }
5805 else
5806 {
5808 {
5809 /* Floating-point FMA/FMUL can also support negations of the
5810 operands, unless the rounding mode is upward or downward in
5811 which case FNMUL is different than FMUL with operand negation. */
5815 {
5820 }
5823 /* FMADD/FNMADD/FNMSUB/FMSUB. */
5825 else
5826 /* FMUL/FNMUL. */
5828 }
5833 }
5834 }
5836 static int
5838 machine_mode mode,
5839 addr_space_t as ATTRIBUTE_UNUSED,
5841 {
5849 {
5851 {
5852 /* This is a CONST or SYMBOL ref which will be split
5853 in a different way depending on the code model in use.
5854 Cost it through the generic infrastructure. */
5856 /* Divide through by the cost of one instruction to
5857 bring it to the same units as the address costs. */
5859 /* The cost is then the cost of preparing the address,
5860 followed by an immediate (possibly 0) offset. */
5862 }
5863 else
5864 {
5865 /* This is most likely a jump table from a case
5866 statement. */
5868 }
5869 }
5872 {
5884 else
5903 }
5907 {
5908 /* For the sake of calculating the cost of the shifted register
5909 component, we can treat same sized modes in the same way. */
5911 {
5924 /* We can't tell, or this is a 128-bit vector. */
5928 }
5929 }
5932 }
5934 /* Return the cost of a branch. If SPEED_P is true then the compiler is
5935 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
5936 to be taken. */
5938 int
5940 {
5941 /* When optimizing for speed, use the cost of unpredictable branches. */
5947 else
5949 }
5951 /* Return true if the RTX X in mode MODE is a zero or sign extract
5952 usable in an ADD or SUB (extended register) instruction. */
5953 static bool
5955 {
5956 /* Catch add with a sign extract.
5957 This is add_<optab><mode>_multp2. */
5960 {
5971 op1))
5972 {
5974 }
5975 }
5976 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
5977 No shift. */
5983 }
5985 static bool
5987 {
5989 {
6001 }
6002 }
6004 /* Return true iff X is an rtx that will match an extr instruction
6005 i.e. as described in the *extr<mode>5_insn family of patterns.
6006 OP0 and OP1 will be set to the operands of the shifts involved
6007 on success and will be NULL_RTX otherwise. */
6009 static bool
6011 {
6026 {
6027 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6039 {
6043 }
6044 }
6047 }
6049 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6050 storing it in *COST. Result is true if the total cost of the operation
6051 has now been calculated. */
6052 static bool
6054 {
6055 rtx inner;
6056 rtx comparator;
6060 {
6064 }
6065 else
6066 {
6070 }
6073 {
6074 /* Conditional branch. */
6077 else
6078 {
6080 {
6082 {
6083 /* TBZ/TBNZ/CBZ/CBNZ. */
6085 /* TBZ/TBNZ. */
6088 else
6089 /* CBZ/CBNZ. */
6093 }
6094 }
6096 {
6097 /* TBZ/TBNZ. */
6100 }
6101 }
6102 }
6104 {
6105 /* CCMP. */
6107 {
6108 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6112 {
6119 else
6121 }
6123 }
6125 /* It's a conditional operation based on the status flags,
6126 so it must be some flavor of CSEL. */
6128 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6134 {
6135 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6138 }
6143 }
6145 /* We don't know what this is, cost all operands. */
6147 }
6149 /* Check whether X is a bitfield operation of the form shift + extend that
6150 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6151 operand to which the bitfield operation is applied. Otherwise return
6152 NULL_RTX. */
6154 static rtx
6156 {
6170 {
6188 }
6191 }
6193 /* Return true if the mask and a shift amount from an RTX of the form
6194 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6195 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6197 bool
6199 {
6204 }
6206 /* Calculate the cost of calculating X, storing it in *COST. Result
6207 is true if the total cost of the operation has now been calculated. */
6208 static bool
6211 {
6217 /* By default, assume that everything has equivalent cost to the
6218 cheapest instruction. Any additional costs are applied as a delta
6219 above this default. */
6223 {
6225 /* The cost depends entirely on the operands to SET. */
6231 {
6234 {
6248 }
6257 /* Fall through. */
6259 /* The cost is one per vector-register copied. */
6261 {
6265 }
6266 /* const0_rtx is in general free, but we will use an
6267 instruction to set a register to 0. */
6269 {
6270 /* The cost is 1 per register copied. */
6274 }
6275 else
6276 /* Cost is just the cost of the RHS of the set. */
6282 /* Bit-field insertion. Strip any redundant widening of
6283 the RHS to meet the width of the target. */
6294 {
6295 /* MOV immediate is assumed to always be cheap. */
6297 }
6298 else
6299 {
6300 /* BFM. */
6304 }
6309 /* We can't make sense of this, assume default cost. */
6312 }
6316 /* If an instruction can incorporate a constant within the
6317 instruction, the instruction's expression avoids calling
6318 rtx_cost() on the constant. If rtx_cost() is called on a
6319 constant, then it is usually because the constant must be
6320 moved into a register by one or more instructions.
6322 The exception is constant 0, which can be expressed
6323 as XZR/WZR and is therefore free. The exception to this is
6324 if we have (set (reg) (const0_rtx)) in which case we must cost
6325 the move. However, we can catch that when we cost the SET, so
6326 we don't need to consider that here. */
6329 else
6330 {
6331 /* To an approximation, building any other constant is
6332 proportionally expensive to the number of instructions
6333 required to build that constant. This is true whether we
6334 are compiling for SPEED or otherwise. */
6337 }
6342 {
6343 /* mov[df,sf]_aarch64. */
6345 /* FMOV (scalar immediate). */
6348 {
6349 /* This will be a load from memory. */
6352 else
6354 }
6355 else
6356 /* Otherwise this is +0.0. We get this using MOVI d0, #0
6357 or MOV v0.s[0], wzr - neither of which are modeled by the
6358 cost tables. Just use the default cost. */
6359 {
6360 }
6361 }
6367 {
6368 /* For loads we want the base cost of a load, plus an
6369 approximation for the additional cost of the addressing
6370 mode. */
6384 }
6392 {
6394 {
6395 /* FNEG. */
6397 }
6399 }
6402 {
6405 {
6406 /* CSETM. */
6409 }
6411 /* Cost this as SUB wzr, X. */
6415 }
6418 {
6419 /* Support (neg(fma...)) as a single instruction only if
6420 sign of zeros is unimportant. This matches the decision
6421 making in aarch64.md. */
6423 {
6424 /* FNMADD. */
6427 }
6429 {
6430 /* FNMUL. */
6433 }
6435 /* FNEG. */
6438 }
6445 {
6448 else
6450 }
6460 {
6464 }
6467 {
6468 /* TODO: A write to the CC flags possibly costs extra, this
6469 needs encoding in the cost tables. */
6472 /* ANDS. */
6474 {
6477 }
6480 {
6481 /* ADDS (and CMN alias). */
6484 }
6487 {
6488 /* SUBS. */
6491 }
6496 {
6497 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
6498 Handle it here directly rather than going to cost_logic
6499 since we know the immediate generated for the TST is valid
6500 so we can avoid creating an intermediate rtx for it only
6501 for costing purposes. */
6508 }
6511 {
6512 /* CMN. */
6519 }
6521 /* CMP.
6523 Compare can freely swap the order of operands, and
6524 canonicalization puts the more complex operation first.
6525 But the integer MINUS logic expects the shift/extend
6526 operation in op1. */
6529 {
6532 }
6534 }
6537 {
6538 /* FCMP. */
6543 {
6545 /* FCMP supports constant 0.0 for no extra cost. */
6547 }
6549 }
6552 {
6553 /* Vector compare. */
6558 {
6559 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6560 cost. */
6562 }
6564 }
6568 {
6572 cost_minus:
6575 /* Detect valid immediates. */
6581 {
6583 /* SUB(S) (immediate). */
6586 }
6588 /* Look for SUB (extended register). */
6590 {
6598 }
6602 /* Cost this as an FMA-alike operation. */
6606 {
6609 speed);
6611 }
6616 {
6618 {
6619 /* Vector SUB. */
6621 }
6623 {
6624 /* SUB(S). */
6626 }
6628 {
6629 /* FSUB. */
6631 }
6632 }
6634 }
6637 {
6638 rtx new_op0;
6643 cost_plus:
6646 {
6647 /* CSINC. */
6651 }
6656 {
6660 /* ADD (immediate). */
6663 }
6667 /* Look for ADD (extended register). */
6669 {
6677 }
6679 /* Strip any extend, leave shifts behind as we will
6680 cost them through mult_cost. */
6685 {
6687 speed);
6689 }
6694 {
6696 {
6697 /* Vector ADD. */
6699 }
6701 {
6702 /* ADD. */
6704 }
6706 {
6707 /* FADD. */
6709 }
6710 }
6712 }
6718 {
6721 else
6723 }
6728 {
6732 {
6735 else
6737 }
6739 }
6742 {
6749 }
6750 /* Fall through. */
6753 cost_logic:
6758 {
6762 }
6770 {
6771 /* This is a UBFM/SBFM. */
6776 }
6779 {
6781 {
6782 /* We have a mask + shift version of a UBFIZ
6783 i.e. the *andim_ashift<mode>_bfiz pattern. */
6787 {
6794 }
6796 {
6797 /* We possibly get the immediate for free, this is not
6798 modelled. */
6804 }
6805 }
6806 else
6807 {
6810 /* Handle ORN, EON, or BIC. */
6816 /* If we had a shift on op0 then this is a logical-shift-
6817 by-register/immediate operation. Otherwise, this is just
6818 a logical operation. */
6820 {
6822 {
6823 /* Shift by immediate. */
6826 else
6828 }
6829 else
6831 }
6833 /* In both cases we want to cost both operands. */
6838 }
6839 }
6847 {
6848 /* Vector NOT. */
6851 }
6853 /* MVN-shifted-reg. */
6855 {
6862 }
6863 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
6864 Handle the second form here taking care that 'a' in the above can
6865 be a shift. */
6867 {
6876 {
6879 else
6881 }
6884 }
6885 /* MVN. */
6894 /* If a value is written in SI mode, then zero extended to DI
6895 mode, the operation will in general be free as a write to
6896 a 'w' register implicitly zeroes the upper bits of an 'x'
6897 register. However, if this is
6899 (set (reg) (zero_extend (reg)))
6901 we must cost the explicit register move. */
6905 {
6908 /* If OP_COST is non-zero, then the cost of the zero extend
6909 is effectively the cost of the inner operation. Otherwise
6910 we have a MOV instruction and we take the cost from the MOV
6911 itself. This is true independently of whether we are
6912 optimizing for space or time. */
6917 }
6919 {
6920 /* All loads can zero extend to any size for free. */
6923 }
6927 {
6932 }
6935 {
6937 {
6938 /* UMOV. */
6940 }
6941 else
6942 {
6943 /* We generate an AND instead of UXTB/UXTH. */
6945 }
6946 }
6951 {
6952 /* LDRSH. */
6954 {
6961 }
6963 }
6967 {
6972 }
6975 {
6978 else
6980 }
6988 {
6990 {
6992 {
6993 /* Vector shift (immediate). */
6995 }
6996 else
6997 {
6998 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
6999 aliases. */
7001 }
7002 }
7004 /* We can incorporate zero/sign extend for free. */
7011 }
7012 else
7013 {
7015 {
7017 {
7018 /* Vector shift (register). */
7020 }
7021 else
7022 {
7023 /* LSLV. */
7025 }
7026 }
7028 }
7038 {
7039 /* ASR (immediate) and friends. */
7041 {
7044 else
7046 }
7050 }
7051 else
7052 {
7054 /* ASR (register) and friends. */
7056 {
7059 else
7061 }
7063 }
7069 {
7070 /* LDR. */
7073 }
7076 {
7077 /* ADRP, followed by ADD. */
7081 }
7084 {
7085 /* ADR. */
7088 }
7091 {
7092 /* One extra load instruction, after accessing the GOT. */
7096 }
7101 /* ADRP/ADD (immediate). */
7108 /* UBFX/SBFX. */
7110 {
7113 else
7115 }
7117 /* We can trust that the immediates used will be correct (there
7118 are no by-register forms), so we need only cost op0. */
7124 /* aarch64_rtx_mult_cost always handles recursion to its
7125 operands. */
7129 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7130 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7131 an unconditional negate. This case should only ever be reached through
7132 the set_smod_pow2_cheap check in expmed.c. */
7136 {
7137 /* We expand to 4 instructions. Reset the baseline. */
7145 }
7147 /* Fall-through. */
7150 {
7162 }
7169 {
7173 /* There is no integer SQRT, so only DIV and UDIV can get
7174 here. */
7176 else
7178 }
7204 {
7207 else
7209 }
7211 /* FMSUB, FNMADD, and FNMSUB are free. */
7218 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7219 and the by-element operand as operand 0. */
7223 /* Catch vector-by-element operations. The by-element operand can
7224 either be (vec_duplicate (vec_select (x))) or just
7225 (vec_select (x)), depending on whether we are multiplying by
7226 a vector or a scalar.
7228 Canonicalization is not very good in these cases, FMA4 will put the
7229 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7240 /* If the remaining parameters are not registers,
7241 get the cost to put them into registers. */
7255 {
7257 {
7258 /*Vector truncate. */
7260 }
7261 else
7263 }
7268 {
7270 {
7271 /*Vector conversion. */
7273 }
7274 else
7276 }
7282 /* Strip the rounding part. They will all be implemented
7283 by the fcvt* family of instructions anyway. */
7285 {
7294 }
7297 {
7300 else
7302 }
7304 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7305 fixed-point fcvt. */
7310 {
7314 }
7321 {
7322 /* ABS (vector). */
7325 }
7327 {
7330 /* FABD, which is analogous to FADD. */
7332 {
7339 }
7340 /* Simple FABS is analogous to FNEG. */
7343 }
7344 else
7345 {
7346 /* Integer ABS will either be split to
7347 two arithmetic instructions, or will be an ABS
7348 (scalar), which we don't model. */
7352 }
7358 {
7361 else
7362 {
7363 /* FMAXNM/FMINNM/FMAX/FMIN.
7364 TODO: This may not be accurate for all implementations, but
7365 we do not model this in the cost tables. */
7367 }
7368 }
7372 /* The floating point round to integer frint* instructions. */
7374 {
7379 }
7382 {
7387 }
7392 /* Decompose <su>muldi3_highpart. */
7394 mode == DImode
7395 /* (lshiftrt:TI */
7398 /* (mult:TI */
7400 /* (ANY_EXTEND:TI (reg:DI))
7401 (ANY_EXTEND:TI (reg:DI))) */
7408 /* (const_int 64) */
7411 {
7412 /* UMULH/SMULH. */
7420 }
7422 /* Fall through. */
7425 }
7433 }
7435 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
7436 calculated for X. This cost is stored in *COST. Returns true
7437 if the total cost of X was calculated. */
7438 static bool
7441 {
7446 {
7451 }
7454 }
7456 static int
7459 {
7465 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
7472 /* Moving between GPR and stack cost is the same as GP2GP. */
7477 /* To/From the stack register, we move via the gprs. */
7483 {
7484 /* 128-bit operations on general registers require 2 instructions. */
7492 /* When AdvSIMD instructions are disabled it is not possible to move
7493 a 128-bit value directly between Q registers. This is handled in
7494 secondary reload. A general register is used as a scratch to move
7495 the upper DI value and the lower DI value is moved directly,
7496 hence the cost is the sum of three moves. */
7501 }
7511 }
7513 static int
7515 reg_class_t rclass ATTRIBUTE_UNUSED,
7517 {
7519 }
7521 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
7522 to optimize 1.0/sqrt. */
7524 static bool
7526 {
7528 && flag_unsafe_math_optimizations
7532 }
7534 /* Function to decide when to use the approximate reciprocal square root
7535 builtin. */
7537 static tree
7539 {
7545 }
7549 /* Select reciprocal square root initial estimate insn depending on machine
7550 mode. */
7552 static rsqrte_type
7554 {
7556 {
7563 }
7564 }
7568 /* Select reciprocal square root series step insn depending on machine mode. */
7570 static rsqrts_type
7572 {
7574 {
7581 }
7582 }
7584 /* Emit instruction sequence to compute either the approximate square root
7585 or its approximate reciprocal, depending on the flag RECP, and return
7586 whether the sequence was emitted or not. */
7588 bool
7590 {
7596 machine_mode mmsk = mode_for_vector
7600 && (flag_mlow_precision_sqrt
7604 && (flag_mrecip_low_precision_sqrt
7609 || flag_trapping_math
7610 || !flag_unsafe_math_optimizations
7617 /* When calculating the approximate square root, compare the argument with
7618 0.0 and create a mask. */
7622 /* Estimate the approximate reciprocal square root. */
7626 /* Iterate over the series twice for SF and thrice for DF. */
7629 /* Optionally iterate over the series once less for faster performance
7630 while sacrificing the accuracy. */
7633 iterations--;
7635 /* Iterate over the series to calculate the approximate reciprocal square
7636 root. */
7639 {
7647 }
7650 {
7651 /* Qualify the approximate reciprocal square root when the argument is
7652 0.0 by squashing the intermediary result to 0.0. */
7658 /* Calculate the approximate square root. */
7660 }
7662 /* Finalize the approximation. */
7666 }
7670 /* Select reciprocal initial estimate insn depending on machine mode. */
7672 static recpe_type
7674 {
7676 {
7683 }
7684 }
7688 /* Select reciprocal series step insn depending on machine mode. */
7690 static recps_type
7692 {
7694 {
7701 }
7702 }
7704 /* Emit the instruction sequence to compute the approximation for the division
7705 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
7707 bool
7709 {
7720 || flag_trapping_math
7721 || !flag_unsafe_math_optimizations
7726 /* Estimate the approximate reciprocal. */
7730 /* Iterate over the series twice for SF and thrice for DF. */
7733 /* Optionally iterate over the series once less for faster performance,
7734 while sacrificing the accuracy. */
7736 iterations--;
7738 /* Iterate over the series to calculate the approximate reciprocal. */
7741 {
7746 }
7749 {
7750 /* As the approximate reciprocal of DEN is already calculated, only
7751 calculate the approximate division when NUM is not 1.0. */
7754 }
7756 /* Finalize the approximation. */
7759 }
7761 /* Return the number of instructions that can be issued per cycle. */
7762 static int
7764 {
7766 }
7768 static int
7770 {
7774 }
7777 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
7778 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
7779 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
7781 static int
7784 {
7786 }
7789 /* Vectorizer cost model target hooks. */
7791 /* Implement targetm.vectorize.builtin_vectorization_cost. */
7792 static int
7794 tree vectype,
7796 {
7800 {
7849 }
7850 }
7852 /* Implement targetm.vectorize.add_stmt_cost. */
7853 static unsigned
7857 {
7862 {
7867 /* Statements in an inner loop relative to the loop being
7868 vectorized are weighted more heavily. The value here is
7869 arbitrary and could potentially be improved with analysis. */
7875 }
7878 }
7882 /* Parse the TO_PARSE string and put the architecture struct that it
7883 selects into RES and the architectural features into ISA_FLAGS.
7884 Return an aarch64_parse_opt_result describing the parse result.
7885 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
7887 static enum aarch64_parse_opt_result
7890 {
7902 else
7909 /* Loop through the list of supported ARCHes to find a match. */
7911 {
7913 {
7917 {
7918 /* TO_PARSE string contains at least one extension. */
7919 enum aarch64_parse_opt_result ext_res
7924 }
7925 /* Extension parsing was successful. Confirm the result
7926 arch and ISA flags. */
7930 }
7931 }
7933 /* ARCH name not found in list. */
7935 }
7937 /* Parse the TO_PARSE string and put the result tuning in RES and the
7938 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
7939 describing the parse result. If there is an error parsing, RES and
7940 ISA_FLAGS are left unchanged. */
7942 static enum aarch64_parse_opt_result
7945 {
7957 else
7964 /* Loop through the list of supported CPUs to find a match. */
7966 {
7968 {
7973 {
7974 /* TO_PARSE string contains at least one extension. */
7975 enum aarch64_parse_opt_result ext_res
7980 }
7981 /* Extension parsing was successfull. Confirm the result
7982 cpu and ISA flags. */
7986 }
7987 }
7989 /* CPU name not found in list. */
7991 }
7993 /* Parse the TO_PARSE string and put the cpu it selects into RES.
7994 Return an aarch64_parse_opt_result describing the parse result.
7995 If the parsing fails the RES does not change. */
7997 static enum aarch64_parse_opt_result
7999 {
8005 /* Loop through the list of supported CPUs to find a match. */
8007 {
8009 {
8012 }
8013 }
8015 /* CPU name not found in list. */
8017 }
8019 /* Parse TOKEN, which has length LENGTH to see if it is an option
8020 described in FLAG. If it is, return the index bit for that fusion type.
8021 If not, error (printing OPTION_NAME) and return zero. */
8023 static unsigned int
8028 {
8030 {
8034 }
8038 }
8040 /* Parse OPTION which is a comma-separated list of flags to enable.
8041 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8042 default state we inherit from the CPU tuning structures. OPTION_NAME
8043 gives the top-level option we are parsing in the -moverride string,
8044 for use in error messages. */
8046 static unsigned int
8051 {
8058 {
8061 token_length,
8062 flags,
8063 option_name);
8064 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8065 in the token stream, reset the supported operations. So:
8067 adrp+add.cmp+branch.none.adrp+add
8069 would have the result of turning on only adrp+add fusion. */
8075 }
8077 /* We ended with a comma, print something. */
8079 {
8082 }
8084 /* We still have one more token to parse. */
8087 token_length,
8088 flags,
8089 option_name);
8095 }
8097 /* Support for overriding instruction fusion. */
8099 static void
8102 {
8104 aarch64_fusible_pairs,
8107 }
8109 /* Support for overriding other tuning flags. */
8111 static void
8114 {
8115 tune->extra_tuning_flags
8117 aarch64_tuning_flags,
8120 }
8122 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8123 we understand. If it is, extract the option string and handoff to
8124 the appropriate function. */
8126 void
8130 {
8136 {
8139 }
8141 /* Get the length of the option name. */
8143 /* Skip the '=' to get to the option string. */
8144 option_part++;
8147 {
8149 {
8152 }
8153 }
8157 }
8159 /* A checking mechanism for the implementation of the tls size. */
8161 static void
8163 {
8168 {
8170 /* Both the default and maximum TLS size allowed under tiny is 1M which
8171 needs two instructions to address, so we clamp the size to 24. */
8176 /* The maximum TLS size allowed under small is 4G. */
8181 /* The maximum TLS size allowed under large is 16E.
8182 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8188 }
8191 }
8193 /* Parse STRING looking for options in the format:
8194 string :: option:string
8195 option :: name=substring
8196 name :: {a-z}
8197 substring :: defined by option. */
8199 static void
8202 {
8213 {
8215 /* Make this substring look like a string. */
8219 }
8221 /* One last option to parse. */
8224 }
8227 static void
8229 {
8230 /* The logic here is that if we are disabling all frame pointer generation
8231 then we do not need to disable leaf frame pointer generation as a
8232 separate operation. But if we are *only* disabling leaf frame pointer
8233 generation then we set flag_omit_frame_pointer to true, but in
8234 aarch64_frame_pointer_required we return false only for leaf functions.
8236 PR 70044: We have to be careful about being called multiple times for the
8237 same function. Once we have decided to set flag_omit_frame_pointer just
8238 so that we can omit leaf frame pointers, we must then not interpret a
8239 second call as meaning that all frame pointer generation should be
8240 omitted. We do this by setting flag_omit_frame_pointer to a special,
8241 non-zero value. */
8250 /* If not optimizing for size, set the default
8251 alignment to what the target wants. */
8253 {
8260 }
8262 /* We default to no pc-relative literal loads. */
8266 /* If -mpc-relative-literal-loads is set on the command line, this
8267 implies that the user asked for PC relative literal loads. */
8271 /* This is PR70113. When building the Linux kernel with
8272 CONFIG_ARM64_ERRATUM_843419, support for relocations
8273 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8274 removed from the kernel to avoid loading objects with possibly
8275 offending sequences. Without -mpc-relative-literal-loads we would
8276 generate such relocations, preventing the kernel build from
8277 succeeding. */
8282 /* In the tiny memory model it makes no sense to disallow PC relative
8283 literal pool loads. */
8288 /* When enabling the lower precision Newton series for the square root, also
8289 enable it for the reciprocal square root, since the latter is an
8290 intermediary step for the former. */
8293 }
8295 /* 'Unpack' up the internal tuning structs and update the options
8296 in OPTS. The caller must have set up selected_tune and selected_arch
8297 as all the other target-specific codegen decisions are
8298 derived from them. */
8300 void
8302 {
8305 /* Make a copy of the tuning parameters attached to the core, which
8306 we may later overwrite. */
8314 /* This target defaults to strict volatile bitfields. */
8323 {
8335 }
8337 /* We don't mind passing in global_options_set here as we don't use
8338 the *options_set structs anyway. */
8340 queue_depth,
8344 /* Set the L1 cache line size. */
8352 }
8354 /* Print a hint with a suggestion for a core or architecture name that
8355 most closely resembles what the user passed in STR. ARCH is true if
8356 the user is asking for an architecture name. ARCH is false if the user
8357 is asking for a core name. */
8359 static void
8361 {
8372 }
8374 /* Print a hint with a suggestion for a core name that most closely resembles
8375 what the user passed in STR. */
8379 {
8381 }
8383 /* Print a hint with a suggestion for an architecture name that most closely
8384 resembles what the user passed in STR. */
8388 {
8390 }
8392 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
8393 specified in STR and throw errors if appropriate. Put the results if
8394 they are valid in RES and ISA_FLAGS. Return whether the option is
8395 valid. */
8397 static bool
8400 {
8401 enum aarch64_parse_opt_result parse_res
8408 {
8421 }
8424 }
8426 /* Validate a command-line -march option. Parse the arch and extensions
8427 (if any) specified in STR and throw errors if appropriate. Put the
8428 results, if they are valid, in RES and ISA_FLAGS. Return whether the
8429 option is valid. */
8431 static bool
8434 {
8435 enum aarch64_parse_opt_result parse_res
8442 {
8455 }
8458 }
8460 /* Validate a command-line -mtune option. Parse the cpu
8461 specified in STR and throw errors if appropriate. Put the
8462 result, if it is valid, in RES. Return whether the option is
8463 valid. */
8465 static bool
8467 {
8468 enum aarch64_parse_opt_result parse_res
8475 {
8485 }
8487 }
8489 /* Return the CPU corresponding to the enum CPU.
8490 If it doesn't specify a cpu, return the default. */
8494 {
8498 /* The & 0x3f is to extract the bottom 6 bits that encode the
8499 default cpu as selected by the --with-cpu GCC configure option
8500 in config.gcc.
8501 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
8502 flags mechanism should be reworked to make it more sane. */
8504 }
8506 /* Return the architecture corresponding to the enum ARCH.
8507 If it doesn't specify a valid architecture, return the default. */
8511 {
8518 }
8520 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
8521 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
8522 tuning structs. In particular it must set selected_tune and
8523 aarch64_isa_flags that define the available ISA features and tuning
8524 decisions. It must also set selected_arch as this will be used to
8525 output the .arch asm tags for each function. */
8527 static void
8529 {
8542 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
8543 If either of -march or -mtune is given, they override their
8544 respective component of -mcpu. */
8556 /* If the user did not specify a processor, choose the default
8557 one for them. This will be the CPU set during configuration using
8558 --with-cpu, otherwise it is "generic". */
8560 {
8562 {
8566 }
8567 else
8568 {
8569 /* Get default configure-time CPU. */
8572 }
8576 }
8577 /* If both -mcpu and -march are specified check that they are architecturally
8578 compatible, warn if they're not and prefer the -march ISA flags. */
8580 {
8582 {
8586 }
8591 }
8592 else
8593 {
8594 /* -mcpu but no -march. */
8601 }
8603 /* Set the arch as well as we will need it when outputing
8604 the .arch directive in assembly. */
8606 {
8609 }
8614 #ifndef HAVE_AS_MABI_OPTION
8615 /* The compiler may have been configured with 2.23.* binutils, which does
8616 not have support for ILP32. */
8619 #endif
8621 /* Make sure we properly set up the explicit options. */
8632 /* Save these options as the default ones in case we push and pop them later
8633 while processing functions with potential target attributes. */
8634 target_option_default_node = target_option_current_node
8636 }
8638 /* Implement targetm.override_options_after_change. */
8640 static void
8642 {
8644 }
8648 {
8652 }
8654 void
8656 {
8658 }
8660 /* A checking mechanism for the implementation of the various code models. */
8661 static void
8663 {
8665 {
8667 {
8672 #ifdef HAVE_AS_SMALL_PIC_RELOCS
8674 ? AARCH64_CMODEL_SMALL_PIC
8676 #else
8678 #endif
8686 }
8687 }
8688 else
8690 }
8692 /* Implement TARGET_OPTION_SAVE. */
8694 static void
8696 {
8698 }
8700 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
8701 using the information saved in PTR. */
8703 static void
8705 {
8713 }
8715 /* Implement TARGET_OPTION_PRINT. */
8717 static void
8719 {
8730 }
8734 void
8736 {
8738 }
8740 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
8741 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
8742 make sure optab availability predicates are recomputed when necessary. */
8744 void
8746 {
8751 else
8753 }
8755 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
8756 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
8757 of the function, if such exists. This function may be called multiple
8758 times on a single function so use aarch64_previous_fndecl to avoid
8759 setting up identical state. */
8761 static void
8763 {
8767 tree old_tree = (aarch64_previous_fndecl
8773 /* If current function has no attributes but the previous one did,
8774 use the default node. */
8778 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
8779 the default have been handled by aarch64_save_restore_target_globals from
8780 aarch64_pragma_target_parse. */
8786 /* First set the target options. */
8790 }
8792 /* Enum describing the various ways we can handle attributes.
8793 In many cases we can reuse the generic option handling machinery. */
8795 enum aarch64_attr_opt_type
8796 {
8800 aarch64_attr_custom /* Attribute requires a custom handling function. */
8801 };
8803 /* All the information needed to handle a target attribute.
8804 NAME is the name of the attribute.
8805 ATTR_TYPE specifies the type of behavior of the attribute as described
8806 in the definition of enum aarch64_attr_opt_type.
8807 ALLOW_NEG is true if the attribute supports a "no-" form.
8808 HANDLER is the function that takes the attribute string and whether
8809 it is a pragma or attribute and handles the option. It is needed only
8810 when the ATTR_TYPE is aarch64_attr_custom.
8811 OPT_NUM is the enum specifying the option that the attribute modifies.
8812 This is needed for attributes that mirror the behavior of a command-line
8813 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
8814 aarch64_attr_enum. */
8816 struct aarch64_attribute_info
8817 {
8823 };
8825 /* Handle the ARCH_STR argument to the arch= target attribute.
8826 PRAGMA_OR_ATTR is used in potential error messages. */
8828 static bool
8830 {
8832 enum aarch64_parse_opt_result parse_res
8836 {
8841 }
8844 {
8858 }
8861 }
8863 /* Handle the argument CPU_STR to the cpu= target attribute.
8864 PRAGMA_OR_ATTR is used in potential error messages. */
8866 static bool
8868 {
8870 enum aarch64_parse_opt_result parse_res
8874 {
8882 }
8885 {
8899 }
8902 }
8904 /* Handle the argument STR to the tune= target attribute.
8905 PRAGMA_OR_ATTR is used in potential error messages. */
8907 static bool
8909 {
8911 enum aarch64_parse_opt_result parse_res
8915 {
8920 }
8923 {
8930 }
8933 }
8935 /* Parse an architecture extensions target attribute string specified in STR.
8936 For example "+fp+nosimd". Show any errors if needed. Return TRUE
8937 if successful. Update aarch64_isa_flags to reflect the ISA features
8938 modified.
8939 PRAGMA_OR_ATTR is used in potential error messages. */
8941 static bool
8943 {
8947 /* We allow "+nothing" in the beginning to clear out all architectural
8948 features if the user wants to handpick specific features. */
8950 {
8953 }
8958 {
8961 }
8964 {
8977 }
8980 }
8982 /* The target attributes that we support. On top of these we also support just
8983 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
8984 handled explicitly in aarch64_process_one_target_attr. */
8987 {
8989 OPT_mgeneral_regs_only },
8991 OPT_mfix_cortex_a53_835769 },
8993 OPT_mfix_cortex_a53_843419 },
8997 OPT_momit_leaf_frame_pointer },
9000 OPT_march_ },
9003 OPT_mtune_ },
9005 };
9007 /* Parse ARG_STR which contains the definition of one target attribute.
9008 Show appropriate errors if any or return true if the attribute is valid.
9009 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9010 we're processing a target attribute or pragma. */
9012 static bool
9014 {
9020 {
9023 }
9028 /* Skip leading whitespace. */
9030 str_to_check++;
9032 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9033 It is easier to detect and handle it explicitly here rather than going
9034 through the machinery for the rest of the target attributes in this
9035 function. */
9040 {
9043 }
9046 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9047 and point ARG to "foo". */
9049 {
9051 arg++;
9052 }
9056 {
9057 /* If the names don't match up, or the user has given an argument
9058 to an attribute that doesn't accept one, or didn't give an argument
9059 to an attribute that expects one, fail to match. */
9068 {
9072 }
9074 /* If the name matches but the attribute does not allow "no-" versions
9075 then we can't match. */
9077 {
9081 }
9084 {
9085 /* Has a custom handler registered.
9086 For example, cpu=, arch=, tune=. */
9093 /* Either set or unset a boolean option. */
9095 {
9103 }
9104 /* Set or unset a bit in the target_flags. aarch64_handle_option
9105 should know what mask to apply given the option number. */
9107 {
9109 /* We only need to specify the option number.
9110 aarch64_handle_option will know which mask to apply. */
9116 }
9117 /* Use the option setting machinery to set an option to an enum. */
9119 {
9126 {
9129 global_dc);
9130 }
9131 else
9132 {
9135 }
9137 }
9140 }
9141 }
9143 /* If we reached here we either have found an attribute and validated
9144 it or didn't match any. If we matched an attribute but its arguments
9145 were malformed we will have returned false already. */
9147 }
9149 /* Count how many times the character C appears in
9150 NULL-terminated string STR. */
9152 static unsigned int
9154 {
9157 {
9159 res++;
9161 str++;
9162 }
9165 }
9167 /* Parse the tree in ARGS that contains the target attribute information
9168 and update the global target options space. PRAGMA_OR_ATTR is a string
9169 to be used in error messages, specifying whether this is processing
9170 a target attribute or a target pragma. */
9172 bool
9174 {
9176 {
9177 do
9178 {
9181 {
9184 }
9189 }
9190 /* We expect to find a string to parse. */
9198 {
9201 }
9203 /* Used to catch empty spaces between commas i.e.
9204 attribute ((target ("attr1,,attr2"))). */
9207 /* Handle multiple target attributes separated by ','. */
9212 {
9213 num_attrs++;
9215 {
9218 }
9221 }
9224 {
9228 }
9231 }
9233 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9234 process attribute ((target ("..."))). */
9236 static bool
9238 {
9241 tree old_optimize;
9245 /* If what we're processing is the current pragma string then the
9246 target option node is already stored in target_option_current_node
9247 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9248 having to re-parse the string. This is especially useful to keep
9249 arm_neon.h compile times down since that header contains a lot
9250 of intrinsics enclosed in pragmas. */
9252 {
9255 }
9261 /* If the function changed the optimization levels as well as setting
9262 target options, start with the optimizations specified. */
9267 /* Save the current target options to restore at the end. */
9270 /* If fndecl already has some target attributes applied to it, unpack
9271 them so that we add this attribute on top of them, rather than
9272 overwriting them. */
9274 {
9280 }
9281 else
9288 /* Set up any additional state. */
9290 {
9292 /* Initialize SIMD builtins if we haven't already.
9293 Set current_target_pragma to NULL for the duration so that
9294 the builtin initialization code doesn't try to tag the functions
9295 being built with the attributes specified by any current pragma, thus
9296 going into an infinite recursion. */
9298 {
9303 }
9305 }
9306 else
9312 {
9317 }
9325 }
9327 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
9328 tri-bool options (yes, no, don't care) and the default value is
9329 DEF, determine whether to reject inlining. */
9331 static bool
9334 {
9335 /* If the callee doesn't care, always allow inlining. */
9339 /* If the caller doesn't care, always allow inlining. */
9343 /* Otherwise, allow inlining if either the callee and caller values
9344 agree, or if the callee is using the default value. */
9346 }
9348 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
9349 to inline CALLEE into CALLER based on target-specific info.
9350 Make sure that the caller and callee have compatible architectural
9351 features. Then go through the other possible target attributes
9352 and see if they can block inlining. Try not to reject always_inline
9353 callees unless they are incompatible architecturally. */
9355 static bool
9357 {
9361 /* If callee has no option attributes, then it is ok to inline. */
9372 /* Callee's ISA flags should be a subset of the caller's. */
9377 /* Allow non-strict aligned functions inlining into strict
9378 aligned ones. */
9388 /* If the architectural features match up and the callee is always_inline
9389 then the other attributes don't matter. */
9401 /* Honour explicit requests to workaround errata. */
9414 /* If the user explicitly specified -momit-leaf-frame-pointer for the
9415 caller and calle and they don't match up, reject inlining. */
9422 /* If the callee has specific tuning overrides, respect them. */
9427 /* If the user specified tuning override strings for the
9428 caller and callee and they don't match up, reject inlining.
9429 We just do a string compare here, we don't analyze the meaning
9430 of the string, as it would be too costly for little gain. */
9438 }
9440 /* Return true if SYMBOL_REF X binds locally. */
9442 static bool
9444 {
9448 }
9450 /* Return true if SYMBOL_REF X is thread local */
9451 static bool
9453 {
9461 }
9463 /* Classify a TLS symbol into one of the TLS kinds. */
9464 enum aarch64_symbol_type
9466 {
9470 {
9477 {
9483 }
9494 else
9503 }
9504 }
9506 /* Return the method that should be used to access SYMBOL_REF or
9507 LABEL_REF X. */
9509 enum aarch64_symbol_type
9511 {
9513 {
9515 {
9530 }
9531 }
9534 {
9539 {
9541 /* When we retrieve symbol + offset address, we have to make sure
9542 the offset does not cause overflow of the final address. But
9543 we have no way of knowing the address of symbol at compile time
9544 so we can't accurately say if the distance between the PC and
9545 symbol + offset is outside the addressible range of +/-1M in the
9546 TINY code model. So we rely on images not being greater than
9547 1M and cap the offset at 1M and anything beyond 1M will have to
9548 be loaded using an alternative mechanism. Furthermore if the
9549 symbol is a weak reference to something that isn't known to
9550 resolve to a symbol in this module, then force to memory. */
9558 /* Same reasoning as the tiny code model, but the offset cap here is
9559 4G. */
9580 /* This is alright even in PIC code as the constant
9581 pool reference is always PC relative and within
9582 the same translation unit. */
9585 else
9590 }
9591 }
9593 /* By default push everything into the constant pool. */
9595 }
9597 bool
9599 {
9601 }
9603 bool
9605 {
9613 }
9615 /* Return true if X holds either a quarter-precision or
9616 floating-point +0.0 constant. */
9617 static bool
9619 {
9626 /* We only handle moving 0.0 to a TFmode register. */
9631 }
9633 static bool
9635 {
9636 /* Do not allow vector struct mode constants. We could support
9637 0 and -1 easily, but they need support in aarch64-simd.md. */
9641 /* This could probably go away because
9642 we now decompose CONST_INTs according to expand_mov_immediate. */
9653 }
9655 rtx
9657 {
9663 /* Can return in any reg. */
9666 }
9668 /* On AAPCS systems, this is the "struct __va_list". */
9671 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
9672 Return the type to use as __builtin_va_list.
9674 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
9676 struct __va_list
9677 {
9678 void *__stack;
9679 void *__gr_top;
9680 void *__vr_top;
9681 int __gr_offs;
9682 int __vr_offs;
9683 }; */
9685 static tree
9687 {
9688 tree va_list_name;
9691 /* Create the type. */
9693 /* Give it the required name. */
9695 TYPE_DECL,
9697 va_list_type);
9702 /* Create the fields. */
9705 ptr_type_node);
9708 ptr_type_node);
9711 ptr_type_node);
9714 integer_type_node);
9717 integer_type_node);
9719 /* Tell tree-stdarg pass about our internal offset fields.
9720 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
9721 purpose to identify whether the code is updating va_list internal
9722 offset fields through irregular way. */
9744 /* Compute its layout. */
9748 }
9750 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
9751 static void
9753 {
9757 tree t;
9771 {
9774 }
9783 NULL_TREE);
9785 NULL_TREE);
9787 NULL_TREE);
9789 NULL_TREE);
9791 NULL_TREE);
9793 /* Emit code to initialize STACK, which points to the next varargs stack
9794 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
9795 by named arguments. STACK is 8-byte aligned. */
9802 /* Emit code to initialize GRTOP, the top of the GR save area.
9803 virtual_incoming_args_rtx should have been 16 byte aligned. */
9808 /* Emit code to initialize VRTOP, the top of the VR save area.
9809 This address is gr_save_area_bytes below GRTOP, rounded
9810 down to the next 16-byte boundary. */
9820 /* Emit code to initialize GROFF, the offset from GRTOP of the
9821 next GPR argument. */
9826 /* Likewise emit code to initialize VROFF, the offset from FTOP
9827 of the next VR argument. */
9831 }
9833 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
9835 static tree
9838 {
9839 tree addr;
9845 machine_mode mode;
9872 type,
9876 {
9877 /* TYPE passed in fp/simd registers. */
9889 {
9892 }
9895 {
9897 }
9898 }
9899 else
9900 {
9901 /* TYPE passed in general registers. */
9914 {
9916 }
9917 }
9919 /* Get a local temporary for the field value. */
9922 /* Emit code to branch if off >= 0. */
9928 {
9929 /* Emit: offs = (offs + 15) & -16. */
9935 }
9936 else
9939 /* Update ap.__[g|v]r_offs */
9944 /* String up. */
9948 /* [cond2] if (ap.__[g|v]r_offs > 0) */
9953 /* String up: make sure the assignment happens before the use. */
9957 /* Prepare the trees handling the argument that is passed on the stack;
9958 the top level node will store in ON_STACK. */
9961 {
9962 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
9970 }
9971 else
9973 /* Advance ap.__stack */
9981 /* String up roundup and advance. */
9984 /* String up with arg */
9986 /* Big-endianness related address adjustment. */
9989 {
9993 }
9998 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10008 {
10009 /* type ha; // treat as "struct {ftype field[n];}"
10010 ... [computing offs]
10011 for (i = 0; i <nregs; ++i, offs += 16)
10012 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10013 return ha; */
10017 /* Declare a local variable. */
10021 /* Establish the base type. */
10023 {
10042 {
10046 }
10050 }
10052 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10060 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10062 {
10072 }
10076 }
10086 }
10088 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10090 static void
10094 {
10096 CUMULATIVE_ARGS local_cum;
10100 /* The caller has advanced CUM up to, but not beyond, the last named
10101 argument. Advance a local copy of CUM past the last "real" named
10102 argument, to find out how many registers are left over. */
10106 /* Found out how many registers we need to save.
10107 Honor tree-stdvar analysis results. */
10116 {
10119 }
10122 {
10124 {
10127 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10135 }
10137 {
10138 /* We can't use move_block_from_reg, because it will use
10139 the wrong mode, storing D regs only. */
10143 /* Set OFF to the offset from virtual_incoming_args_rtx of
10144 the first vector register. The VR save area lies below
10145 the GR one, and is aligned to 16 bytes. */
10152 {
10160 }
10161 }
10162 }
10164 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10165 any complication of having crtl->args.pretend_args_size changed. */
10170 }
10172 static void
10174 {
10177 {
10179 {
10182 }
10183 }
10184 }
10186 /* Walk down the type tree of TYPE counting consecutive base elements.
10187 If *MODEP is VOIDmode, then set it to the first valid floating point
10188 type. If a non-floating point type is found, or if a floating point
10189 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10190 otherwise return the count in the sub-tree. */
10191 static int
10193 {
10194 machine_mode mode;
10195 HOST_WIDE_INT size;
10198 {
10228 /* Use V2SImode and V4SImode as representatives of all 64-bit
10229 and 128-bit vector types. */
10232 {
10241 }
10246 /* Vector modes are considered to be opaque: two vectors are
10247 equivalent for the purposes of being homogeneous aggregates
10248 if they are the same size. */
10255 {
10259 /* Can't handle incomplete types nor sizes that are not
10260 fixed. */
10267 || !index
10278 /* There must be no padding. */
10283 }
10286 {
10289 tree field;
10291 /* Can't handle incomplete types nor sizes that are not
10292 fixed. */
10298 {
10306 }
10308 /* There must be no padding. */
10313 }
10317 {
10318 /* These aren't very interesting except in a degenerate case. */
10321 tree field;
10323 /* Can't handle incomplete types nor sizes that are not
10324 fixed. */
10330 {
10338 }
10340 /* There must be no padding. */
10345 }
10349 }
10352 }
10354 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
10355 type as described in AAPCS64 \S 4.1.2.
10357 See the comment above aarch64_composite_type_p for the notes on MODE. */
10359 static bool
10361 machine_mode mode)
10362 {
10372 }
10374 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
10375 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
10376 array types. The C99 floating-point complex types are also considered
10377 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
10378 types, which are GCC extensions and out of the scope of AAPCS64, are
10379 treated as composite types here as well.
10381 Note that MODE itself is not sufficient in determining whether a type
10382 is such a composite type or not. This is because
10383 stor-layout.c:compute_record_mode may have already changed the MODE
10384 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
10385 structure with only one field may have its MODE set to the mode of the
10386 field. Also an integer mode whose size matches the size of the
10387 RECORD_TYPE type may be used to substitute the original mode
10388 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
10389 solely relied on. */
10391 static bool
10393 machine_mode mode)
10394 {
10407 }
10409 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
10410 shall be passed or returned in simd/fp register(s) (providing these
10411 parameter passing registers are available).
10413 Upon successful return, *COUNT returns the number of needed registers,
10414 *BASE_MODE returns the mode of the individual register and when IS_HAF
10415 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
10416 floating-point aggregate or a homogeneous short-vector aggregate. */
10418 static bool
10420 const_tree type,
10424 {
10432 {
10435 }
10437 {
10441 }
10443 {
10447 {
10450 }
10451 else
10453 }
10454 else
10459 }
10461 /* Implement TARGET_STRUCT_VALUE_RTX. */
10463 static rtx
10466 {
10468 }
10470 /* Implements target hook vector_mode_supported_p. */
10471 static bool
10473 {
10485 }
10487 /* Return appropriate SIMD container
10488 for MODE within a vector of WIDTH bits. */
10489 static machine_mode
10491 {
10494 {
10497 {
10512 }
10513 else
10515 {
10526 }
10527 }
10529 }
10531 /* Return 128-bit container as the preferred SIMD mode for MODE. */
10532 static machine_mode
10534 {
10536 }
10538 /* Return the bitmask of possible vector sizes for the vectorizer
10539 to iterate over. */
10540 static unsigned int
10542 {
10544 }
10546 /* Implement TARGET_MANGLE_TYPE. */
10550 {
10551 /* The AArch64 ABI documents say that "__va_list" has to be
10552 managled as if it is in the "std" namespace. */
10556 /* Half-precision float. */
10560 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
10561 builtin types. */
10565 /* Use the default mangling. */
10567 }
10570 /* Return true if the rtx_insn contains a MEM RTX somewhere
10571 in it. */
10573 static bool
10575 {
10582 }
10584 /* Find the first rtx_insn before insn that will generate an assembly
10585 instruction. */
10589 {
10593 do
10594 {
10596 }
10600 }
10602 static bool
10604 {
10606 /* A number of these may be AArch32 only. */
10611 };
10614 {
10617 }
10620 }
10622 /* Check if there is a register dependency between a load and the insn
10623 for which we hold recog_data. */
10625 static bool
10627 {
10628 rtx load_reg;
10638 {
10644 }
10646 }
10649 /* When working around the Cortex-A53 erratum 835769,
10650 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
10651 instruction and has a preceding memory instruction such that a NOP
10652 should be inserted between them. */
10654 bool
10656 {
10659 rtx body;
10672 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
10673 Restore recog state to INSN to avoid state corruption. */
10681 /* If the previous insn is a memory op and there is no dependency between
10682 it and the DImode madd, emit a NOP between them. If body is NULL then we
10683 have a complex memory operation, probably a load/store pair.
10684 Be conservative for now and emit a NOP. */
10691 }
10694 /* Implement FINAL_PRESCAN_INSN. */
10696 void
10698 {
10701 }
10704 /* Return the equivalent letter for size. */
10705 static char
10707 {
10709 {
10715 }
10716 }
10718 /* Return true iff x is a uniform vector of floating-point
10719 constants, and the constant can be represented in
10720 quarter-precision form. Note, as aarch64_float_const_representable
10721 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
10722 static bool
10724 {
10725 rtx elt;
10729 }
10731 /* Return true for valid and false for invalid. */
10732 bool
10735 {
10736 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
10737 matches = 1; \
10738 for (i = 0; i < idx; i += (STRIDE)) \
10739 if (!(TEST)) \
10740 matches = 0; \
10741 if (matches) \
10742 { \
10743 immtype = (CLASS); \
10744 elsize = (ELSIZE); \
10745 eshift = (SHIFT); \
10746 emvn = (NEG); \
10747 break; \
10748 }
10758 {
10764 {
10769 }
10772 }
10774 /* Splat vector constant out into a byte vector. */
10776 {
10777 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
10778 it must be laid out in the vector register in reverse order. */
10786 {
10789 }
10791 }
10793 /* Sanity check. */
10796 do
10797 {
10846 }
10853 {
10863 /* Un-invert bytes of recognized vector, if necessary. */
10869 {
10870 /* FIXME: Broken on 32-bit H_W_I hosts. */
10879 }
10880 else
10881 {
10885 /* Construct 'abcdefgh' because the assembler cannot handle
10886 generic constants. */
10891 }
10892 }
10895 #undef CHECK
10896 }
10898 /* Check of immediate shift constants are within range. */
10899 bool
10901 {
10905 else
10907 }
10909 /* Return true if X is a uniform vector where all elements
10910 are either the floating-point constant 0.0 or the
10911 integer constant 0. */
10912 bool
10914 {
10916 }
10919 /* Return the bitmask CONST_INT to select the bits required by a zero extract
10920 operation of width WIDTH at bit position POS. */
10922 rtx
10924 {
10928 unsigned HOST_WIDE_INT mask
10931 }
10933 bool
10935 {
10940 {
10945 }
10948 }
10950 bool
10952 {
10965 }
10967 /* Return a const_int vector of VAL. */
10968 rtx
10970 {
10979 }
10981 /* Check OP is a legal scalar immediate for the MOVI instruction. */
10983 bool
10985 {
10986 machine_mode vmode;
10992 }
10994 /* Construct and return a PARALLEL RTX vector with elements numbering the
10995 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
10996 the vector - from the perspective of the architecture. This does not
10997 line up with GCC's perspective on lane numbers, so we end up with
10998 different masks depending on our target endian-ness. The diagram
10999 below may help. We must draw the distinction when building masks
11000 which select one half of the vector. An instruction selecting
11001 architectural low-lanes for a big-endian target, must be described using
11002 a mask selecting GCC high-lanes.
11004 Big-Endian Little-Endian
11006 GCC 0 1 2 3 3 2 1 0
11007 | x | x | x | x | | x | x | x | x |
11008 Architecture 3 2 1 0 3 2 1 0
11010 Low Mask: { 2, 3 } { 0, 1 }
11011 High Mask: { 0, 1 } { 2, 3 }
11012 */
11014 rtx
11016 {
11022 rtx t1;
11027 else
11035 }
11037 /* Check OP for validity as a PARALLEL RTX vector with elements
11038 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11039 from the perspective of the architecture. See the diagram above
11040 aarch64_simd_vect_par_cnst_half for more details. */
11042 bool
11045 {
11058 {
11065 }
11067 }
11069 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11070 HIGH (exclusive). */
11071 void
11073 const_tree exp)
11074 {
11075 HOST_WIDE_INT lane;
11080 {
11083 else
11085 }
11086 }
11088 /* Return TRUE if OP is a valid vector addressing mode. */
11089 bool
11091 {
11094 }
11096 /* Emit a register copy from operand to operand, taking care not to
11097 early-clobber source registers in the process.
11099 COUNT is the number of components into which the copy needs to be
11100 decomposed. */
11101 void
11104 {
11114 else
11118 }
11120 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11121 one of VSTRUCT modes: OI, CI, or XI. */
11122 int
11124 {
11126 }
11128 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11129 alignment of a vector to 128 bits. */
11130 static HOST_WIDE_INT
11132 {
11135 }
11137 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11138 static bool
11140 {
11144 /* We guarantee alignment for vectors up to 128-bits. */
11149 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11151 }
11153 /* If VALS is a vector constant that can be loaded into a register
11154 using DUP, generate instructions to do so and return an RTX to
11155 assign to the register. Otherwise return NULL_RTX. */
11156 static rtx
11158 {
11161 rtx x;
11166 /* We can load this constant by using DUP and a constant in a
11167 single ARM register. This will be cheaper than a vector
11168 load. */
11171 }
11174 /* Generate code to load VALS, which is a PARALLEL containing only
11175 constants (for vec_init) or CONST_VECTOR, efficiently into a
11176 register. Returns an RTX to copy into the register, or NULL_RTX
11177 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11178 static rtx
11180 {
11182 rtx const_dup;
11191 {
11192 /* A CONST_VECTOR must contain only CONST_INTs and
11193 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11194 Only store valid constants in a CONST_VECTOR. */
11196 {
11199 n_const++;
11200 }
11203 }
11204 else
11209 /* Load using MOVI/MVNI. */
11212 /* Loaded using DUP. */
11215 /* Load from constant pool. We can not take advantage of single-cycle
11216 LD1 because we need a PC-relative addressing mode. */
11218 else
11219 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11220 We can not construct an initializer. */
11222 }
11224 /* Expand a vector initialisation sequence, such that TARGET is
11225 initialised to contain VALS. */
11227 void
11229 {
11232 /* The number of vector elements. */
11234 /* The number of vector elements which are not constant. */
11237 /* The first element of vals. */
11241 /* Count the number of variable elements to initialise. */
11243 {
11247 else
11251 }
11253 /* No variable elements, hand off to aarch64_simd_make_constant which knows
11254 how best to handle this. */
11256 {
11259 {
11262 }
11263 }
11265 /* Splat a single non-constant element if we can. */
11267 {
11271 }
11273 /* Initialise a vector which is part-variable. We want to first try
11274 to build those lanes which are constant in the most efficient way we
11275 can. */
11277 {
11280 /* Load constant part of vector. We really don't care what goes into the
11281 parts we will overwrite, but we're more likely to be able to load the
11282 constant efficiently if it has fewer, larger, repeating parts
11283 (see aarch64_simd_valid_immediate). */
11285 {
11291 {
11292 /* Look in the copied vector, as more elements are const. */
11295 {
11298 }
11299 }
11301 }
11303 }
11305 /* Insert the variable lanes directly. */
11311 {
11317 }
11318 }
11320 static unsigned HOST_WIDE_INT
11322 {
11323 return
11324 (!SHIFT_COUNT_TRUNCATED
11327 }
11329 /* Select a format to encode pointers in exception handling data. */
11330 int
11332 {
11335 {
11341 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
11342 for everything. */
11346 /* No assumptions here. 8-byte relocs required. */
11349 }
11351 }
11353 /* The last .arch and .tune assembly strings that we printed. */
11357 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
11358 by the function fndecl. */
11360 void
11362 tree fndecl)
11363 {
11369 else
11380 /* Only update the assembler .arch string if it is distinct from the last
11381 such string we printed. */
11384 {
11387 }
11389 /* Print the cpu name we're tuning for in the comments, might be
11390 useful to readers of the generated asm. Do it only when it changes
11391 from function to function and verbose assembly is requested. */
11396 {
11400 }
11402 /* Don't forget the type directive for ELF. */
11405 }
11407 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
11409 static void
11411 {
11428 }
11430 /* Emit load exclusive. */
11432 static void
11435 {
11439 {
11446 }
11449 }
11451 /* Emit store exclusive. */
11453 static void
11456 {
11460 {
11467 }
11470 }
11472 /* Mark the previous jump instruction as unlikely. */
11474 static void
11476 {
11481 }
11483 /* Expand a compare and swap pattern. */
11485 void
11487 {
11492 gen_cas_fn gen;
11494 {
11495 gen_aarch64_compare_and_swapqi,
11496 gen_aarch64_compare_and_swaphi,
11497 gen_aarch64_compare_and_swapsi,
11498 gen_aarch64_compare_and_swapdi
11499 };
11501 {
11502 gen_aarch64_compare_and_swapqi_lse,
11503 gen_aarch64_compare_and_swaphi_lse,
11504 gen_aarch64_compare_and_swapsi_lse,
11505 gen_aarch64_compare_and_swapdi_lse
11506 };
11519 /* Normally the succ memory model must be stronger than fail, but in the
11520 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
11521 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
11528 {
11531 /* For short modes, we're going to perform the comparison in SImode,
11532 so do the zero-extension now. */
11536 /* Fall through. */
11540 /* Force the value into a register if needed. */
11547 }
11550 {
11557 }
11560 else
11571 }
11573 /* Test whether the target supports using a atomic load-operate instruction.
11574 CODE is the operation and AFTER is TRUE if the data in memory after the
11575 operation should be returned and FALSE if the data before the operation
11576 should be returned. Returns FALSE if the operation isn't supported by the
11577 architecture. */
11579 bool
11581 {
11586 {
11596 }
11597 }
11599 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
11600 sequence implementing an atomic operation. */
11602 static void
11604 {
11611 {
11613 }
11614 }
11616 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
11617 for the data in memory. EXPECTED is the value expected to be in memory.
11618 DESIRED is the value to store to memory. MEM is the memory location. MODEL
11619 is the memory ordering to use. */
11621 void
11624 rtx model)
11625 {
11627 machine_mode mode;
11632 {
11639 }
11641 /* Move the expected value into the CAS destination register. */
11644 /* Emit the CAS. */
11647 /* Compare the expected value with the value loaded by the CAS, to establish
11648 whether the swap was made. */
11650 }
11652 /* Split a compare and swap pattern. */
11654 void
11656 {
11658 machine_mode mode;
11663 rtx model_rtx;
11677 {
11680 }
11683 /* The initial load can be relaxed for a __sync operation since a final
11684 barrier will be emitted to stop code hoisting. */
11688 else
11700 {
11705 }
11706 else
11707 {
11711 }
11715 /* Emit any final barrier needed for a __sync operation. */
11718 }
11720 /* Emit a BIC instruction. */
11722 static void
11724 {
11729 {
11734 }
11737 }
11739 /* Emit an atomic swap. */
11741 static void
11744 {
11748 {
11755 }
11758 }
11760 /* Operations supported by aarch64_emit_atomic_load_op. */
11762 enum aarch64_atomic_load_op_code
11763 {
11767 AARCH64_LDOP_BIC /* A & ~B */
11768 };
11770 /* Emit an atomic load-operate. */
11772 static void
11776 {
11779 {
11780 gen_aarch64_atomic_loadaddqi,
11781 gen_aarch64_atomic_loadaddhi,
11782 gen_aarch64_atomic_loadaddsi,
11783 gen_aarch64_atomic_loadadddi
11784 };
11786 {
11787 gen_aarch64_atomic_loadeorqi,
11788 gen_aarch64_atomic_loadeorhi,
11789 gen_aarch64_atomic_loadeorsi,
11790 gen_aarch64_atomic_loadeordi
11791 };
11793 {
11794 gen_aarch64_atomic_loadsetqi,
11795 gen_aarch64_atomic_loadsethi,
11796 gen_aarch64_atomic_loadsetsi,
11797 gen_aarch64_atomic_loadsetdi
11798 };
11800 {
11801 gen_aarch64_atomic_loadclrqi,
11802 gen_aarch64_atomic_loadclrhi,
11803 gen_aarch64_atomic_loadclrsi,
11804 gen_aarch64_atomic_loadclrdi
11805 };
11806 aarch64_atomic_load_op_fn gen;
11810 {
11817 }
11820 {
11827 }
11830 }
11832 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
11833 location to store the data read from memory. OUT_RESULT is the location to
11834 store the result of the operation. MEM is the memory location to read and
11835 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
11836 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
11837 be NULL. */
11839 void
11842 {
11846 aarch64_atomic_load_op_code ldop_code;
11847 rtx src;
11848 rtx x;
11856 /* Make sure the value is in a register, putting it into a destination
11857 register if it needs to be manipulated. */
11860 {
11863 }
11864 else
11868 /* Preprocess the data for the operation as necessary. If the operation is
11869 a SET then emit a swap instruction and finish. */
11871 {
11877 /* Negate the value and treat it as a PLUS. */
11878 {
11879 rtx neg_src;
11881 /* Resize the value if necessary. */
11890 }
11891 /* Fall-through. */
11905 {
11906 rtx not_src;
11908 /* Resize the value if necessary. */
11917 }
11922 /* The operation can't be done with atomic instructions. */
11924 }
11928 /* If necessary, calculate the data in memory after the update by redoing the
11929 operation from values in registers. */
11934 {
11938 }
11943 {
11959 }
11964 }
11966 /* Split an atomic operation. */
11968 void
11971 {
11977 rtx x;
11979 /* Split the atomic operation into a sequence. */
11987 else
11991 /* The initial load can be relaxed for a __sync operation since a final
11992 barrier will be emitted to stop code hoisting. */
11996 else
12000 {
12014 {
12017 }
12018 /* Fall through. */
12024 }
12034 /* Emit any final barrier needed for a __sync operation. */
12037 }
12039 static void
12041 {
12042 /* Half-precision float operations. The compiler handles all operations
12043 with NULL libfuncs by converting to SFmode. */
12045 /* Conversions. */
12049 /* Arithmetic. */
12056 /* Comparisons. */
12064 }
12066 /* Target hook for c_mode_for_suffix. */
12067 static machine_mode
12069 {
12074 }
12076 /* We can only represent floating point constants which will fit in
12077 "quarter-precision" values. These values are characterised by
12078 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12079 by:
12081 (-1)^s * (n/16) * 2^r
12083 Where:
12084 's' is the sign bit.
12085 'n' is an integer in the range 16 <= n <= 31.
12086 'r' is an integer in the range -3 <= r <= 4. */
12088 /* Return true iff X can be represented by a quarter-precision
12089 floating point immediate operand X. Note, we cannot represent 0.0. */
12090 bool
12092 {
12093 /* This represents our current view of how many bits
12094 make up the mantissa. */
12104 /* We don't support HFmode constants yet. */
12110 /* We cannot represent infinities, NaNs or +/-zero. We won't
12111 know if we have +zero until we analyse the mantissa, but we
12112 can reject the other invalid values. */
12117 /* Extract exponent. */
12121 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12122 highest (sign) bit, with a fixed binary point at bit point_pos.
12123 m1 holds the low part of the mantissa, m2 the high part.
12124 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12125 bits for the mantissa, this can fail (low bits will be lost). */
12129 /* If the low part of the mantissa has bits set we cannot represent
12130 the value. */
12133 /* We have rejected the lower HOST_WIDE_INT, so update our
12134 understanding of how many bits lie in the mantissa and
12135 look only at the high HOST_WIDE_INT. */
12139 /* We can only represent values with a mantissa of the form 1.xxxx. */
12144 /* Having filtered unrepresentable values, we may now remove all
12145 but the highest 5 bits. */
12148 /* We cannot represent the value 0.0, so reject it. This is handled
12149 elsewhere. */
12153 /* Then, as bit 4 is always set, we can mask it off, leaving
12154 the mantissa in the range [0, 15]. */
12158 /* GCC internally does not use IEEE754-like encoding (where normalized
12159 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12160 Our mantissa values are shifted 4 places to the left relative to
12161 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12162 by 5 places to correct for GCC's representation. */
12166 }
12170 machine_mode mode,
12172 {
12182 /* This will return true to show const_vector is legal for use as either
12183 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
12184 also update INFO to show how the immediate should be generated. */
12193 {
12195 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
12196 move immediate path. */
12199 else
12200 {
12209 else
12213 }
12214 }
12227 else
12231 }
12235 machine_mode mode)
12236 {
12237 machine_mode vmode;
12243 }
12245 /* Split operands into moves from op[1] + op[2] into op[0]. */
12247 void
12249 {
12260 {
12261 /* No-op move. Can't split to nothing; emit something. */
12264 }
12266 /* Preserve register attributes for variable tracking. */
12271 /* Special case of reversed high/low parts. */
12274 {
12278 }
12280 {
12281 /* Try to avoid unnecessary moves if part of the result
12282 is in the right place already. */
12287 }
12288 else
12289 {
12294 }
12295 }
12297 /* vec_perm support. */
12299 #define MAX_VECT_LEN 16
12301 struct expand_vec_perm_d
12302 {
12305 machine_mode vmode;
12309 };
12311 /* Generate a variable permutation. */
12313 static void
12315 {
12326 {
12328 {
12329 /* Expand the argument to a V16QI mode by duplicating it. */
12333 }
12334 else
12335 {
12337 }
12338 }
12339 else
12340 {
12341 rtx pair;
12344 {
12348 }
12349 else
12350 {
12354 }
12355 }
12356 }
12358 void
12360 {
12364 rtx mask;
12366 /* The TBL instruction does not use a modulo index, so we must take care
12367 of that ourselves. */
12372 /* For big-endian, we also need to reverse the index within the vector
12373 (but not which vector). */
12375 {
12376 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
12381 }
12383 }
12385 /* Recognize patterns suitable for the TRN instructions. */
12386 static bool
12388 {
12397 /* Note that these are little-endian tests.
12398 We correct for big-endian later. */
12403 else
12408 {
12413 }
12415 /* Success! */
12422 {
12425 }
12429 {
12431 {
12446 }
12447 }
12448 else
12449 {
12451 {
12466 }
12467 }
12471 }
12473 /* Recognize patterns suitable for the UZP instructions. */
12474 static bool
12476 {
12485 /* Note that these are little-endian tests.
12486 We correct for big-endian later. */
12491 else
12496 {
12500 }
12502 /* Success! */
12509 {
12512 }
12516 {
12518 {
12533 }
12534 }
12535 else
12536 {
12538 {
12553 }
12554 }
12558 }
12560 /* Recognize patterns suitable for the ZIP instructions. */
12561 static bool
12563 {
12572 /* Note that these are little-endian tests.
12573 We correct for big-endian later. */
12576 /* Do Nothing. */
12577 ;
12580 else
12585 {
12592 }
12594 /* Success! */
12601 {
12604 }
12608 {
12610 {
12625 }
12626 }
12627 else
12628 {
12630 {
12645 }
12646 }
12650 }
12652 /* Recognize patterns for the EXT insn. */
12654 static bool
12656 {
12659 rtx offset;
12663 /* Check if the extracted indices are increasing by one. */
12665 {
12668 {
12669 /* We'll pass the same vector in twice, so allow indices to wrap. */
12671 }
12674 }
12677 {
12692 }
12694 /* Success! */
12698 /* The case where (location == 0) is a no-op for both big- and little-endian,
12699 and is removed by the mid-end at optimization levels -O1 and higher. */
12702 {
12703 /* After setup, we want the high elements of the first vector (stored
12704 at the LSB end of the register), and the low elements of the second
12705 vector (stored at the MSB end of the register). So swap. */
12707 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
12709 }
12714 }
12716 /* Recognize patterns for the REV insns. */
12718 static bool
12720 {
12729 {
12732 {
12737 }
12741 {
12748 }
12752 {
12765 }
12769 }
12773 {
12774 /* This is guaranteed to be true as the value of diff
12775 is 7, 3, 1 and we should have enough elements in the
12776 queue to generate this. Getting a vector mask with a
12777 value of diff other than these values implies that
12778 something is wrong by the time we get here. */
12782 }
12784 /* Success! */
12790 }
12792 static bool
12794 {
12797 rtx in0;
12800 rtx lane;
12804 {
12807 }
12809 /* The generic preparation in aarch64_expand_vec_perm_const_1
12810 swaps the operand order and the permute indices if it finds
12811 d->perm[0] to be in the second operand. Thus, we can always
12812 use d->op0 and need not do any extra arithmetic to get the
12813 correct lane number. */
12818 {
12833 }
12837 }
12839 static bool
12841 {
12849 /* Generic code will try constant permutation twice. Once with the
12850 original mode and again with the elements lowered to QImode.
12851 So wait and don't do the selector expansion ourselves. */
12856 {
12859 /* If big-endian and two vectors we end up with a weird mixed-endian
12860 mode on NEON. Reverse the index within each word but not the word
12861 itself. */
12864 }
12870 }
12872 static bool
12874 {
12875 /* The pattern matching functions above are written to look for a small
12876 number to begin the sequence (0, 1, N/2). If we begin with an index
12877 from the second operand, we can swap the operands. */
12879 {
12887 }
12890 {
12904 }
12906 }
12908 /* Expand a vec_perm_const pattern. */
12910 bool
12912 {
12926 {
12931 }
12934 {
12943 /* The elements of PERM do not suggest that only the first operand
12944 is used, but both operands are identical. Allow easier matching
12945 of the permutation by folding the permutation into the single
12946 input vector. */
12947 /* Fall Through. */
12959 }
12962 }
12964 static bool
12967 {
12977 /* Calculate whether all elements are in one vector. */
12979 {
12983 }
12985 /* If all elements are from the second vector, reindex as if from the
12986 first vector. */
12991 /* Check whether the mask can be applied to a single vector. */
13004 }
13006 rtx
13008 {
13009 /* We have to reverse each vector because we dont have
13010 a permuted load that can reverse-load according to ABI rules. */
13011 rtx mask;
13025 }
13027 /* Implement MODES_TIEABLE_P. In principle we should always return true.
13028 However due to issues with register allocation it is preferable to avoid
13029 tieing integer scalar and FP scalar modes. Executing integer operations
13030 in general registers is better than treating them as scalar vector
13031 operations. This reduces latency and avoids redundant int<->FP moves.
13032 So tie modes if they are either the same class, or vector modes with
13033 other vector modes, vector structs or any scalar mode.
13034 */
13036 bool
13038 {
13042 /* We specifically want to allow elements of "structure" modes to
13043 be tieable to the structure. This more general condition allows
13044 other rarer situations too. */
13048 /* Also allow any scalar modes with vectors. */
13054 }
13056 /* Return a new RTX holding the result of moving POINTER forward by
13057 AMOUNT bytes. */
13059 static rtx
13061 {
13066 }
13068 /* Return a new RTX holding the result of moving POINTER forward by the
13069 size of the mode it points to. */
13071 static rtx
13073 {
13077 }
13079 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13080 MODE bytes. */
13082 static void
13084 machine_mode mode)
13085 {
13088 /* "Cast" the pointers to the correct mode. */
13091 /* Emit the memcpy. */
13094 /* Move the pointers forward. */
13097 }
13099 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13100 we succeed, otherwise return false. */
13102 bool
13104 {
13108 rtx base;
13111 /* When optimizing for size, give a better estimate of the length of a
13112 memcpy call, but use the default otherwise. */
13115 /* We can't do anything smart if the amount to copy is not constant. */
13121 /* Try to keep the number of instructions low. For cases below 16 bytes we
13122 need to make at most two moves. For cases above 16 bytes it will be one
13123 move for each 16 byte chunk, then at most two additional moves. */
13133 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13134 1-byte chunk. */
13136 {
13138 {
13141 }
13147 }
13149 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13150 4-byte chunk, partially overlapping with the previously copied chunk. */
13152 {
13156 {
13162 }
13164 }
13166 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13167 them, then (if applicable) an 8-byte chunk. */
13169 {
13171 {
13174 }
13175 else
13176 {
13179 }
13180 }
13182 /* Finish the final bytes of the copy. We can always do this in one
13183 instruction. We either copy the exact amount we need, or partially
13184 overlap with the previous chunk we copied and copy 8-bytes. */
13193 else
13194 {
13196 {
13200 }
13201 else
13202 {
13208 }
13209 }
13212 }
13214 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
13215 SImode stores. Handle the case when the constant has identical
13216 bottom and top halves. This is beneficial when the two stores can be
13217 merged into an STP and we avoid synthesising potentially expensive
13218 immediates twice. Return true if such a split is possible. */
13220 bool
13222 {
13231 unsigned int orig_cost
13233 unsigned int lo_cost
13236 /* We want to transform:
13237 MOV x1, 49370
13238 MOVK x1, 0x140, lsl 16
13239 MOVK x1, 0xc0da, lsl 32
13240 MOVK x1, 0x140, lsl 48
13241 STR x1, [x0]
13242 into:
13243 MOV w1, 49370
13244 MOVK w1, 0x140, lsl 16
13245 STP w1, w1, [x0]
13246 So we want to perform this only when we save two instructions
13247 or more. When optimizing for size, however, accept any code size
13248 savings we can. */
13263 /* Don't emit an explicit store pair as this may not be always profitable.
13264 Let the sched-fusion logic decide whether to merge them. */
13269 }
13271 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
13273 static unsigned HOST_WIDE_INT
13275 {
13277 }
13279 static bool
13284 {
13285 /* STORE_BY_PIECES can be used when copying a constant string, but
13286 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
13287 For now we always fail this and let the move_by_pieces code copy
13288 the string from read-only memory. */
13293 }
13295 static rtx
13298 {
13302 insn_code icode;
13313 {
13341 }
13346 {
13349 }
13358 {
13361 }
13367 }
13369 static rtx
13372 {
13376 insn_code icode;
13388 {
13416 }
13421 {
13424 }
13432 {
13437 }
13448 {
13451 }
13457 }
13459 #undef TARGET_GEN_CCMP_FIRST
13460 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
13462 #undef TARGET_GEN_CCMP_NEXT
13463 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
13465 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
13466 instruction fusion of some sort. */
13468 static bool
13470 {
13472 }
13475 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
13476 should be kept together during scheduling. */
13478 static bool
13480 {
13481 rtx set_dest;
13484 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
13491 {
13492 /* We are trying to match:
13493 prev (mov) == (set (reg r0) (const_int imm16))
13494 curr (movk) == (set (zero_extract (reg r0)
13495 (const_int 16)
13496 (const_int 16))
13497 (const_int imm16_1)) */
13509 {
13511 }
13512 }
13515 {
13517 /* We're trying to match:
13518 prev (adrp) == (set (reg r1)
13519 (high (symbol_ref ("SYM"))))
13520 curr (add) == (set (reg r0)
13521 (lo_sum (reg r1)
13522 (symbol_ref ("SYM"))))
13523 Note that r0 need not necessarily be the same as r1, especially
13524 during pre-regalloc scheduling. */
13528 {
13536 }
13537 }
13540 {
13542 /* We're trying to match:
13543 prev (movk) == (set (zero_extract (reg r0)
13544 (const_int 16)
13545 (const_int 32))
13546 (const_int imm16_1))
13547 curr (movk) == (set (zero_extract (reg r0)
13548 (const_int 16)
13549 (const_int 48))
13550 (const_int imm16_2)) */
13566 }
13568 {
13569 /* We're trying to match:
13570 prev (adrp) == (set (reg r0)
13571 (high (symbol_ref ("SYM"))))
13572 curr (ldr) == (set (reg r1)
13573 (mem (lo_sum (reg r0)
13574 (symbol_ref ("SYM")))))
13575 or
13576 curr (ldr) == (set (reg r1)
13577 (zero_extend (mem
13578 (lo_sum (reg r0)
13579 (symbol_ref ("SYM")))))) */
13582 {
13595 }
13596 }
13604 {
13607 /* FIXME: this misses some which is considered simple arthematic
13608 instructions for ThunderX. Simple shifts are missed here. */
13614 }
13617 }
13619 /* Return true iff the instruction fusion described by OP is enabled. */
13621 bool
13623 {
13625 }
13627 /* If MEM is in the form of [base+offset], extract the two parts
13628 of address and set to BASE and OFFSET, otherwise return false
13629 after clearing BASE and OFFSET. */
13631 bool
13633 {
13634 rtx addr;
13641 {
13645 }
13649 {
13653 }
13659 }
13661 /* Types for scheduling fusion. */
13662 enum sched_fusion_type
13663 {
13665 SCHED_FUSION_LD_SIGN_EXTEND,
13666 SCHED_FUSION_LD_ZERO_EXTEND,
13667 SCHED_FUSION_LD,
13668 SCHED_FUSION_ST,
13669 SCHED_FUSION_NUM
13670 };
13672 /* If INSN is a load or store of address in the form of [base+offset],
13673 extract the two parts and set to BASE and OFFSET. Return scheduling
13674 fusion type this INSN is. */
13676 static enum sched_fusion_type
13678 {
13696 {
13701 }
13703 {
13708 }
13713 {
13716 }
13717 else
13724 }
13726 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
13728 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
13729 and PRI are only calculated for these instructions. For other instruction,
13730 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
13731 type instruction fusion can be added by returning different priorities.
13733 It's important that irrelevant instructions get the largest FUSION_PRI. */
13735 static void
13738 {
13748 {
13752 }
13754 /* Set FUSION_PRI according to fusion type and base register. */
13757 /* Calculate PRI. */
13760 /* INSN with smaller offset goes first. */
13764 else
13769 }
13771 /* Given OPERANDS of consecutive load/store, check if we can merge
13772 them into ldp/stp. LOAD is true if they are load instructions.
13773 MODE is the mode of memory operands. */
13775 bool
13778 {
13784 {
13792 }
13793 else
13794 {
13799 }
13801 /* The mems cannot be volatile. */
13805 /* If we have SImode and slow unaligned ldp,
13806 check the alignment to be at least 8 byte. */
13810 && !optimize_size
13814 /* Check if the addresses are in the form of [base+offset]. */
13822 /* Check if the bases are same. */
13829 /* Check if the offsets are consecutive. */
13833 /* Check if the addresses are clobbered by load. */
13835 {
13839 /* In increasing order, the last load can clobber the address. */
13842 }
13846 else
13851 else
13854 /* Check if the registers are of same class. */
13859 }
13861 /* Given OPERANDS of consecutive load/store, check if we can merge
13862 them into ldp/stp by adjusting the offset. LOAD is true if they
13863 are load instructions. MODE is the mode of memory operands.
13865 Given below consecutive stores:
13867 str w1, [xb, 0x100]
13868 str w1, [xb, 0x104]
13869 str w1, [xb, 0x108]
13870 str w1, [xb, 0x10c]
13872 Though the offsets are out of the range supported by stp, we can
13873 still pair them after adjusting the offset, like:
13875 add scratch, xb, 0x100
13876 stp w1, w1, [scratch]
13877 stp w1, w1, [scratch, 0x8]
13879 The peephole patterns detecting this opportunity should guarantee
13880 the scratch register is avaliable. */
13882 bool
13885 {
13892 {
13905 }
13906 else
13907 {
13916 }
13917 /* Skip if memory operand is by itslef valid for ldp/stp. */
13921 /* The mems cannot be volatile. */
13926 /* Check if the addresses are in the form of [base+offset]. */
13940 /* Check if the bases are same. */
13951 /* Check if the offsets are consecutive. */
13960 /* Check if the addresses are clobbered by load. */
13962 {
13968 /* In increasing order, the last load can clobber the address. */
13971 }
13973 /* If we have SImode and slow unaligned ldp,
13974 check the alignment to be at least 8 byte. */
13978 && !optimize_size
13984 else
13989 else
13994 else
13999 else
14002 /* Check if the registers are of same class. */
14007 }
14009 /* Given OPERANDS of consecutive load/store, this function pairs them
14010 into ldp/stp after adjusting the offset. It depends on the fact
14011 that addresses of load/store instructions are in increasing order.
14012 MODE is the mode of memory operands. CODE is the rtl operator
14013 which should be applied to all memory operands, it's SIGN_EXTEND,
14014 ZERO_EXTEND or UNKNOWN. */
14016 bool
14019 {
14025 {
14030 }
14031 else
14032 {
14038 }
14043 /* Adjust offset thus it can fit in ldp/stp instruction. */
14051 /* Further adjust to make sure all offsets are OK. */
14053 {
14056 }
14058 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14063 {
14066 }
14068 /* Create new memory references. */
14072 /* Check if the adjusted address is OK for ldp/stp. */
14091 {
14096 }
14098 {
14103 }
14106 {
14111 }
14112 else
14113 {
14118 }
14120 /* Emit adjusting instruction. */
14122 /* Emit ldp/stp instructions. */
14130 }
14132 /* Return 1 if pseudo register should be created and used to hold
14133 GOT address for PIC code. */
14135 bool
14137 {
14139 }
14141 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
14143 static int
14145 {
14147 {
14154 }
14157 }
14160 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
14161 return the log2 of that value. Otherwise return -1. */
14163 int
14165 {
14180 }
14182 /* If X is a vector of equal CONST_DOUBLE values and that value is
14183 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
14185 int
14187 {
14203 }
14205 /* Implement TARGET_PROMOTED_TYPE to promote __fp16 to float. */
14206 static tree
14208 {
14212 }
14214 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
14216 static bool
14218 optimization_type opt_type)
14219 {
14221 {
14227 }
14228 }
14230 #undef TARGET_ADDRESS_COST
14231 #define TARGET_ADDRESS_COST aarch64_address_cost
14233 /* This hook will determines whether unnamed bitfields affect the alignment
14234 of the containing structure. The hook returns true if the structure
14235 should inherit the alignment requirements of an unnamed bitfield's
14236 type. */
14237 #undef TARGET_ALIGN_ANON_BITFIELD
14238 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
14240 #undef TARGET_ASM_ALIGNED_DI_OP
14243 #undef TARGET_ASM_ALIGNED_HI_OP
14246 #undef TARGET_ASM_ALIGNED_SI_OP
14249 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14250 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
14251 hook_bool_const_tree_hwi_hwi_const_tree_true
14253 #undef TARGET_ASM_FILE_START
14254 #define TARGET_ASM_FILE_START aarch64_start_file
14256 #undef TARGET_ASM_OUTPUT_MI_THUNK
14257 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
14259 #undef TARGET_ASM_SELECT_RTX_SECTION
14260 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
14262 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
14263 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
14265 #undef TARGET_BUILD_BUILTIN_VA_LIST
14266 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
14268 #undef TARGET_CALLEE_COPIES
14269 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
14271 #undef TARGET_CAN_ELIMINATE
14272 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
14274 #undef TARGET_CAN_INLINE_P
14275 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
14277 #undef TARGET_CANNOT_FORCE_CONST_MEM
14278 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
14280 #undef TARGET_CASE_VALUES_THRESHOLD
14281 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
14283 #undef TARGET_CONDITIONAL_REGISTER_USAGE
14284 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
14286 /* Only the least significant bit is used for initialization guard
14287 variables. */
14288 #undef TARGET_CXX_GUARD_MASK_BIT
14289 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
14291 #undef TARGET_C_MODE_FOR_SUFFIX
14292 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
14294 #ifdef TARGET_BIG_ENDIAN_DEFAULT
14295 #undef TARGET_DEFAULT_TARGET_FLAGS
14296 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
14297 #endif
14299 #undef TARGET_CLASS_MAX_NREGS
14300 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
14302 #undef TARGET_BUILTIN_DECL
14303 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
14305 #undef TARGET_BUILTIN_RECIPROCAL
14306 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
14308 #undef TARGET_EXPAND_BUILTIN
14309 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
14311 #undef TARGET_EXPAND_BUILTIN_VA_START
14312 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
14314 #undef TARGET_FOLD_BUILTIN
14315 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
14317 #undef TARGET_FUNCTION_ARG
14318 #define TARGET_FUNCTION_ARG aarch64_function_arg
14320 #undef TARGET_FUNCTION_ARG_ADVANCE
14321 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
14323 #undef TARGET_FUNCTION_ARG_BOUNDARY
14324 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
14326 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14327 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
14329 #undef TARGET_FUNCTION_VALUE
14330 #define TARGET_FUNCTION_VALUE aarch64_function_value
14332 #undef TARGET_FUNCTION_VALUE_REGNO_P
14333 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
14335 #undef TARGET_FRAME_POINTER_REQUIRED
14336 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
14338 #undef TARGET_GIMPLE_FOLD_BUILTIN
14339 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
14341 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14342 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
14344 #undef TARGET_INIT_BUILTINS
14345 #define TARGET_INIT_BUILTINS aarch64_init_builtins
14347 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
14348 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
14349 aarch64_ira_change_pseudo_allocno_class
14351 #undef TARGET_LEGITIMATE_ADDRESS_P
14352 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
14354 #undef TARGET_LEGITIMATE_CONSTANT_P
14355 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
14357 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
14358 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
14359 aarch64_legitimize_address_displacement
14361 #undef TARGET_LIBGCC_CMP_RETURN_MODE
14362 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
14364 #undef TARGET_MANGLE_TYPE
14365 #define TARGET_MANGLE_TYPE aarch64_mangle_type
14367 #undef TARGET_MEMORY_MOVE_COST
14368 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
14370 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
14371 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
14373 #undef TARGET_MUST_PASS_IN_STACK
14374 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14376 /* This target hook should return true if accesses to volatile bitfields
14377 should use the narrowest mode possible. It should return false if these
14378 accesses should use the bitfield container type. */
14379 #undef TARGET_NARROW_VOLATILE_BITFIELD
14380 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
14382 #undef TARGET_OPTION_OVERRIDE
14383 #define TARGET_OPTION_OVERRIDE aarch64_override_options
14385 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
14386 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
14387 aarch64_override_options_after_change
14389 #undef TARGET_OPTION_SAVE
14390 #define TARGET_OPTION_SAVE aarch64_option_save
14392 #undef TARGET_OPTION_RESTORE
14393 #define TARGET_OPTION_RESTORE aarch64_option_restore
14395 #undef TARGET_OPTION_PRINT
14396 #define TARGET_OPTION_PRINT aarch64_option_print
14398 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
14399 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
14401 #undef TARGET_SET_CURRENT_FUNCTION
14402 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
14404 #undef TARGET_PASS_BY_REFERENCE
14405 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
14407 #undef TARGET_PREFERRED_RELOAD_CLASS
14408 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
14410 #undef TARGET_SCHED_REASSOCIATION_WIDTH
14411 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
14413 #undef TARGET_PROMOTED_TYPE
14414 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
14416 #undef TARGET_SECONDARY_RELOAD
14417 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
14419 #undef TARGET_SHIFT_TRUNCATION_MASK
14420 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
14422 #undef TARGET_SETUP_INCOMING_VARARGS
14423 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
14425 #undef TARGET_STRUCT_VALUE_RTX
14426 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
14428 #undef TARGET_REGISTER_MOVE_COST
14429 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
14431 #undef TARGET_RETURN_IN_MEMORY
14432 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
14434 #undef TARGET_RETURN_IN_MSB
14435 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
14437 #undef TARGET_RTX_COSTS
14438 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
14440 #undef TARGET_SCHED_ISSUE_RATE
14441 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
14443 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14444 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14445 aarch64_sched_first_cycle_multipass_dfa_lookahead
14447 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
14448 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
14449 aarch64_first_cycle_multipass_dfa_lookahead_guard
14451 #undef TARGET_TRAMPOLINE_INIT
14452 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
14454 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14455 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
14457 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14458 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
14460 #undef TARGET_ARRAY_MODE_SUPPORTED_P
14461 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
14463 #undef TARGET_VECTORIZE_ADD_STMT_COST
14464 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
14466 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
14467 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
14468 aarch64_builtin_vectorization_cost
14470 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
14471 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
14473 #undef TARGET_VECTORIZE_BUILTINS
14474 #define TARGET_VECTORIZE_BUILTINS
14476 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
14477 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
14478 aarch64_builtin_vectorized_function
14480 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
14481 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
14482 aarch64_autovectorize_vector_sizes
14484 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
14485 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
14486 aarch64_atomic_assign_expand_fenv
14488 /* Section anchor support. */
14490 #undef TARGET_MIN_ANCHOR_OFFSET
14491 #define TARGET_MIN_ANCHOR_OFFSET -256
14493 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
14494 byte offset; we can do much more for larger data types, but have no way
14495 to determine the size of the access. We assume accesses are aligned. */
14496 #undef TARGET_MAX_ANCHOR_OFFSET
14497 #define TARGET_MAX_ANCHOR_OFFSET 4095
14499 #undef TARGET_VECTOR_ALIGNMENT
14500 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
14502 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
14503 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
14504 aarch64_simd_vector_alignment_reachable
14506 /* vec_perm support. */
14508 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
14509 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
14510 aarch64_vectorize_vec_perm_const_ok
14512 #undef TARGET_INIT_LIBFUNCS
14513 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
14515 #undef TARGET_FIXED_CONDITION_CODE_REGS
14516 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
14518 #undef TARGET_FLAGS_REGNUM
14519 #define TARGET_FLAGS_REGNUM CC_REGNUM
14521 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
14522 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
14524 #undef TARGET_ASAN_SHADOW_OFFSET
14525 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
14527 #undef TARGET_LEGITIMIZE_ADDRESS
14528 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
14530 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
14531 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
14532 aarch64_use_by_pieces_infrastructure_p
14534 #undef TARGET_CAN_USE_DOLOOP_P
14535 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
14537 #undef TARGET_SCHED_MACRO_FUSION_P
14538 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
14540 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
14541 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
14543 #undef TARGET_SCHED_FUSION_PRIORITY
14544 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
14546 #undef TARGET_UNSPEC_MAY_TRAP_P
14547 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
14549 #undef TARGET_USE_PSEUDO_PIC_REG
14550 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
14552 #undef TARGET_PRINT_OPERAND
14553 #define TARGET_PRINT_OPERAND aarch64_print_operand
14555 #undef TARGET_PRINT_OPERAND_ADDRESS
14556 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
14558 #undef TARGET_OPTAB_SUPPORTED_P
14559 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
14561 #undef TARGET_OMIT_STRUCT_RETURN_REG
14562 #define TARGET_OMIT_STRUCT_RETURN_REG true