1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011, 2012 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 struct target_reload default_target_reload
;
87 struct target_reload
*this_target_reload
= &default_target_reload
;
90 #define spill_indirect_levels \
91 (this_target_reload->x_spill_indirect_levels)
93 /* During reload_as_needed, element N contains a REG rtx for the hard reg
94 into which reg N has been reloaded (perhaps for a previous insn). */
95 static rtx
*reg_last_reload_reg
;
97 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
98 for an output reload that stores into reg N. */
99 static regset_head reg_has_output_reload
;
101 /* Indicates which hard regs are reload-registers for an output reload
102 in the current insn. */
103 static HARD_REG_SET reg_is_output_reload
;
105 /* Widest width in which each pseudo reg is referred to (via subreg). */
106 static unsigned int *reg_max_ref_width
;
108 /* Vector to remember old contents of reg_renumber before spilling. */
109 static short *reg_old_renumber
;
111 /* During reload_as_needed, element N contains the last pseudo regno reloaded
112 into hard register N. If that pseudo reg occupied more than one register,
113 reg_reloaded_contents points to that pseudo for each spill register in
114 use; all of these must remain set for an inheritance to occur. */
115 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
117 /* During reload_as_needed, element N contains the insn for which
118 hard register N was last used. Its contents are significant only
119 when reg_reloaded_valid is set for this register. */
120 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
122 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
123 static HARD_REG_SET reg_reloaded_valid
;
124 /* Indicate if the register was dead at the end of the reload.
125 This is only valid if reg_reloaded_contents is set and valid. */
126 static HARD_REG_SET reg_reloaded_dead
;
128 /* Indicate whether the register's current value is one that is not
129 safe to retain across a call, even for registers that are normally
130 call-saved. This is only meaningful for members of reg_reloaded_valid. */
131 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
133 /* Number of spill-regs so far; number of valid elements of spill_regs. */
136 /* In parallel with spill_regs, contains REG rtx's for those regs.
137 Holds the last rtx used for any given reg, or 0 if it has never
138 been used for spilling yet. This rtx is reused, provided it has
140 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
142 /* In parallel with spill_regs, contains nonzero for a spill reg
143 that was stored after the last time it was used.
144 The precise value is the insn generated to do the store. */
145 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
147 /* This is the register that was stored with spill_reg_store. This is a
148 copy of reload_out / reload_out_reg when the value was stored; if
149 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
150 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
152 /* This table is the inverse mapping of spill_regs:
153 indexed by hard reg number,
154 it contains the position of that reg in spill_regs,
155 or -1 for something that is not in spill_regs.
157 ?!? This is no longer accurate. */
158 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
160 /* This reg set indicates registers that can't be used as spill registers for
161 the currently processed insn. These are the hard registers which are live
162 during the insn, but not allocated to pseudos, as well as fixed
164 static HARD_REG_SET bad_spill_regs
;
166 /* These are the hard registers that can't be used as spill register for any
167 insn. This includes registers used for user variables and registers that
168 we can't eliminate. A register that appears in this set also can't be used
169 to retry register allocation. */
170 static HARD_REG_SET bad_spill_regs_global
;
172 /* Describes order of use of registers for reloading
173 of spilled pseudo-registers. `n_spills' is the number of
174 elements that are actually valid; new ones are added at the end.
176 Both spill_regs and spill_reg_order are used on two occasions:
177 once during find_reload_regs, where they keep track of the spill registers
178 for a single insn, but also during reload_as_needed where they show all
179 the registers ever used by reload. For the latter case, the information
180 is calculated during finish_spills. */
181 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
183 /* This vector of reg sets indicates, for each pseudo, which hard registers
184 may not be used for retrying global allocation because the register was
185 formerly spilled from one of them. If we allowed reallocating a pseudo to
186 a register that it was already allocated to, reload might not
188 static HARD_REG_SET
*pseudo_previous_regs
;
190 /* This vector of reg sets indicates, for each pseudo, which hard
191 registers may not be used for retrying global allocation because they
192 are used as spill registers during one of the insns in which the
194 static HARD_REG_SET
*pseudo_forbidden_regs
;
196 /* All hard regs that have been used as spill registers for any insn are
197 marked in this set. */
198 static HARD_REG_SET used_spill_regs
;
200 /* Index of last register assigned as a spill register. We allocate in
201 a round-robin fashion. */
202 static int last_spill_reg
;
204 /* Record the stack slot for each spilled hard register. */
205 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
207 /* Width allocated so far for that stack slot. */
208 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
210 /* Record which pseudos needed to be spilled. */
211 static regset_head spilled_pseudos
;
213 /* Record which pseudos changed their allocation in finish_spills. */
214 static regset_head changed_allocation_pseudos
;
216 /* Used for communication between order_regs_for_reload and count_pseudo.
217 Used to avoid counting one pseudo twice. */
218 static regset_head pseudos_counted
;
220 /* First uid used by insns created by reload in this function.
221 Used in find_equiv_reg. */
222 int reload_first_uid
;
224 /* Flag set by local-alloc or global-alloc if anything is live in
225 a call-clobbered reg across calls. */
226 int caller_save_needed
;
228 /* Set to 1 while reload_as_needed is operating.
229 Required by some machines to handle any generated moves differently. */
230 int reload_in_progress
= 0;
232 /* This obstack is used for allocation of rtl during register elimination.
233 The allocated storage can be freed once find_reloads has processed the
235 static struct obstack reload_obstack
;
237 /* Points to the beginning of the reload_obstack. All insn_chain structures
238 are allocated first. */
239 static char *reload_startobj
;
241 /* The point after all insn_chain structures. Used to quickly deallocate
242 memory allocated in copy_reloads during calculate_needs_all_insns. */
243 static char *reload_firstobj
;
245 /* This points before all local rtl generated by register elimination.
246 Used to quickly free all memory after processing one insn. */
247 static char *reload_insn_firstobj
;
249 /* List of insn_chain instructions, one for every insn that reload needs to
251 struct insn_chain
*reload_insn_chain
;
253 /* TRUE if we potentially left dead insns in the insn stream and want to
254 run DCE immediately after reload, FALSE otherwise. */
255 static bool need_dce
;
257 /* List of all insns needing reloads. */
258 static struct insn_chain
*insns_need_reload
;
260 /* This structure is used to record information about register eliminations.
261 Each array entry describes one possible way of eliminating a register
262 in favor of another. If there is more than one way of eliminating a
263 particular register, the most preferred should be specified first. */
267 int from
; /* Register number to be eliminated. */
268 int to
; /* Register number used as replacement. */
269 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
270 int can_eliminate
; /* Nonzero if this elimination can be done. */
271 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
272 target hook in previous scan over insns
274 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
275 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
276 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
277 rtx from_rtx
; /* REG rtx for the register to be eliminated.
278 We cannot simply compare the number since
279 we might then spuriously replace a hard
280 register corresponding to a pseudo
281 assigned to the reg to be eliminated. */
282 rtx to_rtx
; /* REG rtx for the replacement. */
285 static struct elim_table
*reg_eliminate
= 0;
287 /* This is an intermediate structure to initialize the table. It has
288 exactly the members provided by ELIMINABLE_REGS. */
289 static const struct elim_table_1
293 } reg_eliminate_1
[] =
295 /* If a set of eliminable registers was specified, define the table from it.
296 Otherwise, default to the normal case of the frame pointer being
297 replaced by the stack pointer. */
299 #ifdef ELIMINABLE_REGS
302 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
305 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
307 /* Record the number of pending eliminations that have an offset not equal
308 to their initial offset. If nonzero, we use a new copy of each
309 replacement result in any insns encountered. */
310 int num_not_at_initial_offset
;
312 /* Count the number of registers that we may be able to eliminate. */
313 static int num_eliminable
;
314 /* And the number of registers that are equivalent to a constant that
315 can be eliminated to frame_pointer / arg_pointer + constant. */
316 static int num_eliminable_invariants
;
318 /* For each label, we record the offset of each elimination. If we reach
319 a label by more than one path and an offset differs, we cannot do the
320 elimination. This information is indexed by the difference of the
321 number of the label and the first label number. We can't offset the
322 pointer itself as this can cause problems on machines with segmented
323 memory. The first table is an array of flags that records whether we
324 have yet encountered a label and the second table is an array of arrays,
325 one entry in the latter array for each elimination. */
327 static int first_label_num
;
328 static char *offsets_known_at
;
329 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
331 VEC(reg_equivs_t
,gc
) *reg_equivs
;
333 /* Stack of addresses where an rtx has been changed. We can undo the
334 changes by popping items off the stack and restoring the original
335 value at each location.
337 We use this simplistic undo capability rather than copy_rtx as copy_rtx
338 will not make a deep copy of a normally sharable rtx, such as
339 (const (plus (symbol_ref) (const_int))). If such an expression appears
340 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
341 rtx expression would be changed. See PR 42431. */
345 DEF_VEC_ALLOC_P(rtx_p
,heap
);
346 static VEC(rtx_p
,heap
) *substitute_stack
;
348 /* Number of labels in the current function. */
350 static int num_labels
;
352 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
353 static void maybe_fix_stack_asms (void);
354 static void copy_reloads (struct insn_chain
*);
355 static void calculate_needs_all_insns (int);
356 static int find_reg (struct insn_chain
*, int);
357 static void find_reload_regs (struct insn_chain
*);
358 static void select_reload_regs (void);
359 static void delete_caller_save_insns (void);
361 static void spill_failure (rtx
, enum reg_class
);
362 static void count_spilled_pseudo (int, int, int);
363 static void delete_dead_insn (rtx
);
364 static void alter_reg (int, int, bool);
365 static void set_label_offsets (rtx
, rtx
, int);
366 static void check_eliminable_occurrences (rtx
);
367 static void elimination_effects (rtx
, enum machine_mode
);
368 static rtx
eliminate_regs_1 (rtx
, enum machine_mode
, rtx
, bool, bool);
369 static int eliminate_regs_in_insn (rtx
, int);
370 static void update_eliminable_offsets (void);
371 static void mark_not_eliminable (rtx
, const_rtx
, void *);
372 static void set_initial_elim_offsets (void);
373 static bool verify_initial_elim_offsets (void);
374 static void set_initial_label_offsets (void);
375 static void set_offsets_for_label (rtx
);
376 static void init_eliminable_invariants (rtx
, bool);
377 static void init_elim_table (void);
378 static void free_reg_equiv (void);
379 static void update_eliminables (HARD_REG_SET
*);
380 static void elimination_costs_in_insn (rtx
);
381 static void spill_hard_reg (unsigned int, int);
382 static int finish_spills (int);
383 static void scan_paradoxical_subregs (rtx
);
384 static void count_pseudo (int);
385 static void order_regs_for_reload (struct insn_chain
*);
386 static void reload_as_needed (int);
387 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
388 static void forget_marked_reloads (regset
);
389 static int reload_reg_class_lower (const void *, const void *);
390 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
392 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
394 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
395 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
397 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
399 static int allocate_reload_reg (struct insn_chain
*, int, int);
400 static int conflicts_with_override (rtx
);
401 static void failed_reload (rtx
, int);
402 static int set_reload_reg (int, int);
403 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
404 static void choose_reload_regs (struct insn_chain
*);
405 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
407 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
409 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
410 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
411 static void emit_reload_insns (struct insn_chain
*);
412 static void delete_output_reload (rtx
, int, int, rtx
);
413 static void delete_address_reloads (rtx
, rtx
);
414 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
415 static void inc_for_reload (rtx
, rtx
, rtx
, int);
417 static void add_auto_inc_notes (rtx
, rtx
);
419 static void substitute (rtx
*, const_rtx
, rtx
);
420 static bool gen_reload_chain_without_interm_reg_p (int, int);
421 static int reloads_conflict (int, int);
422 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
423 static rtx
emit_insn_if_valid_for_reload (rtx
);
425 /* Initialize the reload pass. This is called at the beginning of compilation
426 and may be called again if the target is reinitialized. */
433 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
434 Set spill_indirect_levels to the number of levels such addressing is
435 permitted, zero if it is not permitted at all. */
438 = gen_rtx_MEM (Pmode
,
441 LAST_VIRTUAL_REGISTER
+ 1),
443 spill_indirect_levels
= 0;
445 while (memory_address_p (QImode
, tem
))
447 spill_indirect_levels
++;
448 tem
= gen_rtx_MEM (Pmode
, tem
);
451 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
453 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
454 indirect_symref_ok
= memory_address_p (QImode
, tem
);
456 /* See if reg+reg is a valid (and offsettable) address. */
458 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
460 tem
= gen_rtx_PLUS (Pmode
,
461 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
462 gen_rtx_REG (Pmode
, i
));
464 /* This way, we make sure that reg+reg is an offsettable address. */
465 tem
= plus_constant (tem
, 4);
467 if (memory_address_p (QImode
, tem
))
469 double_reg_address_ok
= 1;
474 /* Initialize obstack for our rtl allocation. */
475 gcc_obstack_init (&reload_obstack
);
476 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
478 INIT_REG_SET (&spilled_pseudos
);
479 INIT_REG_SET (&changed_allocation_pseudos
);
480 INIT_REG_SET (&pseudos_counted
);
483 /* List of insn chains that are currently unused. */
484 static struct insn_chain
*unused_insn_chains
= 0;
486 /* Allocate an empty insn_chain structure. */
488 new_insn_chain (void)
490 struct insn_chain
*c
;
492 if (unused_insn_chains
== 0)
494 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
495 INIT_REG_SET (&c
->live_throughout
);
496 INIT_REG_SET (&c
->dead_or_set
);
500 c
= unused_insn_chains
;
501 unused_insn_chains
= c
->next
;
503 c
->is_caller_save_insn
= 0;
504 c
->need_operand_change
= 0;
510 /* Small utility function to set all regs in hard reg set TO which are
511 allocated to pseudos in regset FROM. */
514 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
517 reg_set_iterator rsi
;
519 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
521 int r
= reg_renumber
[regno
];
525 /* reload_combine uses the information from DF_LIVE_IN,
526 which might still contain registers that have not
527 actually been allocated since they have an
529 gcc_assert (ira_conflicts_p
|| reload_completed
);
532 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
536 /* Replace all pseudos found in LOC with their corresponding
540 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
553 unsigned int regno
= REGNO (x
);
555 if (regno
< FIRST_PSEUDO_REGISTER
)
558 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
562 replace_pseudos_in (loc
, mem_mode
, usage
);
566 if (reg_equiv_constant (regno
))
567 *loc
= reg_equiv_constant (regno
);
568 else if (reg_equiv_invariant (regno
))
569 *loc
= reg_equiv_invariant (regno
);
570 else if (reg_equiv_mem (regno
))
571 *loc
= reg_equiv_mem (regno
);
572 else if (reg_equiv_address (regno
))
573 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
576 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
577 || REGNO (regno_reg_rtx
[regno
]) != regno
);
578 *loc
= regno_reg_rtx
[regno
];
583 else if (code
== MEM
)
585 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
589 /* Process each of our operands recursively. */
590 fmt
= GET_RTX_FORMAT (code
);
591 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
593 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
594 else if (*fmt
== 'E')
595 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
596 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
599 /* Determine if the current function has an exception receiver block
600 that reaches the exit block via non-exceptional edges */
603 has_nonexceptional_receiver (void)
607 basic_block
*tos
, *worklist
, bb
;
609 /* If we're not optimizing, then just err on the safe side. */
613 /* First determine which blocks can reach exit via normal paths. */
614 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks
+ 1);
617 bb
->flags
&= ~BB_REACHABLE
;
619 /* Place the exit block on our worklist. */
620 EXIT_BLOCK_PTR
->flags
|= BB_REACHABLE
;
621 *tos
++ = EXIT_BLOCK_PTR
;
623 /* Iterate: find everything reachable from what we've already seen. */
624 while (tos
!= worklist
)
628 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
629 if (!(e
->flags
& EDGE_ABNORMAL
))
631 basic_block src
= e
->src
;
633 if (!(src
->flags
& BB_REACHABLE
))
635 src
->flags
|= BB_REACHABLE
;
642 /* Now see if there's a reachable block with an exceptional incoming
645 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
648 /* No exceptional block reached exit unexceptionally. */
652 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
653 zero elements) to MAX_REG_NUM elements.
655 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
657 grow_reg_equivs (void)
659 int old_size
= VEC_length (reg_equivs_t
, reg_equivs
);
660 int max_regno
= max_reg_num ();
663 VEC_reserve (reg_equivs_t
, gc
, reg_equivs
, max_regno
);
664 for (i
= old_size
; i
< max_regno
; i
++)
666 VEC_quick_insert (reg_equivs_t
, reg_equivs
, i
, 0);
667 memset (VEC_index (reg_equivs_t
, reg_equivs
, i
), 0, sizeof (reg_equivs_t
));
673 /* Global variables used by reload and its subroutines. */
675 /* The current basic block while in calculate_elim_costs_all_insns. */
676 static basic_block elim_bb
;
678 /* Set during calculate_needs if an insn needs register elimination. */
679 static int something_needs_elimination
;
680 /* Set during calculate_needs if an insn needs an operand changed. */
681 static int something_needs_operands_changed
;
682 /* Set by alter_regs if we spilled a register to the stack. */
683 static bool something_was_spilled
;
685 /* Nonzero means we couldn't get enough spill regs. */
688 /* Temporary array of pseudo-register number. */
689 static int *temp_pseudo_reg_arr
;
691 /* Main entry point for the reload pass.
693 FIRST is the first insn of the function being compiled.
695 GLOBAL nonzero means we were called from global_alloc
696 and should attempt to reallocate any pseudoregs that we
697 displace from hard regs we will use for reloads.
698 If GLOBAL is zero, we do not have enough information to do that,
699 so any pseudo reg that is spilled must go to the stack.
701 Return value is TRUE if reload likely left dead insns in the
702 stream and a DCE pass should be run to elimiante them. Else the
703 return value is FALSE. */
706 reload (rtx first
, int global
)
710 struct elim_table
*ep
;
714 /* Make sure even insns with volatile mem refs are recognizable. */
719 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
721 /* Make sure that the last insn in the chain
722 is not something that needs reloading. */
723 emit_note (NOTE_INSN_DELETED
);
725 /* Enable find_equiv_reg to distinguish insns made by reload. */
726 reload_first_uid
= get_max_uid ();
728 #ifdef SECONDARY_MEMORY_NEEDED
729 /* Initialize the secondary memory table. */
730 clear_secondary_mem ();
733 /* We don't have a stack slot for any spill reg yet. */
734 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
735 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
737 /* Initialize the save area information for caller-save, in case some
741 /* Compute which hard registers are now in use
742 as homes for pseudo registers.
743 This is done here rather than (eg) in global_alloc
744 because this point is reached even if not optimizing. */
745 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
748 /* A function that has a nonlocal label that can reach the exit
749 block via non-exceptional paths must save all call-saved
751 if (cfun
->has_nonlocal_label
752 && has_nonexceptional_receiver ())
753 crtl
->saves_all_registers
= 1;
755 if (crtl
->saves_all_registers
)
756 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
757 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
758 df_set_regs_ever_live (i
, true);
760 /* Find all the pseudo registers that didn't get hard regs
761 but do have known equivalent constants or memory slots.
762 These include parameters (known equivalent to parameter slots)
763 and cse'd or loop-moved constant memory addresses.
765 Record constant equivalents in reg_equiv_constant
766 so they will be substituted by find_reloads.
767 Record memory equivalents in reg_mem_equiv so they can
768 be substituted eventually by altering the REG-rtx's. */
771 reg_old_renumber
= XCNEWVEC (short, max_regno
);
772 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
773 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
774 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
776 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
778 init_eliminable_invariants (first
, true);
781 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
782 stack slots to the pseudos that lack hard regs or equivalents.
783 Do not touch virtual registers. */
785 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
786 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
787 temp_pseudo_reg_arr
[n
++] = i
;
790 /* Ask IRA to order pseudo-registers for better stack slot
792 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
794 for (i
= 0; i
< n
; i
++)
795 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
797 /* If we have some registers we think can be eliminated, scan all insns to
798 see if there is an insn that sets one of these registers to something
799 other than itself plus a constant. If so, the register cannot be
800 eliminated. Doing this scan here eliminates an extra pass through the
801 main reload loop in the most common case where register elimination
803 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
805 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
807 maybe_fix_stack_asms ();
809 insns_need_reload
= 0;
810 something_needs_elimination
= 0;
812 /* Initialize to -1, which means take the first spill register. */
815 /* Spill any hard regs that we know we can't eliminate. */
816 CLEAR_HARD_REG_SET (used_spill_regs
);
817 /* There can be multiple ways to eliminate a register;
818 they should be listed adjacently.
819 Elimination for any register fails only if all possible ways fail. */
820 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
823 int can_eliminate
= 0;
826 can_eliminate
|= ep
->can_eliminate
;
829 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
831 spill_hard_reg (from
, 1);
834 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
835 if (frame_pointer_needed
)
836 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
838 finish_spills (global
);
840 /* From now on, we may need to generate moves differently. We may also
841 allow modifications of insns which cause them to not be recognized.
842 Any such modifications will be cleaned up during reload itself. */
843 reload_in_progress
= 1;
845 /* This loop scans the entire function each go-round
846 and repeats until one repetition spills no additional hard regs. */
849 int something_changed
;
851 HOST_WIDE_INT starting_frame_size
;
853 starting_frame_size
= get_frame_size ();
854 something_was_spilled
= false;
856 set_initial_elim_offsets ();
857 set_initial_label_offsets ();
859 /* For each pseudo register that has an equivalent location defined,
860 try to eliminate any eliminable registers (such as the frame pointer)
861 assuming initial offsets for the replacement register, which
864 If the resulting location is directly addressable, substitute
865 the MEM we just got directly for the old REG.
867 If it is not addressable but is a constant or the sum of a hard reg
868 and constant, it is probably not addressable because the constant is
869 out of range, in that case record the address; we will generate
870 hairy code to compute the address in a register each time it is
871 needed. Similarly if it is a hard register, but one that is not
872 valid as an address register.
874 If the location is not addressable, but does not have one of the
875 above forms, assign a stack slot. We have to do this to avoid the
876 potential of producing lots of reloads if, e.g., a location involves
877 a pseudo that didn't get a hard register and has an equivalent memory
878 location that also involves a pseudo that didn't get a hard register.
880 Perhaps at some point we will improve reload_when_needed handling
881 so this problem goes away. But that's very hairy. */
883 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
884 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
886 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
889 if (strict_memory_address_addr_space_p
890 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
892 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
893 else if (CONSTANT_P (XEXP (x
, 0))
894 || (REG_P (XEXP (x
, 0))
895 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
896 || (GET_CODE (XEXP (x
, 0)) == PLUS
897 && REG_P (XEXP (XEXP (x
, 0), 0))
898 && (REGNO (XEXP (XEXP (x
, 0), 0))
899 < FIRST_PSEUDO_REGISTER
)
900 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
901 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
904 /* Make a new stack slot. Then indicate that something
905 changed so we go back and recompute offsets for
906 eliminable registers because the allocation of memory
907 below might change some offset. reg_equiv_{mem,address}
908 will be set up for this pseudo on the next pass around
910 reg_equiv_memory_loc (i
) = 0;
911 reg_equiv_init (i
) = 0;
912 alter_reg (i
, -1, true);
916 if (caller_save_needed
)
919 /* If we allocated another stack slot, redo elimination bookkeeping. */
920 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
922 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
924 /* If we have a stack frame, we must align it now. The
925 stack size may be a part of the offset computation for
926 register elimination. So if this changes the stack size,
927 then repeat the elimination bookkeeping. We don't
928 realign when there is no stack, as that will cause a
929 stack frame when none is needed should
930 STARTING_FRAME_OFFSET not be already aligned to
932 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
933 if (starting_frame_size
!= get_frame_size ())
937 if (caller_save_needed
)
939 save_call_clobbered_regs ();
940 /* That might have allocated new insn_chain structures. */
941 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
944 calculate_needs_all_insns (global
);
946 if (! ira_conflicts_p
)
947 /* Don't do it for IRA. We need this info because we don't
948 change live_throughout and dead_or_set for chains when IRA
950 CLEAR_REG_SET (&spilled_pseudos
);
954 something_changed
= 0;
956 /* If we allocated any new memory locations, make another pass
957 since it might have changed elimination offsets. */
958 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
959 something_changed
= 1;
961 /* Even if the frame size remained the same, we might still have
962 changed elimination offsets, e.g. if find_reloads called
963 force_const_mem requiring the back end to allocate a constant
964 pool base register that needs to be saved on the stack. */
965 else if (!verify_initial_elim_offsets ())
966 something_changed
= 1;
969 HARD_REG_SET to_spill
;
970 CLEAR_HARD_REG_SET (to_spill
);
971 update_eliminables (&to_spill
);
972 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
974 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
975 if (TEST_HARD_REG_BIT (to_spill
, i
))
977 spill_hard_reg (i
, 1);
980 /* Regardless of the state of spills, if we previously had
981 a register that we thought we could eliminate, but now can
982 not eliminate, we must run another pass.
984 Consider pseudos which have an entry in reg_equiv_* which
985 reference an eliminable register. We must make another pass
986 to update reg_equiv_* so that we do not substitute in the
987 old value from when we thought the elimination could be
989 something_changed
= 1;
993 select_reload_regs ();
997 if (insns_need_reload
!= 0 || did_spill
)
998 something_changed
|= finish_spills (global
);
1000 if (! something_changed
)
1003 if (caller_save_needed
)
1004 delete_caller_save_insns ();
1006 obstack_free (&reload_obstack
, reload_firstobj
);
1009 /* If global-alloc was run, notify it of any register eliminations we have
1012 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1013 if (ep
->can_eliminate
)
1014 mark_elimination (ep
->from
, ep
->to
);
1016 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1017 If that insn didn't set the register (i.e., it copied the register to
1018 memory), just delete that insn instead of the equivalencing insn plus
1019 anything now dead. If we call delete_dead_insn on that insn, we may
1020 delete the insn that actually sets the register if the register dies
1021 there and that is incorrect. */
1023 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1025 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
1028 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
1030 rtx equiv_insn
= XEXP (list
, 0);
1032 /* If we already deleted the insn or if it may trap, we can't
1033 delete it. The latter case shouldn't happen, but can
1034 if an insn has a variable address, gets a REG_EH_REGION
1035 note added to it, and then gets converted into a load
1036 from a constant address. */
1037 if (NOTE_P (equiv_insn
)
1038 || can_throw_internal (equiv_insn
))
1040 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1041 delete_dead_insn (equiv_insn
);
1043 SET_INSN_DELETED (equiv_insn
);
1048 /* Use the reload registers where necessary
1049 by generating move instructions to move the must-be-register
1050 values into or out of the reload registers. */
1052 if (insns_need_reload
!= 0 || something_needs_elimination
1053 || something_needs_operands_changed
)
1055 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1057 reload_as_needed (global
);
1059 gcc_assert (old_frame_size
== get_frame_size ());
1061 gcc_assert (verify_initial_elim_offsets ());
1064 /* If we were able to eliminate the frame pointer, show that it is no
1065 longer live at the start of any basic block. If it ls live by
1066 virtue of being in a pseudo, that pseudo will be marked live
1067 and hence the frame pointer will be known to be live via that
1070 if (! frame_pointer_needed
)
1072 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1074 /* Come here (with failure set nonzero) if we can't get enough spill
1078 CLEAR_REG_SET (&changed_allocation_pseudos
);
1079 CLEAR_REG_SET (&spilled_pseudos
);
1080 reload_in_progress
= 0;
1082 /* Now eliminate all pseudo regs by modifying them into
1083 their equivalent memory references.
1084 The REG-rtx's for the pseudos are modified in place,
1085 so all insns that used to refer to them now refer to memory.
1087 For a reg that has a reg_equiv_address, all those insns
1088 were changed by reloading so that no insns refer to it any longer;
1089 but the DECL_RTL of a variable decl may refer to it,
1090 and if so this causes the debugging info to mention the variable. */
1092 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1096 if (reg_equiv_mem (i
))
1097 addr
= XEXP (reg_equiv_mem (i
), 0);
1099 if (reg_equiv_address (i
))
1100 addr
= reg_equiv_address (i
);
1104 if (reg_renumber
[i
] < 0)
1106 rtx reg
= regno_reg_rtx
[i
];
1108 REG_USERVAR_P (reg
) = 0;
1109 PUT_CODE (reg
, MEM
);
1110 XEXP (reg
, 0) = addr
;
1111 if (reg_equiv_memory_loc (i
))
1112 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1114 MEM_ATTRS (reg
) = 0;
1115 MEM_NOTRAP_P (reg
) = 1;
1117 else if (reg_equiv_mem (i
))
1118 XEXP (reg_equiv_mem (i
), 0) = addr
;
1121 /* We don't want complex addressing modes in debug insns
1122 if simpler ones will do, so delegitimize equivalences
1124 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1126 rtx reg
= regno_reg_rtx
[i
];
1130 if (reg_equiv_constant (i
))
1131 equiv
= reg_equiv_constant (i
);
1132 else if (reg_equiv_invariant (i
))
1133 equiv
= reg_equiv_invariant (i
);
1134 else if (reg
&& MEM_P (reg
))
1135 equiv
= targetm
.delegitimize_address (reg
);
1136 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1142 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1144 insn
= DF_REF_INSN (use
);
1146 /* Make sure the next ref is for a different instruction,
1147 so that we're not affected by the rescan. */
1148 next
= DF_REF_NEXT_REG (use
);
1149 while (next
&& DF_REF_INSN (next
) == insn
)
1150 next
= DF_REF_NEXT_REG (next
);
1152 if (DEBUG_INSN_P (insn
))
1156 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1157 df_insn_rescan_debug_internal (insn
);
1160 INSN_VAR_LOCATION_LOC (insn
)
1161 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1168 /* We must set reload_completed now since the cleanup_subreg_operands call
1169 below will re-recognize each insn and reload may have generated insns
1170 which are only valid during and after reload. */
1171 reload_completed
= 1;
1173 /* Make a pass over all the insns and delete all USEs which we inserted
1174 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1175 notes. Delete all CLOBBER insns, except those that refer to the return
1176 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1177 from misarranging variable-array code, and simplify (subreg (reg))
1178 operands. Strip and regenerate REG_INC notes that may have been moved
1181 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1187 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1188 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1190 if ((GET_CODE (PATTERN (insn
)) == USE
1191 /* We mark with QImode USEs introduced by reload itself. */
1192 && (GET_MODE (insn
) == QImode
1193 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1194 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1195 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1196 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1197 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1198 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1199 != stack_pointer_rtx
))
1200 && (!REG_P (XEXP (PATTERN (insn
), 0))
1201 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1207 /* Some CLOBBERs may survive until here and still reference unassigned
1208 pseudos with const equivalent, which may in turn cause ICE in later
1209 passes if the reference remains in place. */
1210 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1211 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1212 VOIDmode
, PATTERN (insn
));
1214 /* Discard obvious no-ops, even without -O. This optimization
1215 is fast and doesn't interfere with debugging. */
1216 if (NONJUMP_INSN_P (insn
)
1217 && GET_CODE (PATTERN (insn
)) == SET
1218 && REG_P (SET_SRC (PATTERN (insn
)))
1219 && REG_P (SET_DEST (PATTERN (insn
)))
1220 && (REGNO (SET_SRC (PATTERN (insn
)))
1221 == REGNO (SET_DEST (PATTERN (insn
)))))
1227 pnote
= ®_NOTES (insn
);
1230 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1231 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1232 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1233 *pnote
= XEXP (*pnote
, 1);
1235 pnote
= &XEXP (*pnote
, 1);
1239 add_auto_inc_notes (insn
, PATTERN (insn
));
1242 /* Simplify (subreg (reg)) if it appears as an operand. */
1243 cleanup_subreg_operands (insn
);
1245 /* Clean up invalid ASMs so that they don't confuse later passes.
1247 if (asm_noperands (PATTERN (insn
)) >= 0)
1249 extract_insn (insn
);
1250 if (!constrain_operands (1))
1252 error_for_asm (insn
,
1253 "%<asm%> operand has impossible constraints");
1260 /* If we are doing generic stack checking, give a warning if this
1261 function's frame size is larger than we expect. */
1262 if (flag_stack_check
== GENERIC_STACK_CHECK
)
1264 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1265 static int verbose_warned
= 0;
1267 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1268 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1269 size
+= UNITS_PER_WORD
;
1271 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1273 warning (0, "frame size too large for reliable stack checking");
1274 if (! verbose_warned
)
1276 warning (0, "try reducing the number of local variables");
1282 free (temp_pseudo_reg_arr
);
1284 /* Indicate that we no longer have known memory locations or constants. */
1287 free (reg_max_ref_width
);
1288 free (reg_old_renumber
);
1289 free (pseudo_previous_regs
);
1290 free (pseudo_forbidden_regs
);
1292 CLEAR_HARD_REG_SET (used_spill_regs
);
1293 for (i
= 0; i
< n_spills
; i
++)
1294 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1296 /* Free all the insn_chain structures at once. */
1297 obstack_free (&reload_obstack
, reload_startobj
);
1298 unused_insn_chains
= 0;
1300 inserted
= fixup_abnormal_edges ();
1302 /* We've possibly turned single trapping insn into multiple ones. */
1303 if (cfun
->can_throw_non_call_exceptions
)
1306 blocks
= sbitmap_alloc (last_basic_block
);
1307 sbitmap_ones (blocks
);
1308 find_many_sub_basic_blocks (blocks
);
1309 sbitmap_free (blocks
);
1313 commit_edge_insertions ();
1315 /* Replacing pseudos with their memory equivalents might have
1316 created shared rtx. Subsequent passes would get confused
1317 by this, so unshare everything here. */
1318 unshare_all_rtl_again (first
);
1320 #ifdef STACK_BOUNDARY
1321 /* init_emit has set the alignment of the hard frame pointer
1322 to STACK_BOUNDARY. It is very likely no longer valid if
1323 the hard frame pointer was used for register allocation. */
1324 if (!frame_pointer_needed
)
1325 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1328 VEC_free (rtx_p
, heap
, substitute_stack
);
1330 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1332 reload_completed
= !failure
;
1337 /* Yet another special case. Unfortunately, reg-stack forces people to
1338 write incorrect clobbers in asm statements. These clobbers must not
1339 cause the register to appear in bad_spill_regs, otherwise we'll call
1340 fatal_insn later. We clear the corresponding regnos in the live
1341 register sets to avoid this.
1342 The whole thing is rather sick, I'm afraid. */
1345 maybe_fix_stack_asms (void)
1348 const char *constraints
[MAX_RECOG_OPERANDS
];
1349 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1350 struct insn_chain
*chain
;
1352 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1355 HARD_REG_SET clobbered
, allowed
;
1358 if (! INSN_P (chain
->insn
)
1359 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1361 pat
= PATTERN (chain
->insn
);
1362 if (GET_CODE (pat
) != PARALLEL
)
1365 CLEAR_HARD_REG_SET (clobbered
);
1366 CLEAR_HARD_REG_SET (allowed
);
1368 /* First, make a mask of all stack regs that are clobbered. */
1369 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1371 rtx t
= XVECEXP (pat
, 0, i
);
1372 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1373 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1376 /* Get the operand values and constraints out of the insn. */
1377 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1378 constraints
, operand_mode
, NULL
);
1380 /* For every operand, see what registers are allowed. */
1381 for (i
= 0; i
< noperands
; i
++)
1383 const char *p
= constraints
[i
];
1384 /* For every alternative, we compute the class of registers allowed
1385 for reloading in CLS, and merge its contents into the reg set
1387 int cls
= (int) NO_REGS
;
1393 if (c
== '\0' || c
== ',' || c
== '#')
1395 /* End of one alternative - mark the regs in the current
1396 class, and reset the class. */
1397 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1403 } while (c
!= '\0' && c
!= ',');
1411 case '=': case '+': case '*': case '%': case '?': case '!':
1412 case '0': case '1': case '2': case '3': case '4': case '<':
1413 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1414 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1415 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1416 case TARGET_MEM_CONSTRAINT
:
1420 cls
= (int) reg_class_subunion
[cls
]
1421 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1427 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1431 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1432 cls
= (int) reg_class_subunion
[cls
]
1433 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1436 cls
= (int) reg_class_subunion
[cls
]
1437 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1439 p
+= CONSTRAINT_LEN (c
, p
);
1442 /* Those of the registers which are clobbered, but allowed by the
1443 constraints, must be usable as reload registers. So clear them
1444 out of the life information. */
1445 AND_HARD_REG_SET (allowed
, clobbered
);
1446 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1447 if (TEST_HARD_REG_BIT (allowed
, i
))
1449 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1450 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1457 /* Copy the global variables n_reloads and rld into the corresponding elts
1460 copy_reloads (struct insn_chain
*chain
)
1462 chain
->n_reloads
= n_reloads
;
1463 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1464 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1465 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1468 /* Walk the chain of insns, and determine for each whether it needs reloads
1469 and/or eliminations. Build the corresponding insns_need_reload list, and
1470 set something_needs_elimination as appropriate. */
1472 calculate_needs_all_insns (int global
)
1474 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1475 struct insn_chain
*chain
, *next
= 0;
1477 something_needs_elimination
= 0;
1479 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1480 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1482 rtx insn
= chain
->insn
;
1486 /* Clear out the shortcuts. */
1487 chain
->n_reloads
= 0;
1488 chain
->need_elim
= 0;
1489 chain
->need_reload
= 0;
1490 chain
->need_operand_change
= 0;
1492 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1493 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1494 what effects this has on the known offsets at labels. */
1496 if (LABEL_P (insn
) || JUMP_P (insn
)
1497 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1498 set_label_offsets (insn
, insn
, 0);
1502 rtx old_body
= PATTERN (insn
);
1503 int old_code
= INSN_CODE (insn
);
1504 rtx old_notes
= REG_NOTES (insn
);
1505 int did_elimination
= 0;
1506 int operands_changed
= 0;
1507 rtx set
= single_set (insn
);
1509 /* Skip insns that only set an equivalence. */
1510 if (set
&& REG_P (SET_DEST (set
))
1511 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1512 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1513 || (reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1514 && reg_equiv_init (REGNO (SET_DEST (set
))))
1517 /* If needed, eliminate any eliminable registers. */
1518 if (num_eliminable
|| num_eliminable_invariants
)
1519 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1521 /* Analyze the instruction. */
1522 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1523 global
, spill_reg_order
);
1525 /* If a no-op set needs more than one reload, this is likely
1526 to be something that needs input address reloads. We
1527 can't get rid of this cleanly later, and it is of no use
1528 anyway, so discard it now.
1529 We only do this when expensive_optimizations is enabled,
1530 since this complements reload inheritance / output
1531 reload deletion, and it can make debugging harder. */
1532 if (flag_expensive_optimizations
&& n_reloads
> 1)
1534 rtx set
= single_set (insn
);
1537 ((SET_SRC (set
) == SET_DEST (set
)
1538 && REG_P (SET_SRC (set
))
1539 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1540 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1541 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1542 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1543 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1544 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1545 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1546 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1548 if (ira_conflicts_p
)
1549 /* Inform IRA about the insn deletion. */
1550 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1551 REGNO (SET_SRC (set
)));
1553 /* Delete it from the reload chain. */
1555 chain
->prev
->next
= next
;
1557 reload_insn_chain
= next
;
1559 next
->prev
= chain
->prev
;
1560 chain
->next
= unused_insn_chains
;
1561 unused_insn_chains
= chain
;
1566 update_eliminable_offsets ();
1568 /* Remember for later shortcuts which insns had any reloads or
1569 register eliminations. */
1570 chain
->need_elim
= did_elimination
;
1571 chain
->need_reload
= n_reloads
> 0;
1572 chain
->need_operand_change
= operands_changed
;
1574 /* Discard any register replacements done. */
1575 if (did_elimination
)
1577 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1578 PATTERN (insn
) = old_body
;
1579 INSN_CODE (insn
) = old_code
;
1580 REG_NOTES (insn
) = old_notes
;
1581 something_needs_elimination
= 1;
1584 something_needs_operands_changed
|= operands_changed
;
1588 copy_reloads (chain
);
1589 *pprev_reload
= chain
;
1590 pprev_reload
= &chain
->next_need_reload
;
1597 /* This function is called from the register allocator to set up estimates
1598 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1599 an invariant. The structure is similar to calculate_needs_all_insns. */
1602 calculate_elim_costs_all_insns (void)
1604 int *reg_equiv_init_cost
;
1608 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1610 init_eliminable_invariants (get_insns (), false);
1612 set_initial_elim_offsets ();
1613 set_initial_label_offsets ();
1620 FOR_BB_INSNS (bb
, insn
)
1622 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1623 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1624 what effects this has on the known offsets at labels. */
1626 if (LABEL_P (insn
) || JUMP_P (insn
)
1627 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1628 set_label_offsets (insn
, insn
, 0);
1632 rtx set
= single_set (insn
);
1634 /* Skip insns that only set an equivalence. */
1635 if (set
&& REG_P (SET_DEST (set
))
1636 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1637 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1638 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1640 unsigned regno
= REGNO (SET_DEST (set
));
1641 rtx init
= reg_equiv_init (regno
);
1644 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1646 int cost
= set_src_cost (t
, optimize_bb_for_speed_p (bb
));
1647 int freq
= REG_FREQ_FROM_BB (bb
);
1649 reg_equiv_init_cost
[regno
] = cost
* freq
;
1653 /* If needed, eliminate any eliminable registers. */
1654 if (num_eliminable
|| num_eliminable_invariants
)
1655 elimination_costs_in_insn (insn
);
1658 update_eliminable_offsets ();
1662 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1664 if (reg_equiv_invariant (i
))
1666 if (reg_equiv_init (i
))
1668 int cost
= reg_equiv_init_cost
[i
];
1671 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1673 ira_adjust_equiv_reg_cost (i
, cost
);
1679 "Reg %d had equivalence, but can't be eliminated\n",
1681 ira_adjust_equiv_reg_cost (i
, 0);
1686 free (reg_equiv_init_cost
);
1687 free (offsets_known_at
);
1690 offsets_known_at
= NULL
;
1693 /* Comparison function for qsort to decide which of two reloads
1694 should be handled first. *P1 and *P2 are the reload numbers. */
1697 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1699 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1702 /* Consider required reloads before optional ones. */
1703 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1707 /* Count all solitary classes before non-solitary ones. */
1708 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1709 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1713 /* Aside from solitaires, consider all multi-reg groups first. */
1714 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1718 /* Consider reloads in order of increasing reg-class number. */
1719 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1723 /* If reloads are equally urgent, sort by reload number,
1724 so that the results of qsort leave nothing to chance. */
1728 /* The cost of spilling each hard reg. */
1729 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1731 /* When spilling multiple hard registers, we use SPILL_COST for the first
1732 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1733 only the first hard reg for a multi-reg pseudo. */
1734 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1736 /* Map of hard regno to pseudo regno currently occupying the hard
1738 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1740 /* Update the spill cost arrays, considering that pseudo REG is live. */
1743 count_pseudo (int reg
)
1745 int freq
= REG_FREQ (reg
);
1746 int r
= reg_renumber
[reg
];
1749 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1750 if (ira_conflicts_p
&& r
< 0)
1753 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1754 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1757 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1759 gcc_assert (r
>= 0);
1761 spill_add_cost
[r
] += freq
;
1762 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1765 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1766 spill_cost
[r
+ nregs
] += freq
;
1770 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1771 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1774 order_regs_for_reload (struct insn_chain
*chain
)
1777 HARD_REG_SET used_by_pseudos
;
1778 HARD_REG_SET used_by_pseudos2
;
1779 reg_set_iterator rsi
;
1781 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1783 memset (spill_cost
, 0, sizeof spill_cost
);
1784 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1785 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1786 hard_regno_to_pseudo_regno
[i
] = -1;
1788 /* Count number of uses of each hard reg by pseudo regs allocated to it
1789 and then order them by decreasing use. First exclude hard registers
1790 that are live in or across this insn. */
1792 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1793 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1794 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1795 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1797 /* Now find out which pseudos are allocated to it, and update
1799 CLEAR_REG_SET (&pseudos_counted
);
1801 EXECUTE_IF_SET_IN_REG_SET
1802 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1806 EXECUTE_IF_SET_IN_REG_SET
1807 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1811 CLEAR_REG_SET (&pseudos_counted
);
1814 /* Vector of reload-numbers showing the order in which the reloads should
1816 static short reload_order
[MAX_RELOADS
];
1818 /* This is used to keep track of the spill regs used in one insn. */
1819 static HARD_REG_SET used_spill_regs_local
;
1821 /* We decided to spill hard register SPILLED, which has a size of
1822 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1823 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1824 update SPILL_COST/SPILL_ADD_COST. */
1827 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1829 int freq
= REG_FREQ (reg
);
1830 int r
= reg_renumber
[reg
];
1833 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1834 if (ira_conflicts_p
&& r
< 0)
1837 gcc_assert (r
>= 0);
1839 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1841 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1842 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1845 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1847 spill_add_cost
[r
] -= freq
;
1850 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1851 spill_cost
[r
+ nregs
] -= freq
;
1855 /* Find reload register to use for reload number ORDER. */
1858 find_reg (struct insn_chain
*chain
, int order
)
1860 int rnum
= reload_order
[order
];
1861 struct reload
*rl
= rld
+ rnum
;
1862 int best_cost
= INT_MAX
;
1864 unsigned int i
, j
, n
;
1866 HARD_REG_SET not_usable
;
1867 HARD_REG_SET used_by_other_reload
;
1868 reg_set_iterator rsi
;
1869 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1870 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1872 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1873 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1874 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1876 CLEAR_HARD_REG_SET (used_by_other_reload
);
1877 for (k
= 0; k
< order
; k
++)
1879 int other
= reload_order
[k
];
1881 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1882 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1883 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1886 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1888 #ifdef REG_ALLOC_ORDER
1889 unsigned int regno
= reg_alloc_order
[i
];
1891 unsigned int regno
= i
;
1894 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1895 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1896 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1898 int this_cost
= spill_cost
[regno
];
1900 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1902 for (j
= 1; j
< this_nregs
; j
++)
1904 this_cost
+= spill_add_cost
[regno
+ j
];
1905 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1906 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1912 if (ira_conflicts_p
)
1914 /* Ask IRA to find a better pseudo-register for
1916 for (n
= j
= 0; j
< this_nregs
; j
++)
1918 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1922 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1923 regno_pseudo_regs
[n
++] = r
;
1925 regno_pseudo_regs
[n
++] = -1;
1927 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1928 best_regno_pseudo_regs
,
1935 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1936 if (regno_pseudo_regs
[j
] < 0)
1943 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1945 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1947 if (this_cost
< best_cost
1948 /* Among registers with equal cost, prefer caller-saved ones, or
1949 use REG_ALLOC_ORDER if it is defined. */
1950 || (this_cost
== best_cost
1951 #ifdef REG_ALLOC_ORDER
1952 && (inv_reg_alloc_order
[regno
]
1953 < inv_reg_alloc_order
[best_reg
])
1955 && call_used_regs
[regno
]
1956 && ! call_used_regs
[best_reg
]
1961 best_cost
= this_cost
;
1969 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1971 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1972 rl
->regno
= best_reg
;
1974 EXECUTE_IF_SET_IN_REG_SET
1975 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1977 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1980 EXECUTE_IF_SET_IN_REG_SET
1981 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1983 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1986 for (i
= 0; i
< rl
->nregs
; i
++)
1988 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1989 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1990 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1991 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1996 /* Find more reload regs to satisfy the remaining need of an insn, which
1998 Do it by ascending class number, since otherwise a reg
1999 might be spilled for a big class and might fail to count
2000 for a smaller class even though it belongs to that class. */
2003 find_reload_regs (struct insn_chain
*chain
)
2007 /* In order to be certain of getting the registers we need,
2008 we must sort the reloads into order of increasing register class.
2009 Then our grabbing of reload registers will parallel the process
2010 that provided the reload registers. */
2011 for (i
= 0; i
< chain
->n_reloads
; i
++)
2013 /* Show whether this reload already has a hard reg. */
2014 if (chain
->rld
[i
].reg_rtx
)
2016 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
2017 chain
->rld
[i
].regno
= regno
;
2019 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
2022 chain
->rld
[i
].regno
= -1;
2023 reload_order
[i
] = i
;
2026 n_reloads
= chain
->n_reloads
;
2027 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
2029 CLEAR_HARD_REG_SET (used_spill_regs_local
);
2032 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2034 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2036 /* Compute the order of preference for hard registers to spill. */
2038 order_regs_for_reload (chain
);
2040 for (i
= 0; i
< n_reloads
; i
++)
2042 int r
= reload_order
[i
];
2044 /* Ignore reloads that got marked inoperative. */
2045 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2046 && ! rld
[r
].optional
2047 && rld
[r
].regno
== -1)
2048 if (! find_reg (chain
, i
))
2051 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2052 spill_failure (chain
->insn
, rld
[r
].rclass
);
2058 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2059 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2061 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2065 select_reload_regs (void)
2067 struct insn_chain
*chain
;
2069 /* Try to satisfy the needs for each insn. */
2070 for (chain
= insns_need_reload
; chain
!= 0;
2071 chain
= chain
->next_need_reload
)
2072 find_reload_regs (chain
);
2075 /* Delete all insns that were inserted by emit_caller_save_insns during
2078 delete_caller_save_insns (void)
2080 struct insn_chain
*c
= reload_insn_chain
;
2084 while (c
!= 0 && c
->is_caller_save_insn
)
2086 struct insn_chain
*next
= c
->next
;
2089 if (c
== reload_insn_chain
)
2090 reload_insn_chain
= next
;
2094 next
->prev
= c
->prev
;
2096 c
->prev
->next
= next
;
2097 c
->next
= unused_insn_chains
;
2098 unused_insn_chains
= c
;
2106 /* Handle the failure to find a register to spill.
2107 INSN should be one of the insns which needed this particular spill reg. */
2110 spill_failure (rtx insn
, enum reg_class rclass
)
2112 if (asm_noperands (PATTERN (insn
)) >= 0)
2113 error_for_asm (insn
, "can%'t find a register in class %qs while "
2114 "reloading %<asm%>",
2115 reg_class_names
[rclass
]);
2118 error ("unable to find a register to spill in class %qs",
2119 reg_class_names
[rclass
]);
2123 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2124 debug_reload_to_stream (dump_file
);
2126 fatal_insn ("this is the insn:", insn
);
2130 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2131 data that is dead in INSN. */
2134 delete_dead_insn (rtx insn
)
2136 rtx prev
= prev_active_insn (insn
);
2139 /* If the previous insn sets a register that dies in our insn make
2140 a note that we want to run DCE immediately after reload.
2142 We used to delete the previous insn & recurse, but that's wrong for
2143 block local equivalences. Instead of trying to figure out the exact
2144 circumstances where we can delete the potentially dead insns, just
2145 let DCE do the job. */
2146 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2147 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2148 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2149 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2150 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2153 SET_INSN_DELETED (insn
);
2156 /* Modify the home of pseudo-reg I.
2157 The new home is present in reg_renumber[I].
2159 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2160 or it may be -1, meaning there is none or it is not relevant.
2161 This is used so that all pseudos spilled from a given hard reg
2162 can share one stack slot. */
2165 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2167 /* When outputting an inline function, this can happen
2168 for a reg that isn't actually used. */
2169 if (regno_reg_rtx
[i
] == 0)
2172 /* If the reg got changed to a MEM at rtl-generation time,
2174 if (!REG_P (regno_reg_rtx
[i
]))
2177 /* Modify the reg-rtx to contain the new hard reg
2178 number or else to contain its pseudo reg number. */
2179 SET_REGNO (regno_reg_rtx
[i
],
2180 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2182 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2183 allocate a stack slot for it. */
2185 if (reg_renumber
[i
] < 0
2186 && REG_N_REFS (i
) > 0
2187 && reg_equiv_constant (i
) == 0
2188 && (reg_equiv_invariant (i
) == 0
2189 || reg_equiv_init (i
) == 0)
2190 && reg_equiv_memory_loc (i
) == 0)
2193 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2194 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2195 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2196 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2197 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2200 something_was_spilled
= true;
2202 if (ira_conflicts_p
)
2204 /* Mark the spill for IRA. */
2205 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2207 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2213 /* Each pseudo reg has an inherent size which comes from its own mode,
2214 and a total size which provides room for paradoxical subregs
2215 which refer to the pseudo reg in wider modes.
2217 We can use a slot already allocated if it provides both
2218 enough inherent space and enough total space.
2219 Otherwise, we allocate a new slot, making sure that it has no less
2220 inherent space, and no less total space, then the previous slot. */
2221 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2225 /* No known place to spill from => no slot to reuse. */
2226 x
= assign_stack_local (mode
, total_size
,
2227 min_align
> inherent_align
2228 || total_size
> inherent_size
? -1 : 0);
2232 /* Cancel the big-endian correction done in assign_stack_local.
2233 Get the address of the beginning of the slot. This is so we
2234 can do a big-endian correction unconditionally below. */
2235 if (BYTES_BIG_ENDIAN
)
2237 adjust
= inherent_size
- total_size
;
2240 = adjust_address_nv (x
, mode_for_size (total_size
2246 if (! dont_share_p
&& ira_conflicts_p
)
2247 /* Inform IRA about allocation a new stack slot. */
2248 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2251 /* Reuse a stack slot if possible. */
2252 else if (spill_stack_slot
[from_reg
] != 0
2253 && spill_stack_slot_width
[from_reg
] >= total_size
2254 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2256 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2257 x
= spill_stack_slot
[from_reg
];
2259 /* Allocate a bigger slot. */
2262 /* Compute maximum size needed, both for inherent size
2263 and for total size. */
2266 if (spill_stack_slot
[from_reg
])
2268 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2270 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2271 if (spill_stack_slot_width
[from_reg
] > total_size
)
2272 total_size
= spill_stack_slot_width
[from_reg
];
2273 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2274 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2277 /* Make a slot with that size. */
2278 x
= assign_stack_local (mode
, total_size
,
2279 min_align
> inherent_align
2280 || total_size
> inherent_size
? -1 : 0);
2283 /* Cancel the big-endian correction done in assign_stack_local.
2284 Get the address of the beginning of the slot. This is so we
2285 can do a big-endian correction unconditionally below. */
2286 if (BYTES_BIG_ENDIAN
)
2288 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2291 = adjust_address_nv (x
, mode_for_size (total_size
2297 spill_stack_slot
[from_reg
] = stack_slot
;
2298 spill_stack_slot_width
[from_reg
] = total_size
;
2301 /* On a big endian machine, the "address" of the slot
2302 is the address of the low part that fits its inherent mode. */
2303 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2304 adjust
+= (total_size
- inherent_size
);
2306 /* If we have any adjustment to make, or if the stack slot is the
2307 wrong mode, make a new stack slot. */
2308 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2310 /* Set all of the memory attributes as appropriate for a spill. */
2311 set_mem_attrs_for_spill (x
);
2313 /* Save the stack slot for later. */
2314 reg_equiv_memory_loc (i
) = x
;
2318 /* Mark the slots in regs_ever_live for the hard regs used by
2319 pseudo-reg number REGNO, accessed in MODE. */
2322 mark_home_live_1 (int regno
, enum machine_mode mode
)
2326 i
= reg_renumber
[regno
];
2329 lim
= end_hard_regno (mode
, i
);
2331 df_set_regs_ever_live(i
++, true);
2334 /* Mark the slots in regs_ever_live for the hard regs
2335 used by pseudo-reg number REGNO. */
2338 mark_home_live (int regno
)
2340 if (reg_renumber
[regno
] >= 0)
2341 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2344 /* This function handles the tracking of elimination offsets around branches.
2346 X is a piece of RTL being scanned.
2348 INSN is the insn that it came from, if any.
2350 INITIAL_P is nonzero if we are to set the offset to be the initial
2351 offset and zero if we are setting the offset of the label to be the
2355 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2357 enum rtx_code code
= GET_CODE (x
);
2360 struct elim_table
*p
;
2365 if (LABEL_REF_NONLOCAL_P (x
))
2370 /* ... fall through ... */
2373 /* If we know nothing about this label, set the desired offsets. Note
2374 that this sets the offset at a label to be the offset before a label
2375 if we don't know anything about the label. This is not correct for
2376 the label after a BARRIER, but is the best guess we can make. If
2377 we guessed wrong, we will suppress an elimination that might have
2378 been possible had we been able to guess correctly. */
2380 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2382 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2383 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2384 = (initial_p
? reg_eliminate
[i
].initial_offset
2385 : reg_eliminate
[i
].offset
);
2386 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2389 /* Otherwise, if this is the definition of a label and it is
2390 preceded by a BARRIER, set our offsets to the known offset of
2394 && (tem
= prev_nonnote_insn (insn
)) != 0
2396 set_offsets_for_label (insn
);
2398 /* If neither of the above cases is true, compare each offset
2399 with those previously recorded and suppress any eliminations
2400 where the offsets disagree. */
2402 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2403 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2404 != (initial_p
? reg_eliminate
[i
].initial_offset
2405 : reg_eliminate
[i
].offset
))
2406 reg_eliminate
[i
].can_eliminate
= 0;
2411 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2413 /* ... fall through ... */
2417 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2418 to indirectly and hence must have all eliminations at their
2420 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2421 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2422 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2428 /* Each of the labels in the parallel or address vector must be
2429 at their initial offsets. We want the first field for PARALLEL
2430 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2432 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2433 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2438 /* We only care about setting PC. If the source is not RETURN,
2439 IF_THEN_ELSE, or a label, disable any eliminations not at
2440 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2441 isn't one of those possibilities. For branches to a label,
2442 call ourselves recursively.
2444 Note that this can disable elimination unnecessarily when we have
2445 a non-local goto since it will look like a non-constant jump to
2446 someplace in the current function. This isn't a significant
2447 problem since such jumps will normally be when all elimination
2448 pairs are back to their initial offsets. */
2450 if (SET_DEST (x
) != pc_rtx
)
2453 switch (GET_CODE (SET_SRC (x
)))
2460 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2464 tem
= XEXP (SET_SRC (x
), 1);
2465 if (GET_CODE (tem
) == LABEL_REF
)
2466 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2467 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2470 tem
= XEXP (SET_SRC (x
), 2);
2471 if (GET_CODE (tem
) == LABEL_REF
)
2472 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2473 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2481 /* If we reach here, all eliminations must be at their initial
2482 offset because we are doing a jump to a variable address. */
2483 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2484 if (p
->offset
!= p
->initial_offset
)
2485 p
->can_eliminate
= 0;
2493 /* Called through for_each_rtx, this function examines every reg that occurs
2494 in PX and adjusts the costs for its elimination which are gathered by IRA.
2495 DATA is the insn in which PX occurs. We do not recurse into MEM
2499 note_reg_elim_costly (rtx
*px
, void *data
)
2501 rtx insn
= (rtx
)data
;
2508 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2509 && reg_equiv_init (REGNO (x
))
2510 && reg_equiv_invariant (REGNO (x
)))
2512 rtx t
= reg_equiv_invariant (REGNO (x
));
2513 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2514 int cost
= set_src_cost (new_rtx
, optimize_bb_for_speed_p (elim_bb
));
2515 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2518 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2523 /* Scan X and replace any eliminable registers (such as fp) with a
2524 replacement (such as sp), plus an offset.
2526 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2527 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2528 MEM, we are allowed to replace a sum of a register and the constant zero
2529 with the register, which we cannot do outside a MEM. In addition, we need
2530 to record the fact that a register is referenced outside a MEM.
2532 If INSN is an insn, it is the insn containing X. If we replace a REG
2533 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2534 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2535 the REG is being modified.
2537 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2538 That's used when we eliminate in expressions stored in notes.
2539 This means, do not set ref_outside_mem even if the reference
2542 If FOR_COSTS is true, we are being called before reload in order to
2543 estimate the costs of keeping registers with an equivalence unallocated.
2545 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2546 replacements done assuming all offsets are at their initial values. If
2547 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2548 encounter, return the actual location so that find_reloads will do
2549 the proper thing. */
2552 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2553 bool may_use_invariant
, bool for_costs
)
2555 enum rtx_code code
= GET_CODE (x
);
2556 struct elim_table
*ep
;
2563 if (! current_function_decl
)
2586 /* First handle the case where we encounter a bare register that
2587 is eliminable. Replace it with a PLUS. */
2588 if (regno
< FIRST_PSEUDO_REGISTER
)
2590 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2592 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2593 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2596 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2598 && reg_equiv_invariant (regno
))
2600 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2601 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2602 mem_mode
, insn
, true, for_costs
);
2603 /* There exists at least one use of REGNO that cannot be
2604 eliminated. Prevent the defining insn from being deleted. */
2605 reg_equiv_init (regno
) = NULL_RTX
;
2607 alter_reg (regno
, -1, true);
2611 /* You might think handling MINUS in a manner similar to PLUS is a
2612 good idea. It is not. It has been tried multiple times and every
2613 time the change has had to have been reverted.
2615 Other parts of reload know a PLUS is special (gen_reload for example)
2616 and require special code to handle code a reloaded PLUS operand.
2618 Also consider backends where the flags register is clobbered by a
2619 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2620 lea instruction comes to mind). If we try to reload a MINUS, we
2621 may kill the flags register that was holding a useful value.
2623 So, please before trying to handle MINUS, consider reload as a
2624 whole instead of this little section as well as the backend issues. */
2626 /* If this is the sum of an eliminable register and a constant, rework
2628 if (REG_P (XEXP (x
, 0))
2629 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2630 && CONSTANT_P (XEXP (x
, 1)))
2632 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2634 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2636 /* The only time we want to replace a PLUS with a REG (this
2637 occurs when the constant operand of the PLUS is the negative
2638 of the offset) is when we are inside a MEM. We won't want
2639 to do so at other times because that would change the
2640 structure of the insn in a way that reload can't handle.
2641 We special-case the commonest situation in
2642 eliminate_regs_in_insn, so just replace a PLUS with a
2643 PLUS here, unless inside a MEM. */
2644 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2645 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2648 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2649 plus_constant (XEXP (x
, 1),
2650 ep
->previous_offset
));
2653 /* If the register is not eliminable, we are done since the other
2654 operand is a constant. */
2658 /* If this is part of an address, we want to bring any constant to the
2659 outermost PLUS. We will do this by doing register replacement in
2660 our operands and seeing if a constant shows up in one of them.
2662 Note that there is no risk of modifying the structure of the insn,
2663 since we only get called for its operands, thus we are either
2664 modifying the address inside a MEM, or something like an address
2665 operand of a load-address insn. */
2668 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2670 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2673 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2675 /* If one side is a PLUS and the other side is a pseudo that
2676 didn't get a hard register but has a reg_equiv_constant,
2677 we must replace the constant here since it may no longer
2678 be in the position of any operand. */
2679 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2680 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2681 && reg_renumber
[REGNO (new1
)] < 0
2683 && reg_equiv_constant (REGNO (new1
)) != 0)
2684 new1
= reg_equiv_constant (REGNO (new1
));
2685 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2686 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2687 && reg_renumber
[REGNO (new0
)] < 0
2688 && reg_equiv_constant (REGNO (new0
)) != 0)
2689 new0
= reg_equiv_constant (REGNO (new0
));
2691 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2693 /* As above, if we are not inside a MEM we do not want to
2694 turn a PLUS into something else. We might try to do so here
2695 for an addition of 0 if we aren't optimizing. */
2696 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2697 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2705 /* If this is the product of an eliminable register and a
2706 constant, apply the distribute law and move the constant out
2707 so that we have (plus (mult ..) ..). This is needed in order
2708 to keep load-address insns valid. This case is pathological.
2709 We ignore the possibility of overflow here. */
2710 if (REG_P (XEXP (x
, 0))
2711 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2712 && CONST_INT_P (XEXP (x
, 1)))
2713 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2715 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2718 /* Refs inside notes or in DEBUG_INSNs don't count for
2720 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2721 || GET_CODE (insn
) == INSN_LIST
2722 || DEBUG_INSN_P (insn
))))
2723 ep
->ref_outside_mem
= 1;
2726 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2727 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2730 /* ... fall through ... */
2734 /* See comments before PLUS about handling MINUS. */
2736 case DIV
: case UDIV
:
2737 case MOD
: case UMOD
:
2738 case AND
: case IOR
: case XOR
:
2739 case ROTATERT
: case ROTATE
:
2740 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2742 case GE
: case GT
: case GEU
: case GTU
:
2743 case LE
: case LT
: case LEU
: case LTU
:
2745 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2747 rtx new1
= XEXP (x
, 1)
2748 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2751 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2752 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2757 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2760 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2762 if (new_rtx
!= XEXP (x
, 0))
2764 /* If this is a REG_DEAD note, it is not valid anymore.
2765 Using the eliminated version could result in creating a
2766 REG_DEAD note for the stack or frame pointer. */
2767 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2769 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2773 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2777 /* ... fall through ... */
2780 /* Now do eliminations in the rest of the chain. If this was
2781 an EXPR_LIST, this might result in allocating more memory than is
2782 strictly needed, but it simplifies the code. */
2785 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2787 if (new_rtx
!= XEXP (x
, 1))
2789 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2797 /* We do not support elimination of a register that is modified.
2798 elimination_effects has already make sure that this does not
2804 /* We do not support elimination of a register that is modified.
2805 elimination_effects has already make sure that this does not
2806 happen. The only remaining case we need to consider here is
2807 that the increment value may be an eliminable register. */
2808 if (GET_CODE (XEXP (x
, 1)) == PLUS
2809 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2811 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2812 insn
, true, for_costs
);
2814 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2815 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2816 gen_rtx_PLUS (GET_MODE (x
),
2817 XEXP (x
, 0), new_rtx
));
2821 case STRICT_LOW_PART
:
2823 case SIGN_EXTEND
: case ZERO_EXTEND
:
2824 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2825 case FLOAT
: case FIX
:
2826 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2835 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2837 if (new_rtx
!= XEXP (x
, 0))
2838 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2842 /* Similar to above processing, but preserve SUBREG_BYTE.
2843 Convert (subreg (mem)) to (mem) if not paradoxical.
2844 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2845 pseudo didn't get a hard reg, we must replace this with the
2846 eliminated version of the memory location because push_reload
2847 may do the replacement in certain circumstances. */
2848 if (REG_P (SUBREG_REG (x
))
2849 && !paradoxical_subreg_p (x
)
2851 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2853 new_rtx
= SUBREG_REG (x
);
2856 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2858 if (new_rtx
!= SUBREG_REG (x
))
2860 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2861 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2864 && ((x_size
< new_size
2865 #ifdef WORD_REGISTER_OPERATIONS
2866 /* On these machines, combine can create rtl of the form
2867 (set (subreg:m1 (reg:m2 R) 0) ...)
2868 where m1 < m2, and expects something interesting to
2869 happen to the entire word. Moreover, it will use the
2870 (reg:m2 R) later, expecting all bits to be preserved.
2871 So if the number of words is the same, preserve the
2872 subreg so that push_reload can see it. */
2873 && ! ((x_size
- 1) / UNITS_PER_WORD
2874 == (new_size
-1 ) / UNITS_PER_WORD
)
2877 || x_size
== new_size
)
2879 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2881 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2887 /* Our only special processing is to pass the mode of the MEM to our
2888 recursive call and copy the flags. While we are here, handle this
2889 case more efficiently. */
2891 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2894 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2895 && !memory_address_p (GET_MODE (x
), new_rtx
))
2896 for_each_rtx (&XEXP (x
, 0), note_reg_elim_costly
, insn
);
2898 return replace_equiv_address_nv (x
, new_rtx
);
2901 /* Handle insn_list USE that a call to a pure function may generate. */
2902 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2904 if (new_rtx
!= XEXP (x
, 0))
2905 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2910 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2920 /* Process each of our operands recursively. If any have changed, make a
2922 fmt
= GET_RTX_FORMAT (code
);
2923 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2927 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2929 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2931 x
= shallow_copy_rtx (x
);
2934 XEXP (x
, i
) = new_rtx
;
2936 else if (*fmt
== 'E')
2939 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2941 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2943 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2945 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2949 x
= shallow_copy_rtx (x
);
2952 XVEC (x
, i
) = new_v
;
2955 XVECEXP (x
, i
, j
) = new_rtx
;
2964 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2966 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2969 /* Scan rtx X for modifications of elimination target registers. Update
2970 the table of eliminables to reflect the changed state. MEM_MODE is
2971 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2974 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2976 enum rtx_code code
= GET_CODE (x
);
2977 struct elim_table
*ep
;
3002 /* First handle the case where we encounter a bare register that
3003 is eliminable. Replace it with a PLUS. */
3004 if (regno
< FIRST_PSEUDO_REGISTER
)
3006 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3008 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
3011 ep
->ref_outside_mem
= 1;
3016 else if (reg_renumber
[regno
] < 0
3018 && reg_equiv_constant (regno
)
3019 && ! function_invariant_p (reg_equiv_constant (regno
)))
3020 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3029 /* If we modify the source of an elimination rule, disable it. */
3030 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3031 if (ep
->from_rtx
== XEXP (x
, 0))
3032 ep
->can_eliminate
= 0;
3034 /* If we modify the target of an elimination rule by adding a constant,
3035 update its offset. If we modify the target in any other way, we'll
3036 have to disable the rule as well. */
3037 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3038 if (ep
->to_rtx
== XEXP (x
, 0))
3040 int size
= GET_MODE_SIZE (mem_mode
);
3042 /* If more bytes than MEM_MODE are pushed, account for them. */
3043 #ifdef PUSH_ROUNDING
3044 if (ep
->to_rtx
== stack_pointer_rtx
)
3045 size
= PUSH_ROUNDING (size
);
3047 if (code
== PRE_DEC
|| code
== POST_DEC
)
3049 else if (code
== PRE_INC
|| code
== POST_INC
)
3051 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3053 if (GET_CODE (XEXP (x
, 1)) == PLUS
3054 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3055 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3056 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3058 ep
->can_eliminate
= 0;
3062 /* These two aren't unary operators. */
3063 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3066 /* Fall through to generic unary operation case. */
3067 case STRICT_LOW_PART
:
3069 case SIGN_EXTEND
: case ZERO_EXTEND
:
3070 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3071 case FLOAT
: case FIX
:
3072 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3081 elimination_effects (XEXP (x
, 0), mem_mode
);
3085 if (REG_P (SUBREG_REG (x
))
3086 && (GET_MODE_SIZE (GET_MODE (x
))
3087 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3089 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3092 elimination_effects (SUBREG_REG (x
), mem_mode
);
3096 /* If using a register that is the source of an eliminate we still
3097 think can be performed, note it cannot be performed since we don't
3098 know how this register is used. */
3099 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3100 if (ep
->from_rtx
== XEXP (x
, 0))
3101 ep
->can_eliminate
= 0;
3103 elimination_effects (XEXP (x
, 0), mem_mode
);
3107 /* If clobbering a register that is the replacement register for an
3108 elimination we still think can be performed, note that it cannot
3109 be performed. Otherwise, we need not be concerned about it. */
3110 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3111 if (ep
->to_rtx
== XEXP (x
, 0))
3112 ep
->can_eliminate
= 0;
3114 elimination_effects (XEXP (x
, 0), mem_mode
);
3118 /* Check for setting a register that we know about. */
3119 if (REG_P (SET_DEST (x
)))
3121 /* See if this is setting the replacement register for an
3124 If DEST is the hard frame pointer, we do nothing because we
3125 assume that all assignments to the frame pointer are for
3126 non-local gotos and are being done at a time when they are valid
3127 and do not disturb anything else. Some machines want to
3128 eliminate a fake argument pointer (or even a fake frame pointer)
3129 with either the real frame or the stack pointer. Assignments to
3130 the hard frame pointer must not prevent this elimination. */
3132 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3134 if (ep
->to_rtx
== SET_DEST (x
)
3135 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3137 /* If it is being incremented, adjust the offset. Otherwise,
3138 this elimination can't be done. */
3139 rtx src
= SET_SRC (x
);
3141 if (GET_CODE (src
) == PLUS
3142 && XEXP (src
, 0) == SET_DEST (x
)
3143 && CONST_INT_P (XEXP (src
, 1)))
3144 ep
->offset
-= INTVAL (XEXP (src
, 1));
3146 ep
->can_eliminate
= 0;
3150 elimination_effects (SET_DEST (x
), VOIDmode
);
3151 elimination_effects (SET_SRC (x
), VOIDmode
);
3155 /* Our only special processing is to pass the mode of the MEM to our
3157 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3164 fmt
= GET_RTX_FORMAT (code
);
3165 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3168 elimination_effects (XEXP (x
, i
), mem_mode
);
3169 else if (*fmt
== 'E')
3170 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3171 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3175 /* Descend through rtx X and verify that no references to eliminable registers
3176 remain. If any do remain, mark the involved register as not
3180 check_eliminable_occurrences (rtx x
)
3189 code
= GET_CODE (x
);
3191 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3193 struct elim_table
*ep
;
3195 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3196 if (ep
->from_rtx
== x
)
3197 ep
->can_eliminate
= 0;
3201 fmt
= GET_RTX_FORMAT (code
);
3202 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3205 check_eliminable_occurrences (XEXP (x
, i
));
3206 else if (*fmt
== 'E')
3209 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3210 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3215 /* Scan INSN and eliminate all eliminable registers in it.
3217 If REPLACE is nonzero, do the replacement destructively. Also
3218 delete the insn as dead it if it is setting an eliminable register.
3220 If REPLACE is zero, do all our allocations in reload_obstack.
3222 If no eliminations were done and this insn doesn't require any elimination
3223 processing (these are not identical conditions: it might be updating sp,
3224 but not referencing fp; this needs to be seen during reload_as_needed so
3225 that the offset between fp and sp can be taken into consideration), zero
3226 is returned. Otherwise, 1 is returned. */
3229 eliminate_regs_in_insn (rtx insn
, int replace
)
3231 int icode
= recog_memoized (insn
);
3232 rtx old_body
= PATTERN (insn
);
3233 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3234 rtx old_set
= single_set (insn
);
3238 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3239 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3240 struct elim_table
*ep
;
3241 rtx plus_src
, plus_cst_src
;
3243 if (! insn_is_asm
&& icode
< 0)
3245 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
3246 || GET_CODE (PATTERN (insn
)) == CLOBBER
3247 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
3248 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3249 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
3250 || DEBUG_INSN_P (insn
));
3251 if (DEBUG_INSN_P (insn
))
3252 INSN_VAR_LOCATION_LOC (insn
)
3253 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3257 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3258 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3260 /* Check for setting an eliminable register. */
3261 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3262 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3264 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3265 /* If this is setting the frame pointer register to the
3266 hardware frame pointer register and this is an elimination
3267 that will be done (tested above), this insn is really
3268 adjusting the frame pointer downward to compensate for
3269 the adjustment done before a nonlocal goto. */
3270 if (ep
->from
== FRAME_POINTER_REGNUM
3271 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3273 rtx base
= SET_SRC (old_set
);
3274 rtx base_insn
= insn
;
3275 HOST_WIDE_INT offset
= 0;
3277 while (base
!= ep
->to_rtx
)
3279 rtx prev_insn
, prev_set
;
3281 if (GET_CODE (base
) == PLUS
3282 && CONST_INT_P (XEXP (base
, 1)))
3284 offset
+= INTVAL (XEXP (base
, 1));
3285 base
= XEXP (base
, 0);
3287 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3288 && (prev_set
= single_set (prev_insn
)) != 0
3289 && rtx_equal_p (SET_DEST (prev_set
), base
))
3291 base
= SET_SRC (prev_set
);
3292 base_insn
= prev_insn
;
3298 if (base
== ep
->to_rtx
)
3301 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3303 new_body
= old_body
;
3306 new_body
= copy_insn (old_body
);
3307 if (REG_NOTES (insn
))
3308 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3310 PATTERN (insn
) = new_body
;
3311 old_set
= single_set (insn
);
3313 /* First see if this insn remains valid when we
3314 make the change. If not, keep the INSN_CODE
3315 the same and let reload fit it up. */
3316 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3317 validate_change (insn
, &SET_DEST (old_set
),
3319 if (! apply_change_group ())
3321 SET_SRC (old_set
) = src
;
3322 SET_DEST (old_set
) = ep
->to_rtx
;
3331 /* In this case this insn isn't serving a useful purpose. We
3332 will delete it in reload_as_needed once we know that this
3333 elimination is, in fact, being done.
3335 If REPLACE isn't set, we can't delete this insn, but needn't
3336 process it since it won't be used unless something changes. */
3339 delete_dead_insn (insn
);
3347 /* We allow one special case which happens to work on all machines we
3348 currently support: a single set with the source or a REG_EQUAL
3349 note being a PLUS of an eliminable register and a constant. */
3350 plus_src
= plus_cst_src
= 0;
3351 if (old_set
&& REG_P (SET_DEST (old_set
)))
3353 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3354 plus_src
= SET_SRC (old_set
);
3355 /* First see if the source is of the form (plus (...) CST). */
3357 && CONST_INT_P (XEXP (plus_src
, 1)))
3358 plus_cst_src
= plus_src
;
3359 else if (REG_P (SET_SRC (old_set
))
3362 /* Otherwise, see if we have a REG_EQUAL note of the form
3363 (plus (...) CST). */
3365 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3367 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3368 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3369 && GET_CODE (XEXP (links
, 0)) == PLUS
3370 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3372 plus_cst_src
= XEXP (links
, 0);
3378 /* Check that the first operand of the PLUS is a hard reg or
3379 the lowpart subreg of one. */
3382 rtx reg
= XEXP (plus_cst_src
, 0);
3383 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3384 reg
= SUBREG_REG (reg
);
3386 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3392 rtx reg
= XEXP (plus_cst_src
, 0);
3393 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3395 if (GET_CODE (reg
) == SUBREG
)
3396 reg
= SUBREG_REG (reg
);
3398 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3399 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3401 rtx to_rtx
= ep
->to_rtx
;
3402 offset
+= ep
->offset
;
3403 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3405 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3406 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3408 /* If we have a nonzero offset, and the source is already
3409 a simple REG, the following transformation would
3410 increase the cost of the insn by replacing a simple REG
3411 with (plus (reg sp) CST). So try only when we already
3412 had a PLUS before. */
3413 if (offset
== 0 || plus_src
)
3415 rtx new_src
= plus_constant (to_rtx
, offset
);
3417 new_body
= old_body
;
3420 new_body
= copy_insn (old_body
);
3421 if (REG_NOTES (insn
))
3422 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3424 PATTERN (insn
) = new_body
;
3425 old_set
= single_set (insn
);
3427 /* First see if this insn remains valid when we make the
3428 change. If not, try to replace the whole pattern with
3429 a simple set (this may help if the original insn was a
3430 PARALLEL that was only recognized as single_set due to
3431 REG_UNUSED notes). If this isn't valid either, keep
3432 the INSN_CODE the same and let reload fix it up. */
3433 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3435 rtx new_pat
= gen_rtx_SET (VOIDmode
,
3436 SET_DEST (old_set
), new_src
);
3438 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3439 SET_SRC (old_set
) = new_src
;
3446 /* This can't have an effect on elimination offsets, so skip right
3452 /* Determine the effects of this insn on elimination offsets. */
3453 elimination_effects (old_body
, VOIDmode
);
3455 /* Eliminate all eliminable registers occurring in operands that
3456 can be handled by reload. */
3457 extract_insn (insn
);
3458 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3460 orig_operand
[i
] = recog_data
.operand
[i
];
3461 substed_operand
[i
] = recog_data
.operand
[i
];
3463 /* For an asm statement, every operand is eliminable. */
3464 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3466 bool is_set_src
, in_plus
;
3468 /* Check for setting a register that we know about. */
3469 if (recog_data
.operand_type
[i
] != OP_IN
3470 && REG_P (orig_operand
[i
]))
3472 /* If we are assigning to a register that can be eliminated, it
3473 must be as part of a PARALLEL, since the code above handles
3474 single SETs. We must indicate that we can no longer
3475 eliminate this reg. */
3476 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3478 if (ep
->from_rtx
== orig_operand
[i
])
3479 ep
->can_eliminate
= 0;
3482 /* Companion to the above plus substitution, we can allow
3483 invariants as the source of a plain move. */
3486 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3490 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3491 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3495 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3496 replace
? insn
: NULL_RTX
,
3497 is_set_src
|| in_plus
, false);
3498 if (substed_operand
[i
] != orig_operand
[i
])
3500 /* Terminate the search in check_eliminable_occurrences at
3502 *recog_data
.operand_loc
[i
] = 0;
3504 /* If an output operand changed from a REG to a MEM and INSN is an
3505 insn, write a CLOBBER insn. */
3506 if (recog_data
.operand_type
[i
] != OP_IN
3507 && REG_P (orig_operand
[i
])
3508 && MEM_P (substed_operand
[i
])
3510 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3514 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3515 *recog_data
.dup_loc
[i
]
3516 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3518 /* If any eliminable remain, they aren't eliminable anymore. */
3519 check_eliminable_occurrences (old_body
);
3521 /* Substitute the operands; the new values are in the substed_operand
3523 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3524 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3525 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3526 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3528 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3529 re-recognize the insn. We do this in case we had a simple addition
3530 but now can do this as a load-address. This saves an insn in this
3532 If re-recognition fails, the old insn code number will still be used,
3533 and some register operands may have changed into PLUS expressions.
3534 These will be handled by find_reloads by loading them into a register
3539 /* If we aren't replacing things permanently and we changed something,
3540 make another copy to ensure that all the RTL is new. Otherwise
3541 things can go wrong if find_reload swaps commutative operands
3542 and one is inside RTL that has been copied while the other is not. */
3543 new_body
= old_body
;
3546 new_body
= copy_insn (old_body
);
3547 if (REG_NOTES (insn
))
3548 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3550 PATTERN (insn
) = new_body
;
3552 /* If we had a move insn but now we don't, rerecognize it. This will
3553 cause spurious re-recognition if the old move had a PARALLEL since
3554 the new one still will, but we can't call single_set without
3555 having put NEW_BODY into the insn and the re-recognition won't
3556 hurt in this rare case. */
3557 /* ??? Why this huge if statement - why don't we just rerecognize the
3561 && ((REG_P (SET_SRC (old_set
))
3562 && (GET_CODE (new_body
) != SET
3563 || !REG_P (SET_SRC (new_body
))))
3564 /* If this was a load from or store to memory, compare
3565 the MEM in recog_data.operand to the one in the insn.
3566 If they are not equal, then rerecognize the insn. */
3568 && ((MEM_P (SET_SRC (old_set
))
3569 && SET_SRC (old_set
) != recog_data
.operand
[1])
3570 || (MEM_P (SET_DEST (old_set
))
3571 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3572 /* If this was an add insn before, rerecognize. */
3573 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3575 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3577 INSN_CODE (insn
) = new_icode
;
3581 /* Restore the old body. If there were any changes to it, we made a copy
3582 of it while the changes were still in place, so we'll correctly return
3583 a modified insn below. */
3586 /* Restore the old body. */
3587 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3588 /* Restoring a top-level match_parallel would clobber the new_body
3589 we installed in the insn. */
3590 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3591 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3592 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3593 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3596 /* Update all elimination pairs to reflect the status after the current
3597 insn. The changes we make were determined by the earlier call to
3598 elimination_effects.
3600 We also detect cases where register elimination cannot be done,
3601 namely, if a register would be both changed and referenced outside a MEM
3602 in the resulting insn since such an insn is often undefined and, even if
3603 not, we cannot know what meaning will be given to it. Note that it is
3604 valid to have a register used in an address in an insn that changes it
3605 (presumably with a pre- or post-increment or decrement).
3607 If anything changes, return nonzero. */
3609 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3611 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3612 ep
->can_eliminate
= 0;
3614 ep
->ref_outside_mem
= 0;
3616 if (ep
->previous_offset
!= ep
->offset
)
3621 /* If we changed something, perform elimination in REG_NOTES. This is
3622 needed even when REPLACE is zero because a REG_DEAD note might refer
3623 to a register that we eliminate and could cause a different number
3624 of spill registers to be needed in the final reload pass than in
3626 if (val
&& REG_NOTES (insn
) != 0)
3628 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3634 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3635 register allocator. INSN is the instruction we need to examine, we perform
3636 eliminations in its operands and record cases where eliminating a reg with
3637 an invariant equivalence would add extra cost. */
3640 elimination_costs_in_insn (rtx insn
)
3642 int icode
= recog_memoized (insn
);
3643 rtx old_body
= PATTERN (insn
);
3644 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3645 rtx old_set
= single_set (insn
);
3647 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3648 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3649 struct elim_table
*ep
;
3650 rtx plus_src
, plus_cst_src
;
3653 if (! insn_is_asm
&& icode
< 0)
3655 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
3656 || GET_CODE (PATTERN (insn
)) == CLOBBER
3657 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
3658 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3659 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
3660 || DEBUG_INSN_P (insn
));
3664 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3665 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3667 /* Check for setting an eliminable register. */
3668 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3669 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3673 /* We allow one special case which happens to work on all machines we
3674 currently support: a single set with the source or a REG_EQUAL
3675 note being a PLUS of an eliminable register and a constant. */
3676 plus_src
= plus_cst_src
= 0;
3678 if (old_set
&& REG_P (SET_DEST (old_set
)))
3681 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3682 plus_src
= SET_SRC (old_set
);
3683 /* First see if the source is of the form (plus (...) CST). */
3685 && CONST_INT_P (XEXP (plus_src
, 1)))
3686 plus_cst_src
= plus_src
;
3687 else if (REG_P (SET_SRC (old_set
))
3690 /* Otherwise, see if we have a REG_EQUAL note of the form
3691 (plus (...) CST). */
3693 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3695 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3696 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3697 && GET_CODE (XEXP (links
, 0)) == PLUS
3698 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3700 plus_cst_src
= XEXP (links
, 0);
3707 /* Determine the effects of this insn on elimination offsets. */
3708 elimination_effects (old_body
, VOIDmode
);
3710 /* Eliminate all eliminable registers occurring in operands that
3711 can be handled by reload. */
3712 extract_insn (insn
);
3713 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3714 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3716 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3718 orig_operand
[i
] = recog_data
.operand
[i
];
3720 /* For an asm statement, every operand is eliminable. */
3721 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3723 bool is_set_src
, in_plus
;
3725 /* Check for setting a register that we know about. */
3726 if (recog_data
.operand_type
[i
] != OP_IN
3727 && REG_P (orig_operand
[i
]))
3729 /* If we are assigning to a register that can be eliminated, it
3730 must be as part of a PARALLEL, since the code above handles
3731 single SETs. We must indicate that we can no longer
3732 eliminate this reg. */
3733 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3735 if (ep
->from_rtx
== orig_operand
[i
])
3736 ep
->can_eliminate
= 0;
3739 /* Companion to the above plus substitution, we can allow
3740 invariants as the source of a plain move. */
3742 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3744 if (is_set_src
&& !sets_reg_p
)
3745 note_reg_elim_costly (&SET_SRC (old_set
), insn
);
3747 if (plus_src
&& sets_reg_p
3748 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3749 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3752 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3754 is_set_src
|| in_plus
, true);
3755 /* Terminate the search in check_eliminable_occurrences at
3757 *recog_data
.operand_loc
[i
] = 0;
3761 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3762 *recog_data
.dup_loc
[i
]
3763 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3765 /* If any eliminable remain, they aren't eliminable anymore. */
3766 check_eliminable_occurrences (old_body
);
3768 /* Restore the old body. */
3769 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3770 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3771 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3772 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3774 /* Update all elimination pairs to reflect the status after the current
3775 insn. The changes we make were determined by the earlier call to
3776 elimination_effects. */
3778 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3780 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3781 ep
->can_eliminate
= 0;
3783 ep
->ref_outside_mem
= 0;
3789 /* Loop through all elimination pairs.
3790 Recalculate the number not at initial offset.
3792 Compute the maximum offset (minimum offset if the stack does not
3793 grow downward) for each elimination pair. */
3796 update_eliminable_offsets (void)
3798 struct elim_table
*ep
;
3800 num_not_at_initial_offset
= 0;
3801 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3803 ep
->previous_offset
= ep
->offset
;
3804 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3805 num_not_at_initial_offset
++;
3809 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3810 replacement we currently believe is valid, mark it as not eliminable if X
3811 modifies DEST in any way other than by adding a constant integer to it.
3813 If DEST is the frame pointer, we do nothing because we assume that
3814 all assignments to the hard frame pointer are nonlocal gotos and are being
3815 done at a time when they are valid and do not disturb anything else.
3816 Some machines want to eliminate a fake argument pointer with either the
3817 frame or stack pointer. Assignments to the hard frame pointer must not
3818 prevent this elimination.
3820 Called via note_stores from reload before starting its passes to scan
3821 the insns of the function. */
3824 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3828 /* A SUBREG of a hard register here is just changing its mode. We should
3829 not see a SUBREG of an eliminable hard register, but check just in
3831 if (GET_CODE (dest
) == SUBREG
)
3832 dest
= SUBREG_REG (dest
);
3834 if (dest
== hard_frame_pointer_rtx
)
3837 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3838 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3839 && (GET_CODE (x
) != SET
3840 || GET_CODE (SET_SRC (x
)) != PLUS
3841 || XEXP (SET_SRC (x
), 0) != dest
3842 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3844 reg_eliminate
[i
].can_eliminate_previous
3845 = reg_eliminate
[i
].can_eliminate
= 0;
3850 /* Verify that the initial elimination offsets did not change since the
3851 last call to set_initial_elim_offsets. This is used to catch cases
3852 where something illegal happened during reload_as_needed that could
3853 cause incorrect code to be generated if we did not check for it. */
3856 verify_initial_elim_offsets (void)
3860 if (!num_eliminable
)
3863 #ifdef ELIMINABLE_REGS
3865 struct elim_table
*ep
;
3867 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3869 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3870 if (t
!= ep
->initial_offset
)
3875 INITIAL_FRAME_POINTER_OFFSET (t
);
3876 if (t
!= reg_eliminate
[0].initial_offset
)
3883 /* Reset all offsets on eliminable registers to their initial values. */
3886 set_initial_elim_offsets (void)
3888 struct elim_table
*ep
= reg_eliminate
;
3890 #ifdef ELIMINABLE_REGS
3891 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3893 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3894 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3897 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3898 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3901 num_not_at_initial_offset
= 0;
3904 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3907 set_initial_eh_label_offset (rtx label
)
3909 set_label_offsets (label
, NULL_RTX
, 1);
3912 /* Initialize the known label offsets.
3913 Set a known offset for each forced label to be at the initial offset
3914 of each elimination. We do this because we assume that all
3915 computed jumps occur from a location where each elimination is
3916 at its initial offset.
3917 For all other labels, show that we don't know the offsets. */
3920 set_initial_label_offsets (void)
3923 memset (offsets_known_at
, 0, num_labels
);
3925 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3927 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3929 for (x
= nonlocal_goto_handler_labels
; x
; x
= XEXP (x
, 1))
3931 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3933 for_each_eh_label (set_initial_eh_label_offset
);
3936 /* Set all elimination offsets to the known values for the code label given
3940 set_offsets_for_label (rtx insn
)
3943 int label_nr
= CODE_LABEL_NUMBER (insn
);
3944 struct elim_table
*ep
;
3946 num_not_at_initial_offset
= 0;
3947 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3949 ep
->offset
= ep
->previous_offset
3950 = offsets_at
[label_nr
- first_label_num
][i
];
3951 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3952 num_not_at_initial_offset
++;
3956 /* See if anything that happened changes which eliminations are valid.
3957 For example, on the SPARC, whether or not the frame pointer can
3958 be eliminated can depend on what registers have been used. We need
3959 not check some conditions again (such as flag_omit_frame_pointer)
3960 since they can't have changed. */
3963 update_eliminables (HARD_REG_SET
*pset
)
3965 int previous_frame_pointer_needed
= frame_pointer_needed
;
3966 struct elim_table
*ep
;
3968 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3969 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3970 && targetm
.frame_pointer_required ())
3971 #ifdef ELIMINABLE_REGS
3972 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3975 ep
->can_eliminate
= 0;
3977 /* Look for the case where we have discovered that we can't replace
3978 register A with register B and that means that we will now be
3979 trying to replace register A with register C. This means we can
3980 no longer replace register C with register B and we need to disable
3981 such an elimination, if it exists. This occurs often with A == ap,
3982 B == sp, and C == fp. */
3984 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3986 struct elim_table
*op
;
3989 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3991 /* Find the current elimination for ep->from, if there is a
3993 for (op
= reg_eliminate
;
3994 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3995 if (op
->from
== ep
->from
&& op
->can_eliminate
)
4001 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
4003 for (op
= reg_eliminate
;
4004 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
4005 if (op
->from
== new_to
&& op
->to
== ep
->to
)
4006 op
->can_eliminate
= 0;
4010 /* See if any registers that we thought we could eliminate the previous
4011 time are no longer eliminable. If so, something has changed and we
4012 must spill the register. Also, recompute the number of eliminable
4013 registers and see if the frame pointer is needed; it is if there is
4014 no elimination of the frame pointer that we can perform. */
4016 frame_pointer_needed
= 1;
4017 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4019 if (ep
->can_eliminate
4020 && ep
->from
== FRAME_POINTER_REGNUM
4021 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
4022 && (! SUPPORTS_STACK_ALIGNMENT
4023 || ! crtl
->stack_realign_needed
))
4024 frame_pointer_needed
= 0;
4026 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
4028 ep
->can_eliminate_previous
= 0;
4029 SET_HARD_REG_BIT (*pset
, ep
->from
);
4034 /* If we didn't need a frame pointer last time, but we do now, spill
4035 the hard frame pointer. */
4036 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4037 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4040 /* Return true if X is used as the target register of an elimination. */
4043 elimination_target_reg_p (rtx x
)
4045 struct elim_table
*ep
;
4047 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4048 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4054 /* Initialize the table of registers to eliminate.
4055 Pre-condition: global flag frame_pointer_needed has been set before
4056 calling this function. */
4059 init_elim_table (void)
4061 struct elim_table
*ep
;
4062 #ifdef ELIMINABLE_REGS
4063 const struct elim_table_1
*ep1
;
4067 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4071 #ifdef ELIMINABLE_REGS
4072 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4073 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4075 ep
->from
= ep1
->from
;
4077 ep
->can_eliminate
= ep
->can_eliminate_previous
4078 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4079 && ! (ep
->to
== STACK_POINTER_REGNUM
4080 && frame_pointer_needed
4081 && (! SUPPORTS_STACK_ALIGNMENT
4082 || ! stack_realign_fp
)));
4085 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4086 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4087 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4088 = ! frame_pointer_needed
;
4091 /* Count the number of eliminable registers and build the FROM and TO
4092 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4093 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4094 We depend on this. */
4095 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4097 num_eliminable
+= ep
->can_eliminate
;
4098 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4099 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4103 /* Find all the pseudo registers that didn't get hard regs
4104 but do have known equivalent constants or memory slots.
4105 These include parameters (known equivalent to parameter slots)
4106 and cse'd or loop-moved constant memory addresses.
4108 Record constant equivalents in reg_equiv_constant
4109 so they will be substituted by find_reloads.
4110 Record memory equivalents in reg_mem_equiv so they can
4111 be substituted eventually by altering the REG-rtx's. */
4114 init_eliminable_invariants (rtx first
, bool do_subregs
)
4121 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4123 reg_max_ref_width
= NULL
;
4125 num_eliminable_invariants
= 0;
4127 first_label_num
= get_first_label_num ();
4128 num_labels
= max_label_num () - first_label_num
;
4130 /* Allocate the tables used to store offset information at labels. */
4131 offsets_known_at
= XNEWVEC (char, num_labels
);
4132 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4134 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4135 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4136 find largest such for each pseudo. FIRST is the head of the insn
4139 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4141 rtx set
= single_set (insn
);
4143 /* We may introduce USEs that we want to remove at the end, so
4144 we'll mark them with QImode. Make sure there are no
4145 previously-marked insns left by say regmove. */
4146 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4147 && GET_MODE (insn
) != VOIDmode
)
4148 PUT_MODE (insn
, VOIDmode
);
4150 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4151 scan_paradoxical_subregs (PATTERN (insn
));
4153 if (set
!= 0 && REG_P (SET_DEST (set
)))
4155 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4161 i
= REGNO (SET_DEST (set
));
4164 if (i
<= LAST_VIRTUAL_REGISTER
)
4167 /* If flag_pic and we have constant, verify it's legitimate. */
4169 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4171 /* It can happen that a REG_EQUIV note contains a MEM
4172 that is not a legitimate memory operand. As later
4173 stages of reload assume that all addresses found
4174 in the reg_equiv_* arrays were originally legitimate,
4175 we ignore such REG_EQUIV notes. */
4176 if (memory_operand (x
, VOIDmode
))
4178 /* Always unshare the equivalence, so we can
4179 substitute into this insn without touching the
4181 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4183 else if (function_invariant_p (x
))
4185 enum machine_mode mode
;
4187 mode
= GET_MODE (SET_DEST (set
));
4188 if (GET_CODE (x
) == PLUS
)
4190 /* This is PLUS of frame pointer and a constant,
4191 and might be shared. Unshare it. */
4192 reg_equiv_invariant (i
) = copy_rtx (x
);
4193 num_eliminable_invariants
++;
4195 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4197 reg_equiv_invariant (i
) = x
;
4198 num_eliminable_invariants
++;
4200 else if (targetm
.legitimate_constant_p (mode
, x
))
4201 reg_equiv_constant (i
) = x
;
4204 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4205 if (! reg_equiv_memory_loc (i
))
4206 reg_equiv_init (i
) = NULL_RTX
;
4211 reg_equiv_init (i
) = NULL_RTX
;
4216 reg_equiv_init (i
) = NULL_RTX
;
4221 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4222 if (reg_equiv_init (i
))
4224 fprintf (dump_file
, "init_insns for %u: ", i
);
4225 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4226 fprintf (dump_file
, "\n");
4230 /* Indicate that we no longer have known memory locations or constants.
4231 Free all data involved in tracking these. */
4234 free_reg_equiv (void)
4239 free (offsets_known_at
);
4242 offsets_known_at
= 0;
4244 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4245 if (reg_equiv_alt_mem_list (i
))
4246 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4247 VEC_free (reg_equivs_t
, gc
, reg_equivs
);
4252 /* Kick all pseudos out of hard register REGNO.
4254 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4255 because we found we can't eliminate some register. In the case, no pseudos
4256 are allowed to be in the register, even if they are only in a block that
4257 doesn't require spill registers, unlike the case when we are spilling this
4258 hard reg to produce another spill register.
4260 Return nonzero if any pseudos needed to be kicked out. */
4263 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4269 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4270 df_set_regs_ever_live (regno
, true);
4273 /* Spill every pseudo reg that was allocated to this reg
4274 or to something that overlaps this reg. */
4276 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4277 if (reg_renumber
[i
] >= 0
4278 && (unsigned int) reg_renumber
[i
] <= regno
4279 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4280 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4283 /* After find_reload_regs has been run for all insn that need reloads,
4284 and/or spill_hard_regs was called, this function is used to actually
4285 spill pseudo registers and try to reallocate them. It also sets up the
4286 spill_regs array for use by choose_reload_regs. */
4289 finish_spills (int global
)
4291 struct insn_chain
*chain
;
4292 int something_changed
= 0;
4294 reg_set_iterator rsi
;
4296 /* Build the spill_regs array for the function. */
4297 /* If there are some registers still to eliminate and one of the spill regs
4298 wasn't ever used before, additional stack space may have to be
4299 allocated to store this register. Thus, we may have changed the offset
4300 between the stack and frame pointers, so mark that something has changed.
4302 One might think that we need only set VAL to 1 if this is a call-used
4303 register. However, the set of registers that must be saved by the
4304 prologue is not identical to the call-used set. For example, the
4305 register used by the call insn for the return PC is a call-used register,
4306 but must be saved by the prologue. */
4309 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4310 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4312 spill_reg_order
[i
] = n_spills
;
4313 spill_regs
[n_spills
++] = i
;
4314 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4315 something_changed
= 1;
4316 df_set_regs_ever_live (i
, true);
4319 spill_reg_order
[i
] = -1;
4321 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4322 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4324 /* Record the current hard register the pseudo is allocated to
4325 in pseudo_previous_regs so we avoid reallocating it to the
4326 same hard reg in a later pass. */
4327 gcc_assert (reg_renumber
[i
] >= 0);
4329 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4330 /* Mark it as no longer having a hard register home. */
4331 reg_renumber
[i
] = -1;
4332 if (ira_conflicts_p
)
4333 /* Inform IRA about the change. */
4334 ira_mark_allocation_change (i
);
4335 /* We will need to scan everything again. */
4336 something_changed
= 1;
4339 /* Retry global register allocation if possible. */
4340 if (global
&& ira_conflicts_p
)
4344 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4345 /* For every insn that needs reloads, set the registers used as spill
4346 regs in pseudo_forbidden_regs for every pseudo live across the
4348 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4350 EXECUTE_IF_SET_IN_REG_SET
4351 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4353 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4354 chain
->used_spill_regs
);
4356 EXECUTE_IF_SET_IN_REG_SET
4357 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4359 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4360 chain
->used_spill_regs
);
4364 /* Retry allocating the pseudos spilled in IRA and the
4365 reload. For each reg, merge the various reg sets that
4366 indicate which hard regs can't be used, and call
4367 ira_reassign_pseudos. */
4368 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4369 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4371 if (reg_renumber
[i
] < 0)
4372 temp_pseudo_reg_arr
[n
++] = i
;
4374 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4376 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4377 bad_spill_regs_global
,
4378 pseudo_forbidden_regs
, pseudo_previous_regs
,
4380 something_changed
= 1;
4382 /* Fix up the register information in the insn chain.
4383 This involves deleting those of the spilled pseudos which did not get
4384 a new hard register home from the live_{before,after} sets. */
4385 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4387 HARD_REG_SET used_by_pseudos
;
4388 HARD_REG_SET used_by_pseudos2
;
4390 if (! ira_conflicts_p
)
4392 /* Don't do it for IRA because IRA and the reload still can
4393 assign hard registers to the spilled pseudos on next
4394 reload iterations. */
4395 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4396 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4398 /* Mark any unallocated hard regs as available for spills. That
4399 makes inheritance work somewhat better. */
4400 if (chain
->need_reload
)
4402 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4403 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4404 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4406 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4407 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4408 /* Value of chain->used_spill_regs from previous iteration
4409 may be not included in the value calculated here because
4410 of possible removing caller-saves insns (see function
4411 delete_caller_save_insns. */
4412 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4413 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4417 CLEAR_REG_SET (&changed_allocation_pseudos
);
4418 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4419 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4421 int regno
= reg_renumber
[i
];
4422 if (reg_old_renumber
[i
] == regno
)
4425 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4427 alter_reg (i
, reg_old_renumber
[i
], false);
4428 reg_old_renumber
[i
] = regno
;
4432 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4434 fprintf (dump_file
, " Register %d now in %d.\n\n",
4435 i
, reg_renumber
[i
]);
4439 return something_changed
;
4442 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4445 scan_paradoxical_subregs (rtx x
)
4449 enum rtx_code code
= GET_CODE (x
);
4460 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
4468 if (REG_P (SUBREG_REG (x
))
4469 && (GET_MODE_SIZE (GET_MODE (x
))
4470 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4472 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4473 = GET_MODE_SIZE (GET_MODE (x
));
4474 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4482 fmt
= GET_RTX_FORMAT (code
);
4483 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4486 scan_paradoxical_subregs (XEXP (x
, i
));
4487 else if (fmt
[i
] == 'E')
4490 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4491 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4496 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4497 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4498 and apply the corresponding narrowing subreg to *OTHER_PTR.
4499 Return true if the operands were changed, false otherwise. */
4502 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4504 rtx op
, inner
, other
, tem
;
4507 if (!paradoxical_subreg_p (op
))
4509 inner
= SUBREG_REG (op
);
4512 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4516 /* If the lowpart operation turned a hard register into a subreg,
4517 rather than simplifying it to another hard register, then the
4518 mode change cannot be properly represented. For example, OTHER
4519 might be valid in its current mode, but not in the new one. */
4520 if (GET_CODE (tem
) == SUBREG
4522 && HARD_REGISTER_P (other
))
4530 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4531 examine all of the reload insns between PREV and NEXT exclusive, and
4532 annotate all that may trap. */
4535 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
4537 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4540 if (!insn_could_throw_p (insn
))
4541 remove_note (insn
, note
);
4542 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4545 /* Reload pseudo-registers into hard regs around each insn as needed.
4546 Additional register load insns are output before the insn that needs it
4547 and perhaps store insns after insns that modify the reloaded pseudo reg.
4549 reg_last_reload_reg and reg_reloaded_contents keep track of
4550 which registers are already available in reload registers.
4551 We update these for the reloads that we perform,
4552 as the insns are scanned. */
4555 reload_as_needed (int live_known
)
4557 struct insn_chain
*chain
;
4558 #if defined (AUTO_INC_DEC)
4563 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4564 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4565 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4566 INIT_REG_SET (®_has_output_reload
);
4567 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4568 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4570 set_initial_elim_offsets ();
4572 /* Generate a marker insn that we will move around. */
4573 marker
= emit_note (NOTE_INSN_DELETED
);
4574 unlink_insn_chain (marker
, marker
);
4576 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4579 rtx insn
= chain
->insn
;
4580 rtx old_next
= NEXT_INSN (insn
);
4582 rtx old_prev
= PREV_INSN (insn
);
4585 /* If we pass a label, copy the offsets from the label information
4586 into the current offsets of each elimination. */
4588 set_offsets_for_label (insn
);
4590 else if (INSN_P (insn
))
4592 regset_head regs_to_forget
;
4593 INIT_REG_SET (®s_to_forget
);
4594 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4596 /* If this is a USE and CLOBBER of a MEM, ensure that any
4597 references to eliminable registers have been removed. */
4599 if ((GET_CODE (PATTERN (insn
)) == USE
4600 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4601 && MEM_P (XEXP (PATTERN (insn
), 0)))
4602 XEXP (XEXP (PATTERN (insn
), 0), 0)
4603 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4604 GET_MODE (XEXP (PATTERN (insn
), 0)),
4607 /* If we need to do register elimination processing, do so.
4608 This might delete the insn, in which case we are done. */
4609 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4611 eliminate_regs_in_insn (insn
, 1);
4614 update_eliminable_offsets ();
4615 CLEAR_REG_SET (®s_to_forget
);
4620 /* If need_elim is nonzero but need_reload is zero, one might think
4621 that we could simply set n_reloads to 0. However, find_reloads
4622 could have done some manipulation of the insn (such as swapping
4623 commutative operands), and these manipulations are lost during
4624 the first pass for every insn that needs register elimination.
4625 So the actions of find_reloads must be redone here. */
4627 if (! chain
->need_elim
&& ! chain
->need_reload
4628 && ! chain
->need_operand_change
)
4630 /* First find the pseudo regs that must be reloaded for this insn.
4631 This info is returned in the tables reload_... (see reload.h).
4632 Also modify the body of INSN by substituting RELOAD
4633 rtx's for those pseudo regs. */
4636 CLEAR_REG_SET (®_has_output_reload
);
4637 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4639 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4645 rtx next
= NEXT_INSN (insn
);
4648 /* ??? PREV can get deleted by reload inheritance.
4649 Work around this by emitting a marker note. */
4650 prev
= PREV_INSN (insn
);
4651 reorder_insns_nobb (marker
, marker
, prev
);
4653 /* Now compute which reload regs to reload them into. Perhaps
4654 reusing reload regs from previous insns, or else output
4655 load insns to reload them. Maybe output store insns too.
4656 Record the choices of reload reg in reload_reg_rtx. */
4657 choose_reload_regs (chain
);
4659 /* Generate the insns to reload operands into or out of
4660 their reload regs. */
4661 emit_reload_insns (chain
);
4663 /* Substitute the chosen reload regs from reload_reg_rtx
4664 into the insn's body (or perhaps into the bodies of other
4665 load and store insn that we just made for reloading
4666 and that we moved the structure into). */
4667 subst_reloads (insn
);
4669 prev
= PREV_INSN (marker
);
4670 unlink_insn_chain (marker
, marker
);
4672 /* Adjust the exception region notes for loads and stores. */
4673 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4674 fixup_eh_region_note (insn
, prev
, next
);
4676 /* Adjust the location of REG_ARGS_SIZE. */
4677 p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4680 remove_note (insn
, p
);
4681 fixup_args_size_notes (prev
, PREV_INSN (next
),
4682 INTVAL (XEXP (p
, 0)));
4685 /* If this was an ASM, make sure that all the reload insns
4686 we have generated are valid. If not, give an error
4688 if (asm_noperands (PATTERN (insn
)) >= 0)
4689 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4690 if (p
!= insn
&& INSN_P (p
)
4691 && GET_CODE (PATTERN (p
)) != USE
4692 && (recog_memoized (p
) < 0
4693 || (extract_insn (p
), ! constrain_operands (1))))
4695 error_for_asm (insn
,
4696 "%<asm%> operand requires "
4697 "impossible reload");
4702 if (num_eliminable
&& chain
->need_elim
)
4703 update_eliminable_offsets ();
4705 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4706 is no longer validly lying around to save a future reload.
4707 Note that this does not detect pseudos that were reloaded
4708 for this insn in order to be stored in
4709 (obeying register constraints). That is correct; such reload
4710 registers ARE still valid. */
4711 forget_marked_reloads (®s_to_forget
);
4712 CLEAR_REG_SET (®s_to_forget
);
4714 /* There may have been CLOBBER insns placed after INSN. So scan
4715 between INSN and NEXT and use them to forget old reloads. */
4716 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4717 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4718 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4721 /* Likewise for regs altered by auto-increment in this insn.
4722 REG_INC notes have been changed by reloading:
4723 find_reloads_address_1 records substitutions for them,
4724 which have been performed by subst_reloads above. */
4725 for (i
= n_reloads
- 1; i
>= 0; i
--)
4727 rtx in_reg
= rld
[i
].in_reg
;
4730 enum rtx_code code
= GET_CODE (in_reg
);
4731 /* PRE_INC / PRE_DEC will have the reload register ending up
4732 with the same value as the stack slot, but that doesn't
4733 hold true for POST_INC / POST_DEC. Either we have to
4734 convert the memory access to a true POST_INC / POST_DEC,
4735 or we can't use the reload register for inheritance. */
4736 if ((code
== POST_INC
|| code
== POST_DEC
)
4737 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4738 REGNO (rld
[i
].reg_rtx
))
4739 /* Make sure it is the inc/dec pseudo, and not
4740 some other (e.g. output operand) pseudo. */
4741 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4742 == REGNO (XEXP (in_reg
, 0))))
4745 rtx reload_reg
= rld
[i
].reg_rtx
;
4746 enum machine_mode mode
= GET_MODE (reload_reg
);
4750 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4752 /* We really want to ignore REG_INC notes here, so
4753 use PATTERN (p) as argument to reg_set_p . */
4754 if (reg_set_p (reload_reg
, PATTERN (p
)))
4756 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4762 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4764 validate_replace_rtx_group (reload_reg
,
4766 n
= verify_changes (0);
4768 /* We must also verify that the constraints
4769 are met after the replacement. Make sure
4770 extract_insn is only called for an insn
4771 where the replacements were found to be
4776 n
= constrain_operands (1);
4779 /* If the constraints were not met, then
4780 undo the replacement, else confirm it. */
4784 confirm_change_group ();
4790 add_reg_note (p
, REG_INC
, reload_reg
);
4791 /* Mark this as having an output reload so that the
4792 REG_INC processing code below won't invalidate
4793 the reload for inheritance. */
4794 SET_HARD_REG_BIT (reg_is_output_reload
,
4795 REGNO (reload_reg
));
4796 SET_REGNO_REG_SET (®_has_output_reload
,
4797 REGNO (XEXP (in_reg
, 0)));
4800 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4803 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4804 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4805 REGNO (rld
[i
].reg_rtx
))
4806 /* Make sure it is the inc/dec pseudo, and not
4807 some other (e.g. output operand) pseudo. */
4808 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4809 == REGNO (XEXP (in_reg
, 0))))
4811 SET_HARD_REG_BIT (reg_is_output_reload
,
4812 REGNO (rld
[i
].reg_rtx
));
4813 SET_REGNO_REG_SET (®_has_output_reload
,
4814 REGNO (XEXP (in_reg
, 0)));
4816 else if (code
== PRE_INC
|| code
== PRE_DEC
4817 || code
== POST_INC
|| code
== POST_DEC
)
4819 int in_regno
= REGNO (XEXP (in_reg
, 0));
4821 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4824 bool forget_p
= true;
4826 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4827 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4830 for (x
= old_prev
? NEXT_INSN (old_prev
) : insn
;
4833 if (x
== reg_reloaded_insn
[in_hard_regno
])
4839 /* If for some reasons, we didn't set up
4840 reg_last_reload_reg in this insn,
4841 invalidate inheritance from previous
4842 insns for the incremented/decremented
4843 register. Such registers will be not in
4844 reg_has_output_reload. Invalidate it
4845 also if the corresponding element in
4846 reg_reloaded_insn is also
4849 forget_old_reloads_1 (XEXP (in_reg
, 0),
4855 /* If a pseudo that got a hard register is auto-incremented,
4856 we must purge records of copying it into pseudos without
4858 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4859 if (REG_NOTE_KIND (x
) == REG_INC
)
4861 /* See if this pseudo reg was reloaded in this insn.
4862 If so, its last-reload info is still valid
4863 because it is based on this insn's reload. */
4864 for (i
= 0; i
< n_reloads
; i
++)
4865 if (rld
[i
].out
== XEXP (x
, 0))
4869 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4873 /* A reload reg's contents are unknown after a label. */
4875 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4877 /* Don't assume a reload reg is still good after a call insn
4878 if it is a call-used reg, or if it contains a value that will
4879 be partially clobbered by the call. */
4880 else if (CALL_P (insn
))
4882 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4883 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4885 /* If this is a call to a setjmp-type function, we must not
4886 reuse any reload reg contents across the call; that will
4887 just be clobbered by other uses of the register in later
4888 code, before the longjmp. */
4889 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4890 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4895 free (reg_last_reload_reg
);
4896 CLEAR_REG_SET (®_has_output_reload
);
4899 /* Discard all record of any value reloaded from X,
4900 or reloaded in X from someplace else;
4901 unless X is an output reload reg of the current insn.
4903 X may be a hard reg (the reload reg)
4904 or it may be a pseudo reg that was reloaded from.
4906 When DATA is non-NULL just mark the registers in regset
4907 to be forgotten later. */
4910 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4915 regset regs
= (regset
) data
;
4917 /* note_stores does give us subregs of hard regs,
4918 subreg_regno_offset requires a hard reg. */
4919 while (GET_CODE (x
) == SUBREG
)
4921 /* We ignore the subreg offset when calculating the regno,
4922 because we are using the entire underlying hard register
4932 if (regno
>= FIRST_PSEUDO_REGISTER
)
4938 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4939 /* Storing into a spilled-reg invalidates its contents.
4940 This can happen if a block-local pseudo is allocated to that reg
4941 and it wasn't spilled because this block's total need is 0.
4942 Then some insn might have an optional reload and use this reg. */
4944 for (i
= 0; i
< nr
; i
++)
4945 /* But don't do this if the reg actually serves as an output
4946 reload reg in the current instruction. */
4948 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4950 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4951 spill_reg_store
[regno
+ i
] = 0;
4957 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4960 /* Since value of X has changed,
4961 forget any value previously copied from it. */
4964 /* But don't forget a copy if this is the output reload
4965 that establishes the copy's validity. */
4967 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4968 reg_last_reload_reg
[regno
+ nr
] = 0;
4972 /* Forget the reloads marked in regset by previous function. */
4974 forget_marked_reloads (regset regs
)
4977 reg_set_iterator rsi
;
4978 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4980 if (reg
< FIRST_PSEUDO_REGISTER
4981 /* But don't do this if the reg actually serves as an output
4982 reload reg in the current instruction. */
4984 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4986 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4987 spill_reg_store
[reg
] = 0;
4990 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4991 reg_last_reload_reg
[reg
] = 0;
4995 /* The following HARD_REG_SETs indicate when each hard register is
4996 used for a reload of various parts of the current insn. */
4998 /* If reg is unavailable for all reloads. */
4999 static HARD_REG_SET reload_reg_unavailable
;
5000 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
5001 static HARD_REG_SET reload_reg_used
;
5002 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
5003 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5004 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
5005 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5006 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
5007 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5008 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5009 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5010 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5011 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5012 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5013 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5014 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5015 static HARD_REG_SET reload_reg_used_in_op_addr
;
5016 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5017 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
5018 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5019 static HARD_REG_SET reload_reg_used_in_insn
;
5020 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5021 static HARD_REG_SET reload_reg_used_in_other_addr
;
5023 /* If reg is in use as a reload reg for any sort of reload. */
5024 static HARD_REG_SET reload_reg_used_at_all
;
5026 /* If reg is use as an inherited reload. We just mark the first register
5028 static HARD_REG_SET reload_reg_used_for_inherit
;
5030 /* Records which hard regs are used in any way, either as explicit use or
5031 by being allocated to a pseudo during any point of the current insn. */
5032 static HARD_REG_SET reg_used_in_insn
;
5034 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5035 TYPE. MODE is used to indicate how many consecutive regs are
5039 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
5040 enum machine_mode mode
)
5045 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
5048 case RELOAD_FOR_INPUT_ADDRESS
:
5049 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
5052 case RELOAD_FOR_INPADDR_ADDRESS
:
5053 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
5056 case RELOAD_FOR_OUTPUT_ADDRESS
:
5057 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
5060 case RELOAD_FOR_OUTADDR_ADDRESS
:
5061 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
5064 case RELOAD_FOR_OPERAND_ADDRESS
:
5065 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
5068 case RELOAD_FOR_OPADDR_ADDR
:
5069 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
5072 case RELOAD_FOR_OTHER_ADDRESS
:
5073 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
5076 case RELOAD_FOR_INPUT
:
5077 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
5080 case RELOAD_FOR_OUTPUT
:
5081 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
5084 case RELOAD_FOR_INSN
:
5085 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5089 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5092 /* Similarly, but show REGNO is no longer in use for a reload. */
5095 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5096 enum reload_type type
, enum machine_mode mode
)
5098 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5099 unsigned int start_regno
, end_regno
, r
;
5101 /* A complication is that for some reload types, inheritance might
5102 allow multiple reloads of the same types to share a reload register.
5103 We set check_opnum if we have to check only reloads with the same
5104 operand number, and check_any if we have to check all reloads. */
5105 int check_opnum
= 0;
5107 HARD_REG_SET
*used_in_set
;
5112 used_in_set
= &reload_reg_used
;
5115 case RELOAD_FOR_INPUT_ADDRESS
:
5116 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5119 case RELOAD_FOR_INPADDR_ADDRESS
:
5121 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5124 case RELOAD_FOR_OUTPUT_ADDRESS
:
5125 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5128 case RELOAD_FOR_OUTADDR_ADDRESS
:
5130 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5133 case RELOAD_FOR_OPERAND_ADDRESS
:
5134 used_in_set
= &reload_reg_used_in_op_addr
;
5137 case RELOAD_FOR_OPADDR_ADDR
:
5139 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5142 case RELOAD_FOR_OTHER_ADDRESS
:
5143 used_in_set
= &reload_reg_used_in_other_addr
;
5147 case RELOAD_FOR_INPUT
:
5148 used_in_set
= &reload_reg_used_in_input
[opnum
];
5151 case RELOAD_FOR_OUTPUT
:
5152 used_in_set
= &reload_reg_used_in_output
[opnum
];
5155 case RELOAD_FOR_INSN
:
5156 used_in_set
= &reload_reg_used_in_insn
;
5161 /* We resolve conflicts with remaining reloads of the same type by
5162 excluding the intervals of reload registers by them from the
5163 interval of freed reload registers. Since we only keep track of
5164 one set of interval bounds, we might have to exclude somewhat
5165 more than what would be necessary if we used a HARD_REG_SET here.
5166 But this should only happen very infrequently, so there should
5167 be no reason to worry about it. */
5169 start_regno
= regno
;
5170 end_regno
= regno
+ nregs
;
5171 if (check_opnum
|| check_any
)
5173 for (i
= n_reloads
- 1; i
>= 0; i
--)
5175 if (rld
[i
].when_needed
== type
5176 && (check_any
|| rld
[i
].opnum
== opnum
)
5179 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5180 unsigned int conflict_end
5181 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5183 /* If there is an overlap with the first to-be-freed register,
5184 adjust the interval start. */
5185 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5186 start_regno
= conflict_end
;
5187 /* Otherwise, if there is a conflict with one of the other
5188 to-be-freed registers, adjust the interval end. */
5189 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5190 end_regno
= conflict_start
;
5195 for (r
= start_regno
; r
< end_regno
; r
++)
5196 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5199 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5200 specified by OPNUM and TYPE. */
5203 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5207 /* In use for a RELOAD_OTHER means it's not available for anything. */
5208 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5209 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5215 /* In use for anything means we can't use it for RELOAD_OTHER. */
5216 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5217 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5218 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5219 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5222 for (i
= 0; i
< reload_n_operands
; i
++)
5223 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5224 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5225 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5226 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5227 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5228 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5233 case RELOAD_FOR_INPUT
:
5234 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5235 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5238 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5241 /* If it is used for some other input, can't use it. */
5242 for (i
= 0; i
< reload_n_operands
; i
++)
5243 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5246 /* If it is used in a later operand's address, can't use it. */
5247 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5248 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5249 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5254 case RELOAD_FOR_INPUT_ADDRESS
:
5255 /* Can't use a register if it is used for an input address for this
5256 operand or used as an input in an earlier one. */
5257 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5258 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5261 for (i
= 0; i
< opnum
; i
++)
5262 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5267 case RELOAD_FOR_INPADDR_ADDRESS
:
5268 /* Can't use a register if it is used for an input address
5269 for this operand or used as an input in an earlier
5271 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5274 for (i
= 0; i
< opnum
; i
++)
5275 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5280 case RELOAD_FOR_OUTPUT_ADDRESS
:
5281 /* Can't use a register if it is used for an output address for this
5282 operand or used as an output in this or a later operand. Note
5283 that multiple output operands are emitted in reverse order, so
5284 the conflicting ones are those with lower indices. */
5285 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5288 for (i
= 0; i
<= opnum
; i
++)
5289 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5294 case RELOAD_FOR_OUTADDR_ADDRESS
:
5295 /* Can't use a register if it is used for an output address
5296 for this operand or used as an output in this or a
5297 later operand. Note that multiple output operands are
5298 emitted in reverse order, so the conflicting ones are
5299 those with lower indices. */
5300 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5303 for (i
= 0; i
<= opnum
; i
++)
5304 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5309 case RELOAD_FOR_OPERAND_ADDRESS
:
5310 for (i
= 0; i
< reload_n_operands
; i
++)
5311 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5314 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5315 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5317 case RELOAD_FOR_OPADDR_ADDR
:
5318 for (i
= 0; i
< reload_n_operands
; i
++)
5319 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5322 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5324 case RELOAD_FOR_OUTPUT
:
5325 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5326 outputs, or an operand address for this or an earlier output.
5327 Note that multiple output operands are emitted in reverse order,
5328 so the conflicting ones are those with higher indices. */
5329 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5332 for (i
= 0; i
< reload_n_operands
; i
++)
5333 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5336 for (i
= opnum
; i
< reload_n_operands
; i
++)
5337 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5338 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5343 case RELOAD_FOR_INSN
:
5344 for (i
= 0; i
< reload_n_operands
; i
++)
5345 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5346 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5349 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5350 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5352 case RELOAD_FOR_OTHER_ADDRESS
:
5353 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5360 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5361 the number RELOADNUM, is still available in REGNO at the end of the insn.
5363 We can assume that the reload reg was already tested for availability
5364 at the time it is needed, and we should not check this again,
5365 in case the reg has already been marked in use. */
5368 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5370 int opnum
= rld
[reloadnum
].opnum
;
5371 enum reload_type type
= rld
[reloadnum
].when_needed
;
5374 /* See if there is a reload with the same type for this operand, using
5375 the same register. This case is not handled by the code below. */
5376 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5381 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5383 reg
= rld
[i
].reg_rtx
;
5384 if (reg
== NULL_RTX
)
5386 nregs
= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)];
5387 if (regno
>= REGNO (reg
) && regno
< REGNO (reg
) + nregs
)
5394 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5395 its value must reach the end. */
5398 /* If this use is for part of the insn,
5399 its value reaches if no subsequent part uses the same register.
5400 Just like the above function, don't try to do this with lots
5403 case RELOAD_FOR_OTHER_ADDRESS
:
5404 /* Here we check for everything else, since these don't conflict
5405 with anything else and everything comes later. */
5407 for (i
= 0; i
< reload_n_operands
; i
++)
5408 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5409 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5410 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5411 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5412 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5413 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5416 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5417 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5418 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5419 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5421 case RELOAD_FOR_INPUT_ADDRESS
:
5422 case RELOAD_FOR_INPADDR_ADDRESS
:
5423 /* Similar, except that we check only for this and subsequent inputs
5424 and the address of only subsequent inputs and we do not need
5425 to check for RELOAD_OTHER objects since they are known not to
5428 for (i
= opnum
; i
< reload_n_operands
; i
++)
5429 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5432 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5433 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5434 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5437 for (i
= 0; i
< reload_n_operands
; i
++)
5438 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5439 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5440 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5443 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5446 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5447 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5448 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5450 case RELOAD_FOR_INPUT
:
5451 /* Similar to input address, except we start at the next operand for
5452 both input and input address and we do not check for
5453 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5456 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5457 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5458 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5459 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5462 /* ... fall through ... */
5464 case RELOAD_FOR_OPERAND_ADDRESS
:
5465 /* Check outputs and their addresses. */
5467 for (i
= 0; i
< reload_n_operands
; i
++)
5468 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5469 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5470 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5473 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5475 case RELOAD_FOR_OPADDR_ADDR
:
5476 for (i
= 0; i
< reload_n_operands
; i
++)
5477 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5478 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5479 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5482 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5483 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5484 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5486 case RELOAD_FOR_INSN
:
5487 /* These conflict with other outputs with RELOAD_OTHER. So
5488 we need only check for output addresses. */
5490 opnum
= reload_n_operands
;
5492 /* ... fall through ... */
5494 case RELOAD_FOR_OUTPUT
:
5495 case RELOAD_FOR_OUTPUT_ADDRESS
:
5496 case RELOAD_FOR_OUTADDR_ADDRESS
:
5497 /* We already know these can't conflict with a later output. So the
5498 only thing to check are later output addresses.
5499 Note that multiple output operands are emitted in reverse order,
5500 so the conflicting ones are those with lower indices. */
5501 for (i
= 0; i
< opnum
; i
++)
5502 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5503 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5513 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5514 every register in REG. */
5517 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5521 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5522 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5528 /* Returns whether R1 and R2 are uniquely chained: the value of one
5529 is used by the other, and that value is not used by any other
5530 reload for this insn. This is used to partially undo the decision
5531 made in find_reloads when in the case of multiple
5532 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5533 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5534 reloads. This code tries to avoid the conflict created by that
5535 change. It might be cleaner to explicitly keep track of which
5536 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5537 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5538 this after the fact. */
5540 reloads_unique_chain_p (int r1
, int r2
)
5544 /* We only check input reloads. */
5545 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5548 /* Avoid anything with output reloads. */
5549 if (rld
[r1
].out
|| rld
[r2
].out
)
5552 /* "chained" means one reload is a component of the other reload,
5553 not the same as the other reload. */
5554 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5555 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5556 || rld
[r1
].optional
|| rld
[r2
].optional
5557 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5558 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5561 for (i
= 0; i
< n_reloads
; i
++)
5562 /* Look for input reloads that aren't our two */
5563 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5565 /* If our reload is mentioned at all, it isn't a simple chain. */
5566 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5572 /* The recursive function change all occurrences of WHAT in *WHERE
5575 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5584 if (*where
== what
|| rtx_equal_p (*where
, what
))
5586 /* Record the location of the changed rtx. */
5587 VEC_safe_push (rtx_p
, heap
, substitute_stack
, where
);
5592 code
= GET_CODE (*where
);
5593 fmt
= GET_RTX_FORMAT (code
);
5594 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5600 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5601 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5603 else if (fmt
[i
] == 'e')
5604 substitute (&XEXP (*where
, i
), what
, repl
);
5608 /* The function returns TRUE if chain of reload R1 and R2 (in any
5609 order) can be evaluated without usage of intermediate register for
5610 the reload containing another reload. It is important to see
5611 gen_reload to understand what the function is trying to do. As an
5612 example, let us have reload chain
5615 r1: <something> + const
5617 and reload R2 got reload reg HR. The function returns true if
5618 there is a correct insn HR = HR + <something>. Otherwise,
5619 gen_reload will use intermediate register (and this is the reload
5620 reg for R1) to reload <something>.
5622 We need this function to find a conflict for chain reloads. In our
5623 example, if HR = HR + <something> is incorrect insn, then we cannot
5624 use HR as a reload register for R2. If we do use it then we get a
5633 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5635 /* Assume other cases in gen_reload are not possible for
5636 chain reloads or do need an intermediate hard registers. */
5640 rtx last
= get_last_insn ();
5642 /* Make r2 a component of r1. */
5643 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5649 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5650 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5651 gcc_assert (regno
>= 0);
5652 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5654 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5656 /* If IN is a paradoxical SUBREG, remove it and try to put the
5657 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5658 strip_paradoxical_subreg (&in
, &out
);
5660 if (GET_CODE (in
) == PLUS
5661 && (REG_P (XEXP (in
, 0))
5662 || GET_CODE (XEXP (in
, 0)) == SUBREG
5663 || MEM_P (XEXP (in
, 0)))
5664 && (REG_P (XEXP (in
, 1))
5665 || GET_CODE (XEXP (in
, 1)) == SUBREG
5666 || CONSTANT_P (XEXP (in
, 1))
5667 || MEM_P (XEXP (in
, 1))))
5669 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
5670 code
= recog_memoized (insn
);
5675 extract_insn (insn
);
5676 /* We want constrain operands to treat this insn strictly in
5677 its validity determination, i.e., the way it would after
5678 reload has completed. */
5679 result
= constrain_operands (1);
5682 delete_insns_since (last
);
5685 /* Restore the original value at each changed address within R1. */
5686 while (!VEC_empty (rtx_p
, substitute_stack
))
5688 rtx
*where
= VEC_pop (rtx_p
, substitute_stack
);
5689 *where
= rld
[r2
].in
;
5695 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5698 This function uses the same algorithm as reload_reg_free_p above. */
5701 reloads_conflict (int r1
, int r2
)
5703 enum reload_type r1_type
= rld
[r1
].when_needed
;
5704 enum reload_type r2_type
= rld
[r2
].when_needed
;
5705 int r1_opnum
= rld
[r1
].opnum
;
5706 int r2_opnum
= rld
[r2
].opnum
;
5708 /* RELOAD_OTHER conflicts with everything. */
5709 if (r2_type
== RELOAD_OTHER
)
5712 /* Otherwise, check conflicts differently for each type. */
5716 case RELOAD_FOR_INPUT
:
5717 return (r2_type
== RELOAD_FOR_INSN
5718 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5719 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5720 || r2_type
== RELOAD_FOR_INPUT
5721 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5722 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5723 && r2_opnum
> r1_opnum
));
5725 case RELOAD_FOR_INPUT_ADDRESS
:
5726 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5727 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5729 case RELOAD_FOR_INPADDR_ADDRESS
:
5730 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5731 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5733 case RELOAD_FOR_OUTPUT_ADDRESS
:
5734 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5735 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5737 case RELOAD_FOR_OUTADDR_ADDRESS
:
5738 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5739 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5741 case RELOAD_FOR_OPERAND_ADDRESS
:
5742 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5743 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5744 && (!reloads_unique_chain_p (r1
, r2
)
5745 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5747 case RELOAD_FOR_OPADDR_ADDR
:
5748 return (r2_type
== RELOAD_FOR_INPUT
5749 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5751 case RELOAD_FOR_OUTPUT
:
5752 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5753 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5754 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5755 && r2_opnum
>= r1_opnum
));
5757 case RELOAD_FOR_INSN
:
5758 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5759 || r2_type
== RELOAD_FOR_INSN
5760 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5762 case RELOAD_FOR_OTHER_ADDRESS
:
5763 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5773 /* Indexed by reload number, 1 if incoming value
5774 inherited from previous insns. */
5775 static char reload_inherited
[MAX_RELOADS
];
5777 /* For an inherited reload, this is the insn the reload was inherited from,
5778 if we know it. Otherwise, this is 0. */
5779 static rtx reload_inheritance_insn
[MAX_RELOADS
];
5781 /* If nonzero, this is a place to get the value of the reload,
5782 rather than using reload_in. */
5783 static rtx reload_override_in
[MAX_RELOADS
];
5785 /* For each reload, the hard register number of the register used,
5786 or -1 if we did not need a register for this reload. */
5787 static int reload_spill_index
[MAX_RELOADS
];
5789 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5790 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5792 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5793 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5795 /* Subroutine of free_for_value_p, used to check a single register.
5796 START_REGNO is the starting regno of the full reload register
5797 (possibly comprising multiple hard registers) that we are considering. */
5800 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5801 enum reload_type type
, rtx value
, rtx out
,
5802 int reloadnum
, int ignore_address_reloads
)
5805 /* Set if we see an input reload that must not share its reload register
5806 with any new earlyclobber, but might otherwise share the reload
5807 register with an output or input-output reload. */
5808 int check_earlyclobber
= 0;
5812 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5815 if (out
== const0_rtx
)
5821 /* We use some pseudo 'time' value to check if the lifetimes of the
5822 new register use would overlap with the one of a previous reload
5823 that is not read-only or uses a different value.
5824 The 'time' used doesn't have to be linear in any shape or form, just
5826 Some reload types use different 'buckets' for each operand.
5827 So there are MAX_RECOG_OPERANDS different time values for each
5829 We compute TIME1 as the time when the register for the prospective
5830 new reload ceases to be live, and TIME2 for each existing
5831 reload as the time when that the reload register of that reload
5833 Where there is little to be gained by exact lifetime calculations,
5834 we just make conservative assumptions, i.e. a longer lifetime;
5835 this is done in the 'default:' cases. */
5838 case RELOAD_FOR_OTHER_ADDRESS
:
5839 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5840 time1
= copy
? 0 : 1;
5843 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5845 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5846 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5847 respectively, to the time values for these, we get distinct time
5848 values. To get distinct time values for each operand, we have to
5849 multiply opnum by at least three. We round that up to four because
5850 multiply by four is often cheaper. */
5851 case RELOAD_FOR_INPADDR_ADDRESS
:
5852 time1
= opnum
* 4 + 2;
5854 case RELOAD_FOR_INPUT_ADDRESS
:
5855 time1
= opnum
* 4 + 3;
5857 case RELOAD_FOR_INPUT
:
5858 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5859 executes (inclusive). */
5860 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5862 case RELOAD_FOR_OPADDR_ADDR
:
5864 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5865 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5867 case RELOAD_FOR_OPERAND_ADDRESS
:
5868 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5870 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5872 case RELOAD_FOR_OUTADDR_ADDRESS
:
5873 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5875 case RELOAD_FOR_OUTPUT_ADDRESS
:
5876 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5879 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5882 for (i
= 0; i
< n_reloads
; i
++)
5884 rtx reg
= rld
[i
].reg_rtx
;
5885 if (reg
&& REG_P (reg
)
5886 && ((unsigned) regno
- true_regnum (reg
)
5887 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5890 rtx other_input
= rld
[i
].in
;
5892 /* If the other reload loads the same input value, that
5893 will not cause a conflict only if it's loading it into
5894 the same register. */
5895 if (true_regnum (reg
) != start_regno
)
5896 other_input
= NULL_RTX
;
5897 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5898 || rld
[i
].out
|| out
)
5901 switch (rld
[i
].when_needed
)
5903 case RELOAD_FOR_OTHER_ADDRESS
:
5906 case RELOAD_FOR_INPADDR_ADDRESS
:
5907 /* find_reloads makes sure that a
5908 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5909 by at most one - the first -
5910 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5911 address reload is inherited, the address address reload
5912 goes away, so we can ignore this conflict. */
5913 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5914 && ignore_address_reloads
5915 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5916 Then the address address is still needed to store
5917 back the new address. */
5918 && ! rld
[reloadnum
].out
)
5920 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5921 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5923 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5924 && ignore_address_reloads
5925 /* Unless we are reloading an auto_inc expression. */
5926 && ! rld
[reloadnum
].out
)
5928 time2
= rld
[i
].opnum
* 4 + 2;
5930 case RELOAD_FOR_INPUT_ADDRESS
:
5931 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5932 && ignore_address_reloads
5933 && ! rld
[reloadnum
].out
)
5935 time2
= rld
[i
].opnum
* 4 + 3;
5937 case RELOAD_FOR_INPUT
:
5938 time2
= rld
[i
].opnum
* 4 + 4;
5939 check_earlyclobber
= 1;
5941 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5942 == MAX_RECOG_OPERAND * 4 */
5943 case RELOAD_FOR_OPADDR_ADDR
:
5944 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5945 && ignore_address_reloads
5946 && ! rld
[reloadnum
].out
)
5948 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5950 case RELOAD_FOR_OPERAND_ADDRESS
:
5951 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5952 check_earlyclobber
= 1;
5954 case RELOAD_FOR_INSN
:
5955 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5957 case RELOAD_FOR_OUTPUT
:
5958 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5959 instruction is executed. */
5960 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5962 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5963 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5965 case RELOAD_FOR_OUTADDR_ADDRESS
:
5966 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5967 && ignore_address_reloads
5968 && ! rld
[reloadnum
].out
)
5970 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5972 case RELOAD_FOR_OUTPUT_ADDRESS
:
5973 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5976 /* If there is no conflict in the input part, handle this
5977 like an output reload. */
5978 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5980 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5981 /* Earlyclobbered outputs must conflict with inputs. */
5982 if (earlyclobber_operand_p (rld
[i
].out
))
5983 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5988 /* RELOAD_OTHER might be live beyond instruction execution,
5989 but this is not obvious when we set time2 = 1. So check
5990 here if there might be a problem with the new reload
5991 clobbering the register used by the RELOAD_OTHER. */
5999 && (! rld
[i
].in
|| rld
[i
].out
6000 || ! rtx_equal_p (other_input
, value
)))
6001 || (out
&& rld
[reloadnum
].out_reg
6002 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
6008 /* Earlyclobbered outputs must conflict with inputs. */
6009 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
6015 /* Return 1 if the value in reload reg REGNO, as used by a reload
6016 needed for the part of the insn specified by OPNUM and TYPE,
6017 may be used to load VALUE into it.
6019 MODE is the mode in which the register is used, this is needed to
6020 determine how many hard regs to test.
6022 Other read-only reloads with the same value do not conflict
6023 unless OUT is nonzero and these other reloads have to live while
6024 output reloads live.
6025 If OUT is CONST0_RTX, this is a special case: it means that the
6026 test should not be for using register REGNO as reload register, but
6027 for copying from register REGNO into the reload register.
6029 RELOADNUM is the number of the reload we want to load this value for;
6030 a reload does not conflict with itself.
6032 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6033 reloads that load an address for the very reload we are considering.
6035 The caller has to make sure that there is no conflict with the return
6039 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
6040 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
6041 int ignore_address_reloads
)
6043 int nregs
= hard_regno_nregs
[regno
][mode
];
6045 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
6046 value
, out
, reloadnum
,
6047 ignore_address_reloads
))
6052 /* Return nonzero if the rtx X is invariant over the current function. */
6053 /* ??? Actually, the places where we use this expect exactly what is
6054 tested here, and not everything that is function invariant. In
6055 particular, the frame pointer and arg pointer are special cased;
6056 pic_offset_table_rtx is not, and we must not spill these things to
6060 function_invariant_p (const_rtx x
)
6064 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
6066 if (GET_CODE (x
) == PLUS
6067 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
6068 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6073 /* Determine whether the reload reg X overlaps any rtx'es used for
6074 overriding inheritance. Return nonzero if so. */
6077 conflicts_with_override (rtx x
)
6080 for (i
= 0; i
< n_reloads
; i
++)
6081 if (reload_override_in
[i
]
6082 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6087 /* Give an error message saying we failed to find a reload for INSN,
6088 and clear out reload R. */
6090 failed_reload (rtx insn
, int r
)
6092 if (asm_noperands (PATTERN (insn
)) < 0)
6093 /* It's the compiler's fault. */
6094 fatal_insn ("could not find a spill register", insn
);
6096 /* It's the user's fault; the operand's mode and constraint
6097 don't match. Disable this reload so we don't crash in final. */
6098 error_for_asm (insn
,
6099 "%<asm%> operand constraint incompatible with operand size");
6103 rld
[r
].optional
= 1;
6104 rld
[r
].secondary_p
= 1;
6107 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6108 for reload R. If it's valid, get an rtx for it. Return nonzero if
6111 set_reload_reg (int i
, int r
)
6113 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6115 int regno ATTRIBUTE_UNUSED
;
6116 rtx reg
= spill_reg_rtx
[i
];
6118 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6119 spill_reg_rtx
[i
] = reg
6120 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6122 regno
= true_regnum (reg
);
6124 /* Detect when the reload reg can't hold the reload mode.
6125 This used to be one `if', but Sequent compiler can't handle that. */
6126 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6128 enum machine_mode test_mode
= VOIDmode
;
6130 test_mode
= GET_MODE (rld
[r
].in
);
6131 /* If rld[r].in has VOIDmode, it means we will load it
6132 in whatever mode the reload reg has: to wit, rld[r].mode.
6133 We have already tested that for validity. */
6134 /* Aside from that, we need to test that the expressions
6135 to reload from or into have modes which are valid for this
6136 reload register. Otherwise the reload insns would be invalid. */
6137 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6138 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6139 if (! (rld
[r
].out
!= 0
6140 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6142 /* The reg is OK. */
6145 /* Mark as in use for this insn the reload regs we use
6147 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6148 rld
[r
].when_needed
, rld
[r
].mode
);
6150 rld
[r
].reg_rtx
= reg
;
6151 reload_spill_index
[r
] = spill_regs
[i
];
6158 /* Find a spill register to use as a reload register for reload R.
6159 LAST_RELOAD is nonzero if this is the last reload for the insn being
6162 Set rld[R].reg_rtx to the register allocated.
6164 We return 1 if successful, or 0 if we couldn't find a spill reg and
6165 we didn't change anything. */
6168 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6173 /* If we put this reload ahead, thinking it is a group,
6174 then insist on finding a group. Otherwise we can grab a
6175 reg that some other reload needs.
6176 (That can happen when we have a 68000 DATA_OR_FP_REG
6177 which is a group of data regs or one fp reg.)
6178 We need not be so restrictive if there are no more reloads
6181 ??? Really it would be nicer to have smarter handling
6182 for that kind of reg class, where a problem like this is normal.
6183 Perhaps those classes should be avoided for reloading
6184 by use of more alternatives. */
6186 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6188 /* If we want a single register and haven't yet found one,
6189 take any reg in the right class and not in use.
6190 If we want a consecutive group, here is where we look for it.
6192 We use three passes so we can first look for reload regs to
6193 reuse, which are already in use for other reloads in this insn,
6194 and only then use additional registers which are not "bad", then
6195 finally any register.
6197 I think that maximizing reuse is needed to make sure we don't
6198 run out of reload regs. Suppose we have three reloads, and
6199 reloads A and B can share regs. These need two regs.
6200 Suppose A and B are given different regs.
6201 That leaves none for C. */
6202 for (pass
= 0; pass
< 3; pass
++)
6204 /* I is the index in spill_regs.
6205 We advance it round-robin between insns to use all spill regs
6206 equally, so that inherited reloads have a chance
6207 of leapfrogging each other. */
6211 for (count
= 0; count
< n_spills
; count
++)
6213 int rclass
= (int) rld
[r
].rclass
;
6219 regnum
= spill_regs
[i
];
6221 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6224 /* We check reload_reg_used to make sure we
6225 don't clobber the return register. */
6226 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6227 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6228 rld
[r
].when_needed
, rld
[r
].in
,
6230 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6231 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6232 /* Look first for regs to share, then for unshared. But
6233 don't share regs used for inherited reloads; they are
6234 the ones we want to preserve. */
6236 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6238 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6241 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6243 /* During the second pass we want to avoid reload registers
6244 which are "bad" for this reload. */
6246 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6249 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6250 (on 68000) got us two FP regs. If NR is 1,
6251 we would reject both of them. */
6254 /* If we need only one reg, we have already won. */
6257 /* But reject a single reg if we demand a group. */
6262 /* Otherwise check that as many consecutive regs as we need
6263 are available here. */
6266 int regno
= regnum
+ nr
- 1;
6267 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6268 && spill_reg_order
[regno
] >= 0
6269 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6270 rld
[r
].when_needed
)))
6279 /* If we found something on the current pass, omit later passes. */
6280 if (count
< n_spills
)
6284 /* We should have found a spill register by now. */
6285 if (count
>= n_spills
)
6288 /* I is the index in SPILL_REG_RTX of the reload register we are to
6289 allocate. Get an rtx for it and find its register number. */
6291 return set_reload_reg (i
, r
);
6294 /* Initialize all the tables needed to allocate reload registers.
6295 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6296 is the array we use to restore the reg_rtx field for every reload. */
6299 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6303 for (i
= 0; i
< n_reloads
; i
++)
6304 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6306 memset (reload_inherited
, 0, MAX_RELOADS
);
6307 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6308 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6310 CLEAR_HARD_REG_SET (reload_reg_used
);
6311 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6312 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6313 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6314 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6315 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6317 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6320 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6321 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6322 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6323 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6324 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6325 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6328 for (i
= 0; i
< reload_n_operands
; i
++)
6330 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6331 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6332 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6333 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6334 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6335 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6338 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6340 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6342 for (i
= 0; i
< n_reloads
; i
++)
6343 /* If we have already decided to use a certain register,
6344 don't use it in another way. */
6346 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6347 rld
[i
].when_needed
, rld
[i
].mode
);
6350 /* Assign hard reg targets for the pseudo-registers we must reload
6351 into hard regs for this insn.
6352 Also output the instructions to copy them in and out of the hard regs.
6354 For machines with register classes, we are responsible for
6355 finding a reload reg in the proper class. */
6358 choose_reload_regs (struct insn_chain
*chain
)
6360 rtx insn
= chain
->insn
;
6362 unsigned int max_group_size
= 1;
6363 enum reg_class group_class
= NO_REGS
;
6364 int pass
, win
, inheritance
;
6366 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6368 /* In order to be certain of getting the registers we need,
6369 we must sort the reloads into order of increasing register class.
6370 Then our grabbing of reload registers will parallel the process
6371 that provided the reload registers.
6373 Also note whether any of the reloads wants a consecutive group of regs.
6374 If so, record the maximum size of the group desired and what
6375 register class contains all the groups needed by this insn. */
6377 for (j
= 0; j
< n_reloads
; j
++)
6379 reload_order
[j
] = j
;
6380 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6382 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6383 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6384 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6387 reload_spill_index
[j
] = -1;
6389 if (rld
[j
].nregs
> 1)
6391 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6393 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6396 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6400 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6402 /* If -O, try first with inheritance, then turning it off.
6403 If not -O, don't do inheritance.
6404 Using inheritance when not optimizing leads to paradoxes
6405 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6406 because one side of the comparison might be inherited. */
6408 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6410 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6412 /* Process the reloads in order of preference just found.
6413 Beyond this point, subregs can be found in reload_reg_rtx.
6415 This used to look for an existing reloaded home for all of the
6416 reloads, and only then perform any new reloads. But that could lose
6417 if the reloads were done out of reg-class order because a later
6418 reload with a looser constraint might have an old home in a register
6419 needed by an earlier reload with a tighter constraint.
6421 To solve this, we make two passes over the reloads, in the order
6422 described above. In the first pass we try to inherit a reload
6423 from a previous insn. If there is a later reload that needs a
6424 class that is a proper subset of the class being processed, we must
6425 also allocate a spill register during the first pass.
6427 Then make a second pass over the reloads to allocate any reloads
6428 that haven't been given registers yet. */
6430 for (j
= 0; j
< n_reloads
; j
++)
6432 int r
= reload_order
[j
];
6433 rtx search_equiv
= NULL_RTX
;
6435 /* Ignore reloads that got marked inoperative. */
6436 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6437 && ! rld
[r
].secondary_p
)
6440 /* If find_reloads chose to use reload_in or reload_out as a reload
6441 register, we don't need to chose one. Otherwise, try even if it
6442 found one since we might save an insn if we find the value lying
6444 Try also when reload_in is a pseudo without a hard reg. */
6445 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6446 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6447 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6448 && !MEM_P (rld
[r
].in
)
6449 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6452 #if 0 /* No longer needed for correct operation.
6453 It might give better code, or might not; worth an experiment? */
6454 /* If this is an optional reload, we can't inherit from earlier insns
6455 until we are sure that any non-optional reloads have been allocated.
6456 The following code takes advantage of the fact that optional reloads
6457 are at the end of reload_order. */
6458 if (rld
[r
].optional
!= 0)
6459 for (i
= 0; i
< j
; i
++)
6460 if ((rld
[reload_order
[i
]].out
!= 0
6461 || rld
[reload_order
[i
]].in
!= 0
6462 || rld
[reload_order
[i
]].secondary_p
)
6463 && ! rld
[reload_order
[i
]].optional
6464 && rld
[reload_order
[i
]].reg_rtx
== 0)
6465 allocate_reload_reg (chain
, reload_order
[i
], 0);
6468 /* First see if this pseudo is already available as reloaded
6469 for a previous insn. We cannot try to inherit for reloads
6470 that are smaller than the maximum number of registers needed
6471 for groups unless the register we would allocate cannot be used
6474 We could check here to see if this is a secondary reload for
6475 an object that is already in a register of the desired class.
6476 This would avoid the need for the secondary reload register.
6477 But this is complex because we can't easily determine what
6478 objects might want to be loaded via this reload. So let a
6479 register be allocated here. In `emit_reload_insns' we suppress
6480 one of the loads in the case described above. */
6486 enum machine_mode mode
= VOIDmode
;
6490 else if (REG_P (rld
[r
].in
))
6492 regno
= REGNO (rld
[r
].in
);
6493 mode
= GET_MODE (rld
[r
].in
);
6495 else if (REG_P (rld
[r
].in_reg
))
6497 regno
= REGNO (rld
[r
].in_reg
);
6498 mode
= GET_MODE (rld
[r
].in_reg
);
6500 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6501 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6503 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6504 if (regno
< FIRST_PSEUDO_REGISTER
)
6505 regno
= subreg_regno (rld
[r
].in_reg
);
6507 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
6508 mode
= GET_MODE (rld
[r
].in_reg
);
6511 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6512 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6514 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6515 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6516 rld
[r
].out
= rld
[r
].in
;
6520 /* This won't work, since REGNO can be a pseudo reg number.
6521 Also, it takes much more hair to keep track of all the things
6522 that can invalidate an inherited reload of part of a pseudoreg. */
6523 else if (GET_CODE (rld
[r
].in
) == SUBREG
6524 && REG_P (SUBREG_REG (rld
[r
].in
)))
6525 regno
= subreg_regno (rld
[r
].in
);
6529 && reg_last_reload_reg
[regno
] != 0
6530 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
6531 >= GET_MODE_SIZE (mode
) + byte
)
6532 #ifdef CANNOT_CHANGE_MODE_CLASS
6533 /* Verify that the register it's in can be used in
6535 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6536 GET_MODE (reg_last_reload_reg
[regno
]),
6541 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6542 rtx last_reg
= reg_last_reload_reg
[regno
];
6544 i
= REGNO (last_reg
);
6545 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6546 last_class
= REGNO_REG_CLASS (i
);
6548 if (reg_reloaded_contents
[i
] == regno
6549 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6550 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6551 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6552 /* Even if we can't use this register as a reload
6553 register, we might use it for reload_override_in,
6554 if copying it to the desired class is cheap
6556 || ((register_move_cost (mode
, last_class
, rclass
)
6557 < memory_move_cost (mode
, rclass
, true))
6558 && (secondary_reload_class (1, rclass
, mode
,
6561 #ifdef SECONDARY_MEMORY_NEEDED
6562 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6567 && (rld
[r
].nregs
== max_group_size
6568 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6570 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6571 rld
[r
].when_needed
, rld
[r
].in
,
6574 /* If a group is needed, verify that all the subsequent
6575 registers still have their values intact. */
6576 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6579 for (k
= 1; k
< nr
; k
++)
6580 if (reg_reloaded_contents
[i
+ k
] != regno
6581 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6589 last_reg
= (GET_MODE (last_reg
) == mode
6590 ? last_reg
: gen_rtx_REG (mode
, i
));
6593 for (k
= 0; k
< nr
; k
++)
6594 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6597 /* We found a register that contains the
6598 value we need. If this register is the
6599 same as an `earlyclobber' operand of the
6600 current insn, just mark it as a place to
6601 reload from since we can't use it as the
6602 reload register itself. */
6604 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6605 if (reg_overlap_mentioned_for_reload_p
6606 (reg_last_reload_reg
[regno
],
6607 reload_earlyclobbers
[i1
]))
6610 if (i1
!= n_earlyclobbers
6611 || ! (free_for_value_p (i
, rld
[r
].mode
,
6613 rld
[r
].when_needed
, rld
[r
].in
,
6615 /* Don't use it if we'd clobber a pseudo reg. */
6616 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6618 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6619 /* Don't clobber the frame pointer. */
6620 || (i
== HARD_FRAME_POINTER_REGNUM
6621 && frame_pointer_needed
6623 /* Don't really use the inherited spill reg
6624 if we need it wider than we've got it. */
6625 || (GET_MODE_SIZE (rld
[r
].mode
)
6626 > GET_MODE_SIZE (mode
))
6629 /* If find_reloads chose reload_out as reload
6630 register, stay with it - that leaves the
6631 inherited register for subsequent reloads. */
6632 || (rld
[r
].out
&& rld
[r
].reg_rtx
6633 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6635 if (! rld
[r
].optional
)
6637 reload_override_in
[r
] = last_reg
;
6638 reload_inheritance_insn
[r
]
6639 = reg_reloaded_insn
[i
];
6645 /* We can use this as a reload reg. */
6646 /* Mark the register as in use for this part of
6648 mark_reload_reg_in_use (i
,
6652 rld
[r
].reg_rtx
= last_reg
;
6653 reload_inherited
[r
] = 1;
6654 reload_inheritance_insn
[r
]
6655 = reg_reloaded_insn
[i
];
6656 reload_spill_index
[r
] = i
;
6657 for (k
= 0; k
< nr
; k
++)
6658 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6666 /* Here's another way to see if the value is already lying around. */
6669 && ! reload_inherited
[r
]
6671 && (CONSTANT_P (rld
[r
].in
)
6672 || GET_CODE (rld
[r
].in
) == PLUS
6673 || REG_P (rld
[r
].in
)
6674 || MEM_P (rld
[r
].in
))
6675 && (rld
[r
].nregs
== max_group_size
6676 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6677 search_equiv
= rld
[r
].in
;
6682 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6683 -1, NULL
, 0, rld
[r
].mode
);
6689 regno
= REGNO (equiv
);
6692 /* This must be a SUBREG of a hard register.
6693 Make a new REG since this might be used in an
6694 address and not all machines support SUBREGs
6696 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6697 regno
= subreg_regno (equiv
);
6698 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6699 /* If we choose EQUIV as the reload register, but the
6700 loop below decides to cancel the inheritance, we'll
6701 end up reloading EQUIV in rld[r].mode, not the mode
6702 it had originally. That isn't safe when EQUIV isn't
6703 available as a spill register since its value might
6704 still be live at this point. */
6705 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6706 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6711 /* If we found a spill reg, reject it unless it is free
6712 and of the desired class. */
6716 int bad_for_class
= 0;
6717 int max_regno
= regno
+ rld
[r
].nregs
;
6719 for (i
= regno
; i
< max_regno
; i
++)
6721 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6723 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6728 && ! free_for_value_p (regno
, rld
[r
].mode
,
6729 rld
[r
].opnum
, rld
[r
].when_needed
,
6730 rld
[r
].in
, rld
[r
].out
, r
, 1))
6735 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6738 /* We found a register that contains the value we need.
6739 If this register is the same as an `earlyclobber' operand
6740 of the current insn, just mark it as a place to reload from
6741 since we can't use it as the reload register itself. */
6744 for (i
= 0; i
< n_earlyclobbers
; i
++)
6745 if (reg_overlap_mentioned_for_reload_p (equiv
,
6746 reload_earlyclobbers
[i
]))
6748 if (! rld
[r
].optional
)
6749 reload_override_in
[r
] = equiv
;
6754 /* If the equiv register we have found is explicitly clobbered
6755 in the current insn, it depends on the reload type if we
6756 can use it, use it for reload_override_in, or not at all.
6757 In particular, we then can't use EQUIV for a
6758 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6762 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6763 switch (rld
[r
].when_needed
)
6765 case RELOAD_FOR_OTHER_ADDRESS
:
6766 case RELOAD_FOR_INPADDR_ADDRESS
:
6767 case RELOAD_FOR_INPUT_ADDRESS
:
6768 case RELOAD_FOR_OPADDR_ADDR
:
6771 case RELOAD_FOR_INPUT
:
6772 case RELOAD_FOR_OPERAND_ADDRESS
:
6773 if (! rld
[r
].optional
)
6774 reload_override_in
[r
] = equiv
;
6780 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6781 switch (rld
[r
].when_needed
)
6783 case RELOAD_FOR_OTHER_ADDRESS
:
6784 case RELOAD_FOR_INPADDR_ADDRESS
:
6785 case RELOAD_FOR_INPUT_ADDRESS
:
6786 case RELOAD_FOR_OPADDR_ADDR
:
6787 case RELOAD_FOR_OPERAND_ADDRESS
:
6788 case RELOAD_FOR_INPUT
:
6791 if (! rld
[r
].optional
)
6792 reload_override_in
[r
] = equiv
;
6800 /* If we found an equivalent reg, say no code need be generated
6801 to load it, and use it as our reload reg. */
6803 && (regno
!= HARD_FRAME_POINTER_REGNUM
6804 || !frame_pointer_needed
))
6806 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6808 rld
[r
].reg_rtx
= equiv
;
6809 reload_spill_index
[r
] = regno
;
6810 reload_inherited
[r
] = 1;
6812 /* If reg_reloaded_valid is not set for this register,
6813 there might be a stale spill_reg_store lying around.
6814 We must clear it, since otherwise emit_reload_insns
6815 might delete the store. */
6816 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6817 spill_reg_store
[regno
] = NULL_RTX
;
6818 /* If any of the hard registers in EQUIV are spill
6819 registers, mark them as in use for this insn. */
6820 for (k
= 0; k
< nr
; k
++)
6822 i
= spill_reg_order
[regno
+ k
];
6825 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6828 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6835 /* If we found a register to use already, or if this is an optional
6836 reload, we are done. */
6837 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6841 /* No longer needed for correct operation. Might or might
6842 not give better code on the average. Want to experiment? */
6844 /* See if there is a later reload that has a class different from our
6845 class that intersects our class or that requires less register
6846 than our reload. If so, we must allocate a register to this
6847 reload now, since that reload might inherit a previous reload
6848 and take the only available register in our class. Don't do this
6849 for optional reloads since they will force all previous reloads
6850 to be allocated. Also don't do this for reloads that have been
6853 for (i
= j
+ 1; i
< n_reloads
; i
++)
6855 int s
= reload_order
[i
];
6857 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6858 && ! rld
[s
].secondary_p
)
6862 if ((rld
[s
].rclass
!= rld
[r
].rclass
6863 && reg_classes_intersect_p (rld
[r
].rclass
,
6865 || rld
[s
].nregs
< rld
[r
].nregs
)
6872 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6876 /* Now allocate reload registers for anything non-optional that
6877 didn't get one yet. */
6878 for (j
= 0; j
< n_reloads
; j
++)
6880 int r
= reload_order
[j
];
6882 /* Ignore reloads that got marked inoperative. */
6883 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6886 /* Skip reloads that already have a register allocated or are
6888 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6891 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6895 /* If that loop got all the way, we have won. */
6902 /* Loop around and try without any inheritance. */
6907 /* First undo everything done by the failed attempt
6908 to allocate with inheritance. */
6909 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6911 /* Some sanity tests to verify that the reloads found in the first
6912 pass are identical to the ones we have now. */
6913 gcc_assert (chain
->n_reloads
== n_reloads
);
6915 for (i
= 0; i
< n_reloads
; i
++)
6917 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6919 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6920 for (j
= 0; j
< n_spills
; j
++)
6921 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6922 if (! set_reload_reg (j
, i
))
6923 failed_reload (chain
->insn
, i
);
6927 /* If we thought we could inherit a reload, because it seemed that
6928 nothing else wanted the same reload register earlier in the insn,
6929 verify that assumption, now that all reloads have been assigned.
6930 Likewise for reloads where reload_override_in has been set. */
6932 /* If doing expensive optimizations, do one preliminary pass that doesn't
6933 cancel any inheritance, but removes reloads that have been needed only
6934 for reloads that we know can be inherited. */
6935 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6937 for (j
= 0; j
< n_reloads
; j
++)
6939 int r
= reload_order
[j
];
6941 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6942 check_reg
= rld
[r
].reg_rtx
;
6943 else if (reload_override_in
[r
]
6944 && (REG_P (reload_override_in
[r
])
6945 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6946 check_reg
= reload_override_in
[r
];
6949 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6950 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6951 (reload_inherited
[r
]
6952 ? rld
[r
].out
: const0_rtx
),
6957 reload_inherited
[r
] = 0;
6958 reload_override_in
[r
] = 0;
6960 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6961 reload_override_in, then we do not need its related
6962 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6963 likewise for other reload types.
6964 We handle this by removing a reload when its only replacement
6965 is mentioned in reload_in of the reload we are going to inherit.
6966 A special case are auto_inc expressions; even if the input is
6967 inherited, we still need the address for the output. We can
6968 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6969 If we succeeded removing some reload and we are doing a preliminary
6970 pass just to remove such reloads, make another pass, since the
6971 removal of one reload might allow us to inherit another one. */
6973 && rld
[r
].out
!= rld
[r
].in
6974 && remove_address_replacements (rld
[r
].in
) && pass
)
6979 /* Now that reload_override_in is known valid,
6980 actually override reload_in. */
6981 for (j
= 0; j
< n_reloads
; j
++)
6982 if (reload_override_in
[j
])
6983 rld
[j
].in
= reload_override_in
[j
];
6985 /* If this reload won't be done because it has been canceled or is
6986 optional and not inherited, clear reload_reg_rtx so other
6987 routines (such as subst_reloads) don't get confused. */
6988 for (j
= 0; j
< n_reloads
; j
++)
6989 if (rld
[j
].reg_rtx
!= 0
6990 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
6991 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
6992 && ! rld
[j
].secondary_p
)))
6994 int regno
= true_regnum (rld
[j
].reg_rtx
);
6996 if (spill_reg_order
[regno
] >= 0)
6997 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
6998 rld
[j
].when_needed
, rld
[j
].mode
);
7000 reload_spill_index
[j
] = -1;
7003 /* Record which pseudos and which spill regs have output reloads. */
7004 for (j
= 0; j
< n_reloads
; j
++)
7006 int r
= reload_order
[j
];
7008 i
= reload_spill_index
[r
];
7010 /* I is nonneg if this reload uses a register.
7011 If rld[r].reg_rtx is 0, this is an optional reload
7012 that we opted to ignore. */
7013 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7014 && rld
[r
].reg_rtx
!= 0)
7016 int nregno
= REGNO (rld
[r
].out_reg
);
7019 if (nregno
< FIRST_PSEUDO_REGISTER
)
7020 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
7023 SET_REGNO_REG_SET (®_has_output_reload
,
7027 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7029 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7030 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7031 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7036 /* Deallocate the reload register for reload R. This is called from
7037 remove_address_replacements. */
7040 deallocate_reload_reg (int r
)
7044 if (! rld
[r
].reg_rtx
)
7046 regno
= true_regnum (rld
[r
].reg_rtx
);
7048 if (spill_reg_order
[regno
] >= 0)
7049 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7051 reload_spill_index
[r
] = -1;
7054 /* These arrays are filled by emit_reload_insns and its subroutines. */
7055 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
7056 static rtx other_input_address_reload_insns
= 0;
7057 static rtx other_input_reload_insns
= 0;
7058 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7059 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7060 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
7061 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7062 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7063 static rtx operand_reload_insns
= 0;
7064 static rtx other_operand_reload_insns
= 0;
7065 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7067 /* Values to be put in spill_reg_store are put here first. Instructions
7068 must only be placed here if the associated reload register reaches
7069 the end of the instruction's reload sequence. */
7070 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7071 static HARD_REG_SET reg_reloaded_died
;
7073 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7074 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7075 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7076 adjusted register, and return true. Otherwise, return false. */
7078 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7079 enum reg_class new_class
,
7080 enum machine_mode new_mode
)
7085 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7087 unsigned regno
= REGNO (reg
);
7089 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7091 if (GET_MODE (reg
) != new_mode
)
7093 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7095 if (hard_regno_nregs
[regno
][new_mode
]
7096 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7098 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7106 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7107 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7108 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7109 adjusted register, and return true. Otherwise, return false. */
7111 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7112 enum insn_code icode
)
7115 enum reg_class new_class
= scratch_reload_class (icode
);
7116 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7118 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7119 new_class
, new_mode
);
7122 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7123 has the number J. OLD contains the value to be used as input. */
7126 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7129 rtx insn
= chain
->insn
;
7131 rtx oldequiv_reg
= 0;
7134 enum machine_mode mode
;
7137 /* delete_output_reload is only invoked properly if old contains
7138 the original pseudo register. Since this is replaced with a
7139 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7140 find the pseudo in RELOAD_IN_REG. */
7141 if (reload_override_in
[j
]
7142 && REG_P (rl
->in_reg
))
7149 else if (REG_P (oldequiv
))
7150 oldequiv_reg
= oldequiv
;
7151 else if (GET_CODE (oldequiv
) == SUBREG
)
7152 oldequiv_reg
= SUBREG_REG (oldequiv
);
7154 reloadreg
= reload_reg_rtx_for_input
[j
];
7155 mode
= GET_MODE (reloadreg
);
7157 /* If we are reloading from a register that was recently stored in
7158 with an output-reload, see if we can prove there was
7159 actually no need to store the old value in it. */
7161 if (optimize
&& REG_P (oldequiv
)
7162 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7163 && spill_reg_store
[REGNO (oldequiv
)]
7165 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7166 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7168 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7170 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7173 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7174 oldequiv
= SUBREG_REG (oldequiv
);
7175 if (GET_MODE (oldequiv
) != VOIDmode
7176 && mode
!= GET_MODE (oldequiv
))
7177 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7179 /* Switch to the right place to emit the reload insns. */
7180 switch (rl
->when_needed
)
7183 where
= &other_input_reload_insns
;
7185 case RELOAD_FOR_INPUT
:
7186 where
= &input_reload_insns
[rl
->opnum
];
7188 case RELOAD_FOR_INPUT_ADDRESS
:
7189 where
= &input_address_reload_insns
[rl
->opnum
];
7191 case RELOAD_FOR_INPADDR_ADDRESS
:
7192 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7194 case RELOAD_FOR_OUTPUT_ADDRESS
:
7195 where
= &output_address_reload_insns
[rl
->opnum
];
7197 case RELOAD_FOR_OUTADDR_ADDRESS
:
7198 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7200 case RELOAD_FOR_OPERAND_ADDRESS
:
7201 where
= &operand_reload_insns
;
7203 case RELOAD_FOR_OPADDR_ADDR
:
7204 where
= &other_operand_reload_insns
;
7206 case RELOAD_FOR_OTHER_ADDRESS
:
7207 where
= &other_input_address_reload_insns
;
7213 push_to_sequence (*where
);
7215 /* Auto-increment addresses must be reloaded in a special way. */
7216 if (rl
->out
&& ! rl
->out_reg
)
7218 /* We are not going to bother supporting the case where a
7219 incremented register can't be copied directly from
7220 OLDEQUIV since this seems highly unlikely. */
7221 gcc_assert (rl
->secondary_in_reload
< 0);
7223 if (reload_inherited
[j
])
7224 oldequiv
= reloadreg
;
7226 old
= XEXP (rl
->in_reg
, 0);
7228 /* Prevent normal processing of this reload. */
7230 /* Output a special code sequence for this case. */
7231 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7234 /* If we are reloading a pseudo-register that was set by the previous
7235 insn, see if we can get rid of that pseudo-register entirely
7236 by redirecting the previous insn into our reload register. */
7238 else if (optimize
&& REG_P (old
)
7239 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7240 && dead_or_set_p (insn
, old
)
7241 /* This is unsafe if some other reload
7242 uses the same reg first. */
7243 && ! conflicts_with_override (reloadreg
)
7244 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7245 rl
->when_needed
, old
, rl
->out
, j
, 0))
7247 rtx temp
= PREV_INSN (insn
);
7248 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7249 temp
= PREV_INSN (temp
);
7251 && NONJUMP_INSN_P (temp
)
7252 && GET_CODE (PATTERN (temp
)) == SET
7253 && SET_DEST (PATTERN (temp
)) == old
7254 /* Make sure we can access insn_operand_constraint. */
7255 && asm_noperands (PATTERN (temp
)) < 0
7256 /* This is unsafe if operand occurs more than once in current
7257 insn. Perhaps some occurrences aren't reloaded. */
7258 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7260 rtx old
= SET_DEST (PATTERN (temp
));
7261 /* Store into the reload register instead of the pseudo. */
7262 SET_DEST (PATTERN (temp
)) = reloadreg
;
7264 /* Verify that resulting insn is valid. */
7265 extract_insn (temp
);
7266 if (constrain_operands (1))
7268 /* If the previous insn is an output reload, the source is
7269 a reload register, and its spill_reg_store entry will
7270 contain the previous destination. This is now
7272 if (REG_P (SET_SRC (PATTERN (temp
)))
7273 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7275 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7276 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7279 /* If these are the only uses of the pseudo reg,
7280 pretend for GDB it lives in the reload reg we used. */
7281 if (REG_N_DEATHS (REGNO (old
)) == 1
7282 && REG_N_SETS (REGNO (old
)) == 1)
7284 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7285 if (ira_conflicts_p
)
7286 /* Inform IRA about the change. */
7287 ira_mark_allocation_change (REGNO (old
));
7288 alter_reg (REGNO (old
), -1, false);
7292 /* Adjust any debug insns between temp and insn. */
7293 while ((temp
= NEXT_INSN (temp
)) != insn
)
7294 if (DEBUG_INSN_P (temp
))
7295 replace_rtx (PATTERN (temp
), old
, reloadreg
);
7297 gcc_assert (NOTE_P (temp
));
7301 SET_DEST (PATTERN (temp
)) = old
;
7306 /* We can't do that, so output an insn to load RELOADREG. */
7308 /* If we have a secondary reload, pick up the secondary register
7309 and icode, if any. If OLDEQUIV and OLD are different or
7310 if this is an in-out reload, recompute whether or not we
7311 still need a secondary register and what the icode should
7312 be. If we still need a secondary register and the class or
7313 icode is different, go back to reloading from OLD if using
7314 OLDEQUIV means that we got the wrong type of register. We
7315 cannot have different class or icode due to an in-out reload
7316 because we don't make such reloads when both the input and
7317 output need secondary reload registers. */
7319 if (! special
&& rl
->secondary_in_reload
>= 0)
7321 rtx second_reload_reg
= 0;
7322 rtx third_reload_reg
= 0;
7323 int secondary_reload
= rl
->secondary_in_reload
;
7324 rtx real_oldequiv
= oldequiv
;
7327 enum insn_code icode
;
7328 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7330 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7331 and similarly for OLD.
7332 See comments in get_secondary_reload in reload.c. */
7333 /* If it is a pseudo that cannot be replaced with its
7334 equivalent MEM, we must fall back to reload_in, which
7335 will have all the necessary substitutions registered.
7336 Likewise for a pseudo that can't be replaced with its
7337 equivalent constant.
7339 Take extra care for subregs of such pseudos. Note that
7340 we cannot use reg_equiv_mem in this case because it is
7341 not in the right mode. */
7344 if (GET_CODE (tmp
) == SUBREG
)
7345 tmp
= SUBREG_REG (tmp
);
7347 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7348 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7349 || reg_equiv_constant (REGNO (tmp
)) != 0))
7351 if (! reg_equiv_mem (REGNO (tmp
))
7352 || num_not_at_initial_offset
7353 || GET_CODE (oldequiv
) == SUBREG
)
7354 real_oldequiv
= rl
->in
;
7356 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7360 if (GET_CODE (tmp
) == SUBREG
)
7361 tmp
= SUBREG_REG (tmp
);
7363 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7364 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7365 || reg_equiv_constant (REGNO (tmp
)) != 0))
7367 if (! reg_equiv_mem (REGNO (tmp
))
7368 || num_not_at_initial_offset
7369 || GET_CODE (old
) == SUBREG
)
7372 real_old
= reg_equiv_mem (REGNO (tmp
));
7375 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7376 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7378 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7380 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7381 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7382 /* We'd have to add more code for quartary reloads. */
7383 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7385 icode
= rl
->secondary_in_icode
;
7387 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7388 || (rl
->in
!= 0 && rl
->out
!= 0))
7390 secondary_reload_info sri
, sri2
;
7391 enum reg_class new_class
, new_t_class
;
7393 sri
.icode
= CODE_FOR_nothing
;
7394 sri
.prev_sri
= NULL
;
7396 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7400 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7401 second_reload_reg
= 0;
7402 else if (new_class
== NO_REGS
)
7404 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7406 (enum insn_code
) sri
.icode
))
7408 icode
= (enum insn_code
) sri
.icode
;
7409 third_reload_reg
= 0;
7414 real_oldequiv
= real_old
;
7417 else if (sri
.icode
!= CODE_FOR_nothing
)
7418 /* We currently lack a way to express this in reloads. */
7422 sri2
.icode
= CODE_FOR_nothing
;
7423 sri2
.prev_sri
= &sri
;
7425 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7428 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7430 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7434 third_reload_reg
= 0;
7435 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7440 real_oldequiv
= real_old
;
7443 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7445 rtx intermediate
= second_reload_reg
;
7447 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7449 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7453 second_reload_reg
= intermediate
;
7454 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7459 real_oldequiv
= real_old
;
7462 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7464 rtx intermediate
= second_reload_reg
;
7466 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7468 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7471 second_reload_reg
= intermediate
;
7472 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7477 real_oldequiv
= real_old
;
7482 /* This could be handled more intelligently too. */
7484 real_oldequiv
= real_old
;
7489 /* If we still need a secondary reload register, check
7490 to see if it is being used as a scratch or intermediate
7491 register and generate code appropriately. If we need
7492 a scratch register, use REAL_OLDEQUIV since the form of
7493 the insn may depend on the actual address if it is
7496 if (second_reload_reg
)
7498 if (icode
!= CODE_FOR_nothing
)
7500 /* We'd have to add extra code to handle this case. */
7501 gcc_assert (!third_reload_reg
);
7503 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7504 second_reload_reg
));
7509 /* See if we need a scratch register to load the
7510 intermediate register (a tertiary reload). */
7511 if (tertiary_icode
!= CODE_FOR_nothing
)
7513 emit_insn ((GEN_FCN (tertiary_icode
)
7514 (second_reload_reg
, real_oldequiv
,
7515 third_reload_reg
)));
7517 else if (third_reload_reg
)
7519 gen_reload (third_reload_reg
, real_oldequiv
,
7522 gen_reload (second_reload_reg
, third_reload_reg
,
7527 gen_reload (second_reload_reg
, real_oldequiv
,
7531 oldequiv
= second_reload_reg
;
7536 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7538 rtx real_oldequiv
= oldequiv
;
7540 if ((REG_P (oldequiv
)
7541 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7542 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7543 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7544 || (GET_CODE (oldequiv
) == SUBREG
7545 && REG_P (SUBREG_REG (oldequiv
))
7546 && (REGNO (SUBREG_REG (oldequiv
))
7547 >= FIRST_PSEUDO_REGISTER
)
7548 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7549 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7550 || (CONSTANT_P (oldequiv
)
7551 && (targetm
.preferred_reload_class (oldequiv
,
7552 REGNO_REG_CLASS (REGNO (reloadreg
)))
7554 real_oldequiv
= rl
->in
;
7555 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7559 if (cfun
->can_throw_non_call_exceptions
)
7560 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7562 /* End this sequence. */
7563 *where
= get_insns ();
7566 /* Update reload_override_in so that delete_address_reloads_1
7567 can see the actual register usage. */
7569 reload_override_in
[j
] = oldequiv
;
7572 /* Generate insns to for the output reload RL, which is for the insn described
7573 by CHAIN and has the number J. */
7575 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7579 rtx insn
= chain
->insn
;
7582 enum machine_mode mode
;
7586 if (rl
->when_needed
== RELOAD_OTHER
)
7589 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7591 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7592 mode
= GET_MODE (rl_reg_rtx
);
7594 reloadreg
= rl_reg_rtx
;
7596 /* If we need two reload regs, set RELOADREG to the intermediate
7597 one, since it will be stored into OLD. We might need a secondary
7598 register only for an input reload, so check again here. */
7600 if (rl
->secondary_out_reload
>= 0)
7603 int secondary_reload
= rl
->secondary_out_reload
;
7604 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7606 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7607 && reg_equiv_mem (REGNO (old
)) != 0)
7608 real_old
= reg_equiv_mem (REGNO (old
));
7610 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7612 rtx second_reloadreg
= reloadreg
;
7613 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7615 /* See if RELOADREG is to be used as a scratch register
7616 or as an intermediate register. */
7617 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7619 /* We'd have to add extra code to handle this case. */
7620 gcc_assert (tertiary_reload
< 0);
7622 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7623 (real_old
, second_reloadreg
, reloadreg
)));
7628 /* See if we need both a scratch and intermediate reload
7631 enum insn_code tertiary_icode
7632 = rld
[secondary_reload
].secondary_out_icode
;
7634 /* We'd have to add more code for quartary reloads. */
7635 gcc_assert (tertiary_reload
< 0
7636 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7638 if (GET_MODE (reloadreg
) != mode
)
7639 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7641 if (tertiary_icode
!= CODE_FOR_nothing
)
7643 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7645 /* Copy primary reload reg to secondary reload reg.
7646 (Note that these have been swapped above, then
7647 secondary reload reg to OLD using our insn.) */
7649 /* If REAL_OLD is a paradoxical SUBREG, remove it
7650 and try to put the opposite SUBREG on
7652 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7654 gen_reload (reloadreg
, second_reloadreg
,
7655 rl
->opnum
, rl
->when_needed
);
7656 emit_insn ((GEN_FCN (tertiary_icode
)
7657 (real_old
, reloadreg
, third_reloadreg
)));
7663 /* Copy between the reload regs here and then to
7666 gen_reload (reloadreg
, second_reloadreg
,
7667 rl
->opnum
, rl
->when_needed
);
7668 if (tertiary_reload
>= 0)
7670 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7672 gen_reload (third_reloadreg
, reloadreg
,
7673 rl
->opnum
, rl
->when_needed
);
7674 reloadreg
= third_reloadreg
;
7681 /* Output the last reload insn. */
7686 /* Don't output the last reload if OLD is not the dest of
7687 INSN and is in the src and is clobbered by INSN. */
7688 if (! flag_expensive_optimizations
7690 || !(set
= single_set (insn
))
7691 || rtx_equal_p (old
, SET_DEST (set
))
7692 || !reg_mentioned_p (old
, SET_SRC (set
))
7693 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7694 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7695 gen_reload (old
, reloadreg
, rl
->opnum
,
7699 /* Look at all insns we emitted, just to be safe. */
7700 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7703 rtx pat
= PATTERN (p
);
7705 /* If this output reload doesn't come from a spill reg,
7706 clear any memory of reloaded copies of the pseudo reg.
7707 If this output reload comes from a spill reg,
7708 reg_has_output_reload will make this do nothing. */
7709 note_stores (pat
, forget_old_reloads_1
, NULL
);
7711 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7713 rtx set
= single_set (insn
);
7714 if (reload_spill_index
[j
] < 0
7716 && SET_SRC (set
) == rl_reg_rtx
)
7718 int src
= REGNO (SET_SRC (set
));
7720 reload_spill_index
[j
] = src
;
7721 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7722 if (find_regno_note (insn
, REG_DEAD
, src
))
7723 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7725 if (HARD_REGISTER_P (rl_reg_rtx
))
7727 int s
= rl
->secondary_out_reload
;
7728 set
= single_set (p
);
7729 /* If this reload copies only to the secondary reload
7730 register, the secondary reload does the actual
7732 if (s
>= 0 && set
== NULL_RTX
)
7733 /* We can't tell what function the secondary reload
7734 has and where the actual store to the pseudo is
7735 made; leave new_spill_reg_store alone. */
7738 && SET_SRC (set
) == rl_reg_rtx
7739 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7741 /* Usually the next instruction will be the
7742 secondary reload insn; if we can confirm
7743 that it is, setting new_spill_reg_store to
7744 that insn will allow an extra optimization. */
7745 rtx s_reg
= rld
[s
].reg_rtx
;
7746 rtx next
= NEXT_INSN (p
);
7747 rld
[s
].out
= rl
->out
;
7748 rld
[s
].out_reg
= rl
->out_reg
;
7749 set
= single_set (next
);
7750 if (set
&& SET_SRC (set
) == s_reg
7751 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7753 SET_HARD_REG_BIT (reg_is_output_reload
,
7755 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7758 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7759 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7764 if (rl
->when_needed
== RELOAD_OTHER
)
7766 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7767 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7770 output_reload_insns
[rl
->opnum
] = get_insns ();
7772 if (cfun
->can_throw_non_call_exceptions
)
7773 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7778 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7779 and has the number J. */
7781 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7783 rtx insn
= chain
->insn
;
7784 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7785 ? rl
->in_reg
: rl
->in
);
7786 rtx reg_rtx
= rl
->reg_rtx
;
7790 enum machine_mode mode
;
7792 /* Determine the mode to reload in.
7793 This is very tricky because we have three to choose from.
7794 There is the mode the insn operand wants (rl->inmode).
7795 There is the mode of the reload register RELOADREG.
7796 There is the intrinsic mode of the operand, which we could find
7797 by stripping some SUBREGs.
7798 It turns out that RELOADREG's mode is irrelevant:
7799 we can change that arbitrarily.
7801 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7802 then the reload reg may not support QImode moves, so use SImode.
7803 If foo is in memory due to spilling a pseudo reg, this is safe,
7804 because the QImode value is in the least significant part of a
7805 slot big enough for a SImode. If foo is some other sort of
7806 memory reference, then it is impossible to reload this case,
7807 so previous passes had better make sure this never happens.
7809 Then consider a one-word union which has SImode and one of its
7810 members is a float, being fetched as (SUBREG:SF union:SI).
7811 We must fetch that as SFmode because we could be loading into
7812 a float-only register. In this case OLD's mode is correct.
7814 Consider an immediate integer: it has VOIDmode. Here we need
7815 to get a mode from something else.
7817 In some cases, there is a fourth mode, the operand's
7818 containing mode. If the insn specifies a containing mode for
7819 this operand, it overrides all others.
7821 I am not sure whether the algorithm here is always right,
7822 but it does the right things in those cases. */
7824 mode
= GET_MODE (old
);
7825 if (mode
== VOIDmode
)
7828 /* We cannot use gen_lowpart_common since it can do the wrong thing
7829 when REG_RTX has a multi-word mode. Note that REG_RTX must
7830 always be a REG here. */
7831 if (GET_MODE (reg_rtx
) != mode
)
7832 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7834 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7837 /* AUTO_INC reloads need to be handled even if inherited. We got an
7838 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7839 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7840 && ! rtx_equal_p (reg_rtx
, old
)
7842 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7844 /* When inheriting a wider reload, we have a MEM in rl->in,
7845 e.g. inheriting a SImode output reload for
7846 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7847 if (optimize
&& reload_inherited
[j
] && rl
->in
7849 && MEM_P (rl
->in_reg
)
7850 && reload_spill_index
[j
] >= 0
7851 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7852 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7854 /* If we are reloading a register that was recently stored in with an
7855 output-reload, see if we can prove there was
7856 actually no need to store the old value in it. */
7859 && (reload_inherited
[j
] || reload_override_in
[j
])
7862 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7864 /* There doesn't seem to be any reason to restrict this to pseudos
7865 and doing so loses in the case where we are copying from a
7866 register of the wrong class. */
7867 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7869 /* The insn might have already some references to stackslots
7870 replaced by MEMs, while reload_out_reg still names the
7872 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7873 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7874 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7877 /* Do output reloading for reload RL, which is for the insn described by
7878 CHAIN and has the number J.
7879 ??? At some point we need to support handling output reloads of
7880 JUMP_INSNs or insns that set cc0. */
7882 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7885 rtx insn
= chain
->insn
;
7886 /* If this is an output reload that stores something that is
7887 not loaded in this same reload, see if we can eliminate a previous
7889 rtx pseudo
= rl
->out_reg
;
7890 rtx reg_rtx
= rl
->reg_rtx
;
7892 if (rl
->out
&& reg_rtx
)
7894 enum machine_mode mode
;
7896 /* Determine the mode to reload in.
7897 See comments above (for input reloading). */
7898 mode
= GET_MODE (rl
->out
);
7899 if (mode
== VOIDmode
)
7901 /* VOIDmode should never happen for an output. */
7902 if (asm_noperands (PATTERN (insn
)) < 0)
7903 /* It's the compiler's fault. */
7904 fatal_insn ("VOIDmode on an output", insn
);
7905 error_for_asm (insn
, "output operand is constant in %<asm%>");
7906 /* Prevent crash--use something we know is valid. */
7908 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
7910 if (GET_MODE (reg_rtx
) != mode
)
7911 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7913 reload_reg_rtx_for_output
[j
] = reg_rtx
;
7918 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7919 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7920 && reg_last_reload_reg
[REGNO (pseudo
)])
7922 int pseudo_no
= REGNO (pseudo
);
7923 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7925 /* We don't need to test full validity of last_regno for
7926 inherit here; we only want to know if the store actually
7927 matches the pseudo. */
7928 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7929 && reg_reloaded_contents
[last_regno
] == pseudo_no
7930 && spill_reg_store
[last_regno
]
7931 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7932 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
7938 || rtx_equal_p (old
, reg_rtx
))
7941 /* An output operand that dies right away does need a reload,
7942 but need not be copied from it. Show the new location in the
7944 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7945 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7947 XEXP (note
, 0) = reg_rtx
;
7950 /* Likewise for a SUBREG of an operand that dies. */
7951 else if (GET_CODE (old
) == SUBREG
7952 && REG_P (SUBREG_REG (old
))
7953 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7956 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
7959 else if (GET_CODE (old
) == SCRATCH
)
7960 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7961 but we don't want to make an output reload. */
7964 /* If is a JUMP_INSN, we can't support output reloads yet. */
7965 gcc_assert (NONJUMP_INSN_P (insn
));
7967 emit_output_reload_insns (chain
, rld
+ j
, j
);
7970 /* A reload copies values of MODE from register SRC to register DEST.
7971 Return true if it can be treated for inheritance purposes like a
7972 group of reloads, each one reloading a single hard register. The
7973 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7974 occupy the same number of hard registers. */
7977 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
7978 int src ATTRIBUTE_UNUSED
,
7979 enum machine_mode mode ATTRIBUTE_UNUSED
)
7981 #ifdef CANNOT_CHANGE_MODE_CLASS
7982 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
7983 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
7989 /* Output insns to reload values in and out of the chosen reload regs. */
7992 emit_reload_insns (struct insn_chain
*chain
)
7994 rtx insn
= chain
->insn
;
7998 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8000 for (j
= 0; j
< reload_n_operands
; j
++)
8001 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8002 = inpaddr_address_reload_insns
[j
]
8003 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8004 = outaddr_address_reload_insns
[j
]
8005 = other_output_reload_insns
[j
] = 0;
8006 other_input_address_reload_insns
= 0;
8007 other_input_reload_insns
= 0;
8008 operand_reload_insns
= 0;
8009 other_operand_reload_insns
= 0;
8011 /* Dump reloads into the dump file. */
8014 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8015 debug_reload_to_stream (dump_file
);
8018 for (j
= 0; j
< n_reloads
; j
++)
8019 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8023 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8024 new_spill_reg_store
[i
] = 0;
8027 /* Now output the instructions to copy the data into and out of the
8028 reload registers. Do these in the order that the reloads were reported,
8029 since reloads of base and index registers precede reloads of operands
8030 and the operands may need the base and index registers reloaded. */
8032 for (j
= 0; j
< n_reloads
; j
++)
8034 do_input_reload (chain
, rld
+ j
, j
);
8035 do_output_reload (chain
, rld
+ j
, j
);
8038 /* Now write all the insns we made for reloads in the order expected by
8039 the allocation functions. Prior to the insn being reloaded, we write
8040 the following reloads:
8042 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8044 RELOAD_OTHER reloads.
8046 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8047 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8048 RELOAD_FOR_INPUT reload for the operand.
8050 RELOAD_FOR_OPADDR_ADDRS reloads.
8052 RELOAD_FOR_OPERAND_ADDRESS reloads.
8054 After the insn being reloaded, we write the following:
8056 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8057 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8058 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8059 reloads for the operand. The RELOAD_OTHER output reloads are
8060 output in descending order by reload number. */
8062 emit_insn_before (other_input_address_reload_insns
, insn
);
8063 emit_insn_before (other_input_reload_insns
, insn
);
8065 for (j
= 0; j
< reload_n_operands
; j
++)
8067 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8068 emit_insn_before (input_address_reload_insns
[j
], insn
);
8069 emit_insn_before (input_reload_insns
[j
], insn
);
8072 emit_insn_before (other_operand_reload_insns
, insn
);
8073 emit_insn_before (operand_reload_insns
, insn
);
8075 for (j
= 0; j
< reload_n_operands
; j
++)
8077 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8078 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8079 x
= emit_insn_after (output_reload_insns
[j
], x
);
8080 emit_insn_after (other_output_reload_insns
[j
], x
);
8083 /* For all the spill regs newly reloaded in this instruction,
8084 record what they were reloaded from, so subsequent instructions
8085 can inherit the reloads.
8087 Update spill_reg_store for the reloads of this insn.
8088 Copy the elements that were updated in the loop above. */
8090 for (j
= 0; j
< n_reloads
; j
++)
8092 int r
= reload_order
[j
];
8093 int i
= reload_spill_index
[r
];
8095 /* If this is a non-inherited input reload from a pseudo, we must
8096 clear any memory of a previous store to the same pseudo. Only do
8097 something if there will not be an output reload for the pseudo
8099 if (rld
[r
].in_reg
!= 0
8100 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8102 rtx reg
= rld
[r
].in_reg
;
8104 if (GET_CODE (reg
) == SUBREG
)
8105 reg
= SUBREG_REG (reg
);
8108 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8109 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8111 int nregno
= REGNO (reg
);
8113 if (reg_last_reload_reg
[nregno
])
8115 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8117 if (reg_reloaded_contents
[last_regno
] == nregno
)
8118 spill_reg_store
[last_regno
] = 0;
8123 /* I is nonneg if this reload used a register.
8124 If rld[r].reg_rtx is 0, this is an optional reload
8125 that we opted to ignore. */
8127 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8129 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8132 /* For a multi register reload, we need to check if all or part
8133 of the value lives to the end. */
8134 for (k
= 0; k
< nr
; k
++)
8135 if (reload_reg_reaches_end_p (i
+ k
, r
))
8136 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8138 /* Maybe the spill reg contains a copy of reload_out. */
8140 && (REG_P (rld
[r
].out
)
8142 ? REG_P (rld
[r
].out_reg
)
8143 /* The reload value is an auto-modification of
8144 some kind. For PRE_INC, POST_INC, PRE_DEC
8145 and POST_DEC, we record an equivalence
8146 between the reload register and the operand
8147 on the optimistic assumption that we can make
8148 the equivalence hold. reload_as_needed must
8149 then either make it hold or invalidate the
8152 PRE_MODIFY and POST_MODIFY addresses are reloaded
8153 somewhat differently, and allowing them here leads
8155 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8156 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8160 reg
= reload_reg_rtx_for_output
[r
];
8161 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8163 enum machine_mode mode
= GET_MODE (reg
);
8164 int regno
= REGNO (reg
);
8165 int nregs
= hard_regno_nregs
[regno
][mode
];
8166 rtx out
= (REG_P (rld
[r
].out
)
8170 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8171 int out_regno
= REGNO (out
);
8172 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8173 : hard_regno_nregs
[out_regno
][mode
]);
8176 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8177 spill_reg_stored_to
[regno
] = out
;
8178 reg_last_reload_reg
[out_regno
] = reg
;
8180 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8181 && nregs
== out_nregs
8182 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8184 /* If OUT_REGNO is a hard register, it may occupy more than
8185 one register. If it does, say what is in the
8186 rest of the registers assuming that both registers
8187 agree on how many words the object takes. If not,
8188 invalidate the subsequent registers. */
8190 if (HARD_REGISTER_NUM_P (out_regno
))
8191 for (k
= 1; k
< out_nregs
; k
++)
8192 reg_last_reload_reg
[out_regno
+ k
]
8193 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8195 /* Now do the inverse operation. */
8196 for (k
= 0; k
< nregs
; k
++)
8198 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8199 reg_reloaded_contents
[regno
+ k
]
8200 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8203 reg_reloaded_insn
[regno
+ k
] = insn
;
8204 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8205 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8206 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8209 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8214 /* Maybe the spill reg contains a copy of reload_in. Only do
8215 something if there will not be an output reload for
8216 the register being reloaded. */
8217 else if (rld
[r
].out_reg
== 0
8219 && ((REG_P (rld
[r
].in
)
8220 && !HARD_REGISTER_P (rld
[r
].in
)
8221 && !REGNO_REG_SET_P (®_has_output_reload
,
8223 || (REG_P (rld
[r
].in_reg
)
8224 && !REGNO_REG_SET_P (®_has_output_reload
,
8225 REGNO (rld
[r
].in_reg
))))
8226 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8230 reg
= reload_reg_rtx_for_input
[r
];
8231 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8233 enum machine_mode mode
;
8241 mode
= GET_MODE (reg
);
8242 regno
= REGNO (reg
);
8243 nregs
= hard_regno_nregs
[regno
][mode
];
8244 if (REG_P (rld
[r
].in
)
8245 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8247 else if (REG_P (rld
[r
].in_reg
))
8250 in
= XEXP (rld
[r
].in_reg
, 0);
8251 in_regno
= REGNO (in
);
8253 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8254 : hard_regno_nregs
[in_regno
][mode
]);
8256 reg_last_reload_reg
[in_regno
] = reg
;
8258 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8259 && nregs
== in_nregs
8260 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8262 if (HARD_REGISTER_NUM_P (in_regno
))
8263 for (k
= 1; k
< in_nregs
; k
++)
8264 reg_last_reload_reg
[in_regno
+ k
]
8265 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8267 /* Unless we inherited this reload, show we haven't
8268 recently done a store.
8269 Previous stores of inherited auto_inc expressions
8270 also have to be discarded. */
8271 if (! reload_inherited
[r
]
8272 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8273 spill_reg_store
[regno
] = 0;
8275 for (k
= 0; k
< nregs
; k
++)
8277 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8278 reg_reloaded_contents
[regno
+ k
]
8279 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8282 reg_reloaded_insn
[regno
+ k
] = insn
;
8283 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8284 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8285 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8288 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8295 /* The following if-statement was #if 0'd in 1.34 (or before...).
8296 It's reenabled in 1.35 because supposedly nothing else
8297 deals with this problem. */
8299 /* If a register gets output-reloaded from a non-spill register,
8300 that invalidates any previous reloaded copy of it.
8301 But forget_old_reloads_1 won't get to see it, because
8302 it thinks only about the original insn. So invalidate it here.
8303 Also do the same thing for RELOAD_OTHER constraints where the
8304 output is discarded. */
8306 && ((rld
[r
].out
!= 0
8307 && (REG_P (rld
[r
].out
)
8308 || (MEM_P (rld
[r
].out
)
8309 && REG_P (rld
[r
].out_reg
))))
8310 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8311 && REG_P (rld
[r
].out_reg
))))
8313 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8314 ? rld
[r
].out
: rld
[r
].out_reg
);
8315 int out_regno
= REGNO (out
);
8316 enum machine_mode mode
= GET_MODE (out
);
8318 /* REG_RTX is now set or clobbered by the main instruction.
8319 As the comment above explains, forget_old_reloads_1 only
8320 sees the original instruction, and there is no guarantee
8321 that the original instruction also clobbered REG_RTX.
8322 For example, if find_reloads sees that the input side of
8323 a matched operand pair dies in this instruction, it may
8324 use the input register as the reload register.
8326 Calling forget_old_reloads_1 is a waste of effort if
8327 REG_RTX is also the output register.
8329 If we know that REG_RTX holds the value of a pseudo
8330 register, the code after the call will record that fact. */
8331 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8332 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8334 if (!HARD_REGISTER_NUM_P (out_regno
))
8336 rtx src_reg
, store_insn
= NULL_RTX
;
8338 reg_last_reload_reg
[out_regno
] = 0;
8340 /* If we can find a hard register that is stored, record
8341 the storing insn so that we may delete this insn with
8342 delete_output_reload. */
8343 src_reg
= reload_reg_rtx_for_output
[r
];
8347 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8348 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8354 /* If this is an optional reload, try to find the
8355 source reg from an input reload. */
8356 rtx set
= single_set (insn
);
8357 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8361 src_reg
= SET_SRC (set
);
8363 for (k
= 0; k
< n_reloads
; k
++)
8365 if (rld
[k
].in
== src_reg
)
8367 src_reg
= reload_reg_rtx_for_input
[k
];
8373 if (src_reg
&& REG_P (src_reg
)
8374 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8376 int src_regno
, src_nregs
, k
;
8379 gcc_assert (GET_MODE (src_reg
) == mode
);
8380 src_regno
= REGNO (src_reg
);
8381 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8382 /* The place where to find a death note varies with
8383 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8384 necessarily checked exactly in the code that moves
8385 notes, so just check both locations. */
8386 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8387 if (! note
&& store_insn
)
8388 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8389 for (k
= 0; k
< src_nregs
; k
++)
8391 spill_reg_store
[src_regno
+ k
] = store_insn
;
8392 spill_reg_stored_to
[src_regno
+ k
] = out
;
8393 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8394 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8395 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8396 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8397 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8399 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8402 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8404 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8406 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8408 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8410 reg_last_reload_reg
[out_regno
] = src_reg
;
8411 /* We have to set reg_has_output_reload here, or else
8412 forget_old_reloads_1 will clear reg_last_reload_reg
8414 SET_REGNO_REG_SET (®_has_output_reload
,
8420 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8422 for (k
= 0; k
< out_nregs
; k
++)
8423 reg_last_reload_reg
[out_regno
+ k
] = 0;
8427 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8430 /* Go through the motions to emit INSN and test if it is strictly valid.
8431 Return the emitted insn if valid, else return NULL. */
8434 emit_insn_if_valid_for_reload (rtx insn
)
8436 rtx last
= get_last_insn ();
8439 insn
= emit_insn (insn
);
8440 code
= recog_memoized (insn
);
8444 extract_insn (insn
);
8445 /* We want constrain operands to treat this insn strictly in its
8446 validity determination, i.e., the way it would after reload has
8448 if (constrain_operands (1))
8452 delete_insns_since (last
);
8456 /* Emit code to perform a reload from IN (which may be a reload register) to
8457 OUT (which may also be a reload register). IN or OUT is from operand
8458 OPNUM with reload type TYPE.
8460 Returns first insn emitted. */
8463 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8465 rtx last
= get_last_insn ();
8468 /* If IN is a paradoxical SUBREG, remove it and try to put the
8469 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8470 if (!strip_paradoxical_subreg (&in
, &out
))
8471 strip_paradoxical_subreg (&out
, &in
);
8473 /* How to do this reload can get quite tricky. Normally, we are being
8474 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8475 register that didn't get a hard register. In that case we can just
8476 call emit_move_insn.
8478 We can also be asked to reload a PLUS that adds a register or a MEM to
8479 another register, constant or MEM. This can occur during frame pointer
8480 elimination and while reloading addresses. This case is handled by
8481 trying to emit a single insn to perform the add. If it is not valid,
8482 we use a two insn sequence.
8484 Or we can be asked to reload an unary operand that was a fragment of
8485 an addressing mode, into a register. If it isn't recognized as-is,
8486 we try making the unop operand and the reload-register the same:
8487 (set reg:X (unop:X expr:Y))
8488 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8490 Finally, we could be called to handle an 'o' constraint by putting
8491 an address into a register. In that case, we first try to do this
8492 with a named pattern of "reload_load_address". If no such pattern
8493 exists, we just emit a SET insn and hope for the best (it will normally
8494 be valid on machines that use 'o').
8496 This entire process is made complex because reload will never
8497 process the insns we generate here and so we must ensure that
8498 they will fit their constraints and also by the fact that parts of
8499 IN might be being reloaded separately and replaced with spill registers.
8500 Because of this, we are, in some sense, just guessing the right approach
8501 here. The one listed above seems to work.
8503 ??? At some point, this whole thing needs to be rethought. */
8505 if (GET_CODE (in
) == PLUS
8506 && (REG_P (XEXP (in
, 0))
8507 || GET_CODE (XEXP (in
, 0)) == SUBREG
8508 || MEM_P (XEXP (in
, 0)))
8509 && (REG_P (XEXP (in
, 1))
8510 || GET_CODE (XEXP (in
, 1)) == SUBREG
8511 || CONSTANT_P (XEXP (in
, 1))
8512 || MEM_P (XEXP (in
, 1))))
8514 /* We need to compute the sum of a register or a MEM and another
8515 register, constant, or MEM, and put it into the reload
8516 register. The best possible way of doing this is if the machine
8517 has a three-operand ADD insn that accepts the required operands.
8519 The simplest approach is to try to generate such an insn and see if it
8520 is recognized and matches its constraints. If so, it can be used.
8522 It might be better not to actually emit the insn unless it is valid,
8523 but we need to pass the insn as an operand to `recog' and
8524 `extract_insn' and it is simpler to emit and then delete the insn if
8525 not valid than to dummy things up. */
8527 rtx op0
, op1
, tem
, insn
;
8528 enum insn_code code
;
8530 op0
= find_replacement (&XEXP (in
, 0));
8531 op1
= find_replacement (&XEXP (in
, 1));
8533 /* Since constraint checking is strict, commutativity won't be
8534 checked, so we need to do that here to avoid spurious failure
8535 if the add instruction is two-address and the second operand
8536 of the add is the same as the reload reg, which is frequently
8537 the case. If the insn would be A = B + A, rearrange it so
8538 it will be A = A + B as constrain_operands expects. */
8540 if (REG_P (XEXP (in
, 1))
8541 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8542 tem
= op0
, op0
= op1
, op1
= tem
;
8544 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8545 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8547 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8551 /* If that failed, we must use a conservative two-insn sequence.
8553 Use a move to copy one operand into the reload register. Prefer
8554 to reload a constant, MEM or pseudo since the move patterns can
8555 handle an arbitrary operand. If OP1 is not a constant, MEM or
8556 pseudo and OP1 is not a valid operand for an add instruction, then
8559 After reloading one of the operands into the reload register, add
8560 the reload register to the output register.
8562 If there is another way to do this for a specific machine, a
8563 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8566 code
= optab_handler (add_optab
, GET_MODE (out
));
8568 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8570 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8571 || (code
!= CODE_FOR_nothing
8572 && !insn_operand_matches (code
, 2, op1
)))
8573 tem
= op0
, op0
= op1
, op1
= tem
;
8575 gen_reload (out
, op0
, opnum
, type
);
8577 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8578 This fixes a problem on the 32K where the stack pointer cannot
8579 be used as an operand of an add insn. */
8581 if (rtx_equal_p (op0
, op1
))
8584 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8587 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8588 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8592 /* If that failed, copy the address register to the reload register.
8593 Then add the constant to the reload register. */
8595 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8596 gen_reload (out
, op1
, opnum
, type
);
8597 insn
= emit_insn (gen_add2_insn (out
, op0
));
8598 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8601 #ifdef SECONDARY_MEMORY_NEEDED
8602 /* If we need a memory location to do the move, do it that way. */
8603 else if ((REG_P (in
)
8604 || (GET_CODE (in
) == SUBREG
&& REG_P (SUBREG_REG (in
))))
8605 && reg_or_subregno (in
) < FIRST_PSEUDO_REGISTER
8607 || (GET_CODE (out
) == SUBREG
&& REG_P (SUBREG_REG (out
))))
8608 && reg_or_subregno (out
) < FIRST_PSEUDO_REGISTER
8609 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in
)),
8610 REGNO_REG_CLASS (reg_or_subregno (out
)),
8613 /* Get the memory to use and rewrite both registers to its mode. */
8614 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8616 if (GET_MODE (loc
) != GET_MODE (out
))
8617 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8619 if (GET_MODE (loc
) != GET_MODE (in
))
8620 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8622 gen_reload (loc
, in
, opnum
, type
);
8623 gen_reload (out
, loc
, opnum
, type
);
8626 else if (REG_P (out
) && UNARY_P (in
))
8633 op1
= find_replacement (&XEXP (in
, 0));
8634 if (op1
!= XEXP (in
, 0))
8635 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8637 /* First, try a plain SET. */
8638 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8642 /* If that failed, move the inner operand to the reload
8643 register, and try the same unop with the inner expression
8644 replaced with the reload register. */
8646 if (GET_MODE (op1
) != GET_MODE (out
))
8647 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8651 gen_reload (out_moded
, op1
, opnum
, type
);
8654 = gen_rtx_SET (VOIDmode
, out
,
8655 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8657 insn
= emit_insn_if_valid_for_reload (insn
);
8660 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8664 fatal_insn ("failure trying to reload:", set
);
8666 /* If IN is a simple operand, use gen_move_insn. */
8667 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8669 tem
= emit_insn (gen_move_insn (out
, in
));
8670 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8671 mark_jump_label (in
, tem
, 0);
8674 #ifdef HAVE_reload_load_address
8675 else if (HAVE_reload_load_address
)
8676 emit_insn (gen_reload_load_address (out
, in
));
8679 /* Otherwise, just write (set OUT IN) and hope for the best. */
8681 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8683 /* Return the first insn emitted.
8684 We can not just return get_last_insn, because there may have
8685 been multiple instructions emitted. Also note that gen_move_insn may
8686 emit more than one insn itself, so we can not assume that there is one
8687 insn emitted per emit_insn_before call. */
8689 return last
? NEXT_INSN (last
) : get_insns ();
8692 /* Delete a previously made output-reload whose result we now believe
8693 is not needed. First we double-check.
8695 INSN is the insn now being processed.
8696 LAST_RELOAD_REG is the hard register number for which we want to delete
8697 the last output reload.
8698 J is the reload-number that originally used REG. The caller has made
8699 certain that reload J doesn't use REG any longer for input.
8700 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8703 delete_output_reload (rtx insn
, int j
, int last_reload_reg
, rtx new_reload_reg
)
8705 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8706 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8709 int n_inherited
= 0;
8715 /* It is possible that this reload has been only used to set another reload
8716 we eliminated earlier and thus deleted this instruction too. */
8717 if (INSN_DELETED_P (output_reload_insn
))
8720 /* Get the raw pseudo-register referred to. */
8722 while (GET_CODE (reg
) == SUBREG
)
8723 reg
= SUBREG_REG (reg
);
8724 substed
= reg_equiv_memory_loc (REGNO (reg
));
8726 /* This is unsafe if the operand occurs more often in the current
8727 insn than it is inherited. */
8728 for (k
= n_reloads
- 1; k
>= 0; k
--)
8730 rtx reg2
= rld
[k
].in
;
8733 if (MEM_P (reg2
) || reload_override_in
[k
])
8734 reg2
= rld
[k
].in_reg
;
8736 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8737 reg2
= XEXP (rld
[k
].in_reg
, 0);
8739 while (GET_CODE (reg2
) == SUBREG
)
8740 reg2
= SUBREG_REG (reg2
);
8741 if (rtx_equal_p (reg2
, reg
))
8743 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8749 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8750 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8751 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8754 n_occurrences
+= count_occurrences (PATTERN (insn
),
8755 eliminate_regs (substed
, VOIDmode
,
8757 for (i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8759 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8760 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8762 if (n_occurrences
> n_inherited
)
8765 regno
= REGNO (reg
);
8766 if (regno
>= FIRST_PSEUDO_REGISTER
)
8769 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8771 /* If the pseudo-reg we are reloading is no longer referenced
8772 anywhere between the store into it and here,
8773 and we're within the same basic block, then the value can only
8774 pass through the reload reg and end up here.
8775 Otherwise, give up--return. */
8776 for (i1
= NEXT_INSN (output_reload_insn
);
8777 i1
!= insn
; i1
= NEXT_INSN (i1
))
8779 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8781 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8782 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8784 /* If this is USE in front of INSN, we only have to check that
8785 there are no more references than accounted for by inheritance. */
8786 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8788 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8789 i1
= NEXT_INSN (i1
);
8791 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8797 /* We will be deleting the insn. Remove the spill reg information. */
8798 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8800 spill_reg_store
[last_reload_reg
+ k
] = 0;
8801 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8804 /* The caller has already checked that REG dies or is set in INSN.
8805 It has also checked that we are optimizing, and thus some
8806 inaccuracies in the debugging information are acceptable.
8807 So we could just delete output_reload_insn. But in some cases
8808 we can improve the debugging information without sacrificing
8809 optimization - maybe even improving the code: See if the pseudo
8810 reg has been completely replaced with reload regs. If so, delete
8811 the store insn and forget we had a stack slot for the pseudo. */
8812 if (rld
[j
].out
!= rld
[j
].in
8813 && REG_N_DEATHS (REGNO (reg
)) == 1
8814 && REG_N_SETS (REGNO (reg
)) == 1
8815 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8816 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8820 /* We know that it was used only between here and the beginning of
8821 the current basic block. (We also know that the last use before
8822 INSN was the output reload we are thinking of deleting, but never
8823 mind that.) Search that range; see if any ref remains. */
8824 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8826 rtx set
= single_set (i2
);
8828 /* Uses which just store in the pseudo don't count,
8829 since if they are the only uses, they are dead. */
8830 if (set
!= 0 && SET_DEST (set
) == reg
)
8835 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8836 && reg_mentioned_p (reg
, PATTERN (i2
)))
8838 /* Some other ref remains; just delete the output reload we
8840 delete_address_reloads (output_reload_insn
, insn
);
8841 delete_insn (output_reload_insn
);
8846 /* Delete the now-dead stores into this pseudo. Note that this
8847 loop also takes care of deleting output_reload_insn. */
8848 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8850 rtx set
= single_set (i2
);
8852 if (set
!= 0 && SET_DEST (set
) == reg
)
8854 delete_address_reloads (i2
, insn
);
8862 /* For the debugging info, say the pseudo lives in this reload reg. */
8863 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8864 if (ira_conflicts_p
)
8865 /* Inform IRA about the change. */
8866 ira_mark_allocation_change (REGNO (reg
));
8867 alter_reg (REGNO (reg
), -1, false);
8871 delete_address_reloads (output_reload_insn
, insn
);
8872 delete_insn (output_reload_insn
);
8876 /* We are going to delete DEAD_INSN. Recursively delete loads of
8877 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8878 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8880 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
8882 rtx set
= single_set (dead_insn
);
8883 rtx set2
, dst
, prev
, next
;
8886 rtx dst
= SET_DEST (set
);
8888 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8890 /* If we deleted the store from a reloaded post_{in,de}c expression,
8891 we can delete the matching adds. */
8892 prev
= PREV_INSN (dead_insn
);
8893 next
= NEXT_INSN (dead_insn
);
8894 if (! prev
|| ! next
)
8896 set
= single_set (next
);
8897 set2
= single_set (prev
);
8899 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8900 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
8901 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
8903 dst
= SET_DEST (set
);
8904 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8905 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8906 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8907 || (INTVAL (XEXP (SET_SRC (set
), 1))
8908 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8910 delete_related_insns (prev
);
8911 delete_related_insns (next
);
8914 /* Subfunction of delete_address_reloads: process registers found in X. */
8916 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
8918 rtx prev
, set
, dst
, i2
;
8920 enum rtx_code code
= GET_CODE (x
);
8924 const char *fmt
= GET_RTX_FORMAT (code
);
8925 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8928 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8929 else if (fmt
[i
] == 'E')
8931 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8932 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8939 if (spill_reg_order
[REGNO (x
)] < 0)
8942 /* Scan backwards for the insn that sets x. This might be a way back due
8944 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8946 code
= GET_CODE (prev
);
8947 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8951 if (reg_set_p (x
, PATTERN (prev
)))
8953 if (reg_referenced_p (x
, PATTERN (prev
)))
8956 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8958 /* Check that PREV only sets the reload register. */
8959 set
= single_set (prev
);
8962 dst
= SET_DEST (set
);
8964 || ! rtx_equal_p (dst
, x
))
8966 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8968 /* Check if DST was used in a later insn -
8969 it might have been inherited. */
8970 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8976 if (reg_referenced_p (dst
, PATTERN (i2
)))
8978 /* If there is a reference to the register in the current insn,
8979 it might be loaded in a non-inherited reload. If no other
8980 reload uses it, that means the register is set before
8982 if (i2
== current_insn
)
8984 for (j
= n_reloads
- 1; j
>= 0; j
--)
8985 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8986 || reload_override_in
[j
] == dst
)
8988 for (j
= n_reloads
- 1; j
>= 0; j
--)
8989 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
8998 /* If DST is still live at CURRENT_INSN, check if it is used for
8999 any reload. Note that even if CURRENT_INSN sets DST, we still
9000 have to check the reloads. */
9001 if (i2
== current_insn
)
9003 for (j
= n_reloads
- 1; j
>= 0; j
--)
9004 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9005 || reload_override_in
[j
] == dst
)
9007 /* ??? We can't finish the loop here, because dst might be
9008 allocated to a pseudo in this block if no reload in this
9009 block needs any of the classes containing DST - see
9010 spill_hard_reg. There is no easy way to tell this, so we
9011 have to scan till the end of the basic block. */
9013 if (reg_set_p (dst
, PATTERN (i2
)))
9017 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9018 reg_reloaded_contents
[REGNO (dst
)] = -1;
9022 /* Output reload-insns to reload VALUE into RELOADREG.
9023 VALUE is an autoincrement or autodecrement RTX whose operand
9024 is a register or memory location;
9025 so reloading involves incrementing that location.
9026 IN is either identical to VALUE, or some cheaper place to reload from.
9028 INC_AMOUNT is the number to increment or decrement by (always positive).
9029 This cannot be deduced from VALUE. */
9032 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9034 /* REG or MEM to be copied and incremented. */
9035 rtx incloc
= find_replacement (&XEXP (value
, 0));
9036 /* Nonzero if increment after copying. */
9037 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9038 || GET_CODE (value
) == POST_MODIFY
);
9043 rtx real_in
= in
== value
? incloc
: in
;
9045 /* No hard register is equivalent to this register after
9046 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9047 we could inc/dec that register as well (maybe even using it for
9048 the source), but I'm not sure it's worth worrying about. */
9050 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9052 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9054 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9055 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9059 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9060 inc_amount
= -inc_amount
;
9062 inc
= GEN_INT (inc_amount
);
9065 /* If this is post-increment, first copy the location to the reload reg. */
9066 if (post
&& real_in
!= reloadreg
)
9067 emit_insn (gen_move_insn (reloadreg
, real_in
));
9071 /* See if we can directly increment INCLOC. Use a method similar to
9072 that in gen_reload. */
9074 last
= get_last_insn ();
9075 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
9076 gen_rtx_PLUS (GET_MODE (incloc
),
9079 code
= recog_memoized (add_insn
);
9082 extract_insn (add_insn
);
9083 if (constrain_operands (1))
9085 /* If this is a pre-increment and we have incremented the value
9086 where it lives, copy the incremented value to RELOADREG to
9087 be used as an address. */
9090 emit_insn (gen_move_insn (reloadreg
, incloc
));
9094 delete_insns_since (last
);
9097 /* If couldn't do the increment directly, must increment in RELOADREG.
9098 The way we do this depends on whether this is pre- or post-increment.
9099 For pre-increment, copy INCLOC to the reload register, increment it
9100 there, then save back. */
9104 if (in
!= reloadreg
)
9105 emit_insn (gen_move_insn (reloadreg
, real_in
));
9106 emit_insn (gen_add2_insn (reloadreg
, inc
));
9107 emit_insn (gen_move_insn (incloc
, reloadreg
));
9112 Because this might be a jump insn or a compare, and because RELOADREG
9113 may not be available after the insn in an input reload, we must do
9114 the incrementation before the insn being reloaded for.
9116 We have already copied IN to RELOADREG. Increment the copy in
9117 RELOADREG, save that back, then decrement RELOADREG so it has
9118 the original value. */
9120 emit_insn (gen_add2_insn (reloadreg
, inc
));
9121 emit_insn (gen_move_insn (incloc
, reloadreg
));
9122 if (CONST_INT_P (inc
))
9123 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-INTVAL (inc
))));
9125 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9131 add_auto_inc_notes (rtx insn
, rtx x
)
9133 enum rtx_code code
= GET_CODE (x
);
9137 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9139 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9143 /* Scan all the operand sub-expressions. */
9144 fmt
= GET_RTX_FORMAT (code
);
9145 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9148 add_auto_inc_notes (insn
, XEXP (x
, i
));
9149 else if (fmt
[i
] == 'E')
9150 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9151 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));