1 ;; Faraday FA626TE Pipeline Description
2 ;; Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it under
8 ;; the terms of the GNU General Public License as published by the Free
9 ;; Software Foundation; either version 3, or (at your option) any later
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; These descriptions are based on the information contained in the
22 ;; FA626TE Core Design Note, Copyright (c) 2010 Faraday Technology Corp.
24 ;; Modeled pipeline characteristics:
25 ;; ALU -> simple address LDR/STR: latency = 2 (available after 2 cycles).
26 ;; ALU -> shifted address LDR/STR: latency = 3.
27 ;; ( extra 1 cycle unavoidable stall).
28 ;; ALU -> other use: latency = 2 (available after 2 cycles).
29 ;; LD -> simple address LDR/STR: latency = 3 (available after 3 cycles).
30 ;; LD -> shifted address LDR/STR: latency = 4
31 ;; ( extra 1 cycle unavoidable stall).
32 ;; LD -> any other use: latency = 3 (available after 3 cycles).
34 ;; This automaton provides a pipeline description for the Faraday
37 ;; The model given here assumes that the condition for all conditional
38 ;; instructions is "true", i.e., that all of the instructions are
41 (define_automaton "fa626te")
43 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
45 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
47 ;; There is a single pipeline
49 ;; The ALU pipeline has fetch, decode, execute, memory, and
50 ;; write stages. We only need to model the execute, memory and write
55 (define_cpu_unit "fa626te_core" "fa626te")
57 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
59 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
61 ;; ALU instructions require two cycles to execute, and use the ALU
62 ;; pipeline in each of the three stages. The results are available
63 ;; after the execute stage has finished.
65 ;; If the destination register is the PC, the pipelines are stalled
66 ;; for several cycles. That case is not modeled here.
69 (define_insn_reservation "626te_alu_op" 1
70 (and (eq_attr "tune" "fa626,fa626te")
71 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
72 alu_sreg,alus_sreg,logic_reg,logics_reg,\
73 adc_imm,adcs_imm,adc_reg,adcs_reg,\
76 mov_imm,mov_reg,mvn_imm,mvn_reg,\
77 mrs,multiple,no_insn"))
80 (define_insn_reservation "626te_alu_shift_op" 2
81 (and (eq_attr "tune" "fa626,fa626te")
82 (eq_attr "type" "extend,\
83 alu_shift_imm,alus_shift_imm,\
84 logic_shift_imm,logics_shift_imm,\
85 alu_shift_reg,alus_shift_reg,\
86 logic_shift_reg,logics_shift_reg,\
87 mov_shift,mov_shift_reg,\
88 mvn_shift,mvn_shift_reg"))
91 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
92 ;; Multiplication Instructions
93 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
95 (define_insn_reservation "626te_mult1" 2
96 (and (eq_attr "tune" "fa626,fa626te")
97 (eq_attr "type" "smulwy,smlawy,smulxy,smlaxy"))
100 (define_insn_reservation "626te_mult2" 2
101 (and (eq_attr "tune" "fa626,fa626te")
102 (eq_attr "type" "mul,mla"))
105 (define_insn_reservation "626te_mult3" 3
106 (and (eq_attr "tune" "fa626,fa626te")
107 (eq_attr "type" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx"))
110 (define_insn_reservation "626te_mult4" 4
111 (and (eq_attr "tune" "fa626,fa626te")
112 (eq_attr "type" "smulls,smlals,umulls,umlals"))
115 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
116 ;; Load/Store Instructions
117 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
119 ;; The models for load/store instructions do not accurately describe
120 ;; the difference between operations with a base register writeback
121 ;; (such as "ldm!"). These models assume that all memory references
124 (define_insn_reservation "626te_load1_op" 3
125 (and (eq_attr "tune" "fa626,fa626te")
126 (eq_attr "type" "load1,load_byte"))
129 (define_insn_reservation "626te_load2_op" 4
130 (and (eq_attr "tune" "fa626,fa626te")
131 (eq_attr "type" "load2,load3"))
134 (define_insn_reservation "626te_load3_op" 5
135 (and (eq_attr "tune" "fa626,fa626te")
136 (eq_attr "type" "load4"))
139 (define_insn_reservation "626te_store1_op" 0
140 (and (eq_attr "tune" "fa626,fa626te")
141 (eq_attr "type" "store1"))
144 (define_insn_reservation "626te_store2_op" 1
145 (and (eq_attr "tune" "fa626,fa626te")
146 (eq_attr "type" "store2,store3"))
149 (define_insn_reservation "626te_store3_op" 2
150 (and (eq_attr "tune" "fa626,fa626te")
151 (eq_attr "type" "store4"))
154 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
155 ;; Branch and Call Instructions
156 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
158 ;; Branch instructions are difficult to model accurately. The FA626TE
159 ;; core can predict most branches. If the branch is predicted
160 ;; correctly, and predicted early enough, the branch can be completely
161 ;; eliminated from the instruction stream. Some branches can
162 ;; therefore appear to require zero cycle to execute. We assume that
163 ;; all branches are predicted correctly, and that the latency is
164 ;; therefore the minimum value.
166 (define_insn_reservation "626te_branch_op" 0
167 (and (eq_attr "tune" "fa626,fa626te")
168 (eq_attr "type" "branch"))
171 ;; The latency for a call is actually the latency when the result is available.
172 ;; i.e. R0 ready for int return value.
173 (define_insn_reservation "626te_call_op" 1
174 (and (eq_attr "tune" "fa626,fa626te")
175 (eq_attr "type" "call"))