1 ;; ARM 1020E & ARM 1022E Pipeline Description
2 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
3 ;; Contributed by Richard Earnshaw (richard.earnshaw@arm.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; These descriptions are based on the information contained in the
22 ;; ARM1020E Technical Reference Manual, Copyright (c) 2003 ARM
26 ;; This automaton provides a pipeline description for the ARM
29 ;; The model given here assumes that the condition for all conditional
30 ;; instructions is "true", i.e., that all of the instructions are
33 (define_automaton "arm1020e")
35 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
39 ;; There are two pipelines:
41 ;; - An Arithmetic Logic Unit (ALU) pipeline.
43 ;; The ALU pipeline has fetch, issue, decode, execute, memory, and
44 ;; write stages. We only need to model the execute, memory and write
47 ;; - A Load-Store Unit (LSU) pipeline.
49 ;; The LSU pipeline has decode, execute, memory, and write stages.
50 ;; We only model the execute, memory and write stages.
52 (define_cpu_unit "1020a_e,1020a_m,1020a_w" "arm1020e")
53 (define_cpu_unit "1020l_e,1020l_m,1020l_w" "arm1020e")
55 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
57 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
59 ;; ALU instructions require three cycles to execute, and use the ALU
60 ;; pipeline in each of the three stages. The results are available
61 ;; after the execute stage has finished.
63 ;; If the destination register is the PC, the pipelines are stalled
64 ;; for several cycles. That case is not modeled here.
66 ;; ALU operations with no shifted operand
67 (define_insn_reservation "1020alu_op" 1
68 (and (eq_attr "tune" "arm1020e,arm1022e")
69 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
70 alu_sreg,alus_sreg,logic_reg,logics_reg,\
71 adc_imm,adcs_imm,adc_reg,adcs_reg,\
74 mov_imm,mov_reg,mvn_imm,mvn_reg,\
76 "1020a_e,1020a_m,1020a_w")
78 ;; ALU operations with a shift-by-constant operand
79 (define_insn_reservation "1020alu_shift_op" 1
80 (and (eq_attr "tune" "arm1020e,arm1022e")
81 (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
82 logic_shift_imm,logics_shift_imm,\
83 extend,mov_shift,mvn_shift"))
84 "1020a_e,1020a_m,1020a_w")
86 ;; ALU operations with a shift-by-register operand
87 ;; These really stall in the decoder, in order to read
88 ;; the shift value in a second cycle. Pretend we take two cycles in
90 (define_insn_reservation "1020alu_shift_reg_op" 2
91 (and (eq_attr "tune" "arm1020e,arm1022e")
92 (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
93 logic_shift_reg,logics_shift_reg,\
94 mov_shift_reg,mvn_shift_reg"))
95 "1020a_e*2,1020a_m,1020a_w")
97 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
98 ;; Multiplication Instructions
99 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
101 ;; Multiplication instructions loop in the execute stage until the
102 ;; instruction has been passed through the multiplier array enough
105 ;; The result of the "smul" and "smulw" instructions is not available
106 ;; until after the memory stage.
107 (define_insn_reservation "1020mult1" 2
108 (and (eq_attr "tune" "arm1020e,arm1022e")
109 (eq_attr "type" "smulxy,smulwy"))
110 "1020a_e,1020a_m,1020a_w")
112 ;; The "smlaxy" and "smlawx" instructions require two iterations through
113 ;; the execute stage; the result is available immediately following
114 ;; the execute stage.
115 (define_insn_reservation "1020mult2" 2
116 (and (eq_attr "tune" "arm1020e,arm1022e")
117 (eq_attr "type" "smlaxy,smlalxy,smlawx"))
118 "1020a_e*2,1020a_m,1020a_w")
120 ;; The "smlalxy", "mul", and "mla" instructions require two iterations
121 ;; through the execute stage; the result is not available until after
123 (define_insn_reservation "1020mult3" 3
124 (and (eq_attr "tune" "arm1020e,arm1022e")
125 (eq_attr "type" "smlalxy,mul,mla"))
126 "1020a_e*2,1020a_m,1020a_w")
128 ;; The "muls" and "mlas" instructions loop in the execute stage for
129 ;; four iterations in order to set the flags. The value result is
130 ;; available after three iterations.
131 (define_insn_reservation "1020mult4" 3
132 (and (eq_attr "tune" "arm1020e,arm1022e")
133 (eq_attr "type" "muls,mlas"))
134 "1020a_e*4,1020a_m,1020a_w")
136 ;; Long multiply instructions that produce two registers of
137 ;; output (such as umull) make their results available in two cycles;
138 ;; the least significant word is available before the most significant
139 ;; word. That fact is not modeled; instead, the instructions are
140 ;; described.as if the entire result was available at the end of the
141 ;; cycle in which both words are available.
143 ;; The "umull", "umlal", "smull", and "smlal" instructions all take
144 ;; three iterations through the execute cycle, and make their results
145 ;; available after the memory cycle.
146 (define_insn_reservation "1020mult5" 4
147 (and (eq_attr "tune" "arm1020e,arm1022e")
148 (eq_attr "type" "umull,umlal,smull,smlal"))
149 "1020a_e*3,1020a_m,1020a_w")
151 ;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
152 ;; the execute stage for five iterations in order to set the flags.
153 ;; The value result is available after four iterations.
154 (define_insn_reservation "1020mult6" 4
155 (and (eq_attr "tune" "arm1020e,arm1022e")
156 (eq_attr "type" "umulls,umlals,smulls,smlals"))
157 "1020a_e*5,1020a_m,1020a_w")
159 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
160 ;; Load/Store Instructions
161 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
163 ;; The models for load/store instructions do not accurately describe
164 ;; the difference between operations with a base register writeback
165 ;; (such as "ldm!"). These models assume that all memory references
168 ;; LSU instructions require six cycles to execute. They use the ALU
169 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
170 ;; three through six.
171 ;; Loads and stores which use a scaled register offset or scaled
172 ;; register pre-indexed addressing mode take three cycles EXCEPT for
173 ;; those that are base + offset with LSL of 0 or 2, or base - offset
174 ;; with LSL of zero. The remainder take 1 cycle to execute.
175 ;; For 4byte loads there is a bypass from the load stage
177 (define_insn_reservation "1020load1_op" 2
178 (and (eq_attr "tune" "arm1020e,arm1022e")
179 (eq_attr "type" "load_byte,load1"))
180 "1020a_e+1020l_e,1020l_m,1020l_w")
182 (define_insn_reservation "1020store1_op" 0
183 (and (eq_attr "tune" "arm1020e,arm1022e")
184 (eq_attr "type" "store1"))
185 "1020a_e+1020l_e,1020l_m,1020l_w")
187 ;; A load's result can be stored by an immediately following store
188 (define_bypass 1 "1020load1_op" "1020store1_op" "arm_no_early_store_addr_dep")
190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
191 ;; registers have been processed.
193 ;; The time it takes to load the data depends on whether or not the
194 ;; base address is 64-bit aligned; if it is not, an additional cycle
195 ;; is required. This model assumes that the address is always 64-bit
196 ;; aligned. Because the processor can load two registers per cycle,
197 ;; that assumption means that we use the same instruction reservations
198 ;; for loading 2k and 2k - 1 registers.
200 ;; The ALU pipeline is decoupled after the first cycle unless there is
201 ;; a register dependency; the dependency is cleared as soon as the LDM/STM
202 ;; has dealt with the corresponding register. So for example,
205 ;; will have one fewer stalls than
209 ;; As with ALU operations, if one of the destination registers is the
210 ;; PC, there are additional stalls; that is not modeled.
212 (define_insn_reservation "1020load2_op" 2
213 (and (eq_attr "tune" "arm1020e,arm1022e")
214 (eq_attr "type" "load2"))
215 "1020a_e+1020l_e,1020l_m,1020l_w")
217 (define_insn_reservation "1020store2_op" 0
218 (and (eq_attr "tune" "arm1020e,arm1022e")
219 (eq_attr "type" "store2"))
220 "1020a_e+1020l_e,1020l_m,1020l_w")
222 (define_insn_reservation "1020load34_op" 3
223 (and (eq_attr "tune" "arm1020e,arm1022e")
224 (eq_attr "type" "load3,load4"))
225 "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
227 (define_insn_reservation "1020store34_op" 0
228 (and (eq_attr "tune" "arm1020e,arm1022e")
229 (eq_attr "type" "store3,store4"))
230 "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
232 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
233 ;; Branch and Call Instructions
234 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
236 ;; Branch instructions are difficult to model accurately. The ARM
237 ;; core can predict most branches. If the branch is predicted
238 ;; correctly, and predicted early enough, the branch can be completely
239 ;; eliminated from the instruction stream. Some branches can
240 ;; therefore appear to require zero cycles to execute. We assume that
241 ;; all branches are predicted correctly, and that the latency is
242 ;; therefore the minimum value.
244 (define_insn_reservation "1020branch_op" 0
245 (and (eq_attr "tune" "arm1020e,arm1022e")
246 (eq_attr "type" "branch"))
249 ;; The latency for a call is not predictable. Therefore, we model as blocking
250 ;; execution for a number of cycles but we can't do anything more accurate
253 (define_insn_reservation "1020call_op" 32
254 (and (eq_attr "tune" "arm1020e,arm1022e")
255 (eq_attr "type" "call"))
258 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
260 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
262 (define_cpu_unit "v10_fmac" "arm1020e")
264 (define_cpu_unit "v10_ds" "arm1020e")
266 (define_cpu_unit "v10_fmstat" "arm1020e")
268 (define_cpu_unit "v10_ls1,v10_ls2,v10_ls3" "arm1020e")
270 ;; fmstat is a serializing instruction. It will stall the core until
271 ;; the mac and ds units have completed.
272 (exclusion_set "v10_fmac,v10_ds" "v10_fmstat")
274 (define_attr "vfp10" "yes,no"
275 (const (if_then_else (and (eq_attr "tune" "arm1020e,arm1022e")
276 (eq_attr "fpu" "vfp"))
277 (const_string "yes") (const_string "no"))))
279 ;; Note, no instruction can issue to the VFP if the core is stalled in the
280 ;; first execute state. We model this by using 1020a_e in the first cycle.
281 (define_insn_reservation "v10_ffarith" 5
282 (and (eq_attr "vfp10" "yes")
283 (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
286 (define_insn_reservation "v10_farith" 5
287 (and (eq_attr "vfp10" "yes")
288 (eq_attr "type" "faddd,fadds"))
291 (define_insn_reservation "v10_cvt" 5
292 (and (eq_attr "vfp10" "yes")
293 (eq_attr "type" "f_cvt,f_cvti2f,f_cvtf2i"))
296 (define_insn_reservation "v10_fmul" 6
297 (and (eq_attr "vfp10" "yes")
298 (eq_attr "type" "fmuls,fmacs,ffmas,fmuld,fmacd,ffmad"))
299 "1020a_e+v10_fmac*2")
301 (define_insn_reservation "v10_fdivs" 18
302 (and (eq_attr "vfp10" "yes")
303 (eq_attr "type" "fdivs, fsqrts"))
306 (define_insn_reservation "v10_fdivd" 32
307 (and (eq_attr "vfp10" "yes")
308 (eq_attr "type" "fdivd, fsqrtd"))
309 "1020a_e+v10_fmac+v10_ds*4")
311 (define_insn_reservation "v10_floads" 4
312 (and (eq_attr "vfp10" "yes")
313 (eq_attr "type" "f_loads"))
314 "1020a_e+1020l_e+v10_ls1,v10_ls2")
316 ;; We model a load of a double as needing all the vfp ls* stage in cycle 1.
317 ;; This gives the correct mix between single-and double loads where a flds
318 ;; followed by and fldd will stall for one cycle, but two back-to-back fldd
319 ;; insns stall for two cycles.
320 (define_insn_reservation "v10_floadd" 5
321 (and (eq_attr "vfp10" "yes")
322 (eq_attr "type" "f_loadd"))
323 "1020a_e+1020l_e+v10_ls1+v10_ls2+v10_ls3,v10_ls2+v10_ls3,v10_ls3")
325 ;; Moves to/from arm regs also use the load/store pipeline.
327 (define_insn_reservation "v10_c2v" 4
328 (and (eq_attr "vfp10" "yes")
329 (eq_attr "type" "f_mcr,f_mcrr"))
330 "1020a_e+1020l_e+v10_ls1,v10_ls2")
332 (define_insn_reservation "v10_fstores" 1
333 (and (eq_attr "vfp10" "yes")
334 (eq_attr "type" "f_stores"))
335 "1020a_e+1020l_e+v10_ls1,v10_ls2")
337 (define_insn_reservation "v10_fstored" 1
338 (and (eq_attr "vfp10" "yes")
339 (eq_attr "type" "f_stored"))
340 "1020a_e+1020l_e+v10_ls1+v10_ls2+v10_ls3,v10_ls2+v10_ls3,v10_ls3")
342 (define_insn_reservation "v10_v2c" 1
343 (and (eq_attr "vfp10" "yes")
344 (eq_attr "type" "f_mrc,f_mrrc"))
345 "1020a_e+1020l_e,1020l_m,1020l_w")
347 (define_insn_reservation "v10_to_cpsr" 2
348 (and (eq_attr "vfp10" "yes")
349 (eq_attr "type" "f_flag"))
350 "1020a_e+v10_fmstat,1020a_e+1020l_e,1020l_m,1020l_w")
354 ;; There are bypasses for most operations other than store
358 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd,v10_cvt")
362 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
364 ;; Arithmetic to other arithmetic saves a cycle due to forwarding
366 "v10_ffarith,v10_farith"
367 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
371 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
375 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
379 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
381 ;; VFP anti-dependencies.
383 ;; There is one anti-dependence in the following case (not yet modelled):
384 ;; - After a store: one extra cycle for both fsts and fstd
385 ;; Note, back-to-back fstd instructions will overload the load/store datapath
386 ;; causing a two-cycle stall.