gcc/config/aarch64/aarch64-simd-builtins.def

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2012-2013 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* In the list below, the BUILTIN_<ITERATOR> macros expand to create
  22    builtins for each of the modes described by <ITERATOR>.  When adding
  23    new builtins to this list, a helpful idiom to follow is to add
  24    a line for each pattern in the md file.  Thus, ADDP, which has one
  25    pattern defined for the VD_BHSI iterator, and one for DImode, has two
  26    entries below.
  27
  28    Parameter 1 is the 'type' of the intrinsic.  This is used to
  29    describe the type modifiers (for example; unsigned) applied to
  30    each of the parameters to the intrinsic function.
  31
  32    Parameter 2 is the name of the intrinsic.  This is appended
  33    to `__builtin_aarch64_<name><mode>` to give the intrinsic name
  34    as exported to the front-ends.
  35
  36    Parameter 3 describes how to map from the name to the CODE_FOR_
  37    macro holding the RTL pattern for the intrinsic.  This mapping is:
  38    0 - CODE_FOR_aarch64_<name><mode>
  39    1-9 - CODE_FOR_<name><mode><1-9>
  40    10 - CODE_FOR_<name><mode>.  */
  41
  42   BUILTIN_VD_RE (CREATE, create, 0)
  43   BUILTIN_VQ_S (GETLANE, get_lane_signed, 0)
  44   BUILTIN_VDQ (GETLANE, get_lane_unsigned, 0)
  45   BUILTIN_VDQF (GETLANE, get_lane, 0)
  46   VAR1 (GETLANE, get_lane, 0, di)
  47   BUILTIN_VDC (COMBINE, combine, 0)
  48   BUILTIN_VB (BINOP, pmul, 0)
  49   BUILTIN_VDQF (UNOP, sqrt, 2)
  50   BUILTIN_VD_BHSI (BINOP, addp, 0)
  51   VAR1 (UNOP, addp, 0, di)
  52
  53   BUILTIN_VD_RE (REINTERP, reinterpretdi, 0)
  54   BUILTIN_VDC (REINTERP, reinterpretv8qi, 0)
  55   BUILTIN_VDC (REINTERP, reinterpretv4hi, 0)
  56   BUILTIN_VDC (REINTERP, reinterpretv2si, 0)
  57   BUILTIN_VDC (REINTERP, reinterpretv2sf, 0)
  58   BUILTIN_VQ (REINTERP, reinterpretv16qi, 0)
  59   BUILTIN_VQ (REINTERP, reinterpretv8hi, 0)
  60   BUILTIN_VQ (REINTERP, reinterpretv4si, 0)
  61   BUILTIN_VQ (REINTERP, reinterpretv4sf, 0)
  62   BUILTIN_VQ (REINTERP, reinterpretv2di, 0)
  63   BUILTIN_VQ (REINTERP, reinterpretv2df, 0)
  64
  65   BUILTIN_VDQ_I (BINOP, dup_lane, 0)
  66   BUILTIN_SDQ_I (BINOP, dup_lane, 0)
  67   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
  68   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
  69   BUILTIN_VSDQ_I (BINOP, uqshl, 0)
  70   BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
  71   BUILTIN_VSDQ_I (BINOP, uqrshl, 0)
  72   /* Implemented by aarch64_<su_optab><optab><mode>.  */
  73   BUILTIN_VSDQ_I (BINOP, sqadd, 0)
  74   BUILTIN_VSDQ_I (BINOP, uqadd, 0)
  75   BUILTIN_VSDQ_I (BINOP, sqsub, 0)
  76   BUILTIN_VSDQ_I (BINOP, uqsub, 0)
  77   /* Implemented by aarch64_<sur>qadd<mode>.  */
  78   BUILTIN_VSDQ_I (BINOP, suqadd, 0)
  79   BUILTIN_VSDQ_I (BINOP, usqadd, 0)
  80
  81   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
  82   BUILTIN_VDC (GETLANE, get_dregoi, 0)
  83   BUILTIN_VDC (GETLANE, get_dregci, 0)
  84   BUILTIN_VDC (GETLANE, get_dregxi, 0)
  85   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
  86   BUILTIN_VQ (GETLANE, get_qregoi, 0)
  87   BUILTIN_VQ (GETLANE, get_qregci, 0)
  88   BUILTIN_VQ (GETLANE, get_qregxi, 0)
  89   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
  90   BUILTIN_VQ (SETLANE, set_qregoi, 0)
  91   BUILTIN_VQ (SETLANE, set_qregci, 0)
  92   BUILTIN_VQ (SETLANE, set_qregxi, 0)
  93   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
  94   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
  95   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
  96   BUILTIN_VDC (LOADSTRUCT, ld4, 0)
  97   /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>.  */
  98   BUILTIN_VQ (LOADSTRUCT, ld2, 0)
  99   BUILTIN_VQ (LOADSTRUCT, ld3, 0)
 100   BUILTIN_VQ (LOADSTRUCT, ld4, 0)
 101   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
 102   BUILTIN_VDC (STORESTRUCT, st2, 0)
 103   BUILTIN_VDC (STORESTRUCT, st3, 0)
 104   BUILTIN_VDC (STORESTRUCT, st4, 0)
 105   /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>.  */
 106   BUILTIN_VQ (STORESTRUCT, st2, 0)
 107   BUILTIN_VQ (STORESTRUCT, st3, 0)
 108   BUILTIN_VQ (STORESTRUCT, st4, 0)
 109
 110   BUILTIN_VQW (BINOP, saddl2, 0)
 111   BUILTIN_VQW (BINOP, uaddl2, 0)
 112   BUILTIN_VQW (BINOP, ssubl2, 0)
 113   BUILTIN_VQW (BINOP, usubl2, 0)
 114   BUILTIN_VQW (BINOP, saddw2, 0)
 115   BUILTIN_VQW (BINOP, uaddw2, 0)
 116   BUILTIN_VQW (BINOP, ssubw2, 0)
 117   BUILTIN_VQW (BINOP, usubw2, 0)
 118   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>.  */
 119   BUILTIN_VDW (BINOP, saddl, 0)
 120   BUILTIN_VDW (BINOP, uaddl, 0)
 121   BUILTIN_VDW (BINOP, ssubl, 0)
 122   BUILTIN_VDW (BINOP, usubl, 0)
 123   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>.  */
 124   BUILTIN_VDW (BINOP, saddw, 0)
 125   BUILTIN_VDW (BINOP, uaddw, 0)
 126   BUILTIN_VDW (BINOP, ssubw, 0)
 127   BUILTIN_VDW (BINOP, usubw, 0)
 128   /* Implemented by aarch64_<sur>h<addsub><mode>.  */
 129   BUILTIN_VQ_S (BINOP, shadd, 0)
 130   BUILTIN_VQ_S (BINOP, uhadd, 0)
 131   BUILTIN_VQ_S (BINOP, srhadd, 0)
 132   BUILTIN_VQ_S (BINOP, urhadd, 0)
 133   /* Implemented by aarch64_<sur><addsub>hn<mode>.  */
 134   BUILTIN_VQN (BINOP, addhn, 0)
 135   BUILTIN_VQN (BINOP, raddhn, 0)
 136   /* Implemented by aarch64_<sur><addsub>hn2<mode>.  */
 137   BUILTIN_VQN (TERNOP, addhn2, 0)
 138   BUILTIN_VQN (TERNOP, raddhn2, 0)
 139
 140   BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
 141   /* Implemented by aarch64_<sur>qmovn<mode>.  */
 142   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
 143   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
 144   /* Implemented by aarch64_s<optab><mode>.  */
 145   BUILTIN_VSDQ_I_BHSI (UNOP, sqabs, 0)
 146   BUILTIN_VSDQ_I_BHSI (UNOP, sqneg, 0)
 147
 148   BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0)
 149   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0)
 150   BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq, 0)
 151   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq, 0)
 152   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
 153   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
 154   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane, 0)
 155   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane, 0)
 156   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq, 0)
 157   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq, 0)
 158   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
 159   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
 160   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
 161   BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
 162   BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
 163   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>.  */
 164   BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
 165   BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
 166
 167   BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
 168   BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0)
 169   BUILTIN_VD_HSI (TERNOP, sqdmull_laneq, 0)
 170   BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
 171   BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
 172   BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0)
 173   BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq, 0)
 174   BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
 175   /* Implemented by aarch64_sq<r>dmulh<mode>.  */
 176   BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
 177   BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
 178   /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>.  */
 179   BUILTIN_VDQHS (TERNOP, sqdmulh_lane, 0)
 180   BUILTIN_VDQHS (TERNOP, sqdmulh_laneq, 0)
 181   BUILTIN_VDQHS (TERNOP, sqrdmulh_lane, 0)
 182   BUILTIN_VDQHS (TERNOP, sqrdmulh_laneq, 0)
 183   BUILTIN_SD_HSI (TERNOP, sqdmulh_lane, 0)
 184   BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane, 0)
 185
 186   BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
 187   /* Implemented by aarch64_<sur>shl<mode>.  */
 188   BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
 189   BUILTIN_VSDQ_I_DI (BINOP, ushl, 0)
 190   BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
 191   BUILTIN_VSDQ_I_DI (BINOP, urshl, 0)
 192
 193   BUILTIN_VSDQ_I_DI (SHIFTIMM, ashr, 3)
 194   BUILTIN_VSDQ_I_DI (SHIFTIMM, lshr, 3)
 195   /* Implemented by aarch64_<sur>shr_n<mode>.  */
 196   BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
 197   BUILTIN_VSDQ_I_DI (SHIFTIMM, urshr_n, 0)
 198   /* Implemented by aarch64_<sur>sra_n<mode>.  */
 199   BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
 200   BUILTIN_VSDQ_I_DI (SHIFTACC, usra_n, 0)
 201   BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
 202   BUILTIN_VSDQ_I_DI (SHIFTACC, ursra_n, 0)
 203   /* Implemented by aarch64_<sur>shll_n<mode>.  */
 204   BUILTIN_VDW (SHIFTIMM, sshll_n, 0)
 205   BUILTIN_VDW (SHIFTIMM, ushll_n, 0)
 206   /* Implemented by aarch64_<sur>shll2_n<mode>.  */
 207   BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
 208   BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
 209   /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>.  */
 210   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
 211   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
 212   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
 213   BUILTIN_VSQN_HSDI (SHIFTIMM, uqshrn_n, 0)
 214   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
 215   BUILTIN_VSQN_HSDI (SHIFTIMM, uqrshrn_n, 0)
 216   /* Implemented by aarch64_<sur>s<lr>i_n<mode>.  */
 217   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
 218   BUILTIN_VSDQ_I_DI (SHIFTINSERT, usri_n, 0)
 219   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
 220   BUILTIN_VSDQ_I_DI (SHIFTINSERT, usli_n, 0)
 221   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
 222   BUILTIN_VSDQ_I (SHIFTIMM, sqshlu_n, 0)
 223   BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
 224   BUILTIN_VSDQ_I (SHIFTIMM, uqshl_n, 0)
 225
 226   /* Implemented by aarch64_cm<cmp><mode>.  */
 227   BUILTIN_VSDQ_I_DI (BINOP, cmeq, 0)
 228   BUILTIN_VSDQ_I_DI (BINOP, cmge, 0)
 229   BUILTIN_VSDQ_I_DI (BINOP, cmgt, 0)
 230   BUILTIN_VSDQ_I_DI (BINOP, cmle, 0)
 231   BUILTIN_VSDQ_I_DI (BINOP, cmlt, 0)
 232   /* Implemented by aarch64_cm<cmp><mode>.  */
 233   BUILTIN_VSDQ_I_DI (BINOP, cmhs, 0)
 234   BUILTIN_VSDQ_I_DI (BINOP, cmhi, 0)
 235   BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
 236
 237   /* Implemented by aarch64_<fmaxmin><mode>.  */
 238   BUILTIN_VDQF (BINOP, fmax, 0)
 239   BUILTIN_VDQF (BINOP, fmin, 0)
 240
 241   /* Implemented by aarch64_addv<mode>.  */
 242   BUILTIN_VDQF (UNOP, addv, 0)
 243
 244   /* Implemented by <maxmin><mode>3.  */
 245   BUILTIN_VDQ_BHSI (BINOP, smax, 3)
 246   BUILTIN_VDQ_BHSI (BINOP, smin, 3)
 247   BUILTIN_VDQ_BHSI (BINOP, umax, 3)
 248   BUILTIN_VDQ_BHSI (BINOP, umin, 3)
 249
 250   /* Implemented by aarch64_frint<frint_suffix><mode>.  */
 251   BUILTIN_VDQF (UNOP, frintz, 0)
 252   BUILTIN_VDQF (UNOP, frintp, 0)
 253   BUILTIN_VDQF (UNOP, frintm, 0)
 254   BUILTIN_VDQF (UNOP, frinti, 0)
 255   BUILTIN_VDQF (UNOP, frintx, 0)
 256   BUILTIN_VDQF (UNOP, frinta, 0)
 257
 258   /* Implemented by aarch64_fcvt<frint_suffix><su><mode>.  */
 259   BUILTIN_VDQF (UNOP, fcvtzs, 0)
 260   BUILTIN_VDQF (UNOP, fcvtzu, 0)
 261   BUILTIN_VDQF (UNOP, fcvtas, 0)
 262   BUILTIN_VDQF (UNOP, fcvtau, 0)
 263   BUILTIN_VDQF (UNOP, fcvtps, 0)
 264   BUILTIN_VDQF (UNOP, fcvtpu, 0)
 265   BUILTIN_VDQF (UNOP, fcvtms, 0)
 266   BUILTIN_VDQF (UNOP, fcvtmu, 0)
 267
 268   /* Implemented by
 269      aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>.  */
 270   BUILTIN_VALL (BINOP, zip1, 0)
 271   BUILTIN_VALL (BINOP, zip2, 0)
 272   BUILTIN_VALL (BINOP, uzp1, 0)
 273   BUILTIN_VALL (BINOP, uzp2, 0)
 274   BUILTIN_VALL (BINOP, trn1, 0)
 275   BUILTIN_VALL (BINOP, trn2, 0)
 276
 277   /* Implemented by
 278      aarch64_frecp<FRECP:frecp_suffix><mode>.  */
 279   BUILTIN_GPF (UNOP, frecpe, 0)
 280   BUILTIN_GPF (BINOP, frecps, 0)
 281   BUILTIN_GPF (UNOP, frecpx, 0)
 282
 283   BUILTIN_VDQF (UNOP, frecpe, 0)
 284   BUILTIN_VDQF (BINOP, frecps, 0)
 285
 286   BUILTIN_VDQF (UNOP, abs, 2)