| blob | 5f187736c4b69489357672e88a7c5405ff4dff88 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
59 /* Not really meaningful values, but at least something. */
60 #ifndef SIMULTANEOUS_PREFETCHES
61 #define SIMULTANEOUS_PREFETCHES 3
62 #endif
63 #ifndef PREFETCH_BLOCK
64 #define PREFETCH_BLOCK 32
65 #endif
66 #ifndef HAVE_prefetch
67 #define HAVE_prefetch 0
68 #define CODE_FOR_prefetch 0
69 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
70 #endif
72 /* Give up the prefetch optimizations once we exceed a given threshhold.
73 It is unlikely that we would be able to optimize something in a loop
74 with so many detected prefetches. */
75 #define MAX_PREFETCHES 100
76 /* The number of prefetch blocks that are beneficial to fetch at once before
77 a loop with a known (and low) iteration count. */
78 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
79 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
80 since it is likely that the data are already in the cache. */
81 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
82 /* The minimal number of prefetch blocks that a loop must consume to make
83 the emitting of prefetch instruction in the body of loop worthwhile. */
84 #define PREFETCH_BLOCKS_IN_LOOP_MIN 6
86 /* Parameterize some prefetch heuristics so they can be turned on and off
87 easily for performance testing on new architecures. These can be
88 defined in target-dependent files. */
90 /* Prefetch is worthwhile only when loads/stores are dense. */
91 #ifndef PREFETCH_ONLY_DENSE_MEM
92 #define PREFETCH_ONLY_DENSE_MEM 1
93 #endif
95 /* Define what we mean by "dense" loads and stores; This value divided by 256
96 is the minimum percentage of memory references that worth prefetching. */
97 #ifndef PREFETCH_DENSE_MEM
98 #define PREFETCH_DENSE_MEM 220
99 #endif
101 /* Do not prefetch for a loop whose iteration count is known to be low. */
102 #ifndef PREFETCH_NO_LOW_LOOPCNT
103 #define PREFETCH_NO_LOW_LOOPCNT 1
104 #endif
106 /* Define what we mean by a "low" iteration count. */
107 #ifndef PREFETCH_LOW_LOOPCNT
108 #define PREFETCH_LOW_LOOPCNT 32
109 #endif
111 /* Do not prefetch for a loop that contains a function call; such a loop is
112 probably not an internal loop. */
113 #ifndef PREFETCH_NO_CALL
114 #define PREFETCH_NO_CALL 1
115 #endif
117 /* Do not prefetch accesses with an extreme stride. */
118 #ifndef PREFETCH_NO_EXTREME_STRIDE
119 #define PREFETCH_NO_EXTREME_STRIDE 1
120 #endif
122 /* Define what we mean by an "extreme" stride. */
123 #ifndef PREFETCH_EXTREME_STRIDE
124 #define PREFETCH_EXTREME_STRIDE 4096
125 #endif
127 /* Do not handle reversed order prefetches (negative stride). */
128 #ifndef PREFETCH_NO_REVERSE_ORDER
129 #define PREFETCH_NO_REVERSE_ORDER 1
130 #endif
132 /* Prefetch even if the GIV is not always executed. */
133 #ifndef PREFETCH_NOT_ALWAYS
134 #define PREFETCH_NOT_ALWAYS 0
135 #endif
137 /* If the loop requires more prefetches than the target can process in
138 parallel then don't prefetch anything in that loop. */
139 #ifndef PREFETCH_LIMIT_TO_SIMULTANEOUS
140 #define PREFETCH_LIMIT_TO_SIMULTANEOUS 1
141 #endif
143 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
144 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
146 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
147 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
148 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
150 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
151 ((REGNO) < FIRST_PSEUDO_REGISTER \
152 ? HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
155 /* Vector mapping INSN_UIDs to luids.
156 The luids are like uids but increase monotonically always.
157 We use them to see whether a jump comes from outside a given loop. */
161 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
162 number the insn is contained in. */
166 /* 1 + largest uid of any insn. */
170 /* 1 + luid of last insn. */
174 /* Number of loops detected in current function. Used as index to the
175 next few tables. */
179 /* Bound on pseudo register number before loop optimization.
180 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
183 /* The value to pass to the next call of reg_scan_update. */
186 #define obstack_chunk_alloc xmalloc
187 #define obstack_chunk_free free
188 \f
189 /* During the analysis of a loop, a chain of `struct movable's
190 is made to record all the movable insns found.
191 Then the entire chain can be scanned to decide which to move. */
193 struct movable
194 {
199 of any registers used within the LIBCALL. */
201 that must be moved with this one. */
204 may be adjusted when matching movables
205 that load the same value are found. */
207 including other movables that force this
208 or match this one. */
212 /* If PARTIAL is 1, GLOBAL means something different:
213 that the reg is live outside the range from where it is set
214 to the following label. */
218 In particular, moving it does not make it
219 invariant. */
221 load SRC, rather than copying INSN. */
223 first insn of a consecutive sets group. */
226 that we should avoid changing when clearing
227 the rest of the reg. */
231 };
236 /* Forward declarations. */
251 #if 0
253 #endif
283 rtx *));
366 {
367 rtx r1;
368 rtx r2;
372 {
373 rtx match;
374 rtx replacement;
375 rtx insn;
378 /* Nonzero iff INSN is between START and END, inclusive. */
379 #define INSN_IN_RANGE_P(INSN, START, END) \
380 (INSN_UID (INSN) < max_uid_for_loop \
381 && INSN_LUID (INSN) >= INSN_LUID (START) \
382 && INSN_LUID (INSN) <= INSN_LUID (END))
384 /* Indirect_jump_in_function is computed once per function. */
392 rtx));
393 \f
394 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
395 copy the value of the strength reduced giv to its original register. */
398 /* Cost of using a register, to normalize the benefits of a giv. */
401 void
403 {
409 }
410 \f
411 /* Compute the mapping from uids to luids.
412 LUIDs are numbers assigned to insns, like uids,
413 except that luids increase monotonically through the code.
414 Start at insn START and stop just before END. Assign LUIDs
415 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
416 static int
420 {
422 rtx insn;
425 {
428 /* Don't assign luids to line-number NOTEs, so that the distance in
429 luids between two insns is not affected by -g. */
433 else
434 /* Give a line number note the same luid as preceding insn. */
436 }
438 }
439 \f
440 /* Entry point of this file. Perform loop optimization
441 on the current function. F is the first insn of the function
442 and DUMPFILE is a stream for output of a trace of actions taken
443 (or 0 if none should be output). */
445 void
447 /* f is the first instruction of a chain of insns for one function */
448 rtx f;
451 {
452 rtx insn;
467 /* Count the number of loops. */
471 {
474 max_loop_num++;
475 }
477 /* Don't waste time if no loops. */
483 /* Get size to use for tables indexed by uids.
484 Leave some space for labels allocated by find_and_verify_loops. */
491 /* Allocate storage for array of loops. */
495 /* Find and process each loop.
496 First, find them, and record them in order of their beginnings. */
499 /* Allocate and initialize auxiliary loop information. */
504 /* Now find all register lifetimes. This must be done after
505 find_and_verify_loops, because it might reorder the insns in the
506 function. */
509 /* This must occur after reg_scan so that registers created by gcse
510 will have entries in the register tables.
512 We could have added a call to reg_scan after gcse_main in toplev.c,
513 but moving this call to init_alias_analysis is more efficient. */
516 /* See if we went too far. Note that get_max_uid already returns
517 one more that the maximum uid of all insn. */
520 /* Now reset it to the actual size we need. See above. */
523 /* find_and_verify_loops has already called compute_luids, but it
524 might have rearranged code afterwards, so we need to recompute
525 the luids now. */
528 /* Don't leave gaps in uid_luid for insns that have been
529 deleted. It is possible that the first or last insn
530 using some register has been deleted by cross-jumping.
531 Make sure that uid_luid for that former insn's uid
532 points to the general area where that insn used to be. */
534 {
538 }
543 /* Determine if the function has indirect jump. On some systems
544 this prevents low overhead loop instructions from being used. */
547 /* Now scan the loops, last ones first, since this means inner ones are done
548 before outer ones. */
550 {
555 }
557 /* If there were lexical blocks inside the loop, they have been
558 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
559 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
560 the BLOCKs as well. */
566 /* Clean up. */
571 }
572 \f
573 /* Returns the next insn, in execution order, after INSN. START and
574 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
575 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
576 insn-stream; it is used with loops that are entered near the
577 bottom. */
579 static rtx
582 rtx insn;
583 {
587 {
589 /* Go to the top of the loop, and continue there. */
591 else
592 /* We're done. */
594 }
597 /* We're done. */
601 }
603 /* Optimize one loop described by LOOP. */
605 /* ??? Could also move memory writes out of loops if the destination address
606 is invariant, the source is invariant, the memory write is not volatile,
607 and if we can prove that no read inside the loop can read this address
608 before the write occurs. If there is a read of this address after the
609 write, then we can also mark the memory read as invariant. */
611 static void
615 {
621 rtx p;
622 /* 1 if we are scanning insns that could be executed zero times. */
624 /* 1 if we are scanning insns that might never be executed
625 due to a subroutine call which might exit before they are reached. */
627 /* Jump insn that enters the loop, or 0 if control drops in. */
629 /* Number of insns in the loop. */
633 /* The SET from an insn, if it is the only SET in the insn. */
635 /* Chain describing insns movable in current loop. */
637 /* Ratio of extra register life span we can justify
638 for saving an instruction. More if loop doesn't call subroutines
639 since in that case saving an insn makes more difference
640 and more registers are available. */
642 /* Nonzero if we are scanning instructions in a sub-loop. */
650 /* Determine whether this loop starts with a jump down to a test at
651 the end. This will occur for a small number of loops with a test
652 that is too complex to duplicate in front of the loop.
654 We search for the first insn or label in the loop, skipping NOTEs.
655 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
656 (because we might have a loop executed only once that contains a
657 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
658 (in case we have a degenerate loop).
660 Note that if we mistakenly think that a loop is entered at the top
661 when, in fact, it is entered at the exit test, the only effect will be
662 slightly poorer optimization. Making the opposite error can generate
663 incorrect code. Since very few loops now start with a jump to the
664 exit test, the code here to detect that case is very conservative. */
667 p != loop_end
673 ;
677 /* If loop end is the end of the current function, then emit a
678 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
679 note insn. This is the position we use when sinking insns out of
680 the loop. */
683 else
686 /* Set up variables describing this loop. */
690 /* If loop has a jump before the first label,
691 the true entry is the target of that jump.
692 Start scan from there.
693 But record in LOOP->TOP the place where the end-test jumps
694 back to so we can scan that after the end of the loop. */
696 {
699 /* Loop entry must be unconditional jump (and not a RETURN) */
702 /* Check to see whether the jump actually
703 jumps out of the loop (meaning it's no loop).
704 This case can happen for things like
705 do {..} while (0). If this label was generated previously
706 by loop, we can't tell anything about it and have to reject
707 the loop. */
709 {
712 }
713 }
715 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
716 as required by loop_reg_used_before_p. So skip such loops. (This
717 test may never be true, but it's best to play it safe.)
719 Also, skip loops where we do not start scanning at a label. This
720 test also rejects loops starting with a JUMP_INSN that failed the
721 test above. */
725 {
730 }
732 /* Allocate extra space for REGs that might be created by load_mems.
733 We allocate a little extra slop as well, in the hopes that we
734 won't have to reallocate the regs array. */
739 {
745 }
747 /* Scan through the loop finding insns that are safe to move.
748 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
749 this reg will be considered invariant for subsequent insns.
750 We consider whether subsequent insns use the reg
751 in deciding whether it is worth actually moving.
753 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
754 and therefore it is possible that the insns we are scanning
755 would never be executed. At such times, we must make sure
756 that it is safe to execute the insn once instead of zero times.
757 When MAYBE_NEVER is 0, all insns will be executed at least once
758 so that is not a problem. */
763 {
767 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
769 #endif
771 {
778 /* Figure out what to use as a source of this insn. If a REG_EQUIV
779 note is given or if a REG_EQUAL note with a constant operand is
780 specified, use it as the source and mark that we should move
781 this insn by calling emit_move_insn rather that duplicating the
782 insn.
784 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
785 is present. */
789 else
790 {
795 {
797 /* A libcall block can use regs that don't appear in
798 the equivalent expression. To move the libcall,
799 we must move those regs too. */
801 }
802 }
804 /* For parallels, add any possible uses to the depencies, as we can't move
805 the insn without resolving them first. */
807 {
809 {
813 }
814 }
816 /* Don't try to optimize a register that was made
817 by loop-optimization for an inner loop.
818 We don't know its life-span, so we can't compute the benefit. */
820 ;
822 than the one where it is set (meaning that
823 something after this point in the loop might
824 depend on its value before the set). */
826 /* And the set is not guaranteed to be executed once
827 the loop starts, or the value before the set is
828 needed before the set occurs...
830 ??? Note we have quadratic behaviour here, mitigated
831 by the fact that the previous test will often fail for
832 large loops. Rather than re-scanning the entire loop
833 each time for register usage, we should build tables
834 of the register usage and use them here instead. */
835 && (maybe_never
837 /* It is unsafe to move the set.
839 This code used to consider it OK to move a set of a variable
840 which was not created by the user and not used in an exit test.
841 That behavior is incorrect and was removed. */
842 ;
847 || (tem1
848 = consec_sets_invariant_p
851 p)))
852 /* If the insn can cause a trap (such as divide by zero),
853 can't move it unless it's guaranteed to be executed
854 once loop is entered. Even a function call might
855 prevent the trap insn from being reached
856 (since it might exit!) */
859 {
863 /* A potential lossage is where we have a case where two insns
864 can be combined as long as they are both in the loop, but
865 we move one of them outside the loop. For large loops,
866 this can lose. The most common case of this is the address
867 of a function being called.
869 Therefore, if this register is marked as being used exactly
870 once if we are in a loop with calls (a "large loop"), see if
871 we can replace the usage of this register with the source
872 of this SET. If we can, delete this insn.
874 Don't do this if P has a REG_RETVAL note or if we have
875 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
887 && (! SMALL_REGISTER_CLASSES
890 /* This test is not redundant; SET_SRC (set) might be
891 a call-clobbered register and the life of REGNO
892 might span a call. */
898 {
899 /* Replace any usage in a REG_EQUAL note. Must copy the
900 new source, so that we don't get rtx sharing between the
901 SET_SOURCE and REG_NOTES of insn p. */
910 }
928 /* Set M->cond if either loop_invariant_p
929 or consec_sets_invariant_p returned 2
930 (only conditionally invariant). */
940 /* Add M to the end of the chain MOVABLES. */
944 {
945 /* It is possible for the first instruction to have a
946 REG_EQUAL note but a non-invariant SET_SRC, so we must
947 remember the status of the first instruction in case
948 the last instruction doesn't have a REG_EQUAL note. */
951 /* Skip this insn, not checking REG_LIBCALL notes. */
953 /* Skip the consecutive insns, if there are any. */
955 /* Back up to the last insn of the consecutive group. */
958 /* We must now reset m->move_insn, m->is_equiv, and possibly
959 m->set_src to correspond to the effects of all the
960 insns. */
964 else
965 {
969 else
972 }
974 }
975 }
976 /* If this register is always set within a STRICT_LOW_PART
977 or set to zero, then its high bytes are constant.
978 So clear them outside the loop and within the loop
979 just load the low bytes.
980 We must check that the machine has an instruction to do so.
981 Also, if the value loaded into the register
982 depends on the same register, this cannot be done. */
992 {
995 {
1009 /* If the insn may not be executed on some cycles,
1010 we can't clear the whole reg; clear just high part.
1011 Not even if the reg is used only within this loop.
1012 Consider this:
1013 while (1)
1014 while (s != t) {
1015 if (foo ()) x = *s;
1016 use (x);
1017 }
1018 Clearing x before the inner loop could clobber a value
1019 being saved from the last time around the outer loop.
1020 However, if the reg is not used outside this loop
1021 and all uses of the register are in the same
1022 basic block as the store, there is no problem.
1024 If this insn was made by loop, we don't know its
1025 INSN_LUID and hence must make a conservative
1026 assumption. */
1029 || (labels_in_range_p
1033 else
1042 /* Add M to the end of the chain MOVABLES. */
1044 }
1045 }
1046 }
1047 /* Past a call insn, we get to insns which might not be executed
1048 because the call might exit. This matters for insns that trap.
1049 Constant and pure call insns always return, so they don't count. */
1052 /* Past a label or a jump, we get to insns for which we
1053 can't count on whether or how many times they will be
1054 executed during each iteration. Therefore, we can
1055 only move out sets of trivial variables
1056 (those not used after the loop). */
1057 /* Similar code appears twice in strength_reduce. */
1059 /* If we enter the loop in the middle, and scan around to the
1060 beginning, don't set maybe_never for that. This must be an
1061 unconditional jump, otherwise the code at the top of the
1062 loop might never be executed. Unconditional jumps are
1063 followed by a barrier then the loop_end. */
1069 {
1070 /* At the virtual top of a converted loop, insns are again known to
1071 be executed: logically, the loop begins here even though the exit
1072 code has been duplicated. */
1076 loop_depth++;
1078 loop_depth--;
1079 }
1080 }
1082 /* If one movable subsumes another, ignore that other. */
1086 /* For each movable insn, see if the reg that it loads
1087 leads when it dies right into another conditionally movable insn.
1088 If so, record that the second insn "forces" the first one,
1089 since the second can be moved only if the first is. */
1093 /* See if there are multiple movable insns that load the same value.
1094 If there are, make all but the first point at the first one
1095 through the `match' field, and add the priorities of them
1096 all together as the priority of the first. */
1100 /* Now consider each movable insn to decide whether it is worth moving.
1101 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1103 Generally this increases code size, so do not move moveables when
1104 optimizing for code size. */
1107 {
1110 /* Recalculate regs->array if move_movables has created new
1111 registers. */
1113 {
1119 ;
1124 }
1125 }
1127 /* Now candidates that still are negative are those not moved.
1128 Change regs->array[I].set_in_loop to indicate that those are not actually
1129 invariant. */
1134 /* Now that we've moved some things out of the loop, we might be able to
1135 hoist even more memory references. */
1138 /* Recalculate regs->array if load_mems has created new registers. */
1146 ;
1153 {
1155 /* Ensure our label doesn't go away. */
1166 }
1169 /* The movable information is required for strength reduction. */
1175 }
1176 \f
1177 /* Add elements to *OUTPUT to record all the pseudo-regs
1178 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1180 void
1184 {
1192 {
1210 }
1214 {
1218 {
1227 }
1228 }
1229 }
1230 \f
1231 /* Check what regs are referred to in the libcall block ending with INSN,
1232 aside from those mentioned in the equivalent value.
1233 If there are none, return 0.
1234 If there are one or more, return an EXPR_LIST containing all of them. */
1236 rtx
1239 {
1244 /* First, find all the regs used in the libcall block
1245 that are not mentioned as inputs to the result. */
1248 {
1253 }
1256 }
1257 \f
1258 /* Return 1 if all uses of REG
1259 are between INSN and the end of the basic block. */
1261 static int
1264 {
1266 rtx p;
1271 /* Search this basic block for the already recorded last use of the reg. */
1273 {
1275 {
1281 /* Ordinary insn: if this is the last use, we win. */
1287 /* Jump insn: if this is the last use, we win. */
1290 /* Otherwise, it's the end of the basic block, so we lose. */
1295 /* It's the end of the basic block, so we lose. */
1300 }
1301 }
1303 /* The "last use" that was recorded can't be found after the first
1304 use. This can happen when the last use was deleted while
1305 processing an inner loop, this inner loop was then completely
1306 unrolled, and the outer loop is always exited after the inner loop,
1307 so that everything after the first use becomes a single basic block. */
1309 }
1310 \f
1311 /* Compute the benefit of eliminating the insns in the block whose
1312 last insn is LAST. This may be a group of insns used to compute a
1313 value directly or can contain a library call. */
1315 static int
1317 rtx last;
1318 {
1319 rtx insn;
1324 {
1327 routine. */
1331 benefit++;
1332 }
1335 }
1336 \f
1337 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1339 static rtx
1341 rtx insn;
1343 {
1345 {
1346 rtx temp;
1348 /* If first insn of libcall sequence, skip to end. */
1349 /* Do this at start of loop, since INSN is guaranteed to
1350 be an insn here. */
1355 do
1358 }
1361 }
1363 /* Ignore any movable whose insn falls within a libcall
1364 which is part of another movable.
1365 We make use of the fact that the movable for the libcall value
1366 was made later and so appears later on the chain. */
1368 static void
1371 {
1375 {
1376 /* Is this a movable for the value of a libcall? */
1379 {
1380 rtx insn;
1381 /* Check for earlier movables inside that range,
1382 and mark them invalid. We cannot use LUIDs here because
1383 insns created by loop.c for prior loops don't have LUIDs.
1384 Rather than reject all such insns from movables, we just
1385 explicitly check each insn in the libcall (since invariant
1386 libcalls aren't that common). */
1391 }
1392 }
1393 }
1395 /* For each movable insn, see if the reg that it loads
1396 leads when it dies right into another conditionally movable insn.
1397 If so, record that the second insn "forces" the first one,
1398 since the second can be moved only if the first is. */
1400 static void
1403 {
1407 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1409 {
1412 /* ??? Could this be a bug? What if CSE caused the
1413 register of M1 to be used after this insn?
1414 Since CSE does not update regno_last_uid,
1415 this insn M->insn might not be where it dies.
1416 But very likely this doesn't matter; what matters is
1417 that M's reg is computed from M1's reg. */
1422 /* If m->consec, m->set_src isn't valid. */
1426 /* Increase the priority of the moving the first insn
1427 since it permits the second to be moved as well. */
1429 {
1433 }
1434 }
1435 }
1436 \f
1437 /* Find invariant expressions that are equal and can be combined into
1438 one register. */
1440 static void
1444 {
1449 /* Regs that are set more than once are not allowed to match
1450 or be matched. I'm no longer sure why not. */
1451 /* Only pseudo registers are allowed to match or be matched,
1452 since move_movables does not validate the change. */
1453 /* Perhaps testing m->consec_sets would be more appropriate here? */
1459 {
1466 /* We want later insns to match the first one. Don't make the first
1467 one match any later ones. So start this loop at m->next. */
1472 /* A reg used outside the loop mustn't be eliminated. */
1474 /* A reg used for zero-extending mustn't be eliminated. */
1477 ||
1478 (
1479 /* Can combine regs with different modes loaded from the
1480 same constant only if the modes are the same or
1481 if both are integer modes with M wider or the same
1482 width as M1. The check for integer is redundant, but
1483 safe, since the only case of differing destination
1484 modes with equal sources is when both sources are
1485 VOIDmode, i.e., CONST_INT. */
1491 /* See if the source of M1 says it matches M. */
1498 {
1504 }
1505 }
1507 /* Now combine the regs used for zero-extension.
1508 This can be done for those not marked `global'
1509 provided their lives don't overlap. */
1513 {
1516 /* Combine all the registers for extension from mode MODE.
1517 Don't combine any that are used outside this loop. */
1521 {
1528 {
1529 /* First one: don't check for overlap, just record it. */
1532 }
1534 /* Make sure they extend to the same mode.
1535 (Almost always true.) */
1539 /* We already have one: check for overlap with those
1540 already combined together. */
1547 /* No overlap: we can combine this with the others. */
1553 overlap:
1554 ;
1555 }
1556 }
1558 /* Clean up. */
1560 }
1562 /* Returns the number of movable instructions in LOOP that were not
1563 moved outside the loop. */
1565 static int
1568 {
1577 }
1579 \f
1580 /* Return 1 if regs X and Y will become the same if moved. */
1582 static int
1586 {
1603 }
1605 /* Return 1 if X and Y are identical-looking rtx's.
1606 This is the Lisp function EQUAL for rtx arguments.
1608 If two registers are matching movables or a movable register and an
1609 equivalent constant, consider them equal. */
1611 static int
1616 {
1630 /* If we have a register and a constant, they may sometimes be
1631 equal. */
1634 {
1639 }
1642 {
1647 }
1649 /* Otherwise, rtx's of different codes cannot be equal. */
1653 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1654 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1659 /* These three types of rtx's can be compared nonrecursively. */
1668 /* Compare the elements. If any pair of corresponding elements
1669 fail to match, return 0 for the whole things. */
1673 {
1675 {
1687 /* Two vectors must have the same length. */
1691 /* And the corresponding elements must match. */
1710 /* These are just backpointers, so they don't matter. */
1716 /* It is believed that rtx's at this level will never
1717 contain anything but integers and other rtx's,
1718 except for within LABEL_REFs and SYMBOL_REFs. */
1721 }
1722 }
1724 }
1725 \f
1726 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1727 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1728 references is incremented once for each added note. */
1730 static void
1732 rtx x;
1733 rtx insns;
1734 {
1738 rtx insn;
1741 {
1742 /* This code used to ignore labels that referred to dispatch tables to
1743 avoid flow generating (slighly) worse code.
1745 We no longer ignore such label references (see LABEL_REF handling in
1746 mark_jump_label for additional information). */
1749 {
1754 }
1755 }
1759 {
1765 }
1766 }
1767 \f
1768 /* Scan MOVABLES, and move the insns that deserve to be moved.
1769 If two matching movables are combined, replace one reg with the
1770 other throughout. */
1772 static void
1778 {
1783 rtx p;
1786 /* Map of pseudo-register replacements to handle combining
1787 when we move several insns that load the same value
1788 into different pseudo-registers. */
1793 {
1794 /* Describe this movable insn. */
1797 {
1818 }
1820 /* Ignore the insn if it's already done (it matched something else).
1821 Otherwise, see if it is now safe to move. */
1833 {
1835 rtx p;
1838 /* We have an insn that is safe to move.
1839 Compute its desirability. */
1850 /* An insn MUST be moved if we already moved something else
1851 which is safe only if this one is moved too: that is,
1852 if already_moved[REGNO] is nonzero. */
1854 /* An insn is desirable to move if the new lifetime of the
1855 register is no more than THRESHOLD times the old lifetime.
1856 If it's not desirable, it means the loop is so big
1857 that moving won't speed things up much,
1858 and it is liable to make register usage worse. */
1860 /* It is also desirable to move if it can be moved at no
1861 extra cost because something else was already moved. */
1864 || flag_move_all_movables
1869 {
1874 /* Now move the insns that set the reg. */
1877 {
1880 /* Find the end of this chain of matching regs.
1881 Thus, we load each reg in the chain from that one reg.
1882 And that reg is loaded with 0 directly,
1883 since it has ->match == 0. */
1889 /* Mark the moved, invariant reg as being allowed to
1890 share a hard reg with the other matching invariant. */
1894 regs_may_share
1897 regs_may_share));
1905 }
1906 /* If we are to re-generate the item being moved with a
1907 new move insn, first delete what we have and then emit
1908 the move insn before the loop. */
1910 {
1914 {
1915 /* If this is the first insn of a library call sequence,
1916 skip to the end. */
1921 /* If this is the last insn of a libcall sequence, then
1922 delete every insn in the sequence except the last.
1923 The last insn is handled in the normal manner. */
1926 {
1930 }
1935 /* simplify_giv_expr expects that it can walk the insns
1936 at m->insn forwards and see this old sequence we are
1937 tossing here. delete_insn does preserve the next
1938 pointers, but when we skip over a NOTE we must fix
1939 it up. Otherwise that code walks into the non-deleted
1940 insn stream. */
1943 }
1962 /* The more regs we move, the less we like moving them. */
1964 }
1965 else
1966 {
1968 {
1971 /* If first insn of libcall sequence, skip to end. */
1972 /* Do this at start of loop, since p is guaranteed to
1973 be an insn here. */
1978 /* If last insn of libcall sequence, move all
1979 insns except the last before the loop. The last
1980 insn is handled in the normal manner. */
1983 {
1991 {
1992 rtx body;
1993 rtx n;
1994 rtx next;
2001 /* Find the next insn after TEMP,
2002 not counting USE or NOTE insns. */
2010 /* If that is the call, this may be the insn
2011 that loads the function address.
2013 Extract the function address from the insn
2014 that loads it into a register.
2015 If this insn was cse'd, we get incorrect code.
2017 So emit a new move insn that copies the
2018 function address into the register that the
2019 call insn will use. flow.c will delete any
2020 redundant stores that we have created. */
2025 NULL_RTX)))
2026 {
2032 }
2033 /* We have the call insn.
2034 If it uses the register we suspect it might,
2035 load it with the correct address directly. */
2040 gen_move_insn
2044 {
2046 /* Because the USAGE information potentially
2047 contains objects other than hard registers
2048 we need to copy it. */
2052 }
2053 else
2062 }
2065 }
2067 {
2068 /* P sets REG to zero; but we should clear only
2069 the bits that are not covered by the mode
2070 m->savemode. */
2072 rtx sequence;
2073 rtx tem;
2076 tem = expand_simple_binop
2089 }
2091 {
2093 /* Because the USAGE information potentially
2094 contains objects other than hard registers
2095 we need to copy it. */
2099 }
2101 {
2102 rtx seq;
2103 /* The SET_SRC might not be invariant, so we must
2104 use the REG_EQUAL note. */
2117 }
2118 else
2122 {
2126 /* If there is a REG_EQUAL note present whose value
2127 is not loop invariant, then delete it, since it
2128 may cause problems with later optimization passes.
2129 It is possible for cse to create such notes
2130 like this as a result of record_jump_cond. */
2135 }
2144 /* If library call, now fix the REG_NOTES that contain
2145 insn pointers, namely REG_LIBCALL on FIRST
2146 and REG_RETVAL on I1. */
2148 {
2152 }
2158 /* simplify_giv_expr expects that it can walk the insns
2159 at m->insn forwards and see this old sequence we are
2160 tossing here. delete_insn does preserve the next
2161 pointers, but when we skip over a NOTE we must fix
2162 it up. Otherwise that code walks into the non-deleted
2163 insn stream. */
2166 }
2168 /* The more regs we move, the less we like moving them. */
2170 }
2172 /* Any other movable that loads the same register
2173 MUST be moved. */
2176 /* This reg has been moved out of one loop. */
2179 /* The reg set here is now invariant. */
2181 {
2185 }
2189 /* Change the length-of-life info for the register
2190 to say it lives at least the full length of this loop.
2191 This will help guide optimizations in outer loops. */
2194 /* This is the old insn before all the moved insns.
2195 We can't use the moved insn because it is out of range
2196 in uid_luid. Only the old insns have luids. */
2201 /* Combine with this moved insn any other matching movables. */
2206 {
2207 rtx temp;
2209 /* Schedule the reg loaded by M1
2210 for replacement so that shares the reg of M.
2211 If the modes differ (only possible in restricted
2212 circumstances, make a SUBREG.
2214 Note this assumes that the target dependent files
2215 treat REG and SUBREG equally, including within
2216 GO_IF_LEGITIMATE_ADDRESS and in all the
2217 predicates since we never verify that replacing the
2218 original register with a SUBREG results in a
2219 recognizable insn. */
2222 else
2227 /* Get rid of the matching insn
2228 and prevent further processing of it. */
2231 /* if library call, delete all insns. */
2233 NULL_RTX)))
2235 else
2238 /* Any other movable that loads the same register
2239 MUST be moved. */
2242 /* The reg merged here is now invariant,
2243 if the reg it matches is invariant. */
2245 {
2249 i++)
2251 }
2252 }
2253 }
2256 }
2262 }
2267 /* Go through all the instructions in the loop, making
2268 all the register substitutions scheduled in REG_MAP. */
2272 {
2276 }
2278 /* Clean up. */
2281 }
2284 static void
2288 {
2291 else
2294 }
2297 static void
2300 {
2305 {
2308 }
2309 }
2310 \f
2311 #if 0
2312 /* Scan X and replace the address of any MEM in it with ADDR.
2313 REG is the address that MEM should have before the replacement. */
2315 static void
2318 {
2327 {
2339 /* Short cut for very common case. */
2344 /* Short cut for very common case. */
2349 /* If this MEM uses a reg other than the one we expected,
2350 something is wrong. */
2358 }
2362 {
2366 {
2370 }
2371 }
2372 }
2373 #endif
2374 \f
2375 /* Return the number of memory refs to addresses that vary
2376 in the rtx X. */
2378 static int
2381 rtx x;
2382 {
2393 {
2410 }
2415 {
2419 {
2423 }
2424 }
2426 }
2427 \f
2428 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2429 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2430 `unknown_address_altered', `unknown_constant_address_altered', and
2431 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2432 list `store_mems' in LOOP. */
2434 static void
2437 {
2439 rtx insn;
2443 /* The label after END. Jumping here is just like falling off the
2444 end of the loop. We use next_nonnote_insn instead of next_label
2445 as a hedge against the (pathological) case where some actual insn
2446 might end up between the two. */
2468 {
2470 {
2473 }
2474 }
2478 {
2480 {
2483 {
2485 /* Count number of loops contained in this one. */
2487 }
2494 {
2497 }
2507 {
2511 {
2516 {
2519 }
2520 else
2521 {
2524 }
2526 do
2527 {
2529 {
2531 {
2532 /* Something tricky. */
2535 }
2538 {
2539 /* A jump outside the current loop. */
2542 }
2543 }
2547 }
2549 }
2550 else
2551 {
2552 /* A return, or something tricky. */
2554 }
2555 }
2556 /* FALLTHRU */
2577 }
2578 }
2580 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2582 anywhere. */
2584 /* We don't want loads for MEMs moved to a location before the
2585 one at which their stack memory becomes allocated. (Note
2586 that this is not a problem for malloc, etc., since those
2587 require actual function calls. */
2588 && ! current_function_calls_alloca
2589 /* There are ways to leave the loop other than falling off the
2590 end. */
2596 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2597 that loop_invariant_p and load_mems can use true_dependence
2598 to determine what is really clobbered. */
2600 {
2603 loop_info->store_mems
2605 }
2607 {
2611 loop_info->store_mems
2613 }
2614 }
2615 \f
2616 /* Invalidate all loops containing LABEL. */
2618 static void
2620 rtx label;
2621 {
2625 }
2627 /* Scan the function looking for loops. Record the start and end of each loop.
2628 Also mark as invalid loops any loops that contain a setjmp or are branched
2629 to from outside the loop. */
2631 static void
2633 rtx f;
2635 {
2636 rtx insn;
2637 rtx label;
2647 /* If there are jumps to undefined labels,
2648 treat them as jumps out of any/all loops.
2649 This also avoids writing past end of tables when there are no loops. */
2652 /* Find boundaries of loops, mark which loops are contained within
2653 loops, and invalidate loops that have setjmp. */
2658 {
2661 {
2665 num_loops++;
2689 }
2693 {
2694 /* In this case, we must invalidate our current loop and any
2695 enclosing loop. */
2697 {
2703 }
2704 }
2706 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2707 enclosing loop, but this doesn't matter. */
2709 }
2711 /* Any loop containing a label used in an initializer must be invalidated,
2712 because it can be jumped into from anywhere. */
2716 /* Any loop containing a label used for an exception handler must be
2717 invalidated, because it can be jumped into from anywhere. */
2720 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2721 loop that it is not contained within, that loop is marked invalid.
2722 If any INSN or CALL_INSN uses a label's address, then the loop containing
2723 that label is marked invalid, because it could be jumped into from
2724 anywhere.
2726 Also look for blocks of code ending in an unconditional branch that
2727 exits the loop. If such a block is surrounded by a conditional
2728 branch around the block, move the block elsewhere (see below) and
2729 invert the jump to point to the code block. This may eliminate a
2730 label in our loop and will simplify processing by both us and a
2731 possible second cse pass. */
2735 {
2739 {
2743 }
2750 /* See if this is an unconditional branch outside the loop. */
2758 {
2759 rtx p;
2765 /* Go backwards until we reach the start of the loop, a label,
2766 or a JUMP_INSN. */
2773 ;
2775 /* Check for the case where we have a jump to an inner nested
2776 loop, and do not perform the optimization in that case. */
2779 {
2782 {
2787 }
2788 }
2790 /* Make sure that the target of P is within the current loop. */
2796 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2797 we have a block of code to try to move.
2799 We look backward and then forward from the target of INSN
2800 to find a BARRIER at the same loop depth as the target.
2801 If we find such a BARRIER, we make a new label for the start
2802 of the block, invert the jump in P and point it to that label,
2803 and move the block of code to the spot we found. */
2808 /* Just ignore jumps to labels that were never emitted.
2809 These always indicate compilation errors. */
2813 /* If it's not safe to move the sequence, then we
2814 mustn't try. */
2817 {
2818 rtx target
2822 rtx tmp;
2824 /* Search for possible garbage past the conditional jumps
2825 and look for the last barrier. */
2833 /* Don't move things inside a tablejump. */
2846 /* Don't move things inside a tablejump. */
2857 {
2861 /* Ensure our label doesn't go away. */
2864 /* Verify that uid_loop is large enough and that
2865 we can invert P. */
2867 {
2870 /* If no suitable BARRIER was found, create a suitable
2871 one before TARGET. Since TARGET is a fall through
2872 path, we'll need to insert an jump around our block
2873 and add a BARRIER before TARGET.
2875 This creates an extra unconditional jump outside
2876 the loop. However, the benefits of removing rarely
2877 executed instructions from inside the loop usually
2878 outweighs the cost of the extra unconditional jump
2879 outside the loop. */
2881 {
2882 rtx temp;
2889 }
2891 /* Include the BARRIER after INSN and copy the
2892 block after LOC. */
2897 /* All those insns are now in TARGET_LOOP. */
2903 /* The label jumped to by INSN is no longer a loop
2904 exit. Unless INSN does not have a label (e.g.,
2905 it is a RETURN insn), search loop->exit_labels
2906 to find its label_ref, and remove it. Also turn
2907 off LABEL_OUTSIDE_LOOP_P bit. */
2909 {
2911 r;
2914 {
2918 else
2921 }
2927 /* If we didn't find it, then something is
2928 wrong. */
2931 }
2933 /* P is now a jump outside the loop, so it must be put
2934 in loop->exit_labels, and marked as such.
2935 The easiest way to do this is to just call
2936 mark_loop_jump again for P. */
2939 /* If INSN now jumps to the insn after it,
2940 delete INSN. */
2945 }
2947 /* Continue the loop after where the conditional
2948 branch used to jump, since the only branch insn
2949 in the block (if it still remains) is an inter-loop
2950 branch and hence needs no processing. */
2956 /* This loop will be continued with NEXT_INSN (insn). */
2958 }
2959 }
2960 }
2961 }
2962 }
2964 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2965 loops it is contained in, mark the target loop invalid.
2967 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2969 static void
2971 rtx x;
2973 {
2979 {
2991 /* There could be a label reference in here. */
3003 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3015 /* Link together all labels that branch outside the loop. This
3016 is used by final_[bg]iv_value and the loop unrolling code. Also
3017 mark this LABEL_REF so we know that this branch should predict
3018 false. */
3020 /* A check to make sure the label is not in an inner nested loop,
3021 since this does not count as a loop exit. */
3023 {
3028 }
3029 else
3033 {
3042 }
3044 /* If this is inside a loop, but not in the current loop or one enclosed
3045 by it, it invalidates at least one loop. */
3050 /* We must invalidate every nested loop containing the target of this
3051 label, except those that also contain the jump insn. */
3054 {
3055 /* Stop when we reach a loop that also contains the jump insn. */
3060 /* If we get here, we know we need to invalidate a loop. */
3067 }
3071 /* If this is not setting pc, ignore. */
3093 /* Strictly speaking this is not a jump into the loop, only a possible
3094 jump out of the loop. However, we have no way to link the destination
3095 of this jump onto the list of exit labels. To be safe we mark this
3096 loop and any containing loops as invalid. */
3098 {
3100 {
3106 }
3107 }
3109 }
3110 }
3111 \f
3112 /* Return nonzero if there is a label in the range from
3113 insn INSN to and including the insn whose luid is END
3114 INSN must have an assigned luid (i.e., it must not have
3115 been previously created by loop.c). */
3117 static int
3119 rtx insn;
3121 {
3123 {
3127 }
3130 }
3132 /* Record that a memory reference X is being set. */
3134 static void
3136 rtx x;
3137 rtx y ATTRIBUTE_UNUSED;
3139 {
3145 /* Count number of memory writes.
3146 This affects heuristics in strength_reduce. */
3149 /* BLKmode MEM means all memory is clobbered. */
3151 {
3154 else
3158 }
3162 }
3164 /* X is a value modified by an INSN that references a biv inside a loop
3165 exit test (ie, X is somehow related to the value of the biv). If X
3166 is a pseudo that is used more than once, then the biv is (effectively)
3167 used more than once. DATA is a pointer to a loop_regs structure. */
3169 static void
3171 rtx x;
3172 rtx y ATTRIBUTE_UNUSED;
3174 {
3189 /* If we do not have usage information, or if we know the register
3190 is used more than once, note that fact for check_dbra_loop. */
3195 }
3196 \f
3197 /* Return nonzero if the rtx X is invariant over the current loop.
3199 The value is 2 if we refer to something only conditionally invariant.
3201 A memory ref is invariant if it is not volatile and does not conflict
3202 with anything stored in `loop_info->store_mems'. */
3204 int
3207 rtx x;
3208 {
3215 rtx mem_list_entry;
3221 {
3229 /* A LABEL_REF is normally invariant, however, if we are unrolling
3230 loops, and this label is inside the loop, then it isn't invariant.
3231 This is because each unrolled copy of the loop body will have
3232 a copy of this label. If this was invariant, then an insn loading
3233 the address of this label into a register might get moved outside
3234 the loop, and then each loop body would end up using the same label.
3236 We don't know the loop bounds here though, so just fail for all
3237 labels. */
3240 else
3249 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3250 since the reg might be set by initialization within the loop. */
3267 /* Volatile memory references must be rejected. Do this before
3268 checking for read-only items, so that volatile read-only items
3269 will be rejected also. */
3273 /* See if there is any dependence between a store and this load. */
3276 {
3282 }
3284 /* It's not invalidated by a store in memory
3285 but we must still verify the address is invariant. */
3289 /* Don't mess with insns declared volatile. */
3296 }
3300 {
3302 {
3308 }
3310 {
3313 {
3319 }
3321 }
3322 }
3325 }
3326 \f
3327 /* Return nonzero if all the insns in the loop that set REG
3328 are INSN and the immediately following insns,
3329 and if each of those insns sets REG in an invariant way
3330 (not counting uses of REG in them).
3332 The value is 2 if some of these insns are only conditionally invariant.
3334 We assume that INSN itself is the first set of REG
3335 and that its source is invariant. */
3337 static int
3342 {
3346 rtx temp;
3347 /* Number of sets we have to insist on finding after INSN. */
3353 /* If N_SETS hit the limit, we can't rely on its value. */
3360 {
3362 rtx set;
3367 /* If library call, skip to end of it. */
3376 {
3381 {
3382 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3383 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3384 notes are OK. */
3390 }
3391 }
3393 count--;
3395 {
3398 }
3399 }
3402 /* If loop_invariant_p ever returned 2, we return 2. */
3404 }
3406 #if 0
3407 /* I don't think this condition is sufficient to allow INSN
3408 to be moved, so we no longer test it. */
3410 /* Return 1 if all insns in the basic block of INSN and following INSN
3411 that set REG are invariant according to TABLE. */
3413 static int
3417 {
3422 {
3431 {
3434 }
3435 }
3436 }
3438 \f
3439 /* Look at all uses (not sets) of registers in X. For each, if it is
3440 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3441 a different insn, set USAGE[REGNO] to const0_rtx. */
3443 static void
3446 rtx insn;
3447 rtx x;
3448 {
3460 {
3461 /* Don't count SET_DEST if it is a REG; otherwise count things
3462 in SET_DEST because if a register is partially modified, it won't
3463 show up as a potential movable so we don't care how USAGE is set
3464 for it. */
3468 }
3469 else
3471 {
3477 }
3478 }
3479 \f
3480 /* Count and record any set in X which is contained in INSN. Update
3481 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3482 in X. */
3484 static void
3489 {
3491 /* Don't move a reg that has an explicit clobber.
3492 It's not worth the pain to try to do it correctly. */
3496 {
3504 {
3508 {
3509 /* If this is the first setting of this reg
3510 in current basic block, and it was set before,
3511 it must be set in two basic blocks, so it cannot
3512 be moved out of the loop. */
3516 /* If this is not first setting in current basic block,
3517 see if reg was used in between previous one and this.
3518 If so, neither one can be moved. */
3525 }
3526 }
3527 }
3528 }
3529 \f
3530 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3531 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3532 contained in insn INSN is used by any insn that precedes INSN in
3533 cyclic order starting from the loop entry point.
3535 We don't want to use INSN_LUID here because if we restrict INSN to those
3536 that have a valid INSN_LUID, it means we cannot move an invariant out
3537 from an inner loop past two loops. */
3539 static int
3543 {
3545 rtx p;
3547 /* Scan forward checking for register usage. If we hit INSN, we
3548 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3550 {
3556 }
3559 }
3560 \f
3562 /* Information we collect about arrays that we might want to prefetch. */
3563 struct prefetch_info
3564 {
3568 index. */
3569 HOST_WIDE_INT index;
3571 iteration. */
3573 prefetch area in one iteration. */
3575 This is set only for loops with known
3576 iteration counts and is 0xffffffff
3577 otherwise. */
3580 /* 1 for those chosen for prefetching. */
3582 /* 1 for those chosen for prefetching. */
3583 };
3585 /* Data used by check_store function. */
3586 struct check_store_data
3587 {
3588 rtx mem_address;
3590 };
3596 /* Set mem_write when mem_address is found. Used as callback to
3597 note_stores. */
3598 static void
3602 {
3607 }
3608 \f
3609 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3610 important to get some addresses combined. Later more sophisticated
3611 transformations can be added when necesary.
3613 ??? Same trick with swapping operand is done at several other places.
3614 It can be nice to develop some common way to handle this. */
3616 static int
3619 {
3633 {
3638 }
3639 /* Compare the elements. If any pair of corresponding elements fails to
3640 match, return 0 for the whole thing. */
3644 {
3646 {
3658 /* Two vectors must have the same length. */
3662 /* And the corresponding elements must match. */
3680 /* These are just backpointers, so they don't matter. */
3686 /* It is believed that rtx's at this level will never
3687 contain anything but integers and other rtx's,
3688 except for within LABEL_REFs and SYMBOL_REFs. */
3691 }
3692 }
3694 }
3695 \f
3696 /* Remove constant addition value from the expression X (when present)
3697 and return it. */
3699 static HOST_WIDE_INT
3702 {
3706 /* Avoid clobbering a shared CONST expression. */
3708 {
3712 {
3715 }
3717 }
3720 {
3723 }
3725 /* For plus expression recurse on ourself. */
3727 {
3731 /* In case our parameter was constant, remove extra zero from the
3732 expression. */
3737 }
3740 }
3742 /* Attempt to identify accesses to arrays that are most likely to cause cache
3743 misses, and emit prefetch instructions a few prefetch blocks forward.
3745 To detect the arrays we use the GIV information that was collected by the
3746 strength reduction pass.
3748 The prefetch instructions are generated after the GIV information is done
3749 and before the strength reduction process. The new GIVs are injected into
3750 the strength reduction tables, so the prefetch addresses are optimized as
3751 well.
3753 GIVs are split into base address, stride, and constant addition values.
3754 GIVs with the same address, stride and close addition values are combined
3755 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3756 for write instructions can be used for the block we write to, on machines
3757 that support write prefetches.
3759 Several heuristics are used to determine when to prefetch. They are
3760 controlled by defined symbols that can be overridden for each target. */
3762 static void
3765 {
3779 /* Consider only loops w/o calls. When a call is done, the loop is probably
3780 slow enough to read the memory. */
3782 {
3787 }
3792 {
3797 }
3799 /* Search all induction variables and pick those interesting for the prefetch
3800 machinery. */
3802 {
3808 /* Expect all BIVs to be executed in each iteration. This makes our
3809 analysis more conservative. */
3811 {
3812 /* Discard non-constant additions that we can't handle well yet, and
3813 BIVs that are executed multiple times; such BIVs ought to be
3814 handled in the nested loop. We accept not_every_iteration BIVs,
3815 since these only result in larger strides and make our
3816 heuristics more conservative.
3817 ??? What does the last sentence mean? */
3819 {
3821 {
3827 }
3829 }
3832 {
3834 {
3840 }
3842 }
3846 }
3852 {
3853 rtx address;
3854 rtx temp;
3857 HOST_WIDE_INT stride;
3861 /* There are several reasons why an induction variable is not
3862 interesting to us. */
3864 /* We are interested only in constant stride memory references
3865 in order to be able to compute density easily. */
3867 /* Don't handle reversed order prefetches, since they are usually
3868 ineffective. Later we may be able to reverse such BIVs. */
3869 || (PREFETCH_NO_REVERSE_ORDER
3871 /* Prefetching of accesses with such an extreme stride is probably
3872 not worthwhile, either. */
3873 || (PREFETCH_NO_EXTREME_STRIDE
3875 /* Ignore GIVs with varying add values; we can't predict the
3876 value for the next iteration. */
3878 /* Ignore GIVs in the nested loops; they ought to have been
3879 handled already. */
3881 {
3886 }
3888 /* Determine the pointer to the basic array we are examining. It is
3889 the sum of the BIV's initial value and the GIV's add_val. */
3902 /* When the GIV is not always executed, we might be better off by
3903 not dirtying the cache pages. */
3907 /* Attempt to find another prefetch to the same array and see if we
3908 can merge this one. */
3912 {
3913 /* In case both access same array (same location
3914 just with small difference in constant indexes), merge
3915 the prefetches. Just do the later and the earlier will
3916 get prefetched from previous iteration.
3917 4096 is artificial threshold. It should not be too small,
3918 but also not bigger than small portion of memory usually
3919 traversed by single loop. */
3921 {
3930 }
3933 {
3938 }
3939 }
3941 /* Merging failed. */
3943 {
3951 num_prefetches++;
3953 {
3958 }
3959 }
3960 }
3961 }
3964 {
3965 /* Attempt to calculate the number of bytes fetched by the loop.
3966 Avoid overflow. */
3971 else
3974 /* Prefetch is worthwhile only when the loads/stores are dense. */
3979 {
3984 }
3985 else
3989 {
3993 num_real_write_prefetches
3995 }
3996 }
3999 {
4001 {
4016 }
4020 }
4031 {
4033 {
4038 {
4040 rtx insn;
4045 /* We can save some effort by offsetting the address on
4046 architectures with offsettable memory references. */
4049 else
4050 {
4056 }
4058 /* Make sure the address operand is valid for prefetch. */
4065 before_insn);
4067 /* Check all insns emitted and record the new GIV
4068 information. */
4071 {
4076 }
4077 }
4078 }
4081 {
4084 /* Emit INSNs before the loop to fetch the first cache lines. */
4088 {
4100 loop_start);
4101 }
4102 }
4103 }
4106 }
4107 \f
4108 /* A "basic induction variable" or biv is a pseudo reg that is set
4109 (within this loop) only by incrementing or decrementing it. */
4110 /* A "general induction variable" or giv is a pseudo reg whose
4111 value is a linear function of a biv. */
4113 /* Bivs are recognized by `basic_induction_var';
4114 Givs by `general_induction_var'. */
4116 /* Communication with routines called via `note_stores'. */
4120 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
4124 /* ??? Unfinished optimizations, and possible future optimizations,
4125 for the strength reduction code. */
4127 /* ??? The interaction of biv elimination, and recognition of 'constant'
4128 bivs, may cause problems. */
4130 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4131 performance problems.
4133 Perhaps don't eliminate things that can be combined with an addressing
4134 mode. Find all givs that have the same biv, mult_val, and add_val;
4135 then for each giv, check to see if its only use dies in a following
4136 memory address. If so, generate a new memory address and check to see
4137 if it is valid. If it is valid, then store the modified memory address,
4138 otherwise, mark the giv as not done so that it will get its own iv. */
4140 /* ??? Could try to optimize branches when it is known that a biv is always
4141 positive. */
4143 /* ??? When replace a biv in a compare insn, we should replace with closest
4144 giv so that an optimized branch can still be recognized by the combiner,
4145 e.g. the VAX acb insn. */
4147 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4148 was rerun in loop_optimize whenever a register was added or moved.
4149 Also, some of the optimizations could be a little less conservative. */
4150 \f
4151 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4152 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4153 callback.
4155 NOT_EVERY_ITERATION if current insn is not executed at least once for every
4156 loop iteration except for the last one.
4158 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4159 loop iteration.
4160 */
4161 void
4164 loop_insn_callback fncall;
4165 {
4166 /* This is 1 if current insn is not executed at least once for every loop
4167 iteration. */
4172 rtx p;
4174 /* If loop_scan_start points to the loop exit test, we have to be wary of
4175 subversive use of gotos inside expression statements. */
4179 /* Scan through loop to find all possible bivs. */
4184 {
4187 /* Past CODE_LABEL, we get to insns that may be executed multiple
4188 times. The only way we can be sure that they can't is if every
4189 jump insn between here and the end of the loop either
4190 returns, exits the loop, is a jump to a location that is still
4191 behind the label, or is a jump to the loop start. */
4194 {
4200 {
4205 {
4208 else
4212 }
4220 {
4223 }
4224 }
4225 }
4227 /* Past a jump, we get to insns for which we can't count
4228 on whether they will be executed during each iteration. */
4229 /* This code appears twice in strength_reduce. There is also similar
4230 code in scan_loop. */
4232 /* If we enter the loop in the middle, and scan around to the
4233 beginning, don't set not_every_iteration for that.
4234 This can be any kind of jump, since we want to know if insns
4235 will be executed if the loop is executed. */
4240 {
4243 /* If this is a jump outside the loop, then it also doesn't
4244 matter. Check to see if the target of this branch is on the
4245 loop->exits_labels list. */
4253 }
4256 {
4257 /* At the virtual top of a converted loop, insns are again known to
4258 be executed each iteration: logically, the loop begins here
4259 even though the exit code has been duplicated.
4261 Insns are also again known to be executed each iteration at
4262 the LOOP_CONT note. */
4268 loop_depth++;
4270 loop_depth--;
4271 }
4273 /* Note if we pass a loop latch. If we do, then we can not clear
4274 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4275 a loop since a jump before the last CODE_LABEL may have started
4276 a new loop iteration.
4278 Note that LOOP_TOP is only set for rotated loops and we need
4279 this check for all loops, so compare against the CODE_LABEL
4280 which immediately follows LOOP_START. */
4285 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4286 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4287 or not an insn is known to be executed each iteration of the
4288 loop, whether or not any iterations are known to occur.
4290 Therefore, if we have just passed a label and have no more labels
4291 between here and the test insn of the loop, and we have not passed
4292 a jump to the top of the loop, then we know these insns will be
4293 executed each iteration. */
4296 && !past_loop_latch
4301 }
4302 }
4303 \f
4304 static void
4307 {
4310 /* Temporary list pointers for traversing ivs->list. */
4317 /* Scan ivs->list to remove all regs that proved not to be bivs.
4318 Make a sanity check against regs->n_times_set. */
4320 {
4322 /* Above happens if register modified by subreg, etc. */
4323 /* Make sure it is not recognized as a basic induction var: */
4325 /* If never incremented, it is invariant that we decided not to
4326 move. So leave it alone. */
4328 {
4339 }
4340 else
4341 {
4346 }
4347 }
4348 }
4351 /* Determine how BIVS are initialised by looking through pre-header
4352 extended basic block. */
4353 static void
4356 {
4358 /* Temporary list pointers for traversing ivs->list. */
4361 rtx p;
4363 /* Find initial value for each biv by searching backwards from loop_start,
4364 halting at first label. Also record any test condition. */
4368 {
4369 rtx test;
4379 /* Record any test of a biv that branches around the loop if no store
4380 between it and the start of loop. We only care about tests with
4381 constants and registers and only certain of those. */
4391 {
4392 /* If an NE test, we have an initial value! */
4394 {
4398 }
4399 else
4401 }
4402 }
4403 }
4406 /* Look at the each biv and see if we can say anything better about its
4407 initial value from any initializing insns set up above. (This is done
4408 in two passes to avoid missing SETs in a PARALLEL.) */
4409 static void
4412 {
4414 /* Temporary list pointers for traversing ivs->list. */
4419 {
4420 rtx src;
4421 rtx note;
4426 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4427 is a constant, use the value of that. */
4433 else
4446 {
4450 {
4453 }
4454 }
4455 /* If we can't make it a giv,
4456 let biv keep initial value of "itself". */
4459 }
4460 }
4463 /* Search the loop for general induction variables. */
4465 static void
4468 {
4470 }
4473 /* For each giv for which we still don't know whether or not it is
4474 replaceable, check to see if it is replaceable because its final value
4475 can be calculated. */
4477 static void
4480 {
4485 {
4491 }
4492 }
4495 /* Return non-zero if it is possible to eliminate the biv BL provided
4496 all givs are reduced. This is possible if either the reg is not
4497 used outside the loop, or we can compute what its final value will
4498 be. */
4500 static int
4506 {
4507 /* For architectures with a decrement_and_branch_until_zero insn,
4508 don't do this if we put a REG_NONNEG note on the endtest for this
4509 biv. */
4511 #ifdef HAVE_decrement_and_branch_until_zero
4513 {
4518 }
4519 #endif
4521 /* Check that biv is used outside loop or if it has a final value.
4522 Compare against bl->init_insn rather than loop->start. We aren't
4523 concerned with any uses of the biv between init_insn and
4524 loop->start since these won't be affected by the value of the biv
4525 elsewhere in the function, so long as init_insn doesn't use the
4526 biv itself. */
4537 {
4545 }
4547 }
4550 /* Reduce each giv of BL that we have decided to reduce. */
4552 static void
4556 {
4560 {
4563 {
4566 /* If the code for derived givs immediately below has already
4567 allocated a new_reg, we must keep it. */
4571 #ifdef AUTO_INC_DEC
4572 /* If the target has auto-increment addressing modes, and
4573 this is an address giv, then try to put the increment
4574 immediately after its use, so that flow can create an
4575 auto-increment addressing mode. */
4578 /* We don't handle reversed biv's because bl->biv->insn
4579 does not have a valid INSN_LUID. */
4583 {
4584 /* If other giv's have been combined with this one, then
4585 this will work only if all uses of the other giv's occur
4586 before this giv's insn. This is difficult to check.
4588 We simplify this by looking for the common case where
4589 there is one DEST_REG giv, and this giv's insn is the
4590 last use of the dest_reg of that DEST_REG giv. If the
4591 increment occurs after the address giv, then we can
4592 perform the optimization. (Otherwise, the increment
4593 would have to go before other_giv, and we would not be
4594 able to combine it with the address giv to get an
4595 auto-inc address.) */
4597 {
4602 {
4605 else
4607 }
4614 }
4615 /* Check for case where increment is before the address
4616 giv. Do this test in "loop order". */
4625 else
4628 #ifdef HAVE_cc0
4629 {
4630 rtx prev;
4632 /* We can't put an insn immediately after one setting
4633 cc0, or immediately before one using cc0. */
4640 }
4641 #endif
4645 }
4646 #endif
4648 /* For each place where the biv is incremented, add an insn
4649 to increment the new, reduced reg for the giv. */
4651 {
4652 rtx insert_before;
4658 else
4666 /* A multiply is acceptable here
4667 since this is presumed to be seldom executed. */
4671 }
4673 /* Add code at loop start to initialize giv's reduced reg. */
4678 }
4679 }
4680 }
4683 /* Check for givs whose first use is their definition and whose
4684 last use is the definition of another giv. If so, it is likely
4685 dead and should not be used to derive another giv nor to
4686 eliminate a biv. */
4688 static void
4692 {
4696 {
4703 {
4709 }
4710 }
4711 }
4714 static void
4719 {
4723 {
4730 /* Update expression if this was combined, in case other giv was
4731 replaced. */
4736 /* See if this register is known to be a pointer to something. If
4737 so, see if we can find the alignment. First see if there is a
4738 destination register that is a pointer. If so, this shares the
4739 alignment too. Next see if we can deduce anything from the
4740 computational information. If not, and this is a DEST_ADDR
4741 giv, at least we know that it's a pointer, though we don't know
4742 the alignment. */
4750 {
4759 }
4763 {
4771 }
4776 /* Store reduced reg as the address in the memref where we found
4777 this giv. */
4780 {
4782 }
4783 else
4784 {
4785 /* Not replaceable; emit an insn to set the original giv reg from
4786 the reduced giv, same as above. */
4789 }
4791 /* When a loop is reversed, givs which depend on the reversed
4792 biv, and which are live outside the loop, must be set to their
4793 correct final value. This insn is only needed if the giv is
4794 not replaceable. The correct final value is the same as the
4795 value that the giv starts the reversed loop with. */
4806 {
4811 }
4812 }
4813 }
4816 static int
4821 rtx test_reg;
4822 {
4831 /* Reduce benefit if not replaceable, since we will insert a
4832 move-insn to replace the insn that calculates this giv. Don't do
4833 this unless the giv is a user variable, since it will often be
4834 marked non-replaceable because of the duplication of the exit
4835 code outside the loop. In such a case, the copies we insert are
4836 dead and will be deleted. So they don't have a cost. Similar
4837 situations exist. */
4838 /* ??? The new final_[bg]iv_value code does a much better job of
4839 finding replaceable giv's, and hence this code may no longer be
4840 necessary. */
4845 /* Decrease the benefit to count the add-insns that we will insert
4846 to increment the reduced reg for the giv. ??? This can
4847 overestimate the run-time cost of the additional insns, e.g. if
4848 there are multiple basic blocks that increment the biv, but only
4849 one of these blocks is executed during each iteration. There is
4850 no good way to detect cases like this with the current structure
4851 of the loop optimizer. This code is more accurate for
4852 determining code size than run-time benefits. */
4855 /* Decide whether to strength-reduce this giv or to leave the code
4856 unchanged (recompute it from the biv each time it is used). This
4857 decision can be made independently for each giv. */
4859 #ifdef AUTO_INC_DEC
4860 /* Attempt to guess whether autoincrement will handle some of the
4861 new add insns; if so, increase BENEFIT (undo the subtraction of
4862 add_cost that was done above). */
4864 /* Increasing the benefit is risky, since this is only a guess.
4865 Avoid increasing register pressure in cases where there would
4866 be no other benefit from reducing this giv. */
4869 {
4884 }
4885 #endif
4888 }
4891 /* Free IV structures for LOOP. */
4893 static void
4896 {
4903 {
4909 {
4912 }
4914 {
4917 }
4921 }
4922 }
4925 /* Perform strength reduction and induction variable elimination.
4927 Pseudo registers created during this function will be beyond the
4928 last valid index in several tables including
4929 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
4930 problem here, because the added registers cannot be givs outside of
4931 their loop, and hence will never be reconsidered. But scan_loop
4932 must check regnos to make sure they are in bounds. */
4934 static void
4938 {
4942 rtx p;
4943 /* Temporary list pointer for traversing ivs->list. */
4945 /* Ratio of extra register life span we can justify
4946 for saving an instruction. More if loop doesn't call subroutines
4947 since in that case saving an insn makes more difference
4948 and more registers are available. */
4949 /* ??? could set this to last value of threshold in move_movables */
4951 /* Map of pseudo-register replacements. */
4963 /* Find all BIVs in loop. */
4966 /* Exit if there are no bivs. */
4968 {
4969 /* Can still unroll the loop anyways, but indicate that there is no
4970 strength reduction info available. */
4976 }
4978 /* Determine how BIVS are initialised by looking through pre-header
4979 extended basic block. */
4982 /* Look at the each biv and see if we can say anything better about its
4983 initial value from any initializing insns set up above. */
4986 /* Search the loop for general induction variables. */
4989 /* Try to calculate and save the number of loop iterations. This is
4990 set to zero if the actual number can not be calculated. This must
4991 be called after all giv's have been identified, since otherwise it may
4992 fail if the iteration variable is a giv. */
4995 #ifdef HAVE_prefetch
4998 #endif
5000 /* Now for each giv for which we still don't know whether or not it is
5001 replaceable, check to see if it is replaceable because its final value
5002 can be calculated. This must be done after loop_iterations is called,
5003 so that final_giv_value will work correctly. */
5006 /* Try to prove that the loop counter variable (if any) is always
5007 nonnegative; if so, record that fact with a REG_NONNEG note
5008 so that "decrement and branch until zero" insn can be used. */
5011 /* Create reg_map to hold substitutions for replaceable giv regs.
5012 Some givs might have been made from biv increments, so look at
5013 ivs->reg_iv_type for a suitable size. */
5017 /* Examine each iv class for feasibility of strength reduction/induction
5018 variable elimination. */
5021 {
5025 /* Test whether it will be possible to eliminate this biv
5026 provided all givs are reduced. */
5029 /* This will be true at the end, if all givs which depend on this
5030 biv have been strength reduced.
5031 We can't (currently) eliminate the biv unless this is so. */
5034 /* Check each extension dependent giv in this class to see if its
5035 root biv is safe from wrapping in the interior mode. */
5038 /* Combine all giv's for this iv_class. */
5042 {
5050 /* If an insn is not to be strength reduced, then set its ignore
5051 flag, and clear bl->all_reduced. */
5053 /* A giv that depends on a reversed biv must be reduced if it is
5054 used after the loop exit, otherwise, it would have the wrong
5055 value after the loop exit. To make it simple, just reduce all
5056 of such giv's whether or not we know they are used after the loop
5057 exit. */
5062 {
5070 }
5071 else
5072 {
5073 /* Check that we can increment the reduced giv without a
5074 multiply insn. If not, reject it. */
5079 {
5087 }
5088 }
5089 }
5091 /* Check for givs whose first use is their definition and whose
5092 last use is the definition of another giv. If so, it is likely
5093 dead and should not be used to derive another giv nor to
5094 eliminate a biv. */
5097 /* Reduce each giv that we decided to reduce. */
5100 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5101 as not reduced.
5103 For each giv register that can be reduced now: if replaceable,
5104 substitute reduced reg wherever the old giv occurs;
5105 else add new move insn "giv_reg = reduced_reg". */
5108 /* All the givs based on the biv bl have been reduced if they
5109 merit it. */
5111 /* For each giv not marked as maybe dead that has been combined with a
5112 second giv, clear any "maybe dead" mark on that second giv.
5113 v->new_reg will either be or refer to the register of the giv it
5114 combined with.
5116 Doing this clearing avoids problems in biv elimination where
5117 a giv's new_reg is a complex value that can't be put in the
5118 insn but the giv combined with (with a reg as new_reg) is
5119 marked maybe_dead. Since the register will be used in either
5120 case, we'd prefer it be used from the simpler giv. */
5126 /* Try to eliminate the biv, if it is a candidate.
5127 This won't work if ! bl->all_reduced,
5128 since the givs we planned to use might not have been reduced.
5130 We have to be careful that we didn't initially think we could
5131 eliminate this biv because of a giv that we now think may be
5132 dead and shouldn't be used as a biv replacement.
5134 Also, there is the possibility that we may have a giv that looks
5135 like it can be used to eliminate a biv, but the resulting insn
5136 isn't valid. This can happen, for example, on the 88k, where a
5137 JUMP_INSN can compare a register only with zero. Attempts to
5138 replace it with a compare with a constant will fail.
5140 Note that in cases where this call fails, we may have replaced some
5141 of the occurrences of the biv with a giv, but no harm was done in
5142 doing so in the rare cases where it can occur. */
5146 {
5147 /* ?? If we created a new test to bypass the loop entirely,
5148 or otherwise drop straight in, based on this test, then
5149 we might want to rewrite it also. This way some later
5150 pass has more hope of removing the initialization of this
5151 biv entirely. */
5153 /* If final_value != 0, then the biv may be used after loop end
5154 and we must emit an insn to set it just in case.
5156 Reversed bivs already have an insn after the loop setting their
5157 value, so we don't need another one. We can't calculate the
5158 proper final value for such a biv here anyways. */
5167 }
5168 /* See above note wrt final_value. But since we couldn't eliminate
5169 the biv, we must set the value after the loop instead of before. */
5173 }
5175 /* Go through all the instructions in the loop, making all the
5176 register substitutions scheduled in REG_MAP. */
5181 {
5185 }
5188 {
5189 /* When we completely unroll a loop we will likely not need the increment
5190 of the loop BIV and we will not need the conditional branch at the
5191 end of the loop. */
5194 #ifdef HAVE_cc0
5195 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5196 need the comparison before the conditional branch at the end of the
5197 loop. */
5199 #endif
5201 /* We'll need one copy for each loop iteration. */
5204 /* A little slop to account for the ability to remove initialization
5205 code, better CSE, and other secondary benefits of completely
5206 unrolling some loops. */
5209 /* Clamp the value. */
5212 }
5214 /* Unroll loops from within strength reduction so that we can use the
5215 induction variable information that strength_reduce has already
5216 collected. Always unroll loops that would be as small or smaller
5217 unrolled than when rolled. */
5224 #ifdef HAVE_doloop_end
5229 /* In case number of iterations is known, drop branch prediction note
5230 in the branch. Do that only in second loop pass, as loop unrolling
5231 may change the number of iterations performed. */
5233 {
5234 unsigned HOST_WIDE_INT n
5239 }
5247 }
5248 \f
5249 /*Record all basic induction variables calculated in the insn. */
5250 static rtx
5253 rtx p;
5256 {
5258 rtx set;
5259 rtx dest_reg;
5260 rtx inc_val;
5261 rtx mult_val;
5267 {
5272 {
5277 {
5278 /* It is a possible basic induction variable.
5279 Create and initialize an induction structure for it. */
5287 }
5290 }
5291 }
5293 }
5294 \f
5295 /* Record all givs calculated in the insn.
5296 A register is a giv if: it is only set once, it is a function of a
5297 biv and a constant (or invariant), and it is not a biv. */
5298 static rtx
5301 rtx p;
5304 {
5307 rtx set;
5308 /* Look for a general induction variable in a register. */
5313 {
5314 rtx src_reg;
5315 rtx dest_reg;
5316 rtx add_val;
5317 rtx mult_val;
5318 rtx ext_val;
5321 rtx last_consec_insn;
5330 /* Equivalent expression is a giv. */
5335 /* Don't try to handle any regs made by loop optimization.
5336 We have nothing on them in regno_first_uid, etc. */
5338 /* Don't recognize a BASIC_INDUCT_VAR here. */
5340 /* This must be the only place where the register is set. */
5342 /* or all sets must be consecutive and make a giv. */
5347 {
5351 /* If this is a library call, increase benefit. */
5355 /* Skip the consecutive insns, if there are any. */
5363 }
5364 }
5366 #ifndef DONT_REDUCE_ADDR
5367 /* Look for givs which are memory addresses. */
5368 /* This resulted in worse code on a VAX 8600. I wonder if it
5369 still does. */
5372 maybe_multiple);
5373 #endif
5375 /* Update the status of whether giv can derive other givs. This can
5376 change when we pass a label or an insn that updates a biv. */
5381 }
5382 \f
5383 /* Return 1 if X is a valid source for an initial value (or as value being
5384 compared against in an initial test).
5386 X must be either a register or constant and must not be clobbered between
5387 the current insn and the start of the loop.
5389 INSN is the insn containing X. */
5391 static int
5393 rtx x;
5394 rtx insn;
5396 rtx loop_start;
5397 {
5401 /* Only consider pseudos we know about initialized in insns whose luids
5402 we know. */
5407 /* Don't use call-clobbered registers across a call which clobbers it. On
5408 some machines, don't use any hard registers at all. */
5410 && (SMALL_REGISTER_CLASSES
5414 /* Don't use registers that have been clobbered before the start of the
5415 loop. */
5420 }
5421 \f
5422 /* Scan X for memory refs and check each memory address
5423 as a possible giv. INSN is the insn whose pattern X comes from.
5424 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5425 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5426 more thanonce in each loop iteration. */
5428 static void
5431 rtx x;
5432 rtx insn;
5434 {
5444 {
5460 {
5461 rtx src_reg;
5462 rtx add_val;
5463 rtx mult_val;
5464 rtx ext_val;
5467 /* This code used to disable creating GIVs with mult_val == 1 and
5468 add_val == 0. However, this leads to lost optimizations when
5469 it comes time to combine a set of related DEST_ADDR GIVs, since
5470 this one would not be seen. */
5475 {
5476 /* Found one; record it. */
5485 }
5486 }
5491 }
5493 /* Recursively scan the subexpressions for other mem refs. */
5499 maybe_multiple);
5503 maybe_multiple);
5504 }
5505 \f
5506 /* Fill in the data about one biv update.
5507 V is the `struct induction' in which we record the biv. (It is
5508 allocated by the caller, with alloca.)
5509 INSN is the insn that sets it.
5510 DEST_REG is the biv's reg.
5512 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5513 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5514 being set to INC_VAL.
5516 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5517 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5518 can be executed more than once per iteration. If MAYBE_MULTIPLE
5519 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5520 executed exactly once per iteration. */
5522 static void
5527 rtx insn;
5528 rtx dest_reg;
5529 rtx inc_val;
5530 rtx mult_val;
5534 {
5550 /* Add this to the reg's iv_class, creating a class
5551 if this is the first incrementation of the reg. */
5555 {
5556 /* Create and initialize new iv_class. */
5566 /* Set initial value to the reg itself. */
5569 /* We haven't seen the initializing insn yet */
5579 /* Add this class to ivs->list. */
5583 /* Put it in the array of biv register classes. */
5585 }
5587 /* Update IV_CLASS entry for this biv. */
5596 }
5597 \f
5598 /* Fill in the data about one giv.
5599 V is the `struct induction' in which we record the giv. (It is
5600 allocated by the caller, with alloca.)
5601 INSN is the insn that sets it.
5602 BENEFIT estimates the savings from deleting this insn.
5603 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5604 into a register or is used as a memory address.
5606 SRC_REG is the biv reg which the giv is computed from.
5607 DEST_REG is the giv's reg (if the giv is stored in a reg).
5608 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5609 LOCATION points to the place where this giv's value appears in INSN. */
5611 static void
5616 rtx insn;
5617 rtx src_reg;
5618 rtx dest_reg;
5624 {
5629 rtx temp;
5631 /* Attempt to prove constantness of the values. Don't let simplity_rtx
5632 undo the MULT canonicalization that we performed earlier. */
5662 /* The v->always_computable field is used in update_giv_derive, to
5663 determine whether a giv can be used to derive another giv. For a
5664 DEST_REG giv, INSN computes a new value for the giv, so its value
5665 isn't computable if INSN insn't executed every iteration.
5666 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5667 it does not compute a new value. Hence the value is always computable
5668 regardless of whether INSN is executed each iteration. */
5672 else
5678 {
5681 }
5683 {
5688 /* If the lifetime is zero, it means that this register is
5689 really a dead store. So mark this as a giv that can be
5690 ignored. This will not prevent the biv from being eliminated. */
5696 }
5698 /* Add the giv to the class of givs computed from one biv. */
5702 {
5705 /* Don't count DEST_ADDR. This is supposed to count the number of
5706 insns that calculate givs. */
5710 }
5711 else
5712 /* Fatal error, biv missing for this giv? */
5717 else
5718 {
5719 /* The giv can be replaced outright by the reduced register only if all
5720 of the following conditions are true:
5721 - the insn that sets the giv is always executed on any iteration
5722 on which the giv is used at all
5723 (there are two ways to deduce this:
5724 either the insn is executed on every iteration,
5725 or all uses follow that insn in the same basic block),
5726 - the giv is not used outside the loop
5727 - no assignments to the biv occur during the giv's lifetime. */
5730 /* Previous line always fails if INSN was moved by loop opt. */
5733 && (! not_every_iteration
5735 {
5736 /* Now check that there are no assignments to the biv within the
5737 giv's lifetime. This requires two separate checks. */
5739 /* Check each biv update, and fail if any are between the first
5740 and last use of the giv.
5742 If this loop contains an inner loop that was unrolled, then
5743 the insn modifying the biv may have been emitted by the loop
5744 unrolling code, and hence does not have a valid luid. Just
5745 mark the biv as not replaceable in this case. It is not very
5746 useful as a biv, because it is used in two different loops.
5747 It is very unlikely that we would be able to optimize the giv
5748 using this biv anyways. */
5752 {
5758 {
5762 }
5763 }
5765 /* If there are any backwards branches that go from after the
5766 biv update to before it, then this giv is not replaceable. */
5770 {
5774 }
5775 }
5776 else
5777 {
5778 /* May still be replaceable, we don't have enough info here to
5779 decide. */
5782 }
5783 }
5785 /* Record whether the add_val contains a const_int, for later use by
5786 combine_givs. */
5787 {
5792 ;
5796 {
5798 {
5803 else
5805 }
5808 }
5809 }
5813 }
5815 /* All this does is determine whether a giv can be made replaceable because
5816 its final value can be calculated. This code can not be part of record_giv
5817 above, because final_giv_value requires that the number of loop iterations
5818 be known, and that can not be accurately calculated until after all givs
5819 have been identified. */
5821 static void
5825 {
5832 /* DEST_ADDR givs will never reach here, because they are always marked
5833 replaceable above in record_giv. */
5835 /* The giv can be replaced outright by the reduced register only if all
5836 of the following conditions are true:
5837 - the insn that sets the giv is always executed on any iteration
5838 on which the giv is used at all
5839 (there are two ways to deduce this:
5840 either the insn is executed on every iteration,
5841 or all uses follow that insn in the same basic block),
5842 - its final value can be calculated (this condition is different
5843 than the one above in record_giv)
5844 - it's not used before the it's set
5845 - no assignments to the biv occur during the giv's lifetime. */
5847 #if 0
5848 /* This is only called now when replaceable is known to be false. */
5849 /* Clear replaceable, so that it won't confuse final_giv_value. */
5851 #endif
5855 {
5858 rtx last_giv_use;
5862 /* When trying to determine whether or not a biv increment occurs
5863 during the lifetime of the giv, we can ignore uses of the variable
5864 outside the loop because final_value is true. Hence we can not
5865 use regno_last_uid and regno_first_uid as above in record_giv. */
5867 /* Search the loop to determine whether any assignments to the
5868 biv occur during the giv's lifetime. Start with the insn
5869 that sets the giv, and search around the loop until we come
5870 back to that insn again.
5872 Also fail if there is a jump within the giv's lifetime that jumps
5873 to somewhere outside the lifetime but still within the loop. This
5874 catches spaghetti code where the execution order is not linear, and
5875 hence the above test fails. Here we assume that the giv lifetime
5876 does not extend from one iteration of the loop to the next, so as
5877 to make the test easier. Since the lifetime isn't known yet,
5878 this requires two loops. See also record_giv above. */
5883 {
5886 {
5889 }
5895 {
5896 /* It is possible for the BIV increment to use the GIV if we
5897 have a cycle. Thus we must be sure to check each insn for
5898 both BIV and GIV uses, and we must check for BIV uses
5899 first. */
5906 {
5908 {
5912 }
5914 }
5915 }
5916 }
5918 /* Now that the lifetime of the giv is known, check for branches
5919 from within the lifetime to outside the lifetime if it is still
5920 replaceable. */
5923 {
5926 {
5939 {
5948 }
5949 }
5950 }
5952 /* If it is replaceable, then save the final value. */
5955 }
5960 }
5961 \f
5962 /* Update the status of whether a giv can derive other givs.
5964 We need to do something special if there is or may be an update to the biv
5965 between the time the giv is defined and the time it is used to derive
5966 another giv.
5968 In addition, a giv that is only conditionally set is not allowed to
5969 derive another giv once a label has been passed.
5971 The cases we look at are when a label or an update to a biv is passed. */
5973 static void
5976 rtx p;
5977 {
5981 rtx tem;
5984 /* Search all IV classes, then all bivs, and finally all givs.
5986 There are three cases we are concerned with. First we have the situation
5987 of a giv that is only updated conditionally. In that case, it may not
5988 derive any givs after a label is passed.
5990 The second case is when a biv update occurs, or may occur, after the
5991 definition of a giv. For certain biv updates (see below) that are
5992 known to occur between the giv definition and use, we can adjust the
5993 giv definition. For others, or when the biv update is conditional,
5994 we must prevent the giv from deriving any other givs. There are two
5995 sub-cases within this case.
5997 If this is a label, we are concerned with any biv update that is done
5998 conditionally, since it may be done after the giv is defined followed by
5999 a branch here (actually, we need to pass both a jump and a label, but
6000 this extra tracking doesn't seem worth it).
6002 If this is a jump, we are concerned about any biv update that may be
6003 executed multiple times. We are actually only concerned about
6004 backward jumps, but it is probably not worth performing the test
6005 on the jump again here.
6007 If this is a biv update, we must adjust the giv status to show that a
6008 subsequent biv update was performed. If this adjustment cannot be done,
6009 the giv cannot derive further givs. */
6015 {
6017 {
6018 /* If cant_derive is already true, there is no point in
6019 checking all of these conditions again. */
6023 /* If this giv is conditionally set and we have passed a label,
6024 it cannot derive anything. */
6028 /* Skip givs that have mult_val == 0, since
6029 they are really invariants. Also skip those that are
6030 replaceable, since we know their lifetime doesn't contain
6031 any biv update. */
6035 /* The only way we can allow this giv to derive another
6036 is if this is a biv increment and we can form the product
6037 of biv->add_val and giv->mult_val. In this case, we will
6038 be able to compute a compensation. */
6040 {
6041 rtx ext_val_dummy;
6052 tem = simplify_giv_expr
6059 else
6061 }
6065 }
6066 }
6067 }
6068 \f
6069 /* Check whether an insn is an increment legitimate for a basic induction var.
6070 X is the source of insn P, or a part of it.
6071 MODE is the mode in which X should be interpreted.
6073 DEST_REG is the putative biv, also the destination of the insn.
6074 We accept patterns of these forms:
6075 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6076 REG = INVARIANT + REG
6078 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6079 store the additive term into *INC_VAL, and store the place where
6080 we found the additive term into *LOCATION.
6082 If X is an assignment of an invariant into DEST_REG, we set
6083 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6085 We also want to detect a BIV when it corresponds to a variable
6086 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6087 of the variable may be a PLUS that adds a SUBREG of that variable to
6088 an invariant and then sign- or zero-extends the result of the PLUS
6089 into the variable.
6091 Most GIVs in such cases will be in the promoted mode, since that is the
6092 probably the natural computation mode (and almost certainly the mode
6093 used for addresses) on the machine. So we view the pseudo-reg containing
6094 the variable as the BIV, as if it were simply incremented.
6096 Note that treating the entire pseudo as a BIV will result in making
6097 simple increments to any GIVs based on it. However, if the variable
6098 overflows in its declared mode but not its promoted mode, the result will
6099 be incorrect. This is acceptable if the variable is signed, since
6100 overflows in such cases are undefined, but not if it is unsigned, since
6101 those overflows are defined. So we only check for SIGN_EXTEND and
6102 not ZERO_EXTEND.
6104 If we cannot find a biv, we return 0. */
6106 static int
6109 rtx x;
6111 rtx dest_reg;
6112 rtx p;
6116 {
6124 {
6130 {
6132 }
6137 {
6139 }
6140 else
6153 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6154 handle addition of promoted variables.
6155 ??? The comment at the start of this function is wrong: promoted
6156 variable increments don't look like it says they do. */
6162 /* If this register is assigned in a previous insn, look at its
6163 source, but don't go outside the loop or past a label. */
6165 /* If this sets a register to itself, we would repeat any previous
6166 biv increment if we applied this strategy blindly. */
6172 {
6173 rtx dest;
6174 do
6175 {
6177 }
6206 }
6207 /* Fall through. */
6209 /* Can accept constant setting of biv only when inside inner most loop.
6210 Otherwise, a biv of an inner loop may be incorrectly recognized
6211 as a biv of the outer loop,
6212 causing code to be moved INTO the inner loop. */
6219 /* convert_modes aborts if we try to convert to or from CCmode, so just
6220 exclude that case. It is very unlikely that a condition code value
6221 would be a useful iterator anyways. convert_modes aborts if we try to
6222 convert a float mode to non-float or vice versa too. */
6226 {
6227 /* Possible bug here? Perhaps we don't know the mode of X. */
6231 }
6232 else
6240 /* Similar, since this can be a sign extension. */
6245 ;
6259 location);
6264 }
6265 }
6266 \f
6267 /* A general induction variable (giv) is any quantity that is a linear
6268 function of a basic induction variable,
6269 i.e. giv = biv * mult_val + add_val.
6270 The coefficients can be any loop invariant quantity.
6271 A giv need not be computed directly from the biv;
6272 it can be computed by way of other givs. */
6274 /* Determine whether X computes a giv.
6275 If it does, return a nonzero value
6276 which is the benefit from eliminating the computation of X;
6277 set *SRC_REG to the register of the biv that it is computed from;
6278 set *ADD_VAL and *MULT_VAL to the coefficients,
6279 such that the value of X is biv * mult + add; */
6281 static int
6285 rtx x;
6293 {
6297 /* If this is an invariant, forget it, it isn't a giv. */
6308 {
6311 /* Since this is now an invariant and wasn't before, it must be a giv
6312 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6313 with. */
6320 /* This is equivalent to a BIV. */
6327 /* Either (plus (biv) (invar)) or
6328 (plus (mult (biv) (invar_1)) (invar_2)). */
6330 {
6333 }
6334 else
6335 {
6338 }
6343 /* ADD_VAL is zero. */
6351 }
6353 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6354 unless they are CONST_INT). */
6362 else
6365 /* Always return true if this is a giv so it will be detected as such,
6366 even if the benefit is zero or negative. This allows elimination
6367 of bivs that might otherwise not be eliminated. */
6369 }
6370 \f
6371 /* Given an expression, X, try to form it as a linear function of a biv.
6372 We will canonicalize it to be of the form
6373 (plus (mult (BIV) (invar_1))
6374 (invar_2))
6375 with possible degeneracies.
6377 The invariant expressions must each be of a form that can be used as a
6378 machine operand. We surround then with a USE rtx (a hack, but localized
6379 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6380 routine; it is the caller's responsibility to strip them.
6382 If no such canonicalization is possible (i.e., two biv's are used or an
6383 expression that is neither invariant nor a biv or giv), this routine
6384 returns 0.
6386 For a non-zero return, the result will have a code of CONST_INT, USE,
6387 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6389 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6394 static rtx
6397 rtx x;
6400 {
6405 rtx tem;
6407 /* If this is not an integer mode, or if we cannot do arithmetic in this
6408 mode, this can't be a giv. */
6415 {
6422 /* Put constant last, CONST_INT last if both constant. */
6430 /* Handle addition of zero, then addition of an invariant. */
6435 {
6438 /* Adding two invariants must result in an invariant, so enclose
6439 addition operation inside a USE and return it. */
6449 else
6458 /* biv + invar or mult + invar. Return sum. */
6462 /* (a + invar_1) + invar_2. Associate. */
6463 return
6469 arg1)),
6474 }
6476 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6477 MULT to reduce cases. */
6483 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6484 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6485 Recurse to associate the second PLUS. */
6490 return
6498 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6514 /* Handle "a - b" as "a + b * (-1)". */
6520 constm1_rtx)),
6529 /* Put constant last, CONST_INT last if both constant. */
6534 /* If second argument is not now constant, not giv. */
6538 /* Handle multiply by 0 or 1. */
6546 {
6548 /* biv * invar. Done. */
6552 /* Product of two constants. */
6556 /* invar * invar is a giv, but attempt to simplify it somehow. */
6562 {
6563 /* (invar_0 * invar_1) * invar_2. Associate. */
6570 arg1)),
6572 }
6573 /* Porpagate the MULT expressions to the intermost nodes. */
6575 {
6576 /* (invar_0 + invar_1) * invar_2. Distribute. */
6582 arg1),
6586 arg1)),
6588 }
6592 /* (a * invar_1) * invar_2. Associate. */
6598 arg1)),
6602 /* (a + invar_1) * invar_2. Distribute. */
6607 arg1),
6610 arg1)),
6615 }
6618 /* Shift by constant is multiply by power of two. */
6622 return
6631 /* "-a" is "a * (-1)" */
6637 /* "~a" is "-a - 1". Silly, but easy. */
6641 const1_rtx),
6645 /* Already in proper form for invariant. */
6651 /* Conditionally recognize extensions of simple IVs. After we've
6652 computed loop traversal counts and verified the range of the
6653 source IV, we'll reevaluate this as a GIV. */
6655 {
6658 {
6661 }
6662 }
6666 /* If this is a new register, we can't deal with it. */
6670 /* Check for biv or giv. */
6672 {
6676 {
6679 /* Form expression from giv and add benefit. Ensure this giv
6680 can derive another and subtract any needed adjustment if so. */
6682 /* Increasing the benefit here is risky. The only case in which it
6683 is arguably correct is if this is the only use of V. In other
6684 cases, this will artificially inflate the benefit of the current
6685 giv, and lead to suboptimal code. Thus, it is disabled, since
6686 potentially not reducing an only marginally beneficial giv is
6687 less harmful than reducing many givs that are not really
6688 beneficial. */
6689 {
6693 }
6706 {
6709 }
6710 else
6711 {
6714 }
6716 }
6719 do_default:
6720 /* If it isn't an induction variable, and it is invariant, we
6721 may be able to simplify things further by looking through
6722 the bits we just moved outside the loop. */
6724 {
6730 {
6731 /* Ok, we found a match. Substitute and simplify. */
6733 /* If we match another movable, we must use that, as
6734 this one is going away. */
6739 /* If consec is non-zero, this is a member of a group of
6740 instructions that were moved together. We handle this
6741 case only to the point of seeking to the last insn and
6742 looking for a REG_EQUAL. Fail if we don't find one. */
6744 {
6747 do
6748 {
6750 }
6756 }
6757 else
6758 {
6762 }
6765 {
6766 /* What we are most interested in is pointer
6767 arithmetic on invariants -- only take
6768 patterns we may be able to do something with. */
6774 {
6776 benefit);
6779 }
6784 {
6789 }
6790 }
6792 }
6793 }
6795 }
6797 /* Fall through to general case. */
6799 /* If invariant, return as USE (unless CONST_INT).
6800 Otherwise, not giv. */
6805 {
6814 }
6815 else
6817 }
6818 }
6820 /* This routine folds invariants such that there is only ever one
6821 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6823 static rtx
6826 {
6832 {
6835 }
6838 {
6841 }
6842 else
6843 {
6846 }
6847 }
6849 static rtx
6853 {
6855 {
6859 else
6862 }
6865 else
6868 }
6869 \f
6870 /* Help detect a giv that is calculated by several consecutive insns;
6871 for example,
6872 giv = biv * M
6873 giv = giv + A
6874 The caller has already identified the first insn P as having a giv as dest;
6875 we check that all other insns that set the same register follow
6876 immediately after P, that they alter nothing else,
6877 and that the result of the last is still a giv.
6879 The value is 0 if the reg set in P is not really a giv.
6880 Otherwise, the value is the amount gained by eliminating
6881 all the consecutive insns that compute the value.
6883 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6884 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6886 The coefficients of the ultimate giv value are stored in
6887 *MULT_VAL and *ADD_VAL. */
6889 static int
6894 rtx p;
6895 rtx src_reg;
6896 rtx dest_reg;
6901 {
6907 rtx temp;
6908 rtx set;
6910 /* Indicate that this is a giv so that we can update the value produced in
6911 each insn of the multi-insn sequence.
6913 This induction structure will be used only by the call to
6914 general_induction_var below, so we can allocate it on our stack.
6915 If this is a giv, our caller will replace the induct var entry with
6916 a new induction structure. */
6937 {
6941 /* If libcall, skip to end of call sequence. */
6952 /* Giv created by equivalent expression. */
6958 {
6962 count--;
6966 }
6968 {
6969 /* Allow insns that set something other than this giv to a
6970 constant. Such insns are needed on machines which cannot
6971 include long constants and should not disqualify a giv. */
6980 }
6981 }
6986 }
6987 \f
6988 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6989 represented by G1. If no such expression can be found, or it is clear that
6990 it cannot possibly be a valid address, 0 is returned.
6992 To perform the computation, we note that
6993 G1 = x * v + a and
6994 G2 = y * v + b
6995 where `v' is the biv.
6997 So G2 = (y/b) * G1 + (b - a*y/x).
6999 Note that MULT = y/x.
7001 Update: A and B are now allowed to be additive expressions such that
7002 B contains all variables in A. That is, computing B-A will not require
7003 subtracting variables. */
7005 static rtx
7008 {
7009 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7014 /* If MULT is not 1, we cannot handle A with non-constants, since we
7015 would then be required to subtract multiples of the registers in A.
7016 This is theoretically possible, and may even apply to some Fortran
7017 constructs, but it is a lot of work and we do not attempt it here. */
7022 /* In general these structures are sorted top to bottom (down the PLUS
7023 chain), but not left to right across the PLUS. If B is a higher
7024 order giv than A, we can strip one level and recurse. If A is higher
7025 order, we'll eventually bail out, but won't know that until the end.
7026 If they are the same, we'll strip one level around this loop. */
7029 {
7041 /* We matched: remove one reg completely. */
7044 /* An alternate match. */
7047 /* An alternate match. */
7049 else
7050 {
7051 /* Indicates an extra register in B. Strip one level from B and
7052 recurse, hoping B was the higher order expression. */
7057 }
7058 }
7060 /* Here we are at the last level of A, go through the cases hoping to
7061 get rid of everything but a constant. */
7064 {
7077 }
7079 {
7081 }
7083 {
7088 }
7090 {
7095 else
7097 }
7102 }
7104 rtx
7107 {
7110 /* The value that G1 will be multiplied by must be a constant integer. Also,
7111 the only chance we have of getting a valid address is if b*c/a (see above
7112 for notation) is also an integer. */
7115 {
7120 }
7123 else
7124 {
7125 /* ??? Find out if the one is a multiple of the other? */
7127 }
7131 {
7132 /* Failed. If we've got a multiplication factor between G1 and G2,
7133 scale G1's addend and try again. */
7135 {
7139 {
7140 HOST_WIDE_INT m;
7144 }
7145 else
7146 {
7148 mult);
7149 }
7152 }
7153 }
7157 /* Form simplified final result. */
7162 else
7167 else
7168 {
7171 {
7175 }
7178 }
7179 }
7180 \f
7181 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7182 represented by G1. This indicates that G2 should be combined with G1 and
7183 that G2 can use (either directly or via an address expression) a register
7184 used to represent G1. */
7186 static rtx
7189 {
7192 /* With the introduction of ext dependent givs, we must care for modes.
7193 G2 must not use a wider mode than G1. */
7203 /* If these givs are identical, they can be combined. We use the results
7204 of express_from because the addends are not in a canonical form, so
7205 rtx_equal_p is a weaker test. */
7206 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7207 combination to be the other way round. */
7210 {
7212 }
7214 /* If G2 can be expressed as a function of G1 and that function is valid
7215 as an address and no more expensive than using a register for G2,
7216 the expression of G2 in terms of G1 can be used. */
7220 /* ??? Looses, especially with -fforce-addr, where *g2->location
7221 will always be a register, and so anything more complicated
7222 gets discarded. */
7223 #if 0
7224 #ifdef ADDRESS_COST
7226 #else
7228 #endif
7229 #endif
7230 )
7231 {
7233 }
7236 }
7237 \f
7238 /* Check each extension dependent giv in this class to see if its
7239 root biv is safe from wrapping in the interior mode, which would
7240 make the giv illegal. */
7242 static void
7246 {
7249 HOST_WIDE_INT start_val;
7255 /* Make sure the iteration data is available. We must have
7256 constants in order to be certain of no overflow. */
7257 /* ??? An unknown iteration count with an increment of +-1
7258 combined with friendly exit tests of against an invariant
7259 value is also ameanable to optimization. Not implemented. */
7265 /* Make sure the host can represent the arithmetic. */
7267 {
7269 HOST_WIDE_INT s_end_val;
7281 /* Check for host arithmatic overflow. */
7283 {
7285 HOST_WIDE_INT s_max;
7292 /* Check zero extension of biv ok. */
7294 /* Check for host arithmatic overflow. */
7295 && (neg_incr
7298 /* Check for target arithmetic overflow. */
7299 && (neg_incr
7302 {
7304 }
7306 /* Check sign extension of biv ok. */
7307 /* ??? While it is true that overflow with signed and pointer
7308 arithmetic is undefined, I fear too many programmers don't
7309 keep this fact in mind -- myself included on occasion.
7310 So leave alone with the signed overflow optimizations. */
7312 /* Check for host arithmatic overflow. */
7313 && (neg_incr
7316 /* Check for target arithmetic overflow. */
7317 && (neg_incr
7320 {
7322 }
7323 }
7324 }
7326 /* Invalidate givs that fail the tests. */
7329 {
7334 {
7343 /* We don't know whether this value is being used as either
7344 signed or unsigned, so to safely truncate we must satisfy
7345 both. The initial check here verifies the BIV itself;
7346 once that is successful we may check its range wrt the
7347 derived GIV. */
7349 {
7353 /* We know from the above that both endpoints are nonnegative,
7354 and that there is no wrapping. Verify that both endpoints
7355 are within the (signed) range of the outer mode. */
7358 }
7363 }
7366 {
7368 {
7372 }
7373 }
7374 else
7375 {
7377 {
7382 else
7383 {
7388 else
7390 }
7395 }
7398 }
7399 }
7400 }
7402 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7404 rtx
7407 rtx value;
7408 {
7414 /* Recall that check_ext_dependent_givs verified that the known bounds
7415 of a biv did not overflow or wrap with respect to the extension for
7416 the giv. Therefore, constants need no additional adjustment. */
7420 /* Otherwise, we must adjust the value to compensate for the
7421 differing modes of the biv and the giv. */
7423 }
7424 \f
7425 struct combine_givs_stats
7426 {
7429 };
7431 static int
7435 {
7442 /* Stabilize the sort. */
7446 }
7448 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7449 any other. If so, point SAME to the giv combined with and set NEW_REG to
7450 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7451 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7453 static void
7457 {
7458 /* Additional benefit to add for being combined multiple times. */
7466 /* Count givs, because bl->giv_count is incorrect here. */
7470 giv_count++;
7472 giv_array
7483 {
7485 rtx single_use;
7490 /* If a DEST_REG GIV is used only once, do not allow it to combine
7491 with anything, for in doing so we will gain nothing that cannot
7492 be had by simply letting the GIV with which we would have combined
7493 to be reduced on its own. The losage shows up in particular with
7494 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7495 be seen elsewhere as well. */
7502 /* Add an additional weight for zero addends. */
7507 {
7508 rtx this_combine;
7513 {
7516 }
7517 }
7519 }
7521 /* Iterate, combining until we can't. */
7522 restart:
7526 {
7529 {
7535 }
7537 }
7540 {
7546 /* If it has already been combined, skip. */
7551 {
7554 /* If it has already been combined, skip. */
7556 {
7561 /* For destination, we now may replace by mem expression instead
7562 of register. This changes the costs considerably, so add the
7563 compensation. */
7573 /* ??? The new final_[bg]iv_value code does a much better job
7574 of finding replaceable giv's, and hence this code may no
7575 longer be necessary. */
7579 /* To help optimize the next set of combinations, remove
7580 this giv from the benefits of other potential mates. */
7582 {
7586 }
7593 }
7594 }
7596 /* To help optimize the next set of combinations, remove
7597 this giv from the benefits of other potential mates. */
7599 {
7601 {
7605 }
7609 /* We've finished with this giv, and everything it touched.
7610 Restart the combination so that proper weights for the
7611 rest of the givs are properly taken into account. */
7612 /* ??? Ideally we would compact the arrays at this point, so
7613 as to not cover old ground. But sanely compacting
7614 can_combine is tricky. */
7616 }
7617 }
7619 /* Clean up. */
7622 }
7623 \f
7624 /* Generate sequence for REG = B * M + A. */
7626 static rtx
7632 {
7633 rtx seq;
7634 rtx result;
7637 /* Use unsigned arithmetic. */
7645 }
7648 /* Update registers created in insn sequence SEQ. */
7650 static void
7653 rtx seq;
7654 {
7655 /* Update register info for alias analysis. */
7658 {
7661 {
7665 }
7666 }
7667 else
7668 {
7672 }
7673 }
7676 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7678 void
7685 basic_block before_bb;
7686 rtx before_insn;
7687 {
7688 rtx seq;
7691 {
7694 }
7696 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7699 /* Increase the lifetime of any invariants moved further in code. */
7706 /* It is possible that the expansion created lots of new registers.
7707 Iterate over the sequence we just created and record them all. */
7709 }
7712 /* Emit insns in loop pre-header to set REG = B * M + A. */
7714 void
7721 {
7722 rtx seq;
7724 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7727 /* Increase the lifetime of any invariants moved further in code.
7728 ???? Is this really necessary? */
7735 /* It is possible that the expansion created lots of new registers.
7736 Iterate over the sequence we just created and record them all. */
7738 }
7741 /* Emit insns after loop to set REG = B * M + A. */
7743 void
7750 {
7751 rtx seq;
7753 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7758 /* It is possible that the expansion created lots of new registers.
7759 Iterate over the sequence we just created and record them all. */
7761 }
7765 /* Similar to gen_add_mult, but compute cost rather than generating
7766 sequence. */
7768 static int
7774 {
7784 {
7789 }
7792 }
7793 \f
7794 /* Test whether A * B can be computed without
7795 an actual multiply insn. Value is 1 if so. */
7797 static int
7799 rtx a;
7800 rtx b;
7801 {
7803 rtx tmp;
7806 /* If only one is constant, make it B. */
7810 /* If first constant, both constant, so don't need multiply. */
7814 /* If second not constant, neither is constant, so would need multiply. */
7818 /* One operand is constant, so might not need multiply insn. Generate the
7819 code for the multiply and see if a call or multiply, or long sequence
7820 of insns is generated. */
7828 {
7833 else
7835 {
7844 {
7847 }
7848 }
7849 }
7859 }
7860 \f
7861 /* Check to see if loop can be terminated by a "decrement and branch until
7862 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7863 Also try reversing an increment loop to a decrement loop
7864 to see if the optimization can be performed.
7865 Value is nonzero if optimization was performed. */
7867 /* This is useful even if the architecture doesn't have such an insn,
7868 because it might change a loops which increments from 0 to n to a loop
7869 which decrements from n to 0. A loop that decrements to zero is usually
7870 faster than one that increments from zero. */
7872 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7873 such as approx_final_value, biv_total_increment, loop_iterations, and
7874 final_[bg]iv_value. */
7876 static int
7880 {
7885 rtx reg;
7886 rtx jump_label;
7887 rtx final_value;
7888 rtx start_value;
7889 rtx new_add_val;
7890 rtx comparison;
7891 rtx before_comparison;
7892 rtx p;
7893 rtx jump;
7894 rtx first_compare;
7899 /* If last insn is a conditional branch, and the insn before tests a
7900 register value, try to optimize it. Otherwise, we can't do anything. */
7909 /* Try to compute whether the compare/branch at the loop end is one or
7910 two instructions. */
7916 else
7919 {
7920 /* If more than one condition is present to control the loop, then
7921 do not proceed, as this function does not know how to rewrite
7922 loop tests with more than one condition.
7924 Look backwards from the first insn in the last comparison
7925 sequence and see if we've got another comparison sequence. */
7927 rtx jump1;
7931 }
7933 /* Check all of the bivs to see if the compare uses one of them.
7934 Skip biv's set more than once because we can't guarantee that
7935 it will be zero on the last iteration. Also skip if the biv is
7936 used between its update and the test insn. */
7939 {
7944 first_compare))
7946 }
7951 /* Look for the case where the basic induction variable is always
7952 nonnegative, and equals zero on the last iteration.
7953 In this case, add a reg_note REG_NONNEG, which allows the
7954 m68k DBRA instruction to be used. */
7962 {
7963 /* Initial value must be greater than 0,
7964 init_val % -dec_value == 0 to ensure that it equals zero on
7965 the last iteration */
7971 {
7972 /* register always nonnegative, add REG_NOTE to branch */
7980 }
7982 /* If the decrement is 1 and the value was tested as >= 0 before
7983 the loop, then we can safely optimize. */
7985 {
7998 {
8006 }
8007 }
8008 }
8011 {
8012 /* Try to change inc to dec, so can apply above optimization. */
8013 /* Can do this if:
8014 all registers modified are induction variables or invariant,
8015 all memory references have non-overlapping addresses
8016 (obviously true if only one write)
8017 allow 2 insns for the compare/jump at the end of the loop. */
8018 /* Also, we must avoid any instructions which use both the reversed
8019 biv and another biv. Such instructions will fail if the loop is
8020 reversed. We meet this condition by requiring that either
8021 no_use_except_counting is true, or else that there is only
8022 one biv. */
8024 /* 1 if the iteration var is used only to count iterations. */
8026 /* 1 if the loop has no memory store, or it has a single memory store
8027 which is reversible. */
8033 {
8037 /* If there are no givs for this biv, and the only exit is the
8038 fall through at the end of the loop, then
8039 see if perhaps there are no uses except to count. */
8043 {
8048 /* An insn that sets the biv is okay. */
8049 ;
8053 {
8054 /* If either of these insns uses the biv and sets a pseudo
8055 that has more than one usage, then the biv has uses
8056 other than counting since it's used to derive a value
8057 that is used more than one time. */
8059 regs);
8061 {
8064 }
8065 }
8067 {
8070 }
8071 }
8073 /* A biv has uses besides counting if it is used to set
8074 another biv. */
8078 {
8081 }
8082 }
8085 /* No need to worry about MEMs. */
8086 ;
8088 {
8093 /* If the loop has a single store, and the destination address is
8094 invariant, then we can't reverse the loop, because this address
8095 might then have the wrong value at loop exit.
8096 This would work if the source was invariant also, however, in that
8097 case, the insn should have been moved out of the loop. */
8100 {
8103 /* If we could prove that each of the memory locations
8104 written to was different, then we could reverse the
8105 store -- but we don't presently have any way of
8106 knowing that. */
8109 /* If the store depends on a register that is set after the
8110 store, it depends on the initial value, and is thus not
8111 reversible. */
8113 {
8120 }
8121 }
8122 }
8123 else
8126 /* This code only acts for innermost loops. Also it simplifies
8127 the memory address check by only reversing loops with
8128 zero or one memory access.
8129 Two memory accesses could involve parts of the same array,
8130 and that can't be reversed.
8131 If the biv is used only for counting, than we don't need to worry
8132 about all these things. */
8137 && reversible_mem_store
8142 {
8143 rtx tem;
8145 /* Loop can be reversed. */
8149 /* Now check other conditions:
8151 The increment must be a constant, as must the initial value,
8152 and the comparison code must be LT.
8154 This test can probably be improved since +/- 1 in the constant
8155 can be obtained by changing LT to LE and vice versa; this is
8156 confusing. */
8159 /* for constants, LE gets turned into LT */
8163 {
8174 comparison_const_width
8176 else
8177 comparison_const_width
8181 comparison_sign_mask
8184 /* If the comparison value is not a loop invariant, then we
8185 can not reverse this loop.
8187 ??? If the insns which initialize the comparison value as
8188 a whole compute an invariant result, then we could move
8189 them out of the loop and proceed with loop reversal. */
8197 /* Normalize the initial value if it is an integer and
8198 has no other use except as a counter. This will allow
8199 a few more loops to be reversed. */
8203 {
8205 /* The code below requires comparison_val to be a multiple
8206 of add_val in order to do the loop reversal, so
8207 round up comparison_val to a multiple of add_val.
8208 Since comparison_value is constant, we know that the
8209 current comparison code is LT. */
8211 comparison_val
8213 /* We postpone overflow checks for COMPARISON_VAL here;
8214 even if there is an overflow, we might still be able to
8215 reverse the loop, if converting the loop exit test to
8216 NE is possible. */
8218 }
8220 /* First check if we can do a vanilla loop reversal. */
8222 /* If we have a decrement_and_branch_on_count,
8223 prefer the NE test, since this will allow that
8224 instruction to be generated. Note that we must
8225 use a vanilla loop reversal if the biv is used to
8226 calculate a giv or has a non-counting use. */
8227 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8228 && defined (HAVE_decrement_and_branch_on_count)
8232 #endif
8234 /* Now do postponed overflow checks on COMPARISON_VAL. */
8237 {
8238 /* Register will always be nonnegative, with value
8239 0 on last iteration */
8243 }
8247 {
8250 }
8251 else
8257 /* If the initial value is not zero, or if the comparison
8258 value is not an exact multiple of the increment, then we
8259 can not reverse this loop. */
8262 {
8265 }
8266 else
8267 {
8270 }
8274 /* Reset these in case we normalized the initial value
8275 and comparison value above. */
8278 {
8280 final_value
8282 }
8285 /* Save some info needed to produce the new insns. */
8290 /* Set start_value; if this is not a CONST_INT, we need
8291 to generate a SUB.
8292 Initialize biv to start_value before loop start.
8293 The old initializing insn will be deleted as a
8294 dead store by flow.c. */
8297 {
8300 }
8302 {
8310 start_value
8316 }
8318 {
8321 initial_value);
8325 start_value
8328 }
8329 else
8330 /* We could handle the other cases too, but it'll be
8331 better to have a testcase first. */
8334 /* We may not have a single insn which can increment a reg, so
8335 create a sequence to hold all the insns from expand_inc. */
8344 /* Update biv info to reflect its new status. */
8349 /* Update loop info. */
8358 /* Inc LABEL_NUSES so that delete_insn will
8359 not delete the label. */
8362 /* Emit an insn after the end of the loop to set the biv's
8363 proper exit value if it is used anywhere outside the loop. */
8369 /* Delete compare/branch at end of loop. */
8374 /* Add new compare/branch insn at end of loop. */
8386 ;
8392 {
8394 {
8395 /* Increment of LABEL_NUSES done above. */
8396 /* Register is now always nonnegative,
8397 so add REG_NONNEG note to the branch. */
8400 }
8402 }
8404 /* No insn may reference both the reversed and another biv or it
8405 will fail (see comment near the top of the loop reversal
8406 code).
8407 Earlier on, we have verified that the biv has no use except
8408 counting, or it is the only biv in this function.
8409 However, the code that computes no_use_except_counting does
8410 not verify reg notes. It's possible to have an insn that
8411 references another biv, and has a REG_EQUAL note with an
8412 expression based on the reversed biv. To avoid this case,
8413 remove all REG_EQUAL notes based on the reversed biv
8414 here. */
8417 {
8420 /* If this is a set of a GIV based on the reversed biv, any
8421 REG_EQUAL notes should still be correct. */
8428 {
8433 else
8435 }
8436 }
8438 /* Mark that this biv has been reversed. Each giv which depends
8439 on this biv, and which is also live past the end of the loop
8440 will have to be fixed up. */
8445 {
8449 else
8451 }
8454 }
8455 }
8456 }
8459 }
8460 \f
8461 /* Verify whether the biv BL appears to be eliminable,
8462 based on the insns in the loop that refer to it.
8464 If ELIMINATE_P is non-zero, actually do the elimination.
8466 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8467 determine whether invariant insns should be placed inside or at the
8468 start of the loop. */
8470 static int
8476 {
8479 rtx p;
8481 /* Scan all insns in the loop, stopping if we find one that uses the
8482 biv in a way that we cannot eliminate. */
8485 {
8490 /* If this is a libcall that sets a giv, skip ahead to its end. */
8492 {
8496 {
8501 {
8508 }
8509 }
8510 }
8515 {
8521 }
8522 }
8525 {
8530 }
8533 }
8534 \f
8535 /* INSN and REFERENCE are instructions in the same insn chain.
8536 Return non-zero if INSN is first. */
8538 int
8541 {
8545 {
8546 /* Start with test for not first so that INSN == REFERENCE yields not
8547 first. */
8553 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8554 previous insn, hence the <= comparison below does not work if
8555 P is a note. */
8566 }
8567 }
8569 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8570 the offset that we have to take into account due to auto-increment /
8571 div derivation is zero. */
8572 static int
8575 rtx insn;
8576 {
8577 /* If the giv V had the auto-inc address optimization applied
8578 to it, and INSN occurs between the giv insn and the biv
8579 insn, then we'd have to adjust the value used here.
8580 This is rare, so we don't bother to make this possible. */
8589 }
8591 /* If BL appears in X (part of the pattern of INSN), see if we can
8592 eliminate its use. If so, return 1. If not, return 0.
8594 If BIV does not appear in X, return 1.
8596 If ELIMINATE_P is non-zero, actually do the elimination.
8597 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8598 Depending on how many items have been moved out of the loop, it
8599 will either be before INSN (when WHERE_INSN is non-zero) or at the
8600 start of the loop (when WHERE_INSN is zero). */
8602 static int
8608 basic_block where_bb;
8609 rtx where_insn;
8610 {
8616 #ifdef HAVE_cc0
8618 #endif
8624 {
8626 /* If we haven't already been able to do something with this BIV,
8627 we can't eliminate it. */
8633 /* If this sets the BIV, it is not a problem. */
8637 /* If this is an insn that defines a giv, it is also ok because
8638 it will go away when the giv is reduced. */
8643 #ifdef HAVE_cc0
8645 {
8646 /* Can replace with any giv that was reduced and
8647 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8648 Require a constant for MULT_VAL, so we know it's nonzero.
8649 ??? We disable this optimization to avoid potential
8650 overflows. */
8658 {
8665 /* If the giv has the opposite direction of change,
8666 then reverse the comparison. */
8670 else
8673 /* We can probably test that giv's reduced reg. */
8676 }
8678 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8679 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8680 Require a constant for MULT_VAL, so we know it's nonzero.
8681 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8682 overflow problem. */
8694 {
8701 /* If the giv has the opposite direction of change,
8702 then reverse the comparison. */
8706 else
8710 /* Replace biv with the giv's reduced register. */
8715 /* Insn doesn't support that constant or invariant. Copy it
8716 into a register (it will be a loop invariant.) */
8723 /* Substitute the new register for its invariant value in
8724 the compare expression. */
8728 }
8729 }
8730 #endif
8737 /* See if either argument is the biv. */
8742 else
8746 {
8747 /* First try to replace with any giv that has constant positive
8748 mult_val and constant add_val. We might be able to support
8749 negative mult_val, but it seems complex to do it in general. */
8761 {
8768 /* Replace biv with the giv's reduced reg. */
8771 /* If all constants are actually constant integers and
8772 the derived constant can be directly placed in the COMPARE,
8773 do so. */
8777 {
8782 }
8783 else
8784 {
8785 /* Otherwise, load it into a register. */
8791 }
8794 }
8796 /* Look for giv with positive constant mult_val and nonconst add_val.
8797 Insert insns to calculate new compare value.
8798 ??? Turn this off due to possible overflow. */
8806 {
8807 rtx tem;
8817 /* Replace biv with giv's reduced register. */
8821 /* Compute value to compare against. */
8825 /* Use it in this insn. */
8829 }
8830 }
8832 {
8834 {
8835 /* Look for giv with constant positive mult_val and nonconst
8836 add_val. Insert insns to compute new compare value.
8837 ??? Turn this off due to possible overflow. */
8844 {
8845 rtx tem;
8855 /* Replace biv with giv's reduced register. */
8859 /* Compute value to compare against. */
8866 }
8867 }
8869 /* This code has problems. Basically, you can't know when
8870 seeing if we will eliminate BL, whether a particular giv
8871 of ARG will be reduced. If it isn't going to be reduced,
8872 we can't eliminate BL. We can try forcing it to be reduced,
8873 but that can generate poor code.
8875 The problem is that the benefit of reducing TV, below should
8876 be increased if BL can actually be eliminated, but this means
8877 we might have to do a topological sort of the order in which
8878 we try to process biv. It doesn't seem worthwhile to do
8879 this sort of thing now. */
8881 #if 0
8882 /* Otherwise the reg compared with had better be a biv. */
8887 /* Look for a pair of givs, one for each biv,
8888 with identical coefficients. */
8890 {
8902 {
8909 /* Replace biv with its giv's reduced reg. */
8911 /* Replace other operand with the other giv's
8912 reduced reg. */
8915 }
8916 }
8917 #endif
8918 }
8920 /* If we get here, the biv can't be eliminated. */
8924 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8925 biv is used in it, since it will be replaced. */
8933 }
8935 /* See if any subexpression fails elimination. */
8938 {
8940 {
8953 }
8954 }
8957 }
8958 \f
8959 /* Return nonzero if the last use of REG
8960 is in an insn following INSN in the same basic block. */
8962 static int
8964 rtx reg;
8965 rtx insn;
8966 {
8967 rtx n;
8971 {
8974 }
8976 }
8977 \f
8978 /* Called via `note_stores' to record the initial value of a biv. Here we
8979 just record the location of the set and process it later. */
8981 static void
8983 rtx dest;
8984 rtx set;
8986 {
8997 /* If this is the first set found, record it. */
8999 {
9002 }
9003 }
9004 \f
9005 /* If any of the registers in X are "old" and currently have a last use earlier
9006 than INSN, update them to have a last use of INSN. Their actual last use
9007 will be the previous insn but it will not have a valid uid_luid so we can't
9008 use it. X must be a source expression only. */
9010 static void
9012 rtx x;
9013 rtx insn;
9014 {
9015 /* Check for the case where INSN does not have a valid luid. In this case,
9016 there is no need to modify the regno_last_uid, as this can only happen
9017 when code is inserted after the loop_end to set a pseudo's final value,
9018 and hence this insn will never be the last use of x.
9019 ???? This comment is not correct. See for example loop_givs_reduce.
9020 This may insert an insn before another new insn. */
9024 {
9026 }
9027 else
9028 {
9032 {
9038 }
9039 }
9040 }
9041 \f
9042 /* Given an insn INSN and condition COND, return the condition in a
9043 canonical form to simplify testing by callers. Specifically:
9045 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9046 (2) Both operands will be machine operands; (cc0) will have been replaced.
9047 (3) If an operand is a constant, it will be the second operand.
9048 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9049 for GE, GEU, and LEU.
9051 If the condition cannot be understood, or is an inequality floating-point
9052 comparison which needs to be reversed, 0 will be returned.
9054 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
9056 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9057 insn used in locating the condition was found. If a replacement test
9058 of the condition is desired, it should be placed in front of that
9059 insn and we will be sure that the inputs are still valid.
9061 If WANT_REG is non-zero, we wish the condition to be relative to that
9062 register, if possible. Therefore, do not canonicalize the condition
9063 further. */
9065 rtx
9067 rtx insn;
9068 rtx cond;
9071 rtx want_reg;
9072 {
9075 rtx set;
9076 rtx tem;
9094 /* If we are comparing a register with zero, see if the register is set
9095 in the previous insn to a COMPARE or a comparison operation. Perform
9096 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9097 in cse.c */
9102 {
9103 /* Set non-zero when we find something of interest. */
9106 #ifdef HAVE_cc0
9107 /* If comparison with cc0, import actual comparison from compare
9108 insn. */
9110 {
9121 }
9122 #endif
9124 /* If this is a COMPARE, pick up the two things being compared. */
9126 {
9130 }
9134 /* Go back to the previous insn. Stop if it is not an INSN. We also
9135 stop if it isn't a single set or if it has a REG_INC note because
9136 we don't want to bother dealing with it. */
9150 /* If this is setting OP0, get what it sets it to if it looks
9151 relevant. */
9153 {
9156 /* ??? We may not combine comparisons done in a CCmode with
9157 comparisons not done in a CCmode. This is to aid targets
9158 like Alpha that have an IEEE compliant EQ instruction, and
9159 a non-IEEE compliant BEQ instruction. The use of CCmode is
9160 actually artificial, simply to prevent the combination, but
9161 should not affect other platforms.
9163 However, we must allow VOIDmode comparisons to match either
9164 CCmode or non-CCmode comparison, because some ports have
9165 modeless comparisons inside branch patterns.
9167 ??? This mode check should perhaps look more like the mode check
9168 in simplify_comparison in combine. */
9176 && (STORE_FLAG_VALUE
9179 #ifdef FLOAT_STORE_FLAG_VALUE
9182 && (REAL_VALUE_NEGATIVE
9184 #endif
9185 ))
9196 && (STORE_FLAG_VALUE
9199 #ifdef FLOAT_STORE_FLAG_VALUE
9202 && (REAL_VALUE_NEGATIVE
9204 #endif
9205 ))
9211 {
9214 }
9215 else
9217 }
9220 /* If this sets OP0, but not directly, we have to give up. */
9224 {
9228 {
9233 }
9238 }
9239 }
9241 /* If constant is first, put it last. */
9245 /* If OP0 is the result of a comparison, we weren't able to find what
9246 was really being compared, so fail. */
9250 /* Canonicalize any ordered comparison with integers involving equality
9251 if we can do computations in the relevant mode and we do not
9252 overflow. */
9257 {
9260 unsigned HOST_WIDE_INT max_val
9264 {
9270 /* When cross-compiling, const_val might be sign-extended from
9271 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9291 }
9292 }
9294 #ifdef HAVE_cc0
9295 /* Never return CC0; return zero instead. */
9298 #endif
9301 }
9303 /* Given a jump insn JUMP, return the condition that will cause it to branch
9304 to its JUMP_LABEL. If the condition cannot be understood, or is an
9305 inequality floating-point comparison which needs to be reversed, 0 will
9306 be returned.
9308 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9309 insn used in locating the condition was found. If a replacement test
9310 of the condition is desired, it should be placed in front of that
9311 insn and we will be sure that the inputs are still valid. */
9313 rtx
9315 rtx jump;
9317 {
9318 rtx cond;
9320 rtx set;
9322 /* If this is not a standard conditional jump, we can't parse it. */
9330 /* If this branches to JUMP_LABEL when the condition is false, reverse
9331 the condition. */
9332 reverse
9337 }
9339 /* Similar to above routine, except that we also put an invariant last
9340 unless both operands are invariants. */
9342 rtx
9345 rtx x;
9346 {
9356 }
9358 /* Scan the function and determine whether it has indirect (computed) jumps.
9360 This is taken mostly from flow.c; similar code exists elsewhere
9361 in the compiler. It may be useful to put this into rtlanal.c. */
9362 static int
9364 rtx start;
9365 {
9366 rtx insn;
9373 }
9375 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9376 documentation for LOOP_MEMS for the definition of `appropriate'.
9377 This function is called from prescan_loop via for_each_rtx. */
9379 static int
9383 {
9392 {
9397 /* We're not interested in MEMs that are only clobbered. */
9401 /* We're not interested in the MEM associated with a
9402 CONST_DOUBLE, so there's no need to traverse into this. */
9406 /* We're not interested in any MEMs that only appear in notes. */
9410 /* This is not a MEM. */
9412 }
9414 /* See if we've already seen this MEM. */
9417 {
9419 /* The modes of the two memory accesses are different. If
9420 this happens, something tricky is going on, and we just
9421 don't optimize accesses to this MEM. */
9425 }
9427 /* Resize the array, if necessary. */
9429 {
9432 else
9438 }
9440 /* Actually insert the MEM. */
9442 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9443 because we can't put it in a register. We still store it in the
9444 table, though, so that if we see the same address later, but in a
9445 non-BLK mode, we'll not think we can optimize it at that point. */
9451 }
9454 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9456 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9457 register that is modified by an insn between FROM and TO. If the
9458 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9459 more, stop incrementing it, to avoid overflow.
9461 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9462 register I is used, if it is only used once. Otherwise, it is set
9463 to 0 (for no uses) or const0_rtx for more than one use. This
9464 parameter may be zero, in which case this processing is not done.
9466 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9467 optimize register I. */
9469 static void
9473 {
9476 /* last_set[n] is nonzero iff reg n has been set in the current
9477 basic block. In that case, it is the insn that last set reg n. */
9479 rtx insn;
9485 /* Grow the regs array if not allocated or too small. */
9487 {
9493 /* Zero the new elements. */
9496 }
9498 /* Clear previously scanned fields but do not clear n_times_set. */
9500 {
9504 }
9508 /* Scan the loop, recording register usage. */
9511 {
9513 {
9514 /* Record registers that have exactly one use. */
9517 /* Include uses in REG_EQUAL notes. */
9525 {
9529 last_set);
9530 }
9531 }
9535 }
9537 /* Invalidate all hard registers clobbered by calls. With one exception:
9538 a call-clobbered PIC register is still function-invariant for our
9539 purposes, since we can hoist any PIC calculations out of the loop.
9540 Thus the call to rtx_varies_p. */
9545 {
9548 }
9550 #ifdef AVOID_CCMODE_COPIES
9551 /* Don't try to move insns which set CC registers if we should not
9552 create CCmode register copies. */
9556 #endif
9558 /* Set regs->array[I].n_times_set for the new registers. */
9563 }
9565 /* Returns the number of real INSNs in the LOOP. */
9567 static int
9570 {
9572 rtx insn;
9580 }
9582 /* Move MEMs into registers for the duration of the loop. */
9584 static void
9587 {
9594 rtx end_label;
9595 /* Nonzero if the next instruction may never be executed. */
9602 /* We cannot use next_label here because it skips over normal insns. */
9607 /* Check to see if it's possible that some instructions in the loop are
9608 never executed. Also check if there is a goto out of the loop other
9609 than right after the end of the loop. */
9613 {
9617 /* If we enter the loop in the middle, and scan
9618 around to the beginning, don't set maybe_never
9619 for that. This must be an unconditional jump,
9620 otherwise the code at the top of the loop might
9621 never be executed. Unconditional jumps are
9622 followed a by barrier then loop end. */
9627 {
9628 /* If this is a jump outside of the loop but not right
9629 after the end of the loop, we would have to emit new fixup
9630 sequences for each such label. */
9632 JUMP_INSN is executed, we must be conservative. */
9641 /* Something complicated. */
9643 else
9644 /* If there are any more instructions in the loop, they
9645 might not be reached. */
9647 }
9650 }
9652 /* Find start of the extended basic block that enters the loop. */
9656 ;
9661 /* Build table of mems that get set to constant values before the
9662 loop. */
9666 /* Actually move the MEMs. */
9668 {
9669 regset_head load_copies;
9670 regset_head store_copies;
9672 rtx reg;
9674 rtx mem_list_entry;
9678 /* There's no telling whether or not MEM is modified. */
9681 /* Go through the MEMs written to in the loop to see if this
9682 one is aliased by one of them. */
9685 {
9690 {
9691 /* MEM is indeed aliased by this store. */
9694 }
9696 }
9702 /* If this MEM is written to, we must be sure that there
9703 are no reads from another MEM that aliases this one. */
9705 {
9709 {
9713 VOIDmode,
9715 rtx_varies_p))
9716 {
9717 /* It's not safe to hoist loop_info->mems[i] out of
9718 the loop because writes to it might not be
9719 seen by reads from loop_info->mems[j]. */
9722 }
9723 }
9724 }
9727 /* We can't access the MEM outside the loop; it might
9728 cause a trap that wouldn't have happened otherwise. */
9732 /* We thought we were going to lift this MEM out of the
9733 loop, but later discovered that we could not. */
9739 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9740 order to keep scan_loop from moving stores to this MEM
9741 out of the loop just because this REG is neither a
9742 user-variable nor used in the loop test. */
9747 /* Now, replace all references to the MEM with the
9748 corresponding pseudos. */
9753 {
9755 {
9756 rtx set;
9760 /* See if this copies the mem into a register that isn't
9761 modified afterwards. We'll try to do copy propagation
9762 a little further on. */
9764 /* @@@ This test is _way_ too conservative. */
9765 && ! maybe_never
9773 /* See if this copies the mem from a register that isn't
9774 modified afterwards. We'll try to remove the
9775 redundant copy later on by doing a little register
9776 renaming and copy propagation. This will help
9777 to untangle things for the BIV detection code. */
9779 && ! maybe_never
9787 /* If this is a call which uses / clobbers this memory
9788 location, we must not change the interface here. */
9792 {
9796 }
9797 else
9798 /* Replace the memory reference with the shadow register. */
9801 }
9806 }
9811 /* We couldn't replace all occurrences of the MEM. */
9813 else
9814 {
9815 /* Load the memory immediately before LOOP->START, which is
9816 the NOTE_LOOP_BEG. */
9818 rtx set;
9824 {
9828 {
9832 /* Extending hard register lifetimes causes crash
9833 on SRC targets. Doing so on non-SRC is
9834 probably also not good idea, since we most
9835 probably have pseudoregister equivalence as
9836 well. */
9839 }
9840 /* Use the constant equivalence if that is cheap enough. */
9846 {
9849 }
9851 /* If best_equiv is nonzero, we know that MEM is set to a
9852 constant or register before the loop. We will use this
9853 knowledge to initialize the shadow register with that
9854 constant or reg rather than by loading from MEM. */
9857 }
9862 {
9865 {
9868 }
9869 }
9875 {
9877 {
9880 }
9882 /* Store the memory immediately after END, which is
9883 the NOTE_LOOP_END. */
9886 }
9889 {
9894 }
9896 /* Attempt a bit of copy propagation. This helps untangle the
9897 data flow, and enables {basic,general}_induction_var to find
9898 more bivs/givs. */
9899 EXECUTE_IF_SET_IN_REG_SET
9901 {
9903 });
9906 EXECUTE_IF_SET_IN_REG_SET
9908 {
9910 });
9912 }
9913 }
9916 {
9917 /* Now, we need to replace all references to the previous exit
9918 label with the new one. */
9919 rtx_pair rr;
9924 {
9927 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9928 field. This is not handled by for_each_rtx because it doesn't
9929 handle unprinted ('0') fields. We need to update JUMP_LABEL
9930 because the immediately following unroll pass will use it.
9931 replace_label would not work anyways, because that only handles
9932 LABEL_REFs. */
9935 }
9936 }
9939 }
9941 /* For communication between note_reg_stored and its caller. */
9942 struct note_reg_stored_arg
9943 {
9945 rtx reg;
9946 };
9948 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9949 is equal to ARG. */
9950 static void
9954 {
9958 }
9960 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9961 There must be exactly one insn that sets this pseudo; it will be
9962 deleted if all replacements succeed and we can prove that the register
9963 is not used after the loop. */
9965 static void
9968 rtx replacement;
9970 {
9971 /* This is the reg that we are copying from. */
9974 rtx insn;
9975 /* These help keep track of whether we replaced all uses of the reg. */
9982 {
9983 rtx set;
9985 /* Only substitute within one extended basic block from the initializing
9986 insn. */
9993 /* Is this the initializing insn? */
9998 {
10005 }
10007 /* Only substitute after seeing the initializing insn. */
10009 {
10016 /* Stop replacing when REPLACEMENT is modified. */
10021 {
10024 /* It is possible that we've turned previously valid REG_EQUAL to
10025 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10026 REPLACEMENT is modified, we get different meaning. */
10030 }
10031 }
10032 }
10036 {
10040 {
10041 rtx first;
10042 rtx retval_note;
10044 /* Assume we're just deleting INIT_INSN. */
10046 /* Look for REG_RETVAL note. If we're deleting the end of
10047 the libcall sequence, the whole sequence can go. */
10049 /* If we found a REG_RETVAL note, find the first instruction
10050 in the sequence. */
10054 /* Delete the instructions. */
10056 }
10059 }
10060 }
10062 /* Replace all the instructions from FIRST up to and including LAST
10063 with NOTE_INSN_DELETED notes. */
10065 static void
10067 rtx first;
10068 rtx last;
10069 {
10071 {
10077 /* If this was the LAST instructions we're supposed to delete,
10078 we're done. */
10083 }
10084 }
10086 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10087 loop LOOP if the order of the sets of these registers can be
10088 swapped. There must be exactly one insn within the loop that sets
10089 this pseudo followed immediately by a move insn that sets
10090 REPLACEMENT with REGNO. */
10091 static void
10094 rtx replacement;
10096 {
10097 rtx insn;
10106 {
10107 /* Search for the insn that copies REGNO to NEW_REGNO? */
10115 }
10118 {
10119 rtx prev_insn;
10120 rtx prev_set;
10122 /* Some DEF-USE info would come in handy here to make this
10123 function more general. For now, just check the previous insn
10124 which is the most likely candidate for setting REGNO. */
10132 {
10133 /* We have:
10134 (set (reg regno) (expr))
10135 (set (reg new_regno) (reg regno))
10137 so try converting this to:
10138 (set (reg new_regno) (expr))
10139 (set (reg regno) (reg new_regno))
10141 The former construct is often generated when a global
10142 variable used for an induction variable is shadowed by a
10143 register (NEW_REGNO). The latter construct improves the
10144 chances of GIV replacement and BIV elimination. */
10154 {
10161 /* Update first use of REGNO. */
10165 /* Now perform copy propagation to hopefully
10166 remove all uses of REGNO within the loop. */
10168 }
10169 }
10170 }
10171 }
10173 /* Replace MEM with its associated pseudo register. This function is
10174 called from load_mems via for_each_rtx. DATA is actually a pointer
10175 to a structure describing the instruction currently being scanned
10176 and the MEM we are currently replacing. */
10178 static int
10182 {
10190 {
10195 /* We're not interested in the MEM associated with a
10196 CONST_DOUBLE, so there's no need to traverse into one. */
10200 /* This is not a MEM. */
10202 }
10205 /* This is not the MEM we are currently replacing. */
10208 /* Actually replace the MEM. */
10212 }
10214 static void
10216 rtx insn;
10217 rtx mem;
10218 rtx reg;
10219 {
10220 loop_replace_args args;
10227 }
10229 /* Replace one register with another. Called through for_each_rtx; PX points
10230 to the rtx being scanned. DATA is actually a pointer to
10231 a structure of arguments. */
10233 static int
10237 {
10248 }
10250 static void
10252 rtx insn;
10253 rtx reg;
10254 rtx replacement;
10255 {
10256 loop_replace_args args;
10263 }
10265 /* Replace occurrences of the old exit label for the loop with the new
10266 one. DATA is an rtx_pair containing the old and new labels,
10267 respectively. */
10269 static int
10273 {
10292 }
10293 \f
10294 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10295 (ignored in the interim). */
10297 static rtx
10300 basic_block where_bb ATTRIBUTE_UNUSED;
10301 rtx where_insn;
10302 rtx pattern;
10303 {
10305 }
10308 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
10309 in basic block WHERE_BB (ignored in the interim) within the loop
10310 otherwise hoist PATTERN into the loop pre-header. */
10312 rtx
10315 basic_block where_bb ATTRIBUTE_UNUSED;
10316 rtx where_insn;
10317 rtx pattern;
10318 {
10322 }
10325 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10326 WHERE_BB (ignored in the interim) within the loop. */
10328 static rtx
10331 basic_block where_bb ATTRIBUTE_UNUSED;
10332 rtx where_insn;
10333 rtx pattern;
10334 {
10336 }
10339 /* Hoist insn for PATTERN into the loop pre-header. */
10341 rtx
10344 rtx pattern;
10345 {
10347 }
10350 /* Hoist call insn for PATTERN into the loop pre-header. */
10352 static rtx
10355 rtx pattern;
10356 {
10358 }
10361 /* Sink insn for PATTERN after the loop end. */
10363 rtx
10366 rtx pattern;
10367 {
10369 }
10371 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10372 and constant. Emit sequence of intructions to load it into REG */
10373 static rtx
10376 {
10377 rtx seq;
10385 }
10387 /* If the loop has multiple exits, emit insn for PATTERN before the
10388 loop to ensure that it will always be executed no matter how the
10389 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10390 since this is slightly more efficient. */
10392 static rtx
10395 rtx pattern;
10396 {
10399 else
10401 }
10402 \f
10403 static void
10408 {
10416 iv_num++;
10421 {
10424 }
10425 }
10428 static void
10433 {
10435 rtx incr;
10446 {
10449 }
10451 {
10454 }
10458 {
10462 }
10465 {
10469 }
10471 /* List the increments. */
10473 {
10477 }
10479 /* List the givs. */
10481 {
10486 else
10489 }
10490 }
10493 static void
10498 {
10509 {
10513 }
10516 }
10519 static void
10524 {
10531 else
10547 {
10549 {
10561 }
10562 }
10573 {
10577 }
10580 }
10583 void
10586 {
10588 }
10591 void
10594 {
10596 }
10599 void
10602 {
10604 }
10607 void
10610 {
10612 }
10615 #define LOOP_BLOCK_NUM_1(INSN) \
10616 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10618 /* The notes do not have an assigned block, so look at the next insn. */
10619 #define LOOP_BLOCK_NUM(INSN) \
10620 ((INSN) ? (GET_CODE (INSN) == NOTE \
10621 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10622 : LOOP_BLOCK_NUM_1 (INSN)) \
10623 : -1)
10625 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10627 static void
10632 {
10633 rtx label;
10638 /* Print diagnostics to compare our concept of a loop with
10639 what the loop notes say. */
10654 {
10674 {
10677 {
10680 }
10681 }
10684 /* This can happen when a marked loop appears as two nested loops,
10685 say from while (a || b) {}. The inner loop won't match
10686 the loop markers but the outer one will. */
10689 }
10690 }
10692 /* Call this function from the debugger to dump LOOP. */
10694 void
10697 {
10699 }
10701 /* Call this function from the debugger to dump LOOPS. */
10703 void
10706 {
10708 }