PR ada/67205
[official-gcc.git] / gcc / config / mips / mips.c
blob0e83cb4d9c8fbcac693952369efa8048e357b36f
1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "backend.h"
28 #include "target.h"
29 #include "rtl.h"
30 #include "tree.h"
31 #include "memmodel.h"
32 #include "gimple.h"
33 #include "cfghooks.h"
34 #include "df.h"
35 #include "tm_p.h"
36 #include "stringpool.h"
37 #include "optabs.h"
38 #include "regs.h"
39 #include "emit-rtl.h"
40 #include "recog.h"
41 #include "cgraph.h"
42 #include "diagnostic.h"
43 #include "insn-attr.h"
44 #include "output.h"
45 #include "alias.h"
46 #include "fold-const.h"
47 #include "varasm.h"
48 #include "stor-layout.h"
49 #include "calls.h"
50 #include "explow.h"
51 #include "expr.h"
52 #include "libfuncs.h"
53 #include "reload.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
56 #include "cfgrtl.h"
57 #include "cfganal.h"
58 #include "sched-int.h"
59 #include "gimplify.h"
60 #include "target-globals.h"
61 #include "tree-pass.h"
62 #include "context.h"
63 #include "builtins.h"
64 #include "rtl-iter.h"
66 /* This file should be included last. */
67 #include "target-def.h"
69 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
70 #define UNSPEC_ADDRESS_P(X) \
71 (GET_CODE (X) == UNSPEC \
72 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
73 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
75 /* Extract the symbol or label from UNSPEC wrapper X. */
76 #define UNSPEC_ADDRESS(X) \
77 XVECEXP (X, 0, 0)
79 /* Extract the symbol type from UNSPEC wrapper X. */
80 #define UNSPEC_ADDRESS_TYPE(X) \
81 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
83 /* The maximum distance between the top of the stack frame and the
84 value $sp has when we save and restore registers.
86 The value for normal-mode code must be a SMALL_OPERAND and must
87 preserve the maximum stack alignment. We therefore use a value
88 of 0x7ff0 in this case.
90 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
91 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
93 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
94 up to 0x7f8 bytes and can usually save or restore all the registers
95 that we need to save or restore. (Note that we can only use these
96 instructions for o32, for which the stack alignment is 8 bytes.)
98 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
99 RESTORE are not available. We can then use unextended instructions
100 to save and restore registers, and to allocate and deallocate the top
101 part of the frame. */
102 #define MIPS_MAX_FIRST_STACK_STEP \
103 (!TARGET_COMPRESSION ? 0x7ff0 \
104 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
105 : TARGET_64BIT ? 0x100 : 0x400)
107 /* True if INSN is a mips.md pattern or asm statement. */
108 /* ??? This test exists through the compiler, perhaps it should be
109 moved to rtl.h. */
110 #define USEFUL_INSN_P(INSN) \
111 (NONDEBUG_INSN_P (INSN) \
112 && GET_CODE (PATTERN (INSN)) != USE \
113 && GET_CODE (PATTERN (INSN)) != CLOBBER)
115 /* If INSN is a delayed branch sequence, return the first instruction
116 in the sequence, otherwise return INSN itself. */
117 #define SEQ_BEGIN(INSN) \
118 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
119 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
120 : (INSN))
122 /* Likewise for the last instruction in a delayed branch sequence. */
123 #define SEQ_END(INSN) \
124 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
125 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
126 0, \
127 XVECLEN (PATTERN (INSN), 0) - 1)) \
128 : (INSN))
130 /* Execute the following loop body with SUBINSN set to each instruction
131 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
132 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
133 for ((SUBINSN) = SEQ_BEGIN (INSN); \
134 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
135 (SUBINSN) = NEXT_INSN (SUBINSN))
137 /* True if bit BIT is set in VALUE. */
138 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
140 /* Return the opcode for a ptr_mode load of the form:
142 l[wd] DEST, OFFSET(BASE). */
143 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
144 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
145 | ((BASE) << 21) \
146 | ((DEST) << 16) \
147 | (OFFSET))
149 /* Return the opcode to move register SRC into register DEST. */
150 #define MIPS_MOVE(DEST, SRC) \
151 ((TARGET_64BIT ? 0x2d : 0x21) \
152 | ((DEST) << 11) \
153 | ((SRC) << 21))
155 /* Return the opcode for:
157 lui DEST, VALUE. */
158 #define MIPS_LUI(DEST, VALUE) \
159 ((0xf << 26) | ((DEST) << 16) | (VALUE))
161 /* Return the opcode to jump to register DEST. When the JR opcode is not
162 available use JALR $0, DEST. */
163 #define MIPS_JR(DEST) \
164 (TARGET_CB_ALWAYS ? ((0x1b << 27) | ((DEST) << 16)) \
165 : (((DEST) << 21) | (ISA_HAS_JR ? 0x8 : 0x9)))
167 /* Return the opcode for:
169 bal . + (1 + OFFSET) * 4. */
170 #define MIPS_BAL(OFFSET) \
171 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
173 /* Return the usual opcode for a nop. */
174 #define MIPS_NOP 0
176 /* Classifies an address.
178 ADDRESS_REG
179 A natural register + offset address. The register satisfies
180 mips_valid_base_register_p and the offset is a const_arith_operand.
182 ADDRESS_LO_SUM
183 A LO_SUM rtx. The first operand is a valid base register and
184 the second operand is a symbolic address.
186 ADDRESS_CONST_INT
187 A signed 16-bit constant address.
189 ADDRESS_SYMBOLIC:
190 A constant symbolic address. */
191 enum mips_address_type {
192 ADDRESS_REG,
193 ADDRESS_LO_SUM,
194 ADDRESS_CONST_INT,
195 ADDRESS_SYMBOLIC
198 /* Macros to create an enumeration identifier for a function prototype. */
199 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
200 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
201 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
202 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
204 /* Classifies the prototype of a built-in function. */
205 enum mips_function_type {
206 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
207 #include "config/mips/mips-ftypes.def"
208 #undef DEF_MIPS_FTYPE
209 MIPS_MAX_FTYPE_MAX
212 /* Specifies how a built-in function should be converted into rtl. */
213 enum mips_builtin_type {
214 /* The function corresponds directly to an .md pattern. The return
215 value is mapped to operand 0 and the arguments are mapped to
216 operands 1 and above. */
217 MIPS_BUILTIN_DIRECT,
219 /* The function corresponds directly to an .md pattern. There is no return
220 value and the arguments are mapped to operands 0 and above. */
221 MIPS_BUILTIN_DIRECT_NO_TARGET,
223 /* The function corresponds to a comparison instruction followed by
224 a mips_cond_move_tf_ps pattern. The first two arguments are the
225 values to compare and the second two arguments are the vector
226 operands for the movt.ps or movf.ps instruction (in assembly order). */
227 MIPS_BUILTIN_MOVF,
228 MIPS_BUILTIN_MOVT,
230 /* The function corresponds to a V2SF comparison instruction. Operand 0
231 of this instruction is the result of the comparison, which has mode
232 CCV2 or CCV4. The function arguments are mapped to operands 1 and
233 above. The function's return value is an SImode boolean that is
234 true under the following conditions:
236 MIPS_BUILTIN_CMP_ANY: one of the registers is true
237 MIPS_BUILTIN_CMP_ALL: all of the registers are true
238 MIPS_BUILTIN_CMP_LOWER: the first register is true
239 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
240 MIPS_BUILTIN_CMP_ANY,
241 MIPS_BUILTIN_CMP_ALL,
242 MIPS_BUILTIN_CMP_UPPER,
243 MIPS_BUILTIN_CMP_LOWER,
245 /* As above, but the instruction only sets a single $fcc register. */
246 MIPS_BUILTIN_CMP_SINGLE,
248 /* The function corresponds to an MSA conditional branch instruction
249 combined with a compare instruction. */
250 MIPS_BUILTIN_MSA_TEST_BRANCH,
252 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
253 MIPS_BUILTIN_BPOSGE32
256 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
257 #define MIPS_FP_CONDITIONS(MACRO) \
258 MACRO (f), \
259 MACRO (un), \
260 MACRO (eq), \
261 MACRO (ueq), \
262 MACRO (olt), \
263 MACRO (ult), \
264 MACRO (ole), \
265 MACRO (ule), \
266 MACRO (sf), \
267 MACRO (ngle), \
268 MACRO (seq), \
269 MACRO (ngl), \
270 MACRO (lt), \
271 MACRO (nge), \
272 MACRO (le), \
273 MACRO (ngt)
275 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
276 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
277 enum mips_fp_condition {
278 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
280 #undef DECLARE_MIPS_COND
282 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
283 #define STRINGIFY(X) #X
284 static const char *const mips_fp_conditions[] = {
285 MIPS_FP_CONDITIONS (STRINGIFY)
287 #undef STRINGIFY
289 /* A class used to control a comdat-style stub that we output in each
290 translation unit that needs it. */
291 class mips_one_only_stub {
292 public:
293 virtual ~mips_one_only_stub () {}
295 /* Return the name of the stub. */
296 virtual const char *get_name () = 0;
298 /* Output the body of the function to asm_out_file. */
299 virtual void output_body () = 0;
302 /* Tuning information that is automatically derived from other sources
303 (such as the scheduler). */
304 static struct {
305 /* The architecture and tuning settings that this structure describes. */
306 enum processor arch;
307 enum processor tune;
309 /* True if this structure describes MIPS16 settings. */
310 bool mips16_p;
312 /* True if the structure has been initialized. */
313 bool initialized_p;
315 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
316 when optimizing for speed. */
317 bool fast_mult_zero_zero_p;
318 } mips_tuning_info;
320 /* Information about a single argument. */
321 struct mips_arg_info {
322 /* True if the argument is passed in a floating-point register, or
323 would have been if we hadn't run out of registers. */
324 bool fpr_p;
326 /* The number of words passed in registers, rounded up. */
327 unsigned int reg_words;
329 /* For EABI, the offset of the first register from GP_ARG_FIRST or
330 FP_ARG_FIRST. For other ABIs, the offset of the first register from
331 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
332 comment for details).
334 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
335 on the stack. */
336 unsigned int reg_offset;
338 /* The number of words that must be passed on the stack, rounded up. */
339 unsigned int stack_words;
341 /* The offset from the start of the stack overflow area of the argument's
342 first stack word. Only meaningful when STACK_WORDS is nonzero. */
343 unsigned int stack_offset;
346 /* Information about an address described by mips_address_type.
348 ADDRESS_CONST_INT
349 No fields are used.
351 ADDRESS_REG
352 REG is the base register and OFFSET is the constant offset.
354 ADDRESS_LO_SUM
355 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
356 is the type of symbol it references.
358 ADDRESS_SYMBOLIC
359 SYMBOL_TYPE is the type of symbol that the address references. */
360 struct mips_address_info {
361 enum mips_address_type type;
362 rtx reg;
363 rtx offset;
364 enum mips_symbol_type symbol_type;
367 /* One stage in a constant building sequence. These sequences have
368 the form:
370 A = VALUE[0]
371 A = A CODE[1] VALUE[1]
372 A = A CODE[2] VALUE[2]
375 where A is an accumulator, each CODE[i] is a binary rtl operation
376 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
377 struct mips_integer_op {
378 enum rtx_code code;
379 unsigned HOST_WIDE_INT value;
382 /* The largest number of operations needed to load an integer constant.
383 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
384 When the lowest bit is clear, we can try, but reject a sequence with
385 an extra SLL at the end. */
386 #define MIPS_MAX_INTEGER_OPS 7
388 /* Information about a MIPS16e SAVE or RESTORE instruction. */
389 struct mips16e_save_restore_info {
390 /* The number of argument registers saved by a SAVE instruction.
391 0 for RESTORE instructions. */
392 unsigned int nargs;
394 /* Bit X is set if the instruction saves or restores GPR X. */
395 unsigned int mask;
397 /* The total number of bytes to allocate. */
398 HOST_WIDE_INT size;
401 /* Costs of various operations on the different architectures. */
403 struct mips_rtx_cost_data
405 unsigned short fp_add;
406 unsigned short fp_mult_sf;
407 unsigned short fp_mult_df;
408 unsigned short fp_div_sf;
409 unsigned short fp_div_df;
410 unsigned short int_mult_si;
411 unsigned short int_mult_di;
412 unsigned short int_div_si;
413 unsigned short int_div_di;
414 unsigned short branch_cost;
415 unsigned short memory_latency;
418 /* Global variables for machine-dependent things. */
420 /* The -G setting, or the configuration's default small-data limit if
421 no -G option is given. */
422 static unsigned int mips_small_data_threshold;
424 /* The number of file directives written by mips_output_filename. */
425 int num_source_filenames;
427 /* The name that appeared in the last .file directive written by
428 mips_output_filename, or "" if mips_output_filename hasn't
429 written anything yet. */
430 const char *current_function_file = "";
432 /* Arrays that map GCC register numbers to debugger register numbers. */
433 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
434 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
436 /* Information about the current function's epilogue, used only while
437 expanding it. */
438 static struct {
439 /* A list of queued REG_CFA_RESTORE notes. */
440 rtx cfa_restores;
442 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
443 rtx cfa_reg;
444 HOST_WIDE_INT cfa_offset;
446 /* The offset of the CFA from the stack pointer while restoring
447 registers. */
448 HOST_WIDE_INT cfa_restore_sp_offset;
449 } mips_epilogue;
451 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
452 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
453 struct mips_asm_switch mips_nomacro = { "macro", 0 };
454 struct mips_asm_switch mips_noat = { "at", 0 };
456 /* True if we're writing out a branch-likely instruction rather than a
457 normal branch. */
458 static bool mips_branch_likely;
460 /* The current instruction-set architecture. */
461 enum processor mips_arch;
462 const struct mips_cpu_info *mips_arch_info;
464 /* The processor that we should tune the code for. */
465 enum processor mips_tune;
466 const struct mips_cpu_info *mips_tune_info;
468 /* The ISA level associated with mips_arch. */
469 int mips_isa;
471 /* The ISA revision level. This is 0 for MIPS I to V and N for
472 MIPS{32,64}rN. */
473 int mips_isa_rev;
475 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
476 static const struct mips_cpu_info *mips_isa_option_info;
478 /* Which cost information to use. */
479 static const struct mips_rtx_cost_data *mips_cost;
481 /* The ambient target flags, excluding MASK_MIPS16. */
482 static int mips_base_target_flags;
484 /* The default compression mode. */
485 unsigned int mips_base_compression_flags;
487 /* The ambient values of other global variables. */
488 static int mips_base_schedule_insns; /* flag_schedule_insns */
489 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
490 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
491 static int mips_base_align_loops; /* align_loops */
492 static int mips_base_align_jumps; /* align_jumps */
493 static int mips_base_align_functions; /* align_functions */
495 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
496 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
498 /* Index C is true if character C is a valid PRINT_OPERAND punctation
499 character. */
500 static bool mips_print_operand_punct[256];
502 static GTY (()) int mips_output_filename_first_time = 1;
504 /* mips_split_p[X] is true if symbols of type X can be split by
505 mips_split_symbol. */
506 bool mips_split_p[NUM_SYMBOL_TYPES];
508 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
509 can be split by mips_split_symbol. */
510 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
512 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
513 forced into a PC-relative constant pool. */
514 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
516 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
517 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
518 if they are matched by a special .md file pattern. */
519 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
521 /* Likewise for HIGHs. */
522 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
524 /* Target state for MIPS16. */
525 struct target_globals *mips16_globals;
527 /* Target state for MICROMIPS. */
528 struct target_globals *micromips_globals;
530 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
531 and returned from mips_sched_reorder2. */
532 static int cached_can_issue_more;
534 /* The stubs for various MIPS16 support functions, if used. */
535 static mips_one_only_stub *mips16_rdhwr_stub;
536 static mips_one_only_stub *mips16_get_fcsr_stub;
537 static mips_one_only_stub *mips16_set_fcsr_stub;
539 /* Index R is the smallest register class that contains register R. */
540 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
541 LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG,
542 M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS,
543 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
544 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
545 M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS,
546 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
547 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
548 LEA_REGS, M16_SP_REGS, LEA_REGS, LEA_REGS,
550 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
551 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
552 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
553 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
554 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
555 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
556 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
557 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
558 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
559 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
560 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
561 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
562 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
563 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
564 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
565 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
566 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
567 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
568 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
569 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
570 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
571 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
572 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
573 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
574 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
575 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
576 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
577 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
578 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
579 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
580 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
581 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
582 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
583 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
584 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
585 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
586 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
587 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
588 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
591 static tree mips_handle_interrupt_attr (tree *, tree, tree, int, bool *);
592 static tree mips_handle_use_shadow_register_set_attr (tree *, tree, tree, int,
593 bool *);
595 /* The value of TARGET_ATTRIBUTE_TABLE. */
596 static const struct attribute_spec mips_attribute_table[] = {
597 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
598 om_diagnostic } */
599 { "long_call", 0, 0, false, true, true, NULL, false },
600 { "far", 0, 0, false, true, true, NULL, false },
601 { "near", 0, 0, false, true, true, NULL, false },
602 /* We would really like to treat "mips16" and "nomips16" as type
603 attributes, but GCC doesn't provide the hooks we need to support
604 the right conversion rules. As declaration attributes, they affect
605 code generation but don't carry other semantics. */
606 { "mips16", 0, 0, true, false, false, NULL, false },
607 { "nomips16", 0, 0, true, false, false, NULL, false },
608 { "micromips", 0, 0, true, false, false, NULL, false },
609 { "nomicromips", 0, 0, true, false, false, NULL, false },
610 { "nocompression", 0, 0, true, false, false, NULL, false },
611 /* Allow functions to be specified as interrupt handlers */
612 { "interrupt", 0, 1, false, true, true, mips_handle_interrupt_attr,
613 false },
614 { "use_shadow_register_set", 0, 1, false, true, true,
615 mips_handle_use_shadow_register_set_attr, false },
616 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
617 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
618 { NULL, 0, 0, false, false, false, NULL, false }
621 /* A table describing all the processors GCC knows about; see
622 mips-cpus.def for details. */
623 static const struct mips_cpu_info mips_cpu_info_table[] = {
624 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
625 { NAME, CPU, ISA, FLAGS },
626 #include "mips-cpus.def"
627 #undef MIPS_CPU
630 /* Default costs. If these are used for a processor we should look
631 up the actual costs. */
632 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
633 COSTS_N_INSNS (7), /* fp_mult_sf */ \
634 COSTS_N_INSNS (8), /* fp_mult_df */ \
635 COSTS_N_INSNS (23), /* fp_div_sf */ \
636 COSTS_N_INSNS (36), /* fp_div_df */ \
637 COSTS_N_INSNS (10), /* int_mult_si */ \
638 COSTS_N_INSNS (10), /* int_mult_di */ \
639 COSTS_N_INSNS (69), /* int_div_si */ \
640 COSTS_N_INSNS (69), /* int_div_di */ \
641 2, /* branch_cost */ \
642 4 /* memory_latency */
644 /* Floating-point costs for processors without an FPU. Just assume that
645 all floating-point libcalls are very expensive. */
646 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
647 COSTS_N_INSNS (256), /* fp_mult_sf */ \
648 COSTS_N_INSNS (256), /* fp_mult_df */ \
649 COSTS_N_INSNS (256), /* fp_div_sf */ \
650 COSTS_N_INSNS (256) /* fp_div_df */
652 /* Costs to use when optimizing for size. */
653 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
654 COSTS_N_INSNS (1), /* fp_add */
655 COSTS_N_INSNS (1), /* fp_mult_sf */
656 COSTS_N_INSNS (1), /* fp_mult_df */
657 COSTS_N_INSNS (1), /* fp_div_sf */
658 COSTS_N_INSNS (1), /* fp_div_df */
659 COSTS_N_INSNS (1), /* int_mult_si */
660 COSTS_N_INSNS (1), /* int_mult_di */
661 COSTS_N_INSNS (1), /* int_div_si */
662 COSTS_N_INSNS (1), /* int_div_di */
663 2, /* branch_cost */
664 4 /* memory_latency */
667 /* Costs to use when optimizing for speed, indexed by processor. */
668 static const struct mips_rtx_cost_data
669 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
670 { /* R3000 */
671 COSTS_N_INSNS (2), /* fp_add */
672 COSTS_N_INSNS (4), /* fp_mult_sf */
673 COSTS_N_INSNS (5), /* fp_mult_df */
674 COSTS_N_INSNS (12), /* fp_div_sf */
675 COSTS_N_INSNS (19), /* fp_div_df */
676 COSTS_N_INSNS (12), /* int_mult_si */
677 COSTS_N_INSNS (12), /* int_mult_di */
678 COSTS_N_INSNS (35), /* int_div_si */
679 COSTS_N_INSNS (35), /* int_div_di */
680 1, /* branch_cost */
681 4 /* memory_latency */
683 { /* 4KC */
684 SOFT_FP_COSTS,
685 COSTS_N_INSNS (6), /* int_mult_si */
686 COSTS_N_INSNS (6), /* int_mult_di */
687 COSTS_N_INSNS (36), /* int_div_si */
688 COSTS_N_INSNS (36), /* int_div_di */
689 1, /* branch_cost */
690 4 /* memory_latency */
692 { /* 4KP */
693 SOFT_FP_COSTS,
694 COSTS_N_INSNS (36), /* int_mult_si */
695 COSTS_N_INSNS (36), /* int_mult_di */
696 COSTS_N_INSNS (37), /* int_div_si */
697 COSTS_N_INSNS (37), /* int_div_di */
698 1, /* branch_cost */
699 4 /* memory_latency */
701 { /* 5KC */
702 SOFT_FP_COSTS,
703 COSTS_N_INSNS (4), /* int_mult_si */
704 COSTS_N_INSNS (11), /* int_mult_di */
705 COSTS_N_INSNS (36), /* int_div_si */
706 COSTS_N_INSNS (68), /* int_div_di */
707 1, /* branch_cost */
708 4 /* memory_latency */
710 { /* 5KF */
711 COSTS_N_INSNS (4), /* fp_add */
712 COSTS_N_INSNS (4), /* fp_mult_sf */
713 COSTS_N_INSNS (5), /* fp_mult_df */
714 COSTS_N_INSNS (17), /* fp_div_sf */
715 COSTS_N_INSNS (32), /* fp_div_df */
716 COSTS_N_INSNS (4), /* int_mult_si */
717 COSTS_N_INSNS (11), /* int_mult_di */
718 COSTS_N_INSNS (36), /* int_div_si */
719 COSTS_N_INSNS (68), /* int_div_di */
720 1, /* branch_cost */
721 4 /* memory_latency */
723 { /* 20KC */
724 COSTS_N_INSNS (4), /* fp_add */
725 COSTS_N_INSNS (4), /* fp_mult_sf */
726 COSTS_N_INSNS (5), /* fp_mult_df */
727 COSTS_N_INSNS (17), /* fp_div_sf */
728 COSTS_N_INSNS (32), /* fp_div_df */
729 COSTS_N_INSNS (4), /* int_mult_si */
730 COSTS_N_INSNS (7), /* int_mult_di */
731 COSTS_N_INSNS (42), /* int_div_si */
732 COSTS_N_INSNS (72), /* int_div_di */
733 1, /* branch_cost */
734 4 /* memory_latency */
736 { /* 24KC */
737 SOFT_FP_COSTS,
738 COSTS_N_INSNS (5), /* int_mult_si */
739 COSTS_N_INSNS (5), /* int_mult_di */
740 COSTS_N_INSNS (41), /* int_div_si */
741 COSTS_N_INSNS (41), /* int_div_di */
742 1, /* branch_cost */
743 4 /* memory_latency */
745 { /* 24KF2_1 */
746 COSTS_N_INSNS (8), /* fp_add */
747 COSTS_N_INSNS (8), /* fp_mult_sf */
748 COSTS_N_INSNS (10), /* fp_mult_df */
749 COSTS_N_INSNS (34), /* fp_div_sf */
750 COSTS_N_INSNS (64), /* fp_div_df */
751 COSTS_N_INSNS (5), /* int_mult_si */
752 COSTS_N_INSNS (5), /* int_mult_di */
753 COSTS_N_INSNS (41), /* int_div_si */
754 COSTS_N_INSNS (41), /* int_div_di */
755 1, /* branch_cost */
756 4 /* memory_latency */
758 { /* 24KF1_1 */
759 COSTS_N_INSNS (4), /* fp_add */
760 COSTS_N_INSNS (4), /* fp_mult_sf */
761 COSTS_N_INSNS (5), /* fp_mult_df */
762 COSTS_N_INSNS (17), /* fp_div_sf */
763 COSTS_N_INSNS (32), /* fp_div_df */
764 COSTS_N_INSNS (5), /* int_mult_si */
765 COSTS_N_INSNS (5), /* int_mult_di */
766 COSTS_N_INSNS (41), /* int_div_si */
767 COSTS_N_INSNS (41), /* int_div_di */
768 1, /* branch_cost */
769 4 /* memory_latency */
771 { /* 74KC */
772 SOFT_FP_COSTS,
773 COSTS_N_INSNS (5), /* int_mult_si */
774 COSTS_N_INSNS (5), /* int_mult_di */
775 COSTS_N_INSNS (41), /* int_div_si */
776 COSTS_N_INSNS (41), /* int_div_di */
777 1, /* branch_cost */
778 4 /* memory_latency */
780 { /* 74KF2_1 */
781 COSTS_N_INSNS (8), /* fp_add */
782 COSTS_N_INSNS (8), /* fp_mult_sf */
783 COSTS_N_INSNS (10), /* fp_mult_df */
784 COSTS_N_INSNS (34), /* fp_div_sf */
785 COSTS_N_INSNS (64), /* fp_div_df */
786 COSTS_N_INSNS (5), /* int_mult_si */
787 COSTS_N_INSNS (5), /* int_mult_di */
788 COSTS_N_INSNS (41), /* int_div_si */
789 COSTS_N_INSNS (41), /* int_div_di */
790 1, /* branch_cost */
791 4 /* memory_latency */
793 { /* 74KF1_1 */
794 COSTS_N_INSNS (4), /* fp_add */
795 COSTS_N_INSNS (4), /* fp_mult_sf */
796 COSTS_N_INSNS (5), /* fp_mult_df */
797 COSTS_N_INSNS (17), /* fp_div_sf */
798 COSTS_N_INSNS (32), /* fp_div_df */
799 COSTS_N_INSNS (5), /* int_mult_si */
800 COSTS_N_INSNS (5), /* int_mult_di */
801 COSTS_N_INSNS (41), /* int_div_si */
802 COSTS_N_INSNS (41), /* int_div_di */
803 1, /* branch_cost */
804 4 /* memory_latency */
806 { /* 74KF3_2 */
807 COSTS_N_INSNS (6), /* fp_add */
808 COSTS_N_INSNS (6), /* fp_mult_sf */
809 COSTS_N_INSNS (7), /* fp_mult_df */
810 COSTS_N_INSNS (25), /* fp_div_sf */
811 COSTS_N_INSNS (48), /* fp_div_df */
812 COSTS_N_INSNS (5), /* int_mult_si */
813 COSTS_N_INSNS (5), /* int_mult_di */
814 COSTS_N_INSNS (41), /* int_div_si */
815 COSTS_N_INSNS (41), /* int_div_di */
816 1, /* branch_cost */
817 4 /* memory_latency */
819 { /* Loongson-2E */
820 DEFAULT_COSTS
822 { /* Loongson-2F */
823 DEFAULT_COSTS
825 { /* Loongson-3A */
826 DEFAULT_COSTS
828 { /* M4k */
829 DEFAULT_COSTS
831 /* Octeon */
833 SOFT_FP_COSTS,
834 COSTS_N_INSNS (5), /* int_mult_si */
835 COSTS_N_INSNS (5), /* int_mult_di */
836 COSTS_N_INSNS (72), /* int_div_si */
837 COSTS_N_INSNS (72), /* int_div_di */
838 1, /* branch_cost */
839 4 /* memory_latency */
841 /* Octeon II */
843 SOFT_FP_COSTS,
844 COSTS_N_INSNS (6), /* int_mult_si */
845 COSTS_N_INSNS (6), /* int_mult_di */
846 COSTS_N_INSNS (18), /* int_div_si */
847 COSTS_N_INSNS (35), /* int_div_di */
848 4, /* branch_cost */
849 4 /* memory_latency */
851 /* Octeon III */
853 COSTS_N_INSNS (6), /* fp_add */
854 COSTS_N_INSNS (6), /* fp_mult_sf */
855 COSTS_N_INSNS (7), /* fp_mult_df */
856 COSTS_N_INSNS (25), /* fp_div_sf */
857 COSTS_N_INSNS (48), /* fp_div_df */
858 COSTS_N_INSNS (6), /* int_mult_si */
859 COSTS_N_INSNS (6), /* int_mult_di */
860 COSTS_N_INSNS (18), /* int_div_si */
861 COSTS_N_INSNS (35), /* int_div_di */
862 4, /* branch_cost */
863 4 /* memory_latency */
865 { /* R3900 */
866 COSTS_N_INSNS (2), /* fp_add */
867 COSTS_N_INSNS (4), /* fp_mult_sf */
868 COSTS_N_INSNS (5), /* fp_mult_df */
869 COSTS_N_INSNS (12), /* fp_div_sf */
870 COSTS_N_INSNS (19), /* fp_div_df */
871 COSTS_N_INSNS (2), /* int_mult_si */
872 COSTS_N_INSNS (2), /* int_mult_di */
873 COSTS_N_INSNS (35), /* int_div_si */
874 COSTS_N_INSNS (35), /* int_div_di */
875 1, /* branch_cost */
876 4 /* memory_latency */
878 { /* R6000 */
879 COSTS_N_INSNS (3), /* fp_add */
880 COSTS_N_INSNS (5), /* fp_mult_sf */
881 COSTS_N_INSNS (6), /* fp_mult_df */
882 COSTS_N_INSNS (15), /* fp_div_sf */
883 COSTS_N_INSNS (16), /* fp_div_df */
884 COSTS_N_INSNS (17), /* int_mult_si */
885 COSTS_N_INSNS (17), /* int_mult_di */
886 COSTS_N_INSNS (38), /* int_div_si */
887 COSTS_N_INSNS (38), /* int_div_di */
888 2, /* branch_cost */
889 6 /* memory_latency */
891 { /* R4000 */
892 COSTS_N_INSNS (6), /* fp_add */
893 COSTS_N_INSNS (7), /* fp_mult_sf */
894 COSTS_N_INSNS (8), /* fp_mult_df */
895 COSTS_N_INSNS (23), /* fp_div_sf */
896 COSTS_N_INSNS (36), /* fp_div_df */
897 COSTS_N_INSNS (10), /* int_mult_si */
898 COSTS_N_INSNS (10), /* int_mult_di */
899 COSTS_N_INSNS (69), /* int_div_si */
900 COSTS_N_INSNS (69), /* int_div_di */
901 2, /* branch_cost */
902 6 /* memory_latency */
904 { /* R4100 */
905 DEFAULT_COSTS
907 { /* R4111 */
908 DEFAULT_COSTS
910 { /* R4120 */
911 DEFAULT_COSTS
913 { /* R4130 */
914 /* The only costs that appear to be updated here are
915 integer multiplication. */
916 SOFT_FP_COSTS,
917 COSTS_N_INSNS (4), /* int_mult_si */
918 COSTS_N_INSNS (6), /* int_mult_di */
919 COSTS_N_INSNS (69), /* int_div_si */
920 COSTS_N_INSNS (69), /* int_div_di */
921 1, /* branch_cost */
922 4 /* memory_latency */
924 { /* R4300 */
925 DEFAULT_COSTS
927 { /* R4600 */
928 DEFAULT_COSTS
930 { /* R4650 */
931 DEFAULT_COSTS
933 { /* R4700 */
934 DEFAULT_COSTS
936 { /* R5000 */
937 COSTS_N_INSNS (6), /* fp_add */
938 COSTS_N_INSNS (4), /* fp_mult_sf */
939 COSTS_N_INSNS (5), /* fp_mult_df */
940 COSTS_N_INSNS (23), /* fp_div_sf */
941 COSTS_N_INSNS (36), /* fp_div_df */
942 COSTS_N_INSNS (5), /* int_mult_si */
943 COSTS_N_INSNS (5), /* int_mult_di */
944 COSTS_N_INSNS (36), /* int_div_si */
945 COSTS_N_INSNS (36), /* int_div_di */
946 1, /* branch_cost */
947 4 /* memory_latency */
949 { /* R5400 */
950 COSTS_N_INSNS (6), /* fp_add */
951 COSTS_N_INSNS (5), /* fp_mult_sf */
952 COSTS_N_INSNS (6), /* fp_mult_df */
953 COSTS_N_INSNS (30), /* fp_div_sf */
954 COSTS_N_INSNS (59), /* fp_div_df */
955 COSTS_N_INSNS (3), /* int_mult_si */
956 COSTS_N_INSNS (4), /* int_mult_di */
957 COSTS_N_INSNS (42), /* int_div_si */
958 COSTS_N_INSNS (74), /* int_div_di */
959 1, /* branch_cost */
960 4 /* memory_latency */
962 { /* R5500 */
963 COSTS_N_INSNS (6), /* fp_add */
964 COSTS_N_INSNS (5), /* fp_mult_sf */
965 COSTS_N_INSNS (6), /* fp_mult_df */
966 COSTS_N_INSNS (30), /* fp_div_sf */
967 COSTS_N_INSNS (59), /* fp_div_df */
968 COSTS_N_INSNS (5), /* int_mult_si */
969 COSTS_N_INSNS (9), /* int_mult_di */
970 COSTS_N_INSNS (42), /* int_div_si */
971 COSTS_N_INSNS (74), /* int_div_di */
972 1, /* branch_cost */
973 4 /* memory_latency */
975 { /* R5900 */
976 COSTS_N_INSNS (4), /* fp_add */
977 COSTS_N_INSNS (4), /* fp_mult_sf */
978 COSTS_N_INSNS (256), /* fp_mult_df */
979 COSTS_N_INSNS (8), /* fp_div_sf */
980 COSTS_N_INSNS (256), /* fp_div_df */
981 COSTS_N_INSNS (4), /* int_mult_si */
982 COSTS_N_INSNS (256), /* int_mult_di */
983 COSTS_N_INSNS (37), /* int_div_si */
984 COSTS_N_INSNS (256), /* int_div_di */
985 1, /* branch_cost */
986 4 /* memory_latency */
988 { /* R7000 */
989 /* The only costs that are changed here are
990 integer multiplication. */
991 COSTS_N_INSNS (6), /* fp_add */
992 COSTS_N_INSNS (7), /* fp_mult_sf */
993 COSTS_N_INSNS (8), /* fp_mult_df */
994 COSTS_N_INSNS (23), /* fp_div_sf */
995 COSTS_N_INSNS (36), /* fp_div_df */
996 COSTS_N_INSNS (5), /* int_mult_si */
997 COSTS_N_INSNS (9), /* int_mult_di */
998 COSTS_N_INSNS (69), /* int_div_si */
999 COSTS_N_INSNS (69), /* int_div_di */
1000 1, /* branch_cost */
1001 4 /* memory_latency */
1003 { /* R8000 */
1004 DEFAULT_COSTS
1006 { /* R9000 */
1007 /* The only costs that are changed here are
1008 integer multiplication. */
1009 COSTS_N_INSNS (6), /* fp_add */
1010 COSTS_N_INSNS (7), /* fp_mult_sf */
1011 COSTS_N_INSNS (8), /* fp_mult_df */
1012 COSTS_N_INSNS (23), /* fp_div_sf */
1013 COSTS_N_INSNS (36), /* fp_div_df */
1014 COSTS_N_INSNS (3), /* int_mult_si */
1015 COSTS_N_INSNS (8), /* int_mult_di */
1016 COSTS_N_INSNS (69), /* int_div_si */
1017 COSTS_N_INSNS (69), /* int_div_di */
1018 1, /* branch_cost */
1019 4 /* memory_latency */
1021 { /* R1x000 */
1022 COSTS_N_INSNS (2), /* fp_add */
1023 COSTS_N_INSNS (2), /* fp_mult_sf */
1024 COSTS_N_INSNS (2), /* fp_mult_df */
1025 COSTS_N_INSNS (12), /* fp_div_sf */
1026 COSTS_N_INSNS (19), /* fp_div_df */
1027 COSTS_N_INSNS (5), /* int_mult_si */
1028 COSTS_N_INSNS (9), /* int_mult_di */
1029 COSTS_N_INSNS (34), /* int_div_si */
1030 COSTS_N_INSNS (66), /* int_div_di */
1031 1, /* branch_cost */
1032 4 /* memory_latency */
1034 { /* SB1 */
1035 /* These costs are the same as the SB-1A below. */
1036 COSTS_N_INSNS (4), /* fp_add */
1037 COSTS_N_INSNS (4), /* fp_mult_sf */
1038 COSTS_N_INSNS (4), /* fp_mult_df */
1039 COSTS_N_INSNS (24), /* fp_div_sf */
1040 COSTS_N_INSNS (32), /* fp_div_df */
1041 COSTS_N_INSNS (3), /* int_mult_si */
1042 COSTS_N_INSNS (4), /* int_mult_di */
1043 COSTS_N_INSNS (36), /* int_div_si */
1044 COSTS_N_INSNS (68), /* int_div_di */
1045 1, /* branch_cost */
1046 4 /* memory_latency */
1048 { /* SB1-A */
1049 /* These costs are the same as the SB-1 above. */
1050 COSTS_N_INSNS (4), /* fp_add */
1051 COSTS_N_INSNS (4), /* fp_mult_sf */
1052 COSTS_N_INSNS (4), /* fp_mult_df */
1053 COSTS_N_INSNS (24), /* fp_div_sf */
1054 COSTS_N_INSNS (32), /* fp_div_df */
1055 COSTS_N_INSNS (3), /* int_mult_si */
1056 COSTS_N_INSNS (4), /* int_mult_di */
1057 COSTS_N_INSNS (36), /* int_div_si */
1058 COSTS_N_INSNS (68), /* int_div_di */
1059 1, /* branch_cost */
1060 4 /* memory_latency */
1062 { /* SR71000 */
1063 DEFAULT_COSTS
1065 { /* XLR */
1066 SOFT_FP_COSTS,
1067 COSTS_N_INSNS (8), /* int_mult_si */
1068 COSTS_N_INSNS (8), /* int_mult_di */
1069 COSTS_N_INSNS (72), /* int_div_si */
1070 COSTS_N_INSNS (72), /* int_div_di */
1071 1, /* branch_cost */
1072 4 /* memory_latency */
1074 { /* XLP */
1075 /* These costs are the same as 5KF above. */
1076 COSTS_N_INSNS (4), /* fp_add */
1077 COSTS_N_INSNS (4), /* fp_mult_sf */
1078 COSTS_N_INSNS (5), /* fp_mult_df */
1079 COSTS_N_INSNS (17), /* fp_div_sf */
1080 COSTS_N_INSNS (32), /* fp_div_df */
1081 COSTS_N_INSNS (4), /* int_mult_si */
1082 COSTS_N_INSNS (11), /* int_mult_di */
1083 COSTS_N_INSNS (36), /* int_div_si */
1084 COSTS_N_INSNS (68), /* int_div_di */
1085 1, /* branch_cost */
1086 4 /* memory_latency */
1088 { /* P5600 */
1089 COSTS_N_INSNS (4), /* fp_add */
1090 COSTS_N_INSNS (5), /* fp_mult_sf */
1091 COSTS_N_INSNS (5), /* fp_mult_df */
1092 COSTS_N_INSNS (17), /* fp_div_sf */
1093 COSTS_N_INSNS (17), /* fp_div_df */
1094 COSTS_N_INSNS (5), /* int_mult_si */
1095 COSTS_N_INSNS (5), /* int_mult_di */
1096 COSTS_N_INSNS (8), /* int_div_si */
1097 COSTS_N_INSNS (8), /* int_div_di */
1098 2, /* branch_cost */
1099 4 /* memory_latency */
1101 { /* M5100 */
1102 COSTS_N_INSNS (4), /* fp_add */
1103 COSTS_N_INSNS (4), /* fp_mult_sf */
1104 COSTS_N_INSNS (5), /* fp_mult_df */
1105 COSTS_N_INSNS (17), /* fp_div_sf */
1106 COSTS_N_INSNS (32), /* fp_div_df */
1107 COSTS_N_INSNS (5), /* int_mult_si */
1108 COSTS_N_INSNS (5), /* int_mult_di */
1109 COSTS_N_INSNS (34), /* int_div_si */
1110 COSTS_N_INSNS (68), /* int_div_di */
1111 1, /* branch_cost */
1112 4 /* memory_latency */
1114 { /* I6400 */
1115 COSTS_N_INSNS (4), /* fp_add */
1116 COSTS_N_INSNS (5), /* fp_mult_sf */
1117 COSTS_N_INSNS (5), /* fp_mult_df */
1118 COSTS_N_INSNS (32), /* fp_div_sf */
1119 COSTS_N_INSNS (32), /* fp_div_df */
1120 COSTS_N_INSNS (5), /* int_mult_si */
1121 COSTS_N_INSNS (5), /* int_mult_di */
1122 COSTS_N_INSNS (36), /* int_div_si */
1123 COSTS_N_INSNS (36), /* int_div_di */
1124 2, /* branch_cost */
1125 4 /* memory_latency */
1129 static rtx mips_find_pic_call_symbol (rtx_insn *, rtx, bool);
1130 static int mips_register_move_cost (machine_mode, reg_class_t,
1131 reg_class_t);
1132 static unsigned int mips_function_arg_boundary (machine_mode, const_tree);
1133 static machine_mode mips_get_reg_raw_mode (int regno);
1134 static rtx mips_gen_const_int_vector_shuffle (machine_mode, int);
1136 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1137 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1138 static GTY (()) hash_map<nofree_string_hash, bool> *mflip_mips16_htab;
1140 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1141 mode, false if it should next add an attribute for the opposite mode. */
1142 static GTY(()) bool mips16_flipper;
1144 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1145 for -mflip-mips16. Return true if it should use "mips16" and false if
1146 it should use "nomips16". */
1148 static bool
1149 mflip_mips16_use_mips16_p (tree decl)
1151 const char *name;
1152 bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0;
1154 /* Use the opposite of the command-line setting for anonymous decls. */
1155 if (!DECL_NAME (decl))
1156 return !base_is_mips16;
1158 if (!mflip_mips16_htab)
1159 mflip_mips16_htab = hash_map<nofree_string_hash, bool>::create_ggc (37);
1161 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1163 bool existed;
1164 bool *slot = &mflip_mips16_htab->get_or_insert (name, &existed);
1165 if (!existed)
1167 mips16_flipper = !mips16_flipper;
1168 *slot = mips16_flipper ? !base_is_mips16 : base_is_mips16;
1170 return *slot;
1173 /* Predicates to test for presence of "near" and "far"/"long_call"
1174 attributes on the given TYPE. */
1176 static bool
1177 mips_near_type_p (const_tree type)
1179 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1182 static bool
1183 mips_far_type_p (const_tree type)
1185 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1186 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1190 /* Check if the interrupt attribute is set for a function. */
1192 static bool
1193 mips_interrupt_type_p (tree type)
1195 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1198 /* Return the mask for the "interrupt" attribute. */
1200 static enum mips_int_mask
1201 mips_interrupt_mask (tree type)
1203 tree attr = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type));
1204 tree args, cst;
1205 const char *str;
1207 /* For missing attributes or no arguments then return 'eic' as a safe
1208 fallback. */
1209 if (attr == NULL)
1210 return INT_MASK_EIC;
1212 args = TREE_VALUE (attr);
1214 if (args == NULL)
1215 return INT_MASK_EIC;
1217 cst = TREE_VALUE (args);
1219 if (strcmp (TREE_STRING_POINTER (cst), "eic") == 0)
1220 return INT_MASK_EIC;
1222 /* The validation code in mips_handle_interrupt_attr guarantees that the
1223 argument is now in the form:
1224 vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5). */
1225 str = TREE_STRING_POINTER (cst);
1227 gcc_assert (strlen (str) == strlen ("vector=sw0"));
1229 if (str[7] == 's')
1230 return (enum mips_int_mask) (INT_MASK_SW0 + (str[9] - '0'));
1232 return (enum mips_int_mask) (INT_MASK_HW0 + (str[9] - '0'));
1235 /* Return the mips_shadow_set if the "use_shadow_register_set" attribute is
1236 set for a function. */
1238 static enum mips_shadow_set
1239 mips_use_shadow_register_set (tree type)
1241 tree attr = lookup_attribute ("use_shadow_register_set",
1242 TYPE_ATTRIBUTES (type));
1243 tree args;
1245 /* The validation code in mips_handle_use_shadow_register_set_attr guarantees
1246 that if an argument is present then it means: Assume the shadow register
1247 set has a valid stack pointer in it. */
1248 if (attr == NULL)
1249 return SHADOW_SET_NO;
1251 args = TREE_VALUE (attr);
1253 if (args == NULL)
1254 return SHADOW_SET_YES;
1256 return SHADOW_SET_INTSTACK;
1259 /* Check if the attribute to keep interrupts masked is set for a function. */
1261 static bool
1262 mips_keep_interrupts_masked_p (tree type)
1264 return lookup_attribute ("keep_interrupts_masked",
1265 TYPE_ATTRIBUTES (type)) != NULL;
1268 /* Check if the attribute to use debug exception return is set for
1269 a function. */
1271 static bool
1272 mips_use_debug_exception_return_p (tree type)
1274 return lookup_attribute ("use_debug_exception_return",
1275 TYPE_ATTRIBUTES (type)) != NULL;
1278 /* Return the set of compression modes that are explicitly required
1279 by the attributes in ATTRIBUTES. */
1281 static unsigned int
1282 mips_get_compress_on_flags (tree attributes)
1284 unsigned int flags = 0;
1286 if (lookup_attribute ("mips16", attributes) != NULL)
1287 flags |= MASK_MIPS16;
1289 if (lookup_attribute ("micromips", attributes) != NULL)
1290 flags |= MASK_MICROMIPS;
1292 return flags;
1295 /* Return the set of compression modes that are explicitly forbidden
1296 by the attributes in ATTRIBUTES. */
1298 static unsigned int
1299 mips_get_compress_off_flags (tree attributes)
1301 unsigned int flags = 0;
1303 if (lookup_attribute ("nocompression", attributes) != NULL)
1304 flags |= MASK_MIPS16 | MASK_MICROMIPS;
1306 if (lookup_attribute ("nomips16", attributes) != NULL)
1307 flags |= MASK_MIPS16;
1309 if (lookup_attribute ("nomicromips", attributes) != NULL)
1310 flags |= MASK_MICROMIPS;
1312 return flags;
1315 /* Return the compression mode that should be used for function DECL.
1316 Return the ambient setting if DECL is null. */
1318 static unsigned int
1319 mips_get_compress_mode (tree decl)
1321 unsigned int flags, force_on;
1323 flags = mips_base_compression_flags;
1324 if (decl)
1326 /* Nested functions must use the same frame pointer as their
1327 parent and must therefore use the same ISA mode. */
1328 tree parent = decl_function_context (decl);
1329 if (parent)
1330 decl = parent;
1331 force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1332 if (force_on)
1333 return force_on;
1334 flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1336 return flags;
1339 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1340 flags FLAGS. */
1342 static const char *
1343 mips_get_compress_on_name (unsigned int flags)
1345 if (flags == MASK_MIPS16)
1346 return "mips16";
1347 return "micromips";
1350 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1351 flags FLAGS. */
1353 static const char *
1354 mips_get_compress_off_name (unsigned int flags)
1356 if (flags == MASK_MIPS16)
1357 return "nomips16";
1358 if (flags == MASK_MICROMIPS)
1359 return "nomicromips";
1360 return "nocompression";
1363 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1365 static int
1366 mips_comp_type_attributes (const_tree type1, const_tree type2)
1368 /* Disallow mixed near/far attributes. */
1369 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1370 return 0;
1371 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1372 return 0;
1373 return 1;
1376 /* Implement TARGET_INSERT_ATTRIBUTES. */
1378 static void
1379 mips_insert_attributes (tree decl, tree *attributes)
1381 const char *name;
1382 unsigned int compression_flags, nocompression_flags;
1384 /* Check for "mips16" and "nomips16" attributes. */
1385 compression_flags = mips_get_compress_on_flags (*attributes);
1386 nocompression_flags = mips_get_compress_off_flags (*attributes);
1388 if (TREE_CODE (decl) != FUNCTION_DECL)
1390 if (nocompression_flags)
1391 error ("%qs attribute only applies to functions",
1392 mips_get_compress_off_name (nocompression_flags));
1394 if (compression_flags)
1395 error ("%qs attribute only applies to functions",
1396 mips_get_compress_on_name (nocompression_flags));
1398 else
1400 compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1401 nocompression_flags |=
1402 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1404 if (compression_flags && nocompression_flags)
1405 error ("%qE cannot have both %qs and %qs attributes",
1406 DECL_NAME (decl), mips_get_compress_on_name (compression_flags),
1407 mips_get_compress_off_name (nocompression_flags));
1409 if (compression_flags & MASK_MIPS16
1410 && compression_flags & MASK_MICROMIPS)
1411 error ("%qE cannot have both %qs and %qs attributes",
1412 DECL_NAME (decl), "mips16", "micromips");
1414 if (TARGET_FLIP_MIPS16
1415 && !DECL_ARTIFICIAL (decl)
1416 && compression_flags == 0
1417 && nocompression_flags == 0)
1419 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1420 "mips16" attribute, arbitrarily pick one. We must pick the same
1421 setting for duplicate declarations of a function. */
1422 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1423 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1424 name = "nomicromips";
1425 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1430 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1432 static tree
1433 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1435 unsigned int diff;
1437 diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl))
1438 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl)));
1439 if (diff)
1440 error ("%qE redeclared with conflicting %qs attributes",
1441 DECL_NAME (newdecl), mips_get_compress_on_name (diff));
1443 diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl))
1444 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl)));
1445 if (diff)
1446 error ("%qE redeclared with conflicting %qs attributes",
1447 DECL_NAME (newdecl), mips_get_compress_off_name (diff));
1449 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1450 DECL_ATTRIBUTES (newdecl));
1453 /* Implement TARGET_CAN_INLINE_P. */
1455 static bool
1456 mips_can_inline_p (tree caller, tree callee)
1458 if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller))
1459 return false;
1460 return default_target_can_inline_p (caller, callee);
1463 /* Handle an "interrupt" attribute with an optional argument. */
1465 static tree
1466 mips_handle_interrupt_attr (tree *node ATTRIBUTE_UNUSED, tree name, tree args,
1467 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
1469 /* Check for an argument. */
1470 if (is_attribute_p ("interrupt", name) && args != NULL)
1472 tree cst;
1474 cst = TREE_VALUE (args);
1475 if (TREE_CODE (cst) != STRING_CST)
1477 warning (OPT_Wattributes,
1478 "%qE attribute requires a string argument",
1479 name);
1480 *no_add_attrs = true;
1482 else if (strcmp (TREE_STRING_POINTER (cst), "eic") != 0
1483 && strncmp (TREE_STRING_POINTER (cst), "vector=", 7) != 0)
1485 warning (OPT_Wattributes,
1486 "argument to %qE attribute is neither eic, nor "
1487 "vector=<line>", name);
1488 *no_add_attrs = true;
1490 else if (strncmp (TREE_STRING_POINTER (cst), "vector=", 7) == 0)
1492 const char *arg = TREE_STRING_POINTER (cst) + 7;
1494 /* Acceptable names are: sw0,sw1,hw0,hw1,hw2,hw3,hw4,hw5. */
1495 if (strlen (arg) != 3
1496 || (arg[0] != 's' && arg[0] != 'h')
1497 || arg[1] != 'w'
1498 || (arg[0] == 's' && arg[2] != '0' && arg[2] != '1')
1499 || (arg[0] == 'h' && (arg[2] < '0' || arg[2] > '5')))
1501 warning (OPT_Wattributes,
1502 "interrupt vector to %qE attribute is not "
1503 "vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5)",
1504 name);
1505 *no_add_attrs = true;
1509 return NULL_TREE;
1512 return NULL_TREE;
1515 /* Handle a "use_shadow_register_set" attribute with an optional argument. */
1517 static tree
1518 mips_handle_use_shadow_register_set_attr (tree *node ATTRIBUTE_UNUSED,
1519 tree name, tree args,
1520 int flags ATTRIBUTE_UNUSED,
1521 bool *no_add_attrs)
1523 /* Check for an argument. */
1524 if (is_attribute_p ("use_shadow_register_set", name) && args != NULL)
1526 tree cst;
1528 cst = TREE_VALUE (args);
1529 if (TREE_CODE (cst) != STRING_CST)
1531 warning (OPT_Wattributes,
1532 "%qE attribute requires a string argument",
1533 name);
1534 *no_add_attrs = true;
1536 else if (strcmp (TREE_STRING_POINTER (cst), "intstack") != 0)
1538 warning (OPT_Wattributes,
1539 "argument to %qE attribute is not intstack", name);
1540 *no_add_attrs = true;
1543 return NULL_TREE;
1546 return NULL_TREE;
1549 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1550 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1552 static void
1553 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1555 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1557 *base_ptr = XEXP (x, 0);
1558 *offset_ptr = INTVAL (XEXP (x, 1));
1560 else
1562 *base_ptr = x;
1563 *offset_ptr = 0;
1567 static unsigned int mips_build_integer (struct mips_integer_op *,
1568 unsigned HOST_WIDE_INT);
1570 /* A subroutine of mips_build_integer, with the same interface.
1571 Assume that the final action in the sequence should be a left shift. */
1573 static unsigned int
1574 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1576 unsigned int i, shift;
1578 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1579 since signed numbers are easier to load than unsigned ones. */
1580 shift = 0;
1581 while ((value & 1) == 0)
1582 value /= 2, shift++;
1584 i = mips_build_integer (codes, value);
1585 codes[i].code = ASHIFT;
1586 codes[i].value = shift;
1587 return i + 1;
1590 /* As for mips_build_shift, but assume that the final action will be
1591 an IOR or PLUS operation. */
1593 static unsigned int
1594 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1596 unsigned HOST_WIDE_INT high;
1597 unsigned int i;
1599 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1600 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1602 /* The constant is too complex to load with a simple LUI/ORI pair,
1603 so we want to give the recursive call as many trailing zeros as
1604 possible. In this case, we know bit 16 is set and that the
1605 low 16 bits form a negative number. If we subtract that number
1606 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1607 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1608 codes[i].code = PLUS;
1609 codes[i].value = CONST_LOW_PART (value);
1611 else
1613 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1614 bits gives a value with at least 17 trailing zeros. */
1615 i = mips_build_integer (codes, high);
1616 codes[i].code = IOR;
1617 codes[i].value = value & 0xffff;
1619 return i + 1;
1622 /* Fill CODES with a sequence of rtl operations to load VALUE.
1623 Return the number of operations needed. */
1625 static unsigned int
1626 mips_build_integer (struct mips_integer_op *codes,
1627 unsigned HOST_WIDE_INT value)
1629 if (SMALL_OPERAND (value)
1630 || SMALL_OPERAND_UNSIGNED (value)
1631 || LUI_OPERAND (value))
1633 /* The value can be loaded with a single instruction. */
1634 codes[0].code = UNKNOWN;
1635 codes[0].value = value;
1636 return 1;
1638 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1640 /* Either the constant is a simple LUI/ORI combination or its
1641 lowest bit is set. We don't want to shift in this case. */
1642 return mips_build_lower (codes, value);
1644 else if ((value & 0xffff) == 0)
1646 /* The constant will need at least three actions. The lowest
1647 16 bits are clear, so the final action will be a shift. */
1648 return mips_build_shift (codes, value);
1650 else
1652 /* The final action could be a shift, add or inclusive OR.
1653 Rather than use a complex condition to select the best
1654 approach, try both mips_build_shift and mips_build_lower
1655 and pick the one that gives the shortest sequence.
1656 Note that this case is only used once per constant. */
1657 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1658 unsigned int cost, alt_cost;
1660 cost = mips_build_shift (codes, value);
1661 alt_cost = mips_build_lower (alt_codes, value);
1662 if (alt_cost < cost)
1664 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1665 cost = alt_cost;
1667 return cost;
1671 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1673 static bool
1674 mips_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1676 return mips_const_insns (x) > 0;
1679 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1681 static rtx
1682 mips16_stub_function (const char *name)
1684 rtx x;
1686 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1687 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1688 return x;
1691 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1692 support function. */
1694 static rtx
1695 mips16_stub_call_address (mips_one_only_stub *stub)
1697 rtx fn = mips16_stub_function (stub->get_name ());
1698 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
1699 if (!call_insn_operand (fn, VOIDmode))
1700 fn = force_reg (Pmode, fn);
1701 return fn;
1704 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1706 class mips16_rdhwr_one_only_stub : public mips_one_only_stub
1708 virtual const char *get_name ();
1709 virtual void output_body ();
1712 const char *
1713 mips16_rdhwr_one_only_stub::get_name ()
1715 return "__mips16_rdhwr";
1718 void
1719 mips16_rdhwr_one_only_stub::output_body ()
1721 fprintf (asm_out_file,
1722 "\t.set\tpush\n"
1723 "\t.set\tmips32r2\n"
1724 "\t.set\tnoreorder\n"
1725 "\trdhwr\t$3,$29\n"
1726 "\t.set\tpop\n"
1727 "\tj\t$31\n");
1730 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1731 class mips16_get_fcsr_one_only_stub : public mips_one_only_stub
1733 virtual const char *get_name ();
1734 virtual void output_body ();
1737 const char *
1738 mips16_get_fcsr_one_only_stub::get_name ()
1740 return "__mips16_get_fcsr";
1743 void
1744 mips16_get_fcsr_one_only_stub::output_body ()
1746 fprintf (asm_out_file,
1747 "\tcfc1\t%s,$31\n"
1748 "\tj\t$31\n", reg_names[GET_FCSR_REGNUM]);
1751 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1752 class mips16_set_fcsr_one_only_stub : public mips_one_only_stub
1754 virtual const char *get_name ();
1755 virtual void output_body ();
1758 const char *
1759 mips16_set_fcsr_one_only_stub::get_name ()
1761 return "__mips16_set_fcsr";
1764 void
1765 mips16_set_fcsr_one_only_stub::output_body ()
1767 fprintf (asm_out_file,
1768 "\tctc1\t%s,$31\n"
1769 "\tj\t$31\n", reg_names[SET_FCSR_REGNUM]);
1772 /* Return true if symbols of type TYPE require a GOT access. */
1774 static bool
1775 mips_got_symbol_type_p (enum mips_symbol_type type)
1777 switch (type)
1779 case SYMBOL_GOT_PAGE_OFST:
1780 case SYMBOL_GOT_DISP:
1781 return true;
1783 default:
1784 return false;
1788 /* Return true if X is a thread-local symbol. */
1790 static bool
1791 mips_tls_symbol_p (rtx x)
1793 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1796 /* Return true if SYMBOL_REF X is associated with a global symbol
1797 (in the STB_GLOBAL sense). */
1799 static bool
1800 mips_global_symbol_p (const_rtx x)
1802 const_tree decl = SYMBOL_REF_DECL (x);
1804 if (!decl)
1805 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1807 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1808 or weak symbols. Relocations in the object file will be against
1809 the target symbol, so it's that symbol's binding that matters here. */
1810 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1813 /* Return true if function X is a libgcc MIPS16 stub function. */
1815 static bool
1816 mips16_stub_function_p (const_rtx x)
1818 return (GET_CODE (x) == SYMBOL_REF
1819 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1822 /* Return true if function X is a locally-defined and locally-binding
1823 MIPS16 function. */
1825 static bool
1826 mips16_local_function_p (const_rtx x)
1828 return (GET_CODE (x) == SYMBOL_REF
1829 && SYMBOL_REF_LOCAL_P (x)
1830 && !SYMBOL_REF_EXTERNAL_P (x)
1831 && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
1834 /* Return true if SYMBOL_REF X binds locally. */
1836 static bool
1837 mips_symbol_binds_local_p (const_rtx x)
1839 return (SYMBOL_REF_DECL (x)
1840 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1841 : SYMBOL_REF_LOCAL_P (x));
1844 /* Return true if OP is a constant vector with the number of units in MODE,
1845 and each unit has the same bit set. */
1847 bool
1848 mips_const_vector_bitimm_set_p (rtx op, machine_mode mode)
1850 if (GET_CODE (op) == CONST_VECTOR && op != CONST0_RTX (mode))
1852 unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (op, 0));
1853 int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
1855 if (vlog2 != -1)
1857 gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
1858 gcc_assert (vlog2 >= 0 && vlog2 <= GET_MODE_UNIT_BITSIZE (mode) - 1);
1859 return mips_const_vector_same_val_p (op, mode);
1863 return false;
1866 /* Return true if OP is a constant vector with the number of units in MODE,
1867 and each unit has the same bit clear. */
1869 bool
1870 mips_const_vector_bitimm_clr_p (rtx op, machine_mode mode)
1872 if (GET_CODE (op) == CONST_VECTOR && op != CONSTM1_RTX (mode))
1874 unsigned HOST_WIDE_INT val = ~UINTVAL (CONST_VECTOR_ELT (op, 0));
1875 int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
1877 if (vlog2 != -1)
1879 gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
1880 gcc_assert (vlog2 >= 0 && vlog2 <= GET_MODE_UNIT_BITSIZE (mode) - 1);
1881 return mips_const_vector_same_val_p (op, mode);
1885 return false;
1888 /* Return true if OP is a constant vector with the number of units in MODE,
1889 and each unit has the same value. */
1891 bool
1892 mips_const_vector_same_val_p (rtx op, machine_mode mode)
1894 int i, nunits = GET_MODE_NUNITS (mode);
1895 rtx first;
1897 if (GET_CODE (op) != CONST_VECTOR || GET_MODE (op) != mode)
1898 return false;
1900 first = CONST_VECTOR_ELT (op, 0);
1901 for (i = 1; i < nunits; i++)
1902 if (!rtx_equal_p (first, CONST_VECTOR_ELT (op, i)))
1903 return false;
1905 return true;
1908 /* Return true if OP is a constant vector with the number of units in MODE,
1909 and each unit has the same value as well as replicated bytes in the value.
1912 bool
1913 mips_const_vector_same_bytes_p (rtx op, machine_mode mode)
1915 int i, bytes;
1916 HOST_WIDE_INT val, first_byte;
1917 rtx first;
1919 if (!mips_const_vector_same_val_p (op, mode))
1920 return false;
1922 first = CONST_VECTOR_ELT (op, 0);
1923 bytes = GET_MODE_UNIT_SIZE (mode);
1924 val = INTVAL (first);
1925 first_byte = val & 0xff;
1926 for (i = 1; i < bytes; i++)
1928 val >>= 8;
1929 if ((val & 0xff) != first_byte)
1930 return false;
1933 return true;
1936 /* Return true if OP is a constant vector with the number of units in MODE,
1937 and each unit has the same integer value in the range [LOW, HIGH]. */
1939 bool
1940 mips_const_vector_same_int_p (rtx op, machine_mode mode, HOST_WIDE_INT low,
1941 HOST_WIDE_INT high)
1943 HOST_WIDE_INT value;
1944 rtx elem0;
1946 if (!mips_const_vector_same_val_p (op, mode))
1947 return false;
1949 elem0 = CONST_VECTOR_ELT (op, 0);
1950 if (!CONST_INT_P (elem0))
1951 return false;
1953 value = INTVAL (elem0);
1954 return (value >= low && value <= high);
1957 /* Return true if OP is a constant vector with repeated 4-element sets
1958 in mode MODE. */
1960 bool
1961 mips_const_vector_shuffle_set_p (rtx op, machine_mode mode)
1963 int nunits = GET_MODE_NUNITS (mode);
1964 int nsets = nunits / 4;
1965 int set = 0;
1966 int i, j;
1968 /* Check if we have the same 4-element sets. */
1969 for (j = 0; j < nsets; j++, set = 4 * j)
1970 for (i = 0; i < 4; i++)
1971 if ((INTVAL (XVECEXP (op, 0, i))
1972 != (INTVAL (XVECEXP (op, 0, set + i)) - set))
1973 || !IN_RANGE (INTVAL (XVECEXP (op, 0, set + i)), 0, set + 3))
1974 return false;
1975 return true;
1978 /* Return true if rtx constants of mode MODE should be put into a small
1979 data section. */
1981 static bool
1982 mips_rtx_constant_in_small_data_p (machine_mode mode)
1984 return (!TARGET_EMBEDDED_DATA
1985 && TARGET_LOCAL_SDATA
1986 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1989 /* Return true if X should not be moved directly into register $25.
1990 We need this because many versions of GAS will treat "la $25,foo" as
1991 part of a call sequence and so allow a global "foo" to be lazily bound. */
1993 bool
1994 mips_dangerous_for_la25_p (rtx x)
1996 return (!TARGET_EXPLICIT_RELOCS
1997 && TARGET_USE_GOT
1998 && GET_CODE (x) == SYMBOL_REF
1999 && mips_global_symbol_p (x));
2002 /* Return true if calls to X might need $25 to be valid on entry. */
2004 bool
2005 mips_use_pic_fn_addr_reg_p (const_rtx x)
2007 if (!TARGET_USE_PIC_FN_ADDR_REG)
2008 return false;
2010 /* MIPS16 stub functions are guaranteed not to use $25. */
2011 if (mips16_stub_function_p (x))
2012 return false;
2014 if (GET_CODE (x) == SYMBOL_REF)
2016 /* If PLTs and copy relocations are available, the static linker
2017 will make sure that $25 is valid on entry to the target function. */
2018 if (TARGET_ABICALLS_PIC0)
2019 return false;
2021 /* Locally-defined functions use absolute accesses to set up
2022 the global pointer. */
2023 if (TARGET_ABSOLUTE_ABICALLS
2024 && mips_symbol_binds_local_p (x)
2025 && !SYMBOL_REF_EXTERNAL_P (x))
2026 return false;
2029 return true;
2032 /* Return the method that should be used to access SYMBOL_REF or
2033 LABEL_REF X in context CONTEXT. */
2035 static enum mips_symbol_type
2036 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
2038 if (TARGET_RTP_PIC)
2039 return SYMBOL_GOT_DISP;
2041 if (GET_CODE (x) == LABEL_REF)
2043 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
2044 code and if we know that the label is in the current function's
2045 text section. LABEL_REFs are used for jump tables as well as
2046 text labels, so we must check whether jump tables live in the
2047 text section. */
2048 if (TARGET_MIPS16_SHORT_JUMP_TABLES
2049 && !LABEL_REF_NONLOCAL_P (x))
2050 return SYMBOL_PC_RELATIVE;
2052 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
2053 return SYMBOL_GOT_PAGE_OFST;
2055 return SYMBOL_ABSOLUTE;
2058 gcc_assert (GET_CODE (x) == SYMBOL_REF);
2060 if (SYMBOL_REF_TLS_MODEL (x))
2061 return SYMBOL_TLS;
2063 if (CONSTANT_POOL_ADDRESS_P (x))
2065 if (TARGET_MIPS16_TEXT_LOADS)
2066 return SYMBOL_PC_RELATIVE;
2068 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
2069 return SYMBOL_PC_RELATIVE;
2071 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
2072 return SYMBOL_GP_RELATIVE;
2075 /* Do not use small-data accesses for weak symbols; they may end up
2076 being zero. */
2077 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
2078 return SYMBOL_GP_RELATIVE;
2080 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
2081 is in effect. */
2082 if (TARGET_ABICALLS_PIC2
2083 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
2085 /* There are three cases to consider:
2087 - o32 PIC (either with or without explicit relocs)
2088 - n32/n64 PIC without explicit relocs
2089 - n32/n64 PIC with explicit relocs
2091 In the first case, both local and global accesses will use an
2092 R_MIPS_GOT16 relocation. We must correctly predict which of
2093 the two semantics (local or global) the assembler and linker
2094 will apply. The choice depends on the symbol's binding rather
2095 than its visibility.
2097 In the second case, the assembler will not use R_MIPS_GOT16
2098 relocations, but it chooses between local and global accesses
2099 in the same way as for o32 PIC.
2101 In the third case we have more freedom since both forms of
2102 access will work for any kind of symbol. However, there seems
2103 little point in doing things differently. */
2104 if (mips_global_symbol_p (x))
2105 return SYMBOL_GOT_DISP;
2107 return SYMBOL_GOT_PAGE_OFST;
2110 return SYMBOL_ABSOLUTE;
2113 /* Classify the base of symbolic expression X, given that X appears in
2114 context CONTEXT. */
2116 static enum mips_symbol_type
2117 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
2119 rtx offset;
2121 split_const (x, &x, &offset);
2122 if (UNSPEC_ADDRESS_P (x))
2123 return UNSPEC_ADDRESS_TYPE (x);
2125 return mips_classify_symbol (x, context);
2128 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
2129 is the alignment in bytes of SYMBOL_REF X. */
2131 static bool
2132 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
2134 HOST_WIDE_INT align;
2136 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
2137 return IN_RANGE (offset, 0, align - 1);
2140 /* Return true if X is a symbolic constant that can be used in context
2141 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
2143 bool
2144 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
2145 enum mips_symbol_type *symbol_type)
2147 rtx offset;
2149 split_const (x, &x, &offset);
2150 if (UNSPEC_ADDRESS_P (x))
2152 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
2153 x = UNSPEC_ADDRESS (x);
2155 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
2157 *symbol_type = mips_classify_symbol (x, context);
2158 if (*symbol_type == SYMBOL_TLS)
2159 return false;
2161 else
2162 return false;
2164 if (offset == const0_rtx)
2165 return true;
2167 /* Check whether a nonzero offset is valid for the underlying
2168 relocations. */
2169 switch (*symbol_type)
2171 case SYMBOL_ABSOLUTE:
2172 case SYMBOL_64_HIGH:
2173 case SYMBOL_64_MID:
2174 case SYMBOL_64_LOW:
2175 /* If the target has 64-bit pointers and the object file only
2176 supports 32-bit symbols, the values of those symbols will be
2177 sign-extended. In this case we can't allow an arbitrary offset
2178 in case the 32-bit value X + OFFSET has a different sign from X. */
2179 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
2180 return offset_within_block_p (x, INTVAL (offset));
2182 /* In other cases the relocations can handle any offset. */
2183 return true;
2185 case SYMBOL_PC_RELATIVE:
2186 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2187 In this case, we no longer have access to the underlying constant,
2188 but the original symbol-based access was known to be valid. */
2189 if (GET_CODE (x) == LABEL_REF)
2190 return true;
2192 /* Fall through. */
2194 case SYMBOL_GP_RELATIVE:
2195 /* Make sure that the offset refers to something within the
2196 same object block. This should guarantee that the final
2197 PC- or GP-relative offset is within the 16-bit limit. */
2198 return offset_within_block_p (x, INTVAL (offset));
2200 case SYMBOL_GOT_PAGE_OFST:
2201 case SYMBOL_GOTOFF_PAGE:
2202 /* If the symbol is global, the GOT entry will contain the symbol's
2203 address, and we will apply a 16-bit offset after loading it.
2204 If the symbol is local, the linker should provide enough local
2205 GOT entries for a 16-bit offset, but larger offsets may lead
2206 to GOT overflow. */
2207 return SMALL_INT (offset);
2209 case SYMBOL_TPREL:
2210 case SYMBOL_DTPREL:
2211 /* There is no carry between the HI and LO REL relocations, so the
2212 offset is only valid if we know it won't lead to such a carry. */
2213 return mips_offset_within_alignment_p (x, INTVAL (offset));
2215 case SYMBOL_GOT_DISP:
2216 case SYMBOL_GOTOFF_DISP:
2217 case SYMBOL_GOTOFF_CALL:
2218 case SYMBOL_GOTOFF_LOADGP:
2219 case SYMBOL_TLSGD:
2220 case SYMBOL_TLSLDM:
2221 case SYMBOL_GOTTPREL:
2222 case SYMBOL_TLS:
2223 case SYMBOL_HALF:
2224 return false;
2226 gcc_unreachable ();
2229 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2230 single instruction. We rely on the fact that, in the worst case,
2231 all instructions involved in a MIPS16 address calculation are usually
2232 extended ones. */
2234 static int
2235 mips_symbol_insns_1 (enum mips_symbol_type type, machine_mode mode)
2237 if (mips_use_pcrel_pool_p[(int) type])
2239 if (mode == MAX_MACHINE_MODE)
2240 /* LEAs will be converted into constant-pool references by
2241 mips_reorg. */
2242 type = SYMBOL_PC_RELATIVE;
2243 else
2244 /* The constant must be loaded and then dereferenced. */
2245 return 0;
2248 switch (type)
2250 case SYMBOL_ABSOLUTE:
2251 /* When using 64-bit symbols, we need 5 preparatory instructions,
2252 such as:
2254 lui $at,%highest(symbol)
2255 daddiu $at,$at,%higher(symbol)
2256 dsll $at,$at,16
2257 daddiu $at,$at,%hi(symbol)
2258 dsll $at,$at,16
2260 The final address is then $at + %lo(symbol). With 32-bit
2261 symbols we just need a preparatory LUI for normal mode and
2262 a preparatory LI and SLL for MIPS16. */
2263 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
2265 case SYMBOL_GP_RELATIVE:
2266 /* Treat GP-relative accesses as taking a single instruction on
2267 MIPS16 too; the copy of $gp can often be shared. */
2268 return 1;
2270 case SYMBOL_PC_RELATIVE:
2271 /* PC-relative constants can be only be used with ADDIUPC,
2272 DADDIUPC, LWPC and LDPC. */
2273 if (mode == MAX_MACHINE_MODE
2274 || GET_MODE_SIZE (mode) == 4
2275 || GET_MODE_SIZE (mode) == 8)
2276 return 1;
2278 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2279 return 0;
2281 case SYMBOL_GOT_DISP:
2282 /* The constant will have to be loaded from the GOT before it
2283 is used in an address. */
2284 if (mode != MAX_MACHINE_MODE)
2285 return 0;
2287 /* Fall through. */
2289 case SYMBOL_GOT_PAGE_OFST:
2290 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2291 local/global classification is accurate. The worst cases are:
2293 (1) For local symbols when generating o32 or o64 code. The assembler
2294 will use:
2296 lw $at,%got(symbol)
2299 ...and the final address will be $at + %lo(symbol).
2301 (2) For global symbols when -mxgot. The assembler will use:
2303 lui $at,%got_hi(symbol)
2304 (d)addu $at,$at,$gp
2306 ...and the final address will be $at + %got_lo(symbol). */
2307 return 3;
2309 case SYMBOL_GOTOFF_PAGE:
2310 case SYMBOL_GOTOFF_DISP:
2311 case SYMBOL_GOTOFF_CALL:
2312 case SYMBOL_GOTOFF_LOADGP:
2313 case SYMBOL_64_HIGH:
2314 case SYMBOL_64_MID:
2315 case SYMBOL_64_LOW:
2316 case SYMBOL_TLSGD:
2317 case SYMBOL_TLSLDM:
2318 case SYMBOL_DTPREL:
2319 case SYMBOL_GOTTPREL:
2320 case SYMBOL_TPREL:
2321 case SYMBOL_HALF:
2322 /* A 16-bit constant formed by a single relocation, or a 32-bit
2323 constant formed from a high 16-bit relocation and a low 16-bit
2324 relocation. Use mips_split_p to determine which. 32-bit
2325 constants need an "lui; addiu" sequence for normal mode and
2326 an "li; sll; addiu" sequence for MIPS16 mode. */
2327 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
2329 case SYMBOL_TLS:
2330 /* We don't treat a bare TLS symbol as a constant. */
2331 return 0;
2333 gcc_unreachable ();
2336 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2337 to load symbols of type TYPE into a register. Return 0 if the given
2338 type of symbol cannot be used as an immediate operand.
2340 Otherwise, return the number of instructions needed to load or store
2341 values of mode MODE to or from addresses of type TYPE. Return 0 if
2342 the given type of symbol is not valid in addresses.
2344 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2346 static int
2347 mips_symbol_insns (enum mips_symbol_type type, machine_mode mode)
2349 /* MSA LD.* and ST.* cannot support loading symbols via an immediate
2350 operand. */
2351 if (MSA_SUPPORTED_MODE_P (mode))
2352 return 0;
2354 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
2357 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2359 static bool
2360 mips_cannot_force_const_mem (machine_mode mode, rtx x)
2362 enum mips_symbol_type type;
2363 rtx base, offset;
2365 /* There is no assembler syntax for expressing an address-sized
2366 high part. */
2367 if (GET_CODE (x) == HIGH)
2368 return true;
2370 /* As an optimization, reject constants that mips_legitimize_move
2371 can expand inline.
2373 Suppose we have a multi-instruction sequence that loads constant C
2374 into register R. If R does not get allocated a hard register, and
2375 R is used in an operand that allows both registers and memory
2376 references, reload will consider forcing C into memory and using
2377 one of the instruction's memory alternatives. Returning false
2378 here will force it to use an input reload instead. */
2379 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
2380 return true;
2382 split_const (x, &base, &offset);
2383 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
2385 /* See whether we explicitly want these symbols in the pool. */
2386 if (mips_use_pcrel_pool_p[(int) type])
2387 return false;
2389 /* The same optimization as for CONST_INT. */
2390 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2391 return true;
2393 /* If MIPS16 constant pools live in the text section, they should
2394 not refer to anything that might need run-time relocation. */
2395 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2396 return true;
2399 /* TLS symbols must be computed by mips_legitimize_move. */
2400 if (tls_referenced_p (x))
2401 return true;
2403 return false;
2406 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2407 constants when we're using a per-function constant pool. */
2409 static bool
2410 mips_use_blocks_for_constant_p (machine_mode mode ATTRIBUTE_UNUSED,
2411 const_rtx x ATTRIBUTE_UNUSED)
2413 return !TARGET_MIPS16_PCREL_LOADS;
2416 /* Return true if register REGNO is a valid base register for mode MODE.
2417 STRICT_P is true if REG_OK_STRICT is in effect. */
2420 mips_regno_mode_ok_for_base_p (int regno, machine_mode mode,
2421 bool strict_p)
2423 if (!HARD_REGISTER_NUM_P (regno))
2425 if (!strict_p)
2426 return true;
2427 regno = reg_renumber[regno];
2430 /* These fake registers will be eliminated to either the stack or
2431 hard frame pointer, both of which are usually valid base registers.
2432 Reload deals with the cases where the eliminated form isn't valid. */
2433 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2434 return true;
2436 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2437 values, nothing smaller. */
2438 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2439 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2441 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2444 /* Return true if X is a valid base register for mode MODE.
2445 STRICT_P is true if REG_OK_STRICT is in effect. */
2447 static bool
2448 mips_valid_base_register_p (rtx x, machine_mode mode, bool strict_p)
2450 if (!strict_p && GET_CODE (x) == SUBREG)
2451 x = SUBREG_REG (x);
2453 return (REG_P (x)
2454 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2457 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2458 can address a value of mode MODE. */
2460 static bool
2461 mips_valid_offset_p (rtx x, machine_mode mode)
2463 /* Check that X is a signed 16-bit number. */
2464 if (!const_arith_operand (x, Pmode))
2465 return false;
2467 /* We may need to split multiword moves, so make sure that every word
2468 is accessible. */
2469 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2470 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2471 return false;
2473 /* MSA LD.* and ST.* supports 10-bit signed offsets. */
2474 if (MSA_SUPPORTED_MODE_P (mode)
2475 && !mips_signed_immediate_p (INTVAL (x), 10,
2476 mips_ldst_scaled_shift (mode)))
2477 return false;
2479 return true;
2482 /* Return true if a LO_SUM can address a value of mode MODE when the
2483 LO_SUM symbol has type SYMBOL_TYPE. */
2485 static bool
2486 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, machine_mode mode)
2488 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2489 of mode MODE. */
2490 if (mips_symbol_insns (symbol_type, mode) == 0)
2491 return false;
2493 /* Check that there is a known low-part relocation. */
2494 if (mips_lo_relocs[symbol_type] == NULL)
2495 return false;
2497 /* We may need to split multiword moves, so make sure that each word
2498 can be accessed without inducing a carry. This is mainly needed
2499 for o64, which has historically only guaranteed 64-bit alignment
2500 for 128-bit types. */
2501 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2502 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2503 return false;
2505 /* MSA LD.* and ST.* cannot support loading symbols via %lo($base). */
2506 if (MSA_SUPPORTED_MODE_P (mode))
2507 return false;
2509 return true;
2512 /* Return true if X is a valid address for machine mode MODE. If it is,
2513 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2514 effect. */
2516 static bool
2517 mips_classify_address (struct mips_address_info *info, rtx x,
2518 machine_mode mode, bool strict_p)
2520 switch (GET_CODE (x))
2522 case REG:
2523 case SUBREG:
2524 info->type = ADDRESS_REG;
2525 info->reg = x;
2526 info->offset = const0_rtx;
2527 return mips_valid_base_register_p (info->reg, mode, strict_p);
2529 case PLUS:
2530 info->type = ADDRESS_REG;
2531 info->reg = XEXP (x, 0);
2532 info->offset = XEXP (x, 1);
2533 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2534 && mips_valid_offset_p (info->offset, mode));
2536 case LO_SUM:
2537 info->type = ADDRESS_LO_SUM;
2538 info->reg = XEXP (x, 0);
2539 info->offset = XEXP (x, 1);
2540 /* We have to trust the creator of the LO_SUM to do something vaguely
2541 sane. Target-independent code that creates a LO_SUM should also
2542 create and verify the matching HIGH. Target-independent code that
2543 adds an offset to a LO_SUM must prove that the offset will not
2544 induce a carry. Failure to do either of these things would be
2545 a bug, and we are not required to check for it here. The MIPS
2546 backend itself should only create LO_SUMs for valid symbolic
2547 constants, with the high part being either a HIGH or a copy
2548 of _gp. */
2549 info->symbol_type
2550 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2551 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2552 && mips_valid_lo_sum_p (info->symbol_type, mode));
2554 case CONST_INT:
2555 /* Small-integer addresses don't occur very often, but they
2556 are legitimate if $0 is a valid base register. */
2557 info->type = ADDRESS_CONST_INT;
2558 return !TARGET_MIPS16 && SMALL_INT (x);
2560 case CONST:
2561 case LABEL_REF:
2562 case SYMBOL_REF:
2563 info->type = ADDRESS_SYMBOLIC;
2564 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2565 &info->symbol_type)
2566 && mips_symbol_insns (info->symbol_type, mode) > 0
2567 && !mips_split_p[info->symbol_type]);
2569 default:
2570 return false;
2574 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2576 static bool
2577 mips_legitimate_address_p (machine_mode mode, rtx x, bool strict_p)
2579 struct mips_address_info addr;
2581 return mips_classify_address (&addr, x, mode, strict_p);
2584 /* Return true if X is a legitimate $sp-based address for mode MODE. */
2586 bool
2587 mips_stack_address_p (rtx x, machine_mode mode)
2589 struct mips_address_info addr;
2591 return (mips_classify_address (&addr, x, mode, false)
2592 && addr.type == ADDRESS_REG
2593 && addr.reg == stack_pointer_rtx);
2596 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2597 address instruction. Note that such addresses are not considered
2598 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2599 is so restricted. */
2601 static bool
2602 mips_lwxs_address_p (rtx addr)
2604 if (ISA_HAS_LWXS
2605 && GET_CODE (addr) == PLUS
2606 && REG_P (XEXP (addr, 1)))
2608 rtx offset = XEXP (addr, 0);
2609 if (GET_CODE (offset) == MULT
2610 && REG_P (XEXP (offset, 0))
2611 && CONST_INT_P (XEXP (offset, 1))
2612 && INTVAL (XEXP (offset, 1)) == 4)
2613 return true;
2615 return false;
2618 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2619 indexed address instruction. Note that such addresses are
2620 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2621 sense, because their use is so restricted. */
2623 static bool
2624 mips_lx_address_p (rtx addr, machine_mode mode)
2626 if (GET_CODE (addr) != PLUS
2627 || !REG_P (XEXP (addr, 0))
2628 || !REG_P (XEXP (addr, 1)))
2629 return false;
2630 if (ISA_HAS_LBX && mode == QImode)
2631 return true;
2632 if (ISA_HAS_LHX && mode == HImode)
2633 return true;
2634 if (ISA_HAS_LWX && mode == SImode)
2635 return true;
2636 if (ISA_HAS_LDX && mode == DImode)
2637 return true;
2638 if (MSA_SUPPORTED_MODE_P (mode))
2639 return true;
2640 return false;
2643 /* Return true if a value at OFFSET bytes from base register BASE can be
2644 accessed using an unextended MIPS16 instruction. MODE is the mode of
2645 the value.
2647 Usually the offset in an unextended instruction is a 5-bit field.
2648 The offset is unsigned and shifted left once for LH and SH, twice
2649 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2650 an 8-bit immediate field that's shifted left twice. */
2652 static bool
2653 mips16_unextended_reference_p (machine_mode mode, rtx base,
2654 unsigned HOST_WIDE_INT offset)
2656 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2658 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2659 return offset < 256U * GET_MODE_SIZE (mode);
2660 return offset < 32U * GET_MODE_SIZE (mode);
2662 return false;
2665 /* Return the number of instructions needed to load or store a value
2666 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2667 length of one instruction. Return 0 if X isn't valid for MODE.
2668 Assume that multiword moves may need to be split into word moves
2669 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2670 enough. */
2673 mips_address_insns (rtx x, machine_mode mode, bool might_split_p)
2675 struct mips_address_info addr;
2676 int factor;
2677 bool msa_p = (!might_split_p && MSA_SUPPORTED_MODE_P (mode));
2679 /* BLKmode is used for single unaligned loads and stores and should
2680 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2681 meaningless, so we have to single it out as a special case one way
2682 or the other.) */
2683 if (mode != BLKmode && might_split_p)
2684 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2685 else
2686 factor = 1;
2688 if (mips_classify_address (&addr, x, mode, false))
2689 switch (addr.type)
2691 case ADDRESS_REG:
2692 if (msa_p)
2694 /* MSA LD.* and ST.* supports 10-bit signed offsets. */
2695 if (mips_signed_immediate_p (INTVAL (addr.offset), 10,
2696 mips_ldst_scaled_shift (mode)))
2697 return 1;
2698 else
2699 return 0;
2701 if (TARGET_MIPS16
2702 && !mips16_unextended_reference_p (mode, addr.reg,
2703 UINTVAL (addr.offset)))
2704 return factor * 2;
2705 return factor;
2707 case ADDRESS_LO_SUM:
2708 return msa_p ? 0 : TARGET_MIPS16 ? factor * 2 : factor;
2710 case ADDRESS_CONST_INT:
2711 return msa_p ? 0 : factor;
2713 case ADDRESS_SYMBOLIC:
2714 return msa_p ? 0 : factor * mips_symbol_insns (addr.symbol_type, mode);
2716 return 0;
2719 /* Return true if X fits within an unsigned field of BITS bits that is
2720 shifted left SHIFT bits before being used. */
2722 bool
2723 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2725 return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits));
2728 /* Return true if X fits within a signed field of BITS bits that is
2729 shifted left SHIFT bits before being used. */
2731 bool
2732 mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2734 x += 1 << (bits + shift - 1);
2735 return mips_unsigned_immediate_p (x, bits, shift);
2738 /* Return the scale shift that applied to MSA LD/ST address offset. */
2741 mips_ldst_scaled_shift (machine_mode mode)
2743 int shift = exact_log2 (GET_MODE_UNIT_SIZE (mode));
2745 if (shift < 0 || shift > 8)
2746 gcc_unreachable ();
2748 return shift;
2751 /* Return true if X is legitimate for accessing values of mode MODE,
2752 if it is based on a MIPS16 register, and if the offset satisfies
2753 OFFSET_PREDICATE. */
2755 bool
2756 m16_based_address_p (rtx x, machine_mode mode,
2757 insn_operand_predicate_fn offset_predicate)
2759 struct mips_address_info addr;
2761 return (mips_classify_address (&addr, x, mode, false)
2762 && addr.type == ADDRESS_REG
2763 && M16_REG_P (REGNO (addr.reg))
2764 && offset_predicate (addr.offset, mode));
2767 /* Return true if X is a legitimate address that conforms to the requirements
2768 for a microMIPS LWSP or SWSP insn. */
2770 bool
2771 lwsp_swsp_address_p (rtx x, machine_mode mode)
2773 struct mips_address_info addr;
2775 return (mips_classify_address (&addr, x, mode, false)
2776 && addr.type == ADDRESS_REG
2777 && REGNO (addr.reg) == STACK_POINTER_REGNUM
2778 && uw5_operand (addr.offset, mode));
2781 /* Return true if X is a legitimate address with a 12-bit offset.
2782 MODE is the mode of the value being accessed. */
2784 bool
2785 umips_12bit_offset_address_p (rtx x, machine_mode mode)
2787 struct mips_address_info addr;
2789 return (mips_classify_address (&addr, x, mode, false)
2790 && addr.type == ADDRESS_REG
2791 && CONST_INT_P (addr.offset)
2792 && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
2795 /* Return true if X is a legitimate address with a 9-bit offset.
2796 MODE is the mode of the value being accessed. */
2798 bool
2799 mips_9bit_offset_address_p (rtx x, machine_mode mode)
2801 struct mips_address_info addr;
2803 return (mips_classify_address (&addr, x, mode, false)
2804 && addr.type == ADDRESS_REG
2805 && CONST_INT_P (addr.offset)
2806 && MIPS_9BIT_OFFSET_P (INTVAL (addr.offset)));
2809 /* Return the number of instructions needed to load constant X,
2810 assuming that BASE_INSN_LENGTH is the length of one instruction.
2811 Return 0 if X isn't a valid constant. */
2814 mips_const_insns (rtx x)
2816 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2817 enum mips_symbol_type symbol_type;
2818 rtx offset;
2820 switch (GET_CODE (x))
2822 case HIGH:
2823 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2824 &symbol_type)
2825 || !mips_split_p[symbol_type])
2826 return 0;
2828 /* This is simply an LUI for normal mode. It is an extended
2829 LI followed by an extended SLL for MIPS16. */
2830 return TARGET_MIPS16 ? 4 : 1;
2832 case CONST_INT:
2833 if (TARGET_MIPS16)
2834 /* Unsigned 8-bit constants can be loaded using an unextended
2835 LI instruction. Unsigned 16-bit constants can be loaded
2836 using an extended LI. Negative constants must be loaded
2837 using LI and then negated. */
2838 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2839 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2840 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2841 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2842 : 0);
2844 return mips_build_integer (codes, INTVAL (x));
2846 case CONST_VECTOR:
2847 if (ISA_HAS_MSA
2848 && mips_const_vector_same_int_p (x, GET_MODE (x), -512, 511))
2849 return 1;
2850 /* Fall through. */
2851 case CONST_DOUBLE:
2852 /* Allow zeros for normal mode, where we can use $0. */
2853 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2855 case CONST:
2856 if (CONST_GP_P (x))
2857 return 1;
2859 /* See if we can refer to X directly. */
2860 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2861 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2863 /* Otherwise try splitting the constant into a base and offset.
2864 If the offset is a 16-bit value, we can load the base address
2865 into a register and then use (D)ADDIU to add in the offset.
2866 If the offset is larger, we can load the base and offset
2867 into separate registers and add them together with (D)ADDU.
2868 However, the latter is only possible before reload; during
2869 and after reload, we must have the option of forcing the
2870 constant into the pool instead. */
2871 split_const (x, &x, &offset);
2872 if (offset != 0)
2874 int n = mips_const_insns (x);
2875 if (n != 0)
2877 if (SMALL_INT (offset))
2878 return n + 1;
2879 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2880 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2883 return 0;
2885 case SYMBOL_REF:
2886 case LABEL_REF:
2887 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2888 MAX_MACHINE_MODE);
2890 default:
2891 return 0;
2895 /* X is a doubleword constant that can be handled by splitting it into
2896 two words and loading each word separately. Return the number of
2897 instructions required to do this, assuming that BASE_INSN_LENGTH
2898 is the length of one instruction. */
2901 mips_split_const_insns (rtx x)
2903 unsigned int low, high;
2905 low = mips_const_insns (mips_subword (x, false));
2906 high = mips_const_insns (mips_subword (x, true));
2907 gcc_assert (low > 0 && high > 0);
2908 return low + high;
2911 /* Return one word of 128-bit value OP, taking into account the fixed
2912 endianness of certain registers. BYTE selects from the byte address. */
2915 mips_subword_at_byte (rtx op, unsigned int byte)
2917 machine_mode mode;
2919 mode = GET_MODE (op);
2920 if (mode == VOIDmode)
2921 mode = TImode;
2923 gcc_assert (!FP_REG_RTX_P (op));
2925 if (MEM_P (op))
2926 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2928 return simplify_gen_subreg (word_mode, op, mode, byte);
2931 /* Return the number of instructions needed to implement INSN,
2932 given that it loads from or stores to MEM. Assume that
2933 BASE_INSN_LENGTH is the length of one instruction. */
2936 mips_load_store_insns (rtx mem, rtx_insn *insn)
2938 machine_mode mode;
2939 bool might_split_p;
2940 rtx set;
2942 gcc_assert (MEM_P (mem));
2943 mode = GET_MODE (mem);
2945 /* Try to prove that INSN does not need to be split. */
2946 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2947 if (might_split_p)
2949 set = single_set (insn);
2950 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2951 might_split_p = false;
2954 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2957 /* Return the number of instructions needed for an integer division,
2958 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2961 mips_idiv_insns (machine_mode mode)
2963 int count;
2965 count = 1;
2966 if (TARGET_CHECK_ZERO_DIV)
2968 if (GENERATE_DIVIDE_TRAPS && !MSA_SUPPORTED_MODE_P (mode))
2969 count++;
2970 else
2971 count += 2;
2974 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2975 count++;
2976 return count;
2980 /* Emit a move from SRC to DEST. Assume that the move expanders can
2981 handle all moves if !can_create_pseudo_p (). The distinction is
2982 important because, unlike emit_move_insn, the move expanders know
2983 how to force Pmode objects into the constant pool even when the
2984 constant pool address is not itself legitimate. */
2986 rtx_insn *
2987 mips_emit_move (rtx dest, rtx src)
2989 return (can_create_pseudo_p ()
2990 ? emit_move_insn (dest, src)
2991 : emit_move_insn_1 (dest, src));
2994 /* Emit a move from SRC to DEST, splitting compound moves into individual
2995 instructions. SPLIT_TYPE is the type of split to perform. */
2997 static void
2998 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
3000 if (mips_split_move_p (dest, src, split_type))
3001 mips_split_move (dest, src, split_type);
3002 else
3003 mips_emit_move (dest, src);
3006 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
3008 static void
3009 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
3011 emit_insn (gen_rtx_SET (target, gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
3014 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
3015 Return that new register. */
3017 static rtx
3018 mips_force_unary (machine_mode mode, enum rtx_code code, rtx op0)
3020 rtx reg;
3022 reg = gen_reg_rtx (mode);
3023 mips_emit_unary (code, reg, op0);
3024 return reg;
3027 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3029 void
3030 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
3032 emit_insn (gen_rtx_SET (target, gen_rtx_fmt_ee (code, GET_MODE (target),
3033 op0, op1)));
3036 /* Compute (CODE OP0 OP1) and store the result in a new register
3037 of mode MODE. Return that new register. */
3039 static rtx
3040 mips_force_binary (machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
3042 rtx reg;
3044 reg = gen_reg_rtx (mode);
3045 mips_emit_binary (code, reg, op0, op1);
3046 return reg;
3049 /* Copy VALUE to a register and return that register. If new pseudos
3050 are allowed, copy it into a new register, otherwise use DEST. */
3052 static rtx
3053 mips_force_temporary (rtx dest, rtx value)
3055 if (can_create_pseudo_p ())
3056 return force_reg (Pmode, value);
3057 else
3059 mips_emit_move (dest, value);
3060 return dest;
3064 /* Emit a call sequence with call pattern PATTERN and return the call
3065 instruction itself (which is not necessarily the last instruction
3066 emitted). ORIG_ADDR is the original, unlegitimized address,
3067 ADDR is the legitimized form, and LAZY_P is true if the call
3068 address is lazily-bound. */
3070 static rtx_insn *
3071 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
3073 rtx_insn *insn;
3074 rtx reg;
3076 insn = emit_call_insn (pattern);
3078 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
3080 /* MIPS16 JALRs only take MIPS16 registers. If the target
3081 function requires $25 to be valid on entry, we must copy it
3082 there separately. The move instruction can be put in the
3083 call's delay slot. */
3084 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
3085 emit_insn_before (gen_move_insn (reg, addr), insn);
3086 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
3089 if (lazy_p)
3090 /* Lazy-binding stubs require $gp to be valid on entry. */
3091 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3093 if (TARGET_USE_GOT)
3095 /* See the comment above load_call<mode> for details. */
3096 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
3097 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
3098 emit_insn (gen_update_got_version ());
3101 if (TARGET_MIPS16
3102 && TARGET_EXPLICIT_RELOCS
3103 && TARGET_CALL_CLOBBERED_GP)
3105 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG);
3106 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), post_call_tmp_reg);
3109 return insn;
3112 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
3113 then add CONST_INT OFFSET to the result. */
3115 static rtx
3116 mips_unspec_address_offset (rtx base, rtx offset,
3117 enum mips_symbol_type symbol_type)
3119 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
3120 UNSPEC_ADDRESS_FIRST + symbol_type);
3121 if (offset != const0_rtx)
3122 base = gen_rtx_PLUS (Pmode, base, offset);
3123 return gen_rtx_CONST (Pmode, base);
3126 /* Return an UNSPEC address with underlying address ADDRESS and symbol
3127 type SYMBOL_TYPE. */
3130 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
3132 rtx base, offset;
3134 split_const (address, &base, &offset);
3135 return mips_unspec_address_offset (base, offset, symbol_type);
3138 /* If OP is an UNSPEC address, return the address to which it refers,
3139 otherwise return OP itself. */
3142 mips_strip_unspec_address (rtx op)
3144 rtx base, offset;
3146 split_const (op, &base, &offset);
3147 if (UNSPEC_ADDRESS_P (base))
3148 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
3149 return op;
3152 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
3153 high part to BASE and return the result. Just return BASE otherwise.
3154 TEMP is as for mips_force_temporary.
3156 The returned expression can be used as the first operand to a LO_SUM. */
3158 static rtx
3159 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
3160 enum mips_symbol_type symbol_type)
3162 if (mips_split_p[symbol_type])
3164 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
3165 addr = mips_force_temporary (temp, addr);
3166 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
3168 return base;
3171 /* Return an instruction that copies $gp into register REG. We want
3172 GCC to treat the register's value as constant, so that its value
3173 can be rematerialized on demand. */
3175 static rtx
3176 gen_load_const_gp (rtx reg)
3178 return PMODE_INSN (gen_load_const_gp, (reg));
3181 /* Return a pseudo register that contains the value of $gp throughout
3182 the current function. Such registers are needed by MIPS16 functions,
3183 for which $gp itself is not a valid base register or addition operand. */
3185 static rtx
3186 mips16_gp_pseudo_reg (void)
3188 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
3190 rtx_insn *scan;
3192 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
3194 push_topmost_sequence ();
3196 scan = get_insns ();
3197 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
3198 scan = NEXT_INSN (scan);
3200 rtx set = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
3201 rtx_insn *insn = emit_insn_after (set, scan);
3202 INSN_LOCATION (insn) = 0;
3204 pop_topmost_sequence ();
3207 return cfun->machine->mips16_gp_pseudo_rtx;
3210 /* Return a base register that holds pic_offset_table_rtx.
3211 TEMP, if nonnull, is a scratch Pmode base register. */
3214 mips_pic_base_register (rtx temp)
3216 if (!TARGET_MIPS16)
3217 return pic_offset_table_rtx;
3219 if (currently_expanding_to_rtl)
3220 return mips16_gp_pseudo_reg ();
3222 if (can_create_pseudo_p ())
3223 temp = gen_reg_rtx (Pmode);
3225 if (TARGET_USE_GOT)
3226 /* The first post-reload split exposes all references to $gp
3227 (both uses and definitions). All references must remain
3228 explicit after that point.
3230 It is safe to introduce uses of $gp at any time, so for
3231 simplicity, we do that before the split too. */
3232 mips_emit_move (temp, pic_offset_table_rtx);
3233 else
3234 emit_insn (gen_load_const_gp (temp));
3235 return temp;
3238 /* Return the RHS of a load_call<mode> insn. */
3240 static rtx
3241 mips_unspec_call (rtx reg, rtx symbol)
3243 rtvec vec;
3245 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
3246 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
3249 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
3250 reference. Return NULL_RTX otherwise. */
3252 static rtx
3253 mips_strip_unspec_call (rtx src)
3255 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
3256 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
3257 return NULL_RTX;
3260 /* Create and return a GOT reference of type TYPE for address ADDR.
3261 TEMP, if nonnull, is a scratch Pmode base register. */
3264 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
3266 rtx base, high, lo_sum_symbol;
3268 base = mips_pic_base_register (temp);
3270 /* If we used the temporary register to load $gp, we can't use
3271 it for the high part as well. */
3272 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
3273 temp = NULL;
3275 high = mips_unspec_offset_high (temp, base, addr, type);
3276 lo_sum_symbol = mips_unspec_address (addr, type);
3278 if (type == SYMBOL_GOTOFF_CALL)
3279 return mips_unspec_call (high, lo_sum_symbol);
3280 else
3281 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
3284 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3285 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3286 constant in that context and can be split into high and low parts.
3287 If so, and if LOW_OUT is nonnull, emit the high part and store the
3288 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3290 TEMP is as for mips_force_temporary and is used to load the high
3291 part into a register.
3293 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3294 a legitimize SET_SRC for an .md pattern, otherwise the low part
3295 is guaranteed to be a legitimate address for mode MODE. */
3297 bool
3298 mips_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
3300 enum mips_symbol_context context;
3301 enum mips_symbol_type symbol_type;
3302 rtx high;
3304 context = (mode == MAX_MACHINE_MODE
3305 ? SYMBOL_CONTEXT_LEA
3306 : SYMBOL_CONTEXT_MEM);
3307 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
3309 addr = XEXP (addr, 0);
3310 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3311 && mips_symbol_insns (symbol_type, mode) > 0
3312 && mips_split_hi_p[symbol_type])
3314 if (low_out)
3315 switch (symbol_type)
3317 case SYMBOL_GOT_PAGE_OFST:
3318 /* The high part of a page/ofst pair is loaded from the GOT. */
3319 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
3320 break;
3322 default:
3323 gcc_unreachable ();
3325 return true;
3328 else
3330 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3331 && mips_symbol_insns (symbol_type, mode) > 0
3332 && mips_split_p[symbol_type])
3334 if (low_out)
3335 switch (symbol_type)
3337 case SYMBOL_GOT_DISP:
3338 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3339 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
3340 break;
3342 case SYMBOL_GP_RELATIVE:
3343 high = mips_pic_base_register (temp);
3344 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3345 break;
3347 default:
3348 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
3349 high = mips_force_temporary (temp, high);
3350 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3351 break;
3353 return true;
3356 return false;
3359 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3360 mips_force_temporary; it is only needed when OFFSET is not a
3361 SMALL_OPERAND. */
3363 static rtx
3364 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
3366 if (!SMALL_OPERAND (offset))
3368 rtx high;
3370 if (TARGET_MIPS16)
3372 /* Load the full offset into a register so that we can use
3373 an unextended instruction for the address itself. */
3374 high = GEN_INT (offset);
3375 offset = 0;
3377 else
3379 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3380 The addition inside the macro CONST_HIGH_PART may cause an
3381 overflow, so we need to force a sign-extension check. */
3382 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
3383 offset = CONST_LOW_PART (offset);
3385 high = mips_force_temporary (temp, high);
3386 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
3388 return plus_constant (Pmode, reg, offset);
3391 /* The __tls_get_attr symbol. */
3392 static GTY(()) rtx mips_tls_symbol;
3394 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3395 the TLS symbol we are referencing and TYPE is the symbol type to use
3396 (either global dynamic or local dynamic). V0 is an RTX for the
3397 return value location. */
3399 static rtx_insn *
3400 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
3402 rtx loc, a0;
3403 rtx_insn *insn;
3405 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
3407 if (!mips_tls_symbol)
3408 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
3410 loc = mips_unspec_address (sym, type);
3412 start_sequence ();
3414 emit_insn (gen_rtx_SET (a0, gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx,
3415 loc)));
3416 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
3417 const0_rtx, NULL_RTX, false);
3418 RTL_CONST_CALL_P (insn) = 1;
3419 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
3420 insn = get_insns ();
3422 end_sequence ();
3424 return insn;
3427 /* Return a pseudo register that contains the current thread pointer. */
3430 mips_expand_thread_pointer (rtx tp)
3432 rtx fn;
3434 if (TARGET_MIPS16)
3436 if (!mips16_rdhwr_stub)
3437 mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ();
3438 fn = mips16_stub_call_address (mips16_rdhwr_stub);
3439 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
3441 else
3442 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
3443 return tp;
3446 static rtx
3447 mips_get_tp (void)
3449 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
3452 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3453 its address. The return value will be both a valid address and a valid
3454 SET_SRC (either a REG or a LO_SUM). */
3456 static rtx
3457 mips_legitimize_tls_address (rtx loc)
3459 rtx dest, v0, tp, tmp1, tmp2, eqv, offset;
3460 enum tls_model model;
3462 model = SYMBOL_REF_TLS_MODEL (loc);
3463 /* Only TARGET_ABICALLS code can have more than one module; other
3464 code must be static and should not use a GOT. All TLS models
3465 reduce to local exec in this situation. */
3466 if (!TARGET_ABICALLS)
3467 model = TLS_MODEL_LOCAL_EXEC;
3469 switch (model)
3471 case TLS_MODEL_GLOBAL_DYNAMIC:
3473 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3474 rtx_insn *insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
3475 dest = gen_reg_rtx (Pmode);
3476 emit_libcall_block (insn, dest, v0, loc);
3477 break;
3480 case TLS_MODEL_LOCAL_DYNAMIC:
3482 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3483 rtx_insn *insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
3484 tmp1 = gen_reg_rtx (Pmode);
3486 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3487 share the LDM result with other LD model accesses. */
3488 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3489 UNSPEC_TLS_LDM);
3490 emit_libcall_block (insn, tmp1, v0, eqv);
3492 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
3493 if (mips_split_p[SYMBOL_DTPREL])
3495 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
3496 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3498 else
3499 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3500 0, 0, OPTAB_DIRECT);
3501 break;
3504 case TLS_MODEL_INITIAL_EXEC:
3505 tp = mips_get_tp ();
3506 tmp1 = gen_reg_rtx (Pmode);
3507 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
3508 if (Pmode == DImode)
3509 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
3510 else
3511 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
3512 dest = gen_reg_rtx (Pmode);
3513 emit_insn (gen_add3_insn (dest, tmp1, tp));
3514 break;
3516 case TLS_MODEL_LOCAL_EXEC:
3517 tmp1 = mips_get_tp ();
3518 offset = mips_unspec_address (loc, SYMBOL_TPREL);
3519 if (mips_split_p[SYMBOL_TPREL])
3521 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
3522 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3524 else
3525 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3526 0, 0, OPTAB_DIRECT);
3527 break;
3529 default:
3530 gcc_unreachable ();
3532 return dest;
3535 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3536 using a stub. */
3538 void
3539 mips16_expand_get_fcsr (rtx target)
3541 if (!mips16_get_fcsr_stub)
3542 mips16_get_fcsr_stub = new mips16_get_fcsr_one_only_stub ();
3543 rtx fn = mips16_stub_call_address (mips16_get_fcsr_stub);
3544 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16, (fn)));
3545 emit_move_insn (target, gen_rtx_REG (SImode, GET_FCSR_REGNUM));
3548 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3550 void
3551 mips16_expand_set_fcsr (rtx newval)
3553 if (!mips16_set_fcsr_stub)
3554 mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ();
3555 rtx fn = mips16_stub_call_address (mips16_set_fcsr_stub);
3556 emit_move_insn (gen_rtx_REG (SImode, SET_FCSR_REGNUM), newval);
3557 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16, (fn)));
3560 /* If X is not a valid address for mode MODE, force it into a register. */
3562 static rtx
3563 mips_force_address (rtx x, machine_mode mode)
3565 if (!mips_legitimate_address_p (mode, x, false))
3566 x = force_reg (Pmode, x);
3567 return x;
3570 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3571 be legitimized in a way that the generic machinery might not expect,
3572 return a new address, otherwise return NULL. MODE is the mode of
3573 the memory being accessed. */
3575 static rtx
3576 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3577 machine_mode mode)
3579 rtx base, addr;
3580 HOST_WIDE_INT offset;
3582 if (mips_tls_symbol_p (x))
3583 return mips_legitimize_tls_address (x);
3585 /* See if the address can split into a high part and a LO_SUM. */
3586 if (mips_split_symbol (NULL, x, mode, &addr))
3587 return mips_force_address (addr, mode);
3589 /* Handle BASE + OFFSET using mips_add_offset. */
3590 mips_split_plus (x, &base, &offset);
3591 if (offset != 0)
3593 if (!mips_valid_base_register_p (base, mode, false))
3594 base = copy_to_mode_reg (Pmode, base);
3595 addr = mips_add_offset (NULL, base, offset);
3596 return mips_force_address (addr, mode);
3599 return x;
3602 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3604 void
3605 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3607 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3608 machine_mode mode;
3609 unsigned int i, num_ops;
3610 rtx x;
3612 mode = GET_MODE (dest);
3613 num_ops = mips_build_integer (codes, value);
3615 /* Apply each binary operation to X. Invariant: X is a legitimate
3616 source operand for a SET pattern. */
3617 x = GEN_INT (codes[0].value);
3618 for (i = 1; i < num_ops; i++)
3620 if (!can_create_pseudo_p ())
3622 emit_insn (gen_rtx_SET (temp, x));
3623 x = temp;
3625 else
3626 x = force_reg (mode, x);
3627 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3630 emit_insn (gen_rtx_SET (dest, x));
3633 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3634 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3635 move_operand. */
3637 static void
3638 mips_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
3640 rtx base, offset;
3642 /* Split moves of big integers into smaller pieces. */
3643 if (splittable_const_int_operand (src, mode))
3645 mips_move_integer (dest, dest, INTVAL (src));
3646 return;
3649 /* Split moves of symbolic constants into high/low pairs. */
3650 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3652 emit_insn (gen_rtx_SET (dest, src));
3653 return;
3656 /* Generate the appropriate access sequences for TLS symbols. */
3657 if (mips_tls_symbol_p (src))
3659 mips_emit_move (dest, mips_legitimize_tls_address (src));
3660 return;
3663 /* If we have (const (plus symbol offset)), and that expression cannot
3664 be forced into memory, load the symbol first and add in the offset.
3665 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3666 forced into memory, as it usually produces better code. */
3667 split_const (src, &base, &offset);
3668 if (offset != const0_rtx
3669 && (targetm.cannot_force_const_mem (mode, src)
3670 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3672 base = mips_force_temporary (dest, base);
3673 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3674 return;
3677 src = force_const_mem (mode, src);
3679 /* When using explicit relocs, constant pool references are sometimes
3680 not legitimate addresses. */
3681 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3682 mips_emit_move (dest, src);
3685 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3686 sequence that is valid. */
3688 bool
3689 mips_legitimize_move (machine_mode mode, rtx dest, rtx src)
3691 /* Both src and dest are non-registers; one special case is supported where
3692 the source is (const_int 0) and the store can source the zero register.
3693 MIPS16 and MSA are never able to source the zero register directly in
3694 memory operations. */
3695 if (!register_operand (dest, mode)
3696 && !register_operand (src, mode)
3697 && (TARGET_MIPS16 || !const_0_operand (src, mode)
3698 || MSA_SUPPORTED_MODE_P (mode)))
3700 mips_emit_move (dest, force_reg (mode, src));
3701 return true;
3704 /* We need to deal with constants that would be legitimate
3705 immediate_operands but aren't legitimate move_operands. */
3706 if (CONSTANT_P (src) && !move_operand (src, mode))
3708 mips_legitimize_const_move (mode, dest, src);
3709 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3710 return true;
3712 return false;
3715 /* Return true if value X in context CONTEXT is a small-data address
3716 that can be rewritten as a LO_SUM. */
3718 static bool
3719 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3721 enum mips_symbol_type symbol_type;
3723 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3724 && !mips_split_p[SYMBOL_GP_RELATIVE]
3725 && mips_symbolic_constant_p (x, context, &symbol_type)
3726 && symbol_type == SYMBOL_GP_RELATIVE);
3729 /* Return true if OP refers to small data symbols directly, not through
3730 a LO_SUM. CONTEXT is the context in which X appears. */
3732 static int
3733 mips_small_data_pattern_1 (rtx x, enum mips_symbol_context context)
3735 subrtx_var_iterator::array_type array;
3736 FOR_EACH_SUBRTX_VAR (iter, array, x, ALL)
3738 rtx x = *iter;
3740 /* Ignore things like "g" constraints in asms. We make no particular
3741 guarantee about which symbolic constants are acceptable as asm operands
3742 versus which must be forced into a GPR. */
3743 if (GET_CODE (x) == LO_SUM || GET_CODE (x) == ASM_OPERANDS)
3744 iter.skip_subrtxes ();
3745 else if (MEM_P (x))
3747 if (mips_small_data_pattern_1 (XEXP (x, 0), SYMBOL_CONTEXT_MEM))
3748 return true;
3749 iter.skip_subrtxes ();
3751 else if (mips_rewrite_small_data_p (x, context))
3752 return true;
3754 return false;
3757 /* Return true if OP refers to small data symbols directly, not through
3758 a LO_SUM. */
3760 bool
3761 mips_small_data_pattern_p (rtx op)
3763 return mips_small_data_pattern_1 (op, SYMBOL_CONTEXT_LEA);
3766 /* Rewrite *LOC so that it refers to small data using explicit
3767 relocations. CONTEXT is the context in which *LOC appears. */
3769 static void
3770 mips_rewrite_small_data_1 (rtx *loc, enum mips_symbol_context context)
3772 subrtx_ptr_iterator::array_type array;
3773 FOR_EACH_SUBRTX_PTR (iter, array, loc, ALL)
3775 rtx *loc = *iter;
3776 if (MEM_P (*loc))
3778 mips_rewrite_small_data_1 (&XEXP (*loc, 0), SYMBOL_CONTEXT_MEM);
3779 iter.skip_subrtxes ();
3781 else if (mips_rewrite_small_data_p (*loc, context))
3783 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3784 iter.skip_subrtxes ();
3786 else if (GET_CODE (*loc) == LO_SUM)
3787 iter.skip_subrtxes ();
3791 /* Rewrite instruction pattern PATTERN so that it refers to small data
3792 using explicit relocations. */
3795 mips_rewrite_small_data (rtx pattern)
3797 pattern = copy_insn (pattern);
3798 mips_rewrite_small_data_1 (&pattern, SYMBOL_CONTEXT_LEA);
3799 return pattern;
3802 /* The cost of loading values from the constant pool. It should be
3803 larger than the cost of any constant we want to synthesize inline. */
3804 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3806 /* Return the cost of X when used as an operand to the MIPS16 instruction
3807 that implements CODE. Return -1 if there is no such instruction, or if
3808 X is not a valid immediate operand for it. */
3810 static int
3811 mips16_constant_cost (int code, HOST_WIDE_INT x)
3813 switch (code)
3815 case ASHIFT:
3816 case ASHIFTRT:
3817 case LSHIFTRT:
3818 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3819 other shifts are extended. The shift patterns truncate the shift
3820 count to the right size, so there are no out-of-range values. */
3821 if (IN_RANGE (x, 1, 8))
3822 return 0;
3823 return COSTS_N_INSNS (1);
3825 case PLUS:
3826 if (IN_RANGE (x, -128, 127))
3827 return 0;
3828 if (SMALL_OPERAND (x))
3829 return COSTS_N_INSNS (1);
3830 return -1;
3832 case LEU:
3833 /* Like LE, but reject the always-true case. */
3834 if (x == -1)
3835 return -1;
3836 /* FALLTHRU */
3837 case LE:
3838 /* We add 1 to the immediate and use SLT. */
3839 x += 1;
3840 /* FALLTHRU */
3841 case XOR:
3842 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3843 case LT:
3844 case LTU:
3845 if (IN_RANGE (x, 0, 255))
3846 return 0;
3847 if (SMALL_OPERAND_UNSIGNED (x))
3848 return COSTS_N_INSNS (1);
3849 return -1;
3851 case EQ:
3852 case NE:
3853 /* Equality comparisons with 0 are cheap. */
3854 if (x == 0)
3855 return 0;
3856 return -1;
3858 default:
3859 return -1;
3863 /* Return true if there is a non-MIPS16 instruction that implements CODE
3864 and if that instruction accepts X as an immediate operand. */
3866 static int
3867 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3869 switch (code)
3871 case ASHIFT:
3872 case ASHIFTRT:
3873 case LSHIFTRT:
3874 /* All shift counts are truncated to a valid constant. */
3875 return true;
3877 case ROTATE:
3878 case ROTATERT:
3879 /* Likewise rotates, if the target supports rotates at all. */
3880 return ISA_HAS_ROR;
3882 case AND:
3883 case IOR:
3884 case XOR:
3885 /* These instructions take 16-bit unsigned immediates. */
3886 return SMALL_OPERAND_UNSIGNED (x);
3888 case PLUS:
3889 case LT:
3890 case LTU:
3891 /* These instructions take 16-bit signed immediates. */
3892 return SMALL_OPERAND (x);
3894 case EQ:
3895 case NE:
3896 case GT:
3897 case GTU:
3898 /* The "immediate" forms of these instructions are really
3899 implemented as comparisons with register 0. */
3900 return x == 0;
3902 case GE:
3903 case GEU:
3904 /* Likewise, meaning that the only valid immediate operand is 1. */
3905 return x == 1;
3907 case LE:
3908 /* We add 1 to the immediate and use SLT. */
3909 return SMALL_OPERAND (x + 1);
3911 case LEU:
3912 /* Likewise SLTU, but reject the always-true case. */
3913 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3915 case SIGN_EXTRACT:
3916 case ZERO_EXTRACT:
3917 /* The bit position and size are immediate operands. */
3918 return ISA_HAS_EXT_INS;
3920 default:
3921 /* By default assume that $0 can be used for 0. */
3922 return x == 0;
3926 /* Return the cost of binary operation X, given that the instruction
3927 sequence for a word-sized or smaller operation has cost SINGLE_COST
3928 and that the sequence of a double-word operation has cost DOUBLE_COST.
3929 If SPEED is true, optimize for speed otherwise optimize for size. */
3931 static int
3932 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3934 int cost;
3936 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3937 cost = double_cost;
3938 else
3939 cost = single_cost;
3940 return (cost
3941 + set_src_cost (XEXP (x, 0), GET_MODE (x), speed)
3942 + rtx_cost (XEXP (x, 1), GET_MODE (x), GET_CODE (x), 1, speed));
3945 /* Return the cost of floating-point multiplications of mode MODE. */
3947 static int
3948 mips_fp_mult_cost (machine_mode mode)
3950 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3953 /* Return the cost of floating-point divisions of mode MODE. */
3955 static int
3956 mips_fp_div_cost (machine_mode mode)
3958 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3961 /* Return the cost of sign-extending OP to mode MODE, not including the
3962 cost of OP itself. */
3964 static int
3965 mips_sign_extend_cost (machine_mode mode, rtx op)
3967 if (MEM_P (op))
3968 /* Extended loads are as cheap as unextended ones. */
3969 return 0;
3971 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3972 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3973 return 0;
3975 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3976 /* We can use SEB or SEH. */
3977 return COSTS_N_INSNS (1);
3979 /* We need to use a shift left and a shift right. */
3980 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3983 /* Return the cost of zero-extending OP to mode MODE, not including the
3984 cost of OP itself. */
3986 static int
3987 mips_zero_extend_cost (machine_mode mode, rtx op)
3989 if (MEM_P (op))
3990 /* Extended loads are as cheap as unextended ones. */
3991 return 0;
3993 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3994 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3995 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3997 if (GENERATE_MIPS16E)
3998 /* We can use ZEB or ZEH. */
3999 return COSTS_N_INSNS (1);
4001 if (TARGET_MIPS16)
4002 /* We need to load 0xff or 0xffff into a register and use AND. */
4003 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
4005 /* We can use ANDI. */
4006 return COSTS_N_INSNS (1);
4009 /* Return the cost of moving between two registers of mode MODE,
4010 assuming that the move will be in pieces of at most UNITS bytes. */
4012 static int
4013 mips_set_reg_reg_piece_cost (machine_mode mode, unsigned int units)
4015 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
4018 /* Return the cost of moving between two registers of mode MODE. */
4020 static int
4021 mips_set_reg_reg_cost (machine_mode mode)
4023 switch (GET_MODE_CLASS (mode))
4025 case MODE_CC:
4026 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
4028 case MODE_FLOAT:
4029 case MODE_COMPLEX_FLOAT:
4030 case MODE_VECTOR_FLOAT:
4031 if (TARGET_HARD_FLOAT)
4032 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
4033 /* Fall through */
4035 default:
4036 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
4040 /* Implement TARGET_RTX_COSTS. */
4042 static bool
4043 mips_rtx_costs (rtx x, machine_mode mode, int outer_code,
4044 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
4046 int code = GET_CODE (x);
4047 bool float_mode_p = FLOAT_MODE_P (mode);
4048 int cost;
4049 rtx addr;
4051 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
4052 appear in the instruction stream, and the cost of a comparison is
4053 really the cost of the branch or scc condition. At the time of
4054 writing, GCC only uses an explicit outer COMPARE code when optabs
4055 is testing whether a constant is expensive enough to force into a
4056 register. We want optabs to pass such constants through the MIPS
4057 expanders instead, so make all constants very cheap here. */
4058 if (outer_code == COMPARE)
4060 gcc_assert (CONSTANT_P (x));
4061 *total = 0;
4062 return true;
4065 switch (code)
4067 case CONST_INT:
4068 /* Treat *clear_upper32-style ANDs as having zero cost in the
4069 second operand. The cost is entirely in the first operand.
4071 ??? This is needed because we would otherwise try to CSE
4072 the constant operand. Although that's the right thing for
4073 instructions that continue to be a register operation throughout
4074 compilation, it is disastrous for instructions that could
4075 later be converted into a memory operation. */
4076 if (TARGET_64BIT
4077 && outer_code == AND
4078 && UINTVAL (x) == 0xffffffff)
4080 *total = 0;
4081 return true;
4084 if (TARGET_MIPS16)
4086 cost = mips16_constant_cost (outer_code, INTVAL (x));
4087 if (cost >= 0)
4089 *total = cost;
4090 return true;
4093 else
4095 /* When not optimizing for size, we care more about the cost
4096 of hot code, and hot code is often in a loop. If a constant
4097 operand needs to be forced into a register, we will often be
4098 able to hoist the constant load out of the loop, so the load
4099 should not contribute to the cost. */
4100 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
4102 *total = 0;
4103 return true;
4106 /* Fall through. */
4108 case CONST:
4109 case SYMBOL_REF:
4110 case LABEL_REF:
4111 case CONST_DOUBLE:
4112 if (force_to_mem_operand (x, VOIDmode))
4114 *total = COSTS_N_INSNS (1);
4115 return true;
4117 cost = mips_const_insns (x);
4118 if (cost > 0)
4120 /* If the constant is likely to be stored in a GPR, SETs of
4121 single-insn constants are as cheap as register sets; we
4122 never want to CSE them.
4124 Don't reduce the cost of storing a floating-point zero in
4125 FPRs. If we have a zero in an FPR for other reasons, we
4126 can get better cfg-cleanup and delayed-branch results by
4127 using it consistently, rather than using $0 sometimes and
4128 an FPR at other times. Also, moves between floating-point
4129 registers are sometimes cheaper than (D)MTC1 $0. */
4130 if (cost == 1
4131 && outer_code == SET
4132 && !(float_mode_p && TARGET_HARD_FLOAT))
4133 cost = 0;
4134 /* When non-MIPS16 code loads a constant N>1 times, we rarely
4135 want to CSE the constant itself. It is usually better to
4136 have N copies of the last operation in the sequence and one
4137 shared copy of the other operations. (Note that this is
4138 not true for MIPS16 code, where the final operation in the
4139 sequence is often an extended instruction.)
4141 Also, if we have a CONST_INT, we don't know whether it is
4142 for a word or doubleword operation, so we cannot rely on
4143 the result of mips_build_integer. */
4144 else if (!TARGET_MIPS16
4145 && (outer_code == SET || GET_MODE (x) == VOIDmode))
4146 cost = 1;
4147 *total = COSTS_N_INSNS (cost);
4148 return true;
4150 /* The value will need to be fetched from the constant pool. */
4151 *total = CONSTANT_POOL_COST;
4152 return true;
4154 case MEM:
4155 /* If the address is legitimate, return the number of
4156 instructions it needs. */
4157 addr = XEXP (x, 0);
4158 cost = mips_address_insns (addr, mode, true);
4159 if (cost > 0)
4161 *total = COSTS_N_INSNS (cost + 1);
4162 return true;
4164 /* Check for a scaled indexed address. */
4165 if (mips_lwxs_address_p (addr)
4166 || mips_lx_address_p (addr, mode))
4168 *total = COSTS_N_INSNS (2);
4169 return true;
4171 /* Otherwise use the default handling. */
4172 return false;
4174 case FFS:
4175 *total = COSTS_N_INSNS (6);
4176 return false;
4178 case NOT:
4179 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
4180 return false;
4182 case AND:
4183 /* Check for a *clear_upper32 pattern and treat it like a zero
4184 extension. See the pattern's comment for details. */
4185 if (TARGET_64BIT
4186 && mode == DImode
4187 && CONST_INT_P (XEXP (x, 1))
4188 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
4190 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
4191 + set_src_cost (XEXP (x, 0), mode, speed));
4192 return true;
4194 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
4196 rtx op = XEXP (x, 0);
4197 if (GET_CODE (op) == ASHIFT
4198 && CONST_INT_P (XEXP (op, 1))
4199 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
4201 *total = COSTS_N_INSNS (1);
4202 *total += set_src_cost (XEXP (op, 0), mode, speed);
4203 return true;
4206 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
4207 a single instruction. */
4208 if (!TARGET_MIPS16
4209 && GET_CODE (XEXP (x, 0)) == NOT
4210 && GET_CODE (XEXP (x, 1)) == NOT)
4212 cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1;
4213 *total = (COSTS_N_INSNS (cost)
4214 + set_src_cost (XEXP (XEXP (x, 0), 0), mode, speed)
4215 + set_src_cost (XEXP (XEXP (x, 1), 0), mode, speed));
4216 return true;
4219 /* Fall through. */
4221 case IOR:
4222 case XOR:
4223 /* Double-word operations use two single-word operations. */
4224 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
4225 speed);
4226 return true;
4228 case ASHIFT:
4229 case ASHIFTRT:
4230 case LSHIFTRT:
4231 case ROTATE:
4232 case ROTATERT:
4233 if (CONSTANT_P (XEXP (x, 1)))
4234 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4235 speed);
4236 else
4237 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
4238 speed);
4239 return true;
4241 case ABS:
4242 if (float_mode_p)
4243 *total = mips_cost->fp_add;
4244 else
4245 *total = COSTS_N_INSNS (4);
4246 return false;
4248 case LO_SUM:
4249 /* Low-part immediates need an extended MIPS16 instruction. */
4250 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
4251 + set_src_cost (XEXP (x, 0), mode, speed));
4252 return true;
4254 case LT:
4255 case LTU:
4256 case LE:
4257 case LEU:
4258 case GT:
4259 case GTU:
4260 case GE:
4261 case GEU:
4262 case EQ:
4263 case NE:
4264 case UNORDERED:
4265 case LTGT:
4266 case UNGE:
4267 case UNGT:
4268 case UNLE:
4269 case UNLT:
4270 /* Branch comparisons have VOIDmode, so use the first operand's
4271 mode instead. */
4272 mode = GET_MODE (XEXP (x, 0));
4273 if (FLOAT_MODE_P (mode))
4275 *total = mips_cost->fp_add;
4276 return false;
4278 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4279 speed);
4280 return true;
4282 case MINUS:
4283 if (float_mode_p && ISA_HAS_UNFUSED_MADD4 && !HONOR_SIGNED_ZEROS (mode))
4285 /* See if we can use NMADD or NMSUB via the *nmadd4<mode>_fastmath
4286 or *nmsub4<mode>_fastmath patterns. These patterns check for
4287 HONOR_SIGNED_ZEROS so we check here too. */
4288 rtx op0 = XEXP (x, 0);
4289 rtx op1 = XEXP (x, 1);
4290 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
4292 *total = (mips_fp_mult_cost (mode)
4293 + set_src_cost (XEXP (XEXP (op0, 0), 0), mode, speed)
4294 + set_src_cost (XEXP (op0, 1), mode, speed)
4295 + set_src_cost (op1, mode, speed));
4296 return true;
4298 if (GET_CODE (op1) == MULT)
4300 *total = (mips_fp_mult_cost (mode)
4301 + set_src_cost (op0, mode, speed)
4302 + set_src_cost (XEXP (op1, 0), mode, speed)
4303 + set_src_cost (XEXP (op1, 1), mode, speed));
4304 return true;
4307 /* Fall through. */
4309 case PLUS:
4310 if (float_mode_p)
4312 /* If this is part of a MADD or MSUB, treat the PLUS as
4313 being free. */
4314 if (ISA_HAS_UNFUSED_MADD4 && GET_CODE (XEXP (x, 0)) == MULT)
4315 *total = 0;
4316 else
4317 *total = mips_cost->fp_add;
4318 return false;
4321 /* If it's an add + mult (which is equivalent to shift left) and
4322 it's immediate operand satisfies const_immlsa_operand predicate. */
4323 if (((ISA_HAS_LSA && mode == SImode)
4324 || (ISA_HAS_DLSA && mode == DImode))
4325 && GET_CODE (XEXP (x, 0)) == MULT)
4327 rtx op2 = XEXP (XEXP (x, 0), 1);
4328 if (const_immlsa_operand (op2, mode))
4330 *total = (COSTS_N_INSNS (1)
4331 + set_src_cost (XEXP (XEXP (x, 0), 0), mode, speed)
4332 + set_src_cost (XEXP (x, 1), mode, speed));
4333 return true;
4337 /* Double-word operations require three single-word operations and
4338 an SLTU. The MIPS16 version then needs to move the result of
4339 the SLTU from $24 to a MIPS16 register. */
4340 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
4341 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
4342 speed);
4343 return true;
4345 case NEG:
4346 if (float_mode_p && ISA_HAS_UNFUSED_MADD4)
4348 /* See if we can use NMADD or NMSUB via the *nmadd4<mode> or
4349 *nmsub4<mode> patterns. */
4350 rtx op = XEXP (x, 0);
4351 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
4352 && GET_CODE (XEXP (op, 0)) == MULT)
4354 *total = (mips_fp_mult_cost (mode)
4355 + set_src_cost (XEXP (XEXP (op, 0), 0), mode, speed)
4356 + set_src_cost (XEXP (XEXP (op, 0), 1), mode, speed)
4357 + set_src_cost (XEXP (op, 1), mode, speed));
4358 return true;
4362 if (float_mode_p)
4363 *total = mips_cost->fp_add;
4364 else
4365 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
4366 return false;
4368 case FMA:
4369 *total = mips_fp_mult_cost (mode);
4370 return false;
4372 case MULT:
4373 if (float_mode_p)
4374 *total = mips_fp_mult_cost (mode);
4375 else if (mode == DImode && !TARGET_64BIT)
4376 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4377 where the mulsidi3 always includes an MFHI and an MFLO. */
4378 *total = (speed
4379 ? mips_cost->int_mult_si * 3 + 6
4380 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
4381 else if (!speed)
4382 *total = COSTS_N_INSNS ((ISA_HAS_MUL3 || ISA_HAS_R6MUL) ? 1 : 2) + 1;
4383 else if (mode == DImode)
4384 *total = mips_cost->int_mult_di;
4385 else
4386 *total = mips_cost->int_mult_si;
4387 return false;
4389 case DIV:
4390 /* Check for a reciprocal. */
4391 if (float_mode_p
4392 && ISA_HAS_FP_RECIP_RSQRT (mode)
4393 && flag_unsafe_math_optimizations
4394 && XEXP (x, 0) == CONST1_RTX (mode))
4396 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
4397 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4398 division as being free. */
4399 *total = set_src_cost (XEXP (x, 1), mode, speed);
4400 else
4401 *total = (mips_fp_div_cost (mode)
4402 + set_src_cost (XEXP (x, 1), mode, speed));
4403 return true;
4405 /* Fall through. */
4407 case SQRT:
4408 case MOD:
4409 if (float_mode_p)
4411 *total = mips_fp_div_cost (mode);
4412 return false;
4414 /* Fall through. */
4416 case UDIV:
4417 case UMOD:
4418 if (!speed)
4420 /* It is our responsibility to make division by a power of 2
4421 as cheap as 2 register additions if we want the division
4422 expanders to be used for such operations; see the setting
4423 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4424 should always produce shorter code than using
4425 expand_sdiv2_pow2. */
4426 if (TARGET_MIPS16
4427 && CONST_INT_P (XEXP (x, 1))
4428 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
4430 *total = COSTS_N_INSNS (2);
4431 *total += set_src_cost (XEXP (x, 0), mode, speed);
4432 return true;
4434 *total = COSTS_N_INSNS (mips_idiv_insns (mode));
4436 else if (mode == DImode)
4437 *total = mips_cost->int_div_di;
4438 else
4439 *total = mips_cost->int_div_si;
4440 return false;
4442 case SIGN_EXTEND:
4443 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
4444 return false;
4446 case ZERO_EXTEND:
4447 if (outer_code == SET
4448 && ISA_HAS_BADDU
4449 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
4450 || GET_CODE (XEXP (x, 0)) == SUBREG)
4451 && GET_MODE (XEXP (x, 0)) == QImode
4452 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
4454 *total = set_src_cost (XEXP (XEXP (x, 0), 0), VOIDmode, speed);
4455 return true;
4457 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
4458 return false;
4459 case TRUNCATE:
4460 /* Costings for highpart multiplies. Matching patterns of the form:
4462 (lshiftrt:DI (mult:DI (sign_extend:DI (...)
4463 (sign_extend:DI (...))
4464 (const_int 32)
4466 if (ISA_HAS_R6MUL
4467 && (GET_CODE (XEXP (x, 0)) == ASHIFTRT
4468 || GET_CODE (XEXP (x, 0)) == LSHIFTRT)
4469 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4470 && ((INTVAL (XEXP (XEXP (x, 0), 1)) == 32
4471 && GET_MODE (XEXP (x, 0)) == DImode)
4472 || (ISA_HAS_R6DMUL
4473 && INTVAL (XEXP (XEXP (x, 0), 1)) == 64
4474 && GET_MODE (XEXP (x, 0)) == TImode))
4475 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4476 && ((GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND
4477 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SIGN_EXTEND)
4478 || (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4479 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))
4480 == ZERO_EXTEND))))
4482 if (!speed)
4483 *total = COSTS_N_INSNS (1) + 1;
4484 else if (mode == DImode)
4485 *total = mips_cost->int_mult_di;
4486 else
4487 *total = mips_cost->int_mult_si;
4489 /* Sign extension is free, zero extension costs for DImode when
4490 on a 64bit core / when DMUL is present. */
4491 for (int i = 0; i < 2; ++i)
4493 rtx op = XEXP (XEXP (XEXP (x, 0), 0), i);
4494 if (ISA_HAS_R6DMUL
4495 && GET_CODE (op) == ZERO_EXTEND
4496 && GET_MODE (op) == DImode)
4497 *total += rtx_cost (op, DImode, MULT, i, speed);
4498 else
4499 *total += rtx_cost (XEXP (op, 0), VOIDmode, GET_CODE (op),
4500 0, speed);
4503 return true;
4505 return false;
4507 case FLOAT:
4508 case UNSIGNED_FLOAT:
4509 case FIX:
4510 case FLOAT_EXTEND:
4511 case FLOAT_TRUNCATE:
4512 *total = mips_cost->fp_add;
4513 return false;
4515 case SET:
4516 if (register_operand (SET_DEST (x), VOIDmode)
4517 && reg_or_0_operand (SET_SRC (x), VOIDmode))
4519 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
4520 return true;
4522 return false;
4524 default:
4525 return false;
4529 /* Implement TARGET_ADDRESS_COST. */
4531 static int
4532 mips_address_cost (rtx addr, machine_mode mode,
4533 addr_space_t as ATTRIBUTE_UNUSED,
4534 bool speed ATTRIBUTE_UNUSED)
4536 return mips_address_insns (addr, mode, false);
4539 /* Implement TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P. */
4541 static bool
4542 mips_no_speculation_in_delay_slots_p ()
4544 return TARGET_CB_MAYBE;
4547 /* Information about a single instruction in a multi-instruction
4548 asm sequence. */
4549 struct mips_multi_member {
4550 /* True if this is a label, false if it is code. */
4551 bool is_label_p;
4553 /* The output_asm_insn format of the instruction. */
4554 const char *format;
4556 /* The operands to the instruction. */
4557 rtx operands[MAX_RECOG_OPERANDS];
4559 typedef struct mips_multi_member mips_multi_member;
4561 /* The instructions that make up the current multi-insn sequence. */
4562 static vec<mips_multi_member> mips_multi_members;
4564 /* How many instructions (as opposed to labels) are in the current
4565 multi-insn sequence. */
4566 static unsigned int mips_multi_num_insns;
4568 /* Start a new multi-insn sequence. */
4570 static void
4571 mips_multi_start (void)
4573 mips_multi_members.truncate (0);
4574 mips_multi_num_insns = 0;
4577 /* Add a new, uninitialized member to the current multi-insn sequence. */
4579 static struct mips_multi_member *
4580 mips_multi_add (void)
4582 mips_multi_member empty;
4583 return mips_multi_members.safe_push (empty);
4586 /* Add a normal insn with the given asm format to the current multi-insn
4587 sequence. The other arguments are a null-terminated list of operands. */
4589 static void
4590 mips_multi_add_insn (const char *format, ...)
4592 struct mips_multi_member *member;
4593 va_list ap;
4594 unsigned int i;
4595 rtx op;
4597 member = mips_multi_add ();
4598 member->is_label_p = false;
4599 member->format = format;
4600 va_start (ap, format);
4601 i = 0;
4602 while ((op = va_arg (ap, rtx)))
4603 member->operands[i++] = op;
4604 va_end (ap);
4605 mips_multi_num_insns++;
4608 /* Add the given label definition to the current multi-insn sequence.
4609 The definition should include the colon. */
4611 static void
4612 mips_multi_add_label (const char *label)
4614 struct mips_multi_member *member;
4616 member = mips_multi_add ();
4617 member->is_label_p = true;
4618 member->format = label;
4621 /* Return the index of the last member of the current multi-insn sequence. */
4623 static unsigned int
4624 mips_multi_last_index (void)
4626 return mips_multi_members.length () - 1;
4629 /* Add a copy of an existing instruction to the current multi-insn
4630 sequence. I is the index of the instruction that should be copied. */
4632 static void
4633 mips_multi_copy_insn (unsigned int i)
4635 struct mips_multi_member *member;
4637 member = mips_multi_add ();
4638 memcpy (member, &mips_multi_members[i], sizeof (*member));
4639 gcc_assert (!member->is_label_p);
4642 /* Change the operand of an existing instruction in the current
4643 multi-insn sequence. I is the index of the instruction,
4644 OP is the index of the operand, and X is the new value. */
4646 static void
4647 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4649 mips_multi_members[i].operands[op] = x;
4652 /* Write out the asm code for the current multi-insn sequence. */
4654 static void
4655 mips_multi_write (void)
4657 struct mips_multi_member *member;
4658 unsigned int i;
4660 FOR_EACH_VEC_ELT (mips_multi_members, i, member)
4661 if (member->is_label_p)
4662 fprintf (asm_out_file, "%s\n", member->format);
4663 else
4664 output_asm_insn (member->format, member->operands);
4667 /* Return one word of double-word value OP, taking into account the fixed
4668 endianness of certain registers. HIGH_P is true to select the high part,
4669 false to select the low part. */
4672 mips_subword (rtx op, bool high_p)
4674 unsigned int byte, offset;
4675 machine_mode mode;
4677 mode = GET_MODE (op);
4678 if (mode == VOIDmode)
4679 mode = TARGET_64BIT ? TImode : DImode;
4681 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4682 byte = UNITS_PER_WORD;
4683 else
4684 byte = 0;
4686 if (FP_REG_RTX_P (op))
4688 /* Paired FPRs are always ordered little-endian. */
4689 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4690 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4693 if (MEM_P (op))
4694 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4696 return simplify_gen_subreg (word_mode, op, mode, byte);
4699 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4700 SPLIT_TYPE is the condition under which moves should be split. */
4702 static bool
4703 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4705 return ((split_type != SPLIT_FOR_SPEED
4706 || mips_tuning_info.fast_mult_zero_zero_p)
4707 && src == const0_rtx
4708 && REG_P (dest)
4709 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4710 && (ISA_HAS_DSP_MULT
4711 ? ACC_REG_P (REGNO (dest))
4712 : MD_REG_P (REGNO (dest))));
4715 /* Return true if a move from SRC to DEST should be split into two.
4716 SPLIT_TYPE describes the split condition. */
4718 bool
4719 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4721 /* Check whether the move can be done using some variant of MULT $0,$0. */
4722 if (mips_mult_move_p (dest, src, split_type))
4723 return false;
4725 /* FPR-to-FPR moves can be done in a single instruction, if they're
4726 allowed at all. */
4727 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4728 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4729 return false;
4731 /* Check for floating-point loads and stores. */
4732 if (size == 8 && ISA_HAS_LDC1_SDC1)
4734 if (FP_REG_RTX_P (dest) && MEM_P (src))
4735 return false;
4736 if (FP_REG_RTX_P (src) && MEM_P (dest))
4737 return false;
4740 /* Check if MSA moves need splitting. */
4741 if (MSA_SUPPORTED_MODE_P (GET_MODE (dest)))
4742 return mips_split_128bit_move_p (dest, src);
4744 /* Otherwise split all multiword moves. */
4745 return size > UNITS_PER_WORD;
4748 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4749 SPLIT_TYPE describes the split condition. */
4751 void
4752 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4754 rtx low_dest;
4756 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4757 if (MSA_SUPPORTED_MODE_P (GET_MODE (dest)))
4758 mips_split_128bit_move (dest, src);
4759 else if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4761 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4762 emit_insn (gen_move_doubleword_fprdi (dest, src));
4763 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4764 emit_insn (gen_move_doubleword_fprdf (dest, src));
4765 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4766 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4767 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4768 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4769 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4770 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4771 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4772 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4773 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4774 emit_insn (gen_move_doubleword_fprtf (dest, src));
4775 else
4776 gcc_unreachable ();
4778 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4780 low_dest = mips_subword (dest, false);
4781 mips_emit_move (low_dest, mips_subword (src, false));
4782 if (TARGET_64BIT)
4783 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4784 else
4785 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4787 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4789 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4790 if (TARGET_64BIT)
4791 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4792 else
4793 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4795 else
4797 /* The operation can be split into two normal moves. Decide in
4798 which order to do them. */
4799 low_dest = mips_subword (dest, false);
4800 if (REG_P (low_dest)
4801 && reg_overlap_mentioned_p (low_dest, src))
4803 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4804 mips_emit_move (low_dest, mips_subword (src, false));
4806 else
4808 mips_emit_move (low_dest, mips_subword (src, false));
4809 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4814 /* Return the split type for instruction INSN. */
4816 static enum mips_split_type
4817 mips_insn_split_type (rtx insn)
4819 basic_block bb = BLOCK_FOR_INSN (insn);
4820 if (bb)
4822 if (optimize_bb_for_speed_p (bb))
4823 return SPLIT_FOR_SPEED;
4824 else
4825 return SPLIT_FOR_SIZE;
4827 /* Once CFG information has been removed, we should trust the optimization
4828 decisions made by previous passes and only split where necessary. */
4829 return SPLIT_IF_NECESSARY;
4832 /* Return true if a 128-bit move from SRC to DEST should be split. */
4834 bool
4835 mips_split_128bit_move_p (rtx dest, rtx src)
4837 /* MSA-to-MSA moves can be done in a single instruction. */
4838 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4839 return false;
4841 /* Check for MSA loads and stores. */
4842 if (FP_REG_RTX_P (dest) && MEM_P (src))
4843 return false;
4844 if (FP_REG_RTX_P (src) && MEM_P (dest))
4845 return false;
4847 /* Check for MSA set to an immediate const vector with valid replicated
4848 element. */
4849 if (FP_REG_RTX_P (dest)
4850 && mips_const_vector_same_int_p (src, GET_MODE (src), -512, 511))
4851 return false;
4853 /* Check for MSA load zero immediate. */
4854 if (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src)))
4855 return false;
4857 return true;
4860 /* Split a 128-bit move from SRC to DEST. */
4862 void
4863 mips_split_128bit_move (rtx dest, rtx src)
4865 int byte, index;
4866 rtx low_dest, low_src, d, s;
4868 if (FP_REG_RTX_P (dest))
4870 gcc_assert (!MEM_P (src));
4872 rtx new_dest = dest;
4873 if (!TARGET_64BIT)
4875 if (GET_MODE (dest) != V4SImode)
4876 new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0);
4878 else
4880 if (GET_MODE (dest) != V2DImode)
4881 new_dest = simplify_gen_subreg (V2DImode, dest, GET_MODE (dest), 0);
4884 for (byte = 0, index = 0; byte < GET_MODE_SIZE (TImode);
4885 byte += UNITS_PER_WORD, index++)
4887 s = mips_subword_at_byte (src, byte);
4888 if (!TARGET_64BIT)
4889 emit_insn (gen_msa_insert_w (new_dest, s, new_dest,
4890 GEN_INT (1 << index)));
4891 else
4892 emit_insn (gen_msa_insert_d (new_dest, s, new_dest,
4893 GEN_INT (1 << index)));
4896 else if (FP_REG_RTX_P (src))
4898 gcc_assert (!MEM_P (dest));
4900 rtx new_src = src;
4901 if (!TARGET_64BIT)
4903 if (GET_MODE (src) != V4SImode)
4904 new_src = simplify_gen_subreg (V4SImode, src, GET_MODE (src), 0);
4906 else
4908 if (GET_MODE (src) != V2DImode)
4909 new_src = simplify_gen_subreg (V2DImode, src, GET_MODE (src), 0);
4912 for (byte = 0, index = 0; byte < GET_MODE_SIZE (TImode);
4913 byte += UNITS_PER_WORD, index++)
4915 d = mips_subword_at_byte (dest, byte);
4916 if (!TARGET_64BIT)
4917 emit_insn (gen_msa_copy_s_w (d, new_src, GEN_INT (index)));
4918 else
4919 emit_insn (gen_msa_copy_s_d (d, new_src, GEN_INT (index)));
4922 else
4924 low_dest = mips_subword_at_byte (dest, 0);
4925 low_src = mips_subword_at_byte (src, 0);
4926 gcc_assert (REG_P (low_dest) && REG_P (low_src));
4927 /* Make sure the source register is not written before reading. */
4928 if (REGNO (low_dest) <= REGNO (low_src))
4930 for (byte = 0; byte < GET_MODE_SIZE (TImode);
4931 byte += UNITS_PER_WORD)
4933 d = mips_subword_at_byte (dest, byte);
4934 s = mips_subword_at_byte (src, byte);
4935 mips_emit_move (d, s);
4938 else
4940 for (byte = GET_MODE_SIZE (TImode) - UNITS_PER_WORD; byte >= 0;
4941 byte -= UNITS_PER_WORD)
4943 d = mips_subword_at_byte (dest, byte);
4944 s = mips_subword_at_byte (src, byte);
4945 mips_emit_move (d, s);
4951 /* Split a COPY_S.D with operands DEST, SRC and INDEX. GEN is a function
4952 used to generate subregs. */
4954 void
4955 mips_split_msa_copy_d (rtx dest, rtx src, rtx index,
4956 rtx (*gen_fn)(rtx, rtx, rtx))
4958 gcc_assert ((GET_MODE (src) == V2DImode && GET_MODE (dest) == DImode)
4959 || (GET_MODE (src) == V2DFmode && GET_MODE (dest) == DFmode));
4961 /* Note that low is always from the lower index, and high is always
4962 from the higher index. */
4963 rtx low = mips_subword (dest, false);
4964 rtx high = mips_subword (dest, true);
4965 rtx new_src = simplify_gen_subreg (V4SImode, src, GET_MODE (src), 0);
4967 emit_insn (gen_fn (low, new_src, GEN_INT (INTVAL (index) * 2)));
4968 emit_insn (gen_fn (high, new_src, GEN_INT (INTVAL (index) * 2 + 1)));
4971 /* Split a INSERT.D with operand DEST, SRC1.INDEX and SRC2. */
4973 void
4974 mips_split_msa_insert_d (rtx dest, rtx src1, rtx index, rtx src2)
4976 int i;
4977 gcc_assert (GET_MODE (dest) == GET_MODE (src1));
4978 gcc_assert ((GET_MODE (dest) == V2DImode
4979 && (GET_MODE (src2) == DImode || src2 == const0_rtx))
4980 || (GET_MODE (dest) == V2DFmode && GET_MODE (src2) == DFmode));
4982 /* Note that low is always from the lower index, and high is always
4983 from the higher index. */
4984 rtx low = mips_subword (src2, false);
4985 rtx high = mips_subword (src2, true);
4986 rtx new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0);
4987 rtx new_src1 = simplify_gen_subreg (V4SImode, src1, GET_MODE (src1), 0);
4988 i = exact_log2 (INTVAL (index));
4989 gcc_assert (i != -1);
4991 emit_insn (gen_msa_insert_w (new_dest, low, new_src1,
4992 GEN_INT (1 << (i * 2))));
4993 emit_insn (gen_msa_insert_w (new_dest, high, new_dest,
4994 GEN_INT (1 << (i * 2 + 1))));
4997 /* Split FILL.D. */
4999 void
5000 mips_split_msa_fill_d (rtx dest, rtx src)
5002 gcc_assert ((GET_MODE (dest) == V2DImode
5003 && (GET_MODE (src) == DImode || src == const0_rtx))
5004 || (GET_MODE (dest) == V2DFmode && GET_MODE (src) == DFmode));
5006 /* Note that low is always from the lower index, and high is always
5007 from the higher index. */
5008 rtx low, high;
5009 if (src == const0_rtx)
5011 low = src;
5012 high = src;
5014 else
5016 low = mips_subword (src, false);
5017 high = mips_subword (src, true);
5019 rtx new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0);
5020 emit_insn (gen_msa_fill_w (new_dest, low));
5021 emit_insn (gen_msa_insert_w (new_dest, high, new_dest, GEN_INT (1 << 1)));
5022 emit_insn (gen_msa_insert_w (new_dest, high, new_dest, GEN_INT (1 << 3)));
5025 /* Return true if a move from SRC to DEST in INSN should be split. */
5027 bool
5028 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
5030 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
5033 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
5034 holds. */
5036 void
5037 mips_split_move_insn (rtx dest, rtx src, rtx insn)
5039 mips_split_move (dest, src, mips_insn_split_type (insn));
5042 /* Return the appropriate instructions to move SRC into DEST. Assume
5043 that SRC is operand 1 and DEST is operand 0. */
5045 const char *
5046 mips_output_move (rtx dest, rtx src)
5048 enum rtx_code dest_code = GET_CODE (dest);
5049 enum rtx_code src_code = GET_CODE (src);
5050 machine_mode mode = GET_MODE (dest);
5051 bool dbl_p = (GET_MODE_SIZE (mode) == 8);
5052 bool msa_p = MSA_SUPPORTED_MODE_P (mode);
5053 enum mips_symbol_type symbol_type;
5055 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
5056 return "#";
5058 if (msa_p
5059 && dest_code == REG && FP_REG_P (REGNO (dest))
5060 && src_code == CONST_VECTOR
5061 && CONST_INT_P (CONST_VECTOR_ELT (src, 0)))
5063 gcc_assert (mips_const_vector_same_int_p (src, mode, -512, 511));
5064 return "ldi.%v0\t%w0,%E1";
5067 if ((src_code == REG && GP_REG_P (REGNO (src)))
5068 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
5070 if (dest_code == REG)
5072 if (GP_REG_P (REGNO (dest)))
5073 return "move\t%0,%z1";
5075 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
5077 if (ISA_HAS_DSP_MULT)
5078 return "mult\t%q0,%.,%.";
5079 else
5080 return "mult\t%.,%.";
5083 /* Moves to HI are handled by special .md insns. */
5084 if (REGNO (dest) == LO_REGNUM)
5085 return "mtlo\t%z1";
5087 if (DSP_ACC_REG_P (REGNO (dest)))
5089 static char retval[] = "mt__\t%z1,%q0";
5091 retval[2] = reg_names[REGNO (dest)][4];
5092 retval[3] = reg_names[REGNO (dest)][5];
5093 return retval;
5096 if (FP_REG_P (REGNO (dest)))
5098 if (msa_p)
5100 gcc_assert (src == CONST0_RTX (GET_MODE (src)));
5101 return "ldi.%v0\t%w0,0";
5104 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
5107 if (ALL_COP_REG_P (REGNO (dest)))
5109 static char retval[] = "dmtc_\t%z1,%0";
5111 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
5112 return dbl_p ? retval : retval + 1;
5115 if (dest_code == MEM)
5116 switch (GET_MODE_SIZE (mode))
5118 case 1: return "sb\t%z1,%0";
5119 case 2: return "sh\t%z1,%0";
5120 case 4: return "sw\t%z1,%0";
5121 case 8: return "sd\t%z1,%0";
5122 default: gcc_unreachable ();
5125 if (dest_code == REG && GP_REG_P (REGNO (dest)))
5127 if (src_code == REG)
5129 /* Moves from HI are handled by special .md insns. */
5130 if (REGNO (src) == LO_REGNUM)
5132 /* When generating VR4120 or VR4130 code, we use MACC and
5133 DMACC instead of MFLO. This avoids both the normal
5134 MIPS III HI/LO hazards and the errata related to
5135 -mfix-vr4130. */
5136 if (ISA_HAS_MACCHI)
5137 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
5138 return "mflo\t%0";
5141 if (DSP_ACC_REG_P (REGNO (src)))
5143 static char retval[] = "mf__\t%0,%q1";
5145 retval[2] = reg_names[REGNO (src)][4];
5146 retval[3] = reg_names[REGNO (src)][5];
5147 return retval;
5150 if (FP_REG_P (REGNO (src)))
5152 gcc_assert (!msa_p);
5153 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
5156 if (ALL_COP_REG_P (REGNO (src)))
5158 static char retval[] = "dmfc_\t%0,%1";
5160 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
5161 return dbl_p ? retval : retval + 1;
5165 if (src_code == MEM)
5166 switch (GET_MODE_SIZE (mode))
5168 case 1: return "lbu\t%0,%1";
5169 case 2: return "lhu\t%0,%1";
5170 case 4: return "lw\t%0,%1";
5171 case 8: return "ld\t%0,%1";
5172 default: gcc_unreachable ();
5175 if (src_code == CONST_INT)
5177 /* Don't use the X format for the operand itself, because that
5178 will give out-of-range numbers for 64-bit hosts and 32-bit
5179 targets. */
5180 if (!TARGET_MIPS16)
5181 return "li\t%0,%1\t\t\t# %X1";
5183 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
5184 return "li\t%0,%1";
5186 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
5187 return "#";
5190 if (src_code == HIGH)
5191 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
5193 if (CONST_GP_P (src))
5194 return "move\t%0,%1";
5196 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
5197 && mips_lo_relocs[symbol_type] != 0)
5199 /* A signed 16-bit constant formed by applying a relocation
5200 operator to a symbolic address. */
5201 gcc_assert (!mips_split_p[symbol_type]);
5202 return "li\t%0,%R1";
5205 if (symbolic_operand (src, VOIDmode))
5207 gcc_assert (TARGET_MIPS16
5208 ? TARGET_MIPS16_TEXT_LOADS
5209 : !TARGET_EXPLICIT_RELOCS);
5210 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
5213 if (src_code == REG && FP_REG_P (REGNO (src)))
5215 if (dest_code == REG && FP_REG_P (REGNO (dest)))
5217 if (GET_MODE (dest) == V2SFmode)
5218 return "mov.ps\t%0,%1";
5219 else if (msa_p)
5220 return "move.v\t%w0,%w1";
5221 else
5222 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
5225 if (dest_code == MEM)
5227 if (msa_p)
5228 return "st.%v1\t%w1,%0";
5230 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
5233 if (dest_code == REG && FP_REG_P (REGNO (dest)))
5235 if (src_code == MEM)
5237 if (msa_p)
5238 return "ld.%v0\t%w0,%1";
5240 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
5243 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
5245 static char retval[] = "l_c_\t%0,%1";
5247 retval[1] = (dbl_p ? 'd' : 'w');
5248 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
5249 return retval;
5251 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
5253 static char retval[] = "s_c_\t%1,%0";
5255 retval[1] = (dbl_p ? 'd' : 'w');
5256 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
5257 return retval;
5259 gcc_unreachable ();
5262 /* Return true if CMP1 is a suitable second operand for integer ordering
5263 test CODE. See also the *sCC patterns in mips.md. */
5265 static bool
5266 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
5268 switch (code)
5270 case GT:
5271 case GTU:
5272 return reg_or_0_operand (cmp1, VOIDmode);
5274 case GE:
5275 case GEU:
5276 return !TARGET_MIPS16 && cmp1 == const1_rtx;
5278 case LT:
5279 case LTU:
5280 return arith_operand (cmp1, VOIDmode);
5282 case LE:
5283 return sle_operand (cmp1, VOIDmode);
5285 case LEU:
5286 return sleu_operand (cmp1, VOIDmode);
5288 default:
5289 gcc_unreachable ();
5293 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
5294 integer ordering test *CODE, or if an equivalent combination can
5295 be formed by adjusting *CODE and *CMP1. When returning true, update
5296 *CODE and *CMP1 with the chosen code and operand, otherwise leave
5297 them alone. */
5299 static bool
5300 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
5301 machine_mode mode)
5303 HOST_WIDE_INT plus_one;
5305 if (mips_int_order_operand_ok_p (*code, *cmp1))
5306 return true;
5308 if (CONST_INT_P (*cmp1))
5309 switch (*code)
5311 case LE:
5312 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
5313 if (INTVAL (*cmp1) < plus_one)
5315 *code = LT;
5316 *cmp1 = force_reg (mode, GEN_INT (plus_one));
5317 return true;
5319 break;
5321 case LEU:
5322 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
5323 if (plus_one != 0)
5325 *code = LTU;
5326 *cmp1 = force_reg (mode, GEN_INT (plus_one));
5327 return true;
5329 break;
5331 default:
5332 break;
5334 return false;
5337 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
5338 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
5339 is nonnull, it's OK to set TARGET to the inverse of the result and
5340 flip *INVERT_PTR instead. */
5342 static void
5343 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
5344 rtx target, rtx cmp0, rtx cmp1)
5346 machine_mode mode;
5348 /* First see if there is a MIPS instruction that can do this operation.
5349 If not, try doing the same for the inverse operation. If that also
5350 fails, force CMP1 into a register and try again. */
5351 mode = GET_MODE (cmp0);
5352 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
5353 mips_emit_binary (code, target, cmp0, cmp1);
5354 else
5356 enum rtx_code inv_code = reverse_condition (code);
5357 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
5359 cmp1 = force_reg (mode, cmp1);
5360 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
5362 else if (invert_ptr == 0)
5364 rtx inv_target;
5366 inv_target = mips_force_binary (GET_MODE (target),
5367 inv_code, cmp0, cmp1);
5368 mips_emit_binary (XOR, target, inv_target, const1_rtx);
5370 else
5372 *invert_ptr = !*invert_ptr;
5373 mips_emit_binary (inv_code, target, cmp0, cmp1);
5378 /* Return a register that is zero iff CMP0 and CMP1 are equal.
5379 The register will have the same mode as CMP0. */
5381 static rtx
5382 mips_zero_if_equal (rtx cmp0, rtx cmp1)
5384 if (cmp1 == const0_rtx)
5385 return cmp0;
5387 if (uns_arith_operand (cmp1, VOIDmode))
5388 return expand_binop (GET_MODE (cmp0), xor_optab,
5389 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
5391 return expand_binop (GET_MODE (cmp0), sub_optab,
5392 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
5395 /* Convert *CODE into a code that can be used in a floating-point
5396 scc instruction (C.cond.fmt). Return true if the values of
5397 the condition code registers will be inverted, with 0 indicating
5398 that the condition holds. */
5400 static bool
5401 mips_reversed_fp_cond (enum rtx_code *code)
5403 switch (*code)
5405 case NE:
5406 case LTGT:
5407 case ORDERED:
5408 *code = reverse_condition_maybe_unordered (*code);
5409 return true;
5411 default:
5412 return false;
5416 /* Allocate a floating-point condition-code register of mode MODE.
5418 These condition code registers are used for certain kinds
5419 of compound operation, such as compare and branches, vconds,
5420 and built-in functions. At expand time, their use is entirely
5421 controlled by MIPS-specific code and is entirely internal
5422 to these compound operations.
5424 We could (and did in the past) expose condition-code values
5425 as pseudo registers and leave the register allocator to pick
5426 appropriate registers. The problem is that it is not practically
5427 possible for the rtl optimizers to guarantee that no spills will
5428 be needed, even when AVOID_CCMODE_COPIES is defined. We would
5429 therefore need spill and reload sequences to handle the worst case.
5431 Although such sequences do exist, they are very expensive and are
5432 not something we'd want to use. This is especially true of CCV2 and
5433 CCV4, where all the shuffling would greatly outweigh whatever benefit
5434 the vectorization itself provides.
5436 The main benefit of having more than one condition-code register
5437 is to allow the pipelining of operations, especially those involving
5438 comparisons and conditional moves. We don't really expect the
5439 registers to be live for long periods, and certainly never want
5440 them to be live across calls.
5442 Also, there should be no penalty attached to using all the available
5443 registers. They are simply bits in the same underlying FPU control
5444 register.
5446 We therefore expose the hardware registers from the outset and use
5447 a simple round-robin allocation scheme. */
5449 static rtx
5450 mips_allocate_fcc (machine_mode mode)
5452 unsigned int regno, count;
5454 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
5456 if (mode == CCmode)
5457 count = 1;
5458 else if (mode == CCV2mode)
5459 count = 2;
5460 else if (mode == CCV4mode)
5461 count = 4;
5462 else
5463 gcc_unreachable ();
5465 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
5466 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
5467 cfun->machine->next_fcc = 0;
5468 regno = ST_REG_FIRST + cfun->machine->next_fcc;
5469 cfun->machine->next_fcc += count;
5470 return gen_rtx_REG (mode, regno);
5473 /* Convert a comparison into something that can be used in a branch or
5474 conditional move. On entry, *OP0 and *OP1 are the values being
5475 compared and *CODE is the code used to compare them.
5477 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
5478 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
5479 otherwise any standard branch condition can be used. The standard branch
5480 conditions are:
5482 - EQ or NE between two registers.
5483 - any comparison between a register and zero.
5484 - if compact branches are available then any condition is valid. */
5486 static void
5487 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
5489 rtx cmp_op0 = *op0;
5490 rtx cmp_op1 = *op1;
5492 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
5494 if (!need_eq_ne_p && *op1 == const0_rtx)
5496 else if (*code == EQ || *code == NE)
5498 if (need_eq_ne_p)
5500 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
5501 *op1 = const0_rtx;
5503 else
5504 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
5506 else if (!need_eq_ne_p && TARGET_CB_MAYBE)
5508 bool swap = false;
5509 switch (*code)
5511 case LE:
5512 swap = true;
5513 *code = GE;
5514 break;
5515 case GT:
5516 swap = true;
5517 *code = LT;
5518 break;
5519 case LEU:
5520 swap = true;
5521 *code = GEU;
5522 break;
5523 case GTU:
5524 swap = true;
5525 *code = LTU;
5526 break;
5527 case GE:
5528 case LT:
5529 case GEU:
5530 case LTU:
5531 /* Do nothing. */
5532 break;
5533 default:
5534 gcc_unreachable ();
5536 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
5537 if (swap)
5539 rtx tmp = *op1;
5540 *op1 = *op0;
5541 *op0 = tmp;
5544 else
5546 /* The comparison needs a separate scc instruction. Store the
5547 result of the scc in *OP0 and compare it against zero. */
5548 bool invert = false;
5549 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
5550 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
5551 *code = (invert ? EQ : NE);
5552 *op1 = const0_rtx;
5555 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
5557 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
5558 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
5559 *code = NE;
5560 *op1 = const0_rtx;
5562 else
5564 enum rtx_code cmp_code;
5566 /* Floating-point tests use a separate C.cond.fmt or CMP.cond.fmt
5567 comparison to set a register. The branch or conditional move will
5568 then compare that register against zero.
5570 Set CMP_CODE to the code of the comparison instruction and
5571 *CODE to the code that the branch or move should use. */
5572 cmp_code = *code;
5573 if (ISA_HAS_CCF)
5575 /* All FP conditions can be implemented directly with CMP.cond.fmt
5576 or by reversing the operands. */
5577 *code = NE;
5578 *op0 = gen_reg_rtx (CCFmode);
5580 else
5582 /* Three FP conditions cannot be implemented by reversing the
5583 operands for C.cond.fmt, instead a reversed condition code is
5584 required and a test for false. */
5585 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
5586 if (ISA_HAS_8CC)
5587 *op0 = mips_allocate_fcc (CCmode);
5588 else
5589 *op0 = gen_rtx_REG (CCmode, FPSW_REGNUM);
5592 *op1 = const0_rtx;
5593 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
5597 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
5598 and OPERAND[3]. Store the result in OPERANDS[0].
5600 On 64-bit targets, the mode of the comparison and target will always be
5601 SImode, thus possibly narrower than that of the comparison's operands. */
5603 void
5604 mips_expand_scc (rtx operands[])
5606 rtx target = operands[0];
5607 enum rtx_code code = GET_CODE (operands[1]);
5608 rtx op0 = operands[2];
5609 rtx op1 = operands[3];
5611 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
5613 if (code == EQ || code == NE)
5615 if (ISA_HAS_SEQ_SNE
5616 && reg_imm10_operand (op1, GET_MODE (op1)))
5617 mips_emit_binary (code, target, op0, op1);
5618 else
5620 rtx zie = mips_zero_if_equal (op0, op1);
5621 mips_emit_binary (code, target, zie, const0_rtx);
5624 else
5625 mips_emit_int_order_test (code, 0, target, op0, op1);
5628 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5629 CODE and jump to OPERANDS[3] if the condition holds. */
5631 void
5632 mips_expand_conditional_branch (rtx *operands)
5634 enum rtx_code code = GET_CODE (operands[0]);
5635 rtx op0 = operands[1];
5636 rtx op1 = operands[2];
5637 rtx condition;
5639 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
5640 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
5641 emit_jump_insn (gen_condjump (condition, operands[3]));
5644 /* Implement:
5646 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5647 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5649 void
5650 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
5651 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
5653 rtx cmp_result;
5654 bool reversed_p;
5656 reversed_p = mips_reversed_fp_cond (&cond);
5657 cmp_result = mips_allocate_fcc (CCV2mode);
5658 emit_insn (gen_scc_ps (cmp_result,
5659 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
5660 if (reversed_p)
5661 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
5662 cmp_result));
5663 else
5664 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
5665 cmp_result));
5668 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5669 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5671 void
5672 mips_expand_conditional_move (rtx *operands)
5674 rtx cond;
5675 enum rtx_code code = GET_CODE (operands[1]);
5676 rtx op0 = XEXP (operands[1], 0);
5677 rtx op1 = XEXP (operands[1], 1);
5679 mips_emit_compare (&code, &op0, &op1, true);
5680 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
5682 /* There is no direct support for general conditional GP move involving
5683 two registers using SEL. */
5684 if (ISA_HAS_SEL
5685 && INTEGRAL_MODE_P (GET_MODE (operands[2]))
5686 && register_operand (operands[2], VOIDmode)
5687 && register_operand (operands[3], VOIDmode))
5689 machine_mode mode = GET_MODE (operands[0]);
5690 rtx temp = gen_reg_rtx (mode);
5691 rtx temp2 = gen_reg_rtx (mode);
5693 emit_insn (gen_rtx_SET (temp,
5694 gen_rtx_IF_THEN_ELSE (mode, cond,
5695 operands[2], const0_rtx)));
5697 /* Flip the test for the second operand. */
5698 cond = gen_rtx_fmt_ee ((code == EQ) ? NE : EQ, GET_MODE (op0), op0, op1);
5700 emit_insn (gen_rtx_SET (temp2,
5701 gen_rtx_IF_THEN_ELSE (mode, cond,
5702 operands[3], const0_rtx)));
5704 /* Merge the two results, at least one is guaranteed to be zero. */
5705 emit_insn (gen_rtx_SET (operands[0], gen_rtx_IOR (mode, temp, temp2)));
5707 else
5709 if (FLOAT_MODE_P (GET_MODE (operands[2])) && !ISA_HAS_SEL)
5711 operands[2] = force_reg (GET_MODE (operands[0]), operands[2]);
5712 operands[3] = force_reg (GET_MODE (operands[0]), operands[3]);
5715 emit_insn (gen_rtx_SET (operands[0],
5716 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
5717 operands[2], operands[3])));
5721 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5723 void
5724 mips_expand_conditional_trap (rtx comparison)
5726 rtx op0, op1;
5727 machine_mode mode;
5728 enum rtx_code code;
5730 /* MIPS conditional trap instructions don't have GT or LE flavors,
5731 so we must swap the operands and convert to LT and GE respectively. */
5732 code = GET_CODE (comparison);
5733 switch (code)
5735 case GT:
5736 case LE:
5737 case GTU:
5738 case LEU:
5739 code = swap_condition (code);
5740 op0 = XEXP (comparison, 1);
5741 op1 = XEXP (comparison, 0);
5742 break;
5744 default:
5745 op0 = XEXP (comparison, 0);
5746 op1 = XEXP (comparison, 1);
5747 break;
5750 mode = GET_MODE (XEXP (comparison, 0));
5751 op0 = force_reg (mode, op0);
5752 if (!(ISA_HAS_COND_TRAPI
5753 ? arith_operand (op1, mode)
5754 : reg_or_0_operand (op1, mode)))
5755 op1 = force_reg (mode, op1);
5757 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
5758 gen_rtx_fmt_ee (code, mode, op0, op1),
5759 const0_rtx));
5762 /* Initialize *CUM for a call to a function of type FNTYPE. */
5764 void
5765 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
5767 memset (cum, 0, sizeof (*cum));
5768 cum->prototype = (fntype && prototype_p (fntype));
5769 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
5772 /* Fill INFO with information about a single argument. CUM is the
5773 cumulative state for earlier arguments. MODE is the mode of this
5774 argument and TYPE is its type (if known). NAMED is true if this
5775 is a named (fixed) argument rather than a variable one. */
5777 static void
5778 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
5779 machine_mode mode, const_tree type, bool named)
5781 bool doubleword_aligned_p;
5782 unsigned int num_bytes, num_words, max_regs;
5784 /* Work out the size of the argument. */
5785 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5786 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5788 /* Decide whether it should go in a floating-point register, assuming
5789 one is free. Later code checks for availability.
5791 The checks against UNITS_PER_FPVALUE handle the soft-float and
5792 single-float cases. */
5793 switch (mips_abi)
5795 case ABI_EABI:
5796 /* The EABI conventions have traditionally been defined in terms
5797 of TYPE_MODE, regardless of the actual type. */
5798 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
5799 || mode == V2SFmode)
5800 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5801 break;
5803 case ABI_32:
5804 case ABI_O64:
5805 /* Only leading floating-point scalars are passed in
5806 floating-point registers. We also handle vector floats the same
5807 say, which is OK because they are not covered by the standard ABI. */
5808 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode);
5809 info->fpr_p = (!cum->gp_reg_found
5810 && cum->arg_number < 2
5811 && (type == 0
5812 || SCALAR_FLOAT_TYPE_P (type)
5813 || VECTOR_FLOAT_TYPE_P (type))
5814 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5815 || mode == V2SFmode)
5816 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5817 break;
5819 case ABI_N32:
5820 case ABI_64:
5821 /* Scalar, complex and vector floating-point types are passed in
5822 floating-point registers, as long as this is a named rather
5823 than a variable argument. */
5824 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode);
5825 info->fpr_p = (named
5826 && (type == 0 || FLOAT_TYPE_P (type))
5827 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5828 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5829 || mode == V2SFmode)
5830 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
5832 /* ??? According to the ABI documentation, the real and imaginary
5833 parts of complex floats should be passed in individual registers.
5834 The real and imaginary parts of stack arguments are supposed
5835 to be contiguous and there should be an extra word of padding
5836 at the end.
5838 This has two problems. First, it makes it impossible to use a
5839 single "void *" va_list type, since register and stack arguments
5840 are passed differently. (At the time of writing, MIPSpro cannot
5841 handle complex float varargs correctly.) Second, it's unclear
5842 what should happen when there is only one register free.
5844 For now, we assume that named complex floats should go into FPRs
5845 if there are two FPRs free, otherwise they should be passed in the
5846 same way as a struct containing two floats. */
5847 if (info->fpr_p
5848 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5849 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
5851 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
5852 info->fpr_p = false;
5853 else
5854 num_words = 2;
5856 break;
5858 default:
5859 gcc_unreachable ();
5862 /* See whether the argument has doubleword alignment. */
5863 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
5864 > BITS_PER_WORD);
5866 /* Set REG_OFFSET to the register count we're interested in.
5867 The EABI allocates the floating-point registers separately,
5868 but the other ABIs allocate them like integer registers. */
5869 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5870 ? cum->num_fprs
5871 : cum->num_gprs);
5873 /* Advance to an even register if the argument is doubleword-aligned. */
5874 if (doubleword_aligned_p)
5875 info->reg_offset += info->reg_offset & 1;
5877 /* Work out the offset of a stack argument. */
5878 info->stack_offset = cum->stack_words;
5879 if (doubleword_aligned_p)
5880 info->stack_offset += info->stack_offset & 1;
5882 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5884 /* Partition the argument between registers and stack. */
5885 info->reg_words = MIN (num_words, max_regs);
5886 info->stack_words = num_words - info->reg_words;
5889 /* INFO describes a register argument that has the normal format for the
5890 argument's mode. Return the register it uses, assuming that FPRs are
5891 available if HARD_FLOAT_P. */
5893 static unsigned int
5894 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5896 if (!info->fpr_p || !hard_float_p)
5897 return GP_ARG_FIRST + info->reg_offset;
5898 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5899 /* In o32, the second argument is always passed in $f14
5900 for TARGET_DOUBLE_FLOAT, regardless of whether the
5901 first argument was a word or doubleword. */
5902 return FP_ARG_FIRST + 2;
5903 else
5904 return FP_ARG_FIRST + info->reg_offset;
5907 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5909 static bool
5910 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5912 return !TARGET_OLDABI;
5915 /* Implement TARGET_FUNCTION_ARG. */
5917 static rtx
5918 mips_function_arg (cumulative_args_t cum_v, machine_mode mode,
5919 const_tree type, bool named)
5921 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5922 struct mips_arg_info info;
5924 /* We will be called with a mode of VOIDmode after the last argument
5925 has been seen. Whatever we return will be passed to the call expander.
5926 If we need a MIPS16 fp_code, return a REG with the code stored as
5927 the mode. */
5928 if (mode == VOIDmode)
5930 if (TARGET_MIPS16 && cum->fp_code != 0)
5931 return gen_rtx_REG ((machine_mode) cum->fp_code, 0);
5932 else
5933 return NULL;
5936 mips_get_arg_info (&info, cum, mode, type, named);
5938 /* Return straight away if the whole argument is passed on the stack. */
5939 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5940 return NULL;
5942 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5943 contains a double in its entirety, then that 64-bit chunk is passed
5944 in a floating-point register. */
5945 if (TARGET_NEWABI
5946 && TARGET_HARD_FLOAT
5947 && named
5948 && type != 0
5949 && TREE_CODE (type) == RECORD_TYPE
5950 && TYPE_SIZE_UNIT (type)
5951 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type)))
5953 tree field;
5955 /* First check to see if there is any such field. */
5956 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5957 if (TREE_CODE (field) == FIELD_DECL
5958 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5959 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5960 && tree_fits_shwi_p (bit_position (field))
5961 && int_bit_position (field) % BITS_PER_WORD == 0)
5962 break;
5964 if (field != 0)
5966 /* Now handle the special case by returning a PARALLEL
5967 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5968 chunks are passed in registers. */
5969 unsigned int i;
5970 HOST_WIDE_INT bitpos;
5971 rtx ret;
5973 /* assign_parms checks the mode of ENTRY_PARM, so we must
5974 use the actual mode here. */
5975 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5977 bitpos = 0;
5978 field = TYPE_FIELDS (type);
5979 for (i = 0; i < info.reg_words; i++)
5981 rtx reg;
5983 for (; field; field = DECL_CHAIN (field))
5984 if (TREE_CODE (field) == FIELD_DECL
5985 && int_bit_position (field) >= bitpos)
5986 break;
5988 if (field
5989 && int_bit_position (field) == bitpos
5990 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5991 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5992 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5993 else
5994 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5996 XVECEXP (ret, 0, i)
5997 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5998 GEN_INT (bitpos / BITS_PER_UNIT));
6000 bitpos += BITS_PER_WORD;
6002 return ret;
6006 /* Handle the n32/n64 conventions for passing complex floating-point
6007 arguments in FPR pairs. The real part goes in the lower register
6008 and the imaginary part goes in the upper register. */
6009 if (TARGET_NEWABI
6010 && info.fpr_p
6011 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6013 rtx real, imag;
6014 machine_mode inner;
6015 unsigned int regno;
6017 inner = GET_MODE_INNER (mode);
6018 regno = FP_ARG_FIRST + info.reg_offset;
6019 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
6021 /* Real part in registers, imaginary part on stack. */
6022 gcc_assert (info.stack_words == info.reg_words);
6023 return gen_rtx_REG (inner, regno);
6025 else
6027 gcc_assert (info.stack_words == 0);
6028 real = gen_rtx_EXPR_LIST (VOIDmode,
6029 gen_rtx_REG (inner, regno),
6030 const0_rtx);
6031 imag = gen_rtx_EXPR_LIST (VOIDmode,
6032 gen_rtx_REG (inner,
6033 regno + info.reg_words / 2),
6034 GEN_INT (GET_MODE_SIZE (inner)));
6035 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
6039 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
6042 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
6044 static void
6045 mips_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
6046 const_tree type, bool named)
6048 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6049 struct mips_arg_info info;
6051 mips_get_arg_info (&info, cum, mode, type, named);
6053 if (!info.fpr_p)
6054 cum->gp_reg_found = true;
6056 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
6057 an explanation of what this code does. It assumes that we're using
6058 either the o32 or the o64 ABI, both of which pass at most 2 arguments
6059 in FPRs. */
6060 if (cum->arg_number < 2 && info.fpr_p)
6061 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
6063 /* Advance the register count. This has the effect of setting
6064 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
6065 argument required us to skip the final GPR and pass the whole
6066 argument on the stack. */
6067 if (mips_abi != ABI_EABI || !info.fpr_p)
6068 cum->num_gprs = info.reg_offset + info.reg_words;
6069 else if (info.reg_words > 0)
6070 cum->num_fprs += MAX_FPRS_PER_FMT;
6072 /* Advance the stack word count. */
6073 if (info.stack_words > 0)
6074 cum->stack_words = info.stack_offset + info.stack_words;
6076 cum->arg_number++;
6079 /* Implement TARGET_ARG_PARTIAL_BYTES. */
6081 static int
6082 mips_arg_partial_bytes (cumulative_args_t cum,
6083 machine_mode mode, tree type, bool named)
6085 struct mips_arg_info info;
6087 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
6088 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
6091 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
6092 least PARM_BOUNDARY bits of alignment, but will be given anything up
6093 to STACK_BOUNDARY bits if the type requires it. */
6095 static unsigned int
6096 mips_function_arg_boundary (machine_mode mode, const_tree type)
6098 unsigned int alignment;
6100 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
6101 if (alignment < PARM_BOUNDARY)
6102 alignment = PARM_BOUNDARY;
6103 if (alignment > STACK_BOUNDARY)
6104 alignment = STACK_BOUNDARY;
6105 return alignment;
6108 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
6110 static machine_mode
6111 mips_get_reg_raw_mode (int regno)
6113 if (TARGET_FLOATXX && FP_REG_P (regno))
6114 return DFmode;
6115 return default_get_reg_raw_mode (regno);
6118 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
6119 upward rather than downward. In other words, return true if the
6120 first byte of the stack slot has useful data, false if the last
6121 byte does. */
6123 bool
6124 mips_pad_arg_upward (machine_mode mode, const_tree type)
6126 /* On little-endian targets, the first byte of every stack argument
6127 is passed in the first byte of the stack slot. */
6128 if (!BYTES_BIG_ENDIAN)
6129 return true;
6131 /* Otherwise, integral types are padded downward: the last byte of a
6132 stack argument is passed in the last byte of the stack slot. */
6133 if (type != 0
6134 ? (INTEGRAL_TYPE_P (type)
6135 || POINTER_TYPE_P (type)
6136 || FIXED_POINT_TYPE_P (type))
6137 : (SCALAR_INT_MODE_P (mode)
6138 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
6139 return false;
6141 /* Big-endian o64 pads floating-point arguments downward. */
6142 if (mips_abi == ABI_O64)
6143 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
6144 return false;
6146 /* Other types are padded upward for o32, o64, n32 and n64. */
6147 if (mips_abi != ABI_EABI)
6148 return true;
6150 /* Arguments smaller than a stack slot are padded downward. */
6151 if (mode != BLKmode)
6152 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
6153 else
6154 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
6157 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
6158 if the least significant byte of the register has useful data. Return
6159 the opposite if the most significant byte does. */
6161 bool
6162 mips_pad_reg_upward (machine_mode mode, tree type)
6164 /* No shifting is required for floating-point arguments. */
6165 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
6166 return !BYTES_BIG_ENDIAN;
6168 /* Otherwise, apply the same padding to register arguments as we do
6169 to stack arguments. */
6170 return mips_pad_arg_upward (mode, type);
6173 /* Return nonzero when an argument must be passed by reference. */
6175 static bool
6176 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
6177 machine_mode mode, const_tree type,
6178 bool named ATTRIBUTE_UNUSED)
6180 if (mips_abi == ABI_EABI)
6182 int size;
6184 /* ??? How should SCmode be handled? */
6185 if (mode == DImode || mode == DFmode
6186 || mode == DQmode || mode == UDQmode
6187 || mode == DAmode || mode == UDAmode)
6188 return 0;
6190 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
6191 return size == -1 || size > UNITS_PER_WORD;
6193 else
6195 /* If we have a variable-sized parameter, we have no choice. */
6196 return targetm.calls.must_pass_in_stack (mode, type);
6200 /* Implement TARGET_CALLEE_COPIES. */
6202 static bool
6203 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
6204 machine_mode mode ATTRIBUTE_UNUSED,
6205 const_tree type ATTRIBUTE_UNUSED, bool named)
6207 return mips_abi == ABI_EABI && named;
6210 /* See whether VALTYPE is a record whose fields should be returned in
6211 floating-point registers. If so, return the number of fields and
6212 list them in FIELDS (which should have two elements). Return 0
6213 otherwise.
6215 For n32 & n64, a structure with one or two fields is returned in
6216 floating-point registers as long as every field has a floating-point
6217 type. */
6219 static int
6220 mips_fpr_return_fields (const_tree valtype, tree *fields)
6222 tree field;
6223 int i;
6225 if (!TARGET_NEWABI)
6226 return 0;
6228 if (TREE_CODE (valtype) != RECORD_TYPE)
6229 return 0;
6231 i = 0;
6232 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
6234 if (TREE_CODE (field) != FIELD_DECL)
6235 continue;
6237 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
6238 return 0;
6240 if (i == 2)
6241 return 0;
6243 fields[i++] = field;
6245 return i;
6248 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
6249 a value in the most significant part of $2/$3 if:
6251 - the target is big-endian;
6253 - the value has a structure or union type (we generalize this to
6254 cover aggregates from other languages too); and
6256 - the structure is not returned in floating-point registers. */
6258 static bool
6259 mips_return_in_msb (const_tree valtype)
6261 tree fields[2];
6263 return (TARGET_NEWABI
6264 && TARGET_BIG_ENDIAN
6265 && AGGREGATE_TYPE_P (valtype)
6266 && mips_fpr_return_fields (valtype, fields) == 0);
6269 /* Return true if the function return value MODE will get returned in a
6270 floating-point register. */
6272 static bool
6273 mips_return_mode_in_fpr_p (machine_mode mode)
6275 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode);
6276 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
6277 || mode == V2SFmode
6278 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6279 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
6282 /* Return the representation of an FPR return register when the
6283 value being returned in FP_RETURN has mode VALUE_MODE and the
6284 return type itself has mode TYPE_MODE. On NewABI targets,
6285 the two modes may be different for structures like:
6287 struct __attribute__((packed)) foo { float f; }
6289 where we return the SFmode value of "f" in FP_RETURN, but where
6290 the structure itself has mode BLKmode. */
6292 static rtx
6293 mips_return_fpr_single (machine_mode type_mode,
6294 machine_mode value_mode)
6296 rtx x;
6298 x = gen_rtx_REG (value_mode, FP_RETURN);
6299 if (type_mode != value_mode)
6301 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
6302 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
6304 return x;
6307 /* Return a composite value in a pair of floating-point registers.
6308 MODE1 and OFFSET1 are the mode and byte offset for the first value,
6309 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
6310 complete value.
6312 For n32 & n64, $f0 always holds the first value and $f2 the second.
6313 Otherwise the values are packed together as closely as possible. */
6315 static rtx
6316 mips_return_fpr_pair (machine_mode mode,
6317 machine_mode mode1, HOST_WIDE_INT offset1,
6318 machine_mode mode2, HOST_WIDE_INT offset2)
6320 int inc;
6322 inc = (TARGET_NEWABI || mips_abi == ABI_32 ? 2 : MAX_FPRS_PER_FMT);
6323 return gen_rtx_PARALLEL
6324 (mode,
6325 gen_rtvec (2,
6326 gen_rtx_EXPR_LIST (VOIDmode,
6327 gen_rtx_REG (mode1, FP_RETURN),
6328 GEN_INT (offset1)),
6329 gen_rtx_EXPR_LIST (VOIDmode,
6330 gen_rtx_REG (mode2, FP_RETURN + inc),
6331 GEN_INT (offset2))));
6335 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
6336 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
6337 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
6339 static rtx
6340 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
6341 machine_mode mode)
6343 if (valtype)
6345 tree fields[2];
6346 int unsigned_p;
6347 const_tree func;
6349 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
6350 func = fn_decl_or_type;
6351 else
6352 func = NULL;
6354 mode = TYPE_MODE (valtype);
6355 unsigned_p = TYPE_UNSIGNED (valtype);
6357 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
6358 return values, promote the mode here too. */
6359 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
6361 /* Handle structures whose fields are returned in $f0/$f2. */
6362 switch (mips_fpr_return_fields (valtype, fields))
6364 case 1:
6365 return mips_return_fpr_single (mode,
6366 TYPE_MODE (TREE_TYPE (fields[0])));
6368 case 2:
6369 return mips_return_fpr_pair (mode,
6370 TYPE_MODE (TREE_TYPE (fields[0])),
6371 int_byte_position (fields[0]),
6372 TYPE_MODE (TREE_TYPE (fields[1])),
6373 int_byte_position (fields[1]));
6376 /* If a value is passed in the most significant part of a register, see
6377 whether we have to round the mode up to a whole number of words. */
6378 if (mips_return_in_msb (valtype))
6380 HOST_WIDE_INT size = int_size_in_bytes (valtype);
6381 if (size % UNITS_PER_WORD != 0)
6383 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
6384 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6388 /* For EABI, the class of return register depends entirely on MODE.
6389 For example, "struct { some_type x; }" and "union { some_type x; }"
6390 are returned in the same way as a bare "some_type" would be.
6391 Other ABIs only use FPRs for scalar, complex or vector types. */
6392 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
6393 return gen_rtx_REG (mode, GP_RETURN);
6396 if (!TARGET_MIPS16)
6398 /* Handle long doubles for n32 & n64. */
6399 if (mode == TFmode)
6400 return mips_return_fpr_pair (mode,
6401 DImode, 0,
6402 DImode, GET_MODE_SIZE (mode) / 2);
6404 if (mips_return_mode_in_fpr_p (mode))
6406 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6407 return mips_return_fpr_pair (mode,
6408 GET_MODE_INNER (mode), 0,
6409 GET_MODE_INNER (mode),
6410 GET_MODE_SIZE (mode) / 2);
6411 else
6412 return gen_rtx_REG (mode, FP_RETURN);
6416 return gen_rtx_REG (mode, GP_RETURN);
6419 /* Implement TARGET_FUNCTION_VALUE. */
6421 static rtx
6422 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
6423 bool outgoing ATTRIBUTE_UNUSED)
6425 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
6428 /* Implement TARGET_LIBCALL_VALUE. */
6430 static rtx
6431 mips_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
6433 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
6436 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
6438 On the MIPS, R2 R3 and F0 F2 are the only register thus used. */
6440 static bool
6441 mips_function_value_regno_p (const unsigned int regno)
6443 /* Most types only require one GPR or one FPR for return values but for
6444 hard-float two FPRs can be used for _Complex types (for all ABIs)
6445 and long doubles (for n64). */
6446 if (regno == GP_RETURN
6447 || regno == FP_RETURN
6448 || (FP_RETURN != GP_RETURN
6449 && regno == FP_RETURN + 2))
6450 return true;
6452 /* For o32 FP32, _Complex double will be returned in four 32-bit registers.
6453 This does not apply to o32 FPXX as floating-point function argument and
6454 return registers are described as 64-bit even though floating-point
6455 registers are primarily described as 32-bit internally.
6456 See: mips_get_reg_raw_mode. */
6457 if ((mips_abi == ABI_32 && TARGET_FLOAT32)
6458 && FP_RETURN != GP_RETURN
6459 && (regno == FP_RETURN + 1
6460 || regno == FP_RETURN + 3))
6461 return true;
6463 return false;
6466 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
6467 all BLKmode objects are returned in memory. Under the n32, n64
6468 and embedded ABIs, small structures are returned in a register.
6469 Objects with varying size must still be returned in memory, of
6470 course. */
6472 static bool
6473 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
6475 return (TARGET_OLDABI
6476 ? TYPE_MODE (type) == BLKmode
6477 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
6480 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
6482 static void
6483 mips_setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
6484 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6485 int no_rtl)
6487 CUMULATIVE_ARGS local_cum;
6488 int gp_saved, fp_saved;
6490 /* The caller has advanced CUM up to, but not beyond, the last named
6491 argument. Advance a local copy of CUM past the last "real" named
6492 argument, to find out how many registers are left over. */
6493 local_cum = *get_cumulative_args (cum);
6494 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
6495 true);
6497 /* Found out how many registers we need to save. */
6498 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
6499 fp_saved = (EABI_FLOAT_VARARGS_P
6500 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
6501 : 0);
6503 if (!no_rtl)
6505 if (gp_saved > 0)
6507 rtx ptr, mem;
6509 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
6510 REG_PARM_STACK_SPACE (cfun->decl)
6511 - gp_saved * UNITS_PER_WORD);
6512 mem = gen_frame_mem (BLKmode, ptr);
6513 set_mem_alias_set (mem, get_varargs_alias_set ());
6515 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
6516 mem, gp_saved);
6518 if (fp_saved > 0)
6520 /* We can't use move_block_from_reg, because it will use
6521 the wrong mode. */
6522 machine_mode mode;
6523 int off, i;
6525 /* Set OFF to the offset from virtual_incoming_args_rtx of
6526 the first float register. The FP save area lies below
6527 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
6528 off = ROUND_DOWN (-gp_saved * UNITS_PER_WORD, UNITS_PER_FPVALUE);
6529 off -= fp_saved * UNITS_PER_FPREG;
6531 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6533 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
6534 i += MAX_FPRS_PER_FMT)
6536 rtx ptr, mem;
6538 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
6539 mem = gen_frame_mem (mode, ptr);
6540 set_mem_alias_set (mem, get_varargs_alias_set ());
6541 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
6542 off += UNITS_PER_HWFPVALUE;
6546 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
6547 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
6548 + fp_saved * UNITS_PER_FPREG);
6551 /* Implement TARGET_BUILTIN_VA_LIST. */
6553 static tree
6554 mips_build_builtin_va_list (void)
6556 if (EABI_FLOAT_VARARGS_P)
6558 /* We keep 3 pointers, and two offsets.
6560 Two pointers are to the overflow area, which starts at the CFA.
6561 One of these is constant, for addressing into the GPR save area
6562 below it. The other is advanced up the stack through the
6563 overflow region.
6565 The third pointer is to the bottom of the GPR save area.
6566 Since the FPR save area is just below it, we can address
6567 FPR slots off this pointer.
6569 We also keep two one-byte offsets, which are to be subtracted
6570 from the constant pointers to yield addresses in the GPR and
6571 FPR save areas. These are downcounted as float or non-float
6572 arguments are used, and when they get to zero, the argument
6573 must be obtained from the overflow region. */
6574 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
6575 tree array, index;
6577 record = lang_hooks.types.make_type (RECORD_TYPE);
6579 f_ovfl = build_decl (BUILTINS_LOCATION,
6580 FIELD_DECL, get_identifier ("__overflow_argptr"),
6581 ptr_type_node);
6582 f_gtop = build_decl (BUILTINS_LOCATION,
6583 FIELD_DECL, get_identifier ("__gpr_top"),
6584 ptr_type_node);
6585 f_ftop = build_decl (BUILTINS_LOCATION,
6586 FIELD_DECL, get_identifier ("__fpr_top"),
6587 ptr_type_node);
6588 f_goff = build_decl (BUILTINS_LOCATION,
6589 FIELD_DECL, get_identifier ("__gpr_offset"),
6590 unsigned_char_type_node);
6591 f_foff = build_decl (BUILTINS_LOCATION,
6592 FIELD_DECL, get_identifier ("__fpr_offset"),
6593 unsigned_char_type_node);
6594 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
6595 warn on every user file. */
6596 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
6597 array = build_array_type (unsigned_char_type_node,
6598 build_index_type (index));
6599 f_res = build_decl (BUILTINS_LOCATION,
6600 FIELD_DECL, get_identifier ("__reserved"), array);
6602 DECL_FIELD_CONTEXT (f_ovfl) = record;
6603 DECL_FIELD_CONTEXT (f_gtop) = record;
6604 DECL_FIELD_CONTEXT (f_ftop) = record;
6605 DECL_FIELD_CONTEXT (f_goff) = record;
6606 DECL_FIELD_CONTEXT (f_foff) = record;
6607 DECL_FIELD_CONTEXT (f_res) = record;
6609 TYPE_FIELDS (record) = f_ovfl;
6610 DECL_CHAIN (f_ovfl) = f_gtop;
6611 DECL_CHAIN (f_gtop) = f_ftop;
6612 DECL_CHAIN (f_ftop) = f_goff;
6613 DECL_CHAIN (f_goff) = f_foff;
6614 DECL_CHAIN (f_foff) = f_res;
6616 layout_type (record);
6617 return record;
6619 else
6620 /* Otherwise, we use 'void *'. */
6621 return ptr_type_node;
6624 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
6626 static void
6627 mips_va_start (tree valist, rtx nextarg)
6629 if (EABI_FLOAT_VARARGS_P)
6631 const CUMULATIVE_ARGS *cum;
6632 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
6633 tree ovfl, gtop, ftop, goff, foff;
6634 tree t;
6635 int gpr_save_area_size;
6636 int fpr_save_area_size;
6637 int fpr_offset;
6639 cum = &crtl->args.info;
6640 gpr_save_area_size
6641 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
6642 fpr_save_area_size
6643 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
6645 f_ovfl = TYPE_FIELDS (va_list_type_node);
6646 f_gtop = DECL_CHAIN (f_ovfl);
6647 f_ftop = DECL_CHAIN (f_gtop);
6648 f_goff = DECL_CHAIN (f_ftop);
6649 f_foff = DECL_CHAIN (f_goff);
6651 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6652 NULL_TREE);
6653 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
6654 NULL_TREE);
6655 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
6656 NULL_TREE);
6657 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
6658 NULL_TREE);
6659 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
6660 NULL_TREE);
6662 /* Emit code to initialize OVFL, which points to the next varargs
6663 stack argument. CUM->STACK_WORDS gives the number of stack
6664 words used by named arguments. */
6665 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
6666 if (cum->stack_words > 0)
6667 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
6668 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
6669 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6671 /* Emit code to initialize GTOP, the top of the GPR save area. */
6672 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
6673 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
6674 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6676 /* Emit code to initialize FTOP, the top of the FPR save area.
6677 This address is gpr_save_area_bytes below GTOP, rounded
6678 down to the next fp-aligned boundary. */
6679 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
6680 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
6681 fpr_offset &= -UNITS_PER_FPVALUE;
6682 if (fpr_offset)
6683 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
6684 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
6685 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6687 /* Emit code to initialize GOFF, the offset from GTOP of the
6688 next GPR argument. */
6689 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
6690 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
6691 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6693 /* Likewise emit code to initialize FOFF, the offset from FTOP
6694 of the next FPR argument. */
6695 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
6696 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
6697 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6699 else
6701 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
6702 std_expand_builtin_va_start (valist, nextarg);
6706 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6707 types as well. */
6709 static tree
6710 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6711 gimple_seq *post_p)
6713 tree addr, t, type_size, rounded_size, valist_tmp;
6714 unsigned HOST_WIDE_INT align, boundary;
6715 bool indirect;
6717 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6718 if (indirect)
6719 type = build_pointer_type (type);
6721 align = PARM_BOUNDARY / BITS_PER_UNIT;
6722 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
6724 /* When we align parameter on stack for caller, if the parameter
6725 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6726 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6727 here with caller. */
6728 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6729 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6731 boundary /= BITS_PER_UNIT;
6733 /* Hoist the valist value into a temporary for the moment. */
6734 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
6736 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6737 requires greater alignment, we must perform dynamic alignment. */
6738 if (boundary > align)
6740 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6741 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
6742 gimplify_and_add (t, pre_p);
6744 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6745 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
6746 valist_tmp,
6747 build_int_cst (TREE_TYPE (valist), -boundary)));
6748 gimplify_and_add (t, pre_p);
6750 else
6751 boundary = align;
6753 /* If the actual alignment is less than the alignment of the type,
6754 adjust the type accordingly so that we don't assume strict alignment
6755 when dereferencing the pointer. */
6756 boundary *= BITS_PER_UNIT;
6757 if (boundary < TYPE_ALIGN (type))
6759 type = build_variant_type_copy (type);
6760 SET_TYPE_ALIGN (type, boundary);
6763 /* Compute the rounded size of the type. */
6764 type_size = size_in_bytes (type);
6765 rounded_size = round_up (type_size, align);
6767 /* Reduce rounded_size so it's sharable with the postqueue. */
6768 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
6770 /* Get AP. */
6771 addr = valist_tmp;
6772 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
6774 /* Small args are padded downward. */
6775 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
6776 rounded_size, size_int (align));
6777 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
6778 size_binop (MINUS_EXPR, rounded_size, type_size));
6779 addr = fold_build_pointer_plus (addr, t);
6782 /* Compute new value for AP. */
6783 t = fold_build_pointer_plus (valist_tmp, rounded_size);
6784 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6785 gimplify_and_add (t, pre_p);
6787 addr = fold_convert (build_pointer_type (type), addr);
6789 if (indirect)
6790 addr = build_va_arg_indirect_ref (addr);
6792 return build_va_arg_indirect_ref (addr);
6795 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6797 static tree
6798 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6799 gimple_seq *post_p)
6801 tree addr;
6802 bool indirect_p;
6804 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6805 if (indirect_p)
6806 type = build_pointer_type (type);
6808 if (!EABI_FLOAT_VARARGS_P)
6809 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6810 else
6812 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
6813 tree ovfl, top, off, align;
6814 HOST_WIDE_INT size, rsize, osize;
6815 tree t, u;
6817 f_ovfl = TYPE_FIELDS (va_list_type_node);
6818 f_gtop = DECL_CHAIN (f_ovfl);
6819 f_ftop = DECL_CHAIN (f_gtop);
6820 f_goff = DECL_CHAIN (f_ftop);
6821 f_foff = DECL_CHAIN (f_goff);
6823 /* Let:
6825 TOP be the top of the GPR or FPR save area;
6826 OFF be the offset from TOP of the next register;
6827 ADDR_RTX be the address of the argument;
6828 SIZE be the number of bytes in the argument type;
6829 RSIZE be the number of bytes used to store the argument
6830 when it's in the register save area; and
6831 OSIZE be the number of bytes used to store it when it's
6832 in the stack overflow area.
6834 The code we want is:
6836 1: off &= -rsize; // round down
6837 2: if (off != 0)
6838 3: {
6839 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6840 5: off -= rsize;
6841 6: }
6842 7: else
6843 8: {
6844 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6845 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6846 11: ovfl += osize;
6847 14: }
6849 [1] and [9] can sometimes be optimized away. */
6851 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6852 NULL_TREE);
6853 size = int_size_in_bytes (type);
6855 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
6856 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
6858 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
6859 unshare_expr (valist), f_ftop, NULL_TREE);
6860 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
6861 unshare_expr (valist), f_foff, NULL_TREE);
6863 /* When va_start saves FPR arguments to the stack, each slot
6864 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6865 argument's precision. */
6866 rsize = UNITS_PER_HWFPVALUE;
6868 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6869 (= PARM_BOUNDARY bits). This can be different from RSIZE
6870 in two cases:
6872 (1) On 32-bit targets when TYPE is a structure such as:
6874 struct s { float f; };
6876 Such structures are passed in paired FPRs, so RSIZE
6877 will be 8 bytes. However, the structure only takes
6878 up 4 bytes of memory, so OSIZE will only be 4.
6880 (2) In combinations such as -mgp64 -msingle-float
6881 -fshort-double. Doubles passed in registers will then take
6882 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6883 stack take up UNITS_PER_WORD bytes. */
6884 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
6886 else
6888 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
6889 unshare_expr (valist), f_gtop, NULL_TREE);
6890 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
6891 unshare_expr (valist), f_goff, NULL_TREE);
6892 rsize = ROUND_UP (size, UNITS_PER_WORD);
6893 if (rsize > UNITS_PER_WORD)
6895 /* [1] Emit code for: off &= -rsize. */
6896 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6897 build_int_cst (TREE_TYPE (off), -rsize));
6898 gimplify_assign (unshare_expr (off), t, pre_p);
6900 osize = rsize;
6903 /* [2] Emit code to branch if off == 0. */
6904 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6905 build_int_cst (TREE_TYPE (off), 0));
6906 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6908 /* [5] Emit code for: off -= rsize. We do this as a form of
6909 post-decrement not available to C. */
6910 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6911 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6913 /* [4] Emit code for:
6914 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6915 t = fold_convert (sizetype, t);
6916 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6917 t = fold_build_pointer_plus (top, t);
6918 if (BYTES_BIG_ENDIAN && rsize > size)
6919 t = fold_build_pointer_plus_hwi (t, rsize - size);
6920 COND_EXPR_THEN (addr) = t;
6922 if (osize > UNITS_PER_WORD)
6924 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6925 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6926 u = build_int_cst (TREE_TYPE (t), -osize);
6927 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6928 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6929 unshare_expr (ovfl), t);
6931 else
6932 align = NULL;
6934 /* [10, 11] Emit code for:
6935 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6936 ovfl += osize. */
6937 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6938 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6939 if (BYTES_BIG_ENDIAN && osize > size)
6940 t = fold_build_pointer_plus_hwi (t, osize - size);
6942 /* String [9] and [10, 11] together. */
6943 if (align)
6944 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6945 COND_EXPR_ELSE (addr) = t;
6947 addr = fold_convert (build_pointer_type (type), addr);
6948 addr = build_va_arg_indirect_ref (addr);
6951 if (indirect_p)
6952 addr = build_va_arg_indirect_ref (addr);
6954 return addr;
6957 /* Declare a unique, locally-binding function called NAME, then start
6958 its definition. */
6960 static void
6961 mips_start_unique_function (const char *name)
6963 tree decl;
6965 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6966 get_identifier (name),
6967 build_function_type_list (void_type_node, NULL_TREE));
6968 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6969 NULL_TREE, void_type_node);
6970 TREE_PUBLIC (decl) = 1;
6971 TREE_STATIC (decl) = 1;
6973 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
6975 targetm.asm_out.unique_section (decl, 0);
6976 switch_to_section (get_named_section (decl, NULL, 0));
6978 targetm.asm_out.globalize_label (asm_out_file, name);
6979 fputs ("\t.hidden\t", asm_out_file);
6980 assemble_name (asm_out_file, name);
6981 putc ('\n', asm_out_file);
6984 /* Start a definition of function NAME. MIPS16_P indicates whether the
6985 function contains MIPS16 code. */
6987 static void
6988 mips_start_function_definition (const char *name, bool mips16_p)
6990 if (mips16_p)
6991 fprintf (asm_out_file, "\t.set\tmips16\n");
6992 else
6993 fprintf (asm_out_file, "\t.set\tnomips16\n");
6995 if (TARGET_MICROMIPS)
6996 fprintf (asm_out_file, "\t.set\tmicromips\n");
6997 #ifdef HAVE_GAS_MICROMIPS
6998 else
6999 fprintf (asm_out_file, "\t.set\tnomicromips\n");
7000 #endif
7002 if (!flag_inhibit_size_directive)
7004 fputs ("\t.ent\t", asm_out_file);
7005 assemble_name (asm_out_file, name);
7006 fputs ("\n", asm_out_file);
7009 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
7011 /* Start the definition proper. */
7012 assemble_name (asm_out_file, name);
7013 fputs (":\n", asm_out_file);
7016 /* End a function definition started by mips_start_function_definition. */
7018 static void
7019 mips_end_function_definition (const char *name)
7021 if (!flag_inhibit_size_directive)
7023 fputs ("\t.end\t", asm_out_file);
7024 assemble_name (asm_out_file, name);
7025 fputs ("\n", asm_out_file);
7029 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
7030 then free *STUB_PTR. */
7032 static void
7033 mips_finish_stub (mips_one_only_stub **stub_ptr)
7035 mips_one_only_stub *stub = *stub_ptr;
7036 if (!stub)
7037 return;
7039 const char *name = stub->get_name ();
7040 mips_start_unique_function (name);
7041 mips_start_function_definition (name, false);
7042 stub->output_body ();
7043 mips_end_function_definition (name);
7044 delete stub;
7045 *stub_ptr = 0;
7048 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
7050 static bool
7051 mips_ok_for_lazy_binding_p (rtx x)
7053 return (TARGET_USE_GOT
7054 && GET_CODE (x) == SYMBOL_REF
7055 && !SYMBOL_REF_BIND_NOW_P (x)
7056 && !mips_symbol_binds_local_p (x));
7059 /* Load function address ADDR into register DEST. TYPE is as for
7060 mips_expand_call. Return true if we used an explicit lazy-binding
7061 sequence. */
7063 static bool
7064 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
7066 /* If we're generating PIC, and this call is to a global function,
7067 try to allow its address to be resolved lazily. This isn't
7068 possible for sibcalls when $gp is call-saved because the value
7069 of $gp on entry to the stub would be our caller's gp, not ours. */
7070 if (TARGET_EXPLICIT_RELOCS
7071 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
7072 && mips_ok_for_lazy_binding_p (addr))
7074 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
7075 emit_insn (gen_rtx_SET (dest, addr));
7076 return true;
7078 else
7080 mips_emit_move (dest, addr);
7081 return false;
7085 /* Each locally-defined hard-float MIPS16 function has a local symbol
7086 associated with it. This hash table maps the function symbol (FUNC)
7087 to the local symbol (LOCAL). */
7088 static GTY (()) hash_map<nofree_string_hash, rtx> *mips16_local_aliases;
7090 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
7091 Return a local alias for it, creating a new one if necessary. */
7093 static rtx
7094 mips16_local_alias (rtx func)
7096 /* Create the hash table if this is the first call. */
7097 if (mips16_local_aliases == NULL)
7098 mips16_local_aliases = hash_map<nofree_string_hash, rtx>::create_ggc (37);
7100 /* Look up the function symbol, creating a new entry if need be. */
7101 bool existed;
7102 const char *func_name = XSTR (func, 0);
7103 rtx *slot = &mips16_local_aliases->get_or_insert (func_name, &existed);
7104 gcc_assert (slot != NULL);
7106 if (!existed)
7108 rtx local;
7110 /* Create a new SYMBOL_REF for the local symbol. The choice of
7111 __fn_local_* is based on the __fn_stub_* names that we've
7112 traditionally used for the non-MIPS16 stub. */
7113 func_name = targetm.strip_name_encoding (XSTR (func, 0));
7114 const char *local_name = ACONCAT (("__fn_local_", func_name, NULL));
7115 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
7116 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
7118 /* Create a new structure to represent the mapping. */
7119 *slot = local;
7121 return *slot;
7124 /* A chained list of functions for which mips16_build_call_stub has already
7125 generated a stub. NAME is the name of the function and FP_RET_P is true
7126 if the function returns a value in floating-point registers. */
7127 struct mips16_stub {
7128 struct mips16_stub *next;
7129 char *name;
7130 bool fp_ret_p;
7132 static struct mips16_stub *mips16_stubs;
7134 /* Return the two-character string that identifies floating-point
7135 return mode MODE in the name of a MIPS16 function stub. */
7137 static const char *
7138 mips16_call_stub_mode_suffix (machine_mode mode)
7140 if (mode == SFmode)
7141 return "sf";
7142 else if (mode == DFmode)
7143 return "df";
7144 else if (mode == SCmode)
7145 return "sc";
7146 else if (mode == DCmode)
7147 return "dc";
7148 else if (mode == V2SFmode)
7150 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT);
7151 return "df";
7153 else
7154 gcc_unreachable ();
7157 /* Write instructions to move a 32-bit value between general register
7158 GPREG and floating-point register FPREG. DIRECTION is 't' to move
7159 from GPREG to FPREG and 'f' to move in the opposite direction. */
7161 static void
7162 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
7164 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
7165 reg_names[gpreg], reg_names[fpreg]);
7168 /* Likewise for 64-bit values. */
7170 static void
7171 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
7173 if (TARGET_64BIT)
7174 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
7175 reg_names[gpreg], reg_names[fpreg]);
7176 else if (ISA_HAS_MXHC1)
7178 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
7179 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
7180 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
7181 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
7183 else if (TARGET_FLOATXX && direction == 't')
7185 /* Use the argument save area to move via memory. */
7186 fprintf (asm_out_file, "\tsw\t%s,0($sp)\n", reg_names[gpreg]);
7187 fprintf (asm_out_file, "\tsw\t%s,4($sp)\n", reg_names[gpreg + 1]);
7188 fprintf (asm_out_file, "\tldc1\t%s,0($sp)\n", reg_names[fpreg]);
7190 else if (TARGET_FLOATXX && direction == 'f')
7192 /* Use the argument save area to move via memory. */
7193 fprintf (asm_out_file, "\tsdc1\t%s,0($sp)\n", reg_names[fpreg]);
7194 fprintf (asm_out_file, "\tlw\t%s,0($sp)\n", reg_names[gpreg]);
7195 fprintf (asm_out_file, "\tlw\t%s,4($sp)\n", reg_names[gpreg + 1]);
7197 else
7199 /* Move the least-significant word. */
7200 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
7201 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
7202 /* ...then the most significant word. */
7203 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
7204 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
7208 /* Write out code to move floating-point arguments into or out of
7209 general registers. FP_CODE is the code describing which arguments
7210 are present (see the comment above the definition of CUMULATIVE_ARGS
7211 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
7213 static void
7214 mips_output_args_xfer (int fp_code, char direction)
7216 unsigned int gparg, fparg, f;
7217 CUMULATIVE_ARGS cum;
7219 /* This code only works for o32 and o64. */
7220 gcc_assert (TARGET_OLDABI);
7222 mips_init_cumulative_args (&cum, NULL);
7224 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7226 machine_mode mode;
7227 struct mips_arg_info info;
7229 if ((f & 3) == 1)
7230 mode = SFmode;
7231 else if ((f & 3) == 2)
7232 mode = DFmode;
7233 else
7234 gcc_unreachable ();
7236 mips_get_arg_info (&info, &cum, mode, NULL, true);
7237 gparg = mips_arg_regno (&info, false);
7238 fparg = mips_arg_regno (&info, true);
7240 if (mode == SFmode)
7241 mips_output_32bit_xfer (direction, gparg, fparg);
7242 else
7243 mips_output_64bit_xfer (direction, gparg, fparg);
7245 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
7249 /* Write a MIPS16 stub for the current function. This stub is used
7250 for functions which take arguments in the floating-point registers.
7251 It is normal-mode code that moves the floating-point arguments
7252 into the general registers and then jumps to the MIPS16 code. */
7254 static void
7255 mips16_build_function_stub (void)
7257 const char *fnname, *alias_name, *separator;
7258 char *secname, *stubname;
7259 tree stubdecl;
7260 unsigned int f;
7261 rtx symbol, alias;
7263 /* Create the name of the stub, and its unique section. */
7264 symbol = XEXP (DECL_RTL (current_function_decl), 0);
7265 alias = mips16_local_alias (symbol);
7267 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
7268 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
7269 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
7270 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
7272 /* Build a decl for the stub. */
7273 stubdecl = build_decl (BUILTINS_LOCATION,
7274 FUNCTION_DECL, get_identifier (stubname),
7275 build_function_type_list (void_type_node, NULL_TREE));
7276 set_decl_section_name (stubdecl, secname);
7277 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
7278 RESULT_DECL, NULL_TREE, void_type_node);
7280 /* Output a comment. */
7281 fprintf (asm_out_file, "\t# Stub function for %s (",
7282 current_function_name ());
7283 separator = "";
7284 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
7286 fprintf (asm_out_file, "%s%s", separator,
7287 (f & 3) == 1 ? "float" : "double");
7288 separator = ", ";
7290 fprintf (asm_out_file, ")\n");
7292 /* Start the function definition. */
7293 assemble_start_function (stubdecl, stubname);
7294 mips_start_function_definition (stubname, false);
7296 /* If generating pic2 code, either set up the global pointer or
7297 switch to pic0. */
7298 if (TARGET_ABICALLS_PIC2)
7300 if (TARGET_ABSOLUTE_ABICALLS)
7301 fprintf (asm_out_file, "\t.option\tpic0\n");
7302 else
7304 output_asm_insn ("%(.cpload\t%^%)", NULL);
7305 /* Emit an R_MIPS_NONE relocation to tell the linker what the
7306 target function is. Use a local GOT access when loading the
7307 symbol, to cut down on the number of unnecessary GOT entries
7308 for stubs that aren't needed. */
7309 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
7310 symbol = alias;
7314 /* Load the address of the MIPS16 function into $25. Do this first so
7315 that targets with coprocessor interlocks can use an MFC1 to fill the
7316 delay slot. */
7317 output_asm_insn ("la\t%^,%0", &symbol);
7319 /* Move the arguments from floating-point registers to general registers. */
7320 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
7322 /* Jump to the MIPS16 function. */
7323 output_asm_insn ("jr\t%^", NULL);
7325 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
7326 fprintf (asm_out_file, "\t.option\tpic2\n");
7328 mips_end_function_definition (stubname);
7330 /* If the linker needs to create a dynamic symbol for the target
7331 function, it will associate the symbol with the stub (which,
7332 unlike the target function, follows the proper calling conventions).
7333 It is therefore useful to have a local alias for the target function,
7334 so that it can still be identified as MIPS16 code. As an optimization,
7335 this symbol can also be used for indirect MIPS16 references from
7336 within this file. */
7337 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
7339 switch_to_section (function_section (current_function_decl));
7342 /* The current function is a MIPS16 function that returns a value in an FPR.
7343 Copy the return value from its soft-float to its hard-float location.
7344 libgcc2 has special non-MIPS16 helper functions for each case. */
7346 static void
7347 mips16_copy_fpr_return_value (void)
7349 rtx fn, insn, retval;
7350 tree return_type;
7351 machine_mode return_mode;
7352 const char *name;
7354 return_type = DECL_RESULT (current_function_decl);
7355 return_mode = DECL_MODE (return_type);
7357 name = ACONCAT (("__mips16_ret_",
7358 mips16_call_stub_mode_suffix (return_mode),
7359 NULL));
7360 fn = mips16_stub_function (name);
7362 /* The function takes arguments in $2 (and possibly $3), so calls
7363 to it cannot be lazily bound. */
7364 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
7366 /* Model the call as something that takes the GPR return value as
7367 argument and returns an "updated" value. */
7368 retval = gen_rtx_REG (return_mode, GP_RETURN);
7369 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
7370 const0_rtx, NULL_RTX, false);
7371 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
7374 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
7375 RETVAL is the location of the return value, or null if this is
7376 a "call" rather than a "call_value". ARGS_SIZE is the size of the
7377 arguments and FP_CODE is the code built by mips_function_arg;
7378 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
7380 There are three alternatives:
7382 - If a stub was needed, emit the call and return the call insn itself.
7384 - If we can avoid using a stub by redirecting the call, set *FN_PTR
7385 to the new target and return null.
7387 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
7388 unmodified.
7390 A stub is needed for calls to functions that, in normal mode,
7391 receive arguments in FPRs or return values in FPRs. The stub
7392 copies the arguments from their soft-float positions to their
7393 hard-float positions, calls the real function, then copies the
7394 return value from its hard-float position to its soft-float
7395 position.
7397 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
7398 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
7399 automatically redirects the JAL to the stub, otherwise the JAL
7400 continues to call FN directly. */
7402 static rtx_insn *
7403 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
7405 const char *fnname;
7406 bool fp_ret_p;
7407 struct mips16_stub *l;
7408 rtx_insn *insn;
7409 rtx pattern, fn;
7411 /* We don't need to do anything if we aren't in MIPS16 mode, or if
7412 we were invoked with the -msoft-float option. */
7413 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
7414 return NULL;
7416 /* Figure out whether the value might come back in a floating-point
7417 register. */
7418 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
7420 /* We don't need to do anything if there were no floating-point
7421 arguments and the value will not be returned in a floating-point
7422 register. */
7423 if (fp_code == 0 && !fp_ret_p)
7424 return NULL;
7426 /* We don't need to do anything if this is a call to a special
7427 MIPS16 support function. */
7428 fn = *fn_ptr;
7429 if (mips16_stub_function_p (fn))
7430 return NULL;
7432 /* If we're calling a locally-defined MIPS16 function, we know that
7433 it will return values in both the "soft-float" and "hard-float"
7434 registers. There is no need to use a stub to move the latter
7435 to the former. */
7436 if (fp_code == 0 && mips16_local_function_p (fn))
7437 return NULL;
7439 /* This code will only work for o32 and o64 abis. The other ABI's
7440 require more sophisticated support. */
7441 gcc_assert (TARGET_OLDABI);
7443 /* If we're calling via a function pointer, use one of the magic
7444 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
7445 Each stub expects the function address to arrive in register $2. */
7446 if (GET_CODE (fn) != SYMBOL_REF
7447 || !call_insn_operand (fn, VOIDmode))
7449 char buf[32];
7450 rtx stub_fn, addr;
7451 rtx_insn *insn;
7452 bool lazy_p;
7454 /* If this is a locally-defined and locally-binding function,
7455 avoid the stub by calling the local alias directly. */
7456 if (mips16_local_function_p (fn))
7458 *fn_ptr = mips16_local_alias (fn);
7459 return NULL;
7462 /* Create a SYMBOL_REF for the libgcc.a function. */
7463 if (fp_ret_p)
7464 sprintf (buf, "__mips16_call_stub_%s_%d",
7465 mips16_call_stub_mode_suffix (GET_MODE (retval)),
7466 fp_code);
7467 else
7468 sprintf (buf, "__mips16_call_stub_%d", fp_code);
7469 stub_fn = mips16_stub_function (buf);
7471 /* The function uses $2 as an argument, so calls to it
7472 cannot be lazily bound. */
7473 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
7475 /* Load the target function into $2. */
7476 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
7477 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
7479 /* Emit the call. */
7480 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
7481 args_size, NULL_RTX, lazy_p);
7483 /* Tell GCC that this call does indeed use the value of $2. */
7484 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
7486 /* If we are handling a floating-point return value, we need to
7487 save $18 in the function prologue. Putting a note on the
7488 call will mean that df_regs_ever_live_p ($18) will be true if the
7489 call is not eliminated, and we can check that in the prologue
7490 code. */
7491 if (fp_ret_p)
7492 CALL_INSN_FUNCTION_USAGE (insn) =
7493 gen_rtx_EXPR_LIST (VOIDmode,
7494 gen_rtx_CLOBBER (VOIDmode,
7495 gen_rtx_REG (word_mode, 18)),
7496 CALL_INSN_FUNCTION_USAGE (insn));
7498 return insn;
7501 /* We know the function we are going to call. If we have already
7502 built a stub, we don't need to do anything further. */
7503 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
7504 for (l = mips16_stubs; l != NULL; l = l->next)
7505 if (strcmp (l->name, fnname) == 0)
7506 break;
7508 if (l == NULL)
7510 const char *separator;
7511 char *secname, *stubname;
7512 tree stubid, stubdecl;
7513 unsigned int f;
7515 /* If the function does not return in FPRs, the special stub
7516 section is named
7517 .mips16.call.FNNAME
7519 If the function does return in FPRs, the stub section is named
7520 .mips16.call.fp.FNNAME
7522 Build a decl for the stub. */
7523 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
7524 fnname, NULL));
7525 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
7526 fnname, NULL));
7527 stubid = get_identifier (stubname);
7528 stubdecl = build_decl (BUILTINS_LOCATION,
7529 FUNCTION_DECL, stubid,
7530 build_function_type_list (void_type_node,
7531 NULL_TREE));
7532 set_decl_section_name (stubdecl, secname);
7533 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
7534 RESULT_DECL, NULL_TREE,
7535 void_type_node);
7537 /* Output a comment. */
7538 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7539 (fp_ret_p
7540 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7541 : ""),
7542 fnname);
7543 separator = "";
7544 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7546 fprintf (asm_out_file, "%s%s", separator,
7547 (f & 3) == 1 ? "float" : "double");
7548 separator = ", ";
7550 fprintf (asm_out_file, ")\n");
7552 /* Start the function definition. */
7553 assemble_start_function (stubdecl, stubname);
7554 mips_start_function_definition (stubname, false);
7556 if (fp_ret_p)
7558 fprintf (asm_out_file, "\t.cfi_startproc\n");
7560 /* Create a fake CFA 4 bytes below the stack pointer.
7561 This works around unwinders (like libgcc's) that expect
7562 the CFA for non-signal frames to be unique. */
7563 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
7565 /* "Save" $sp in itself so we don't use the fake CFA.
7566 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
7567 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
7569 /* Save the return address in $18. The stub's caller knows
7570 that $18 might be clobbered, even though $18 is usually
7571 a call-saved register.
7573 Do it early on in case the last move to a floating-point
7574 register can be scheduled into the delay slot of the
7575 call we are about to make. */
7576 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7577 reg_names[GP_REG_FIRST + 18],
7578 reg_names[RETURN_ADDR_REGNUM]);
7580 else
7582 /* Load the address of the MIPS16 function into $25. Do this
7583 first so that targets with coprocessor interlocks can use
7584 an MFC1 to fill the delay slot. */
7585 if (TARGET_EXPLICIT_RELOCS)
7587 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
7588 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
7590 else
7591 output_asm_insn ("la\t%^,%0", &fn);
7594 /* Move the arguments from general registers to floating-point
7595 registers. */
7596 mips_output_args_xfer (fp_code, 't');
7598 if (fp_ret_p)
7600 /* Now call the non-MIPS16 function. */
7601 output_asm_insn (mips_output_jump (&fn, 0, -1, true), &fn);
7602 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
7604 /* Move the result from floating-point registers to
7605 general registers. */
7606 switch (GET_MODE (retval))
7608 case SCmode:
7609 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
7610 TARGET_BIG_ENDIAN
7611 ? FP_REG_FIRST + 2
7612 : FP_REG_FIRST);
7613 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
7614 TARGET_LITTLE_ENDIAN
7615 ? FP_REG_FIRST + 2
7616 : FP_REG_FIRST);
7617 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
7619 /* On 64-bit targets, complex floats are returned in
7620 a single GPR, such that "sd" on a suitably-aligned
7621 target would store the value correctly. */
7622 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
7623 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
7624 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
7625 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
7626 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
7627 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
7628 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
7629 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
7630 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
7631 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
7632 reg_names[GP_RETURN],
7633 reg_names[GP_RETURN],
7634 reg_names[GP_RETURN + 1]);
7636 break;
7638 case SFmode:
7639 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
7640 break;
7642 case DCmode:
7643 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
7644 FP_REG_FIRST + 2);
7645 /* FALLTHRU */
7646 case DFmode:
7647 case V2SFmode:
7648 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
7649 || GET_MODE (retval) != V2SFmode);
7650 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
7651 break;
7653 default:
7654 gcc_unreachable ();
7656 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
7657 fprintf (asm_out_file, "\t.cfi_endproc\n");
7659 else
7661 /* Jump to the previously-loaded address. */
7662 output_asm_insn ("jr\t%^", NULL);
7665 #ifdef ASM_DECLARE_FUNCTION_SIZE
7666 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7667 #endif
7669 mips_end_function_definition (stubname);
7671 /* Record this stub. */
7672 l = XNEW (struct mips16_stub);
7673 l->name = xstrdup (fnname);
7674 l->fp_ret_p = fp_ret_p;
7675 l->next = mips16_stubs;
7676 mips16_stubs = l;
7679 /* If we expect a floating-point return value, but we've built a
7680 stub which does not expect one, then we're in trouble. We can't
7681 use the existing stub, because it won't handle the floating-point
7682 value. We can't build a new stub, because the linker won't know
7683 which stub to use for the various calls in this object file.
7684 Fortunately, this case is illegal, since it means that a function
7685 was declared in two different ways in a single compilation. */
7686 if (fp_ret_p && !l->fp_ret_p)
7687 error ("cannot handle inconsistent calls to %qs", fnname);
7689 if (retval == NULL_RTX)
7690 pattern = gen_call_internal_direct (fn, args_size);
7691 else
7692 pattern = gen_call_value_internal_direct (retval, fn, args_size);
7693 insn = mips_emit_call_insn (pattern, fn, fn, false);
7695 /* If we are calling a stub which handles a floating-point return
7696 value, we need to arrange to save $18 in the prologue. We do this
7697 by marking the function call as using the register. The prologue
7698 will later see that it is used, and emit code to save it. */
7699 if (fp_ret_p)
7700 CALL_INSN_FUNCTION_USAGE (insn) =
7701 gen_rtx_EXPR_LIST (VOIDmode,
7702 gen_rtx_CLOBBER (VOIDmode,
7703 gen_rtx_REG (word_mode, 18)),
7704 CALL_INSN_FUNCTION_USAGE (insn));
7706 return insn;
7709 /* Expand a call of type TYPE. RESULT is where the result will go (null
7710 for "call"s and "sibcall"s), ADDR is the address of the function,
7711 ARGS_SIZE is the size of the arguments and AUX is the value passed
7712 to us by mips_function_arg. LAZY_P is true if this call already
7713 involves a lazily-bound function address (such as when calling
7714 functions through a MIPS16 hard-float stub).
7716 Return the call itself. */
7718 rtx_insn *
7719 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
7720 rtx args_size, rtx aux, bool lazy_p)
7722 rtx orig_addr, pattern;
7723 rtx_insn *insn;
7724 int fp_code;
7726 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
7727 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
7728 if (insn)
7730 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
7731 return insn;
7734 orig_addr = addr;
7735 if (!call_insn_operand (addr, VOIDmode))
7737 if (type == MIPS_CALL_EPILOGUE)
7738 addr = MIPS_EPILOGUE_TEMP (Pmode);
7739 else
7740 addr = gen_reg_rtx (Pmode);
7741 lazy_p |= mips_load_call_address (type, addr, orig_addr);
7744 if (result == 0)
7746 rtx (*fn) (rtx, rtx);
7748 if (type == MIPS_CALL_SIBCALL)
7749 fn = gen_sibcall_internal;
7750 else
7751 fn = gen_call_internal;
7753 pattern = fn (addr, args_size);
7755 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
7757 /* Handle return values created by mips_return_fpr_pair. */
7758 rtx (*fn) (rtx, rtx, rtx, rtx);
7759 rtx reg1, reg2;
7761 if (type == MIPS_CALL_SIBCALL)
7762 fn = gen_sibcall_value_multiple_internal;
7763 else
7764 fn = gen_call_value_multiple_internal;
7766 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
7767 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
7768 pattern = fn (reg1, addr, args_size, reg2);
7770 else
7772 rtx (*fn) (rtx, rtx, rtx);
7774 if (type == MIPS_CALL_SIBCALL)
7775 fn = gen_sibcall_value_internal;
7776 else
7777 fn = gen_call_value_internal;
7779 /* Handle return values created by mips_return_fpr_single. */
7780 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
7781 result = XEXP (XVECEXP (result, 0, 0), 0);
7782 pattern = fn (result, addr, args_size);
7785 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
7788 /* Split call instruction INSN into a $gp-clobbering call and
7789 (where necessary) an instruction to restore $gp from its save slot.
7790 CALL_PATTERN is the pattern of the new call. */
7792 void
7793 mips_split_call (rtx insn, rtx call_pattern)
7795 emit_call_insn (call_pattern);
7796 if (!find_reg_note (insn, REG_NORETURN, 0))
7797 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode,
7798 POST_CALL_TMP_REG));
7801 /* Return true if a call to DECL may need to use JALX. */
7803 static bool
7804 mips_call_may_need_jalx_p (tree decl)
7806 /* If the current translation unit would use a different mode for DECL,
7807 assume that the call needs JALX. */
7808 if (mips_get_compress_mode (decl) != TARGET_COMPRESSION)
7809 return true;
7811 /* mips_get_compress_mode is always accurate for locally-binding
7812 functions in the current translation unit. */
7813 if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl))
7814 return false;
7816 /* When -minterlink-compressed is in effect, assume that functions
7817 could use a different encoding mode unless an attribute explicitly
7818 tells us otherwise. */
7819 if (TARGET_INTERLINK_COMPRESSED)
7821 if (!TARGET_COMPRESSION
7822 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0)
7823 return true;
7824 if (TARGET_COMPRESSION
7825 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0)
7826 return true;
7829 return false;
7832 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7834 static bool
7835 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7837 if (!TARGET_SIBCALLS)
7838 return false;
7840 /* Interrupt handlers need special epilogue code and therefore can't
7841 use sibcalls. */
7842 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
7843 return false;
7845 /* Direct Js are only possible to functions that use the same ISA encoding.
7846 There is no JX counterpoart of JALX. */
7847 if (decl
7848 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)
7849 && mips_call_may_need_jalx_p (decl))
7850 return false;
7852 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7853 require $gp to be valid on entry, so sibcalls can only use stubs
7854 if $gp is call-clobbered. */
7855 if (decl
7856 && TARGET_CALL_SAVED_GP
7857 && !TARGET_ABICALLS_PIC0
7858 && !targetm.binds_local_p (decl))
7859 return false;
7861 /* Otherwise OK. */
7862 return true;
7865 /* Implement TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7867 bool
7868 mips_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
7869 unsigned int align,
7870 enum by_pieces_operation op,
7871 bool speed_p)
7873 if (op == STORE_BY_PIECES)
7874 return mips_store_by_pieces_p (size, align);
7875 if (op == MOVE_BY_PIECES && HAVE_movmemsi)
7877 /* movmemsi is meant to generate code that is at least as good as
7878 move_by_pieces. However, movmemsi effectively uses a by-pieces
7879 implementation both for moves smaller than a word and for
7880 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7881 bytes. We should allow the tree-level optimisers to do such
7882 moves by pieces, as it often exposes other optimization
7883 opportunities. We might as well continue to use movmemsi at
7884 the rtl level though, as it produces better code when
7885 scheduling is disabled (such as at -O). */
7886 if (currently_expanding_to_rtl)
7887 return false;
7888 if (align < BITS_PER_WORD)
7889 return size < UNITS_PER_WORD;
7890 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
7893 return default_use_by_pieces_infrastructure_p (size, align, op, speed_p);
7896 /* Implement a handler for STORE_BY_PIECES operations
7897 for TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7899 bool
7900 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7902 /* Storing by pieces involves moving constants into registers
7903 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7904 We need to decide whether it is cheaper to load the address of
7905 constant data into a register and use a block move instead. */
7907 /* If the data is only byte aligned, then:
7909 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7910 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7911 instead.
7913 (a2) A block move of 4 bytes from aligned source data can use an
7914 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7915 4 SBs that we would generate when storing by pieces. */
7916 if (align <= BITS_PER_UNIT)
7917 return size < 4;
7919 /* If the data is 2-byte aligned, then:
7921 (b1) A block move of less than 4 bytes would use a combination of LBs,
7922 LHs, SBs and SHs. We get better code by using single-instruction
7923 LIs, SBs and SHs instead.
7925 (b2) A block move of 4 bytes from aligned source data would again use
7926 an LW/SWL/SWR sequence. In most cases, loading the address of
7927 the source data would require at least one extra instruction.
7928 It is often more efficient to use 2 single-instruction LIs and
7929 2 SHs instead.
7931 (b3) A block move of up to 3 additional bytes would be like (b1).
7933 (b4) A block move of 8 bytes from aligned source data can use two
7934 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7935 sequences are better than the 4 LIs and 4 SHs that we'd generate
7936 when storing by pieces.
7938 The reasoning for higher alignments is similar:
7940 (c1) A block move of less than 4 bytes would be the same as (b1).
7942 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7943 loading the address of the source data would typically require
7944 at least one extra instruction. It is generally better to use
7945 LUI/ORI/SW instead.
7947 (c3) A block move of up to 3 additional bytes would be like (b1).
7949 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7950 LD/SD sequence, and in these cases we've traditionally preferred
7951 the memory copy over the more bulky constant moves. */
7952 return size < 8;
7955 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7956 Assume that the areas do not overlap. */
7958 static void
7959 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7961 HOST_WIDE_INT offset, delta;
7962 unsigned HOST_WIDE_INT bits;
7963 int i;
7964 machine_mode mode;
7965 rtx *regs;
7967 /* Work out how many bits to move at a time. If both operands have
7968 half-word alignment, it is usually better to move in half words.
7969 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7970 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7971 Otherwise move word-sized chunks.
7973 For ISA_HAS_LWL_LWR we rely on the lwl/lwr & swl/swr load. Otherwise
7974 picking the minimum of alignment or BITS_PER_WORD gets us the
7975 desired size for bits. */
7977 if (!ISA_HAS_LWL_LWR)
7978 bits = MIN (BITS_PER_WORD, MIN (MEM_ALIGN (src), MEM_ALIGN (dest)));
7979 else
7981 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7982 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7983 bits = BITS_PER_WORD / 2;
7984 else
7985 bits = BITS_PER_WORD;
7988 mode = mode_for_size (bits, MODE_INT, 0);
7989 delta = bits / BITS_PER_UNIT;
7991 /* Allocate a buffer for the temporary registers. */
7992 regs = XALLOCAVEC (rtx, length / delta);
7994 /* Load as many BITS-sized chunks as possible. Use a normal load if
7995 the source has enough alignment, otherwise use left/right pairs. */
7996 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7998 regs[i] = gen_reg_rtx (mode);
7999 if (MEM_ALIGN (src) >= bits)
8000 mips_emit_move (regs[i], adjust_address (src, mode, offset));
8001 else
8003 rtx part = adjust_address (src, BLKmode, offset);
8004 set_mem_size (part, delta);
8005 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
8006 gcc_unreachable ();
8010 /* Copy the chunks to the destination. */
8011 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
8012 if (MEM_ALIGN (dest) >= bits)
8013 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
8014 else
8016 rtx part = adjust_address (dest, BLKmode, offset);
8017 set_mem_size (part, delta);
8018 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
8019 gcc_unreachable ();
8022 /* Mop up any left-over bytes. */
8023 if (offset < length)
8025 src = adjust_address (src, BLKmode, offset);
8026 dest = adjust_address (dest, BLKmode, offset);
8027 move_by_pieces (dest, src, length - offset,
8028 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
8032 /* Helper function for doing a loop-based block operation on memory
8033 reference MEM. Each iteration of the loop will operate on LENGTH
8034 bytes of MEM.
8036 Create a new base register for use within the loop and point it to
8037 the start of MEM. Create a new memory reference that uses this
8038 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
8040 static void
8041 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
8042 rtx *loop_reg, rtx *loop_mem)
8044 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
8046 /* Although the new mem does not refer to a known location,
8047 it does keep up to LENGTH bytes of alignment. */
8048 *loop_mem = change_address (mem, BLKmode, *loop_reg);
8049 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
8052 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
8053 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
8054 the memory regions do not overlap. */
8056 static void
8057 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
8058 HOST_WIDE_INT bytes_per_iter)
8060 rtx_code_label *label;
8061 rtx src_reg, dest_reg, final_src, test;
8062 HOST_WIDE_INT leftover;
8064 leftover = length % bytes_per_iter;
8065 length -= leftover;
8067 /* Create registers and memory references for use within the loop. */
8068 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
8069 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
8071 /* Calculate the value that SRC_REG should have after the last iteration
8072 of the loop. */
8073 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
8074 0, 0, OPTAB_WIDEN);
8076 /* Emit the start of the loop. */
8077 label = gen_label_rtx ();
8078 emit_label (label);
8080 /* Emit the loop body. */
8081 mips_block_move_straight (dest, src, bytes_per_iter);
8083 /* Move on to the next block. */
8084 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
8085 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
8087 /* Emit the loop condition. */
8088 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
8089 if (Pmode == DImode)
8090 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
8091 else
8092 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
8094 /* Mop up any left-over bytes. */
8095 if (leftover)
8096 mips_block_move_straight (dest, src, leftover);
8099 /* Expand a movmemsi instruction, which copies LENGTH bytes from
8100 memory reference SRC to memory reference DEST. */
8102 bool
8103 mips_expand_block_move (rtx dest, rtx src, rtx length)
8105 if (!ISA_HAS_LWL_LWR
8106 && (MEM_ALIGN (src) < MIPS_MIN_MOVE_MEM_ALIGN
8107 || MEM_ALIGN (dest) < MIPS_MIN_MOVE_MEM_ALIGN))
8108 return false;
8110 if (CONST_INT_P (length))
8112 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
8114 mips_block_move_straight (dest, src, INTVAL (length));
8115 return true;
8117 else if (optimize)
8119 mips_block_move_loop (dest, src, INTVAL (length),
8120 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
8121 return true;
8124 return false;
8127 /* Expand a loop of synci insns for the address range [BEGIN, END). */
8129 void
8130 mips_expand_synci_loop (rtx begin, rtx end)
8132 rtx inc, cmp_result, mask, length;
8133 rtx_code_label *label, *end_label;
8135 /* Create end_label. */
8136 end_label = gen_label_rtx ();
8138 /* Check if begin equals end. */
8139 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
8140 emit_jump_insn (gen_condjump (cmp_result, end_label));
8142 /* Load INC with the cache line size (rdhwr INC,$1). */
8143 inc = gen_reg_rtx (Pmode);
8144 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
8146 /* Check if inc is 0. */
8147 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
8148 emit_jump_insn (gen_condjump (cmp_result, end_label));
8150 /* Calculate mask. */
8151 mask = mips_force_unary (Pmode, NEG, inc);
8153 /* Mask out begin by mask. */
8154 begin = mips_force_binary (Pmode, AND, begin, mask);
8156 /* Calculate length. */
8157 length = mips_force_binary (Pmode, MINUS, end, begin);
8159 /* Loop back to here. */
8160 label = gen_label_rtx ();
8161 emit_label (label);
8163 emit_insn (gen_synci (begin));
8165 /* Update length. */
8166 mips_emit_binary (MINUS, length, length, inc);
8168 /* Update begin. */
8169 mips_emit_binary (PLUS, begin, begin, inc);
8171 /* Check if length is greater than 0. */
8172 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
8173 emit_jump_insn (gen_condjump (cmp_result, label));
8175 emit_label (end_label);
8178 /* Expand a QI or HI mode atomic memory operation.
8180 GENERATOR contains a pointer to the gen_* function that generates
8181 the SI mode underlying atomic operation using masks that we
8182 calculate.
8184 RESULT is the return register for the operation. Its value is NULL
8185 if unused.
8187 MEM is the location of the atomic access.
8189 OLDVAL is the first operand for the operation.
8191 NEWVAL is the optional second operand for the operation. Its value
8192 is NULL if unused. */
8194 void
8195 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
8196 rtx result, rtx mem, rtx oldval, rtx newval)
8198 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
8199 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
8200 rtx res = NULL;
8201 machine_mode mode;
8203 mode = GET_MODE (mem);
8205 /* Compute the address of the containing SImode value. */
8206 orig_addr = force_reg (Pmode, XEXP (mem, 0));
8207 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
8208 force_reg (Pmode, GEN_INT (-4)));
8210 /* Create a memory reference for it. */
8211 memsi = gen_rtx_MEM (SImode, memsi_addr);
8212 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
8213 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
8215 /* Work out the byte offset of the QImode or HImode value,
8216 counting from the least significant byte. */
8217 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
8218 if (TARGET_BIG_ENDIAN)
8219 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
8221 /* Multiply by eight to convert the shift value from bytes to bits. */
8222 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
8224 /* Make the final shift an SImode value, so that it can be used in
8225 SImode operations. */
8226 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
8228 /* Set MASK to an inclusive mask of the QImode or HImode value. */
8229 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
8230 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
8231 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
8233 /* Compute the equivalent exclusive mask. */
8234 inverted_mask = gen_reg_rtx (SImode);
8235 emit_insn (gen_rtx_SET (inverted_mask, gen_rtx_NOT (SImode, mask)));
8237 /* Shift the old value into place. */
8238 if (oldval != const0_rtx)
8240 oldval = convert_modes (SImode, mode, oldval, true);
8241 oldval = force_reg (SImode, oldval);
8242 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
8245 /* Do the same for the new value. */
8246 if (newval && newval != const0_rtx)
8248 newval = convert_modes (SImode, mode, newval, true);
8249 newval = force_reg (SImode, newval);
8250 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
8253 /* Do the SImode atomic access. */
8254 if (result)
8255 res = gen_reg_rtx (SImode);
8256 if (newval)
8257 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
8258 else if (result)
8259 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
8260 else
8261 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
8263 emit_insn (si_op);
8265 if (result)
8267 /* Shift and convert the result. */
8268 mips_emit_binary (AND, res, res, mask);
8269 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
8270 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
8274 /* Return true if it is possible to use left/right accesses for a
8275 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
8276 When returning true, update *LEFT and *RIGHT as follows:
8278 *LEFT is a QImode reference to the first byte if big endian or
8279 the last byte if little endian. This address can be used in the
8280 left-side instructions (LWL, SWL, LDL, SDL).
8282 *RIGHT is a QImode reference to the opposite end of the field and
8283 can be used in the patterning right-side instruction. */
8285 static bool
8286 mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
8287 rtx *left, rtx *right)
8289 rtx first, last;
8291 /* Check that the size is valid. */
8292 if (width != 32 && (!TARGET_64BIT || width != 64))
8293 return false;
8295 /* We can only access byte-aligned values. Since we are always passed
8296 a reference to the first byte of the field, it is not necessary to
8297 do anything with BITPOS after this check. */
8298 if (bitpos % BITS_PER_UNIT != 0)
8299 return false;
8301 /* Reject aligned bitfields: we want to use a normal load or store
8302 instead of a left/right pair. */
8303 if (MEM_ALIGN (op) >= width)
8304 return false;
8306 /* Get references to both ends of the field. */
8307 first = adjust_address (op, QImode, 0);
8308 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
8310 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
8311 correspond to the MSB and RIGHT to the LSB. */
8312 if (TARGET_BIG_ENDIAN)
8313 *left = first, *right = last;
8314 else
8315 *left = last, *right = first;
8317 return true;
8320 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
8321 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
8322 the operation is the equivalent of:
8324 (set DEST (*_extract SRC WIDTH BITPOS))
8326 Return true on success. */
8328 bool
8329 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
8330 HOST_WIDE_INT bitpos, bool unsigned_p)
8332 rtx left, right, temp;
8333 rtx dest1 = NULL_RTX;
8335 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
8336 be a DImode, create a new temp and emit a zero extend at the end. */
8337 if (GET_MODE (dest) == DImode
8338 && REG_P (dest)
8339 && GET_MODE_BITSIZE (SImode) == width)
8341 dest1 = dest;
8342 dest = gen_reg_rtx (SImode);
8345 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
8346 return false;
8348 temp = gen_reg_rtx (GET_MODE (dest));
8349 if (GET_MODE (dest) == DImode)
8351 emit_insn (gen_mov_ldl (temp, src, left));
8352 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
8354 else
8356 emit_insn (gen_mov_lwl (temp, src, left));
8357 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
8360 /* If we were loading 32bits and the original register was DI then
8361 sign/zero extend into the orignal dest. */
8362 if (dest1)
8364 if (unsigned_p)
8365 emit_insn (gen_zero_extendsidi2 (dest1, dest));
8366 else
8367 emit_insn (gen_extendsidi2 (dest1, dest));
8369 return true;
8372 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
8373 BITPOS and SRC are the operands passed to the expander; the operation
8374 is the equivalent of:
8376 (set (zero_extract DEST WIDTH BITPOS) SRC)
8378 Return true on success. */
8380 bool
8381 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
8382 HOST_WIDE_INT bitpos)
8384 rtx left, right;
8385 machine_mode mode;
8387 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
8388 return false;
8390 mode = mode_for_size (width, MODE_INT, 0);
8391 src = gen_lowpart (mode, src);
8392 if (mode == DImode)
8394 emit_insn (gen_mov_sdl (dest, src, left));
8395 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
8397 else
8399 emit_insn (gen_mov_swl (dest, src, left));
8400 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
8402 return true;
8405 /* Return true if X is a MEM with the same size as MODE. */
8407 bool
8408 mips_mem_fits_mode_p (machine_mode mode, rtx x)
8410 return (MEM_P (x)
8411 && MEM_SIZE_KNOWN_P (x)
8412 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
8415 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
8416 source of an "ext" instruction or the destination of an "ins"
8417 instruction. OP must be a register operand and the following
8418 conditions must hold:
8420 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
8421 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
8422 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
8424 Also reject lengths equal to a word as they are better handled
8425 by the move patterns. */
8427 bool
8428 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
8430 if (!ISA_HAS_EXT_INS
8431 || !register_operand (op, VOIDmode)
8432 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
8433 return false;
8435 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
8436 return false;
8438 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
8439 return false;
8441 return true;
8444 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
8445 operation if MAXLEN is the maxium length of consecutive bits that
8446 can make up MASK. MODE is the mode of the operation. See
8447 mask_low_and_shift_len for the actual definition. */
8449 bool
8450 mask_low_and_shift_p (machine_mode mode, rtx mask, rtx shift, int maxlen)
8452 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
8455 /* Return true iff OP1 and OP2 are valid operands together for the
8456 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
8457 see the table in the comment before the pattern. */
8459 bool
8460 and_operands_ok (machine_mode mode, rtx op1, rtx op2)
8463 if (memory_operand (op1, mode))
8465 if (TARGET_MIPS16) {
8466 struct mips_address_info addr;
8467 if (!mips_classify_address (&addr, op1, mode, false))
8468 return false;
8470 return and_load_operand (op2, mode);
8472 else
8473 return and_reg_operand (op2, mode);
8476 /* The canonical form of a mask-low-and-shift-left operation is
8477 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
8478 cleared. Thus we need to shift MASK to the right before checking if it
8479 is a valid mask value. MODE is the mode of the operation. If true
8480 return the length of the mask, otherwise return -1. */
8483 mask_low_and_shift_len (machine_mode mode, rtx mask, rtx shift)
8485 HOST_WIDE_INT shval;
8487 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
8488 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
8491 /* Return true if -msplit-addresses is selected and should be honored.
8493 -msplit-addresses is a half-way house between explicit relocations
8494 and the traditional assembler macros. It can split absolute 32-bit
8495 symbolic constants into a high/lo_sum pair but uses macros for other
8496 sorts of access.
8498 Like explicit relocation support for REL targets, it relies
8499 on GNU extensions in the assembler and the linker.
8501 Although this code should work for -O0, it has traditionally
8502 been treated as an optimization. */
8504 static bool
8505 mips_split_addresses_p (void)
8507 return (TARGET_SPLIT_ADDRESSES
8508 && optimize
8509 && !TARGET_MIPS16
8510 && !flag_pic
8511 && !ABI_HAS_64BIT_SYMBOLS);
8514 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
8516 static void
8517 mips_init_relocs (void)
8519 memset (mips_split_p, '\0', sizeof (mips_split_p));
8520 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
8521 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
8522 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
8523 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
8525 if (TARGET_MIPS16_PCREL_LOADS)
8526 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
8527 else
8529 if (ABI_HAS_64BIT_SYMBOLS)
8531 if (TARGET_EXPLICIT_RELOCS)
8533 mips_split_p[SYMBOL_64_HIGH] = true;
8534 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
8535 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
8537 mips_split_p[SYMBOL_64_MID] = true;
8538 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
8539 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
8541 mips_split_p[SYMBOL_64_LOW] = true;
8542 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
8543 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
8545 mips_split_p[SYMBOL_ABSOLUTE] = true;
8546 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
8549 else
8551 if (TARGET_EXPLICIT_RELOCS
8552 || mips_split_addresses_p ()
8553 || TARGET_MIPS16)
8555 mips_split_p[SYMBOL_ABSOLUTE] = true;
8556 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
8557 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
8562 if (TARGET_MIPS16)
8564 /* The high part is provided by a pseudo copy of $gp. */
8565 mips_split_p[SYMBOL_GP_RELATIVE] = true;
8566 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
8568 else if (TARGET_EXPLICIT_RELOCS)
8569 /* Small data constants are kept whole until after reload,
8570 then lowered by mips_rewrite_small_data. */
8571 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
8573 if (TARGET_EXPLICIT_RELOCS)
8575 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
8576 if (TARGET_NEWABI)
8578 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
8579 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
8581 else
8583 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
8584 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
8586 if (TARGET_MIPS16)
8587 /* Expose the use of $28 as soon as possible. */
8588 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
8590 if (TARGET_XGOT)
8592 /* The HIGH and LO_SUM are matched by special .md patterns. */
8593 mips_split_p[SYMBOL_GOT_DISP] = true;
8595 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
8596 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
8597 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
8599 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
8600 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
8601 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
8603 else
8605 if (TARGET_NEWABI)
8606 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
8607 else
8608 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
8609 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
8610 if (TARGET_MIPS16)
8611 /* Expose the use of $28 as soon as possible. */
8612 mips_split_p[SYMBOL_GOT_DISP] = true;
8616 if (TARGET_NEWABI)
8618 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
8619 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
8620 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
8623 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
8624 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
8626 if (TARGET_MIPS16_PCREL_LOADS)
8628 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
8629 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
8631 else
8633 mips_split_p[SYMBOL_DTPREL] = true;
8634 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
8635 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
8637 mips_split_p[SYMBOL_TPREL] = true;
8638 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
8639 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
8642 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
8643 mips_lo_relocs[SYMBOL_HALF] = "%half(";
8646 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
8647 in context CONTEXT. RELOCS is the array of relocations to use. */
8649 static void
8650 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
8651 const char **relocs)
8653 enum mips_symbol_type symbol_type;
8654 const char *p;
8656 symbol_type = mips_classify_symbolic_expression (op, context);
8657 gcc_assert (relocs[symbol_type]);
8659 fputs (relocs[symbol_type], file);
8660 output_addr_const (file, mips_strip_unspec_address (op));
8661 for (p = relocs[symbol_type]; *p != 0; p++)
8662 if (*p == '(')
8663 fputc (')', file);
8666 /* Start a new block with the given asm switch enabled. If we need
8667 to print a directive, emit PREFIX before it and SUFFIX after it. */
8669 static void
8670 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
8671 const char *prefix, const char *suffix)
8673 if (asm_switch->nesting_level == 0)
8674 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
8675 asm_switch->nesting_level++;
8678 /* Likewise, but end a block. */
8680 static void
8681 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
8682 const char *prefix, const char *suffix)
8684 gcc_assert (asm_switch->nesting_level);
8685 asm_switch->nesting_level--;
8686 if (asm_switch->nesting_level == 0)
8687 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
8690 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
8691 that either print a complete line or print nothing. */
8693 void
8694 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
8696 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
8699 void
8700 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
8702 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
8705 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8706 The punctuation characters are:
8708 '(' Start a nested ".set noreorder" block.
8709 ')' End a nested ".set noreorder" block.
8710 '[' Start a nested ".set noat" block.
8711 ']' End a nested ".set noat" block.
8712 '<' Start a nested ".set nomacro" block.
8713 '>' End a nested ".set nomacro" block.
8714 '*' Behave like %(%< if generating a delayed-branch sequence.
8715 '#' Print a nop if in a ".set noreorder" block.
8716 '/' Like '#', but do nothing within a delayed-branch sequence.
8717 '?' Print "l" if mips_branch_likely is true
8718 '~' Print a nop if mips_branch_likely is true
8719 '.' Print the name of the register with a hard-wired zero (zero or $0).
8720 '@' Print the name of the assembler temporary register (at or $1).
8721 '^' Print the name of the pic call-through register (t9 or $25).
8722 '+' Print the name of the gp register (usually gp or $28).
8723 '$' Print the name of the stack pointer register (sp or $29).
8724 ':' Print "c" to use the compact version if the delay slot is a nop.
8725 '!' Print "s" to use the short version if the delay slot contains a
8726 16-bit instruction.
8728 See also mips_init_print_operand_punct. */
8730 static void
8731 mips_print_operand_punctuation (FILE *file, int ch)
8733 switch (ch)
8735 case '(':
8736 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
8737 break;
8739 case ')':
8740 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
8741 break;
8743 case '[':
8744 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
8745 break;
8747 case ']':
8748 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
8749 break;
8751 case '<':
8752 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
8753 break;
8755 case '>':
8756 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
8757 break;
8759 case '*':
8760 if (final_sequence != 0)
8762 mips_print_operand_punctuation (file, '(');
8763 mips_print_operand_punctuation (file, '<');
8765 break;
8767 case '#':
8768 if (mips_noreorder.nesting_level > 0)
8769 fputs ("\n\tnop", file);
8770 break;
8772 case '/':
8773 /* Print an extra newline so that the delayed insn is separated
8774 from the following ones. This looks neater and is consistent
8775 with non-nop delayed sequences. */
8776 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
8777 fputs ("\n\tnop\n", file);
8778 break;
8780 case '?':
8781 if (mips_branch_likely)
8782 putc ('l', file);
8783 break;
8785 case '~':
8786 if (mips_branch_likely)
8787 fputs ("\n\tnop", file);
8788 break;
8790 case '.':
8791 fputs (reg_names[GP_REG_FIRST + 0], file);
8792 break;
8794 case '@':
8795 fputs (reg_names[AT_REGNUM], file);
8796 break;
8798 case '^':
8799 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
8800 break;
8802 case '+':
8803 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
8804 break;
8806 case '$':
8807 fputs (reg_names[STACK_POINTER_REGNUM], file);
8808 break;
8810 case ':':
8811 /* When final_sequence is 0, the delay slot will be a nop. We can
8812 use the compact version where available. The %: formatter will
8813 only be present if a compact form of the branch is available. */
8814 if (final_sequence == 0)
8815 putc ('c', file);
8816 break;
8818 case '!':
8819 /* If the delay slot instruction is short, then use the
8820 compact version. */
8821 if (TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED && mips_isa_rev <= 5
8822 && (final_sequence == 0
8823 || get_attr_length (final_sequence->insn (1)) == 2))
8824 putc ('s', file);
8825 break;
8827 default:
8828 gcc_unreachable ();
8829 break;
8833 /* Initialize mips_print_operand_punct. */
8835 static void
8836 mips_init_print_operand_punct (void)
8838 const char *p;
8840 for (p = "()[]<>*#/?~.@^+$:!"; *p; p++)
8841 mips_print_operand_punct[(unsigned char) *p] = true;
8844 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8845 associated with condition CODE. Print the condition part of the
8846 opcode to FILE. */
8848 static void
8849 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
8851 switch (code)
8853 case EQ:
8854 case NE:
8855 case GT:
8856 case GE:
8857 case LT:
8858 case LE:
8859 case GTU:
8860 case GEU:
8861 case LTU:
8862 case LEU:
8863 /* Conveniently, the MIPS names for these conditions are the same
8864 as their RTL equivalents. */
8865 fputs (GET_RTX_NAME (code), file);
8866 break;
8868 default:
8869 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8870 break;
8874 /* Likewise floating-point branches. */
8876 static void
8877 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
8879 switch (code)
8881 case EQ:
8882 if (ISA_HAS_CCF)
8883 fputs ("c1eqz", file);
8884 else
8885 fputs ("c1f", file);
8886 break;
8888 case NE:
8889 if (ISA_HAS_CCF)
8890 fputs ("c1nez", file);
8891 else
8892 fputs ("c1t", file);
8893 break;
8895 default:
8896 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8897 break;
8901 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8903 static bool
8904 mips_print_operand_punct_valid_p (unsigned char code)
8906 return mips_print_operand_punct[code];
8909 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8911 'E' Print CONST_INT OP element 0 of a replicated CONST_VECTOR in decimal.
8912 'X' Print CONST_INT OP in hexadecimal format.
8913 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8914 'd' Print CONST_INT OP in decimal.
8915 'B' Print CONST_INT OP element 0 of a replicated CONST_VECTOR
8916 as an unsigned byte [0..255].
8917 'm' Print one less than CONST_INT OP in decimal.
8918 'y' Print exact log2 of CONST_INT OP in decimal.
8919 'h' Print the high-part relocation associated with OP, after stripping
8920 any outermost HIGH.
8921 'R' Print the low-part relocation associated with OP.
8922 'C' Print the integer branch condition for comparison OP.
8923 'N' Print the inverse of the integer branch condition for comparison OP.
8924 'F' Print the FPU branch condition for comparison OP.
8925 'W' Print the inverse of the FPU branch condition for comparison OP.
8926 'w' Print a MSA register.
8927 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8928 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8929 't' Like 'T', but with the EQ/NE cases reversed
8930 'Y' Print mips_fp_conditions[INTVAL (OP)]
8931 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8932 'q' Print a DSP accumulator register.
8933 'D' Print the second part of a double-word register or memory operand.
8934 'L' Print the low-order register in a double-word register operand.
8935 'M' Print high-order register in a double-word register operand.
8936 'z' Print $0 if OP is zero, otherwise print OP normally.
8937 'b' Print the address of a memory operand, without offset.
8938 'v' Print the insn size suffix b, h, w or d for vector modes V16QI, V8HI,
8939 V4SI, V2SI, and w, d for vector modes V4SF, V2DF respectively.
8940 'V' Print exact log2 of CONST_INT OP element 0 of a replicated
8941 CONST_VECTOR in decimal. */
8943 static void
8944 mips_print_operand (FILE *file, rtx op, int letter)
8946 enum rtx_code code;
8948 if (mips_print_operand_punct_valid_p (letter))
8950 mips_print_operand_punctuation (file, letter);
8951 return;
8954 gcc_assert (op);
8955 code = GET_CODE (op);
8957 switch (letter)
8959 case 'E':
8960 if (GET_CODE (op) == CONST_VECTOR)
8962 gcc_assert (mips_const_vector_same_val_p (op, GET_MODE (op)));
8963 op = CONST_VECTOR_ELT (op, 0);
8964 gcc_assert (CONST_INT_P (op));
8965 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8967 else
8968 output_operand_lossage ("invalid use of '%%%c'", letter);
8969 break;
8971 case 'X':
8972 if (CONST_INT_P (op))
8973 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8974 else
8975 output_operand_lossage ("invalid use of '%%%c'", letter);
8976 break;
8978 case 'x':
8979 if (CONST_INT_P (op))
8980 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8981 else
8982 output_operand_lossage ("invalid use of '%%%c'", letter);
8983 break;
8985 case 'd':
8986 if (CONST_INT_P (op))
8987 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8988 else
8989 output_operand_lossage ("invalid use of '%%%c'", letter);
8990 break;
8992 case 'B':
8993 if (GET_CODE (op) == CONST_VECTOR)
8995 gcc_assert (mips_const_vector_same_val_p (op, GET_MODE (op)));
8996 op = CONST_VECTOR_ELT (op, 0);
8997 gcc_assert (CONST_INT_P (op));
8998 unsigned HOST_WIDE_INT val8 = UINTVAL (op) & GET_MODE_MASK (QImode);
8999 fprintf (file, HOST_WIDE_INT_PRINT_UNSIGNED, val8);
9001 else
9002 output_operand_lossage ("invalid use of '%%%c'", letter);
9003 break;
9005 case 'm':
9006 if (CONST_INT_P (op))
9007 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
9008 else
9009 output_operand_lossage ("invalid use of '%%%c'", letter);
9010 break;
9012 case 'y':
9013 if (CONST_INT_P (op))
9015 int val = exact_log2 (INTVAL (op));
9016 if (val != -1)
9017 fprintf (file, "%d", val);
9018 else
9019 output_operand_lossage ("invalid use of '%%%c'", letter);
9021 else
9022 output_operand_lossage ("invalid use of '%%%c'", letter);
9023 break;
9025 case 'V':
9026 if (GET_CODE (op) == CONST_VECTOR)
9028 machine_mode mode = GET_MODE_INNER (GET_MODE (op));
9029 unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (op, 0));
9030 int vlog2 = exact_log2 (val & GET_MODE_MASK (mode));
9031 if (vlog2 != -1)
9032 fprintf (file, "%d", vlog2);
9033 else
9034 output_operand_lossage ("invalid use of '%%%c'", letter);
9036 else
9037 output_operand_lossage ("invalid use of '%%%c'", letter);
9038 break;
9040 case 'h':
9041 if (code == HIGH)
9042 op = XEXP (op, 0);
9043 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
9044 break;
9046 case 'R':
9047 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
9048 break;
9050 case 'C':
9051 mips_print_int_branch_condition (file, code, letter);
9052 break;
9054 case 'N':
9055 mips_print_int_branch_condition (file, reverse_condition (code), letter);
9056 break;
9058 case 'F':
9059 mips_print_float_branch_condition (file, code, letter);
9060 break;
9062 case 'W':
9063 mips_print_float_branch_condition (file, reverse_condition (code),
9064 letter);
9065 break;
9067 case 'T':
9068 case 't':
9070 int truth = (code == NE) == (letter == 'T');
9071 fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);
9073 break;
9075 case 'Y':
9076 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
9077 fputs (mips_fp_conditions[UINTVAL (op)], file);
9078 else
9079 output_operand_lossage ("'%%%c' is not a valid operand prefix",
9080 letter);
9081 break;
9083 case 'Z':
9084 if (ISA_HAS_8CC || ISA_HAS_CCF)
9086 mips_print_operand (file, op, 0);
9087 fputc (',', file);
9089 break;
9091 case 'q':
9092 if (code == REG && MD_REG_P (REGNO (op)))
9093 fprintf (file, "$ac0");
9094 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
9095 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
9096 else
9097 output_operand_lossage ("invalid use of '%%%c'", letter);
9098 break;
9100 case 'w':
9101 if (code == REG && MSA_REG_P (REGNO (op)))
9102 fprintf (file, "$w%s", &reg_names[REGNO (op)][2]);
9103 else
9104 output_operand_lossage ("invalid use of '%%%c'", letter);
9105 break;
9107 case 'v':
9108 switch (GET_MODE (op))
9110 case V16QImode:
9111 fprintf (file, "b");
9112 break;
9113 case V8HImode:
9114 fprintf (file, "h");
9115 break;
9116 case V4SImode:
9117 case V4SFmode:
9118 fprintf (file, "w");
9119 break;
9120 case V2DImode:
9121 case V2DFmode:
9122 fprintf (file, "d");
9123 break;
9124 default:
9125 output_operand_lossage ("invalid use of '%%%c'", letter);
9127 break;
9129 default:
9130 switch (code)
9132 case REG:
9134 unsigned int regno = REGNO (op);
9135 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
9136 || (letter == 'L' && TARGET_BIG_ENDIAN)
9137 || letter == 'D')
9138 regno++;
9139 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
9140 output_operand_lossage ("invalid use of '%%%c'", letter);
9141 /* We need to print $0 .. $31 for COP0 registers. */
9142 if (COP0_REG_P (regno))
9143 fprintf (file, "$%s", &reg_names[regno][4]);
9144 else
9145 fprintf (file, "%s", reg_names[regno]);
9147 break;
9149 case MEM:
9150 if (letter == 'D')
9151 output_address (GET_MODE (op), plus_constant (Pmode,
9152 XEXP (op, 0), 4));
9153 else if (letter == 'b')
9155 gcc_assert (REG_P (XEXP (op, 0)));
9156 mips_print_operand (file, XEXP (op, 0), 0);
9158 else if (letter && letter != 'z')
9159 output_operand_lossage ("invalid use of '%%%c'", letter);
9160 else
9161 output_address (GET_MODE (op), XEXP (op, 0));
9162 break;
9164 default:
9165 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
9166 fputs (reg_names[GP_REG_FIRST], file);
9167 else if (letter && letter != 'z')
9168 output_operand_lossage ("invalid use of '%%%c'", letter);
9169 else if (CONST_GP_P (op))
9170 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
9171 else
9172 output_addr_const (file, mips_strip_unspec_address (op));
9173 break;
9178 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9180 static void
9181 mips_print_operand_address (FILE *file, machine_mode /*mode*/, rtx x)
9183 struct mips_address_info addr;
9185 if (mips_classify_address (&addr, x, word_mode, true))
9186 switch (addr.type)
9188 case ADDRESS_REG:
9189 mips_print_operand (file, addr.offset, 0);
9190 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
9191 return;
9193 case ADDRESS_LO_SUM:
9194 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
9195 mips_lo_relocs);
9196 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
9197 return;
9199 case ADDRESS_CONST_INT:
9200 output_addr_const (file, x);
9201 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
9202 return;
9204 case ADDRESS_SYMBOLIC:
9205 output_addr_const (file, mips_strip_unspec_address (x));
9206 return;
9208 gcc_unreachable ();
9211 /* Implement TARGET_ENCODE_SECTION_INFO. */
9213 static void
9214 mips_encode_section_info (tree decl, rtx rtl, int first)
9216 default_encode_section_info (decl, rtl, first);
9218 if (TREE_CODE (decl) == FUNCTION_DECL)
9220 rtx symbol = XEXP (rtl, 0);
9221 tree type = TREE_TYPE (decl);
9223 /* Encode whether the symbol is short or long. */
9224 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
9225 || mips_far_type_p (type))
9226 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
9230 /* Implement TARGET_SELECT_RTX_SECTION. */
9232 static section *
9233 mips_select_rtx_section (machine_mode mode, rtx x,
9234 unsigned HOST_WIDE_INT align)
9236 /* ??? Consider using mergeable small data sections. */
9237 if (mips_rtx_constant_in_small_data_p (mode))
9238 return get_named_section (NULL, ".sdata", 0);
9240 return default_elf_select_rtx_section (mode, x, align);
9243 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
9245 The complication here is that, with the combination TARGET_ABICALLS
9246 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
9247 absolute addresses, and should therefore not be included in the
9248 read-only part of a DSO. Handle such cases by selecting a normal
9249 data section instead of a read-only one. The logic apes that in
9250 default_function_rodata_section. */
9252 static section *
9253 mips_function_rodata_section (tree decl)
9255 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
9256 return default_function_rodata_section (decl);
9258 if (decl && DECL_SECTION_NAME (decl))
9260 const char *name = DECL_SECTION_NAME (decl);
9261 if (DECL_COMDAT_GROUP (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
9263 char *rname = ASTRDUP (name);
9264 rname[14] = 'd';
9265 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
9267 else if (flag_function_sections
9268 && flag_data_sections
9269 && strncmp (name, ".text.", 6) == 0)
9271 char *rname = ASTRDUP (name);
9272 memcpy (rname + 1, "data", 4);
9273 return get_section (rname, SECTION_WRITE, decl);
9276 return data_section;
9279 /* Implement TARGET_IN_SMALL_DATA_P. */
9281 static bool
9282 mips_in_small_data_p (const_tree decl)
9284 unsigned HOST_WIDE_INT size;
9286 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
9287 return false;
9289 /* We don't yet generate small-data references for -mabicalls
9290 or VxWorks RTP code. See the related -G handling in
9291 mips_option_override. */
9292 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
9293 return false;
9295 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
9297 const char *name;
9299 /* Reject anything that isn't in a known small-data section. */
9300 name = DECL_SECTION_NAME (decl);
9301 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
9302 return false;
9304 /* If a symbol is defined externally, the assembler will use the
9305 usual -G rules when deciding how to implement macros. */
9306 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
9307 return true;
9309 else if (TARGET_EMBEDDED_DATA)
9311 /* Don't put constants into the small data section: we want them
9312 to be in ROM rather than RAM. */
9313 if (TREE_CODE (decl) != VAR_DECL)
9314 return false;
9316 if (TREE_READONLY (decl)
9317 && !TREE_SIDE_EFFECTS (decl)
9318 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
9319 return false;
9322 /* Enforce -mlocal-sdata. */
9323 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
9324 return false;
9326 /* Enforce -mextern-sdata. */
9327 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
9329 if (DECL_EXTERNAL (decl))
9330 return false;
9331 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
9332 return false;
9335 /* We have traditionally not treated zero-sized objects as small data,
9336 so this is now effectively part of the ABI. */
9337 size = int_size_in_bytes (TREE_TYPE (decl));
9338 return size > 0 && size <= mips_small_data_threshold;
9341 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
9342 anchors for small data: the GP register acts as an anchor in that
9343 case. We also don't want to use them for PC-relative accesses,
9344 where the PC acts as an anchor. */
9346 static bool
9347 mips_use_anchors_for_symbol_p (const_rtx symbol)
9349 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
9351 case SYMBOL_PC_RELATIVE:
9352 case SYMBOL_GP_RELATIVE:
9353 return false;
9355 default:
9356 return default_use_anchors_for_symbol_p (symbol);
9360 /* The MIPS debug format wants all automatic variables and arguments
9361 to be in terms of the virtual frame pointer (stack pointer before
9362 any adjustment in the function), while the MIPS 3.0 linker wants
9363 the frame pointer to be the stack pointer after the initial
9364 adjustment. So, we do the adjustment here. The arg pointer (which
9365 is eliminated) points to the virtual frame pointer, while the frame
9366 pointer (which may be eliminated) points to the stack pointer after
9367 the initial adjustments. */
9369 HOST_WIDE_INT
9370 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
9372 rtx offset2 = const0_rtx;
9373 rtx reg = eliminate_constant_term (addr, &offset2);
9375 if (offset == 0)
9376 offset = INTVAL (offset2);
9378 if (reg == stack_pointer_rtx
9379 || reg == frame_pointer_rtx
9380 || reg == hard_frame_pointer_rtx)
9382 offset -= cfun->machine->frame.total_size;
9383 if (reg == hard_frame_pointer_rtx)
9384 offset += cfun->machine->frame.hard_frame_pointer_offset;
9387 return offset;
9390 /* Implement ASM_OUTPUT_EXTERNAL. */
9392 void
9393 mips_output_external (FILE *file, tree decl, const char *name)
9395 default_elf_asm_output_external (file, decl, name);
9397 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
9398 set in order to avoid putting out names that are never really
9399 used. */
9400 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
9402 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
9404 /* When using assembler macros, emit .extern directives for
9405 all small-data externs so that the assembler knows how
9406 big they are.
9408 In most cases it would be safe (though pointless) to emit
9409 .externs for other symbols too. One exception is when an
9410 object is within the -G limit but declared by the user to
9411 be in a section other than .sbss or .sdata. */
9412 fputs ("\t.extern\t", file);
9413 assemble_name (file, name);
9414 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
9415 int_size_in_bytes (TREE_TYPE (decl)));
9420 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
9422 static void
9423 mips_output_filename (FILE *stream, const char *name)
9425 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
9426 directives. */
9427 if (write_symbols == DWARF2_DEBUG)
9428 return;
9429 else if (mips_output_filename_first_time)
9431 mips_output_filename_first_time = 0;
9432 num_source_filenames += 1;
9433 current_function_file = name;
9434 fprintf (stream, "\t.file\t%d ", num_source_filenames);
9435 output_quoted_string (stream, name);
9436 putc ('\n', stream);
9438 /* If we are emitting stabs, let dbxout.c handle this (except for
9439 the mips_output_filename_first_time case). */
9440 else if (write_symbols == DBX_DEBUG)
9441 return;
9442 else if (name != current_function_file
9443 && strcmp (name, current_function_file) != 0)
9445 num_source_filenames += 1;
9446 current_function_file = name;
9447 fprintf (stream, "\t.file\t%d ", num_source_filenames);
9448 output_quoted_string (stream, name);
9449 putc ('\n', stream);
9453 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
9455 static void ATTRIBUTE_UNUSED
9456 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
9458 switch (size)
9460 case 4:
9461 fputs ("\t.dtprelword\t", file);
9462 break;
9464 case 8:
9465 fputs ("\t.dtpreldword\t", file);
9466 break;
9468 default:
9469 gcc_unreachable ();
9471 output_addr_const (file, x);
9472 fputs ("+0x8000", file);
9475 /* Implement TARGET_DWARF_REGISTER_SPAN. */
9477 static rtx
9478 mips_dwarf_register_span (rtx reg)
9480 rtx high, low;
9481 machine_mode mode;
9483 /* TARGET_FLOATXX is implemented as 32-bit floating-point registers but
9484 ensures that double-precision registers are treated as if they were
9485 64-bit physical registers. The code will run correctly with 32-bit or
9486 64-bit registers which means that dwarf information cannot be precise
9487 for all scenarios. We choose to state that the 64-bit values are stored
9488 in a single 64-bit 'piece'. This slightly unusual construct can then be
9489 interpreted as either a pair of registers if the registers are 32-bit or
9490 a single 64-bit register depending on hardware. */
9491 mode = GET_MODE (reg);
9492 if (FP_REG_P (REGNO (reg))
9493 && TARGET_FLOATXX
9494 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
9496 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, reg));
9498 /* By default, GCC maps increasing register numbers to increasing
9499 memory locations, but paired FPRs are always little-endian,
9500 regardless of the prevailing endianness. */
9501 else if (FP_REG_P (REGNO (reg))
9502 && TARGET_BIG_ENDIAN
9503 && MAX_FPRS_PER_FMT > 1
9504 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
9506 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
9507 high = mips_subword (reg, true);
9508 low = mips_subword (reg, false);
9509 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
9512 return NULL_RTX;
9515 /* Implement TARGET_DWARF_FRAME_REG_MODE. */
9517 static machine_mode
9518 mips_dwarf_frame_reg_mode (int regno)
9520 machine_mode mode = default_dwarf_frame_reg_mode (regno);
9522 if (FP_REG_P (regno) && mips_abi == ABI_32 && TARGET_FLOAT64)
9523 mode = SImode;
9525 return mode;
9528 /* DSP ALU can bypass data with no delays for the following pairs. */
9529 enum insn_code dspalu_bypass_table[][2] =
9531 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
9532 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
9533 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
9534 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
9535 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
9536 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
9537 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
9538 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
9542 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
9544 int i;
9545 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
9546 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
9547 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
9549 for (i = 0; i < num_bypass; i++)
9551 if (out_icode == dspalu_bypass_table[i][0]
9552 && in_icode == dspalu_bypass_table[i][1])
9553 return true;
9556 return false;
9558 /* Implement ASM_OUTPUT_ASCII. */
9560 void
9561 mips_output_ascii (FILE *stream, const char *string, size_t len)
9563 size_t i;
9564 int cur_pos;
9566 cur_pos = 17;
9567 fprintf (stream, "\t.ascii\t\"");
9568 for (i = 0; i < len; i++)
9570 int c;
9572 c = (unsigned char) string[i];
9573 if (ISPRINT (c))
9575 if (c == '\\' || c == '\"')
9577 putc ('\\', stream);
9578 cur_pos++;
9580 putc (c, stream);
9581 cur_pos++;
9583 else
9585 fprintf (stream, "\\%03o", c);
9586 cur_pos += 4;
9589 if (cur_pos > 72 && i+1 < len)
9591 cur_pos = 17;
9592 fprintf (stream, "\"\n\t.ascii\t\"");
9595 fprintf (stream, "\"\n");
9598 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
9599 Update *ADDR with the operand that should be printed. */
9601 const char *
9602 mips_output_tls_reloc_directive (rtx *addr)
9604 enum mips_symbol_type type;
9606 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
9607 *addr = mips_strip_unspec_address (*addr);
9608 switch (type)
9610 case SYMBOL_DTPREL:
9611 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
9613 case SYMBOL_TPREL:
9614 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
9616 default:
9617 gcc_unreachable ();
9621 /* Emit either a label, .comm, or .lcomm directive. When using assembler
9622 macros, mark the symbol as written so that mips_asm_output_external
9623 won't emit an .extern for it. STREAM is the output file, NAME is the
9624 name of the symbol, INIT_STRING is the string that should be written
9625 before the symbol and FINAL_STRING is the string that should be
9626 written after it. FINAL_STRING is a printf format that consumes the
9627 remaining arguments. */
9629 void
9630 mips_declare_object (FILE *stream, const char *name, const char *init_string,
9631 const char *final_string, ...)
9633 va_list ap;
9635 fputs (init_string, stream);
9636 assemble_name (stream, name);
9637 va_start (ap, final_string);
9638 vfprintf (stream, final_string, ap);
9639 va_end (ap);
9641 if (!TARGET_EXPLICIT_RELOCS)
9643 tree name_tree = get_identifier (name);
9644 TREE_ASM_WRITTEN (name_tree) = 1;
9648 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
9649 NAME is the name of the object and ALIGN is the required alignment
9650 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
9651 alignment argument. */
9653 void
9654 mips_declare_common_object (FILE *stream, const char *name,
9655 const char *init_string,
9656 unsigned HOST_WIDE_INT size,
9657 unsigned int align, bool takes_alignment_p)
9659 if (!takes_alignment_p)
9661 size += (align / BITS_PER_UNIT) - 1;
9662 size -= size % (align / BITS_PER_UNIT);
9663 mips_declare_object (stream, name, init_string,
9664 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
9666 else
9667 mips_declare_object (stream, name, init_string,
9668 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
9669 size, align / BITS_PER_UNIT);
9672 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
9673 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
9675 void
9676 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
9677 unsigned HOST_WIDE_INT size,
9678 unsigned int align)
9680 /* If the target wants uninitialized const declarations in
9681 .rdata then don't put them in .comm. */
9682 if (TARGET_EMBEDDED_DATA
9683 && TARGET_UNINIT_CONST_IN_RODATA
9684 && TREE_CODE (decl) == VAR_DECL
9685 && TREE_READONLY (decl)
9686 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
9688 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
9689 targetm.asm_out.globalize_label (stream, name);
9691 switch_to_section (readonly_data_section);
9692 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
9693 mips_declare_object (stream, name, "",
9694 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
9695 size);
9697 else
9698 mips_declare_common_object (stream, name, "\n\t.comm\t",
9699 size, align, true);
9702 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
9703 extern int size_directive_output;
9705 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
9706 definitions except that it uses mips_declare_object to emit the label. */
9708 void
9709 mips_declare_object_name (FILE *stream, const char *name,
9710 tree decl ATTRIBUTE_UNUSED)
9712 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9713 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
9714 #endif
9716 size_directive_output = 0;
9717 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
9719 HOST_WIDE_INT size;
9721 size_directive_output = 1;
9722 size = int_size_in_bytes (TREE_TYPE (decl));
9723 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
9726 mips_declare_object (stream, name, "", ":\n");
9729 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
9731 void
9732 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
9734 const char *name;
9736 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
9737 if (!flag_inhibit_size_directive
9738 && DECL_SIZE (decl) != 0
9739 && !at_end
9740 && top_level
9741 && DECL_INITIAL (decl) == error_mark_node
9742 && !size_directive_output)
9744 HOST_WIDE_INT size;
9746 size_directive_output = 1;
9747 size = int_size_in_bytes (TREE_TYPE (decl));
9748 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
9751 #endif
9753 /* Mark text contents as code or data, mainly for the purpose of correct
9754 disassembly. Emit a local symbol and set its type appropriately for
9755 that purpose. Also emit `.insn' if marking contents as code so that
9756 the ISA mode is recorded and any padding that follows is disassembled
9757 as correct instructions. */
9759 void
9760 mips_set_text_contents_type (FILE *file ATTRIBUTE_UNUSED,
9761 const char *prefix ATTRIBUTE_UNUSED,
9762 unsigned long num ATTRIBUTE_UNUSED,
9763 bool function_p ATTRIBUTE_UNUSED)
9765 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9766 char buf[(sizeof (num) * 10) / 4 + 2];
9767 const char *fnname;
9768 char *sname;
9769 rtx symbol;
9771 sprintf (buf, "%lu", num);
9772 symbol = XEXP (DECL_RTL (current_function_decl), 0);
9773 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
9774 sname = ACONCAT ((prefix, fnname, "_", buf, NULL));
9776 ASM_OUTPUT_TYPE_DIRECTIVE (file, sname, function_p ? "function" : "object");
9777 assemble_name (file, sname);
9778 fputs (":\n", file);
9779 if (function_p)
9780 fputs ("\t.insn\n", file);
9781 #endif
9784 /* Return the FOO in the name of the ".mdebug.FOO" section associated
9785 with the current ABI. */
9787 static const char *
9788 mips_mdebug_abi_name (void)
9790 switch (mips_abi)
9792 case ABI_32:
9793 return "abi32";
9794 case ABI_O64:
9795 return "abiO64";
9796 case ABI_N32:
9797 return "abiN32";
9798 case ABI_64:
9799 return "abi64";
9800 case ABI_EABI:
9801 return TARGET_64BIT ? "eabi64" : "eabi32";
9802 default:
9803 gcc_unreachable ();
9807 /* Implement TARGET_ASM_FILE_START. */
9809 static void
9810 mips_file_start (void)
9812 default_file_start ();
9814 /* Generate a special section to describe the ABI switches used to
9815 produce the resultant binary. */
9817 /* Record the ABI itself. Modern versions of binutils encode
9818 this information in the ELF header flags, but GDB needs the
9819 information in order to correctly debug binaries produced by
9820 older binutils. See the function mips_gdbarch_init in
9821 gdb/mips-tdep.c. */
9822 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
9823 mips_mdebug_abi_name ());
9825 /* There is no ELF header flag to distinguish long32 forms of the
9826 EABI from long64 forms. Emit a special section to help tools
9827 such as GDB. Do the same for o64, which is sometimes used with
9828 -mlong64. */
9829 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
9830 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
9831 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
9833 /* Record the NaN encoding. */
9834 if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT)
9835 fprintf (asm_out_file, "\t.nan\t%s\n",
9836 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
9838 #ifdef HAVE_AS_DOT_MODULE
9839 /* Record the FP ABI. See below for comments. */
9840 if (TARGET_NO_FLOAT)
9841 #ifdef HAVE_AS_GNU_ATTRIBUTE
9842 fputs ("\t.gnu_attribute 4, 0\n", asm_out_file);
9843 #else
9845 #endif
9846 else if (!TARGET_HARD_FLOAT_ABI)
9847 fputs ("\t.module\tsoftfloat\n", asm_out_file);
9848 else if (!TARGET_DOUBLE_FLOAT)
9849 fputs ("\t.module\tsinglefloat\n", asm_out_file);
9850 else if (TARGET_FLOATXX)
9851 fputs ("\t.module\tfp=xx\n", asm_out_file);
9852 else if (TARGET_FLOAT64)
9853 fputs ("\t.module\tfp=64\n", asm_out_file);
9854 else
9855 fputs ("\t.module\tfp=32\n", asm_out_file);
9857 if (TARGET_ODD_SPREG)
9858 fputs ("\t.module\toddspreg\n", asm_out_file);
9859 else
9860 fputs ("\t.module\tnooddspreg\n", asm_out_file);
9862 #else
9863 #ifdef HAVE_AS_GNU_ATTRIBUTE
9865 int attr;
9867 /* No floating-point operations, -mno-float. */
9868 if (TARGET_NO_FLOAT)
9869 attr = 0;
9870 /* Soft-float code, -msoft-float. */
9871 else if (!TARGET_HARD_FLOAT_ABI)
9872 attr = 3;
9873 /* Single-float code, -msingle-float. */
9874 else if (!TARGET_DOUBLE_FLOAT)
9875 attr = 2;
9876 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64.
9877 Reserved attr=4.
9878 This case used 12 callee-saved double-precision registers
9879 and is deprecated. */
9880 /* 64-bit or 32-bit FP registers on a 32-bit target, -mfpxx. */
9881 else if (TARGET_FLOATXX)
9882 attr = 5;
9883 /* 64-bit FP registers on a 32-bit target, -mfp64 -modd-spreg. */
9884 else if (mips_abi == ABI_32 && TARGET_FLOAT64 && TARGET_ODD_SPREG)
9885 attr = 6;
9886 /* 64-bit FP registers on a 32-bit target, -mfp64 -mno-odd-spreg. */
9887 else if (mips_abi == ABI_32 && TARGET_FLOAT64)
9888 attr = 7;
9889 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9890 else
9891 attr = 1;
9893 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
9895 /* 128-bit MSA. */
9896 if (ISA_HAS_MSA)
9897 fprintf (asm_out_file, "\t.gnu_attribute 8, 1\n");
9899 #endif
9900 #endif
9902 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9903 if (TARGET_ABICALLS)
9905 fprintf (asm_out_file, "\t.abicalls\n");
9906 if (TARGET_ABICALLS_PIC0)
9907 fprintf (asm_out_file, "\t.option\tpic0\n");
9910 if (flag_verbose_asm)
9911 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9912 ASM_COMMENT_START,
9913 mips_small_data_threshold, mips_arch_info->name, mips_isa);
9916 /* Implement TARGET_ASM_CODE_END. */
9918 static void
9919 mips_code_end (void)
9921 mips_finish_stub (&mips16_rdhwr_stub);
9922 mips_finish_stub (&mips16_get_fcsr_stub);
9923 mips_finish_stub (&mips16_set_fcsr_stub);
9926 /* Make the last instruction frame-related and note that it performs
9927 the operation described by FRAME_PATTERN. */
9929 static void
9930 mips_set_frame_expr (rtx frame_pattern)
9932 rtx_insn *insn;
9934 insn = get_last_insn ();
9935 RTX_FRAME_RELATED_P (insn) = 1;
9936 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9937 frame_pattern,
9938 REG_NOTES (insn));
9941 /* Return a frame-related rtx that stores REG at MEM.
9942 REG must be a single register. */
9944 static rtx
9945 mips_frame_set (rtx mem, rtx reg)
9947 rtx set;
9949 set = gen_rtx_SET (mem, reg);
9950 RTX_FRAME_RELATED_P (set) = 1;
9952 return set;
9955 /* Record that the epilogue has restored call-saved register REG. */
9957 static void
9958 mips_add_cfa_restore (rtx reg)
9960 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
9961 mips_epilogue.cfa_restores);
9964 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9965 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9966 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9967 static const unsigned char mips16e_s2_s8_regs[] = {
9968 30, 23, 22, 21, 20, 19, 18
9970 static const unsigned char mips16e_a0_a3_regs[] = {
9971 4, 5, 6, 7
9974 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9975 ordered from the uppermost in memory to the lowest in memory. */
9976 static const unsigned char mips16e_save_restore_regs[] = {
9977 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9980 /* Return the index of the lowest X in the range [0, SIZE) for which
9981 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9983 static unsigned int
9984 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
9985 unsigned int size)
9987 unsigned int i;
9989 for (i = 0; i < size; i++)
9990 if (BITSET_P (mask, regs[i]))
9991 break;
9993 return i;
9996 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9997 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9998 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9999 is true for all indexes (X, SIZE). */
10001 static void
10002 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
10003 unsigned int size, unsigned int *num_regs_ptr)
10005 unsigned int i;
10007 i = mips16e_find_first_register (*mask_ptr, regs, size);
10008 for (i++; i < size; i++)
10009 if (!BITSET_P (*mask_ptr, regs[i]))
10011 *num_regs_ptr += 1;
10012 *mask_ptr |= 1 << regs[i];
10016 /* Return a simplified form of X using the register values in REG_VALUES.
10017 REG_VALUES[R] is the last value assigned to hard register R, or null
10018 if R has not been modified.
10020 This function is rather limited, but is good enough for our purposes. */
10022 static rtx
10023 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
10025 x = avoid_constant_pool_reference (x);
10027 if (UNARY_P (x))
10029 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
10030 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
10031 x0, GET_MODE (XEXP (x, 0)));
10034 if (ARITHMETIC_P (x))
10036 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
10037 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
10038 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
10041 if (REG_P (x)
10042 && reg_values[REGNO (x)]
10043 && !rtx_unstable_p (reg_values[REGNO (x)]))
10044 return reg_values[REGNO (x)];
10046 return x;
10049 /* Return true if (set DEST SRC) stores an argument register into its
10050 caller-allocated save slot, storing the number of that argument
10051 register in *REGNO_PTR if so. REG_VALUES is as for
10052 mips16e_collect_propagate_value. */
10054 static bool
10055 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
10056 unsigned int *regno_ptr)
10058 unsigned int argno, regno;
10059 HOST_WIDE_INT offset, required_offset;
10060 rtx addr, base;
10062 /* Check that this is a word-mode store. */
10063 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
10064 return false;
10066 /* Check that the register being saved is an unmodified argument
10067 register. */
10068 regno = REGNO (src);
10069 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
10070 return false;
10071 argno = regno - GP_ARG_FIRST;
10073 /* Check whether the address is an appropriate stack-pointer or
10074 frame-pointer access. */
10075 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
10076 mips_split_plus (addr, &base, &offset);
10077 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
10078 if (base == hard_frame_pointer_rtx)
10079 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
10080 else if (base != stack_pointer_rtx)
10081 return false;
10082 if (offset != required_offset)
10083 return false;
10085 *regno_ptr = regno;
10086 return true;
10089 /* A subroutine of mips_expand_prologue, called only when generating
10090 MIPS16e SAVE instructions. Search the start of the function for any
10091 instructions that save argument registers into their caller-allocated
10092 save slots. Delete such instructions and return a value N such that
10093 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
10094 instructions redundant. */
10096 static unsigned int
10097 mips16e_collect_argument_saves (void)
10099 rtx reg_values[FIRST_PSEUDO_REGISTER];
10100 rtx_insn *insn, *next;
10101 rtx set, dest, src;
10102 unsigned int nargs, regno;
10104 push_topmost_sequence ();
10105 nargs = 0;
10106 memset (reg_values, 0, sizeof (reg_values));
10107 for (insn = get_insns (); insn; insn = next)
10109 next = NEXT_INSN (insn);
10110 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
10111 continue;
10113 if (!INSN_P (insn))
10114 break;
10116 set = PATTERN (insn);
10117 if (GET_CODE (set) != SET)
10118 break;
10120 dest = SET_DEST (set);
10121 src = SET_SRC (set);
10122 if (mips16e_collect_argument_save_p (dest, src, reg_values, &regno))
10124 if (!BITSET_P (cfun->machine->frame.mask, regno))
10126 delete_insn (insn);
10127 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
10130 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
10131 reg_values[REGNO (dest)]
10132 = mips16e_collect_propagate_value (src, reg_values);
10133 else
10134 break;
10136 pop_topmost_sequence ();
10138 return nargs;
10141 /* Return a move between register REGNO and memory location SP + OFFSET.
10142 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
10143 Make the move a load if RESTORE_P, otherwise make it a store. */
10145 static rtx
10146 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
10147 HOST_WIDE_INT offset, unsigned int regno)
10149 rtx reg, mem;
10151 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
10152 offset));
10153 reg = gen_rtx_REG (SImode, regno);
10154 if (restore_p)
10156 mips_add_cfa_restore (reg);
10157 return gen_rtx_SET (reg, mem);
10159 if (reg_parm_p)
10160 return gen_rtx_SET (mem, reg);
10161 return mips_frame_set (mem, reg);
10164 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
10165 The instruction must:
10167 - Allocate or deallocate SIZE bytes in total; SIZE is known
10168 to be nonzero.
10170 - Save or restore as many registers in *MASK_PTR as possible.
10171 The instruction saves the first registers at the top of the
10172 allocated area, with the other registers below it.
10174 - Save NARGS argument registers above the allocated area.
10176 (NARGS is always zero if RESTORE_P.)
10178 The SAVE and RESTORE instructions cannot save and restore all general
10179 registers, so there may be some registers left over for the caller to
10180 handle. Destructively modify *MASK_PTR so that it contains the registers
10181 that still need to be saved or restored. The caller can save these
10182 registers in the memory immediately below *OFFSET_PTR, which is a
10183 byte offset from the bottom of the allocated stack area. */
10185 static rtx
10186 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
10187 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
10188 HOST_WIDE_INT size)
10190 rtx pattern, set;
10191 HOST_WIDE_INT offset, top_offset;
10192 unsigned int i, regno;
10193 int n;
10195 gcc_assert (cfun->machine->frame.num_fp == 0);
10197 /* Calculate the number of elements in the PARALLEL. We need one element
10198 for the stack adjustment, one for each argument register save, and one
10199 for each additional register move. */
10200 n = 1 + nargs;
10201 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
10202 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
10203 n++;
10205 /* Create the final PARALLEL. */
10206 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
10207 n = 0;
10209 /* Add the stack pointer adjustment. */
10210 set = gen_rtx_SET (stack_pointer_rtx,
10211 plus_constant (Pmode, stack_pointer_rtx,
10212 restore_p ? size : -size));
10213 RTX_FRAME_RELATED_P (set) = 1;
10214 XVECEXP (pattern, 0, n++) = set;
10216 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
10217 top_offset = restore_p ? size : 0;
10219 /* Save the arguments. */
10220 for (i = 0; i < nargs; i++)
10222 offset = top_offset + i * UNITS_PER_WORD;
10223 set = mips16e_save_restore_reg (restore_p, true, offset,
10224 GP_ARG_FIRST + i);
10225 XVECEXP (pattern, 0, n++) = set;
10228 /* Then fill in the other register moves. */
10229 offset = top_offset;
10230 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
10232 regno = mips16e_save_restore_regs[i];
10233 if (BITSET_P (*mask_ptr, regno))
10235 offset -= UNITS_PER_WORD;
10236 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
10237 XVECEXP (pattern, 0, n++) = set;
10238 *mask_ptr &= ~(1 << regno);
10242 /* Tell the caller what offset it should use for the remaining registers. */
10243 *offset_ptr = size + (offset - top_offset);
10245 gcc_assert (n == XVECLEN (pattern, 0));
10247 return pattern;
10250 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
10251 pointer. Return true if PATTERN matches the kind of instruction
10252 generated by mips16e_build_save_restore. If INFO is nonnull,
10253 initialize it when returning true. */
10255 bool
10256 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
10257 struct mips16e_save_restore_info *info)
10259 unsigned int i, nargs, mask, extra;
10260 HOST_WIDE_INT top_offset, save_offset, offset;
10261 rtx set, reg, mem, base;
10262 int n;
10264 if (!GENERATE_MIPS16E_SAVE_RESTORE)
10265 return false;
10267 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
10268 top_offset = adjust > 0 ? adjust : 0;
10270 /* Interpret all other members of the PARALLEL. */
10271 save_offset = top_offset - UNITS_PER_WORD;
10272 mask = 0;
10273 nargs = 0;
10274 i = 0;
10275 for (n = 1; n < XVECLEN (pattern, 0); n++)
10277 /* Check that we have a SET. */
10278 set = XVECEXP (pattern, 0, n);
10279 if (GET_CODE (set) != SET)
10280 return false;
10282 /* Check that the SET is a load (if restoring) or a store
10283 (if saving). */
10284 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
10285 if (!MEM_P (mem))
10286 return false;
10288 /* Check that the address is the sum of the stack pointer and a
10289 possibly-zero constant offset. */
10290 mips_split_plus (XEXP (mem, 0), &base, &offset);
10291 if (base != stack_pointer_rtx)
10292 return false;
10294 /* Check that SET's other operand is a register. */
10295 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
10296 if (!REG_P (reg))
10297 return false;
10299 /* Check for argument saves. */
10300 if (offset == top_offset + nargs * UNITS_PER_WORD
10301 && REGNO (reg) == GP_ARG_FIRST + nargs)
10302 nargs++;
10303 else if (offset == save_offset)
10305 while (mips16e_save_restore_regs[i++] != REGNO (reg))
10306 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
10307 return false;
10309 mask |= 1 << REGNO (reg);
10310 save_offset -= UNITS_PER_WORD;
10312 else
10313 return false;
10316 /* Check that the restrictions on register ranges are met. */
10317 extra = 0;
10318 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
10319 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
10320 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
10321 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
10322 if (extra != 0)
10323 return false;
10325 /* Make sure that the topmost argument register is not saved twice.
10326 The checks above ensure that the same is then true for the other
10327 argument registers. */
10328 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
10329 return false;
10331 /* Pass back information, if requested. */
10332 if (info)
10334 info->nargs = nargs;
10335 info->mask = mask;
10336 info->size = (adjust > 0 ? adjust : -adjust);
10339 return true;
10342 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
10343 for the register range [MIN_REG, MAX_REG]. Return a pointer to
10344 the null terminator. */
10346 static char *
10347 mips16e_add_register_range (char *s, unsigned int min_reg,
10348 unsigned int max_reg)
10350 if (min_reg != max_reg)
10351 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
10352 else
10353 s += sprintf (s, ",%s", reg_names[min_reg]);
10354 return s;
10357 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
10358 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
10360 const char *
10361 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
10363 static char buffer[300];
10365 struct mips16e_save_restore_info info;
10366 unsigned int i, end;
10367 char *s;
10369 /* Parse the pattern. */
10370 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
10371 gcc_unreachable ();
10373 /* Add the mnemonic. */
10374 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
10375 s += strlen (s);
10377 /* Save the arguments. */
10378 if (info.nargs > 1)
10379 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
10380 reg_names[GP_ARG_FIRST + info.nargs - 1]);
10381 else if (info.nargs == 1)
10382 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
10384 /* Emit the amount of stack space to allocate or deallocate. */
10385 s += sprintf (s, "%d", (int) info.size);
10387 /* Save or restore $16. */
10388 if (BITSET_P (info.mask, 16))
10389 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
10391 /* Save or restore $17. */
10392 if (BITSET_P (info.mask, 17))
10393 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
10395 /* Save or restore registers in the range $s2...$s8, which
10396 mips16e_s2_s8_regs lists in decreasing order. Note that this
10397 is a software register range; the hardware registers are not
10398 numbered consecutively. */
10399 end = ARRAY_SIZE (mips16e_s2_s8_regs);
10400 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
10401 if (i < end)
10402 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
10403 mips16e_s2_s8_regs[i]);
10405 /* Save or restore registers in the range $a0...$a3. */
10406 end = ARRAY_SIZE (mips16e_a0_a3_regs);
10407 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
10408 if (i < end)
10409 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
10410 mips16e_a0_a3_regs[end - 1]);
10412 /* Save or restore $31. */
10413 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
10414 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
10416 return buffer;
10419 /* Return true if the current function returns its value in a floating-point
10420 register in MIPS16 mode. */
10422 static bool
10423 mips16_cfun_returns_in_fpr_p (void)
10425 tree return_type = DECL_RESULT (current_function_decl);
10426 return (TARGET_MIPS16
10427 && TARGET_HARD_FLOAT_ABI
10428 && !aggregate_value_p (return_type, current_function_decl)
10429 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
10432 /* Return true if predicate PRED is true for at least one instruction.
10433 Cache the result in *CACHE, and assume that the result is true
10434 if *CACHE is already true. */
10436 static bool
10437 mips_find_gp_ref (bool *cache, bool (*pred) (rtx_insn *))
10439 rtx_insn *insn, *subinsn;
10441 if (!*cache)
10443 push_topmost_sequence ();
10444 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10445 FOR_EACH_SUBINSN (subinsn, insn)
10446 if (USEFUL_INSN_P (subinsn) && pred (subinsn))
10448 *cache = true;
10449 break;
10451 pop_topmost_sequence ();
10453 return *cache;
10456 /* Return true if INSN refers to the global pointer in an "inflexible" way.
10457 See mips_cfun_has_inflexible_gp_ref_p for details. */
10459 static bool
10460 mips_insn_has_inflexible_gp_ref_p (rtx_insn *insn)
10462 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
10463 indicate that the target could be a traditional MIPS
10464 lazily-binding stub. */
10465 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
10468 /* Return true if the current function refers to the global pointer
10469 in a way that forces $28 to be valid. This means that we can't
10470 change the choice of global pointer, even for NewABI code.
10472 One example of this (and one which needs several checks) is that
10473 $28 must be valid when calling traditional MIPS lazy-binding stubs.
10474 (This restriction does not apply to PLTs.) */
10476 static bool
10477 mips_cfun_has_inflexible_gp_ref_p (void)
10479 /* If the function has a nonlocal goto, $28 must hold the correct
10480 global pointer for the target function. That is, the target
10481 of the goto implicitly uses $28. */
10482 if (crtl->has_nonlocal_goto)
10483 return true;
10485 if (TARGET_ABICALLS_PIC2)
10487 /* Symbolic accesses implicitly use the global pointer unless
10488 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
10489 might go to traditional MIPS lazy-binding stubs. */
10490 if (!TARGET_EXPLICIT_RELOCS)
10491 return true;
10493 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
10494 can be lazily-bound. */
10495 if (crtl->profile)
10496 return true;
10498 /* MIPS16 functions that return in FPRs need to call an
10499 external libgcc routine. This call is only made explict
10500 during mips_expand_epilogue, and it too might be lazily bound. */
10501 if (mips16_cfun_returns_in_fpr_p ())
10502 return true;
10505 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
10506 mips_insn_has_inflexible_gp_ref_p);
10509 /* Return true if INSN refers to the global pointer in a "flexible" way.
10510 See mips_cfun_has_flexible_gp_ref_p for details. */
10512 static bool
10513 mips_insn_has_flexible_gp_ref_p (rtx_insn *insn)
10515 return (get_attr_got (insn) != GOT_UNSET
10516 || mips_small_data_pattern_p (PATTERN (insn))
10517 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
10520 /* Return true if the current function references the global pointer,
10521 but if those references do not inherently require the global pointer
10522 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
10524 static bool
10525 mips_cfun_has_flexible_gp_ref_p (void)
10527 /* Reload can sometimes introduce constant pool references
10528 into a function that otherwise didn't need them. For example,
10529 suppose we have an instruction like:
10531 (set (reg:DF R1) (float:DF (reg:SI R2)))
10533 If R2 turns out to be a constant such as 1, the instruction may
10534 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
10535 the option of using this constant if R2 doesn't get allocated
10536 to a register.
10538 In cases like these, reload will have added the constant to the
10539 pool but no instruction will yet refer to it. */
10540 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
10541 return true;
10543 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
10544 mips_insn_has_flexible_gp_ref_p);
10547 /* Return the register that should be used as the global pointer
10548 within this function. Return INVALID_REGNUM if the function
10549 doesn't need a global pointer. */
10551 static unsigned int
10552 mips_global_pointer (void)
10554 unsigned int regno;
10556 /* $gp is always available unless we're using a GOT. */
10557 if (!TARGET_USE_GOT)
10558 return GLOBAL_POINTER_REGNUM;
10560 /* If there are inflexible references to $gp, we must use the
10561 standard register. */
10562 if (mips_cfun_has_inflexible_gp_ref_p ())
10563 return GLOBAL_POINTER_REGNUM;
10565 /* If there are no current references to $gp, then the only uses
10566 we can introduce later are those involved in long branches. */
10567 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
10568 return INVALID_REGNUM;
10570 /* If the global pointer is call-saved, try to use a call-clobbered
10571 alternative. */
10572 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
10573 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
10574 if (!df_regs_ever_live_p (regno)
10575 && call_really_used_regs[regno]
10576 && !fixed_regs[regno]
10577 && regno != PIC_FUNCTION_ADDR_REGNUM)
10578 return regno;
10580 return GLOBAL_POINTER_REGNUM;
10583 /* Return true if the current function's prologue must load the global
10584 pointer value into pic_offset_table_rtx and store the same value in
10585 the function's cprestore slot (if any).
10587 One problem we have to deal with is that, when emitting GOT-based
10588 position independent code, long-branch sequences will need to load
10589 the address of the branch target from the GOT. We don't know until
10590 the very end of compilation whether (and where) the function needs
10591 long branches, so we must ensure that _any_ branch can access the
10592 global pointer in some form. However, we do not want to pessimize
10593 the usual case in which all branches are short.
10595 We handle this as follows:
10597 (1) During reload, we set cfun->machine->global_pointer to
10598 INVALID_REGNUM if we _know_ that the current function
10599 doesn't need a global pointer. This is only valid if
10600 long branches don't need the GOT.
10602 Otherwise, we assume that we might need a global pointer
10603 and pick an appropriate register.
10605 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
10606 we ensure that the global pointer is available at every
10607 block boundary bar entry and exit. We do this in one of two ways:
10609 - If the function has a cprestore slot, we ensure that this
10610 slot is valid at every branch. However, as explained in
10611 point (6) below, there is no guarantee that pic_offset_table_rtx
10612 itself is valid if new uses of the global pointer are introduced
10613 after the first post-epilogue split.
10615 We guarantee that the cprestore slot is valid by loading it
10616 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
10617 this register live at every block boundary bar function entry
10618 and exit. It is then invalid to move the load (and thus the
10619 preceding store) across a block boundary.
10621 - If the function has no cprestore slot, we guarantee that
10622 pic_offset_table_rtx itself is valid at every branch.
10624 See mips_eh_uses for the handling of the register liveness.
10626 (3) During prologue and epilogue generation, we emit "ghost"
10627 placeholder instructions to manipulate the global pointer.
10629 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
10630 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
10631 that the function needs a global pointer. (There is no need to set
10632 them earlier than this, and doing it as late as possible leads to
10633 fewer false positives.)
10635 (5) If cfun->machine->must_initialize_gp_p is true during a
10636 split_insns pass, we split the ghost instructions into real
10637 instructions. These split instructions can then be optimized in
10638 the usual way. Otherwise, we keep the ghost instructions intact,
10639 and optimize for the case where they aren't needed. We still
10640 have the option of splitting them later, if we need to introduce
10641 new uses of the global pointer.
10643 For example, the scheduler ignores a ghost instruction that
10644 stores $28 to the stack, but it handles the split form of
10645 the ghost instruction as an ordinary store.
10647 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
10648 is true during the first post-epilogue split_insns pass, we split
10649 calls and restore_gp patterns into instructions that explicitly
10650 load pic_offset_table_rtx from the cprestore slot. Otherwise,
10651 we split these patterns into instructions that _don't_ load from
10652 the cprestore slot.
10654 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
10655 time of the split, then any instructions that exist at that time
10656 can make free use of pic_offset_table_rtx. However, if we want
10657 to introduce new uses of the global pointer after the split,
10658 we must explicitly load the value from the cprestore slot, since
10659 pic_offset_table_rtx itself might not be valid at a given point
10660 in the function.
10662 The idea is that we want to be able to delete redundant
10663 loads from the cprestore slot in the usual case where no
10664 long branches are needed.
10666 (7) If cfun->machine->must_initialize_gp_p is still false at the end
10667 of md_reorg, we decide whether the global pointer is needed for
10668 long branches. If so, we set cfun->machine->must_initialize_gp_p
10669 to true and split the ghost instructions into real instructions
10670 at that stage.
10672 Note that the ghost instructions must have a zero length for three reasons:
10674 - Giving the length of the underlying $gp sequence might cause
10675 us to use long branches in cases where they aren't really needed.
10677 - They would perturb things like alignment calculations.
10679 - More importantly, the hazard detection in md_reorg relies on
10680 empty instructions having a zero length.
10682 If we find a long branch and split the ghost instructions at the
10683 end of md_reorg, the split could introduce more long branches.
10684 That isn't a problem though, because we still do the split before
10685 the final shorten_branches pass.
10687 This is extremely ugly, but it seems like the best compromise between
10688 correctness and efficiency. */
10690 bool
10691 mips_must_initialize_gp_p (void)
10693 return cfun->machine->must_initialize_gp_p;
10696 /* Return true if REGNO is a register that is ordinarily call-clobbered
10697 but must nevertheless be preserved by an interrupt handler. */
10699 static bool
10700 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
10702 if ((ISA_HAS_HILO || TARGET_DSP)
10703 && MD_REG_P (regno))
10704 return true;
10706 if (TARGET_DSP && DSP_ACC_REG_P (regno))
10707 return true;
10709 if (GP_REG_P (regno)
10710 && cfun->machine->use_shadow_register_set == SHADOW_SET_NO)
10712 /* $0 is hard-wired. */
10713 if (regno == GP_REG_FIRST)
10714 return false;
10716 /* The interrupt handler can treat kernel registers as
10717 scratch registers. */
10718 if (KERNEL_REG_P (regno))
10719 return false;
10721 /* The function will return the stack pointer to its original value
10722 anyway. */
10723 if (regno == STACK_POINTER_REGNUM)
10724 return false;
10726 /* Otherwise, return true for registers that aren't ordinarily
10727 call-clobbered. */
10728 return call_really_used_regs[regno];
10731 return false;
10734 /* Return true if the current function should treat register REGNO
10735 as call-saved. */
10737 static bool
10738 mips_cfun_call_saved_reg_p (unsigned int regno)
10740 /* If the user makes an ordinarily-call-saved register global,
10741 that register is no longer call-saved. */
10742 if (global_regs[regno])
10743 return false;
10745 /* Interrupt handlers need to save extra registers. */
10746 if (cfun->machine->interrupt_handler_p
10747 && mips_interrupt_extra_call_saved_reg_p (regno))
10748 return true;
10750 /* call_insns preserve $28 unless they explicitly say otherwise,
10751 so call_really_used_regs[] treats $28 as call-saved. However,
10752 we want the ABI property rather than the default call_insn
10753 property here. */
10754 return (regno == GLOBAL_POINTER_REGNUM
10755 ? TARGET_CALL_SAVED_GP
10756 : !call_really_used_regs[regno]);
10759 /* Return true if the function body might clobber register REGNO.
10760 We know that REGNO is call-saved. */
10762 static bool
10763 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
10765 /* Some functions should be treated as clobbering all call-saved
10766 registers. */
10767 if (crtl->saves_all_registers)
10768 return true;
10770 /* DF handles cases where a register is explicitly referenced in
10771 the rtl. Incoming values are passed in call-clobbered registers,
10772 so we can assume that any live call-saved register is set within
10773 the function. */
10774 if (df_regs_ever_live_p (regno))
10775 return true;
10777 /* Check for registers that are clobbered by FUNCTION_PROFILER.
10778 These clobbers are not explicit in the rtl. */
10779 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
10780 return true;
10782 /* If we're using a call-saved global pointer, the function's
10783 prologue will need to set it up. */
10784 if (cfun->machine->global_pointer == regno)
10785 return true;
10787 /* The function's prologue will need to set the frame pointer if
10788 frame_pointer_needed. */
10789 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
10790 return true;
10792 /* If a MIPS16 function returns a value in FPRs, its epilogue
10793 will need to call an external libgcc routine. This yet-to-be
10794 generated call_insn will clobber $31. */
10795 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
10796 return true;
10798 /* If REGNO is ordinarily call-clobbered, we must assume that any
10799 called function could modify it. */
10800 if (cfun->machine->interrupt_handler_p
10801 && !crtl->is_leaf
10802 && mips_interrupt_extra_call_saved_reg_p (regno))
10803 return true;
10805 return false;
10808 /* Return true if the current function must save register REGNO. */
10810 static bool
10811 mips_save_reg_p (unsigned int regno)
10813 if (mips_cfun_call_saved_reg_p (regno))
10815 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
10816 return true;
10818 /* Save both registers in an FPR pair if either one is used. This is
10819 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
10820 register to be used without the even register. */
10821 if (FP_REG_P (regno)
10822 && MAX_FPRS_PER_FMT == 2
10823 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
10824 return true;
10827 /* We need to save the incoming return address if __builtin_eh_return
10828 is being used to set a different return address. */
10829 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
10830 return true;
10832 return false;
10835 /* Populate the current function's mips_frame_info structure.
10837 MIPS stack frames look like:
10839 +-------------------------------+
10841 | incoming stack arguments |
10843 +-------------------------------+
10845 | caller-allocated save area |
10846 A | for register arguments |
10848 +-------------------------------+ <-- incoming stack pointer
10850 | callee-allocated save area |
10851 B | for arguments that are |
10852 | split between registers and |
10853 | the stack |
10855 +-------------------------------+ <-- arg_pointer_rtx
10857 C | callee-allocated save area |
10858 | for register varargs |
10860 +-------------------------------+ <-- frame_pointer_rtx
10861 | | + cop0_sp_offset
10862 | COP0 reg save area | + UNITS_PER_WORD
10864 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
10865 | | + UNITS_PER_WORD
10866 | accumulator save area |
10868 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
10869 | | + UNITS_PER_HWFPVALUE
10870 | FPR save area |
10872 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
10873 | | + UNITS_PER_WORD
10874 | GPR save area |
10876 +-------------------------------+ <-- frame_pointer_rtx with
10877 | | \ -fstack-protector
10878 | local variables | | var_size
10879 | | /
10880 +-------------------------------+
10881 | | \
10882 | $gp save area | | cprestore_size
10883 | | /
10884 P +-------------------------------+ <-- hard_frame_pointer_rtx for
10885 | | \ MIPS16 code
10886 | outgoing stack arguments | |
10887 | | |
10888 +-------------------------------+ | args_size
10889 | | |
10890 | caller-allocated save area | |
10891 | for register arguments | |
10892 | | /
10893 +-------------------------------+ <-- stack_pointer_rtx
10894 frame_pointer_rtx without
10895 -fstack-protector
10896 hard_frame_pointer_rtx for
10897 non-MIPS16 code.
10899 At least two of A, B and C will be empty.
10901 Dynamic stack allocations such as alloca insert data at point P.
10902 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10903 hard_frame_pointer_rtx unchanged. */
10905 static void
10906 mips_compute_frame_info (void)
10908 struct mips_frame_info *frame;
10909 HOST_WIDE_INT offset, size;
10910 unsigned int regno, i;
10912 /* Skip re-computing the frame info after reload completed. */
10913 if (reload_completed)
10914 return;
10916 /* Set this function's interrupt properties. */
10917 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
10919 if (mips_isa_rev < 2)
10920 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10921 else if (TARGET_MIPS16)
10922 error ("interrupt handlers cannot be MIPS16 functions");
10923 else
10925 cfun->machine->interrupt_handler_p = true;
10926 cfun->machine->int_mask =
10927 mips_interrupt_mask (TREE_TYPE (current_function_decl));
10928 cfun->machine->use_shadow_register_set =
10929 mips_use_shadow_register_set (TREE_TYPE (current_function_decl));
10930 cfun->machine->keep_interrupts_masked_p =
10931 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
10932 cfun->machine->use_debug_exception_return_p =
10933 mips_use_debug_exception_return_p (TREE_TYPE
10934 (current_function_decl));
10938 frame = &cfun->machine->frame;
10939 memset (frame, 0, sizeof (*frame));
10940 size = get_frame_size ();
10942 /* The first two blocks contain the outgoing argument area and the $gp save
10943 slot. This area isn't needed in leaf functions. We can also skip it
10944 if we know that none of the called functions will use this space.
10946 But if the target-independent frame size is nonzero, we have already
10947 committed to allocating these in STARTING_FRAME_OFFSET for
10948 !FRAME_GROWS_DOWNWARD. */
10950 if ((size == 0 || FRAME_GROWS_DOWNWARD)
10951 && (crtl->is_leaf || (cfun->machine->optimize_call_stack && !flag_pic)))
10953 /* The MIPS 3.0 linker does not like functions that dynamically
10954 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10955 looks like we are trying to create a second frame pointer to the
10956 function, so allocate some stack space to make it happy. */
10957 if (cfun->calls_alloca)
10958 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
10959 else
10960 frame->args_size = 0;
10961 frame->cprestore_size = 0;
10963 else
10965 frame->args_size = crtl->outgoing_args_size;
10966 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
10969 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10970 arguments. This tends to increase the chances of using unextended
10971 instructions for local variables and incoming arguments. */
10972 if (TARGET_MIPS16)
10973 frame->hard_frame_pointer_offset = frame->args_size;
10975 /* PR 69129 / 69012: Beware of a possible race condition. mips_global_pointer
10976 might call mips_cfun_has_inflexible_gp_ref_p which in turn can call
10977 mips_find_gp_ref which will iterate over the current insn sequence.
10978 If any of these insns use the cprestore_save_slot_operand or
10979 cprestore_load_slot_operand predicates in order to be recognised then
10980 they will call mips_cprestore_address_p which calls
10981 mips_get_cprestore_base_and_offset which expects the frame information
10982 to be filled in... In fact mips_get_cprestore_base_and_offset only
10983 needs the args_size and hard_frame_pointer_offset fields to be filled
10984 in, which is why the global_pointer field is initialised here and not
10985 earlier. */
10986 cfun->machine->global_pointer = mips_global_pointer ();
10988 offset = frame->args_size + frame->cprestore_size;
10990 /* Move above the local variables. */
10991 frame->var_size = MIPS_STACK_ALIGN (size);
10992 offset += frame->var_size;
10994 /* Find out which GPRs we need to save. */
10995 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
10996 if (mips_save_reg_p (regno))
10998 frame->num_gp++;
10999 frame->mask |= 1 << (regno - GP_REG_FIRST);
11002 /* If this function calls eh_return, we must also save and restore the
11003 EH data registers. */
11004 if (crtl->calls_eh_return)
11005 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
11007 frame->num_gp++;
11008 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
11011 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
11012 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
11013 save all later registers too. */
11014 if (GENERATE_MIPS16E_SAVE_RESTORE)
11016 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
11017 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
11018 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
11019 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
11022 /* Move above the GPR save area. */
11023 if (frame->num_gp > 0)
11025 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
11026 frame->gp_sp_offset = offset - UNITS_PER_WORD;
11029 /* Find out which FPRs we need to save. This loop must iterate over
11030 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
11031 if (TARGET_HARD_FLOAT)
11032 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
11033 if (mips_save_reg_p (regno))
11035 frame->num_fp += MAX_FPRS_PER_FMT;
11036 frame->fmask |= ~(~0U << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
11039 /* Move above the FPR save area. */
11040 if (frame->num_fp > 0)
11042 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
11043 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
11046 /* Add in space for the interrupt context information. */
11047 if (cfun->machine->interrupt_handler_p)
11049 /* Check HI/LO. */
11050 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
11052 frame->num_acc++;
11053 frame->acc_mask |= (1 << 0);
11056 /* Check accumulators 1, 2, 3. */
11057 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
11058 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
11060 frame->num_acc++;
11061 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
11064 /* All interrupt context functions need space to preserve STATUS. */
11065 frame->num_cop0_regs++;
11067 /* We need to save EPC regardless of whether interrupts remain masked
11068 as exceptions will corrupt EPC. */
11069 frame->num_cop0_regs++;
11072 /* Move above the accumulator save area. */
11073 if (frame->num_acc > 0)
11075 /* Each accumulator needs 2 words. */
11076 offset += frame->num_acc * 2 * UNITS_PER_WORD;
11077 frame->acc_sp_offset = offset - UNITS_PER_WORD;
11080 /* Move above the COP0 register save area. */
11081 if (frame->num_cop0_regs > 0)
11083 offset += frame->num_cop0_regs * UNITS_PER_WORD;
11084 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
11087 /* Determine if we can save the callee-saved registers in the frame
11088 header. Restrict this to functions where there is no other reason
11089 to allocate stack space so that we can eliminate the instructions
11090 that modify the stack pointer. */
11092 if (TARGET_OLDABI
11093 && optimize > 0
11094 && flag_frame_header_optimization
11095 && !MAIN_NAME_P (DECL_NAME (current_function_decl))
11096 && cfun->machine->varargs_size == 0
11097 && crtl->args.pretend_args_size == 0
11098 && frame->var_size == 0
11099 && frame->num_acc == 0
11100 && frame->num_cop0_regs == 0
11101 && frame->num_fp == 0
11102 && frame->num_gp > 0
11103 && frame->num_gp <= MAX_ARGS_IN_REGISTERS
11104 && !GENERATE_MIPS16E_SAVE_RESTORE
11105 && !cfun->machine->interrupt_handler_p
11106 && cfun->machine->does_not_use_frame_header
11107 && cfun->machine->optimize_call_stack
11108 && !cfun->machine->callers_may_not_allocate_frame
11109 && !mips_cfun_has_cprestore_slot_p ())
11111 offset = 0;
11112 frame->gp_sp_offset = REG_PARM_STACK_SPACE(cfun) - UNITS_PER_WORD;
11113 cfun->machine->use_frame_header_for_callee_saved_regs = true;
11116 /* Move above the callee-allocated varargs save area. */
11117 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
11118 frame->arg_pointer_offset = offset;
11120 /* Move above the callee-allocated area for pretend stack arguments. */
11121 offset += crtl->args.pretend_args_size;
11122 frame->total_size = offset;
11124 /* Work out the offsets of the save areas from the top of the frame. */
11125 if (frame->gp_sp_offset > 0)
11126 frame->gp_save_offset = frame->gp_sp_offset - offset;
11127 if (frame->fp_sp_offset > 0)
11128 frame->fp_save_offset = frame->fp_sp_offset - offset;
11129 if (frame->acc_sp_offset > 0)
11130 frame->acc_save_offset = frame->acc_sp_offset - offset;
11131 if (frame->num_cop0_regs > 0)
11132 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
11135 /* Return the style of GP load sequence that is being used for the
11136 current function. */
11138 enum mips_loadgp_style
11139 mips_current_loadgp_style (void)
11141 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
11142 return LOADGP_NONE;
11144 if (TARGET_RTP_PIC)
11145 return LOADGP_RTP;
11147 if (TARGET_ABSOLUTE_ABICALLS)
11148 return LOADGP_ABSOLUTE;
11150 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
11153 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11155 static bool
11156 mips_frame_pointer_required (void)
11158 /* If the function contains dynamic stack allocations, we need to
11159 use the frame pointer to access the static parts of the frame. */
11160 if (cfun->calls_alloca)
11161 return true;
11163 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
11164 reload may be unable to compute the address of a local variable,
11165 since there is no way to add a large constant to the stack pointer
11166 without using a second temporary register. */
11167 if (TARGET_MIPS16)
11169 mips_compute_frame_info ();
11170 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
11171 return true;
11174 return false;
11177 /* Make sure that we're not trying to eliminate to the wrong hard frame
11178 pointer. */
11180 static bool
11181 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
11183 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
11186 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
11187 or argument pointer. TO is either the stack pointer or hard frame
11188 pointer. */
11190 HOST_WIDE_INT
11191 mips_initial_elimination_offset (int from, int to)
11193 HOST_WIDE_INT offset;
11195 mips_compute_frame_info ();
11197 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
11198 switch (from)
11200 case FRAME_POINTER_REGNUM:
11201 if (FRAME_GROWS_DOWNWARD)
11202 offset = (cfun->machine->frame.args_size
11203 + cfun->machine->frame.cprestore_size
11204 + cfun->machine->frame.var_size);
11205 else
11206 offset = 0;
11207 break;
11209 case ARG_POINTER_REGNUM:
11210 offset = cfun->machine->frame.arg_pointer_offset;
11211 break;
11213 default:
11214 gcc_unreachable ();
11217 if (to == HARD_FRAME_POINTER_REGNUM)
11218 offset -= cfun->machine->frame.hard_frame_pointer_offset;
11220 return offset;
11223 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
11225 static void
11226 mips_extra_live_on_entry (bitmap regs)
11228 if (TARGET_USE_GOT)
11230 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
11231 the global pointer. */
11232 if (!TARGET_ABSOLUTE_ABICALLS)
11233 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
11235 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
11236 the global pointer. */
11237 if (TARGET_MIPS16)
11238 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
11240 /* See the comment above load_call<mode> for details. */
11241 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
11245 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
11246 previous frame. */
11249 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
11251 if (count != 0)
11252 return const0_rtx;
11254 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
11257 /* Emit code to change the current function's return address to
11258 ADDRESS. SCRATCH is available as a scratch register, if needed.
11259 ADDRESS and SCRATCH are both word-mode GPRs. */
11261 void
11262 mips_set_return_address (rtx address, rtx scratch)
11264 rtx slot_address;
11266 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
11267 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
11268 cfun->machine->frame.gp_sp_offset);
11269 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
11272 /* Return true if the current function has a cprestore slot. */
11274 bool
11275 mips_cfun_has_cprestore_slot_p (void)
11277 return (cfun->machine->global_pointer != INVALID_REGNUM
11278 && cfun->machine->frame.cprestore_size > 0);
11281 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
11282 cprestore slot. LOAD_P is true if the caller wants to load from
11283 the cprestore slot; it is false if the caller wants to store to
11284 the slot. */
11286 static void
11287 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
11288 bool load_p)
11290 const struct mips_frame_info *frame;
11292 frame = &cfun->machine->frame;
11293 /* .cprestore always uses the stack pointer instead of the frame pointer.
11294 We have a free choice for direct stores for non-MIPS16 functions,
11295 and for MIPS16 functions whose cprestore slot is in range of the
11296 stack pointer. Using the stack pointer would sometimes give more
11297 (early) scheduling freedom, but using the frame pointer would
11298 sometimes give more (late) scheduling freedom. It's hard to
11299 predict which applies to a given function, so let's keep things
11300 simple.
11302 Loads must always use the frame pointer in functions that call
11303 alloca, and there's little benefit to using the stack pointer
11304 otherwise. */
11305 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
11307 *base = hard_frame_pointer_rtx;
11308 *offset = frame->args_size - frame->hard_frame_pointer_offset;
11310 else
11312 *base = stack_pointer_rtx;
11313 *offset = frame->args_size;
11317 /* Return true if X is the load or store address of the cprestore slot;
11318 LOAD_P says which. */
11320 bool
11321 mips_cprestore_address_p (rtx x, bool load_p)
11323 rtx given_base, required_base;
11324 HOST_WIDE_INT given_offset, required_offset;
11326 mips_split_plus (x, &given_base, &given_offset);
11327 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
11328 return given_base == required_base && given_offset == required_offset;
11331 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
11332 going to load from it, false if we are going to store to it.
11333 Use TEMP as a temporary register if need be. */
11335 static rtx
11336 mips_cprestore_slot (rtx temp, bool load_p)
11338 rtx base;
11339 HOST_WIDE_INT offset;
11341 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
11342 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
11345 /* Emit instructions to save global pointer value GP into cprestore
11346 slot MEM. OFFSET is the offset that MEM applies to the base register.
11348 MEM may not be a legitimate address. If it isn't, TEMP is a
11349 temporary register that can be used, otherwise it is a SCRATCH. */
11351 void
11352 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
11354 if (TARGET_CPRESTORE_DIRECTIVE)
11356 gcc_assert (gp == pic_offset_table_rtx);
11357 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
11359 else
11360 mips_emit_move (mips_cprestore_slot (temp, false), gp);
11363 /* Restore $gp from its save slot, using TEMP as a temporary base register
11364 if need be. This function is for o32 and o64 abicalls only.
11366 See mips_must_initialize_gp_p for details about how we manage the
11367 global pointer. */
11369 void
11370 mips_restore_gp_from_cprestore_slot (rtx temp)
11372 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
11374 if (!cfun->machine->must_restore_gp_when_clobbered_p)
11376 emit_note (NOTE_INSN_DELETED);
11377 return;
11380 if (TARGET_MIPS16)
11382 mips_emit_move (temp, mips_cprestore_slot (temp, true));
11383 mips_emit_move (pic_offset_table_rtx, temp);
11385 else
11386 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
11387 if (!TARGET_EXPLICIT_RELOCS)
11388 emit_insn (gen_blockage ());
11391 /* A function to save or store a register. The first argument is the
11392 register and the second is the stack slot. */
11393 typedef void (*mips_save_restore_fn) (rtx, rtx);
11395 /* Use FN to save or restore register REGNO. MODE is the register's
11396 mode and OFFSET is the offset of its save slot from the current
11397 stack pointer. */
11399 static void
11400 mips_save_restore_reg (machine_mode mode, int regno,
11401 HOST_WIDE_INT offset, mips_save_restore_fn fn)
11403 rtx mem;
11405 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
11406 offset));
11407 fn (gen_rtx_REG (mode, regno), mem);
11410 /* Call FN for each accumlator that is saved by the current function.
11411 SP_OFFSET is the offset of the current stack pointer from the start
11412 of the frame. */
11414 static void
11415 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
11417 HOST_WIDE_INT offset;
11418 int regno;
11420 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
11421 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
11423 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
11424 offset -= UNITS_PER_WORD;
11425 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
11426 offset -= UNITS_PER_WORD;
11429 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
11430 if (BITSET_P (cfun->machine->frame.acc_mask,
11431 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
11433 mips_save_restore_reg (word_mode, regno, offset, fn);
11434 offset -= UNITS_PER_WORD;
11438 /* Save register REG to MEM. Make the instruction frame-related. */
11440 static void
11441 mips_save_reg (rtx reg, rtx mem)
11443 if (GET_MODE (reg) == DFmode
11444 && (!TARGET_FLOAT64
11445 || mips_abi == ABI_32))
11447 rtx x1, x2;
11449 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
11451 x1 = mips_frame_set (mips_subword (mem, false),
11452 mips_subword (reg, false));
11453 x2 = mips_frame_set (mips_subword (mem, true),
11454 mips_subword (reg, true));
11455 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
11457 else
11458 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
11461 /* Capture the register combinations that are allowed in a SWM or LWM
11462 instruction. The entries are ordered by number of registers set in
11463 the mask. We also ignore the single register encodings because a
11464 normal SW/LW is preferred. */
11466 static const unsigned int umips_swm_mask[17] = {
11467 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
11468 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
11469 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
11470 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
11471 0x00030000
11474 static const unsigned int umips_swm_encoding[17] = {
11475 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
11478 /* Try to use a microMIPS LWM or SWM instruction to save or restore
11479 as many GPRs in *MASK as possible. *OFFSET is the offset from the
11480 stack pointer of the topmost save slot.
11482 Remove from *MASK all registers that were handled using LWM and SWM.
11483 Update *OFFSET so that it points to the first unused save slot. */
11485 static bool
11486 umips_build_save_restore (mips_save_restore_fn fn,
11487 unsigned *mask, HOST_WIDE_INT *offset)
11489 int nregs;
11490 unsigned int i, j;
11491 rtx pattern, set, reg, mem;
11492 HOST_WIDE_INT this_offset;
11493 rtx this_base;
11495 /* Try matching $16 to $31 (s0 to ra). */
11496 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
11497 if ((*mask & 0xffff0000) == umips_swm_mask[i])
11498 break;
11500 if (i == ARRAY_SIZE (umips_swm_mask))
11501 return false;
11503 /* Get the offset of the lowest save slot. */
11504 nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4);
11505 this_offset = *offset - UNITS_PER_WORD * (nregs - 1);
11507 /* LWM/SWM can only support offsets from -2048 to 2047. */
11508 if (!UMIPS_12BIT_OFFSET_P (this_offset))
11509 return false;
11511 /* Create the final PARALLEL. */
11512 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
11513 this_base = stack_pointer_rtx;
11515 /* For registers $16-$23 and $30. */
11516 for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++)
11518 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
11519 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
11520 unsigned int regno = (j != 8) ? 16 + j : 30;
11521 *mask &= ~(1 << regno);
11522 reg = gen_rtx_REG (SImode, regno);
11523 if (fn == mips_save_reg)
11524 set = mips_frame_set (mem, reg);
11525 else
11527 set = gen_rtx_SET (reg, mem);
11528 mips_add_cfa_restore (reg);
11530 XVECEXP (pattern, 0, j) = set;
11533 /* For register $31. */
11534 if (umips_swm_encoding[i] >> 4)
11536 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
11537 *mask &= ~(1 << 31);
11538 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
11539 reg = gen_rtx_REG (SImode, 31);
11540 if (fn == mips_save_reg)
11541 set = mips_frame_set (mem, reg);
11542 else
11544 set = gen_rtx_SET (reg, mem);
11545 mips_add_cfa_restore (reg);
11547 XVECEXP (pattern, 0, j) = set;
11550 pattern = emit_insn (pattern);
11551 if (fn == mips_save_reg)
11552 RTX_FRAME_RELATED_P (pattern) = 1;
11554 /* Adjust the last offset. */
11555 *offset -= UNITS_PER_WORD * nregs;
11557 return true;
11560 /* Call FN for each register that is saved by the current function.
11561 SP_OFFSET is the offset of the current stack pointer from the start
11562 of the frame. */
11564 static void
11565 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
11566 mips_save_restore_fn fn)
11568 machine_mode fpr_mode;
11569 int regno;
11570 const struct mips_frame_info *frame = &cfun->machine->frame;
11571 HOST_WIDE_INT offset;
11572 unsigned int mask;
11574 /* Save registers starting from high to low. The debuggers prefer at least
11575 the return register be stored at func+4, and also it allows us not to
11576 need a nop in the epilogue if at least one register is reloaded in
11577 addition to return address. */
11578 offset = frame->gp_sp_offset - sp_offset;
11579 mask = frame->mask;
11581 if (TARGET_MICROMIPS)
11582 umips_build_save_restore (fn, &mask, &offset);
11584 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
11585 if (BITSET_P (mask, regno - GP_REG_FIRST))
11587 /* Record the ra offset for use by mips_function_profiler. */
11588 if (regno == RETURN_ADDR_REGNUM)
11589 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
11590 mips_save_restore_reg (word_mode, regno, offset, fn);
11591 offset -= UNITS_PER_WORD;
11594 /* This loop must iterate over the same space as its companion in
11595 mips_compute_frame_info. */
11596 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
11597 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
11598 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
11599 regno >= FP_REG_FIRST;
11600 regno -= MAX_FPRS_PER_FMT)
11601 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
11603 if (!TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT
11604 && (fixed_regs[regno] || fixed_regs[regno + 1]))
11606 if (fixed_regs[regno])
11607 mips_save_restore_reg (SFmode, regno + 1, offset, fn);
11608 else
11609 mips_save_restore_reg (SFmode, regno, offset, fn);
11611 else
11612 mips_save_restore_reg (fpr_mode, regno, offset, fn);
11613 offset -= GET_MODE_SIZE (fpr_mode);
11617 /* Return true if a move between register REGNO and its save slot (MEM)
11618 can be done in a single move. LOAD_P is true if we are loading
11619 from the slot, false if we are storing to it. */
11621 static bool
11622 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
11624 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
11625 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
11626 return false;
11628 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
11629 GET_MODE (mem), mem, load_p) == NO_REGS;
11632 /* Emit a move from SRC to DEST, given that one of them is a register
11633 save slot and that the other is a register. TEMP is a temporary
11634 GPR of the same mode that is available if need be. */
11636 void
11637 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
11639 unsigned int regno;
11640 rtx mem;
11642 if (REG_P (src))
11644 regno = REGNO (src);
11645 mem = dest;
11647 else
11649 regno = REGNO (dest);
11650 mem = src;
11653 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
11655 /* We don't yet know whether we'll need this instruction or not.
11656 Postpone the decision by emitting a ghost move. This move
11657 is specifically not frame-related; only the split version is. */
11658 if (TARGET_64BIT)
11659 emit_insn (gen_move_gpdi (dest, src));
11660 else
11661 emit_insn (gen_move_gpsi (dest, src));
11662 return;
11665 if (regno == HI_REGNUM)
11667 if (REG_P (dest))
11669 mips_emit_move (temp, src);
11670 if (TARGET_64BIT)
11671 emit_insn (gen_mthidi_ti (gen_rtx_REG (TImode, MD_REG_FIRST),
11672 temp, gen_rtx_REG (DImode, LO_REGNUM)));
11673 else
11674 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
11675 temp, gen_rtx_REG (SImode, LO_REGNUM)));
11677 else
11679 if (TARGET_64BIT)
11680 emit_insn (gen_mfhidi_ti (temp,
11681 gen_rtx_REG (TImode, MD_REG_FIRST)));
11682 else
11683 emit_insn (gen_mfhisi_di (temp,
11684 gen_rtx_REG (DImode, MD_REG_FIRST)));
11685 mips_emit_move (dest, temp);
11688 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
11689 mips_emit_move (dest, src);
11690 else
11692 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
11693 mips_emit_move (temp, src);
11694 mips_emit_move (dest, temp);
11696 if (MEM_P (dest))
11697 mips_set_frame_expr (mips_frame_set (dest, src));
11700 /* If we're generating n32 or n64 abicalls, and the current function
11701 does not use $28 as its global pointer, emit a cplocal directive.
11702 Use pic_offset_table_rtx as the argument to the directive. */
11704 static void
11705 mips_output_cplocal (void)
11707 if (!TARGET_EXPLICIT_RELOCS
11708 && mips_must_initialize_gp_p ()
11709 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
11710 output_asm_insn (".cplocal %+", 0);
11713 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
11715 static void
11716 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11718 const char *fnname;
11720 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
11721 floating-point arguments. */
11722 if (TARGET_MIPS16
11723 && TARGET_HARD_FLOAT_ABI
11724 && crtl->args.info.fp_code != 0)
11725 mips16_build_function_stub ();
11727 /* Get the function name the same way that toplev.c does before calling
11728 assemble_start_function. This is needed so that the name used here
11729 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11730 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
11731 mips_start_function_definition (fnname, TARGET_MIPS16);
11733 /* Output MIPS-specific frame information. */
11734 if (!flag_inhibit_size_directive)
11736 const struct mips_frame_info *frame;
11738 frame = &cfun->machine->frame;
11740 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
11741 fprintf (file,
11742 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
11743 "# vars= " HOST_WIDE_INT_PRINT_DEC
11744 ", regs= %d/%d"
11745 ", args= " HOST_WIDE_INT_PRINT_DEC
11746 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
11747 reg_names[frame_pointer_needed
11748 ? HARD_FRAME_POINTER_REGNUM
11749 : STACK_POINTER_REGNUM],
11750 (frame_pointer_needed
11751 ? frame->total_size - frame->hard_frame_pointer_offset
11752 : frame->total_size),
11753 reg_names[RETURN_ADDR_REGNUM],
11754 frame->var_size,
11755 frame->num_gp, frame->num_fp,
11756 frame->args_size,
11757 frame->cprestore_size);
11759 /* .mask MASK, OFFSET. */
11760 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
11761 frame->mask, frame->gp_save_offset);
11763 /* .fmask MASK, OFFSET. */
11764 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
11765 frame->fmask, frame->fp_save_offset);
11768 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
11769 Also emit the ".set noreorder; .set nomacro" sequence for functions
11770 that need it. */
11771 if (mips_must_initialize_gp_p ()
11772 && mips_current_loadgp_style () == LOADGP_OLDABI)
11774 if (TARGET_MIPS16)
11776 /* This is a fixed-form sequence. The position of the
11777 first two instructions is important because of the
11778 way _gp_disp is defined. */
11779 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
11780 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
11781 output_asm_insn ("sll\t$2,16", 0);
11782 output_asm_insn ("addu\t$2,$3", 0);
11784 else
11786 /* .cpload must be in a .set noreorder but not a
11787 .set nomacro block. */
11788 mips_push_asm_switch (&mips_noreorder);
11789 output_asm_insn (".cpload\t%^", 0);
11790 if (!cfun->machine->all_noreorder_p)
11791 mips_pop_asm_switch (&mips_noreorder);
11792 else
11793 mips_push_asm_switch (&mips_nomacro);
11796 else if (cfun->machine->all_noreorder_p)
11798 mips_push_asm_switch (&mips_noreorder);
11799 mips_push_asm_switch (&mips_nomacro);
11802 /* Tell the assembler which register we're using as the global
11803 pointer. This is needed for thunks, since they can use either
11804 explicit relocs or assembler macros. */
11805 mips_output_cplocal ();
11808 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
11810 static void
11811 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
11812 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11814 const char *fnname;
11816 /* Reinstate the normal $gp. */
11817 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
11818 mips_output_cplocal ();
11820 if (cfun->machine->all_noreorder_p)
11822 mips_pop_asm_switch (&mips_nomacro);
11823 mips_pop_asm_switch (&mips_noreorder);
11826 /* Get the function name the same way that toplev.c does before calling
11827 assemble_start_function. This is needed so that the name used here
11828 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11829 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
11830 mips_end_function_definition (fnname);
11833 /* Emit an optimisation barrier for accesses to the current frame. */
11835 static void
11836 mips_frame_barrier (void)
11838 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
11842 /* The __gnu_local_gp symbol. */
11844 static GTY(()) rtx mips_gnu_local_gp;
11846 /* If we're generating n32 or n64 abicalls, emit instructions
11847 to set up the global pointer. */
11849 static void
11850 mips_emit_loadgp (void)
11852 rtx addr, offset, incoming_address, base, index, pic_reg;
11854 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11855 switch (mips_current_loadgp_style ())
11857 case LOADGP_ABSOLUTE:
11858 if (mips_gnu_local_gp == NULL)
11860 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
11861 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
11863 emit_insn (PMODE_INSN (gen_loadgp_absolute,
11864 (pic_reg, mips_gnu_local_gp)));
11865 break;
11867 case LOADGP_OLDABI:
11868 /* Added by mips_output_function_prologue. */
11869 break;
11871 case LOADGP_NEWABI:
11872 addr = XEXP (DECL_RTL (current_function_decl), 0);
11873 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
11874 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
11875 emit_insn (PMODE_INSN (gen_loadgp_newabi,
11876 (pic_reg, offset, incoming_address)));
11877 break;
11879 case LOADGP_RTP:
11880 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
11881 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
11882 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
11883 break;
11885 default:
11886 return;
11889 if (TARGET_MIPS16)
11890 emit_insn (PMODE_INSN (gen_copygp_mips16,
11891 (pic_offset_table_rtx, pic_reg)));
11893 /* Emit a blockage if there are implicit uses of the GP register.
11894 This includes profiled functions, because FUNCTION_PROFILE uses
11895 a jal macro. */
11896 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
11897 emit_insn (gen_loadgp_blockage ());
11900 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11902 #if PROBE_INTERVAL > 32768
11903 #error Cannot use indexed addressing mode for stack probing
11904 #endif
11906 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11907 inclusive. These are offsets from the current stack pointer. */
11909 static void
11910 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
11912 if (TARGET_MIPS16)
11913 sorry ("-fstack-check=specific not implemented for MIPS16");
11915 /* See if we have a constant small number of probes to generate. If so,
11916 that's the easy case. */
11917 if (first + size <= 32768)
11919 HOST_WIDE_INT i;
11921 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11922 it exceeds SIZE. If only one probe is needed, this will not
11923 generate any code. Then probe at FIRST + SIZE. */
11924 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
11925 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
11926 -(first + i)));
11928 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
11929 -(first + size)));
11932 /* Otherwise, do the same as above, but in a loop. Note that we must be
11933 extra careful with variables wrapping around because we might be at
11934 the very top (or the very bottom) of the address space and we have
11935 to be able to handle this case properly; in particular, we use an
11936 equality test for the loop condition. */
11937 else
11939 HOST_WIDE_INT rounded_size;
11940 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
11941 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
11943 /* Sanity check for the addressing mode we're going to use. */
11944 gcc_assert (first <= 32768);
11947 /* Step 1: round SIZE to the previous multiple of the interval. */
11949 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
11952 /* Step 2: compute initial and final value of the loop counter. */
11954 /* TEST_ADDR = SP + FIRST. */
11955 emit_insn (gen_rtx_SET (r3, plus_constant (Pmode, stack_pointer_rtx,
11956 -first)));
11958 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
11959 if (rounded_size > 32768)
11961 emit_move_insn (r12, GEN_INT (rounded_size));
11962 emit_insn (gen_rtx_SET (r12, gen_rtx_MINUS (Pmode, r3, r12)));
11964 else
11965 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, r3,
11966 -rounded_size)));
11969 /* Step 3: the loop
11973 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11974 probe at TEST_ADDR
11976 while (TEST_ADDR != LAST_ADDR)
11978 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11979 until it is equal to ROUNDED_SIZE. */
11981 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
11984 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11985 that SIZE is equal to ROUNDED_SIZE. */
11987 if (size != rounded_size)
11988 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
11991 /* Make sure nothing is scheduled before we are done. */
11992 emit_insn (gen_blockage ());
11995 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11996 absolute addresses. */
11998 const char *
11999 mips_output_probe_stack_range (rtx reg1, rtx reg2)
12001 static int labelno = 0;
12002 char loop_lab[32], tmp[64];
12003 rtx xops[2];
12005 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
12007 /* Loop. */
12008 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
12010 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
12011 xops[0] = reg1;
12012 xops[1] = GEN_INT (-PROBE_INTERVAL);
12013 if (TARGET_64BIT && TARGET_LONG64)
12014 output_asm_insn ("daddiu\t%0,%0,%1", xops);
12015 else
12016 output_asm_insn ("addiu\t%0,%0,%1", xops);
12018 /* Probe at TEST_ADDR, test if TEST_ADDR == LAST_ADDR and branch. */
12019 xops[1] = reg2;
12020 strcpy (tmp, "%(%<bne\t%0,%1,");
12021 output_asm_insn (strcat (tmp, &loop_lab[1]), xops);
12022 if (TARGET_64BIT)
12023 output_asm_insn ("sd\t$0,0(%0)%)", xops);
12024 else
12025 output_asm_insn ("sw\t$0,0(%0)%)", xops);
12027 return "";
12030 /* Return true if X contains a kernel register. */
12032 static bool
12033 mips_refers_to_kernel_reg_p (const_rtx x)
12035 subrtx_iterator::array_type array;
12036 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
12037 if (REG_P (*iter) && KERNEL_REG_P (REGNO (*iter)))
12038 return true;
12039 return false;
12042 /* Expand the "prologue" pattern. */
12044 void
12045 mips_expand_prologue (void)
12047 const struct mips_frame_info *frame;
12048 HOST_WIDE_INT size;
12049 unsigned int nargs;
12051 if (cfun->machine->global_pointer != INVALID_REGNUM)
12053 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
12054 or implicitly. If so, we can commit to using a global pointer
12055 straight away, otherwise we need to defer the decision. */
12056 if (mips_cfun_has_inflexible_gp_ref_p ()
12057 || mips_cfun_has_flexible_gp_ref_p ())
12059 cfun->machine->must_initialize_gp_p = true;
12060 cfun->machine->must_restore_gp_when_clobbered_p = true;
12063 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
12066 frame = &cfun->machine->frame;
12067 size = frame->total_size;
12069 if (flag_stack_usage_info)
12070 current_function_static_stack_size = size;
12072 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
12074 if (crtl->is_leaf && !cfun->calls_alloca)
12076 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
12077 mips_emit_probe_stack_range (STACK_CHECK_PROTECT,
12078 size - STACK_CHECK_PROTECT);
12080 else if (size > 0)
12081 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
12084 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
12085 bytes beforehand; this is enough to cover the register save area
12086 without going out of range. */
12087 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
12088 || frame->num_cop0_regs > 0)
12090 HOST_WIDE_INT step1;
12092 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
12093 if (GENERATE_MIPS16E_SAVE_RESTORE)
12095 HOST_WIDE_INT offset;
12096 unsigned int mask, regno;
12098 /* Try to merge argument stores into the save instruction. */
12099 nargs = mips16e_collect_argument_saves ();
12101 /* Build the save instruction. */
12102 mask = frame->mask;
12103 rtx insn = mips16e_build_save_restore (false, &mask, &offset,
12104 nargs, step1);
12105 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
12106 mips_frame_barrier ();
12107 size -= step1;
12109 /* Check if we need to save other registers. */
12110 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
12111 if (BITSET_P (mask, regno - GP_REG_FIRST))
12113 offset -= UNITS_PER_WORD;
12114 mips_save_restore_reg (word_mode, regno,
12115 offset, mips_save_reg);
12118 else
12120 if (cfun->machine->interrupt_handler_p)
12122 HOST_WIDE_INT offset;
12123 rtx mem;
12125 /* If this interrupt is using a shadow register set, we need to
12126 get the stack pointer from the previous register set. */
12127 if (cfun->machine->use_shadow_register_set == SHADOW_SET_YES)
12128 emit_insn (PMODE_INSN (gen_mips_rdpgpr, (stack_pointer_rtx,
12129 stack_pointer_rtx)));
12131 if (!cfun->machine->keep_interrupts_masked_p)
12133 if (cfun->machine->int_mask == INT_MASK_EIC)
12134 /* Move from COP0 Cause to K0. */
12135 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
12136 gen_rtx_REG (SImode, COP0_CAUSE_REG_NUM)));
12138 /* Move from COP0 EPC to K1. */
12139 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
12140 gen_rtx_REG (SImode,
12141 COP0_EPC_REG_NUM)));
12143 /* Allocate the first part of the frame. */
12144 rtx insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
12145 GEN_INT (-step1));
12146 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
12147 mips_frame_barrier ();
12148 size -= step1;
12150 /* Start at the uppermost location for saving. */
12151 offset = frame->cop0_sp_offset - size;
12153 /* Push EPC into its stack slot. */
12154 mem = gen_frame_mem (word_mode,
12155 plus_constant (Pmode, stack_pointer_rtx,
12156 offset));
12157 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
12158 offset -= UNITS_PER_WORD;
12160 /* Move from COP0 Status to K1. */
12161 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
12162 gen_rtx_REG (SImode,
12163 COP0_STATUS_REG_NUM)));
12165 /* Right justify the RIPL in k0. */
12166 if (!cfun->machine->keep_interrupts_masked_p
12167 && cfun->machine->int_mask == INT_MASK_EIC)
12168 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
12169 gen_rtx_REG (SImode, K0_REG_NUM),
12170 GEN_INT (CAUSE_IPL)));
12172 /* Push Status into its stack slot. */
12173 mem = gen_frame_mem (word_mode,
12174 plus_constant (Pmode, stack_pointer_rtx,
12175 offset));
12176 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
12177 offset -= UNITS_PER_WORD;
12179 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
12180 if (!cfun->machine->keep_interrupts_masked_p
12181 && cfun->machine->int_mask == INT_MASK_EIC)
12182 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
12183 GEN_INT (6),
12184 GEN_INT (SR_IPL),
12185 gen_rtx_REG (SImode, K0_REG_NUM)));
12187 /* Clear all interrupt mask bits up to and including the
12188 handler's interrupt line. */
12189 if (!cfun->machine->keep_interrupts_masked_p
12190 && cfun->machine->int_mask != INT_MASK_EIC)
12191 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
12192 GEN_INT (cfun->machine->int_mask + 1),
12193 GEN_INT (SR_IM0),
12194 gen_rtx_REG (SImode, GP_REG_FIRST)));
12196 if (!cfun->machine->keep_interrupts_masked_p)
12197 /* Enable interrupts by clearing the KSU ERL and EXL bits.
12198 IE is already the correct value, so we don't have to do
12199 anything explicit. */
12200 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
12201 GEN_INT (4),
12202 GEN_INT (SR_EXL),
12203 gen_rtx_REG (SImode, GP_REG_FIRST)));
12204 else
12205 /* Disable interrupts by clearing the KSU, ERL, EXL,
12206 and IE bits. */
12207 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
12208 GEN_INT (5),
12209 GEN_INT (SR_IE),
12210 gen_rtx_REG (SImode, GP_REG_FIRST)));
12212 if (TARGET_HARD_FLOAT)
12213 /* Disable COP1 for hard-float. This will lead to an exception
12214 if floating-point code is executed in an ISR. */
12215 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
12216 GEN_INT (1),
12217 GEN_INT (SR_COP1),
12218 gen_rtx_REG (SImode, GP_REG_FIRST)));
12220 else
12222 if (step1 != 0)
12224 rtx insn = gen_add3_insn (stack_pointer_rtx,
12225 stack_pointer_rtx,
12226 GEN_INT (-step1));
12227 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
12228 mips_frame_barrier ();
12229 size -= step1;
12232 mips_for_each_saved_acc (size, mips_save_reg);
12233 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
12237 /* Allocate the rest of the frame. */
12238 if (size > 0)
12240 if (SMALL_OPERAND (-size))
12241 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
12242 stack_pointer_rtx,
12243 GEN_INT (-size)))) = 1;
12244 else
12246 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
12247 if (TARGET_MIPS16)
12249 /* There are no instructions to add or subtract registers
12250 from the stack pointer, so use the frame pointer as a
12251 temporary. We should always be using a frame pointer
12252 in this case anyway. */
12253 gcc_assert (frame_pointer_needed);
12254 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
12255 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
12256 hard_frame_pointer_rtx,
12257 MIPS_PROLOGUE_TEMP (Pmode)));
12258 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
12260 else
12261 emit_insn (gen_sub3_insn (stack_pointer_rtx,
12262 stack_pointer_rtx,
12263 MIPS_PROLOGUE_TEMP (Pmode)));
12265 /* Describe the combined effect of the previous instructions. */
12266 mips_set_frame_expr
12267 (gen_rtx_SET (stack_pointer_rtx,
12268 plus_constant (Pmode, stack_pointer_rtx, -size)));
12270 mips_frame_barrier ();
12273 /* Set up the frame pointer, if we're using one. */
12274 if (frame_pointer_needed)
12276 HOST_WIDE_INT offset;
12278 offset = frame->hard_frame_pointer_offset;
12279 if (offset == 0)
12281 rtx insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
12282 RTX_FRAME_RELATED_P (insn) = 1;
12284 else if (SMALL_OPERAND (offset))
12286 rtx insn = gen_add3_insn (hard_frame_pointer_rtx,
12287 stack_pointer_rtx, GEN_INT (offset));
12288 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
12290 else
12292 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
12293 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
12294 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
12295 hard_frame_pointer_rtx,
12296 MIPS_PROLOGUE_TEMP (Pmode)));
12297 mips_set_frame_expr
12298 (gen_rtx_SET (hard_frame_pointer_rtx,
12299 plus_constant (Pmode, stack_pointer_rtx, offset)));
12303 mips_emit_loadgp ();
12305 /* Initialize the $gp save slot. */
12306 if (mips_cfun_has_cprestore_slot_p ())
12308 rtx base, mem, gp, temp;
12309 HOST_WIDE_INT offset;
12311 mips_get_cprestore_base_and_offset (&base, &offset, false);
12312 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
12313 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
12314 temp = (SMALL_OPERAND (offset)
12315 ? gen_rtx_SCRATCH (Pmode)
12316 : MIPS_PROLOGUE_TEMP (Pmode));
12317 emit_insn (PMODE_INSN (gen_potential_cprestore,
12318 (mem, GEN_INT (offset), gp, temp)));
12320 mips_get_cprestore_base_and_offset (&base, &offset, true);
12321 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
12322 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
12325 /* We need to search back to the last use of K0 or K1. */
12326 if (cfun->machine->interrupt_handler_p)
12328 rtx_insn *insn;
12329 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
12330 if (INSN_P (insn)
12331 && mips_refers_to_kernel_reg_p (PATTERN (insn)))
12332 break;
12333 /* Emit a move from K1 to COP0 Status after insn. */
12334 gcc_assert (insn != NULL_RTX);
12335 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
12336 gen_rtx_REG (SImode, K1_REG_NUM)),
12337 insn);
12340 /* If we are profiling, make sure no instructions are scheduled before
12341 the call to mcount. */
12342 if (crtl->profile)
12343 emit_insn (gen_blockage ());
12346 /* Attach all pending register saves to the previous instruction.
12347 Return that instruction. */
12349 static rtx_insn *
12350 mips_epilogue_emit_cfa_restores (void)
12352 rtx_insn *insn;
12354 insn = get_last_insn ();
12355 if (mips_epilogue.cfa_restores)
12357 gcc_assert (insn && !REG_NOTES (insn));
12358 RTX_FRAME_RELATED_P (insn) = 1;
12359 REG_NOTES (insn) = mips_epilogue.cfa_restores;
12360 mips_epilogue.cfa_restores = 0;
12362 return insn;
12365 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
12366 now at REG + OFFSET. */
12368 static void
12369 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
12371 rtx_insn *insn;
12373 insn = mips_epilogue_emit_cfa_restores ();
12374 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
12376 RTX_FRAME_RELATED_P (insn) = 1;
12377 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
12378 plus_constant (Pmode, reg, offset),
12379 REG_NOTES (insn));
12380 mips_epilogue.cfa_reg = reg;
12381 mips_epilogue.cfa_offset = offset;
12385 /* Emit instructions to restore register REG from slot MEM. Also update
12386 the cfa_restores list. */
12388 static void
12389 mips_restore_reg (rtx reg, rtx mem)
12391 /* There's no MIPS16 instruction to load $31 directly. Load into
12392 $7 instead and adjust the return insn appropriately. */
12393 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
12394 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
12395 else if (GET_MODE (reg) == DFmode
12396 && (!TARGET_FLOAT64
12397 || mips_abi == ABI_32))
12399 mips_add_cfa_restore (mips_subword (reg, true));
12400 mips_add_cfa_restore (mips_subword (reg, false));
12402 else
12403 mips_add_cfa_restore (reg);
12405 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
12406 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
12407 /* The CFA is currently defined in terms of the register whose
12408 value we have just restored. Redefine the CFA in terms of
12409 the stack pointer. */
12410 mips_epilogue_set_cfa (stack_pointer_rtx,
12411 mips_epilogue.cfa_restore_sp_offset);
12414 /* Emit code to set the stack pointer to BASE + OFFSET, given that
12415 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
12416 BASE, if not the stack pointer, is available as a temporary. */
12418 static void
12419 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
12421 if (base == stack_pointer_rtx && offset == const0_rtx)
12422 return;
12424 mips_frame_barrier ();
12425 if (offset == const0_rtx)
12427 emit_move_insn (stack_pointer_rtx, base);
12428 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
12430 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
12432 emit_insn (gen_add3_insn (base, base, offset));
12433 mips_epilogue_set_cfa (base, new_frame_size);
12434 emit_move_insn (stack_pointer_rtx, base);
12436 else
12438 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
12439 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
12443 /* Emit any instructions needed before a return. */
12445 void
12446 mips_expand_before_return (void)
12448 /* When using a call-clobbered gp, we start out with unified call
12449 insns that include instructions to restore the gp. We then split
12450 these unified calls after reload. These split calls explicitly
12451 clobber gp, so there is no need to define
12452 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
12454 For consistency, we should also insert an explicit clobber of $28
12455 before return insns, so that the post-reload optimizers know that
12456 the register is not live on exit. */
12457 if (TARGET_CALL_CLOBBERED_GP)
12458 emit_clobber (pic_offset_table_rtx);
12461 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
12462 says which. */
12464 void
12465 mips_expand_epilogue (bool sibcall_p)
12467 const struct mips_frame_info *frame;
12468 HOST_WIDE_INT step1, step2;
12469 rtx base, adjust;
12470 rtx_insn *insn;
12471 bool use_jraddiusp_p = false;
12473 if (!sibcall_p && mips_can_use_return_insn ())
12475 emit_jump_insn (gen_return ());
12476 return;
12479 /* In MIPS16 mode, if the return value should go into a floating-point
12480 register, we need to call a helper routine to copy it over. */
12481 if (mips16_cfun_returns_in_fpr_p ())
12482 mips16_copy_fpr_return_value ();
12484 /* Split the frame into two. STEP1 is the amount of stack we should
12485 deallocate before restoring the registers. STEP2 is the amount we
12486 should deallocate afterwards.
12488 Start off by assuming that no registers need to be restored. */
12489 frame = &cfun->machine->frame;
12490 step1 = frame->total_size;
12491 step2 = 0;
12493 /* Work out which register holds the frame address. */
12494 if (!frame_pointer_needed)
12495 base = stack_pointer_rtx;
12496 else
12498 base = hard_frame_pointer_rtx;
12499 step1 -= frame->hard_frame_pointer_offset;
12501 mips_epilogue.cfa_reg = base;
12502 mips_epilogue.cfa_offset = step1;
12503 mips_epilogue.cfa_restores = NULL_RTX;
12505 /* If we need to restore registers, deallocate as much stack as
12506 possible in the second step without going out of range. */
12507 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
12508 || frame->num_cop0_regs > 0)
12510 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
12511 step1 -= step2;
12514 /* Get an rtx for STEP1 that we can add to BASE. */
12515 adjust = GEN_INT (step1);
12516 if (!SMALL_OPERAND (step1))
12518 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
12519 adjust = MIPS_EPILOGUE_TEMP (Pmode);
12521 mips_deallocate_stack (base, adjust, step2);
12523 /* If we're using addressing macros, $gp is implicitly used by all
12524 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
12525 from the stack. */
12526 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
12527 emit_insn (gen_blockage ());
12529 mips_epilogue.cfa_restore_sp_offset = step2;
12530 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
12532 unsigned int regno, mask;
12533 HOST_WIDE_INT offset;
12534 rtx restore;
12536 /* Generate the restore instruction. */
12537 mask = frame->mask;
12538 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
12540 /* Restore any other registers manually. */
12541 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
12542 if (BITSET_P (mask, regno - GP_REG_FIRST))
12544 offset -= UNITS_PER_WORD;
12545 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
12548 /* Restore the remaining registers and deallocate the final bit
12549 of the frame. */
12550 mips_frame_barrier ();
12551 emit_insn (restore);
12552 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
12554 else
12556 /* Restore the registers. */
12557 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
12558 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
12559 mips_restore_reg);
12561 if (cfun->machine->interrupt_handler_p)
12563 HOST_WIDE_INT offset;
12564 rtx mem;
12566 offset = frame->cop0_sp_offset - (frame->total_size - step2);
12568 /* Restore the original EPC. */
12569 mem = gen_frame_mem (word_mode,
12570 plus_constant (Pmode, stack_pointer_rtx,
12571 offset));
12572 mips_emit_move (gen_rtx_REG (word_mode, K1_REG_NUM), mem);
12573 offset -= UNITS_PER_WORD;
12575 /* Move to COP0 EPC. */
12576 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
12577 gen_rtx_REG (SImode, K1_REG_NUM)));
12579 /* Restore the original Status. */
12580 mem = gen_frame_mem (word_mode,
12581 plus_constant (Pmode, stack_pointer_rtx,
12582 offset));
12583 mips_emit_move (gen_rtx_REG (word_mode, K1_REG_NUM), mem);
12584 offset -= UNITS_PER_WORD;
12586 /* If we don't use shadow register set, we need to update SP. */
12587 if (cfun->machine->use_shadow_register_set == SHADOW_SET_NO)
12588 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
12589 else
12590 /* The choice of position is somewhat arbitrary in this case. */
12591 mips_epilogue_emit_cfa_restores ();
12593 /* Move to COP0 Status. */
12594 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
12595 gen_rtx_REG (SImode, K1_REG_NUM)));
12597 else if (TARGET_MICROMIPS
12598 && !crtl->calls_eh_return
12599 && !sibcall_p
12600 && step2 > 0
12601 && mips_unsigned_immediate_p (step2, 5, 2))
12602 use_jraddiusp_p = true;
12603 else
12604 /* Deallocate the final bit of the frame. */
12605 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
12608 if (cfun->machine->use_frame_header_for_callee_saved_regs)
12609 mips_epilogue_emit_cfa_restores ();
12610 else if (!use_jraddiusp_p)
12611 gcc_assert (!mips_epilogue.cfa_restores);
12613 /* Add in the __builtin_eh_return stack adjustment. We need to
12614 use a temporary in MIPS16 code. */
12615 if (crtl->calls_eh_return)
12617 if (TARGET_MIPS16)
12619 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
12620 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
12621 MIPS_EPILOGUE_TEMP (Pmode),
12622 EH_RETURN_STACKADJ_RTX));
12623 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
12625 else
12626 emit_insn (gen_add3_insn (stack_pointer_rtx,
12627 stack_pointer_rtx,
12628 EH_RETURN_STACKADJ_RTX));
12631 if (!sibcall_p)
12633 mips_expand_before_return ();
12634 if (cfun->machine->interrupt_handler_p)
12636 /* Interrupt handlers generate eret or deret. */
12637 if (cfun->machine->use_debug_exception_return_p)
12638 emit_jump_insn (gen_mips_deret ());
12639 else
12640 emit_jump_insn (gen_mips_eret ());
12642 else
12644 rtx pat;
12646 /* When generating MIPS16 code, the normal
12647 mips_for_each_saved_gpr_and_fpr path will restore the return
12648 address into $7 rather than $31. */
12649 if (TARGET_MIPS16
12650 && !GENERATE_MIPS16E_SAVE_RESTORE
12651 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
12653 /* simple_returns cannot rely on values that are only available
12654 on paths through the epilogue (because return paths that do
12655 not pass through the epilogue may nevertheless reuse a
12656 simple_return that occurs at the end of the epilogue).
12657 Use a normal return here instead. */
12658 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
12659 pat = gen_return_internal (reg);
12661 else if (use_jraddiusp_p)
12662 pat = gen_jraddiusp (GEN_INT (step2));
12663 else
12665 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
12666 pat = gen_simple_return_internal (reg);
12668 emit_jump_insn (pat);
12669 if (use_jraddiusp_p)
12670 mips_epilogue_set_cfa (stack_pointer_rtx, step2);
12674 /* Search from the beginning to the first use of K0 or K1. */
12675 if (cfun->machine->interrupt_handler_p
12676 && !cfun->machine->keep_interrupts_masked_p)
12678 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
12679 if (INSN_P (insn)
12680 && mips_refers_to_kernel_reg_p (PATTERN (insn)))
12681 break;
12682 gcc_assert (insn != NULL_RTX);
12683 /* Insert disable interrupts before the first use of K0 or K1. */
12684 emit_insn_before (gen_mips_di (), insn);
12685 emit_insn_before (gen_mips_ehb (), insn);
12689 /* Return nonzero if this function is known to have a null epilogue.
12690 This allows the optimizer to omit jumps to jumps if no stack
12691 was created. */
12693 bool
12694 mips_can_use_return_insn (void)
12696 /* Interrupt handlers need to go through the epilogue. */
12697 if (cfun->machine->interrupt_handler_p)
12698 return false;
12700 if (!reload_completed)
12701 return false;
12703 if (crtl->profile)
12704 return false;
12706 /* In MIPS16 mode, a function that returns a floating-point value
12707 needs to arrange to copy the return value into the floating-point
12708 registers. */
12709 if (mips16_cfun_returns_in_fpr_p ())
12710 return false;
12712 return (cfun->machine->frame.total_size == 0
12713 && !cfun->machine->use_frame_header_for_callee_saved_regs);
12716 /* Return true if register REGNO can store a value of mode MODE.
12717 The result of this function is cached in mips_hard_regno_mode_ok. */
12719 static bool
12720 mips_hard_regno_mode_ok_p (unsigned int regno, machine_mode mode)
12722 unsigned int size;
12723 enum mode_class mclass;
12725 if (mode == CCV2mode)
12726 return (ISA_HAS_8CC
12727 && ST_REG_P (regno)
12728 && (regno - ST_REG_FIRST) % 2 == 0);
12730 if (mode == CCV4mode)
12731 return (ISA_HAS_8CC
12732 && ST_REG_P (regno)
12733 && (regno - ST_REG_FIRST) % 4 == 0);
12735 if (mode == CCmode)
12736 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
12738 size = GET_MODE_SIZE (mode);
12739 mclass = GET_MODE_CLASS (mode);
12741 if (GP_REG_P (regno) && mode != CCFmode && !MSA_SUPPORTED_MODE_P (mode))
12742 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
12744 /* For MSA, allow TImode and 128-bit vector modes in all FPR. */
12745 if (FP_REG_P (regno) && MSA_SUPPORTED_MODE_P (mode))
12746 return true;
12748 if (FP_REG_P (regno)
12749 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
12750 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
12752 /* Deny use of odd-numbered registers for 32-bit data for
12753 the o32 FP64A ABI. */
12754 if (TARGET_O32_FP64A_ABI && size <= 4 && (regno & 1) != 0)
12755 return false;
12757 /* The FPXX ABI requires double-precision values to be placed in
12758 even-numbered registers. Disallow odd-numbered registers with
12759 CCFmode because CCFmode double-precision compares will write a
12760 64-bit value to a register. */
12761 if (mode == CCFmode)
12762 return !(TARGET_FLOATXX && (regno & 1) != 0);
12764 /* Allow 64-bit vector modes for Loongson-2E/2F. */
12765 if (TARGET_LOONGSON_VECTORS
12766 && (mode == V2SImode
12767 || mode == V4HImode
12768 || mode == V8QImode
12769 || mode == DImode))
12770 return true;
12772 if (mclass == MODE_FLOAT
12773 || mclass == MODE_COMPLEX_FLOAT
12774 || mclass == MODE_VECTOR_FLOAT)
12775 return size <= UNITS_PER_FPVALUE;
12777 /* Allow integer modes that fit into a single register. We need
12778 to put integers into FPRs when using instructions like CVT
12779 and TRUNC. There's no point allowing sizes smaller than a word,
12780 because the FPU has no appropriate load/store instructions. */
12781 if (mclass == MODE_INT)
12782 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
12785 /* Don't allow vector modes in accumulators. */
12786 if (ACC_REG_P (regno)
12787 && !VECTOR_MODE_P (mode)
12788 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
12790 if (MD_REG_P (regno))
12792 /* After a multiplication or division, clobbering HI makes
12793 the value of LO unpredictable, and vice versa. This means
12794 that, for all interesting cases, HI and LO are effectively
12795 a single register.
12797 We model this by requiring that any value that uses HI
12798 also uses LO. */
12799 if (size <= UNITS_PER_WORD * 2)
12800 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
12802 else
12804 /* DSP accumulators do not have the same restrictions as
12805 HI and LO, so we can treat them as normal doubleword
12806 registers. */
12807 if (size <= UNITS_PER_WORD)
12808 return true;
12810 if (size <= UNITS_PER_WORD * 2
12811 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
12812 return true;
12816 if (ALL_COP_REG_P (regno))
12817 return mclass == MODE_INT && size <= UNITS_PER_WORD;
12819 if (regno == GOT_VERSION_REGNUM)
12820 return mode == SImode;
12822 return false;
12825 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
12827 bool
12828 mips_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
12829 unsigned int new_reg)
12831 /* Interrupt functions can only use registers that have already been
12832 saved by the prologue, even if they would normally be call-clobbered. */
12833 if (cfun->machine->interrupt_handler_p && !df_regs_ever_live_p (new_reg))
12834 return false;
12836 return true;
12839 /* Return nonzero if register REGNO can be used as a scratch register
12840 in peephole2. */
12842 bool
12843 mips_hard_regno_scratch_ok (unsigned int regno)
12845 /* See mips_hard_regno_rename_ok. */
12846 if (cfun->machine->interrupt_handler_p && !df_regs_ever_live_p (regno))
12847 return false;
12849 return true;
12852 /* Implement HARD_REGNO_NREGS. */
12854 unsigned int
12855 mips_hard_regno_nregs (int regno, machine_mode mode)
12857 if (ST_REG_P (regno))
12858 /* The size of FP status registers is always 4, because they only hold
12859 CCmode values, and CCmode is always considered to be 4 bytes wide. */
12860 return (GET_MODE_SIZE (mode) + 3) / 4;
12862 if (FP_REG_P (regno))
12864 if (MSA_SUPPORTED_MODE_P (mode))
12865 return 1;
12867 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
12870 /* All other registers are word-sized. */
12871 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
12874 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
12875 in mips_hard_regno_nregs. */
12878 mips_class_max_nregs (enum reg_class rclass, machine_mode mode)
12880 int size;
12881 HARD_REG_SET left;
12883 size = 0x8000;
12884 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
12885 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
12887 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
12888 size = MIN (size, 4);
12890 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
12892 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
12894 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
12896 if (MSA_SUPPORTED_MODE_P (mode))
12897 size = MIN (size, UNITS_PER_MSA_REG);
12898 else
12899 size = MIN (size, UNITS_PER_FPREG);
12902 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
12904 if (!hard_reg_set_empty_p (left))
12905 size = MIN (size, UNITS_PER_WORD);
12906 return (GET_MODE_SIZE (mode) + size - 1) / size;
12909 /* Implement CANNOT_CHANGE_MODE_CLASS. */
12911 bool
12912 mips_cannot_change_mode_class (machine_mode from,
12913 machine_mode to,
12914 enum reg_class rclass)
12916 /* Allow conversions between different Loongson integer vectors,
12917 and between those vectors and DImode. */
12918 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
12919 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
12920 return false;
12922 /* Allow conversions between different MSA vector modes. */
12923 if (MSA_SUPPORTED_MODE_P (from) && MSA_SUPPORTED_MODE_P (to))
12924 return false;
12926 /* Otherwise, there are several problems with changing the modes of
12927 values in floating-point registers:
12929 - When a multi-word value is stored in paired floating-point
12930 registers, the first register always holds the low word. We
12931 therefore can't allow FPRs to change between single-word and
12932 multi-word modes on big-endian targets.
12934 - GCC assumes that each word of a multiword register can be
12935 accessed individually using SUBREGs. This is not true for
12936 floating-point registers if they are bigger than a word.
12938 - Loading a 32-bit value into a 64-bit floating-point register
12939 will not sign-extend the value, despite what LOAD_EXTEND_OP
12940 says. We can't allow FPRs to change from SImode to a wider
12941 mode on 64-bit targets.
12943 - If the FPU has already interpreted a value in one format, we
12944 must not ask it to treat the value as having a different
12945 format.
12947 We therefore disallow all mode changes involving FPRs. */
12949 return reg_classes_intersect_p (FP_REGS, rclass);
12952 /* Implement target hook small_register_classes_for_mode_p. */
12954 static bool
12955 mips_small_register_classes_for_mode_p (machine_mode mode
12956 ATTRIBUTE_UNUSED)
12958 return TARGET_MIPS16;
12961 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction,
12962 or use the MSA's move.v instruction. */
12964 static bool
12965 mips_mode_ok_for_mov_fmt_p (machine_mode mode)
12967 switch (mode)
12969 case CCFmode:
12970 case SFmode:
12971 return TARGET_HARD_FLOAT;
12973 case DFmode:
12974 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
12976 case V2SFmode:
12977 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
12979 default:
12980 return MSA_SUPPORTED_MODE_P (mode);
12984 /* Implement MODES_TIEABLE_P. */
12986 bool
12987 mips_modes_tieable_p (machine_mode mode1, machine_mode mode2)
12989 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
12990 prefer to put one of them in FPRs. */
12991 return (mode1 == mode2
12992 || (!mips_mode_ok_for_mov_fmt_p (mode1)
12993 && !mips_mode_ok_for_mov_fmt_p (mode2)));
12996 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12998 static reg_class_t
12999 mips_preferred_reload_class (rtx x, reg_class_t rclass)
13001 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
13002 return LEA_REGS;
13004 if (reg_class_subset_p (FP_REGS, rclass)
13005 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
13006 return FP_REGS;
13008 if (reg_class_subset_p (GR_REGS, rclass))
13009 rclass = GR_REGS;
13011 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
13012 rclass = M16_REGS;
13014 return rclass;
13017 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
13018 Return a "canonical" class to represent it in later calculations. */
13020 static reg_class_t
13021 mips_canonicalize_move_class (reg_class_t rclass)
13023 /* All moves involving accumulator registers have the same cost. */
13024 if (reg_class_subset_p (rclass, ACC_REGS))
13025 rclass = ACC_REGS;
13027 /* Likewise promote subclasses of general registers to the most
13028 interesting containing class. */
13029 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
13030 rclass = M16_REGS;
13031 else if (reg_class_subset_p (rclass, GENERAL_REGS))
13032 rclass = GENERAL_REGS;
13034 return rclass;
13037 /* Return the cost of moving a value from a register of class FROM to a GPR.
13038 Return 0 for classes that are unions of other classes handled by this
13039 function. */
13041 static int
13042 mips_move_to_gpr_cost (reg_class_t from)
13044 switch (from)
13046 case M16_REGS:
13047 case GENERAL_REGS:
13048 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
13049 return 2;
13051 case ACC_REGS:
13052 /* MFLO and MFHI. */
13053 return 6;
13055 case FP_REGS:
13056 /* MFC1, etc. */
13057 return 4;
13059 case COP0_REGS:
13060 case COP2_REGS:
13061 case COP3_REGS:
13062 /* This choice of value is historical. */
13063 return 5;
13065 default:
13066 return 0;
13070 /* Return the cost of moving a value from a GPR to a register of class TO.
13071 Return 0 for classes that are unions of other classes handled by this
13072 function. */
13074 static int
13075 mips_move_from_gpr_cost (reg_class_t to)
13077 switch (to)
13079 case M16_REGS:
13080 case GENERAL_REGS:
13081 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
13082 return 2;
13084 case ACC_REGS:
13085 /* MTLO and MTHI. */
13086 return 6;
13088 case FP_REGS:
13089 /* MTC1, etc. */
13090 return 4;
13092 case COP0_REGS:
13093 case COP2_REGS:
13094 case COP3_REGS:
13095 /* This choice of value is historical. */
13096 return 5;
13098 default:
13099 return 0;
13103 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
13104 maximum of the move costs for subclasses; regclass will work out
13105 the maximum for us. */
13107 static int
13108 mips_register_move_cost (machine_mode mode,
13109 reg_class_t from, reg_class_t to)
13111 reg_class_t dregs;
13112 int cost1, cost2;
13114 from = mips_canonicalize_move_class (from);
13115 to = mips_canonicalize_move_class (to);
13117 /* Handle moves that can be done without using general-purpose registers. */
13118 if (from == FP_REGS)
13120 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
13121 /* MOV.FMT. */
13122 return 4;
13125 /* Handle cases in which only one class deviates from the ideal. */
13126 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
13127 if (from == dregs)
13128 return mips_move_from_gpr_cost (to);
13129 if (to == dregs)
13130 return mips_move_to_gpr_cost (from);
13132 /* Handles cases that require a GPR temporary. */
13133 cost1 = mips_move_to_gpr_cost (from);
13134 if (cost1 != 0)
13136 cost2 = mips_move_from_gpr_cost (to);
13137 if (cost2 != 0)
13138 return cost1 + cost2;
13141 return 0;
13144 /* Implement TARGET_REGISTER_PRIORITY. */
13146 static int
13147 mips_register_priority (int hard_regno)
13149 /* Treat MIPS16 registers with higher priority than other regs. */
13150 if (TARGET_MIPS16
13151 && TEST_HARD_REG_BIT (reg_class_contents[M16_REGS], hard_regno))
13152 return 1;
13153 return 0;
13156 /* Implement TARGET_MEMORY_MOVE_COST. */
13158 static int
13159 mips_memory_move_cost (machine_mode mode, reg_class_t rclass, bool in)
13161 return (mips_cost->memory_latency
13162 + memory_move_secondary_cost (mode, rclass, in));
13165 /* Implement SECONDARY_MEMORY_NEEDED. */
13167 bool
13168 mips_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
13169 machine_mode mode)
13171 /* Ignore spilled pseudos. */
13172 if (lra_in_progress && (class1 == NO_REGS || class2 == NO_REGS))
13173 return false;
13175 if (((class1 == FP_REGS) != (class2 == FP_REGS))
13176 && ((TARGET_FLOATXX && !ISA_HAS_MXHC1)
13177 || TARGET_O32_FP64A_ABI)
13178 && GET_MODE_SIZE (mode) >= 8)
13179 return true;
13181 return false;
13184 /* Return the register class required for a secondary register when
13185 copying between one of the registers in RCLASS and value X, which
13186 has mode MODE. X is the source of the move if IN_P, otherwise it
13187 is the destination. Return NO_REGS if no secondary register is
13188 needed. */
13190 enum reg_class
13191 mips_secondary_reload_class (enum reg_class rclass,
13192 machine_mode mode, rtx x, bool)
13194 int regno;
13196 /* If X is a constant that cannot be loaded into $25, it must be loaded
13197 into some other GPR. No other register class allows a direct move. */
13198 if (mips_dangerous_for_la25_p (x))
13199 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
13201 regno = true_regnum (x);
13202 if (TARGET_MIPS16)
13204 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
13205 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
13206 return M16_REGS;
13208 return NO_REGS;
13211 /* Copying from accumulator registers to anywhere other than a general
13212 register requires a temporary general register. */
13213 if (reg_class_subset_p (rclass, ACC_REGS))
13214 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
13215 if (ACC_REG_P (regno))
13216 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
13218 if (reg_class_subset_p (rclass, FP_REGS))
13220 if (regno < 0
13221 || (MEM_P (x)
13222 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)))
13223 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
13224 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
13225 return NO_REGS;
13227 if (MEM_P (x) && MSA_SUPPORTED_MODE_P (mode))
13228 /* In this case we can use MSA LD.* and ST.*. */
13229 return NO_REGS;
13231 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
13232 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
13233 return NO_REGS;
13235 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
13236 /* We can force the constant to memory and use lwc1
13237 and ldc1. As above, we will use pairs of lwc1s if
13238 ldc1 is not supported. */
13239 return NO_REGS;
13241 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
13242 /* In this case we can use mov.fmt. */
13243 return NO_REGS;
13245 /* Otherwise, we need to reload through an integer register. */
13246 return GR_REGS;
13248 if (FP_REG_P (regno))
13249 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
13251 return NO_REGS;
13254 /* Implement TARGET_MODE_REP_EXTENDED. */
13256 static int
13257 mips_mode_rep_extended (machine_mode mode, machine_mode mode_rep)
13259 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
13260 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
13261 return SIGN_EXTEND;
13263 return UNKNOWN;
13266 /* Implement TARGET_VALID_POINTER_MODE. */
13268 static bool
13269 mips_valid_pointer_mode (machine_mode mode)
13271 return mode == SImode || (TARGET_64BIT && mode == DImode);
13274 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
13276 static bool
13277 mips_vector_mode_supported_p (machine_mode mode)
13279 switch (mode)
13281 case V2SFmode:
13282 return TARGET_PAIRED_SINGLE_FLOAT;
13284 case V2HImode:
13285 case V4QImode:
13286 case V2HQmode:
13287 case V2UHQmode:
13288 case V2HAmode:
13289 case V2UHAmode:
13290 case V4QQmode:
13291 case V4UQQmode:
13292 return TARGET_DSP;
13294 case V2SImode:
13295 case V4HImode:
13296 case V8QImode:
13297 return TARGET_LOONGSON_VECTORS;
13299 default:
13300 return MSA_SUPPORTED_MODE_P (mode);
13304 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
13306 static bool
13307 mips_scalar_mode_supported_p (machine_mode mode)
13309 if (ALL_FIXED_POINT_MODE_P (mode)
13310 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
13311 return true;
13313 return default_scalar_mode_supported_p (mode);
13316 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
13318 static machine_mode
13319 mips_preferred_simd_mode (machine_mode mode)
13321 if (TARGET_PAIRED_SINGLE_FLOAT
13322 && mode == SFmode)
13323 return V2SFmode;
13325 if (!ISA_HAS_MSA)
13326 return word_mode;
13328 switch (mode)
13330 case QImode:
13331 return V16QImode;
13332 case HImode:
13333 return V8HImode;
13334 case SImode:
13335 return V4SImode;
13336 case DImode:
13337 return V2DImode;
13339 case SFmode:
13340 return V4SFmode;
13342 case DFmode:
13343 return V2DFmode;
13345 default:
13346 break;
13348 return word_mode;
13351 /* Implement TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES. */
13353 static unsigned int
13354 mips_autovectorize_vector_sizes (void)
13356 return ISA_HAS_MSA ? 16 : 0;
13359 /* Implement TARGET_INIT_LIBFUNCS. */
13361 static void
13362 mips_init_libfuncs (void)
13364 if (TARGET_FIX_VR4120)
13366 /* Register the special divsi3 and modsi3 functions needed to work
13367 around VR4120 division errata. */
13368 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
13369 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
13372 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
13374 /* Register the MIPS16 -mhard-float stubs. */
13375 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
13376 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
13377 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
13378 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
13380 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
13381 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
13382 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
13383 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
13384 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
13385 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
13386 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
13388 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
13389 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
13390 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
13392 if (TARGET_DOUBLE_FLOAT)
13394 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
13395 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
13396 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
13397 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
13399 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
13400 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
13401 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
13402 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
13403 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
13404 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
13405 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
13407 set_conv_libfunc (sext_optab, DFmode, SFmode,
13408 "__mips16_extendsfdf2");
13409 set_conv_libfunc (trunc_optab, SFmode, DFmode,
13410 "__mips16_truncdfsf2");
13411 set_conv_libfunc (sfix_optab, SImode, DFmode,
13412 "__mips16_fix_truncdfsi");
13413 set_conv_libfunc (sfloat_optab, DFmode, SImode,
13414 "__mips16_floatsidf");
13415 set_conv_libfunc (ufloat_optab, DFmode, SImode,
13416 "__mips16_floatunsidf");
13420 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
13421 on an external non-MIPS16 routine to implement __sync_synchronize.
13422 Similarly for the rest of the ll/sc libfuncs. */
13423 if (TARGET_MIPS16)
13425 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
13426 init_sync_libfuncs (UNITS_PER_WORD);
13430 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
13432 static void
13433 mips_process_load_label (rtx target)
13435 rtx base, gp, intop;
13436 HOST_WIDE_INT offset;
13438 mips_multi_start ();
13439 switch (mips_abi)
13441 case ABI_N32:
13442 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
13443 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
13444 break;
13446 case ABI_64:
13447 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
13448 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
13449 break;
13451 default:
13452 gp = pic_offset_table_rtx;
13453 if (mips_cfun_has_cprestore_slot_p ())
13455 gp = gen_rtx_REG (Pmode, AT_REGNUM);
13456 mips_get_cprestore_base_and_offset (&base, &offset, true);
13457 if (!SMALL_OPERAND (offset))
13459 intop = GEN_INT (CONST_HIGH_PART (offset));
13460 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
13461 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
13463 base = gp;
13464 offset = CONST_LOW_PART (offset);
13466 intop = GEN_INT (offset);
13467 if (ISA_HAS_LOAD_DELAY)
13468 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
13469 else
13470 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
13472 if (ISA_HAS_LOAD_DELAY)
13473 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
13474 else
13475 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
13476 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
13477 break;
13481 /* Return the number of instructions needed to load a label into $AT. */
13483 static unsigned int
13484 mips_load_label_num_insns (void)
13486 if (cfun->machine->load_label_num_insns == 0)
13488 mips_process_load_label (pc_rtx);
13489 cfun->machine->load_label_num_insns = mips_multi_num_insns;
13491 return cfun->machine->load_label_num_insns;
13494 /* Emit an asm sequence to start a noat block and load the address
13495 of a label into $1. */
13497 void
13498 mips_output_load_label (rtx target)
13500 mips_push_asm_switch (&mips_noat);
13501 if (TARGET_EXPLICIT_RELOCS)
13503 mips_process_load_label (target);
13504 mips_multi_write ();
13506 else
13508 if (Pmode == DImode)
13509 output_asm_insn ("dla\t%@,%0", &target);
13510 else
13511 output_asm_insn ("la\t%@,%0", &target);
13515 /* Return the length of INSN. LENGTH is the initial length computed by
13516 attributes in the machine-description file. */
13519 mips_adjust_insn_length (rtx_insn *insn, int length)
13521 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
13522 of a PIC long-branch sequence. Substitute the correct value. */
13523 if (length == MAX_PIC_BRANCH_LENGTH
13524 && JUMP_P (insn)
13525 && INSN_CODE (insn) >= 0
13526 && get_attr_type (insn) == TYPE_BRANCH)
13528 /* Add the branch-over instruction and its delay slot, if this
13529 is a conditional branch. */
13530 length = simplejump_p (insn) ? 0 : 8;
13532 /* Add the size of a load into $AT. */
13533 length += BASE_INSN_LENGTH * mips_load_label_num_insns ();
13535 /* Add the length of an indirect jump, ignoring the delay slot. */
13536 length += TARGET_COMPRESSION ? 2 : 4;
13539 /* A unconditional jump has an unfilled delay slot if it is not part
13540 of a sequence. A conditional jump normally has a delay slot, but
13541 does not on MIPS16. */
13542 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
13543 length += TARGET_MIPS16 ? 2 : 4;
13545 /* See how many nops might be needed to avoid hardware hazards. */
13546 if (!cfun->machine->ignore_hazard_length_p
13547 && INSN_P (insn)
13548 && INSN_CODE (insn) >= 0)
13549 switch (get_attr_hazard (insn))
13551 case HAZARD_NONE:
13552 break;
13554 case HAZARD_DELAY:
13555 case HAZARD_FORBIDDEN_SLOT:
13556 length += NOP_INSN_LENGTH;
13557 break;
13559 case HAZARD_HILO:
13560 length += NOP_INSN_LENGTH * 2;
13561 break;
13564 return length;
13567 /* Return the asm template for a call. OPERANDS are the operands, TARGET_OPNO
13568 is the operand number of the target. SIZE_OPNO is the operand number of
13569 the argument size operand that can optionally hold the call attributes. If
13570 SIZE_OPNO is not -1 and the call is indirect, use the function symbol from
13571 the call attributes to attach a R_MIPS_JALR relocation to the call. LINK_P
13572 indicates whether the jump is a call and needs to set the link register.
13574 When generating GOT code without explicit relocation operators, all calls
13575 should use assembly macros. Otherwise, all indirect calls should use "jr"
13576 or "jalr"; we will arrange to restore $gp afterwards if necessary. Finally,
13577 we can only generate direct calls for -mabicalls by temporarily switching
13578 to non-PIC mode.
13580 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
13581 instruction is in the delay slot of jal(r).
13583 Where compact branches are available, we try to use them if the delay slot
13584 has a NOP (or equivalently delay slots were not enabled for the instruction
13585 anyway). */
13587 const char *
13588 mips_output_jump (rtx *operands, int target_opno, int size_opno, bool link_p)
13590 static char buffer[300];
13591 char *s = buffer;
13592 bool reg_p = REG_P (operands[target_opno]);
13594 const char *and_link = link_p ? "al" : "";
13595 const char *reg = reg_p ? "r" : "";
13596 const char *compact = "";
13597 const char *nop = "%/";
13598 const char *short_delay = link_p ? "%!" : "";
13599 const char *insn_name = TARGET_CB_NEVER || reg_p ? "j" : "b";
13601 /* Compact branches can only be described when the ISA has support for them
13602 as both the compact formatter '%:' and the delay slot NOP formatter '%/'
13603 work as a mutually exclusive pair. I.e. a NOP is never required if a
13604 compact form is available. */
13605 if (!final_sequence
13606 && (TARGET_CB_MAYBE
13607 || (ISA_HAS_JRC && !link_p && reg_p)))
13609 compact = "c";
13610 nop = "";
13613 if (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS)
13614 sprintf (s, "%%*%s%s\t%%%d%%/", insn_name, and_link, target_opno);
13615 else
13617 if (!reg_p && TARGET_ABICALLS_PIC2)
13618 s += sprintf (s, ".option\tpic0\n\t");
13620 if (reg_p && mips_get_pic_call_symbol (operands, size_opno))
13621 s += sprintf (s, "%%*.reloc\t1f,%s,%%%d\n1:\t",
13622 TARGET_MICROMIPS ? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
13623 size_opno);
13624 else
13625 s += sprintf (s, "%%*");
13627 s += sprintf (s, "%s%s%s%s%s\t%%%d%s",
13628 insn_name, and_link, reg, compact, short_delay,
13629 target_opno, nop);
13631 if (!reg_p && TARGET_ABICALLS_PIC2)
13632 s += sprintf (s, "\n\t.option\tpic2");
13634 return buffer;
13637 /* Return the assembly code for INSN, which has the operands given by
13638 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
13639 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
13640 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
13641 version of BRANCH_IF_TRUE. */
13643 const char *
13644 mips_output_conditional_branch (rtx_insn *insn, rtx *operands,
13645 const char *branch_if_true,
13646 const char *branch_if_false)
13648 unsigned int length;
13649 rtx taken;
13651 gcc_assert (LABEL_P (operands[0]));
13653 length = get_attr_length (insn);
13654 if (length <= 8)
13656 /* Just a simple conditional branch. */
13657 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
13658 return branch_if_true;
13661 /* Generate a reversed branch around a direct jump. This fallback does
13662 not use branch-likely instructions. */
13663 mips_branch_likely = false;
13664 rtx_code_label *not_taken = gen_label_rtx ();
13665 taken = operands[0];
13667 /* Generate the reversed branch to NOT_TAKEN. */
13668 operands[0] = not_taken;
13669 output_asm_insn (branch_if_false, operands);
13671 /* If INSN has a delay slot, we must provide delay slots for both the
13672 branch to NOT_TAKEN and the conditional jump. We must also ensure
13673 that INSN's delay slot is executed in the appropriate cases. */
13674 if (final_sequence)
13676 /* This first delay slot will always be executed, so use INSN's
13677 delay slot if is not annulled. */
13678 if (!INSN_ANNULLED_BRANCH_P (insn))
13680 final_scan_insn (final_sequence->insn (1),
13681 asm_out_file, optimize, 1, NULL);
13682 final_sequence->insn (1)->set_deleted ();
13684 else
13685 output_asm_insn ("nop", 0);
13686 fprintf (asm_out_file, "\n");
13689 /* Output the unconditional branch to TAKEN. */
13690 if (TARGET_ABSOLUTE_JUMPS && TARGET_CB_MAYBE)
13692 /* Add a hazard nop. */
13693 if (!final_sequence)
13695 output_asm_insn ("nop\t\t# hazard nop", 0);
13696 fprintf (asm_out_file, "\n");
13698 output_asm_insn (MIPS_ABSOLUTE_JUMP ("bc\t%0"), &taken);
13700 else if (TARGET_ABSOLUTE_JUMPS)
13701 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
13702 else
13704 mips_output_load_label (taken);
13705 if (TARGET_CB_MAYBE)
13706 output_asm_insn ("jrc\t%@%]", 0);
13707 else
13708 output_asm_insn ("jr\t%@%]%/", 0);
13711 /* Now deal with its delay slot; see above. */
13712 if (final_sequence)
13714 /* This delay slot will only be executed if the branch is taken.
13715 Use INSN's delay slot if is annulled. */
13716 if (INSN_ANNULLED_BRANCH_P (insn))
13718 final_scan_insn (final_sequence->insn (1),
13719 asm_out_file, optimize, 1, NULL);
13720 final_sequence->insn (1)->set_deleted ();
13722 else if (TARGET_CB_NEVER)
13723 output_asm_insn ("nop", 0);
13724 fprintf (asm_out_file, "\n");
13727 /* Output NOT_TAKEN. */
13728 targetm.asm_out.internal_label (asm_out_file, "L",
13729 CODE_LABEL_NUMBER (not_taken));
13730 return "";
13733 /* Return the assembly code for INSN, which branches to OPERANDS[0]
13734 if some equality condition is true. The condition is given by
13735 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
13736 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
13737 OPERANDS[3] is the second operand and may be zero or a register. */
13739 const char *
13740 mips_output_equal_conditional_branch (rtx_insn* insn, rtx *operands,
13741 bool inverted_p)
13743 const char *branch[2];
13744 /* For a simple BNEZ or BEQZ microMIPSr3 branch. */
13745 if (TARGET_MICROMIPS
13746 && mips_isa_rev <= 5
13747 && operands[3] == const0_rtx
13748 && get_attr_length (insn) <= 8)
13750 if (mips_cb == MIPS_CB_OPTIMAL)
13752 branch[!inverted_p] = "%*b%C1z%:\t%2,%0";
13753 branch[inverted_p] = "%*b%N1z%:\t%2,%0";
13755 else
13757 branch[!inverted_p] = "%*b%C1z\t%2,%0%/";
13758 branch[inverted_p] = "%*b%N1z\t%2,%0%/";
13761 else if (TARGET_CB_MAYBE)
13763 if (operands[3] == const0_rtx)
13765 branch[!inverted_p] = MIPS_BRANCH_C ("b%C1z", "%2,%0");
13766 branch[inverted_p] = MIPS_BRANCH_C ("b%N1z", "%2,%0");
13768 else if (REGNO (operands[2]) != REGNO (operands[3]))
13770 branch[!inverted_p] = MIPS_BRANCH_C ("b%C1", "%2,%3,%0");
13771 branch[inverted_p] = MIPS_BRANCH_C ("b%N1", "%2,%3,%0");
13773 else
13775 /* This case is degenerate. It should not happen, but does. */
13776 if (GET_CODE (operands[1]) == NE)
13777 inverted_p = !inverted_p;
13779 branch[!inverted_p] = MIPS_BRANCH_C ("b", "%0");
13780 branch[inverted_p] = "%*\t\t# branch never";
13783 else
13785 branch[!inverted_p] = MIPS_BRANCH ("b%C1", "%2,%z3,%0");
13786 branch[inverted_p] = MIPS_BRANCH ("b%N1", "%2,%z3,%0");
13789 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
13792 /* Return the assembly code for INSN, which branches to OPERANDS[0]
13793 if some ordering condition is true. The condition is given by
13794 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
13795 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
13796 OPERANDS[3] is the second operand and may be zero or a register. */
13798 const char *
13799 mips_output_order_conditional_branch (rtx_insn *insn, rtx *operands,
13800 bool inverted_p)
13802 const char *branch[2];
13804 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
13805 Make BRANCH[0] branch on the inverse condition. */
13806 if (operands[3] != const0_rtx)
13808 /* Handle degenerate cases that should not, but do, occur. */
13809 if (REGNO (operands[2]) == REGNO (operands[3]))
13811 switch (GET_CODE (operands[1]))
13813 case LT:
13814 case LTU:
13815 inverted_p = !inverted_p;
13816 /* Fall through. */
13817 case GE:
13818 case GEU:
13819 branch[!inverted_p] = MIPS_BRANCH_C ("b", "%0");
13820 branch[inverted_p] = "%*\t\t# branch never";
13821 break;
13822 default:
13823 gcc_unreachable ();
13826 else
13828 branch[!inverted_p] = MIPS_BRANCH_C ("b%C1", "%2,%3,%0");
13829 branch[inverted_p] = MIPS_BRANCH_C ("b%N1", "%2,%3,%0");
13832 else
13834 switch (GET_CODE (operands[1]))
13836 /* These cases are equivalent to comparisons against zero. */
13837 case LEU:
13838 inverted_p = !inverted_p;
13839 /* Fall through. */
13840 case GTU:
13841 if (TARGET_CB_MAYBE)
13843 branch[!inverted_p] = MIPS_BRANCH_C ("bnez", "%2,%0");
13844 branch[inverted_p] = MIPS_BRANCH_C ("beqz", "%2,%0");
13846 else
13848 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
13849 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
13851 break;
13853 /* These cases are always true or always false. */
13854 case LTU:
13855 inverted_p = !inverted_p;
13856 /* Fall through. */
13857 case GEU:
13858 if (TARGET_CB_MAYBE)
13860 branch[!inverted_p] = MIPS_BRANCH_C ("b", "%0");
13861 branch[inverted_p] = "%*\t\t# branch never";
13863 else
13865 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
13866 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
13868 break;
13870 default:
13871 if (TARGET_CB_MAYBE)
13873 branch[!inverted_p] = MIPS_BRANCH_C ("b%C1z", "%2,%0");
13874 branch[inverted_p] = MIPS_BRANCH_C ("b%N1z", "%2,%0");
13876 else
13878 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
13879 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
13881 break;
13884 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
13887 /* Start a block of code that needs access to the LL, SC and SYNC
13888 instructions. */
13890 static void
13891 mips_start_ll_sc_sync_block (void)
13893 if (!ISA_HAS_LL_SC)
13895 output_asm_insn (".set\tpush", 0);
13896 if (TARGET_64BIT)
13897 output_asm_insn (".set\tmips3", 0);
13898 else
13899 output_asm_insn (".set\tmips2", 0);
13903 /* End a block started by mips_start_ll_sc_sync_block. */
13905 static void
13906 mips_end_ll_sc_sync_block (void)
13908 if (!ISA_HAS_LL_SC)
13909 output_asm_insn (".set\tpop", 0);
13912 /* Output and/or return the asm template for a sync instruction. */
13914 const char *
13915 mips_output_sync (void)
13917 mips_start_ll_sc_sync_block ();
13918 output_asm_insn ("sync", 0);
13919 mips_end_ll_sc_sync_block ();
13920 return "";
13923 /* Return the asm template associated with sync_insn1 value TYPE.
13924 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
13926 static const char *
13927 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
13929 switch (type)
13931 case SYNC_INSN1_MOVE:
13932 return "move\t%0,%z2";
13933 case SYNC_INSN1_LI:
13934 return "li\t%0,%2";
13935 case SYNC_INSN1_ADDU:
13936 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
13937 case SYNC_INSN1_ADDIU:
13938 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
13939 case SYNC_INSN1_SUBU:
13940 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
13941 case SYNC_INSN1_AND:
13942 return "and\t%0,%1,%z2";
13943 case SYNC_INSN1_ANDI:
13944 return "andi\t%0,%1,%2";
13945 case SYNC_INSN1_OR:
13946 return "or\t%0,%1,%z2";
13947 case SYNC_INSN1_ORI:
13948 return "ori\t%0,%1,%2";
13949 case SYNC_INSN1_XOR:
13950 return "xor\t%0,%1,%z2";
13951 case SYNC_INSN1_XORI:
13952 return "xori\t%0,%1,%2";
13954 gcc_unreachable ();
13957 /* Return the asm template associated with sync_insn2 value TYPE. */
13959 static const char *
13960 mips_sync_insn2_template (enum attr_sync_insn2 type)
13962 switch (type)
13964 case SYNC_INSN2_NOP:
13965 gcc_unreachable ();
13966 case SYNC_INSN2_AND:
13967 return "and\t%0,%1,%z2";
13968 case SYNC_INSN2_XOR:
13969 return "xor\t%0,%1,%z2";
13970 case SYNC_INSN2_NOT:
13971 return "nor\t%0,%1,%.";
13973 gcc_unreachable ();
13976 /* OPERANDS are the operands to a sync loop instruction and INDEX is
13977 the value of the one of the sync_* attributes. Return the operand
13978 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
13979 have the associated attribute. */
13981 static rtx
13982 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
13984 if (index > 0)
13985 default_value = operands[index - 1];
13986 return default_value;
13989 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
13990 sequence for it. */
13992 static void
13993 mips_process_sync_loop (rtx_insn *insn, rtx *operands)
13995 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
13996 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
13997 unsigned int tmp3_insn;
13998 enum attr_sync_insn1 insn1;
13999 enum attr_sync_insn2 insn2;
14000 bool is_64bit_p;
14001 int memmodel_attr;
14002 enum memmodel model;
14004 /* Read an operand from the sync_WHAT attribute and store it in
14005 variable WHAT. DEFAULT is the default value if no attribute
14006 is specified. */
14007 #define READ_OPERAND(WHAT, DEFAULT) \
14008 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
14009 DEFAULT)
14011 /* Read the memory. */
14012 READ_OPERAND (mem, 0);
14013 gcc_assert (mem);
14014 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
14016 /* Read the other attributes. */
14017 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
14018 READ_OPERAND (oldval, at);
14019 READ_OPERAND (cmp, 0);
14020 READ_OPERAND (newval, at);
14021 READ_OPERAND (inclusive_mask, 0);
14022 READ_OPERAND (exclusive_mask, 0);
14023 READ_OPERAND (required_oldval, 0);
14024 READ_OPERAND (insn1_op2, 0);
14025 insn1 = get_attr_sync_insn1 (insn);
14026 insn2 = get_attr_sync_insn2 (insn);
14028 /* Don't bother setting CMP result that is never used. */
14029 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
14030 cmp = 0;
14032 memmodel_attr = get_attr_sync_memmodel (insn);
14033 switch (memmodel_attr)
14035 case 10:
14036 model = MEMMODEL_ACQ_REL;
14037 break;
14038 case 11:
14039 model = MEMMODEL_ACQUIRE;
14040 break;
14041 default:
14042 model = memmodel_from_int (INTVAL (operands[memmodel_attr]));
14045 mips_multi_start ();
14047 /* Output the release side of the memory barrier. */
14048 if (need_atomic_barrier_p (model, true))
14050 if (required_oldval == 0 && TARGET_OCTEON)
14052 /* Octeon doesn't reorder reads, so a full barrier can be
14053 created by using SYNCW to order writes combined with the
14054 write from the following SC. When the SC successfully
14055 completes, we know that all preceding writes are also
14056 committed to the coherent memory system. It is possible
14057 for a single SYNCW to fail, but a pair of them will never
14058 fail, so we use two. */
14059 mips_multi_add_insn ("syncw", NULL);
14060 mips_multi_add_insn ("syncw", NULL);
14062 else
14063 mips_multi_add_insn ("sync", NULL);
14066 /* Output the branch-back label. */
14067 mips_multi_add_label ("1:");
14069 /* OLDVAL = *MEM. */
14070 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
14071 oldval, mem, NULL);
14073 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
14074 if (required_oldval)
14076 if (inclusive_mask == 0)
14077 tmp1 = oldval;
14078 else
14080 gcc_assert (oldval != at);
14081 mips_multi_add_insn ("and\t%0,%1,%2",
14082 at, oldval, inclusive_mask, NULL);
14083 tmp1 = at;
14085 if (TARGET_CB_NEVER)
14086 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
14088 /* CMP = 0 [delay slot]. */
14089 if (cmp)
14090 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
14092 if (TARGET_CB_MAYBE && required_oldval == const0_rtx)
14093 mips_multi_add_insn ("bnezc\t%0,2f", tmp1, NULL);
14094 else if (TARGET_CB_MAYBE)
14095 mips_multi_add_insn ("bnec\t%0,%1,2f", tmp1, required_oldval, NULL);
14099 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
14100 if (exclusive_mask == 0)
14101 tmp1 = const0_rtx;
14102 else
14104 gcc_assert (oldval != at);
14105 mips_multi_add_insn ("and\t%0,%1,%z2",
14106 at, oldval, exclusive_mask, NULL);
14107 tmp1 = at;
14110 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
14112 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
14113 at least one instruction in that case. */
14114 if (insn1 == SYNC_INSN1_MOVE
14115 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
14116 tmp2 = insn1_op2;
14117 else
14119 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
14120 newval, oldval, insn1_op2, NULL);
14121 tmp2 = newval;
14124 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
14125 if (insn2 == SYNC_INSN2_NOP)
14126 tmp3 = tmp2;
14127 else
14129 mips_multi_add_insn (mips_sync_insn2_template (insn2),
14130 newval, tmp2, inclusive_mask, NULL);
14131 tmp3 = newval;
14133 tmp3_insn = mips_multi_last_index ();
14135 /* $AT = $TMP1 | $TMP3. */
14136 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
14138 mips_multi_set_operand (tmp3_insn, 0, at);
14139 tmp3 = at;
14141 else
14143 gcc_assert (tmp1 != tmp3);
14144 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
14147 /* if (!commit (*MEM = $AT)) goto 1.
14149 This will sometimes be a delayed branch; see the write code below
14150 for details. */
14151 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
14153 /* When using branch likely (-mfix-r10000), the delay slot instruction
14154 will be annulled on false. The normal delay slot instructions
14155 calculate the overall result of the atomic operation and must not
14156 be annulled. To ensure this behavior unconditionally use a NOP
14157 in the delay slot for the branch likely case. */
14159 if (TARGET_CB_MAYBE)
14160 mips_multi_add_insn ("beqzc\t%0,1b", at, NULL);
14161 else
14162 mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at, NULL);
14164 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
14165 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
14167 mips_multi_copy_insn (tmp3_insn);
14168 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
14170 else if (!(required_oldval && cmp) && !mips_branch_likely)
14171 mips_multi_add_insn ("nop", NULL);
14173 /* CMP = 1 -- either standalone or in a delay slot. */
14174 if (required_oldval && cmp)
14175 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
14177 /* Output the acquire side of the memory barrier. */
14178 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
14179 mips_multi_add_insn ("sync", NULL);
14181 /* Output the exit label, if needed. */
14182 if (required_oldval)
14183 mips_multi_add_label ("2:");
14185 #undef READ_OPERAND
14188 /* Output and/or return the asm template for sync loop INSN, which has
14189 the operands given by OPERANDS. */
14191 const char *
14192 mips_output_sync_loop (rtx_insn *insn, rtx *operands)
14194 /* Use branch-likely instructions to work around the LL/SC R10000
14195 errata. */
14196 mips_branch_likely = TARGET_FIX_R10000;
14198 mips_process_sync_loop (insn, operands);
14200 mips_push_asm_switch (&mips_noreorder);
14201 mips_push_asm_switch (&mips_nomacro);
14202 mips_push_asm_switch (&mips_noat);
14203 mips_start_ll_sc_sync_block ();
14205 mips_multi_write ();
14207 mips_end_ll_sc_sync_block ();
14208 mips_pop_asm_switch (&mips_noat);
14209 mips_pop_asm_switch (&mips_nomacro);
14210 mips_pop_asm_switch (&mips_noreorder);
14212 return "";
14215 /* Return the number of individual instructions in sync loop INSN,
14216 which has the operands given by OPERANDS. */
14218 unsigned int
14219 mips_sync_loop_insns (rtx_insn *insn, rtx *operands)
14221 /* Use branch-likely instructions to work around the LL/SC R10000
14222 errata. */
14223 mips_branch_likely = TARGET_FIX_R10000;
14224 mips_process_sync_loop (insn, operands);
14225 return mips_multi_num_insns;
14228 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
14229 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
14231 When working around R4000 and R4400 errata, we need to make sure that
14232 the division is not immediately followed by a shift[1][2]. We also
14233 need to stop the division from being put into a branch delay slot[3].
14234 The easiest way to avoid both problems is to add a nop after the
14235 division. When a divide-by-zero check is needed, this nop can be
14236 used to fill the branch delay slot.
14238 [1] If a double-word or a variable shift executes immediately
14239 after starting an integer division, the shift may give an
14240 incorrect result. See quotations of errata #16 and #28 from
14241 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
14242 in mips.md for details.
14244 [2] A similar bug to [1] exists for all revisions of the
14245 R4000 and the R4400 when run in an MC configuration.
14246 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
14248 "19. In this following sequence:
14250 ddiv (or ddivu or div or divu)
14251 dsll32 (or dsrl32, dsra32)
14253 if an MPT stall occurs, while the divide is slipping the cpu
14254 pipeline, then the following double shift would end up with an
14255 incorrect result.
14257 Workaround: The compiler needs to avoid generating any
14258 sequence with divide followed by extended double shift."
14260 This erratum is also present in "MIPS R4400MC Errata, Processor
14261 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
14262 & 3.0" as errata #10 and #4, respectively.
14264 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
14265 (also valid for MIPS R4000MC processors):
14267 "52. R4000SC: This bug does not apply for the R4000PC.
14269 There are two flavors of this bug:
14271 1) If the instruction just after divide takes an RF exception
14272 (tlb-refill, tlb-invalid) and gets an instruction cache
14273 miss (both primary and secondary) and the line which is
14274 currently in secondary cache at this index had the first
14275 data word, where the bits 5..2 are set, then R4000 would
14276 get a wrong result for the div.
14280 div r8, r9
14281 ------------------- # end-of page. -tlb-refill
14285 div r8, r9
14286 ------------------- # end-of page. -tlb-invalid
14289 2) If the divide is in the taken branch delay slot, where the
14290 target takes RF exception and gets an I-cache miss for the
14291 exception vector or where I-cache miss occurs for the
14292 target address, under the above mentioned scenarios, the
14293 div would get wrong results.
14296 j r2 # to next page mapped or unmapped
14297 div r8,r9 # this bug would be there as long
14298 # as there is an ICache miss and
14299 nop # the "data pattern" is present
14302 beq r0, r0, NextPage # to Next page
14303 div r8,r9
14306 This bug is present for div, divu, ddiv, and ddivu
14307 instructions.
14309 Workaround: For item 1), OS could make sure that the next page
14310 after the divide instruction is also mapped. For item 2), the
14311 compiler could make sure that the divide instruction is not in
14312 the branch delay slot."
14314 These processors have PRId values of 0x00004220 and 0x00004300 for
14315 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
14317 const char *
14318 mips_output_division (const char *division, rtx *operands)
14320 const char *s;
14322 s = division;
14323 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
14325 output_asm_insn (s, operands);
14326 s = "nop";
14328 if (TARGET_CHECK_ZERO_DIV)
14330 if (TARGET_MIPS16)
14332 output_asm_insn (s, operands);
14333 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
14335 else if (GENERATE_DIVIDE_TRAPS)
14337 /* Avoid long replay penalty on load miss by putting the trap before
14338 the divide. */
14339 if (TUNE_74K)
14340 output_asm_insn ("teq\t%2,%.,7", operands);
14341 else
14343 output_asm_insn (s, operands);
14344 s = "teq\t%2,%.,7";
14347 else
14349 if (flag_delayed_branch)
14351 output_asm_insn ("%(bne\t%2,%.,1f", operands);
14352 output_asm_insn (s, operands);
14353 s = "break\t7%)\n1:";
14355 else
14357 output_asm_insn (s, operands);
14358 s = "bne\t%2,%.,1f\n\tnop\n\tbreak\t7\n1:";
14362 return s;
14365 /* Return the assembly code for MSA DIV_{S,U}.DF or MOD_{S,U}.DF instructions,
14366 which has the operands given by OPERANDS. Add in a divide-by-zero check
14367 if needed. */
14369 const char *
14370 mips_msa_output_division (const char *division, rtx *operands)
14372 const char *s;
14374 s = division;
14375 if (TARGET_CHECK_ZERO_DIV)
14377 output_asm_insn ("%(bnz.%v0\t%w2,1f", operands);
14378 output_asm_insn (s, operands);
14379 s = "break\t7%)\n1:";
14381 return s;
14384 /* Return true if destination of IN_INSN is used as add source in
14385 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
14386 madd.s dst, x, y, z
14387 madd.s a, dst, b, c */
14389 bool
14390 mips_fmadd_bypass (rtx_insn *out_insn, rtx_insn *in_insn)
14392 int dst_reg, src_reg;
14394 gcc_assert (get_attr_type (in_insn) == TYPE_FMADD);
14395 gcc_assert (get_attr_type (out_insn) == TYPE_FMADD);
14397 extract_insn (in_insn);
14398 dst_reg = REG_P (recog_data.operand[0]);
14400 extract_insn (out_insn);
14401 src_reg = REG_P (recog_data.operand[1]);
14403 if (dst_reg == src_reg)
14404 return true;
14406 return false;
14409 /* Return true if IN_INSN is a multiply-add or multiply-subtract
14410 instruction and if OUT_INSN assigns to the accumulator operand. */
14412 bool
14413 mips_linked_madd_p (rtx_insn *out_insn, rtx_insn *in_insn)
14415 enum attr_accum_in accum_in;
14416 int accum_in_opnum;
14417 rtx accum_in_op;
14419 if (recog_memoized (in_insn) < 0)
14420 return false;
14422 accum_in = get_attr_accum_in (in_insn);
14423 if (accum_in == ACCUM_IN_NONE)
14424 return false;
14426 accum_in_opnum = accum_in - ACCUM_IN_0;
14428 extract_insn (in_insn);
14429 gcc_assert (accum_in_opnum < recog_data.n_operands);
14430 accum_in_op = recog_data.operand[accum_in_opnum];
14432 return reg_set_p (accum_in_op, out_insn);
14435 /* True if the dependency between OUT_INSN and IN_INSN is on the store
14436 data rather than the address. We need this because the cprestore
14437 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
14438 which causes the default routine to abort. We just return false
14439 for that case. */
14441 bool
14442 mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
14444 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
14445 return false;
14447 return store_data_bypass_p (out_insn, in_insn);
14451 /* Variables and flags used in scheduler hooks when tuning for
14452 Loongson 2E/2F. */
14453 static struct
14455 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
14456 strategy. */
14458 /* If true, then next ALU1/2 instruction will go to ALU1. */
14459 bool alu1_turn_p;
14461 /* If true, then next FALU1/2 unstruction will go to FALU1. */
14462 bool falu1_turn_p;
14464 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
14465 int alu1_core_unit_code;
14466 int alu2_core_unit_code;
14467 int falu1_core_unit_code;
14468 int falu2_core_unit_code;
14470 /* True if current cycle has a multi instruction.
14471 This flag is used in mips_ls2_dfa_post_advance_cycle. */
14472 bool cycle_has_multi_p;
14474 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
14475 These are used in mips_ls2_dfa_post_advance_cycle to initialize
14476 DFA state.
14477 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
14478 instruction to go ALU1. */
14479 rtx_insn *alu1_turn_enabled_insn;
14480 rtx_insn *alu2_turn_enabled_insn;
14481 rtx_insn *falu1_turn_enabled_insn;
14482 rtx_insn *falu2_turn_enabled_insn;
14483 } mips_ls2;
14485 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
14486 dependencies have no cost, except on the 20Kc where output-dependence
14487 is treated like input-dependence. */
14489 static int
14490 mips_adjust_cost (rtx_insn *, int dep_type, rtx_insn *, int cost, unsigned int)
14492 if (dep_type != 0 && (dep_type != REG_DEP_OUTPUT || !TUNE_20KC))
14493 return 0;
14494 return cost;
14497 /* Return the number of instructions that can be issued per cycle. */
14499 static int
14500 mips_issue_rate (void)
14502 switch (mips_tune)
14504 case PROCESSOR_74KC:
14505 case PROCESSOR_74KF2_1:
14506 case PROCESSOR_74KF1_1:
14507 case PROCESSOR_74KF3_2:
14508 /* The 74k is not strictly quad-issue cpu, but can be seen as one
14509 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
14510 but in reality only a maximum of 3 insns can be issued as
14511 floating-point loads and stores also require a slot in the
14512 AGEN pipe. */
14513 case PROCESSOR_R10000:
14514 /* All R10K Processors are quad-issue (being the first MIPS
14515 processors to support this feature). */
14516 return 4;
14518 case PROCESSOR_20KC:
14519 case PROCESSOR_R4130:
14520 case PROCESSOR_R5400:
14521 case PROCESSOR_R5500:
14522 case PROCESSOR_R5900:
14523 case PROCESSOR_R7000:
14524 case PROCESSOR_R9000:
14525 case PROCESSOR_OCTEON:
14526 case PROCESSOR_OCTEON2:
14527 case PROCESSOR_OCTEON3:
14528 case PROCESSOR_I6400:
14529 return 2;
14531 case PROCESSOR_SB1:
14532 case PROCESSOR_SB1A:
14533 /* This is actually 4, but we get better performance if we claim 3.
14534 This is partly because of unwanted speculative code motion with the
14535 larger number, and partly because in most common cases we can't
14536 reach the theoretical max of 4. */
14537 return 3;
14539 case PROCESSOR_LOONGSON_2E:
14540 case PROCESSOR_LOONGSON_2F:
14541 case PROCESSOR_LOONGSON_3A:
14542 case PROCESSOR_P5600:
14543 return 4;
14545 case PROCESSOR_XLP:
14546 return (reload_completed ? 4 : 3);
14548 default:
14549 return 1;
14553 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
14555 static void
14556 mips_ls2_init_dfa_post_cycle_insn (void)
14558 start_sequence ();
14559 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
14560 mips_ls2.alu1_turn_enabled_insn = get_insns ();
14561 end_sequence ();
14563 start_sequence ();
14564 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
14565 mips_ls2.alu2_turn_enabled_insn = get_insns ();
14566 end_sequence ();
14568 start_sequence ();
14569 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
14570 mips_ls2.falu1_turn_enabled_insn = get_insns ();
14571 end_sequence ();
14573 start_sequence ();
14574 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
14575 mips_ls2.falu2_turn_enabled_insn = get_insns ();
14576 end_sequence ();
14578 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
14579 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
14580 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
14581 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
14584 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
14585 Init data used in mips_dfa_post_advance_cycle. */
14587 static void
14588 mips_init_dfa_post_cycle_insn (void)
14590 if (TUNE_LOONGSON_2EF)
14591 mips_ls2_init_dfa_post_cycle_insn ();
14594 /* Initialize STATE when scheduling for Loongson 2E/2F.
14595 Support round-robin dispatch scheme by enabling only one of
14596 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
14597 respectively. */
14599 static void
14600 mips_ls2_dfa_post_advance_cycle (state_t state)
14602 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
14604 /* Though there are no non-pipelined ALU1 insns,
14605 we can get an instruction of type 'multi' before reload. */
14606 gcc_assert (mips_ls2.cycle_has_multi_p);
14607 mips_ls2.alu1_turn_p = false;
14610 mips_ls2.cycle_has_multi_p = false;
14612 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
14613 /* We have a non-pipelined alu instruction in the core,
14614 adjust round-robin counter. */
14615 mips_ls2.alu1_turn_p = true;
14617 if (mips_ls2.alu1_turn_p)
14619 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
14620 gcc_unreachable ();
14622 else
14624 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
14625 gcc_unreachable ();
14628 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
14630 /* There are no non-pipelined FALU1 insns. */
14631 gcc_unreachable ();
14632 mips_ls2.falu1_turn_p = false;
14635 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
14636 /* We have a non-pipelined falu instruction in the core,
14637 adjust round-robin counter. */
14638 mips_ls2.falu1_turn_p = true;
14640 if (mips_ls2.falu1_turn_p)
14642 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
14643 gcc_unreachable ();
14645 else
14647 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
14648 gcc_unreachable ();
14652 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
14653 This hook is being called at the start of each cycle. */
14655 static void
14656 mips_dfa_post_advance_cycle (void)
14658 if (TUNE_LOONGSON_2EF)
14659 mips_ls2_dfa_post_advance_cycle (curr_state);
14662 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
14663 be as wide as the scheduling freedom in the DFA. */
14665 static int
14666 mips_multipass_dfa_lookahead (void)
14668 /* Can schedule up to 4 of the 6 function units in any one cycle. */
14669 if (TUNE_SB1)
14670 return 4;
14672 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
14673 return 4;
14675 if (TUNE_OCTEON)
14676 return 2;
14678 if (TUNE_P5600 || TUNE_I6400)
14679 return 4;
14681 return 0;
14684 /* Remove the instruction at index LOWER from ready queue READY and
14685 reinsert it in front of the instruction at index HIGHER. LOWER must
14686 be <= HIGHER. */
14688 static void
14689 mips_promote_ready (rtx_insn **ready, int lower, int higher)
14691 rtx_insn *new_head;
14692 int i;
14694 new_head = ready[lower];
14695 for (i = lower; i < higher; i++)
14696 ready[i] = ready[i + 1];
14697 ready[i] = new_head;
14700 /* If the priority of the instruction at POS2 in the ready queue READY
14701 is within LIMIT units of that of the instruction at POS1, swap the
14702 instructions if POS2 is not already less than POS1. */
14704 static void
14705 mips_maybe_swap_ready (rtx_insn **ready, int pos1, int pos2, int limit)
14707 if (pos1 < pos2
14708 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
14710 rtx_insn *temp;
14712 temp = ready[pos1];
14713 ready[pos1] = ready[pos2];
14714 ready[pos2] = temp;
14718 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
14719 that may clobber hi or lo. */
14720 static rtx_insn *mips_macc_chains_last_hilo;
14722 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
14723 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
14725 static void
14726 mips_macc_chains_record (rtx_insn *insn)
14728 if (get_attr_may_clobber_hilo (insn))
14729 mips_macc_chains_last_hilo = insn;
14732 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
14733 has NREADY elements, looking for a multiply-add or multiply-subtract
14734 instruction that is cumulative with mips_macc_chains_last_hilo.
14735 If there is one, promote it ahead of anything else that might
14736 clobber hi or lo. */
14738 static void
14739 mips_macc_chains_reorder (rtx_insn **ready, int nready)
14741 int i, j;
14743 if (mips_macc_chains_last_hilo != 0)
14744 for (i = nready - 1; i >= 0; i--)
14745 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
14747 for (j = nready - 1; j > i; j--)
14748 if (recog_memoized (ready[j]) >= 0
14749 && get_attr_may_clobber_hilo (ready[j]))
14751 mips_promote_ready (ready, i, j);
14752 break;
14754 break;
14758 /* The last instruction to be scheduled. */
14759 static rtx_insn *vr4130_last_insn;
14761 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
14762 points to an rtx that is initially an instruction. Nullify the rtx
14763 if the instruction uses the value of register X. */
14765 static void
14766 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
14767 void *data)
14769 rtx *insn_ptr;
14771 insn_ptr = (rtx *) data;
14772 if (REG_P (x)
14773 && *insn_ptr != 0
14774 && reg_referenced_p (x, PATTERN (*insn_ptr)))
14775 *insn_ptr = 0;
14778 /* Return true if there is true register dependence between vr4130_last_insn
14779 and INSN. */
14781 static bool
14782 vr4130_true_reg_dependence_p (rtx insn)
14784 note_stores (PATTERN (vr4130_last_insn),
14785 vr4130_true_reg_dependence_p_1, &insn);
14786 return insn == 0;
14789 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
14790 the ready queue and that INSN2 is the instruction after it, return
14791 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
14792 in which INSN1 and INSN2 can probably issue in parallel, but for
14793 which (INSN2, INSN1) should be less sensitive to instruction
14794 alignment than (INSN1, INSN2). See 4130.md for more details. */
14796 static bool
14797 vr4130_swap_insns_p (rtx_insn *insn1, rtx_insn *insn2)
14799 sd_iterator_def sd_it;
14800 dep_t dep;
14802 /* Check for the following case:
14804 1) there is some other instruction X with an anti dependence on INSN1;
14805 2) X has a higher priority than INSN2; and
14806 3) X is an arithmetic instruction (and thus has no unit restrictions).
14808 If INSN1 is the last instruction blocking X, it would better to
14809 choose (INSN1, X) over (INSN2, INSN1). */
14810 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
14811 if (DEP_TYPE (dep) == REG_DEP_ANTI
14812 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
14813 && recog_memoized (DEP_CON (dep)) >= 0
14814 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
14815 return false;
14817 if (vr4130_last_insn != 0
14818 && recog_memoized (insn1) >= 0
14819 && recog_memoized (insn2) >= 0)
14821 /* See whether INSN1 and INSN2 use different execution units,
14822 or if they are both ALU-type instructions. If so, they can
14823 probably execute in parallel. */
14824 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
14825 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
14826 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
14828 /* If only one of the instructions has a dependence on
14829 vr4130_last_insn, prefer to schedule the other one first. */
14830 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
14831 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
14832 if (dep1_p != dep2_p)
14833 return dep1_p;
14835 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
14836 is not an ALU-type instruction and if INSN1 uses the same
14837 execution unit. (Note that if this condition holds, we already
14838 know that INSN2 uses a different execution unit.) */
14839 if (class1 != VR4130_CLASS_ALU
14840 && recog_memoized (vr4130_last_insn) >= 0
14841 && class1 == get_attr_vr4130_class (vr4130_last_insn))
14842 return true;
14845 return false;
14848 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
14849 queue with at least two instructions. Swap the first two if
14850 vr4130_swap_insns_p says that it could be worthwhile. */
14852 static void
14853 vr4130_reorder (rtx_insn **ready, int nready)
14855 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
14856 mips_promote_ready (ready, nready - 2, nready - 1);
14859 /* Record whether last 74k AGEN instruction was a load or store. */
14860 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
14862 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
14863 resets to TYPE_UNKNOWN state. */
14865 static void
14866 mips_74k_agen_init (rtx_insn *insn)
14868 if (!insn || CALL_P (insn) || JUMP_P (insn))
14869 mips_last_74k_agen_insn = TYPE_UNKNOWN;
14870 else
14872 enum attr_type type = get_attr_type (insn);
14873 if (type == TYPE_LOAD || type == TYPE_STORE)
14874 mips_last_74k_agen_insn = type;
14878 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
14879 loads to be grouped together, and multiple stores to be grouped
14880 together. Swap things around in the ready queue to make this happen. */
14882 static void
14883 mips_74k_agen_reorder (rtx_insn **ready, int nready)
14885 int i;
14886 int store_pos, load_pos;
14888 store_pos = -1;
14889 load_pos = -1;
14891 for (i = nready - 1; i >= 0; i--)
14893 rtx_insn *insn = ready[i];
14894 if (USEFUL_INSN_P (insn))
14895 switch (get_attr_type (insn))
14897 case TYPE_STORE:
14898 if (store_pos == -1)
14899 store_pos = i;
14900 break;
14902 case TYPE_LOAD:
14903 if (load_pos == -1)
14904 load_pos = i;
14905 break;
14907 default:
14908 break;
14912 if (load_pos == -1 || store_pos == -1)
14913 return;
14915 switch (mips_last_74k_agen_insn)
14917 case TYPE_UNKNOWN:
14918 /* Prefer to schedule loads since they have a higher latency. */
14919 case TYPE_LOAD:
14920 /* Swap loads to the front of the queue. */
14921 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
14922 break;
14923 case TYPE_STORE:
14924 /* Swap stores to the front of the queue. */
14925 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
14926 break;
14927 default:
14928 break;
14932 /* Implement TARGET_SCHED_INIT. */
14934 static void
14935 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
14936 int max_ready ATTRIBUTE_UNUSED)
14938 mips_macc_chains_last_hilo = 0;
14939 vr4130_last_insn = 0;
14940 mips_74k_agen_init (NULL);
14942 /* When scheduling for Loongson2, branch instructions go to ALU1,
14943 therefore basic block is most likely to start with round-robin counter
14944 pointed to ALU2. */
14945 mips_ls2.alu1_turn_p = false;
14946 mips_ls2.falu1_turn_p = true;
14949 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
14951 static void
14952 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
14953 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
14955 if (!reload_completed
14956 && TUNE_MACC_CHAINS
14957 && *nreadyp > 0)
14958 mips_macc_chains_reorder (ready, *nreadyp);
14960 if (reload_completed
14961 && TUNE_MIPS4130
14962 && !TARGET_VR4130_ALIGN
14963 && *nreadyp > 1)
14964 vr4130_reorder (ready, *nreadyp);
14966 if (TUNE_74K)
14967 mips_74k_agen_reorder (ready, *nreadyp);
14970 /* Implement TARGET_SCHED_REORDER. */
14972 static int
14973 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
14974 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
14976 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
14977 return mips_issue_rate ();
14980 /* Implement TARGET_SCHED_REORDER2. */
14982 static int
14983 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
14984 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
14986 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
14987 return cached_can_issue_more;
14990 /* Update round-robin counters for ALU1/2 and FALU1/2. */
14992 static void
14993 mips_ls2_variable_issue (rtx_insn *insn)
14995 if (mips_ls2.alu1_turn_p)
14997 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
14998 mips_ls2.alu1_turn_p = false;
15000 else
15002 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
15003 mips_ls2.alu1_turn_p = true;
15006 if (mips_ls2.falu1_turn_p)
15008 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
15009 mips_ls2.falu1_turn_p = false;
15011 else
15013 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
15014 mips_ls2.falu1_turn_p = true;
15017 if (recog_memoized (insn) >= 0)
15018 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
15021 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
15023 static int
15024 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
15025 rtx_insn *insn, int more)
15027 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
15028 if (USEFUL_INSN_P (insn))
15030 if (get_attr_type (insn) != TYPE_GHOST)
15031 more--;
15032 if (!reload_completed && TUNE_MACC_CHAINS)
15033 mips_macc_chains_record (insn);
15034 vr4130_last_insn = insn;
15035 if (TUNE_74K)
15036 mips_74k_agen_init (insn);
15037 else if (TUNE_LOONGSON_2EF)
15038 mips_ls2_variable_issue (insn);
15041 /* Instructions of type 'multi' should all be split before
15042 the second scheduling pass. */
15043 gcc_assert (!reload_completed
15044 || recog_memoized (insn) < 0
15045 || get_attr_type (insn) != TYPE_MULTI);
15047 cached_can_issue_more = more;
15048 return more;
15051 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
15052 return the first operand of the associated PREF or PREFX insn. */
15055 mips_prefetch_cookie (rtx write, rtx locality)
15057 /* store_streamed / load_streamed. */
15058 if (INTVAL (locality) <= 0)
15059 return GEN_INT (INTVAL (write) + 4);
15061 /* store / load. */
15062 if (INTVAL (locality) <= 2)
15063 return write;
15065 /* store_retained / load_retained. */
15066 return GEN_INT (INTVAL (write) + 6);
15069 /* Flags that indicate when a built-in function is available.
15071 BUILTIN_AVAIL_NON_MIPS16
15072 The function is available on the current target if !TARGET_MIPS16.
15074 BUILTIN_AVAIL_MIPS16
15075 The function is available on the current target if TARGET_MIPS16. */
15076 #define BUILTIN_AVAIL_NON_MIPS16 1
15077 #define BUILTIN_AVAIL_MIPS16 2
15079 /* Declare an availability predicate for built-in functions that
15080 require non-MIPS16 mode and also require COND to be true.
15081 NAME is the main part of the predicate's name. */
15082 #define AVAIL_NON_MIPS16(NAME, COND) \
15083 static unsigned int \
15084 mips_builtin_avail_##NAME (void) \
15086 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
15089 /* Declare an availability predicate for built-in functions that
15090 support both MIPS16 and non-MIPS16 code and also require COND
15091 to be true. NAME is the main part of the predicate's name. */
15092 #define AVAIL_ALL(NAME, COND) \
15093 static unsigned int \
15094 mips_builtin_avail_##NAME (void) \
15096 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
15099 /* This structure describes a single built-in function. */
15100 struct mips_builtin_description {
15101 /* The code of the main .md file instruction. See mips_builtin_type
15102 for more information. */
15103 enum insn_code icode;
15105 /* The floating-point comparison code to use with ICODE, if any. */
15106 enum mips_fp_condition cond;
15108 /* The name of the built-in function. */
15109 const char *name;
15111 /* Specifies how the function should be expanded. */
15112 enum mips_builtin_type builtin_type;
15114 /* The function's prototype. */
15115 enum mips_function_type function_type;
15117 /* Whether the function is available. */
15118 unsigned int (*avail) (void);
15121 AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI)
15122 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
15123 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
15124 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
15125 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
15126 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
15127 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
15128 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
15129 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
15130 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
15131 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
15132 AVAIL_NON_MIPS16 (msa, TARGET_MSA)
15134 /* Construct a mips_builtin_description from the given arguments.
15136 INSN is the name of the associated instruction pattern, without the
15137 leading CODE_FOR_mips_.
15139 CODE is the floating-point condition code associated with the
15140 function. It can be 'f' if the field is not applicable.
15142 NAME is the name of the function itself, without the leading
15143 "__builtin_mips_".
15145 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
15147 AVAIL is the name of the availability predicate, without the leading
15148 mips_builtin_avail_. */
15149 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
15150 FUNCTION_TYPE, AVAIL) \
15151 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
15152 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
15153 mips_builtin_avail_ ## AVAIL }
15155 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
15156 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
15157 are as for MIPS_BUILTIN. */
15158 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
15159 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
15161 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
15162 are subject to mips_builtin_avail_<AVAIL>. */
15163 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
15164 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
15165 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
15166 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
15167 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
15169 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
15170 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
15171 while the any and all forms are subject to mips_builtin_avail_mips3d. */
15172 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
15173 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
15174 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
15175 mips3d), \
15176 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
15177 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
15178 mips3d), \
15179 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
15180 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
15181 AVAIL), \
15182 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
15183 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
15184 AVAIL)
15186 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
15187 are subject to mips_builtin_avail_mips3d. */
15188 #define CMP_4S_BUILTINS(INSN, COND) \
15189 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
15190 MIPS_BUILTIN_CMP_ANY, \
15191 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
15192 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
15193 MIPS_BUILTIN_CMP_ALL, \
15194 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
15196 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
15197 instruction requires mips_builtin_avail_<AVAIL>. */
15198 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
15199 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
15200 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
15201 AVAIL), \
15202 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
15203 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
15204 AVAIL)
15206 /* Define all the built-in functions related to C.cond.fmt condition COND. */
15207 #define CMP_BUILTINS(COND) \
15208 MOVTF_BUILTINS (c, COND, paired_single), \
15209 MOVTF_BUILTINS (cabs, COND, mips3d), \
15210 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
15211 CMP_PS_BUILTINS (c, COND, paired_single), \
15212 CMP_PS_BUILTINS (cabs, COND, mips3d), \
15213 CMP_4S_BUILTINS (c, COND), \
15214 CMP_4S_BUILTINS (cabs, COND)
15216 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
15217 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
15218 and AVAIL are as for MIPS_BUILTIN. */
15219 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
15220 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
15221 FUNCTION_TYPE, AVAIL)
15223 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
15224 branch instruction. AVAIL is as for MIPS_BUILTIN. */
15225 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
15226 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
15227 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
15229 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
15230 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
15231 builtin_description field. */
15232 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
15233 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
15234 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
15235 FUNCTION_TYPE, mips_builtin_avail_loongson }
15237 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
15238 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
15239 builtin_description field. */
15240 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
15241 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
15243 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
15244 We use functions of this form when the same insn can be usefully applied
15245 to more than one datatype. */
15246 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
15247 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
15249 /* Define an MSA MIPS_BUILTIN_DIRECT function __builtin_msa_<INSN>
15250 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15251 field. */
15252 #define MSA_BUILTIN(INSN, FUNCTION_TYPE) \
15253 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15254 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \
15255 FUNCTION_TYPE, mips_builtin_avail_msa }
15257 /* Define a remapped MSA MIPS_BUILTIN_DIRECT function __builtin_msa_<INSN>
15258 for instruction CODE_FOR_msa_<INSN2>. FUNCTION_TYPE is
15259 a builtin_description field. */
15260 #define MSA_BUILTIN_REMAP(INSN, INSN2, FUNCTION_TYPE) \
15261 { CODE_FOR_msa_ ## INSN2, MIPS_FP_COND_f, \
15262 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \
15263 FUNCTION_TYPE, mips_builtin_avail_msa }
15265 /* Define an MSA MIPS_BUILTIN_MSA_TEST_BRANCH function __builtin_msa_<INSN>
15266 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15267 field. */
15268 #define MSA_BUILTIN_TEST_BRANCH(INSN, FUNCTION_TYPE) \
15269 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15270 "__builtin_msa_" #INSN, MIPS_BUILTIN_MSA_TEST_BRANCH, \
15271 FUNCTION_TYPE, mips_builtin_avail_msa }
15273 /* Define an MSA MIPS_BUILTIN_DIRECT_NO_TARGET function __builtin_msa_<INSN>
15274 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15275 field. */
15276 #define MSA_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE) \
15277 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15278 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
15279 FUNCTION_TYPE, mips_builtin_avail_msa }
15281 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
15282 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
15283 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
15284 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
15285 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
15286 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
15287 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
15288 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
15290 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
15291 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
15292 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
15293 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
15294 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
15295 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
15296 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
15297 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
15298 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
15299 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
15300 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
15301 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
15302 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
15303 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
15304 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
15305 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
15306 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
15307 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
15308 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
15309 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
15310 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
15311 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
15312 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
15313 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
15314 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
15315 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
15316 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
15317 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
15318 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
15319 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
15321 #define CODE_FOR_msa_adds_s_b CODE_FOR_ssaddv16qi3
15322 #define CODE_FOR_msa_adds_s_h CODE_FOR_ssaddv8hi3
15323 #define CODE_FOR_msa_adds_s_w CODE_FOR_ssaddv4si3
15324 #define CODE_FOR_msa_adds_s_d CODE_FOR_ssaddv2di3
15325 #define CODE_FOR_msa_adds_u_b CODE_FOR_usaddv16qi3
15326 #define CODE_FOR_msa_adds_u_h CODE_FOR_usaddv8hi3
15327 #define CODE_FOR_msa_adds_u_w CODE_FOR_usaddv4si3
15328 #define CODE_FOR_msa_adds_u_d CODE_FOR_usaddv2di3
15329 #define CODE_FOR_msa_addv_b CODE_FOR_addv16qi3
15330 #define CODE_FOR_msa_addv_h CODE_FOR_addv8hi3
15331 #define CODE_FOR_msa_addv_w CODE_FOR_addv4si3
15332 #define CODE_FOR_msa_addv_d CODE_FOR_addv2di3
15333 #define CODE_FOR_msa_addvi_b CODE_FOR_addv16qi3
15334 #define CODE_FOR_msa_addvi_h CODE_FOR_addv8hi3
15335 #define CODE_FOR_msa_addvi_w CODE_FOR_addv4si3
15336 #define CODE_FOR_msa_addvi_d CODE_FOR_addv2di3
15337 #define CODE_FOR_msa_and_v CODE_FOR_andv16qi3
15338 #define CODE_FOR_msa_andi_b CODE_FOR_andv16qi3
15339 #define CODE_FOR_msa_bmnz_v CODE_FOR_msa_bmnz_b
15340 #define CODE_FOR_msa_bmnzi_b CODE_FOR_msa_bmnz_b
15341 #define CODE_FOR_msa_bmz_v CODE_FOR_msa_bmz_b
15342 #define CODE_FOR_msa_bmzi_b CODE_FOR_msa_bmz_b
15343 #define CODE_FOR_msa_bnz_v CODE_FOR_msa_bnz_v_b
15344 #define CODE_FOR_msa_bz_v CODE_FOR_msa_bz_v_b
15345 #define CODE_FOR_msa_bsel_v CODE_FOR_msa_bsel_b
15346 #define CODE_FOR_msa_bseli_b CODE_FOR_msa_bsel_b
15347 #define CODE_FOR_msa_ceqi_b CODE_FOR_msa_ceq_b
15348 #define CODE_FOR_msa_ceqi_h CODE_FOR_msa_ceq_h
15349 #define CODE_FOR_msa_ceqi_w CODE_FOR_msa_ceq_w
15350 #define CODE_FOR_msa_ceqi_d CODE_FOR_msa_ceq_d
15351 #define CODE_FOR_msa_clti_s_b CODE_FOR_msa_clt_s_b
15352 #define CODE_FOR_msa_clti_s_h CODE_FOR_msa_clt_s_h
15353 #define CODE_FOR_msa_clti_s_w CODE_FOR_msa_clt_s_w
15354 #define CODE_FOR_msa_clti_s_d CODE_FOR_msa_clt_s_d
15355 #define CODE_FOR_msa_clti_u_b CODE_FOR_msa_clt_u_b
15356 #define CODE_FOR_msa_clti_u_h CODE_FOR_msa_clt_u_h
15357 #define CODE_FOR_msa_clti_u_w CODE_FOR_msa_clt_u_w
15358 #define CODE_FOR_msa_clti_u_d CODE_FOR_msa_clt_u_d
15359 #define CODE_FOR_msa_clei_s_b CODE_FOR_msa_cle_s_b
15360 #define CODE_FOR_msa_clei_s_h CODE_FOR_msa_cle_s_h
15361 #define CODE_FOR_msa_clei_s_w CODE_FOR_msa_cle_s_w
15362 #define CODE_FOR_msa_clei_s_d CODE_FOR_msa_cle_s_d
15363 #define CODE_FOR_msa_clei_u_b CODE_FOR_msa_cle_u_b
15364 #define CODE_FOR_msa_clei_u_h CODE_FOR_msa_cle_u_h
15365 #define CODE_FOR_msa_clei_u_w CODE_FOR_msa_cle_u_w
15366 #define CODE_FOR_msa_clei_u_d CODE_FOR_msa_cle_u_d
15367 #define CODE_FOR_msa_div_s_b CODE_FOR_divv16qi3
15368 #define CODE_FOR_msa_div_s_h CODE_FOR_divv8hi3
15369 #define CODE_FOR_msa_div_s_w CODE_FOR_divv4si3
15370 #define CODE_FOR_msa_div_s_d CODE_FOR_divv2di3
15371 #define CODE_FOR_msa_div_u_b CODE_FOR_udivv16qi3
15372 #define CODE_FOR_msa_div_u_h CODE_FOR_udivv8hi3
15373 #define CODE_FOR_msa_div_u_w CODE_FOR_udivv4si3
15374 #define CODE_FOR_msa_div_u_d CODE_FOR_udivv2di3
15375 #define CODE_FOR_msa_fadd_w CODE_FOR_addv4sf3
15376 #define CODE_FOR_msa_fadd_d CODE_FOR_addv2df3
15377 #define CODE_FOR_msa_fexdo_w CODE_FOR_vec_pack_trunc_v2df
15378 #define CODE_FOR_msa_ftrunc_s_w CODE_FOR_fix_truncv4sfv4si2
15379 #define CODE_FOR_msa_ftrunc_s_d CODE_FOR_fix_truncv2dfv2di2
15380 #define CODE_FOR_msa_ftrunc_u_w CODE_FOR_fixuns_truncv4sfv4si2
15381 #define CODE_FOR_msa_ftrunc_u_d CODE_FOR_fixuns_truncv2dfv2di2
15382 #define CODE_FOR_msa_ffint_s_w CODE_FOR_floatv4siv4sf2
15383 #define CODE_FOR_msa_ffint_s_d CODE_FOR_floatv2div2df2
15384 #define CODE_FOR_msa_ffint_u_w CODE_FOR_floatunsv4siv4sf2
15385 #define CODE_FOR_msa_ffint_u_d CODE_FOR_floatunsv2div2df2
15386 #define CODE_FOR_msa_fsub_w CODE_FOR_subv4sf3
15387 #define CODE_FOR_msa_fsub_d CODE_FOR_subv2df3
15388 #define CODE_FOR_msa_fmadd_w CODE_FOR_fmav4sf4
15389 #define CODE_FOR_msa_fmadd_d CODE_FOR_fmav2df4
15390 #define CODE_FOR_msa_fmsub_w CODE_FOR_fnmav4sf4
15391 #define CODE_FOR_msa_fmsub_d CODE_FOR_fnmav2df4
15392 #define CODE_FOR_msa_fmul_w CODE_FOR_mulv4sf3
15393 #define CODE_FOR_msa_fmul_d CODE_FOR_mulv2df3
15394 #define CODE_FOR_msa_fdiv_w CODE_FOR_divv4sf3
15395 #define CODE_FOR_msa_fdiv_d CODE_FOR_divv2df3
15396 #define CODE_FOR_msa_fmax_w CODE_FOR_smaxv4sf3
15397 #define CODE_FOR_msa_fmax_d CODE_FOR_smaxv2df3
15398 #define CODE_FOR_msa_fmin_w CODE_FOR_sminv4sf3
15399 #define CODE_FOR_msa_fmin_d CODE_FOR_sminv2df3
15400 #define CODE_FOR_msa_fsqrt_w CODE_FOR_sqrtv4sf2
15401 #define CODE_FOR_msa_fsqrt_d CODE_FOR_sqrtv2df2
15402 #define CODE_FOR_msa_max_s_b CODE_FOR_smaxv16qi3
15403 #define CODE_FOR_msa_max_s_h CODE_FOR_smaxv8hi3
15404 #define CODE_FOR_msa_max_s_w CODE_FOR_smaxv4si3
15405 #define CODE_FOR_msa_max_s_d CODE_FOR_smaxv2di3
15406 #define CODE_FOR_msa_maxi_s_b CODE_FOR_smaxv16qi3
15407 #define CODE_FOR_msa_maxi_s_h CODE_FOR_smaxv8hi3
15408 #define CODE_FOR_msa_maxi_s_w CODE_FOR_smaxv4si3
15409 #define CODE_FOR_msa_maxi_s_d CODE_FOR_smaxv2di3
15410 #define CODE_FOR_msa_max_u_b CODE_FOR_umaxv16qi3
15411 #define CODE_FOR_msa_max_u_h CODE_FOR_umaxv8hi3
15412 #define CODE_FOR_msa_max_u_w CODE_FOR_umaxv4si3
15413 #define CODE_FOR_msa_max_u_d CODE_FOR_umaxv2di3
15414 #define CODE_FOR_msa_maxi_u_b CODE_FOR_umaxv16qi3
15415 #define CODE_FOR_msa_maxi_u_h CODE_FOR_umaxv8hi3
15416 #define CODE_FOR_msa_maxi_u_w CODE_FOR_umaxv4si3
15417 #define CODE_FOR_msa_maxi_u_d CODE_FOR_umaxv2di3
15418 #define CODE_FOR_msa_min_s_b CODE_FOR_sminv16qi3
15419 #define CODE_FOR_msa_min_s_h CODE_FOR_sminv8hi3
15420 #define CODE_FOR_msa_min_s_w CODE_FOR_sminv4si3
15421 #define CODE_FOR_msa_min_s_d CODE_FOR_sminv2di3
15422 #define CODE_FOR_msa_mini_s_b CODE_FOR_sminv16qi3
15423 #define CODE_FOR_msa_mini_s_h CODE_FOR_sminv8hi3
15424 #define CODE_FOR_msa_mini_s_w CODE_FOR_sminv4si3
15425 #define CODE_FOR_msa_mini_s_d CODE_FOR_sminv2di3
15426 #define CODE_FOR_msa_min_u_b CODE_FOR_uminv16qi3
15427 #define CODE_FOR_msa_min_u_h CODE_FOR_uminv8hi3
15428 #define CODE_FOR_msa_min_u_w CODE_FOR_uminv4si3
15429 #define CODE_FOR_msa_min_u_d CODE_FOR_uminv2di3
15430 #define CODE_FOR_msa_mini_u_b CODE_FOR_uminv16qi3
15431 #define CODE_FOR_msa_mini_u_h CODE_FOR_uminv8hi3
15432 #define CODE_FOR_msa_mini_u_w CODE_FOR_uminv4si3
15433 #define CODE_FOR_msa_mini_u_d CODE_FOR_uminv2di3
15434 #define CODE_FOR_msa_mod_s_b CODE_FOR_modv16qi3
15435 #define CODE_FOR_msa_mod_s_h CODE_FOR_modv8hi3
15436 #define CODE_FOR_msa_mod_s_w CODE_FOR_modv4si3
15437 #define CODE_FOR_msa_mod_s_d CODE_FOR_modv2di3
15438 #define CODE_FOR_msa_mod_u_b CODE_FOR_umodv16qi3
15439 #define CODE_FOR_msa_mod_u_h CODE_FOR_umodv8hi3
15440 #define CODE_FOR_msa_mod_u_w CODE_FOR_umodv4si3
15441 #define CODE_FOR_msa_mod_u_d CODE_FOR_umodv2di3
15442 #define CODE_FOR_msa_mod_s_b CODE_FOR_modv16qi3
15443 #define CODE_FOR_msa_mod_s_h CODE_FOR_modv8hi3
15444 #define CODE_FOR_msa_mod_s_w CODE_FOR_modv4si3
15445 #define CODE_FOR_msa_mod_s_d CODE_FOR_modv2di3
15446 #define CODE_FOR_msa_mod_u_b CODE_FOR_umodv16qi3
15447 #define CODE_FOR_msa_mod_u_h CODE_FOR_umodv8hi3
15448 #define CODE_FOR_msa_mod_u_w CODE_FOR_umodv4si3
15449 #define CODE_FOR_msa_mod_u_d CODE_FOR_umodv2di3
15450 #define CODE_FOR_msa_mulv_b CODE_FOR_mulv16qi3
15451 #define CODE_FOR_msa_mulv_h CODE_FOR_mulv8hi3
15452 #define CODE_FOR_msa_mulv_w CODE_FOR_mulv4si3
15453 #define CODE_FOR_msa_mulv_d CODE_FOR_mulv2di3
15454 #define CODE_FOR_msa_nlzc_b CODE_FOR_clzv16qi2
15455 #define CODE_FOR_msa_nlzc_h CODE_FOR_clzv8hi2
15456 #define CODE_FOR_msa_nlzc_w CODE_FOR_clzv4si2
15457 #define CODE_FOR_msa_nlzc_d CODE_FOR_clzv2di2
15458 #define CODE_FOR_msa_nor_v CODE_FOR_msa_nor_b
15459 #define CODE_FOR_msa_or_v CODE_FOR_iorv16qi3
15460 #define CODE_FOR_msa_ori_b CODE_FOR_iorv16qi3
15461 #define CODE_FOR_msa_nori_b CODE_FOR_msa_nor_b
15462 #define CODE_FOR_msa_pcnt_b CODE_FOR_popcountv16qi2
15463 #define CODE_FOR_msa_pcnt_h CODE_FOR_popcountv8hi2
15464 #define CODE_FOR_msa_pcnt_w CODE_FOR_popcountv4si2
15465 #define CODE_FOR_msa_pcnt_d CODE_FOR_popcountv2di2
15466 #define CODE_FOR_msa_xor_v CODE_FOR_xorv16qi3
15467 #define CODE_FOR_msa_xori_b CODE_FOR_xorv16qi3
15468 #define CODE_FOR_msa_sll_b CODE_FOR_vashlv16qi3
15469 #define CODE_FOR_msa_sll_h CODE_FOR_vashlv8hi3
15470 #define CODE_FOR_msa_sll_w CODE_FOR_vashlv4si3
15471 #define CODE_FOR_msa_sll_d CODE_FOR_vashlv2di3
15472 #define CODE_FOR_msa_slli_b CODE_FOR_vashlv16qi3
15473 #define CODE_FOR_msa_slli_h CODE_FOR_vashlv8hi3
15474 #define CODE_FOR_msa_slli_w CODE_FOR_vashlv4si3
15475 #define CODE_FOR_msa_slli_d CODE_FOR_vashlv2di3
15476 #define CODE_FOR_msa_sra_b CODE_FOR_vashrv16qi3
15477 #define CODE_FOR_msa_sra_h CODE_FOR_vashrv8hi3
15478 #define CODE_FOR_msa_sra_w CODE_FOR_vashrv4si3
15479 #define CODE_FOR_msa_sra_d CODE_FOR_vashrv2di3
15480 #define CODE_FOR_msa_srai_b CODE_FOR_vashrv16qi3
15481 #define CODE_FOR_msa_srai_h CODE_FOR_vashrv8hi3
15482 #define CODE_FOR_msa_srai_w CODE_FOR_vashrv4si3
15483 #define CODE_FOR_msa_srai_d CODE_FOR_vashrv2di3
15484 #define CODE_FOR_msa_srl_b CODE_FOR_vlshrv16qi3
15485 #define CODE_FOR_msa_srl_h CODE_FOR_vlshrv8hi3
15486 #define CODE_FOR_msa_srl_w CODE_FOR_vlshrv4si3
15487 #define CODE_FOR_msa_srl_d CODE_FOR_vlshrv2di3
15488 #define CODE_FOR_msa_srli_b CODE_FOR_vlshrv16qi3
15489 #define CODE_FOR_msa_srli_h CODE_FOR_vlshrv8hi3
15490 #define CODE_FOR_msa_srli_w CODE_FOR_vlshrv4si3
15491 #define CODE_FOR_msa_srli_d CODE_FOR_vlshrv2di3
15492 #define CODE_FOR_msa_subv_b CODE_FOR_subv16qi3
15493 #define CODE_FOR_msa_subv_h CODE_FOR_subv8hi3
15494 #define CODE_FOR_msa_subv_w CODE_FOR_subv4si3
15495 #define CODE_FOR_msa_subv_d CODE_FOR_subv2di3
15496 #define CODE_FOR_msa_subvi_b CODE_FOR_subv16qi3
15497 #define CODE_FOR_msa_subvi_h CODE_FOR_subv8hi3
15498 #define CODE_FOR_msa_subvi_w CODE_FOR_subv4si3
15499 #define CODE_FOR_msa_subvi_d CODE_FOR_subv2di3
15501 #define CODE_FOR_msa_move_v CODE_FOR_movv16qi
15503 #define CODE_FOR_msa_vshf_b CODE_FOR_vec_permv16qi
15504 #define CODE_FOR_msa_vshf_h CODE_FOR_vec_permv8hi
15505 #define CODE_FOR_msa_vshf_w CODE_FOR_vec_permv4si
15506 #define CODE_FOR_msa_vshf_d CODE_FOR_vec_permv2di
15508 #define CODE_FOR_msa_ilvod_d CODE_FOR_msa_ilvl_d
15509 #define CODE_FOR_msa_ilvev_d CODE_FOR_msa_ilvr_d
15510 #define CODE_FOR_msa_pckod_d CODE_FOR_msa_ilvl_d
15511 #define CODE_FOR_msa_pckev_d CODE_FOR_msa_ilvr_d
15513 #define CODE_FOR_msa_ldi_b CODE_FOR_msa_ldiv16qi
15514 #define CODE_FOR_msa_ldi_h CODE_FOR_msa_ldiv8hi
15515 #define CODE_FOR_msa_ldi_w CODE_FOR_msa_ldiv4si
15516 #define CODE_FOR_msa_ldi_d CODE_FOR_msa_ldiv2di
15518 static const struct mips_builtin_description mips_builtins[] = {
15519 #define MIPS_GET_FCSR 0
15520 DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float),
15521 #define MIPS_SET_FCSR 1
15522 DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float),
15524 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
15525 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
15526 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
15527 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
15528 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
15529 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
15530 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
15531 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
15533 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
15534 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
15535 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
15536 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
15537 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
15539 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
15540 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
15541 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
15542 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
15543 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
15544 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
15546 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
15547 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
15548 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
15549 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
15550 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
15551 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
15553 MIPS_FP_CONDITIONS (CMP_BUILTINS),
15555 /* Built-in functions for the SB-1 processor. */
15556 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
15558 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
15559 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15560 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15561 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
15562 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
15563 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
15564 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15565 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15566 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
15567 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
15568 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
15569 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
15570 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
15571 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
15572 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
15573 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
15574 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
15575 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
15576 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
15577 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
15578 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
15579 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
15580 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
15581 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
15582 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
15583 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
15584 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
15585 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
15586 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
15587 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
15588 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
15589 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
15590 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
15591 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
15592 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
15593 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
15594 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
15595 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
15596 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
15597 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
15598 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
15599 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15600 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
15601 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
15602 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
15603 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
15604 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
15605 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
15606 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
15607 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
15608 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
15609 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
15610 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
15611 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
15612 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
15613 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
15614 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
15615 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
15616 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15617 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15618 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
15619 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
15620 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
15621 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
15622 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
15623 BPOSGE_BUILTIN (32, dsp),
15625 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
15626 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
15627 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15628 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15629 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
15630 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
15631 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
15632 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
15633 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
15634 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
15635 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
15636 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15637 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15638 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15639 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15640 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15641 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
15642 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
15643 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
15644 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
15645 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
15646 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
15647 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
15648 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15649 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15650 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
15651 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
15652 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15653 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15654 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15655 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15656 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15657 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15658 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15659 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15661 /* Built-in functions for the DSP ASE (32-bit only). */
15662 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
15663 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
15664 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
15665 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
15666 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15667 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15668 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15669 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
15670 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
15671 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15672 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15673 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15674 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15675 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
15676 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
15677 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
15678 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
15679 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
15680 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
15681 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
15682 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
15683 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
15684 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
15685 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
15686 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
15687 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
15688 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
15690 /* Built-in functions for the DSP ASE (64-bit only). */
15691 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
15693 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
15694 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15695 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15696 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15697 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15698 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15699 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15700 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15701 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15702 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15704 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
15705 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
15706 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
15707 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
15708 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
15709 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15710 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15711 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
15712 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
15713 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
15714 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
15715 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
15716 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
15717 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
15718 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15719 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15720 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
15721 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
15722 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15723 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15724 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
15725 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
15726 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
15727 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
15728 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15729 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15730 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
15731 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15732 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15733 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
15734 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
15735 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
15736 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
15737 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15738 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15739 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
15740 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
15741 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
15742 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
15743 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
15744 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15745 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15746 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15747 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15748 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
15749 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
15750 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
15751 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
15752 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
15753 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
15754 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15755 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
15756 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15757 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
15758 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
15759 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15760 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
15761 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
15762 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
15763 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15764 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
15765 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
15766 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
15767 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
15768 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
15769 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
15770 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
15771 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
15772 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
15773 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
15774 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
15775 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
15776 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
15777 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
15778 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
15779 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
15780 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
15781 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15782 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15783 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
15784 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
15785 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
15786 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
15787 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
15788 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
15789 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
15790 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15791 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15792 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15793 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15794 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
15795 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
15796 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
15797 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
15798 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
15799 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
15800 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
15801 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
15802 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
15803 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
15805 /* Sundry other built-in functions. */
15806 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache),
15808 /* Built-in functions for MSA. */
15809 MSA_BUILTIN (sll_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15810 MSA_BUILTIN (sll_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15811 MSA_BUILTIN (sll_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15812 MSA_BUILTIN (sll_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15813 MSA_BUILTIN (slli_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15814 MSA_BUILTIN (slli_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15815 MSA_BUILTIN (slli_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15816 MSA_BUILTIN (slli_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15817 MSA_BUILTIN (sra_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15818 MSA_BUILTIN (sra_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15819 MSA_BUILTIN (sra_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15820 MSA_BUILTIN (sra_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15821 MSA_BUILTIN (srai_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15822 MSA_BUILTIN (srai_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15823 MSA_BUILTIN (srai_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15824 MSA_BUILTIN (srai_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15825 MSA_BUILTIN (srar_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15826 MSA_BUILTIN (srar_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15827 MSA_BUILTIN (srar_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15828 MSA_BUILTIN (srar_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15829 MSA_BUILTIN (srari_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15830 MSA_BUILTIN (srari_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15831 MSA_BUILTIN (srari_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15832 MSA_BUILTIN (srari_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15833 MSA_BUILTIN (srl_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15834 MSA_BUILTIN (srl_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15835 MSA_BUILTIN (srl_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15836 MSA_BUILTIN (srl_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15837 MSA_BUILTIN (srli_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15838 MSA_BUILTIN (srli_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15839 MSA_BUILTIN (srli_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15840 MSA_BUILTIN (srli_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15841 MSA_BUILTIN (srlr_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15842 MSA_BUILTIN (srlr_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15843 MSA_BUILTIN (srlr_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15844 MSA_BUILTIN (srlr_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15845 MSA_BUILTIN (srlri_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15846 MSA_BUILTIN (srlri_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15847 MSA_BUILTIN (srlri_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15848 MSA_BUILTIN (srlri_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15849 MSA_BUILTIN (bclr_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
15850 MSA_BUILTIN (bclr_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
15851 MSA_BUILTIN (bclr_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
15852 MSA_BUILTIN (bclr_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
15853 MSA_BUILTIN (bclri_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
15854 MSA_BUILTIN (bclri_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
15855 MSA_BUILTIN (bclri_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
15856 MSA_BUILTIN (bclri_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
15857 MSA_BUILTIN (bset_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
15858 MSA_BUILTIN (bset_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
15859 MSA_BUILTIN (bset_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
15860 MSA_BUILTIN (bset_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
15861 MSA_BUILTIN (bseti_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
15862 MSA_BUILTIN (bseti_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
15863 MSA_BUILTIN (bseti_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
15864 MSA_BUILTIN (bseti_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
15865 MSA_BUILTIN (bneg_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
15866 MSA_BUILTIN (bneg_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
15867 MSA_BUILTIN (bneg_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
15868 MSA_BUILTIN (bneg_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
15869 MSA_BUILTIN (bnegi_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
15870 MSA_BUILTIN (bnegi_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
15871 MSA_BUILTIN (bnegi_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
15872 MSA_BUILTIN (bnegi_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
15873 MSA_BUILTIN (binsl_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI),
15874 MSA_BUILTIN (binsl_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI),
15875 MSA_BUILTIN (binsl_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI),
15876 MSA_BUILTIN (binsl_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI),
15877 MSA_BUILTIN (binsli_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI),
15878 MSA_BUILTIN (binsli_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI),
15879 MSA_BUILTIN (binsli_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI),
15880 MSA_BUILTIN (binsli_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI),
15881 MSA_BUILTIN (binsr_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI),
15882 MSA_BUILTIN (binsr_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI),
15883 MSA_BUILTIN (binsr_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI),
15884 MSA_BUILTIN (binsr_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI),
15885 MSA_BUILTIN (binsri_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI),
15886 MSA_BUILTIN (binsri_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI),
15887 MSA_BUILTIN (binsri_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI),
15888 MSA_BUILTIN (binsri_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI),
15889 MSA_BUILTIN (addv_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15890 MSA_BUILTIN (addv_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15891 MSA_BUILTIN (addv_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15892 MSA_BUILTIN (addv_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15893 MSA_BUILTIN (addvi_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15894 MSA_BUILTIN (addvi_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15895 MSA_BUILTIN (addvi_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15896 MSA_BUILTIN (addvi_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15897 MSA_BUILTIN (subv_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15898 MSA_BUILTIN (subv_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15899 MSA_BUILTIN (subv_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15900 MSA_BUILTIN (subv_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15901 MSA_BUILTIN (subvi_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15902 MSA_BUILTIN (subvi_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15903 MSA_BUILTIN (subvi_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15904 MSA_BUILTIN (subvi_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15905 MSA_BUILTIN (max_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15906 MSA_BUILTIN (max_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15907 MSA_BUILTIN (max_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15908 MSA_BUILTIN (max_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15909 MSA_BUILTIN (maxi_s_b, MIPS_V16QI_FTYPE_V16QI_QI),
15910 MSA_BUILTIN (maxi_s_h, MIPS_V8HI_FTYPE_V8HI_QI),
15911 MSA_BUILTIN (maxi_s_w, MIPS_V4SI_FTYPE_V4SI_QI),
15912 MSA_BUILTIN (maxi_s_d, MIPS_V2DI_FTYPE_V2DI_QI),
15913 MSA_BUILTIN (max_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
15914 MSA_BUILTIN (max_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
15915 MSA_BUILTIN (max_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
15916 MSA_BUILTIN (max_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
15917 MSA_BUILTIN (maxi_u_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
15918 MSA_BUILTIN (maxi_u_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
15919 MSA_BUILTIN (maxi_u_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
15920 MSA_BUILTIN (maxi_u_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
15921 MSA_BUILTIN (min_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15922 MSA_BUILTIN (min_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15923 MSA_BUILTIN (min_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15924 MSA_BUILTIN (min_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15925 MSA_BUILTIN (mini_s_b, MIPS_V16QI_FTYPE_V16QI_QI),
15926 MSA_BUILTIN (mini_s_h, MIPS_V8HI_FTYPE_V8HI_QI),
15927 MSA_BUILTIN (mini_s_w, MIPS_V4SI_FTYPE_V4SI_QI),
15928 MSA_BUILTIN (mini_s_d, MIPS_V2DI_FTYPE_V2DI_QI),
15929 MSA_BUILTIN (min_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
15930 MSA_BUILTIN (min_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
15931 MSA_BUILTIN (min_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
15932 MSA_BUILTIN (min_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
15933 MSA_BUILTIN (mini_u_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
15934 MSA_BUILTIN (mini_u_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
15935 MSA_BUILTIN (mini_u_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
15936 MSA_BUILTIN (mini_u_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
15937 MSA_BUILTIN (max_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15938 MSA_BUILTIN (max_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15939 MSA_BUILTIN (max_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15940 MSA_BUILTIN (max_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15941 MSA_BUILTIN (min_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15942 MSA_BUILTIN (min_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15943 MSA_BUILTIN (min_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15944 MSA_BUILTIN (min_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15945 MSA_BUILTIN (ceq_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15946 MSA_BUILTIN (ceq_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15947 MSA_BUILTIN (ceq_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15948 MSA_BUILTIN (ceq_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15949 MSA_BUILTIN (ceqi_b, MIPS_V16QI_FTYPE_V16QI_QI),
15950 MSA_BUILTIN (ceqi_h, MIPS_V8HI_FTYPE_V8HI_QI),
15951 MSA_BUILTIN (ceqi_w, MIPS_V4SI_FTYPE_V4SI_QI),
15952 MSA_BUILTIN (ceqi_d, MIPS_V2DI_FTYPE_V2DI_QI),
15953 MSA_BUILTIN (clt_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15954 MSA_BUILTIN (clt_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15955 MSA_BUILTIN (clt_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15956 MSA_BUILTIN (clt_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15957 MSA_BUILTIN (clti_s_b, MIPS_V16QI_FTYPE_V16QI_QI),
15958 MSA_BUILTIN (clti_s_h, MIPS_V8HI_FTYPE_V8HI_QI),
15959 MSA_BUILTIN (clti_s_w, MIPS_V4SI_FTYPE_V4SI_QI),
15960 MSA_BUILTIN (clti_s_d, MIPS_V2DI_FTYPE_V2DI_QI),
15961 MSA_BUILTIN (clt_u_b, MIPS_V16QI_FTYPE_UV16QI_UV16QI),
15962 MSA_BUILTIN (clt_u_h, MIPS_V8HI_FTYPE_UV8HI_UV8HI),
15963 MSA_BUILTIN (clt_u_w, MIPS_V4SI_FTYPE_UV4SI_UV4SI),
15964 MSA_BUILTIN (clt_u_d, MIPS_V2DI_FTYPE_UV2DI_UV2DI),
15965 MSA_BUILTIN (clti_u_b, MIPS_V16QI_FTYPE_UV16QI_UQI),
15966 MSA_BUILTIN (clti_u_h, MIPS_V8HI_FTYPE_UV8HI_UQI),
15967 MSA_BUILTIN (clti_u_w, MIPS_V4SI_FTYPE_UV4SI_UQI),
15968 MSA_BUILTIN (clti_u_d, MIPS_V2DI_FTYPE_UV2DI_UQI),
15969 MSA_BUILTIN (cle_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15970 MSA_BUILTIN (cle_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15971 MSA_BUILTIN (cle_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15972 MSA_BUILTIN (cle_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15973 MSA_BUILTIN (clei_s_b, MIPS_V16QI_FTYPE_V16QI_QI),
15974 MSA_BUILTIN (clei_s_h, MIPS_V8HI_FTYPE_V8HI_QI),
15975 MSA_BUILTIN (clei_s_w, MIPS_V4SI_FTYPE_V4SI_QI),
15976 MSA_BUILTIN (clei_s_d, MIPS_V2DI_FTYPE_V2DI_QI),
15977 MSA_BUILTIN (cle_u_b, MIPS_V16QI_FTYPE_UV16QI_UV16QI),
15978 MSA_BUILTIN (cle_u_h, MIPS_V8HI_FTYPE_UV8HI_UV8HI),
15979 MSA_BUILTIN (cle_u_w, MIPS_V4SI_FTYPE_UV4SI_UV4SI),
15980 MSA_BUILTIN (cle_u_d, MIPS_V2DI_FTYPE_UV2DI_UV2DI),
15981 MSA_BUILTIN (clei_u_b, MIPS_V16QI_FTYPE_UV16QI_UQI),
15982 MSA_BUILTIN (clei_u_h, MIPS_V8HI_FTYPE_UV8HI_UQI),
15983 MSA_BUILTIN (clei_u_w, MIPS_V4SI_FTYPE_UV4SI_UQI),
15984 MSA_BUILTIN (clei_u_d, MIPS_V2DI_FTYPE_UV2DI_UQI),
15985 MSA_BUILTIN (ld_b, MIPS_V16QI_FTYPE_CVPOINTER_SI),
15986 MSA_BUILTIN (ld_h, MIPS_V8HI_FTYPE_CVPOINTER_SI),
15987 MSA_BUILTIN (ld_w, MIPS_V4SI_FTYPE_CVPOINTER_SI),
15988 MSA_BUILTIN (ld_d, MIPS_V2DI_FTYPE_CVPOINTER_SI),
15989 MSA_NO_TARGET_BUILTIN (st_b, MIPS_VOID_FTYPE_V16QI_CVPOINTER_SI),
15990 MSA_NO_TARGET_BUILTIN (st_h, MIPS_VOID_FTYPE_V8HI_CVPOINTER_SI),
15991 MSA_NO_TARGET_BUILTIN (st_w, MIPS_VOID_FTYPE_V4SI_CVPOINTER_SI),
15992 MSA_NO_TARGET_BUILTIN (st_d, MIPS_VOID_FTYPE_V2DI_CVPOINTER_SI),
15993 MSA_BUILTIN (sat_s_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15994 MSA_BUILTIN (sat_s_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15995 MSA_BUILTIN (sat_s_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15996 MSA_BUILTIN (sat_s_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15997 MSA_BUILTIN (sat_u_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
15998 MSA_BUILTIN (sat_u_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
15999 MSA_BUILTIN (sat_u_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
16000 MSA_BUILTIN (sat_u_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
16001 MSA_BUILTIN (add_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16002 MSA_BUILTIN (add_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16003 MSA_BUILTIN (add_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16004 MSA_BUILTIN (add_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16005 MSA_BUILTIN (adds_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16006 MSA_BUILTIN (adds_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16007 MSA_BUILTIN (adds_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16008 MSA_BUILTIN (adds_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16009 MSA_BUILTIN (adds_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16010 MSA_BUILTIN (adds_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16011 MSA_BUILTIN (adds_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16012 MSA_BUILTIN (adds_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16013 MSA_BUILTIN (adds_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16014 MSA_BUILTIN (adds_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16015 MSA_BUILTIN (adds_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16016 MSA_BUILTIN (adds_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16017 MSA_BUILTIN (ave_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16018 MSA_BUILTIN (ave_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16019 MSA_BUILTIN (ave_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16020 MSA_BUILTIN (ave_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16021 MSA_BUILTIN (ave_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16022 MSA_BUILTIN (ave_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16023 MSA_BUILTIN (ave_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16024 MSA_BUILTIN (ave_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16025 MSA_BUILTIN (aver_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16026 MSA_BUILTIN (aver_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16027 MSA_BUILTIN (aver_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16028 MSA_BUILTIN (aver_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16029 MSA_BUILTIN (aver_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16030 MSA_BUILTIN (aver_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16031 MSA_BUILTIN (aver_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16032 MSA_BUILTIN (aver_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16033 MSA_BUILTIN (subs_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16034 MSA_BUILTIN (subs_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16035 MSA_BUILTIN (subs_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16036 MSA_BUILTIN (subs_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16037 MSA_BUILTIN (subs_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16038 MSA_BUILTIN (subs_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16039 MSA_BUILTIN (subs_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16040 MSA_BUILTIN (subs_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16041 MSA_BUILTIN (subsuu_s_b, MIPS_V16QI_FTYPE_UV16QI_UV16QI),
16042 MSA_BUILTIN (subsuu_s_h, MIPS_V8HI_FTYPE_UV8HI_UV8HI),
16043 MSA_BUILTIN (subsuu_s_w, MIPS_V4SI_FTYPE_UV4SI_UV4SI),
16044 MSA_BUILTIN (subsuu_s_d, MIPS_V2DI_FTYPE_UV2DI_UV2DI),
16045 MSA_BUILTIN (subsus_u_b, MIPS_UV16QI_FTYPE_UV16QI_V16QI),
16046 MSA_BUILTIN (subsus_u_h, MIPS_UV8HI_FTYPE_UV8HI_V8HI),
16047 MSA_BUILTIN (subsus_u_w, MIPS_UV4SI_FTYPE_UV4SI_V4SI),
16048 MSA_BUILTIN (subsus_u_d, MIPS_UV2DI_FTYPE_UV2DI_V2DI),
16049 MSA_BUILTIN (asub_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16050 MSA_BUILTIN (asub_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16051 MSA_BUILTIN (asub_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16052 MSA_BUILTIN (asub_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16053 MSA_BUILTIN (asub_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16054 MSA_BUILTIN (asub_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16055 MSA_BUILTIN (asub_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16056 MSA_BUILTIN (asub_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16057 MSA_BUILTIN (mulv_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16058 MSA_BUILTIN (mulv_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16059 MSA_BUILTIN (mulv_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16060 MSA_BUILTIN (mulv_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16061 MSA_BUILTIN (maddv_b, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI),
16062 MSA_BUILTIN (maddv_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16063 MSA_BUILTIN (maddv_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16064 MSA_BUILTIN (maddv_d, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI),
16065 MSA_BUILTIN (msubv_b, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI),
16066 MSA_BUILTIN (msubv_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16067 MSA_BUILTIN (msubv_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16068 MSA_BUILTIN (msubv_d, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI),
16069 MSA_BUILTIN (div_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16070 MSA_BUILTIN (div_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16071 MSA_BUILTIN (div_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16072 MSA_BUILTIN (div_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16073 MSA_BUILTIN (div_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16074 MSA_BUILTIN (div_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16075 MSA_BUILTIN (div_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16076 MSA_BUILTIN (div_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16077 MSA_BUILTIN (hadd_s_h, MIPS_V8HI_FTYPE_V16QI_V16QI),
16078 MSA_BUILTIN (hadd_s_w, MIPS_V4SI_FTYPE_V8HI_V8HI),
16079 MSA_BUILTIN (hadd_s_d, MIPS_V2DI_FTYPE_V4SI_V4SI),
16080 MSA_BUILTIN (hadd_u_h, MIPS_UV8HI_FTYPE_UV16QI_UV16QI),
16081 MSA_BUILTIN (hadd_u_w, MIPS_UV4SI_FTYPE_UV8HI_UV8HI),
16082 MSA_BUILTIN (hadd_u_d, MIPS_UV2DI_FTYPE_UV4SI_UV4SI),
16083 MSA_BUILTIN (hsub_s_h, MIPS_V8HI_FTYPE_V16QI_V16QI),
16084 MSA_BUILTIN (hsub_s_w, MIPS_V4SI_FTYPE_V8HI_V8HI),
16085 MSA_BUILTIN (hsub_s_d, MIPS_V2DI_FTYPE_V4SI_V4SI),
16086 MSA_BUILTIN (hsub_u_h, MIPS_V8HI_FTYPE_UV16QI_UV16QI),
16087 MSA_BUILTIN (hsub_u_w, MIPS_V4SI_FTYPE_UV8HI_UV8HI),
16088 MSA_BUILTIN (hsub_u_d, MIPS_V2DI_FTYPE_UV4SI_UV4SI),
16089 MSA_BUILTIN (mod_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16090 MSA_BUILTIN (mod_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16091 MSA_BUILTIN (mod_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16092 MSA_BUILTIN (mod_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16093 MSA_BUILTIN (mod_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16094 MSA_BUILTIN (mod_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16095 MSA_BUILTIN (mod_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16096 MSA_BUILTIN (mod_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16097 MSA_BUILTIN (dotp_s_h, MIPS_V8HI_FTYPE_V16QI_V16QI),
16098 MSA_BUILTIN (dotp_s_w, MIPS_V4SI_FTYPE_V8HI_V8HI),
16099 MSA_BUILTIN (dotp_s_d, MIPS_V2DI_FTYPE_V4SI_V4SI),
16100 MSA_BUILTIN (dotp_u_h, MIPS_UV8HI_FTYPE_UV16QI_UV16QI),
16101 MSA_BUILTIN (dotp_u_w, MIPS_UV4SI_FTYPE_UV8HI_UV8HI),
16102 MSA_BUILTIN (dotp_u_d, MIPS_UV2DI_FTYPE_UV4SI_UV4SI),
16103 MSA_BUILTIN (dpadd_s_h, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI),
16104 MSA_BUILTIN (dpadd_s_w, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI),
16105 MSA_BUILTIN (dpadd_s_d, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI),
16106 MSA_BUILTIN (dpadd_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV16QI_UV16QI),
16107 MSA_BUILTIN (dpadd_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV8HI_UV8HI),
16108 MSA_BUILTIN (dpadd_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV4SI_UV4SI),
16109 MSA_BUILTIN (dpsub_s_h, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI),
16110 MSA_BUILTIN (dpsub_s_w, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI),
16111 MSA_BUILTIN (dpsub_s_d, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI),
16112 MSA_BUILTIN (dpsub_u_h, MIPS_V8HI_FTYPE_V8HI_UV16QI_UV16QI),
16113 MSA_BUILTIN (dpsub_u_w, MIPS_V4SI_FTYPE_V4SI_UV8HI_UV8HI),
16114 MSA_BUILTIN (dpsub_u_d, MIPS_V2DI_FTYPE_V2DI_UV4SI_UV4SI),
16115 MSA_BUILTIN (sld_b, MIPS_V16QI_FTYPE_V16QI_V16QI_SI),
16116 MSA_BUILTIN (sld_h, MIPS_V8HI_FTYPE_V8HI_V8HI_SI),
16117 MSA_BUILTIN (sld_w, MIPS_V4SI_FTYPE_V4SI_V4SI_SI),
16118 MSA_BUILTIN (sld_d, MIPS_V2DI_FTYPE_V2DI_V2DI_SI),
16119 MSA_BUILTIN (sldi_b, MIPS_V16QI_FTYPE_V16QI_V16QI_UQI),
16120 MSA_BUILTIN (sldi_h, MIPS_V8HI_FTYPE_V8HI_V8HI_UQI),
16121 MSA_BUILTIN (sldi_w, MIPS_V4SI_FTYPE_V4SI_V4SI_UQI),
16122 MSA_BUILTIN (sldi_d, MIPS_V2DI_FTYPE_V2DI_V2DI_UQI),
16123 MSA_BUILTIN (splat_b, MIPS_V16QI_FTYPE_V16QI_SI),
16124 MSA_BUILTIN (splat_h, MIPS_V8HI_FTYPE_V8HI_SI),
16125 MSA_BUILTIN (splat_w, MIPS_V4SI_FTYPE_V4SI_SI),
16126 MSA_BUILTIN (splat_d, MIPS_V2DI_FTYPE_V2DI_SI),
16127 MSA_BUILTIN (splati_b, MIPS_V16QI_FTYPE_V16QI_UQI),
16128 MSA_BUILTIN (splati_h, MIPS_V8HI_FTYPE_V8HI_UQI),
16129 MSA_BUILTIN (splati_w, MIPS_V4SI_FTYPE_V4SI_UQI),
16130 MSA_BUILTIN (splati_d, MIPS_V2DI_FTYPE_V2DI_UQI),
16131 MSA_BUILTIN (pckev_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16132 MSA_BUILTIN (pckev_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16133 MSA_BUILTIN (pckev_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16134 MSA_BUILTIN (pckev_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16135 MSA_BUILTIN (pckod_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16136 MSA_BUILTIN (pckod_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16137 MSA_BUILTIN (pckod_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16138 MSA_BUILTIN (pckod_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16139 MSA_BUILTIN (ilvl_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16140 MSA_BUILTIN (ilvl_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16141 MSA_BUILTIN (ilvl_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16142 MSA_BUILTIN (ilvl_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16143 MSA_BUILTIN (ilvr_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16144 MSA_BUILTIN (ilvr_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16145 MSA_BUILTIN (ilvr_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16146 MSA_BUILTIN (ilvr_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16147 MSA_BUILTIN (ilvev_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16148 MSA_BUILTIN (ilvev_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16149 MSA_BUILTIN (ilvev_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16150 MSA_BUILTIN (ilvev_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16151 MSA_BUILTIN (ilvod_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16152 MSA_BUILTIN (ilvod_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16153 MSA_BUILTIN (ilvod_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16154 MSA_BUILTIN (ilvod_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16155 MSA_BUILTIN (vshf_b, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI),
16156 MSA_BUILTIN (vshf_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16157 MSA_BUILTIN (vshf_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16158 MSA_BUILTIN (vshf_d, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI),
16159 MSA_BUILTIN (and_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16160 MSA_BUILTIN (andi_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
16161 MSA_BUILTIN (or_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16162 MSA_BUILTIN (ori_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
16163 MSA_BUILTIN (nor_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16164 MSA_BUILTIN (nori_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
16165 MSA_BUILTIN (xor_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16166 MSA_BUILTIN (xori_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
16167 MSA_BUILTIN (bmnz_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI),
16168 MSA_BUILTIN (bmnzi_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI),
16169 MSA_BUILTIN (bmz_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI),
16170 MSA_BUILTIN (bmzi_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI),
16171 MSA_BUILTIN (bsel_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI),
16172 MSA_BUILTIN (bseli_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI),
16173 MSA_BUILTIN (shf_b, MIPS_V16QI_FTYPE_V16QI_UQI),
16174 MSA_BUILTIN (shf_h, MIPS_V8HI_FTYPE_V8HI_UQI),
16175 MSA_BUILTIN (shf_w, MIPS_V4SI_FTYPE_V4SI_UQI),
16176 MSA_BUILTIN_TEST_BRANCH (bnz_v, MIPS_SI_FTYPE_UV16QI),
16177 MSA_BUILTIN_TEST_BRANCH (bz_v, MIPS_SI_FTYPE_UV16QI),
16178 MSA_BUILTIN (fill_b, MIPS_V16QI_FTYPE_SI),
16179 MSA_BUILTIN (fill_h, MIPS_V8HI_FTYPE_SI),
16180 MSA_BUILTIN (fill_w, MIPS_V4SI_FTYPE_SI),
16181 MSA_BUILTIN (fill_d, MIPS_V2DI_FTYPE_DI),
16182 MSA_BUILTIN (pcnt_b, MIPS_V16QI_FTYPE_V16QI),
16183 MSA_BUILTIN (pcnt_h, MIPS_V8HI_FTYPE_V8HI),
16184 MSA_BUILTIN (pcnt_w, MIPS_V4SI_FTYPE_V4SI),
16185 MSA_BUILTIN (pcnt_d, MIPS_V2DI_FTYPE_V2DI),
16186 MSA_BUILTIN (nloc_b, MIPS_V16QI_FTYPE_V16QI),
16187 MSA_BUILTIN (nloc_h, MIPS_V8HI_FTYPE_V8HI),
16188 MSA_BUILTIN (nloc_w, MIPS_V4SI_FTYPE_V4SI),
16189 MSA_BUILTIN (nloc_d, MIPS_V2DI_FTYPE_V2DI),
16190 MSA_BUILTIN (nlzc_b, MIPS_V16QI_FTYPE_V16QI),
16191 MSA_BUILTIN (nlzc_h, MIPS_V8HI_FTYPE_V8HI),
16192 MSA_BUILTIN (nlzc_w, MIPS_V4SI_FTYPE_V4SI),
16193 MSA_BUILTIN (nlzc_d, MIPS_V2DI_FTYPE_V2DI),
16194 MSA_BUILTIN (copy_s_b, MIPS_SI_FTYPE_V16QI_UQI),
16195 MSA_BUILTIN (copy_s_h, MIPS_SI_FTYPE_V8HI_UQI),
16196 MSA_BUILTIN (copy_s_w, MIPS_SI_FTYPE_V4SI_UQI),
16197 MSA_BUILTIN (copy_s_d, MIPS_DI_FTYPE_V2DI_UQI),
16198 MSA_BUILTIN (copy_u_b, MIPS_USI_FTYPE_V16QI_UQI),
16199 MSA_BUILTIN (copy_u_h, MIPS_USI_FTYPE_V8HI_UQI),
16200 MSA_BUILTIN_REMAP (copy_u_w, copy_s_w, MIPS_USI_FTYPE_V4SI_UQI),
16201 MSA_BUILTIN_REMAP (copy_u_d, copy_s_d, MIPS_UDI_FTYPE_V2DI_UQI),
16202 MSA_BUILTIN (insert_b, MIPS_V16QI_FTYPE_V16QI_UQI_SI),
16203 MSA_BUILTIN (insert_h, MIPS_V8HI_FTYPE_V8HI_UQI_SI),
16204 MSA_BUILTIN (insert_w, MIPS_V4SI_FTYPE_V4SI_UQI_SI),
16205 MSA_BUILTIN (insert_d, MIPS_V2DI_FTYPE_V2DI_UQI_DI),
16206 MSA_BUILTIN (insve_b, MIPS_V16QI_FTYPE_V16QI_UQI_V16QI),
16207 MSA_BUILTIN (insve_h, MIPS_V8HI_FTYPE_V8HI_UQI_V8HI),
16208 MSA_BUILTIN (insve_w, MIPS_V4SI_FTYPE_V4SI_UQI_V4SI),
16209 MSA_BUILTIN (insve_d, MIPS_V2DI_FTYPE_V2DI_UQI_V2DI),
16210 MSA_BUILTIN_TEST_BRANCH (bnz_b, MIPS_SI_FTYPE_UV16QI),
16211 MSA_BUILTIN_TEST_BRANCH (bnz_h, MIPS_SI_FTYPE_UV8HI),
16212 MSA_BUILTIN_TEST_BRANCH (bnz_w, MIPS_SI_FTYPE_UV4SI),
16213 MSA_BUILTIN_TEST_BRANCH (bnz_d, MIPS_SI_FTYPE_UV2DI),
16214 MSA_BUILTIN_TEST_BRANCH (bz_b, MIPS_SI_FTYPE_UV16QI),
16215 MSA_BUILTIN_TEST_BRANCH (bz_h, MIPS_SI_FTYPE_UV8HI),
16216 MSA_BUILTIN_TEST_BRANCH (bz_w, MIPS_SI_FTYPE_UV4SI),
16217 MSA_BUILTIN_TEST_BRANCH (bz_d, MIPS_SI_FTYPE_UV2DI),
16218 MSA_BUILTIN (ldi_b, MIPS_V16QI_FTYPE_HI),
16219 MSA_BUILTIN (ldi_h, MIPS_V8HI_FTYPE_HI),
16220 MSA_BUILTIN (ldi_w, MIPS_V4SI_FTYPE_HI),
16221 MSA_BUILTIN (ldi_d, MIPS_V2DI_FTYPE_HI),
16222 MSA_BUILTIN (fcaf_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16223 MSA_BUILTIN (fcaf_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16224 MSA_BUILTIN (fcor_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16225 MSA_BUILTIN (fcor_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16226 MSA_BUILTIN (fcun_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16227 MSA_BUILTIN (fcun_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16228 MSA_BUILTIN (fcune_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16229 MSA_BUILTIN (fcune_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16230 MSA_BUILTIN (fcueq_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16231 MSA_BUILTIN (fcueq_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16232 MSA_BUILTIN (fceq_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16233 MSA_BUILTIN (fceq_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16234 MSA_BUILTIN (fcne_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16235 MSA_BUILTIN (fcne_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16236 MSA_BUILTIN (fclt_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16237 MSA_BUILTIN (fclt_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16238 MSA_BUILTIN (fcult_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16239 MSA_BUILTIN (fcult_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16240 MSA_BUILTIN (fcle_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16241 MSA_BUILTIN (fcle_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16242 MSA_BUILTIN (fcule_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16243 MSA_BUILTIN (fcule_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16244 MSA_BUILTIN (fsaf_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16245 MSA_BUILTIN (fsaf_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16246 MSA_BUILTIN (fsor_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16247 MSA_BUILTIN (fsor_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16248 MSA_BUILTIN (fsun_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16249 MSA_BUILTIN (fsun_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16250 MSA_BUILTIN (fsune_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16251 MSA_BUILTIN (fsune_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16252 MSA_BUILTIN (fsueq_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16253 MSA_BUILTIN (fsueq_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16254 MSA_BUILTIN (fseq_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16255 MSA_BUILTIN (fseq_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16256 MSA_BUILTIN (fsne_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16257 MSA_BUILTIN (fsne_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16258 MSA_BUILTIN (fslt_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16259 MSA_BUILTIN (fslt_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16260 MSA_BUILTIN (fsult_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16261 MSA_BUILTIN (fsult_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16262 MSA_BUILTIN (fsle_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16263 MSA_BUILTIN (fsle_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16264 MSA_BUILTIN (fsule_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16265 MSA_BUILTIN (fsule_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16266 MSA_BUILTIN (fadd_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16267 MSA_BUILTIN (fadd_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16268 MSA_BUILTIN (fsub_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16269 MSA_BUILTIN (fsub_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16270 MSA_BUILTIN (fmul_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16271 MSA_BUILTIN (fmul_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16272 MSA_BUILTIN (fdiv_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16273 MSA_BUILTIN (fdiv_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16274 MSA_BUILTIN (fmadd_w, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF),
16275 MSA_BUILTIN (fmadd_d, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF),
16276 MSA_BUILTIN (fmsub_w, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF),
16277 MSA_BUILTIN (fmsub_d, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF),
16278 MSA_BUILTIN (fexp2_w, MIPS_V4SF_FTYPE_V4SF_V4SI),
16279 MSA_BUILTIN (fexp2_d, MIPS_V2DF_FTYPE_V2DF_V2DI),
16280 MSA_BUILTIN (fexdo_h, MIPS_V8HI_FTYPE_V4SF_V4SF),
16281 MSA_BUILTIN (fexdo_w, MIPS_V4SF_FTYPE_V2DF_V2DF),
16282 MSA_BUILTIN (ftq_h, MIPS_V8HI_FTYPE_V4SF_V4SF),
16283 MSA_BUILTIN (ftq_w, MIPS_V4SI_FTYPE_V2DF_V2DF),
16284 MSA_BUILTIN (fmin_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16285 MSA_BUILTIN (fmin_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16286 MSA_BUILTIN (fmin_a_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16287 MSA_BUILTIN (fmin_a_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16288 MSA_BUILTIN (fmax_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16289 MSA_BUILTIN (fmax_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16290 MSA_BUILTIN (fmax_a_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16291 MSA_BUILTIN (fmax_a_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16292 MSA_BUILTIN (mul_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16293 MSA_BUILTIN (mul_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16294 MSA_BUILTIN (mulr_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16295 MSA_BUILTIN (mulr_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16296 MSA_BUILTIN (madd_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16297 MSA_BUILTIN (madd_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16298 MSA_BUILTIN (maddr_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16299 MSA_BUILTIN (maddr_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16300 MSA_BUILTIN (msub_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16301 MSA_BUILTIN (msub_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16302 MSA_BUILTIN (msubr_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16303 MSA_BUILTIN (msubr_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16304 MSA_BUILTIN (fclass_w, MIPS_V4SI_FTYPE_V4SF),
16305 MSA_BUILTIN (fclass_d, MIPS_V2DI_FTYPE_V2DF),
16306 MSA_BUILTIN (fsqrt_w, MIPS_V4SF_FTYPE_V4SF),
16307 MSA_BUILTIN (fsqrt_d, MIPS_V2DF_FTYPE_V2DF),
16308 MSA_BUILTIN (frcp_w, MIPS_V4SF_FTYPE_V4SF),
16309 MSA_BUILTIN (frcp_d, MIPS_V2DF_FTYPE_V2DF),
16310 MSA_BUILTIN (frint_w, MIPS_V4SF_FTYPE_V4SF),
16311 MSA_BUILTIN (frint_d, MIPS_V2DF_FTYPE_V2DF),
16312 MSA_BUILTIN (frsqrt_w, MIPS_V4SF_FTYPE_V4SF),
16313 MSA_BUILTIN (frsqrt_d, MIPS_V2DF_FTYPE_V2DF),
16314 MSA_BUILTIN (flog2_w, MIPS_V4SF_FTYPE_V4SF),
16315 MSA_BUILTIN (flog2_d, MIPS_V2DF_FTYPE_V2DF),
16316 MSA_BUILTIN (fexupl_w, MIPS_V4SF_FTYPE_V8HI),
16317 MSA_BUILTIN (fexupl_d, MIPS_V2DF_FTYPE_V4SF),
16318 MSA_BUILTIN (fexupr_w, MIPS_V4SF_FTYPE_V8HI),
16319 MSA_BUILTIN (fexupr_d, MIPS_V2DF_FTYPE_V4SF),
16320 MSA_BUILTIN (ffql_w, MIPS_V4SF_FTYPE_V8HI),
16321 MSA_BUILTIN (ffql_d, MIPS_V2DF_FTYPE_V4SI),
16322 MSA_BUILTIN (ffqr_w, MIPS_V4SF_FTYPE_V8HI),
16323 MSA_BUILTIN (ffqr_d, MIPS_V2DF_FTYPE_V4SI),
16324 MSA_BUILTIN (ftint_s_w, MIPS_V4SI_FTYPE_V4SF),
16325 MSA_BUILTIN (ftint_s_d, MIPS_V2DI_FTYPE_V2DF),
16326 MSA_BUILTIN (ftint_u_w, MIPS_UV4SI_FTYPE_V4SF),
16327 MSA_BUILTIN (ftint_u_d, MIPS_UV2DI_FTYPE_V2DF),
16328 MSA_BUILTIN (ftrunc_s_w, MIPS_V4SI_FTYPE_V4SF),
16329 MSA_BUILTIN (ftrunc_s_d, MIPS_V2DI_FTYPE_V2DF),
16330 MSA_BUILTIN (ftrunc_u_w, MIPS_UV4SI_FTYPE_V4SF),
16331 MSA_BUILTIN (ftrunc_u_d, MIPS_UV2DI_FTYPE_V2DF),
16332 MSA_BUILTIN (ffint_s_w, MIPS_V4SF_FTYPE_V4SI),
16333 MSA_BUILTIN (ffint_s_d, MIPS_V2DF_FTYPE_V2DI),
16334 MSA_BUILTIN (ffint_u_w, MIPS_V4SF_FTYPE_UV4SI),
16335 MSA_BUILTIN (ffint_u_d, MIPS_V2DF_FTYPE_UV2DI),
16336 MSA_NO_TARGET_BUILTIN (ctcmsa, MIPS_VOID_FTYPE_UQI_SI),
16337 MSA_BUILTIN (cfcmsa, MIPS_SI_FTYPE_UQI),
16338 MSA_BUILTIN (move_v, MIPS_V16QI_FTYPE_V16QI),
16341 /* Index I is the function declaration for mips_builtins[I], or null if the
16342 function isn't defined on this target. */
16343 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
16344 /* Get the index I of the function declaration for mips_builtin_decls[I]
16345 using the instruction code or return null if not defined for the target. */
16346 static GTY(()) int mips_get_builtin_decl_index[NUM_INSN_CODES];
16348 /* MODE is a vector mode whose elements have type TYPE. Return the type
16349 of the vector itself. */
16351 static tree
16352 mips_builtin_vector_type (tree type, machine_mode mode)
16354 static tree types[2 * (int) MAX_MACHINE_MODE];
16355 int mode_index;
16357 mode_index = (int) mode;
16359 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
16360 mode_index += MAX_MACHINE_MODE;
16362 if (types[mode_index] == NULL_TREE)
16363 types[mode_index] = build_vector_type_for_mode (type, mode);
16364 return types[mode_index];
16367 /* Return a type for 'const volatile void *'. */
16369 static tree
16370 mips_build_cvpointer_type (void)
16372 static tree cache;
16374 if (cache == NULL_TREE)
16375 cache = build_pointer_type (build_qualified_type
16376 (void_type_node,
16377 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
16378 return cache;
16381 /* Source-level argument types. */
16382 #define MIPS_ATYPE_VOID void_type_node
16383 #define MIPS_ATYPE_INT integer_type_node
16384 #define MIPS_ATYPE_POINTER ptr_type_node
16385 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
16387 /* Standard mode-based argument types. */
16388 #define MIPS_ATYPE_QI intQI_type_node
16389 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
16390 #define MIPS_ATYPE_HI intHI_type_node
16391 #define MIPS_ATYPE_SI intSI_type_node
16392 #define MIPS_ATYPE_USI unsigned_intSI_type_node
16393 #define MIPS_ATYPE_DI intDI_type_node
16394 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
16395 #define MIPS_ATYPE_SF float_type_node
16396 #define MIPS_ATYPE_DF double_type_node
16398 /* Vector argument types. */
16399 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
16400 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
16401 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
16402 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
16403 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
16404 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
16406 #define MIPS_ATYPE_V2DI \
16407 mips_builtin_vector_type (long_long_integer_type_node, V2DImode)
16408 #define MIPS_ATYPE_V4SI mips_builtin_vector_type (intSI_type_node, V4SImode)
16409 #define MIPS_ATYPE_V8HI mips_builtin_vector_type (intHI_type_node, V8HImode)
16410 #define MIPS_ATYPE_V16QI mips_builtin_vector_type (intQI_type_node, V16QImode)
16411 #define MIPS_ATYPE_V2DF mips_builtin_vector_type (double_type_node, V2DFmode)
16412 #define MIPS_ATYPE_V4SF mips_builtin_vector_type (float_type_node, V4SFmode)
16414 #define MIPS_ATYPE_UV2DI \
16415 mips_builtin_vector_type (long_long_unsigned_type_node, V2DImode)
16416 #define MIPS_ATYPE_UV4SI \
16417 mips_builtin_vector_type (unsigned_intSI_type_node, V4SImode)
16418 #define MIPS_ATYPE_UV8HI \
16419 mips_builtin_vector_type (unsigned_intHI_type_node, V8HImode)
16420 #define MIPS_ATYPE_UV16QI \
16421 mips_builtin_vector_type (unsigned_intQI_type_node, V16QImode)
16423 #define MIPS_ATYPE_UV2SI \
16424 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
16425 #define MIPS_ATYPE_UV4HI \
16426 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
16427 #define MIPS_ATYPE_UV8QI \
16428 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
16430 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
16431 their associated MIPS_ATYPEs. */
16432 #define MIPS_FTYPE_ATYPES1(A, B) \
16433 MIPS_ATYPE_##A, MIPS_ATYPE_##B
16435 #define MIPS_FTYPE_ATYPES2(A, B, C) \
16436 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
16438 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
16439 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
16441 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
16442 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
16443 MIPS_ATYPE_##E
16445 /* Return the function type associated with function prototype TYPE. */
16447 static tree
16448 mips_build_function_type (enum mips_function_type type)
16450 static tree types[(int) MIPS_MAX_FTYPE_MAX];
16452 if (types[(int) type] == NULL_TREE)
16453 switch (type)
16455 #define DEF_MIPS_FTYPE(NUM, ARGS) \
16456 case MIPS_FTYPE_NAME##NUM ARGS: \
16457 types[(int) type] \
16458 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
16459 NULL_TREE); \
16460 break;
16461 #include "config/mips/mips-ftypes.def"
16462 #undef DEF_MIPS_FTYPE
16463 default:
16464 gcc_unreachable ();
16467 return types[(int) type];
16470 /* Implement TARGET_INIT_BUILTINS. */
16472 static void
16473 mips_init_builtins (void)
16475 const struct mips_builtin_description *d;
16476 unsigned int i;
16478 /* Iterate through all of the bdesc arrays, initializing all of the
16479 builtin functions. */
16480 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
16482 d = &mips_builtins[i];
16483 if (d->avail ())
16485 mips_builtin_decls[i]
16486 = add_builtin_function (d->name,
16487 mips_build_function_type (d->function_type),
16488 i, BUILT_IN_MD, NULL, NULL);
16489 mips_get_builtin_decl_index[d->icode] = i;
16494 /* Implement TARGET_BUILTIN_DECL. */
16496 static tree
16497 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
16499 if (code >= ARRAY_SIZE (mips_builtins))
16500 return error_mark_node;
16501 return mips_builtin_decls[code];
16504 /* Implement TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION. */
16506 static tree
16507 mips_builtin_vectorized_function (unsigned int fn, tree type_out, tree type_in)
16509 machine_mode in_mode, out_mode;
16510 int in_n, out_n;
16512 if (TREE_CODE (type_out) != VECTOR_TYPE
16513 || TREE_CODE (type_in) != VECTOR_TYPE
16514 || !ISA_HAS_MSA)
16515 return NULL_TREE;
16517 out_mode = TYPE_MODE (TREE_TYPE (type_out));
16518 out_n = TYPE_VECTOR_SUBPARTS (type_out);
16519 in_mode = TYPE_MODE (TREE_TYPE (type_in));
16520 in_n = TYPE_VECTOR_SUBPARTS (type_in);
16522 /* INSN is the name of the associated instruction pattern, without
16523 the leading CODE_FOR_. */
16524 #define MIPS_GET_BUILTIN(INSN) \
16525 mips_builtin_decls[mips_get_builtin_decl_index[CODE_FOR_##INSN]]
16527 switch (fn)
16529 case BUILT_IN_SQRT:
16530 if (out_mode == DFmode && out_n == 2
16531 && in_mode == DFmode && in_n == 2)
16532 return MIPS_GET_BUILTIN (msa_fsqrt_d);
16533 break;
16534 case BUILT_IN_SQRTF:
16535 if (out_mode == SFmode && out_n == 4
16536 && in_mode == SFmode && in_n == 4)
16537 return MIPS_GET_BUILTIN (msa_fsqrt_w);
16538 break;
16539 default:
16540 break;
16543 return NULL_TREE;
16546 /* Take argument ARGNO from EXP's argument list and convert it into
16547 an expand operand. Store the operand in *OP. */
16549 static void
16550 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
16551 unsigned int argno)
16553 tree arg;
16554 rtx value;
16556 arg = CALL_EXPR_ARG (exp, argno);
16557 value = expand_normal (arg);
16558 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
16561 /* Expand instruction ICODE as part of a built-in function sequence.
16562 Use the first NOPS elements of OPS as the instruction's operands.
16563 HAS_TARGET_P is true if operand 0 is a target; it is false if the
16564 instruction has no target.
16566 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
16568 static rtx
16569 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
16570 struct expand_operand *ops, bool has_target_p)
16572 machine_mode imode;
16574 switch (icode)
16576 case CODE_FOR_msa_addvi_b:
16577 case CODE_FOR_msa_addvi_h:
16578 case CODE_FOR_msa_addvi_w:
16579 case CODE_FOR_msa_addvi_d:
16580 case CODE_FOR_msa_clti_u_b:
16581 case CODE_FOR_msa_clti_u_h:
16582 case CODE_FOR_msa_clti_u_w:
16583 case CODE_FOR_msa_clti_u_d:
16584 case CODE_FOR_msa_clei_u_b:
16585 case CODE_FOR_msa_clei_u_h:
16586 case CODE_FOR_msa_clei_u_w:
16587 case CODE_FOR_msa_clei_u_d:
16588 case CODE_FOR_msa_maxi_u_b:
16589 case CODE_FOR_msa_maxi_u_h:
16590 case CODE_FOR_msa_maxi_u_w:
16591 case CODE_FOR_msa_maxi_u_d:
16592 case CODE_FOR_msa_mini_u_b:
16593 case CODE_FOR_msa_mini_u_h:
16594 case CODE_FOR_msa_mini_u_w:
16595 case CODE_FOR_msa_mini_u_d:
16596 case CODE_FOR_msa_subvi_b:
16597 case CODE_FOR_msa_subvi_h:
16598 case CODE_FOR_msa_subvi_w:
16599 case CODE_FOR_msa_subvi_d:
16600 gcc_assert (has_target_p && nops == 3);
16601 /* We only generate a vector of constants iff the second argument
16602 is an immediate. We also validate the range of the immediate. */
16603 if (!CONST_INT_P (ops[2].value)
16604 || !IN_RANGE (INTVAL (ops[2].value), 0, 31))
16605 break;
16606 ops[2].mode = ops[0].mode;
16607 ops[2].value = mips_gen_const_int_vector (ops[2].mode,
16608 INTVAL (ops[2].value));
16609 break;
16611 case CODE_FOR_msa_ceqi_b:
16612 case CODE_FOR_msa_ceqi_h:
16613 case CODE_FOR_msa_ceqi_w:
16614 case CODE_FOR_msa_ceqi_d:
16615 case CODE_FOR_msa_clti_s_b:
16616 case CODE_FOR_msa_clti_s_h:
16617 case CODE_FOR_msa_clti_s_w:
16618 case CODE_FOR_msa_clti_s_d:
16619 case CODE_FOR_msa_clei_s_b:
16620 case CODE_FOR_msa_clei_s_h:
16621 case CODE_FOR_msa_clei_s_w:
16622 case CODE_FOR_msa_clei_s_d:
16623 case CODE_FOR_msa_maxi_s_b:
16624 case CODE_FOR_msa_maxi_s_h:
16625 case CODE_FOR_msa_maxi_s_w:
16626 case CODE_FOR_msa_maxi_s_d:
16627 case CODE_FOR_msa_mini_s_b:
16628 case CODE_FOR_msa_mini_s_h:
16629 case CODE_FOR_msa_mini_s_w:
16630 case CODE_FOR_msa_mini_s_d:
16631 gcc_assert (has_target_p && nops == 3);
16632 /* We only generate a vector of constants iff the second argument
16633 is an immediate. We also validate the range of the immediate. */
16634 if (!CONST_INT_P (ops[2].value)
16635 || !IN_RANGE (INTVAL (ops[2].value), -16, 15))
16636 break;
16637 ops[2].mode = ops[0].mode;
16638 ops[2].value = mips_gen_const_int_vector (ops[2].mode,
16639 INTVAL (ops[2].value));
16640 break;
16642 case CODE_FOR_msa_andi_b:
16643 case CODE_FOR_msa_ori_b:
16644 case CODE_FOR_msa_nori_b:
16645 case CODE_FOR_msa_xori_b:
16646 gcc_assert (has_target_p && nops == 3);
16647 if (!CONST_INT_P (ops[2].value))
16648 break;
16649 ops[2].mode = ops[0].mode;
16650 ops[2].value = mips_gen_const_int_vector (ops[2].mode,
16651 INTVAL (ops[2].value));
16652 break;
16654 case CODE_FOR_msa_bmzi_b:
16655 case CODE_FOR_msa_bmnzi_b:
16656 case CODE_FOR_msa_bseli_b:
16657 gcc_assert (has_target_p && nops == 4);
16658 if (!CONST_INT_P (ops[3].value))
16659 break;
16660 ops[3].mode = ops[0].mode;
16661 ops[3].value = mips_gen_const_int_vector (ops[3].mode,
16662 INTVAL (ops[3].value));
16663 break;
16665 case CODE_FOR_msa_fill_b:
16666 case CODE_FOR_msa_fill_h:
16667 case CODE_FOR_msa_fill_w:
16668 case CODE_FOR_msa_fill_d:
16669 /* Map the built-ins to vector fill operations. We need fix up the mode
16670 for the element being inserted. */
16671 gcc_assert (has_target_p && nops == 2);
16672 imode = GET_MODE_INNER (ops[0].mode);
16673 ops[1].value = lowpart_subreg (imode, ops[1].value, ops[1].mode);
16674 ops[1].mode = imode;
16675 break;
16677 case CODE_FOR_msa_ilvl_b:
16678 case CODE_FOR_msa_ilvl_h:
16679 case CODE_FOR_msa_ilvl_w:
16680 case CODE_FOR_msa_ilvl_d:
16681 case CODE_FOR_msa_ilvr_b:
16682 case CODE_FOR_msa_ilvr_h:
16683 case CODE_FOR_msa_ilvr_w:
16684 case CODE_FOR_msa_ilvr_d:
16685 case CODE_FOR_msa_ilvev_b:
16686 case CODE_FOR_msa_ilvev_h:
16687 case CODE_FOR_msa_ilvev_w:
16688 case CODE_FOR_msa_ilvod_b:
16689 case CODE_FOR_msa_ilvod_h:
16690 case CODE_FOR_msa_ilvod_w:
16691 case CODE_FOR_msa_pckev_b:
16692 case CODE_FOR_msa_pckev_h:
16693 case CODE_FOR_msa_pckev_w:
16694 case CODE_FOR_msa_pckod_b:
16695 case CODE_FOR_msa_pckod_h:
16696 case CODE_FOR_msa_pckod_w:
16697 /* Swap the operands 1 and 2 for interleave operations. Built-ins follow
16698 convention of ISA, which have op1 as higher component and op2 as lower
16699 component. However, the VEC_PERM op in tree and vec_concat in RTL
16700 expects first operand to be lower component, because of which this
16701 swap is needed for builtins. */
16702 gcc_assert (has_target_p && nops == 3);
16703 std::swap (ops[1], ops[2]);
16704 break;
16706 case CODE_FOR_msa_slli_b:
16707 case CODE_FOR_msa_slli_h:
16708 case CODE_FOR_msa_slli_w:
16709 case CODE_FOR_msa_slli_d:
16710 case CODE_FOR_msa_srai_b:
16711 case CODE_FOR_msa_srai_h:
16712 case CODE_FOR_msa_srai_w:
16713 case CODE_FOR_msa_srai_d:
16714 case CODE_FOR_msa_srli_b:
16715 case CODE_FOR_msa_srli_h:
16716 case CODE_FOR_msa_srli_w:
16717 case CODE_FOR_msa_srli_d:
16718 gcc_assert (has_target_p && nops == 3);
16719 if (!CONST_INT_P (ops[2].value)
16720 || !IN_RANGE (INTVAL (ops[2].value), 0,
16721 GET_MODE_UNIT_PRECISION (ops[0].mode) - 1))
16722 break;
16723 ops[2].mode = ops[0].mode;
16724 ops[2].value = mips_gen_const_int_vector (ops[2].mode,
16725 INTVAL (ops[2].value));
16726 break;
16728 case CODE_FOR_msa_insert_b:
16729 case CODE_FOR_msa_insert_h:
16730 case CODE_FOR_msa_insert_w:
16731 case CODE_FOR_msa_insert_d:
16732 /* Map the built-ins to insert operations. We need to swap operands,
16733 fix up the mode for the element being inserted, and generate
16734 a bit mask for vec_merge. */
16735 gcc_assert (has_target_p && nops == 4);
16736 std::swap (ops[1], ops[2]);
16737 std::swap (ops[1], ops[3]);
16738 imode = GET_MODE_INNER (ops[0].mode);
16739 ops[1].value = lowpart_subreg (imode, ops[1].value, ops[1].mode);
16740 ops[1].mode = imode;
16741 ops[3].value = GEN_INT (1 << INTVAL (ops[3].value));
16742 break;
16744 case CODE_FOR_msa_insve_b:
16745 case CODE_FOR_msa_insve_h:
16746 case CODE_FOR_msa_insve_w:
16747 case CODE_FOR_msa_insve_d:
16748 /* Map the built-ins to element insert operations. We need to swap
16749 operands and generate a bit mask. */
16750 gcc_assert (has_target_p && nops == 4);
16751 std::swap (ops[1], ops[2]);
16752 std::swap (ops[1], ops[3]);
16753 ops[3].value = GEN_INT (1 << INTVAL (ops[3].value));
16754 break;
16756 case CODE_FOR_msa_shf_b:
16757 case CODE_FOR_msa_shf_h:
16758 case CODE_FOR_msa_shf_w:
16759 case CODE_FOR_msa_shf_w_f:
16760 gcc_assert (has_target_p && nops == 3);
16761 ops[2].value = mips_gen_const_int_vector_shuffle (ops[0].mode,
16762 INTVAL (ops[2].value));
16763 break;
16765 case CODE_FOR_msa_vshf_b:
16766 case CODE_FOR_msa_vshf_h:
16767 case CODE_FOR_msa_vshf_w:
16768 case CODE_FOR_msa_vshf_d:
16769 gcc_assert (has_target_p && nops == 4);
16770 std::swap (ops[1], ops[3]);
16771 break;
16773 default:
16774 break;
16777 if (!maybe_expand_insn (icode, nops, ops))
16779 error ("invalid argument to built-in function");
16780 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
16782 return has_target_p ? ops[0].value : const0_rtx;
16785 /* Expand a floating-point comparison for built-in function call EXP.
16786 The first NARGS arguments are the values to be compared. ICODE is
16787 the .md pattern that does the comparison and COND is the condition
16788 that is being tested. Return an rtx for the result. */
16790 static rtx
16791 mips_expand_builtin_compare_1 (enum insn_code icode,
16792 enum mips_fp_condition cond,
16793 tree exp, int nargs)
16795 struct expand_operand ops[MAX_RECOG_OPERANDS];
16796 rtx output;
16797 int opno, argno;
16799 /* The instruction should have a target operand, an operand for each
16800 argument, and an operand for COND. */
16801 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
16803 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
16804 opno = 0;
16805 create_fixed_operand (&ops[opno++], output);
16806 for (argno = 0; argno < nargs; argno++)
16807 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
16808 create_integer_operand (&ops[opno++], (int) cond);
16809 return mips_expand_builtin_insn (icode, opno, ops, true);
16812 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
16813 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
16814 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
16815 suggests a good place to put the result. */
16817 static rtx
16818 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
16819 bool has_target_p)
16821 struct expand_operand ops[MAX_RECOG_OPERANDS];
16822 int opno, argno;
16824 /* Map any target to operand 0. */
16825 opno = 0;
16826 if (has_target_p)
16827 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
16829 /* Map the arguments to the other operands. */
16830 gcc_assert (opno + call_expr_nargs (exp)
16831 == insn_data[icode].n_generator_args);
16832 for (argno = 0; argno < call_expr_nargs (exp); argno++)
16833 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
16835 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
16838 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
16839 function; TYPE says which. EXP is the CALL_EXPR that calls the
16840 function, ICODE is the instruction that should be used to compare
16841 the first two arguments, and COND is the condition it should test.
16842 TARGET, if nonnull, suggests a good place to put the result. */
16844 static rtx
16845 mips_expand_builtin_movtf (enum mips_builtin_type type,
16846 enum insn_code icode, enum mips_fp_condition cond,
16847 rtx target, tree exp)
16849 struct expand_operand ops[4];
16850 rtx cmp_result;
16852 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
16853 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
16854 if (type == MIPS_BUILTIN_MOVT)
16856 mips_prepare_builtin_arg (&ops[2], exp, 2);
16857 mips_prepare_builtin_arg (&ops[1], exp, 3);
16859 else
16861 mips_prepare_builtin_arg (&ops[1], exp, 2);
16862 mips_prepare_builtin_arg (&ops[2], exp, 3);
16864 create_fixed_operand (&ops[3], cmp_result);
16865 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
16866 4, ops, true);
16869 /* Expand an MSA built-in for a compare and branch instruction specified by
16870 ICODE, set a general-purpose register to 1 if the branch was taken,
16871 0 otherwise. */
16873 static rtx
16874 mips_expand_builtin_msa_test_branch (enum insn_code icode, tree exp)
16876 struct expand_operand ops[3];
16877 rtx_insn *cbranch;
16878 rtx_code_label *true_label, *done_label;
16879 rtx cmp_result;
16881 true_label = gen_label_rtx ();
16882 done_label = gen_label_rtx ();
16884 create_input_operand (&ops[0], true_label, TYPE_MODE (TREE_TYPE (exp)));
16885 mips_prepare_builtin_arg (&ops[1], exp, 0);
16886 create_fixed_operand (&ops[2], const0_rtx);
16888 /* Make sure that the operand 1 is a REG. */
16889 if (GET_CODE (ops[1].value) != REG)
16890 ops[1].value = force_reg (ops[1].mode, ops[1].value);
16892 if ((cbranch = maybe_gen_insn (icode, 3, ops)) == NULL_RTX)
16893 error ("failed to expand built-in function");
16895 cmp_result = gen_reg_rtx (SImode);
16897 /* First assume that CMP_RESULT is false. */
16898 mips_emit_move (cmp_result, const0_rtx);
16900 /* Branch to TRUE_LABEL if CBRANCH is taken and DONE_LABEL otherwise. */
16901 emit_jump_insn (cbranch);
16902 emit_jump_insn (gen_jump (done_label));
16903 emit_barrier ();
16905 /* Set CMP_RESULT to true if the branch was taken. */
16906 emit_label (true_label);
16907 mips_emit_move (cmp_result, const1_rtx);
16909 emit_label (done_label);
16910 return cmp_result;
16913 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
16914 into TARGET otherwise. Return TARGET. */
16916 static rtx
16917 mips_builtin_branch_and_move (rtx condition, rtx target,
16918 rtx value_if_true, rtx value_if_false)
16920 rtx_code_label *true_label, *done_label;
16922 true_label = gen_label_rtx ();
16923 done_label = gen_label_rtx ();
16925 /* First assume that CONDITION is false. */
16926 mips_emit_move (target, value_if_false);
16928 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
16929 emit_jump_insn (gen_condjump (condition, true_label));
16930 emit_jump_insn (gen_jump (done_label));
16931 emit_barrier ();
16933 /* Fix TARGET if CONDITION is true. */
16934 emit_label (true_label);
16935 mips_emit_move (target, value_if_true);
16937 emit_label (done_label);
16938 return target;
16941 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
16942 the CALL_EXPR that calls the function, ICODE is the code of the
16943 comparison instruction, and COND is the condition it should test.
16944 TARGET, if nonnull, suggests a good place to put the boolean result. */
16946 static rtx
16947 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
16948 enum insn_code icode, enum mips_fp_condition cond,
16949 rtx target, tree exp)
16951 rtx offset, condition, cmp_result;
16953 if (target == 0 || GET_MODE (target) != SImode)
16954 target = gen_reg_rtx (SImode);
16955 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
16956 call_expr_nargs (exp));
16958 /* If the comparison sets more than one register, we define the result
16959 to be 0 if all registers are false and -1 if all registers are true.
16960 The value of the complete result is indeterminate otherwise. */
16961 switch (builtin_type)
16963 case MIPS_BUILTIN_CMP_ALL:
16964 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
16965 return mips_builtin_branch_and_move (condition, target,
16966 const0_rtx, const1_rtx);
16968 case MIPS_BUILTIN_CMP_UPPER:
16969 case MIPS_BUILTIN_CMP_LOWER:
16970 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
16971 condition = gen_single_cc (cmp_result, offset);
16972 return mips_builtin_branch_and_move (condition, target,
16973 const1_rtx, const0_rtx);
16975 default:
16976 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
16977 return mips_builtin_branch_and_move (condition, target,
16978 const1_rtx, const0_rtx);
16982 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
16983 if nonnull, suggests a good place to put the boolean result. */
16985 static rtx
16986 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
16988 rtx condition, cmp_result;
16989 int cmp_value;
16991 if (target == 0 || GET_MODE (target) != SImode)
16992 target = gen_reg_rtx (SImode);
16994 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
16996 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
16997 cmp_value = 32;
16998 else
16999 gcc_assert (0);
17001 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
17002 return mips_builtin_branch_and_move (condition, target,
17003 const1_rtx, const0_rtx);
17006 /* Implement TARGET_EXPAND_BUILTIN. */
17008 static rtx
17009 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
17010 machine_mode mode, int ignore)
17012 tree fndecl;
17013 unsigned int fcode, avail;
17014 const struct mips_builtin_description *d;
17016 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
17017 fcode = DECL_FUNCTION_CODE (fndecl);
17018 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
17019 d = &mips_builtins[fcode];
17020 avail = d->avail ();
17021 gcc_assert (avail != 0);
17022 if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16))
17024 error ("built-in function %qE not supported for MIPS16",
17025 DECL_NAME (fndecl));
17026 return ignore ? const0_rtx : CONST0_RTX (mode);
17028 switch (d->builtin_type)
17030 case MIPS_BUILTIN_DIRECT:
17031 return mips_expand_builtin_direct (d->icode, target, exp, true);
17033 case MIPS_BUILTIN_DIRECT_NO_TARGET:
17034 return mips_expand_builtin_direct (d->icode, target, exp, false);
17036 case MIPS_BUILTIN_MOVT:
17037 case MIPS_BUILTIN_MOVF:
17038 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
17039 d->cond, target, exp);
17041 case MIPS_BUILTIN_CMP_ANY:
17042 case MIPS_BUILTIN_CMP_ALL:
17043 case MIPS_BUILTIN_CMP_UPPER:
17044 case MIPS_BUILTIN_CMP_LOWER:
17045 case MIPS_BUILTIN_CMP_SINGLE:
17046 return mips_expand_builtin_compare (d->builtin_type, d->icode,
17047 d->cond, target, exp);
17049 case MIPS_BUILTIN_MSA_TEST_BRANCH:
17050 return mips_expand_builtin_msa_test_branch (d->icode, exp);
17052 case MIPS_BUILTIN_BPOSGE32:
17053 return mips_expand_builtin_bposge (d->builtin_type, target);
17055 gcc_unreachable ();
17058 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
17059 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
17060 struct mips16_constant {
17061 struct mips16_constant *next;
17062 rtx value;
17063 rtx_code_label *label;
17064 machine_mode mode;
17067 /* Information about an incomplete MIPS16 constant pool. FIRST is the
17068 first constant, HIGHEST_ADDRESS is the highest address that the first
17069 byte of the pool can have, and INSN_ADDRESS is the current instruction
17070 address. */
17071 struct mips16_constant_pool {
17072 struct mips16_constant *first;
17073 int highest_address;
17074 int insn_address;
17077 /* Add constant VALUE to POOL and return its label. MODE is the
17078 value's mode (used for CONST_INTs, etc.). */
17080 static rtx_code_label *
17081 mips16_add_constant (struct mips16_constant_pool *pool,
17082 rtx value, machine_mode mode)
17084 struct mips16_constant **p, *c;
17085 bool first_of_size_p;
17087 /* See whether the constant is already in the pool. If so, return the
17088 existing label, otherwise leave P pointing to the place where the
17089 constant should be added.
17091 Keep the pool sorted in increasing order of mode size so that we can
17092 reduce the number of alignments needed. */
17093 first_of_size_p = true;
17094 for (p = &pool->first; *p != 0; p = &(*p)->next)
17096 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
17097 return (*p)->label;
17098 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
17099 break;
17100 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
17101 first_of_size_p = false;
17104 /* In the worst case, the constant needed by the earliest instruction
17105 will end up at the end of the pool. The entire pool must then be
17106 accessible from that instruction.
17108 When adding the first constant, set the pool's highest address to
17109 the address of the first out-of-range byte. Adjust this address
17110 downwards each time a new constant is added. */
17111 if (pool->first == 0)
17112 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
17113 of the instruction with the lowest two bits clear. The base PC
17114 value for LDPC has the lowest three bits clear. Assume the worst
17115 case here; namely that the PC-relative instruction occupies the
17116 last 2 bytes in an aligned word. */
17117 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
17118 pool->highest_address -= GET_MODE_SIZE (mode);
17119 if (first_of_size_p)
17120 /* Take into account the worst possible padding due to alignment. */
17121 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
17123 /* Create a new entry. */
17124 c = XNEW (struct mips16_constant);
17125 c->value = value;
17126 c->mode = mode;
17127 c->label = gen_label_rtx ();
17128 c->next = *p;
17129 *p = c;
17131 return c->label;
17134 /* Output constant VALUE after instruction INSN and return the last
17135 instruction emitted. MODE is the mode of the constant. */
17137 static rtx_insn *
17138 mips16_emit_constants_1 (machine_mode mode, rtx value, rtx_insn *insn)
17140 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
17142 rtx size = GEN_INT (GET_MODE_SIZE (mode));
17143 return emit_insn_after (gen_consttable_int (value, size), insn);
17146 if (SCALAR_FLOAT_MODE_P (mode))
17147 return emit_insn_after (gen_consttable_float (value), insn);
17149 if (VECTOR_MODE_P (mode))
17151 int i;
17153 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
17154 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
17155 CONST_VECTOR_ELT (value, i), insn);
17156 return insn;
17159 gcc_unreachable ();
17162 /* Dump out the constants in CONSTANTS after INSN. Record the initial
17163 label number in the `consttable' and `consttable_end' insns emitted
17164 at the beginning and the end of the constant pool respectively, so
17165 that individual pools can be uniquely marked as data for the purpose
17166 of disassembly. */
17168 static void
17169 mips16_emit_constants (struct mips16_constant *constants, rtx_insn *insn)
17171 int label_num = constants ? CODE_LABEL_NUMBER (constants->label) : 0;
17172 struct mips16_constant *c, *next;
17173 int align;
17175 align = 0;
17176 if (constants)
17177 insn = emit_insn_after (gen_consttable (GEN_INT (label_num)), insn);
17178 for (c = constants; c != NULL; c = next)
17180 /* If necessary, increase the alignment of PC. */
17181 if (align < GET_MODE_SIZE (c->mode))
17183 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
17184 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
17186 align = GET_MODE_SIZE (c->mode);
17188 insn = emit_label_after (c->label, insn);
17189 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
17191 next = c->next;
17192 free (c);
17194 if (constants)
17195 insn = emit_insn_after (gen_consttable_end (GEN_INT (label_num)), insn);
17197 emit_barrier_after (insn);
17200 /* Return the length of instruction INSN. */
17202 static int
17203 mips16_insn_length (rtx_insn *insn)
17205 if (JUMP_TABLE_DATA_P (insn))
17207 rtx body = PATTERN (insn);
17208 if (GET_CODE (body) == ADDR_VEC)
17209 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
17210 else if (GET_CODE (body) == ADDR_DIFF_VEC)
17211 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
17212 else
17213 gcc_unreachable ();
17215 return get_attr_length (insn);
17218 /* If *X is a symbolic constant that refers to the constant pool, add
17219 the constant to POOL and rewrite *X to use the constant's label. */
17221 static void
17222 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
17224 rtx base, offset;
17225 rtx_code_label *label;
17227 split_const (*x, &base, &offset);
17228 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
17230 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
17231 get_pool_mode (base));
17232 base = gen_rtx_LABEL_REF (Pmode, label);
17233 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
17237 /* Rewrite INSN so that constant pool references refer to the constant's
17238 label instead. */
17240 static void
17241 mips16_rewrite_pool_refs (rtx_insn *insn, struct mips16_constant_pool *pool)
17243 subrtx_ptr_iterator::array_type array;
17244 FOR_EACH_SUBRTX_PTR (iter, array, &PATTERN (insn), ALL)
17246 rtx *loc = *iter;
17248 if (force_to_mem_operand (*loc, Pmode))
17250 rtx mem = force_const_mem (GET_MODE (*loc), *loc);
17251 validate_change (insn, loc, mem, false);
17254 if (MEM_P (*loc))
17256 mips16_rewrite_pool_constant (pool, &XEXP (*loc, 0));
17257 iter.skip_subrtxes ();
17259 else
17261 if (TARGET_MIPS16_TEXT_LOADS)
17262 mips16_rewrite_pool_constant (pool, loc);
17263 if (GET_CODE (*loc) == CONST
17264 /* Don't rewrite the __mips16_rdwr symbol. */
17265 || (GET_CODE (*loc) == UNSPEC
17266 && XINT (*loc, 1) == UNSPEC_TLS_GET_TP))
17267 iter.skip_subrtxes ();
17272 /* Return whether CFG is used in mips_reorg. */
17274 static bool
17275 mips_cfg_in_reorg (void)
17277 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
17278 || TARGET_RELAX_PIC_CALLS);
17281 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
17282 otherwise assume that they are already split. */
17284 static void
17285 mips16_lay_out_constants (bool split_p)
17287 struct mips16_constant_pool pool;
17288 rtx_insn *insn, *barrier;
17290 if (!TARGET_MIPS16_PCREL_LOADS)
17291 return;
17293 if (split_p)
17295 if (mips_cfg_in_reorg ())
17296 split_all_insns ();
17297 else
17298 split_all_insns_noflow ();
17300 barrier = 0;
17301 memset (&pool, 0, sizeof (pool));
17302 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
17304 /* Rewrite constant pool references in INSN. */
17305 if (USEFUL_INSN_P (insn))
17306 mips16_rewrite_pool_refs (insn, &pool);
17308 pool.insn_address += mips16_insn_length (insn);
17310 if (pool.first != NULL)
17312 /* If there are no natural barriers between the first user of
17313 the pool and the highest acceptable address, we'll need to
17314 create a new instruction to jump around the constant pool.
17315 In the worst case, this instruction will be 4 bytes long.
17317 If it's too late to do this transformation after INSN,
17318 do it immediately before INSN. */
17319 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
17321 rtx_code_label *label;
17322 rtx_insn *jump;
17324 label = gen_label_rtx ();
17326 jump = emit_jump_insn_before (gen_jump (label), insn);
17327 JUMP_LABEL (jump) = label;
17328 LABEL_NUSES (label) = 1;
17329 barrier = emit_barrier_after (jump);
17331 emit_label_after (label, barrier);
17332 pool.insn_address += 4;
17335 /* See whether the constant pool is now out of range of the first
17336 user. If so, output the constants after the previous barrier.
17337 Note that any instructions between BARRIER and INSN (inclusive)
17338 will use negative offsets to refer to the pool. */
17339 if (pool.insn_address > pool.highest_address)
17341 mips16_emit_constants (pool.first, barrier);
17342 pool.first = NULL;
17343 barrier = 0;
17345 else if (BARRIER_P (insn))
17346 barrier = insn;
17349 mips16_emit_constants (pool.first, get_last_insn ());
17352 /* Return true if it is worth r10k_simplify_address's while replacing
17353 an address with X. We are looking for constants, and for addresses
17354 at a known offset from the incoming stack pointer. */
17356 static bool
17357 r10k_simplified_address_p (rtx x)
17359 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
17360 x = XEXP (x, 0);
17361 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
17364 /* X is an expression that appears in INSN. Try to use the UD chains
17365 to simplify it, returning the simplified form on success and the
17366 original form otherwise. Replace the incoming value of $sp with
17367 virtual_incoming_args_rtx (which should never occur in X otherwise). */
17369 static rtx
17370 r10k_simplify_address (rtx x, rtx_insn *insn)
17372 rtx newx, op0, op1, set, note;
17373 rtx_insn *def_insn;
17374 df_ref use, def;
17375 struct df_link *defs;
17377 newx = NULL_RTX;
17378 if (UNARY_P (x))
17380 op0 = r10k_simplify_address (XEXP (x, 0), insn);
17381 if (op0 != XEXP (x, 0))
17382 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
17383 op0, GET_MODE (XEXP (x, 0)));
17385 else if (BINARY_P (x))
17387 op0 = r10k_simplify_address (XEXP (x, 0), insn);
17388 op1 = r10k_simplify_address (XEXP (x, 1), insn);
17389 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
17390 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
17392 else if (GET_CODE (x) == LO_SUM)
17394 /* LO_SUMs can be offset from HIGHs, if we know they won't
17395 overflow. See mips_classify_address for the rationale behind
17396 the lax check. */
17397 op0 = r10k_simplify_address (XEXP (x, 0), insn);
17398 if (GET_CODE (op0) == HIGH)
17399 newx = XEXP (x, 1);
17401 else if (REG_P (x))
17403 /* Uses are recorded by regno_reg_rtx, not X itself. */
17404 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
17405 gcc_assert (use);
17406 defs = DF_REF_CHAIN (use);
17408 /* Require a single definition. */
17409 if (defs && defs->next == NULL)
17411 def = defs->ref;
17412 if (DF_REF_IS_ARTIFICIAL (def))
17414 /* Replace the incoming value of $sp with
17415 virtual_incoming_args_rtx. */
17416 if (x == stack_pointer_rtx
17417 && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun))
17418 newx = virtual_incoming_args_rtx;
17420 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
17421 DF_REF_BB (def)))
17423 /* Make sure that DEF_INSN is a single set of REG. */
17424 def_insn = DF_REF_INSN (def);
17425 if (NONJUMP_INSN_P (def_insn))
17427 set = single_set (def_insn);
17428 if (set && rtx_equal_p (SET_DEST (set), x))
17430 /* Prefer to use notes, since the def-use chains
17431 are often shorter. */
17432 note = find_reg_equal_equiv_note (def_insn);
17433 if (note)
17434 newx = XEXP (note, 0);
17435 else
17436 newx = SET_SRC (set);
17437 newx = r10k_simplify_address (newx, def_insn);
17443 if (newx && r10k_simplified_address_p (newx))
17444 return newx;
17445 return x;
17448 /* Return true if ADDRESS is known to be an uncached address
17449 on R10K systems. */
17451 static bool
17452 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
17454 unsigned HOST_WIDE_INT upper;
17456 /* Check for KSEG1. */
17457 if (address + 0x60000000 < 0x20000000)
17458 return true;
17460 /* Check for uncached XKPHYS addresses. */
17461 if (Pmode == DImode)
17463 upper = (address >> 40) & 0xf9ffff;
17464 if (upper == 0x900000 || upper == 0xb80000)
17465 return true;
17467 return false;
17470 /* Return true if we can prove that an access to address X in instruction
17471 INSN would be safe from R10K speculation. This X is a general
17472 expression; it might not be a legitimate address. */
17474 static bool
17475 r10k_safe_address_p (rtx x, rtx_insn *insn)
17477 rtx base, offset;
17478 HOST_WIDE_INT offset_val;
17480 x = r10k_simplify_address (x, insn);
17482 /* Check for references to the stack frame. It doesn't really matter
17483 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
17484 allows us to assume that accesses to any part of the eventual frame
17485 is safe from speculation at any point in the function. */
17486 mips_split_plus (x, &base, &offset_val);
17487 if (base == virtual_incoming_args_rtx
17488 && offset_val >= -cfun->machine->frame.total_size
17489 && offset_val < cfun->machine->frame.args_size)
17490 return true;
17492 /* Check for uncached addresses. */
17493 if (CONST_INT_P (x))
17494 return r10k_uncached_address_p (INTVAL (x));
17496 /* Check for accesses to a static object. */
17497 split_const (x, &base, &offset);
17498 return offset_within_block_p (base, INTVAL (offset));
17501 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
17502 an in-range access to an automatic variable, or to an object with
17503 a link-time-constant address. */
17505 static bool
17506 r10k_safe_mem_expr_p (tree expr, unsigned HOST_WIDE_INT offset)
17508 HOST_WIDE_INT bitoffset, bitsize;
17509 tree inner, var_offset;
17510 machine_mode mode;
17511 int unsigned_p, reverse_p, volatile_p;
17513 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
17514 &unsigned_p, &reverse_p, &volatile_p);
17515 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
17516 return false;
17518 offset += bitoffset / BITS_PER_UNIT;
17519 return offset < tree_to_uhwi (DECL_SIZE_UNIT (inner));
17522 /* Return true if X contains a MEM that is not safe from R10K speculation.
17523 INSN is the instruction that contains X. */
17525 static bool
17526 r10k_needs_protection_p_1 (rtx x, rtx_insn *insn)
17528 subrtx_var_iterator::array_type array;
17529 FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST)
17531 rtx mem = *iter;
17532 if (MEM_P (mem))
17534 if ((MEM_EXPR (mem)
17535 && MEM_OFFSET_KNOWN_P (mem)
17536 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
17537 || r10k_safe_address_p (XEXP (mem, 0), insn))
17538 iter.skip_subrtxes ();
17539 else
17540 return true;
17543 return false;
17546 /* A note_stores callback for which DATA points to an instruction pointer.
17547 If *DATA is nonnull, make it null if it X contains a MEM that is not
17548 safe from R10K speculation. */
17550 static void
17551 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
17552 void *data)
17554 rtx_insn **insn_ptr;
17556 insn_ptr = (rtx_insn **) data;
17557 if (*insn_ptr && r10k_needs_protection_p_1 (x, *insn_ptr))
17558 *insn_ptr = NULL;
17561 /* X is the pattern of a call instruction. Return true if the call is
17562 not to a declared function. */
17564 static bool
17565 r10k_needs_protection_p_call (const_rtx x)
17567 subrtx_iterator::array_type array;
17568 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
17570 const_rtx mem = *iter;
17571 if (MEM_P (mem))
17573 const_rtx addr = XEXP (mem, 0);
17574 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DECL (addr))
17575 iter.skip_subrtxes ();
17576 else
17577 return true;
17580 return false;
17583 /* Return true if instruction INSN needs to be protected by an R10K
17584 cache barrier. */
17586 static bool
17587 r10k_needs_protection_p (rtx_insn *insn)
17589 if (CALL_P (insn))
17590 return r10k_needs_protection_p_call (PATTERN (insn));
17592 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
17594 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
17595 return insn == NULL_RTX;
17598 return r10k_needs_protection_p_1 (PATTERN (insn), insn);
17601 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
17602 edge is unconditional. */
17604 static bool
17605 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
17607 edge_iterator ei;
17608 edge e;
17610 FOR_EACH_EDGE (e, ei, bb->preds)
17611 if (!single_succ_p (e->src)
17612 || !bitmap_bit_p (protected_bbs, e->src->index)
17613 || (e->flags & EDGE_COMPLEX) != 0)
17614 return false;
17615 return true;
17618 /* Implement -mr10k-cache-barrier= for the current function. */
17620 static void
17621 r10k_insert_cache_barriers (void)
17623 int *rev_post_order;
17624 unsigned int i, n;
17625 basic_block bb;
17626 sbitmap protected_bbs;
17627 rtx_insn *insn, *end;
17628 rtx unprotected_region;
17630 if (TARGET_MIPS16)
17632 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
17633 return;
17636 /* Calculate dominators. */
17637 calculate_dominance_info (CDI_DOMINATORS);
17639 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
17640 X is protected by a cache barrier. */
17641 protected_bbs = sbitmap_alloc (last_basic_block_for_fn (cfun));
17642 bitmap_clear (protected_bbs);
17644 /* Iterate over the basic blocks in reverse post-order. */
17645 rev_post_order = XNEWVEC (int, last_basic_block_for_fn (cfun));
17646 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
17647 for (i = 0; i < n; i++)
17649 bb = BASIC_BLOCK_FOR_FN (cfun, rev_post_order[i]);
17651 /* If this block is only reached by unconditional edges, and if the
17652 source of every edge is protected, the beginning of the block is
17653 also protected. */
17654 if (r10k_protected_bb_p (bb, protected_bbs))
17655 unprotected_region = NULL_RTX;
17656 else
17657 unprotected_region = pc_rtx;
17658 end = NEXT_INSN (BB_END (bb));
17660 /* UNPROTECTED_REGION is:
17662 - null if we are processing a protected region,
17663 - pc_rtx if we are processing an unprotected region but have
17664 not yet found the first instruction in it
17665 - the first instruction in an unprotected region otherwise. */
17666 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
17668 if (unprotected_region && USEFUL_INSN_P (insn))
17670 if (recog_memoized (insn) == CODE_FOR_mips_cache)
17671 /* This CACHE instruction protects the following code. */
17672 unprotected_region = NULL_RTX;
17673 else
17675 /* See if INSN is the first instruction in this
17676 unprotected region. */
17677 if (unprotected_region == pc_rtx)
17678 unprotected_region = insn;
17680 /* See if INSN needs to be protected. If so,
17681 we must insert a cache barrier somewhere between
17682 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
17683 clear which position is better performance-wise,
17684 but as a tie-breaker, we assume that it is better
17685 to allow delay slots to be back-filled where
17686 possible, and that it is better not to insert
17687 barriers in the middle of already-scheduled code.
17688 We therefore insert the barrier at the beginning
17689 of the region. */
17690 if (r10k_needs_protection_p (insn))
17692 emit_insn_before (gen_r10k_cache_barrier (),
17693 unprotected_region);
17694 unprotected_region = NULL_RTX;
17699 if (CALL_P (insn))
17700 /* The called function is not required to protect the exit path.
17701 The code that follows a call is therefore unprotected. */
17702 unprotected_region = pc_rtx;
17705 /* Record whether the end of this block is protected. */
17706 if (unprotected_region == NULL_RTX)
17707 bitmap_set_bit (protected_bbs, bb->index);
17709 XDELETEVEC (rev_post_order);
17711 sbitmap_free (protected_bbs);
17713 free_dominance_info (CDI_DOMINATORS);
17716 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
17717 otherwise. If INSN has two call rtx, then store the second one in
17718 SECOND_CALL. */
17720 static rtx
17721 mips_call_expr_from_insn (rtx_insn *insn, rtx *second_call)
17723 rtx x;
17724 rtx x2;
17726 if (!CALL_P (insn))
17727 return NULL_RTX;
17729 x = PATTERN (insn);
17730 if (GET_CODE (x) == PARALLEL)
17732 /* Calls returning complex values have two CALL rtx. Look for the second
17733 one here, and return it via the SECOND_CALL arg. */
17734 x2 = XVECEXP (x, 0, 1);
17735 if (GET_CODE (x2) == SET)
17736 x2 = XEXP (x2, 1);
17737 if (GET_CODE (x2) == CALL)
17738 *second_call = x2;
17740 x = XVECEXP (x, 0, 0);
17742 if (GET_CODE (x) == SET)
17743 x = XEXP (x, 1);
17744 gcc_assert (GET_CODE (x) == CALL);
17746 return x;
17749 /* REG is set in DEF. See if the definition is one of the ways we load a
17750 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
17751 If it is, return the symbol reference of the function, otherwise return
17752 NULL_RTX.
17754 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
17755 the values of source registers, otherwise treat such registers as
17756 having an unknown value. */
17758 static rtx
17759 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
17761 rtx_insn *def_insn;
17762 rtx set;
17764 if (DF_REF_IS_ARTIFICIAL (def))
17765 return NULL_RTX;
17767 def_insn = DF_REF_INSN (def);
17768 set = single_set (def_insn);
17769 if (set && rtx_equal_p (SET_DEST (set), reg))
17771 rtx note, src, symbol;
17773 /* First see whether the source is a plain symbol. This is used
17774 when calling symbols that are not lazily bound. */
17775 src = SET_SRC (set);
17776 if (GET_CODE (src) == SYMBOL_REF)
17777 return src;
17779 /* Handle %call16 references. */
17780 symbol = mips_strip_unspec_call (src);
17781 if (symbol)
17783 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
17784 return symbol;
17787 /* If we have something more complicated, look for a
17788 REG_EQUAL or REG_EQUIV note. */
17789 note = find_reg_equal_equiv_note (def_insn);
17790 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
17791 return XEXP (note, 0);
17793 /* Follow at most one simple register copy. Such copies are
17794 interesting in cases like:
17796 for (...)
17798 locally_binding_fn (...);
17801 and:
17803 locally_binding_fn (...);
17805 locally_binding_fn (...);
17807 where the load of locally_binding_fn can legitimately be
17808 hoisted or shared. However, we do not expect to see complex
17809 chains of copies, so a full worklist solution to the problem
17810 would probably be overkill. */
17811 if (recurse_p && REG_P (src))
17812 return mips_find_pic_call_symbol (def_insn, src, false);
17815 return NULL_RTX;
17818 /* Find the definition of the use of REG in INSN. See if the definition
17819 is one of the ways we load a register with a symbol address for a
17820 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
17821 of the function, otherwise return NULL_RTX. RECURSE_P is as for
17822 mips_pic_call_symbol_from_set. */
17824 static rtx
17825 mips_find_pic_call_symbol (rtx_insn *insn, rtx reg, bool recurse_p)
17827 df_ref use;
17828 struct df_link *defs;
17829 rtx symbol;
17831 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
17832 if (!use)
17833 return NULL_RTX;
17834 defs = DF_REF_CHAIN (use);
17835 if (!defs)
17836 return NULL_RTX;
17837 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
17838 if (!symbol)
17839 return NULL_RTX;
17841 /* If we have more than one definition, they need to be identical. */
17842 for (defs = defs->next; defs; defs = defs->next)
17844 rtx other;
17846 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
17847 if (!rtx_equal_p (symbol, other))
17848 return NULL_RTX;
17851 return symbol;
17854 /* Replace the args_size operand of the call expression CALL with the
17855 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
17857 static void
17858 mips_annotate_pic_call_expr (rtx call, rtx symbol)
17860 rtx args_size;
17862 args_size = XEXP (call, 1);
17863 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
17864 gen_rtvec (2, args_size, symbol),
17865 UNSPEC_CALL_ATTR);
17868 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
17869 if instead of the arg_size argument it contains the call attributes. If
17870 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
17871 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
17872 -1. */
17874 bool
17875 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
17877 rtx args_size, symbol;
17879 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
17880 return false;
17882 args_size = operands[args_size_opno];
17883 if (GET_CODE (args_size) != UNSPEC)
17884 return false;
17885 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
17887 symbol = XVECEXP (args_size, 0, 1);
17888 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
17890 operands[args_size_opno] = symbol;
17891 return true;
17894 /* Use DF to annotate PIC indirect calls with the function symbol they
17895 dispatch to. */
17897 static void
17898 mips_annotate_pic_calls (void)
17900 basic_block bb;
17901 rtx_insn *insn;
17903 FOR_EACH_BB_FN (bb, cfun)
17904 FOR_BB_INSNS (bb, insn)
17906 rtx call, reg, symbol, second_call;
17908 second_call = 0;
17909 call = mips_call_expr_from_insn (insn, &second_call);
17910 if (!call)
17911 continue;
17912 gcc_assert (MEM_P (XEXP (call, 0)));
17913 reg = XEXP (XEXP (call, 0), 0);
17914 if (!REG_P (reg))
17915 continue;
17917 symbol = mips_find_pic_call_symbol (insn, reg, true);
17918 if (symbol)
17920 mips_annotate_pic_call_expr (call, symbol);
17921 if (second_call)
17922 mips_annotate_pic_call_expr (second_call, symbol);
17927 /* A temporary variable used by note_uses callbacks, etc. */
17928 static rtx_insn *mips_sim_insn;
17930 /* A structure representing the state of the processor pipeline.
17931 Used by the mips_sim_* family of functions. */
17932 struct mips_sim {
17933 /* The maximum number of instructions that can be issued in a cycle.
17934 (Caches mips_issue_rate.) */
17935 unsigned int issue_rate;
17937 /* The current simulation time. */
17938 unsigned int time;
17940 /* How many more instructions can be issued in the current cycle. */
17941 unsigned int insns_left;
17943 /* LAST_SET[X].INSN is the last instruction to set register X.
17944 LAST_SET[X].TIME is the time at which that instruction was issued.
17945 INSN is null if no instruction has yet set register X. */
17946 struct {
17947 rtx_insn *insn;
17948 unsigned int time;
17949 } last_set[FIRST_PSEUDO_REGISTER];
17951 /* The pipeline's current DFA state. */
17952 state_t dfa_state;
17955 /* Reset STATE to the initial simulation state. */
17957 static void
17958 mips_sim_reset (struct mips_sim *state)
17960 curr_state = state->dfa_state;
17962 state->time = 0;
17963 state->insns_left = state->issue_rate;
17964 memset (&state->last_set, 0, sizeof (state->last_set));
17965 state_reset (curr_state);
17967 targetm.sched.init (0, false, 0);
17968 advance_state (curr_state);
17971 /* Initialize STATE before its first use. DFA_STATE points to an
17972 allocated but uninitialized DFA state. */
17974 static void
17975 mips_sim_init (struct mips_sim *state, state_t dfa_state)
17977 if (targetm.sched.init_dfa_pre_cycle_insn)
17978 targetm.sched.init_dfa_pre_cycle_insn ();
17980 if (targetm.sched.init_dfa_post_cycle_insn)
17981 targetm.sched.init_dfa_post_cycle_insn ();
17983 state->issue_rate = mips_issue_rate ();
17984 state->dfa_state = dfa_state;
17985 mips_sim_reset (state);
17988 /* Advance STATE by one clock cycle. */
17990 static void
17991 mips_sim_next_cycle (struct mips_sim *state)
17993 curr_state = state->dfa_state;
17995 state->time++;
17996 state->insns_left = state->issue_rate;
17997 advance_state (curr_state);
18000 /* Advance simulation state STATE until instruction INSN can read
18001 register REG. */
18003 static void
18004 mips_sim_wait_reg (struct mips_sim *state, rtx_insn *insn, rtx reg)
18006 unsigned int regno, end_regno;
18008 end_regno = END_REGNO (reg);
18009 for (regno = REGNO (reg); regno < end_regno; regno++)
18010 if (state->last_set[regno].insn != 0)
18012 unsigned int t;
18014 t = (state->last_set[regno].time
18015 + insn_latency (state->last_set[regno].insn, insn));
18016 while (state->time < t)
18017 mips_sim_next_cycle (state);
18021 /* A note_uses callback. For each register in *X, advance simulation
18022 state DATA until mips_sim_insn can read the register's value. */
18024 static void
18025 mips_sim_wait_regs_1 (rtx *x, void *data)
18027 subrtx_var_iterator::array_type array;
18028 FOR_EACH_SUBRTX_VAR (iter, array, *x, NONCONST)
18029 if (REG_P (*iter))
18030 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *iter);
18033 /* Advance simulation state STATE until all of INSN's register
18034 dependencies are satisfied. */
18036 static void
18037 mips_sim_wait_regs (struct mips_sim *state, rtx_insn *insn)
18039 mips_sim_insn = insn;
18040 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
18043 /* Advance simulation state STATE until the units required by
18044 instruction INSN are available. */
18046 static void
18047 mips_sim_wait_units (struct mips_sim *state, rtx_insn *insn)
18049 state_t tmp_state;
18051 tmp_state = alloca (state_size ());
18052 while (state->insns_left == 0
18053 || (memcpy (tmp_state, state->dfa_state, state_size ()),
18054 state_transition (tmp_state, insn) >= 0))
18055 mips_sim_next_cycle (state);
18058 /* Advance simulation state STATE until INSN is ready to issue. */
18060 static void
18061 mips_sim_wait_insn (struct mips_sim *state, rtx_insn *insn)
18063 mips_sim_wait_regs (state, insn);
18064 mips_sim_wait_units (state, insn);
18067 /* mips_sim_insn has just set X. Update the LAST_SET array
18068 in simulation state DATA. */
18070 static void
18071 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
18073 struct mips_sim *state;
18075 state = (struct mips_sim *) data;
18076 if (REG_P (x))
18078 unsigned int regno, end_regno;
18080 end_regno = END_REGNO (x);
18081 for (regno = REGNO (x); regno < end_regno; regno++)
18083 state->last_set[regno].insn = mips_sim_insn;
18084 state->last_set[regno].time = state->time;
18089 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
18090 can issue immediately (i.e., that mips_sim_wait_insn has already
18091 been called). */
18093 static void
18094 mips_sim_issue_insn (struct mips_sim *state, rtx_insn *insn)
18096 curr_state = state->dfa_state;
18098 state_transition (curr_state, insn);
18099 state->insns_left = targetm.sched.variable_issue (0, false, insn,
18100 state->insns_left);
18102 mips_sim_insn = insn;
18103 note_stores (PATTERN (insn), mips_sim_record_set, state);
18106 /* Simulate issuing a NOP in state STATE. */
18108 static void
18109 mips_sim_issue_nop (struct mips_sim *state)
18111 if (state->insns_left == 0)
18112 mips_sim_next_cycle (state);
18113 state->insns_left--;
18116 /* Update simulation state STATE so that it's ready to accept the instruction
18117 after INSN. INSN should be part of the main rtl chain, not a member of a
18118 SEQUENCE. */
18120 static void
18121 mips_sim_finish_insn (struct mips_sim *state, rtx_insn *insn)
18123 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
18124 if (JUMP_P (insn))
18125 mips_sim_issue_nop (state);
18127 switch (GET_CODE (SEQ_BEGIN (insn)))
18129 case CODE_LABEL:
18130 case CALL_INSN:
18131 /* We can't predict the processor state after a call or label. */
18132 mips_sim_reset (state);
18133 break;
18135 case JUMP_INSN:
18136 /* The delay slots of branch likely instructions are only executed
18137 when the branch is taken. Therefore, if the caller has simulated
18138 the delay slot instruction, STATE does not really reflect the state
18139 of the pipeline for the instruction after the delay slot. Also,
18140 branch likely instructions tend to incur a penalty when not taken,
18141 so there will probably be an extra delay between the branch and
18142 the instruction after the delay slot. */
18143 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
18144 mips_sim_reset (state);
18145 break;
18147 default:
18148 break;
18152 /* Use simulator state STATE to calculate the execution time of
18153 instruction sequence SEQ. */
18155 static unsigned int
18156 mips_seq_time (struct mips_sim *state, rtx_insn *seq)
18158 mips_sim_reset (state);
18159 for (rtx_insn *insn = seq; insn; insn = NEXT_INSN (insn))
18161 mips_sim_wait_insn (state, insn);
18162 mips_sim_issue_insn (state, insn);
18164 return state->time;
18167 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
18168 setting SETTING, using STATE to simulate instruction sequences. */
18170 static unsigned int
18171 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
18173 mips_tuning_info.fast_mult_zero_zero_p = setting;
18174 start_sequence ();
18176 machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
18177 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
18178 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
18180 /* If the target provides mulsidi3_32bit then that's the most likely
18181 consumer of the result. Test for bypasses. */
18182 if (dword_mode == DImode && HAVE_maddsidi4)
18184 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
18185 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
18188 unsigned int time = mips_seq_time (state, get_insns ());
18189 end_sequence ();
18190 return time;
18193 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
18194 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
18195 Prefer MULT -- which is shorter -- in the event of a tie. */
18197 static void
18198 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
18200 if (TARGET_MIPS16 || !ISA_HAS_HILO)
18201 /* No MTLO or MTHI available for MIPS16. Also, when there are no HI or LO
18202 registers then there is no reason to zero them, arbitrarily choose to
18203 say that "MULT $0,$0" would be faster. */
18204 mips_tuning_info.fast_mult_zero_zero_p = true;
18205 else
18207 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
18208 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
18209 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
18213 /* Set up costs based on the current architecture and tuning settings. */
18215 static void
18216 mips_set_tuning_info (void)
18218 if (mips_tuning_info.initialized_p
18219 && mips_tuning_info.arch == mips_arch
18220 && mips_tuning_info.tune == mips_tune
18221 && mips_tuning_info.mips16_p == TARGET_MIPS16)
18222 return;
18224 mips_tuning_info.arch = mips_arch;
18225 mips_tuning_info.tune = mips_tune;
18226 mips_tuning_info.mips16_p = TARGET_MIPS16;
18227 mips_tuning_info.initialized_p = true;
18229 dfa_start ();
18231 struct mips_sim state;
18232 mips_sim_init (&state, alloca (state_size ()));
18234 mips_set_fast_mult_zero_zero_p (&state);
18236 dfa_finish ();
18239 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
18241 static void
18242 mips_expand_to_rtl_hook (void)
18244 /* We need to call this at a point where we can safely create sequences
18245 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
18246 need to call it at a point where the DFA infrastructure is not
18247 already in use, so we can't just call it lazily on demand.
18249 At present, mips_tuning_info is only needed during post-expand
18250 RTL passes such as split_insns, so this hook should be early enough.
18251 We may need to move the call elsewhere if mips_tuning_info starts
18252 to be used for other things (such as rtx_costs, or expanders that
18253 could be called during gimple optimization). */
18254 mips_set_tuning_info ();
18257 /* The VR4130 pipeline issues aligned pairs of instructions together,
18258 but it stalls the second instruction if it depends on the first.
18259 In order to cut down the amount of logic required, this dependence
18260 check is not based on a full instruction decode. Instead, any non-SPECIAL
18261 instruction is assumed to modify the register specified by bits 20-16
18262 (which is usually the "rt" field).
18264 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
18265 input, so we can end up with a false dependence between the branch
18266 and its delay slot. If this situation occurs in instruction INSN,
18267 try to avoid it by swapping rs and rt. */
18269 static void
18270 vr4130_avoid_branch_rt_conflict (rtx_insn *insn)
18272 rtx_insn *first, *second;
18274 first = SEQ_BEGIN (insn);
18275 second = SEQ_END (insn);
18276 if (JUMP_P (first)
18277 && NONJUMP_INSN_P (second)
18278 && GET_CODE (PATTERN (first)) == SET
18279 && GET_CODE (SET_DEST (PATTERN (first))) == PC
18280 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
18282 /* Check for the right kind of condition. */
18283 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
18284 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
18285 && REG_P (XEXP (cond, 0))
18286 && REG_P (XEXP (cond, 1))
18287 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
18288 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
18290 /* SECOND mentions the rt register but not the rs register. */
18291 rtx tmp = XEXP (cond, 0);
18292 XEXP (cond, 0) = XEXP (cond, 1);
18293 XEXP (cond, 1) = tmp;
18298 /* Implement -mvr4130-align. Go through each basic block and simulate the
18299 processor pipeline. If we find that a pair of instructions could execute
18300 in parallel, and the first of those instructions is not 8-byte aligned,
18301 insert a nop to make it aligned. */
18303 static void
18304 vr4130_align_insns (void)
18306 struct mips_sim state;
18307 rtx_insn *insn, *subinsn, *last, *last2, *next;
18308 bool aligned_p;
18310 dfa_start ();
18312 /* LAST is the last instruction before INSN to have a nonzero length.
18313 LAST2 is the last such instruction before LAST. */
18314 last = 0;
18315 last2 = 0;
18317 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
18318 aligned_p = true;
18320 mips_sim_init (&state, alloca (state_size ()));
18321 for (insn = get_insns (); insn != 0; insn = next)
18323 unsigned int length;
18325 next = NEXT_INSN (insn);
18327 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
18328 This isn't really related to the alignment pass, but we do it on
18329 the fly to avoid a separate instruction walk. */
18330 vr4130_avoid_branch_rt_conflict (insn);
18332 length = get_attr_length (insn);
18333 if (length > 0 && USEFUL_INSN_P (insn))
18334 FOR_EACH_SUBINSN (subinsn, insn)
18336 mips_sim_wait_insn (&state, subinsn);
18338 /* If we want this instruction to issue in parallel with the
18339 previous one, make sure that the previous instruction is
18340 aligned. There are several reasons why this isn't worthwhile
18341 when the second instruction is a call:
18343 - Calls are less likely to be performance critical,
18344 - There's a good chance that the delay slot can execute
18345 in parallel with the call.
18346 - The return address would then be unaligned.
18348 In general, if we're going to insert a nop between instructions
18349 X and Y, it's better to insert it immediately after X. That
18350 way, if the nop makes Y aligned, it will also align any labels
18351 between X and Y. */
18352 if (state.insns_left != state.issue_rate
18353 && !CALL_P (subinsn))
18355 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
18357 /* SUBINSN is the first instruction in INSN and INSN is
18358 aligned. We want to align the previous instruction
18359 instead, so insert a nop between LAST2 and LAST.
18361 Note that LAST could be either a single instruction
18362 or a branch with a delay slot. In the latter case,
18363 LAST, like INSN, is already aligned, but the delay
18364 slot must have some extra delay that stops it from
18365 issuing at the same time as the branch. We therefore
18366 insert a nop before the branch in order to align its
18367 delay slot. */
18368 gcc_assert (last2);
18369 emit_insn_after (gen_nop (), last2);
18370 aligned_p = false;
18372 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
18374 /* SUBINSN is the delay slot of INSN, but INSN is
18375 currently unaligned. Insert a nop between
18376 LAST and INSN to align it. */
18377 gcc_assert (last);
18378 emit_insn_after (gen_nop (), last);
18379 aligned_p = true;
18382 mips_sim_issue_insn (&state, subinsn);
18384 mips_sim_finish_insn (&state, insn);
18386 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
18387 length = get_attr_length (insn);
18388 if (length > 0)
18390 /* If the instruction is an asm statement or multi-instruction
18391 mips.md patern, the length is only an estimate. Insert an
18392 8 byte alignment after it so that the following instructions
18393 can be handled correctly. */
18394 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
18395 && (recog_memoized (insn) < 0 || length >= 8))
18397 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
18398 next = NEXT_INSN (next);
18399 mips_sim_next_cycle (&state);
18400 aligned_p = true;
18402 else if (length & 4)
18403 aligned_p = !aligned_p;
18404 last2 = last;
18405 last = insn;
18408 /* See whether INSN is an aligned label. */
18409 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
18410 aligned_p = true;
18412 dfa_finish ();
18415 /* This structure records that the current function has a LO_SUM
18416 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
18417 the largest offset applied to BASE by all such LO_SUMs. */
18418 struct mips_lo_sum_offset {
18419 rtx base;
18420 HOST_WIDE_INT offset;
18423 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
18425 static hashval_t
18426 mips_hash_base (rtx base)
18428 int do_not_record_p;
18430 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
18433 /* Hashtable helpers. */
18435 struct mips_lo_sum_offset_hasher : free_ptr_hash <mips_lo_sum_offset>
18437 typedef rtx_def *compare_type;
18438 static inline hashval_t hash (const mips_lo_sum_offset *);
18439 static inline bool equal (const mips_lo_sum_offset *, const rtx_def *);
18442 /* Hash-table callbacks for mips_lo_sum_offsets. */
18444 inline hashval_t
18445 mips_lo_sum_offset_hasher::hash (const mips_lo_sum_offset *entry)
18447 return mips_hash_base (entry->base);
18450 inline bool
18451 mips_lo_sum_offset_hasher::equal (const mips_lo_sum_offset *entry,
18452 const rtx_def *value)
18454 return rtx_equal_p (entry->base, value);
18457 typedef hash_table<mips_lo_sum_offset_hasher> mips_offset_table;
18459 /* Look up symbolic constant X in HTAB, which is a hash table of
18460 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
18461 paired with a recorded LO_SUM, otherwise record X in the table. */
18463 static bool
18464 mips_lo_sum_offset_lookup (mips_offset_table *htab, rtx x,
18465 enum insert_option option)
18467 rtx base, offset;
18468 mips_lo_sum_offset **slot;
18469 struct mips_lo_sum_offset *entry;
18471 /* Split X into a base and offset. */
18472 split_const (x, &base, &offset);
18473 if (UNSPEC_ADDRESS_P (base))
18474 base = UNSPEC_ADDRESS (base);
18476 /* Look up the base in the hash table. */
18477 slot = htab->find_slot_with_hash (base, mips_hash_base (base), option);
18478 if (slot == NULL)
18479 return false;
18481 entry = (struct mips_lo_sum_offset *) *slot;
18482 if (option == INSERT)
18484 if (entry == NULL)
18486 entry = XNEW (struct mips_lo_sum_offset);
18487 entry->base = base;
18488 entry->offset = INTVAL (offset);
18489 *slot = entry;
18491 else
18493 if (INTVAL (offset) > entry->offset)
18494 entry->offset = INTVAL (offset);
18497 return INTVAL (offset) <= entry->offset;
18500 /* Search X for LO_SUMs and record them in HTAB. */
18502 static void
18503 mips_record_lo_sums (const_rtx x, mips_offset_table *htab)
18505 subrtx_iterator::array_type array;
18506 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
18507 if (GET_CODE (*iter) == LO_SUM)
18508 mips_lo_sum_offset_lookup (htab, XEXP (*iter, 1), INSERT);
18511 /* Return true if INSN is a SET of an orphaned high-part relocation.
18512 HTAB is a hash table of mips_lo_sum_offsets that describes all the
18513 LO_SUMs in the current function. */
18515 static bool
18516 mips_orphaned_high_part_p (mips_offset_table *htab, rtx_insn *insn)
18518 enum mips_symbol_type type;
18519 rtx x, set;
18521 set = single_set (insn);
18522 if (set)
18524 /* Check for %his. */
18525 x = SET_SRC (set);
18526 if (GET_CODE (x) == HIGH
18527 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
18528 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
18530 /* Check for local %gots (and %got_pages, which is redundant but OK). */
18531 if (GET_CODE (x) == UNSPEC
18532 && XINT (x, 1) == UNSPEC_LOAD_GOT
18533 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
18534 SYMBOL_CONTEXT_LEA, &type)
18535 && type == SYMBOL_GOTOFF_PAGE)
18536 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
18538 return false;
18541 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
18542 INSN and a previous instruction, avoid it by inserting nops after
18543 instruction AFTER.
18545 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
18546 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
18547 before using the value of that register. *HILO_DELAY counts the
18548 number of instructions since the last hilo hazard (that is,
18549 the number of instructions since the last MFLO or MFHI).
18551 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
18552 for the next instruction.
18554 LO_REG is an rtx for the LO register, used in dependence checking. */
18556 static void
18557 mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay,
18558 rtx *delayed_reg, rtx lo_reg, bool *fs_delay)
18560 rtx pattern, set;
18561 int nops, ninsns;
18563 pattern = PATTERN (insn);
18565 /* Do not put the whole function in .set noreorder if it contains
18566 an asm statement. We don't know whether there will be hazards
18567 between the asm statement and the gcc-generated code. */
18568 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
18569 cfun->machine->all_noreorder_p = false;
18571 /* Ignore zero-length instructions (barriers and the like). */
18572 ninsns = get_attr_length (insn) / 4;
18573 if (ninsns == 0)
18574 return;
18576 /* Work out how many nops are needed. Note that we only care about
18577 registers that are explicitly mentioned in the instruction's pattern.
18578 It doesn't matter that calls use the argument registers or that they
18579 clobber hi and lo. */
18580 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
18581 nops = 2 - *hilo_delay;
18582 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
18583 nops = 1;
18584 /* If processing a forbidden slot hazard then a NOP is required if the
18585 branch instruction was not in a sequence (as the sequence would
18586 imply it is not actually a compact branch anyway) and the current
18587 insn is not an inline asm, and can't go in a delay slot. */
18588 else if (*fs_delay && get_attr_can_delay (insn) == CAN_DELAY_NO
18589 && GET_CODE (PATTERN (after)) != SEQUENCE
18590 && GET_CODE (pattern) != ASM_INPUT
18591 && asm_noperands (pattern) < 0)
18592 nops = 1;
18593 else
18594 nops = 0;
18596 /* Insert the nops between this instruction and the previous one.
18597 Each new nop takes us further from the last hilo hazard. */
18598 *hilo_delay += nops;
18599 while (nops-- > 0)
18600 emit_insn_after (gen_hazard_nop (), after);
18602 /* Set up the state for the next instruction. */
18603 *hilo_delay += ninsns;
18604 *delayed_reg = 0;
18605 *fs_delay = false;
18606 if (INSN_CODE (insn) >= 0)
18607 switch (get_attr_hazard (insn))
18609 case HAZARD_NONE:
18610 break;
18612 case HAZARD_FORBIDDEN_SLOT:
18613 if (TARGET_CB_MAYBE)
18614 *fs_delay = true;
18615 break;
18617 case HAZARD_HILO:
18618 *hilo_delay = 0;
18619 break;
18621 case HAZARD_DELAY:
18622 set = single_set (insn);
18623 gcc_assert (set);
18624 *delayed_reg = SET_DEST (set);
18625 break;
18629 /* A SEQUENCE is breakable iff the branch inside it has a compact form
18630 and the target has compact branches. */
18632 static bool
18633 mips_breakable_sequence_p (rtx_insn *insn)
18635 return (insn && GET_CODE (PATTERN (insn)) == SEQUENCE
18636 && TARGET_CB_MAYBE
18637 && get_attr_compact_form (SEQ_BEGIN (insn)) != COMPACT_FORM_NEVER);
18640 /* Remove a SEQUENCE and replace it with the delay slot instruction
18641 followed by the branch and return the instruction in the delay slot.
18642 Return the first of the two new instructions.
18643 Subroutine of mips_reorg_process_insns. */
18645 static rtx_insn *
18646 mips_break_sequence (rtx_insn *insn)
18648 rtx_insn *before = PREV_INSN (insn);
18649 rtx_insn *branch = SEQ_BEGIN (insn);
18650 rtx_insn *ds = SEQ_END (insn);
18651 remove_insn (insn);
18652 add_insn_after (ds, before, NULL);
18653 add_insn_after (branch, ds, NULL);
18654 return ds;
18657 /* Go through the instruction stream and insert nops where necessary.
18658 Also delete any high-part relocations whose partnering low parts
18659 are now all dead. See if the whole function can then be put into
18660 .set noreorder and .set nomacro. */
18662 static void
18663 mips_reorg_process_insns (void)
18665 rtx_insn *insn, *last_insn, *subinsn, *next_insn;
18666 rtx lo_reg, delayed_reg;
18667 int hilo_delay;
18668 bool fs_delay;
18670 /* Force all instructions to be split into their final form. */
18671 split_all_insns_noflow ();
18673 /* Recalculate instruction lengths without taking nops into account. */
18674 cfun->machine->ignore_hazard_length_p = true;
18675 shorten_branches (get_insns ());
18677 cfun->machine->all_noreorder_p = true;
18679 /* We don't track MIPS16 PC-relative offsets closely enough to make
18680 a good job of "set .noreorder" code in MIPS16 mode. */
18681 if (TARGET_MIPS16)
18682 cfun->machine->all_noreorder_p = false;
18684 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
18685 if (!TARGET_EXPLICIT_RELOCS)
18686 cfun->machine->all_noreorder_p = false;
18688 /* Profiled functions can't be all noreorder because the profiler
18689 support uses assembler macros. */
18690 if (crtl->profile)
18691 cfun->machine->all_noreorder_p = false;
18693 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
18694 all noreorder because we rely on the assembler to work around some
18695 errata. The R5900 too has several bugs. */
18696 if (TARGET_FIX_VR4120
18697 || TARGET_FIX_RM7000
18698 || TARGET_FIX_24K
18699 || TARGET_MIPS5900)
18700 cfun->machine->all_noreorder_p = false;
18702 /* The same is true for -mfix-vr4130 if we might generate MFLO or
18703 MFHI instructions. Note that we avoid using MFLO and MFHI if
18704 the VR4130 MACC and DMACC instructions are available instead;
18705 see the *mfhilo_{si,di}_macc patterns. */
18706 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
18707 cfun->machine->all_noreorder_p = false;
18709 mips_offset_table htab (37);
18711 /* Make a first pass over the instructions, recording all the LO_SUMs. */
18712 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
18713 FOR_EACH_SUBINSN (subinsn, insn)
18714 if (USEFUL_INSN_P (subinsn))
18716 rtx body = PATTERN (insn);
18717 int noperands = asm_noperands (body);
18718 if (noperands >= 0)
18720 rtx *ops = XALLOCAVEC (rtx, noperands);
18721 bool *used = XALLOCAVEC (bool, noperands);
18722 const char *string = decode_asm_operands (body, ops, NULL, NULL,
18723 NULL, NULL);
18724 get_referenced_operands (string, used, noperands);
18725 for (int i = 0; i < noperands; ++i)
18726 if (used[i])
18727 mips_record_lo_sums (ops[i], &htab);
18729 else
18730 mips_record_lo_sums (PATTERN (subinsn), &htab);
18733 last_insn = 0;
18734 hilo_delay = 2;
18735 delayed_reg = 0;
18736 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
18737 fs_delay = false;
18739 /* Make a second pass over the instructions. Delete orphaned
18740 high-part relocations or turn them into NOPs. Avoid hazards
18741 by inserting NOPs. */
18742 for (insn = get_insns (); insn != 0; insn = next_insn)
18744 next_insn = NEXT_INSN (insn);
18745 if (USEFUL_INSN_P (insn))
18747 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
18749 rtx_insn *next_active = next_active_insn (insn);
18750 /* Undo delay slots to avoid bubbles if the next instruction can
18751 be placed in a forbidden slot or the cost of adding an
18752 explicit NOP in a forbidden slot is OK and if the SEQUENCE is
18753 safely breakable. */
18754 if (TARGET_CB_MAYBE
18755 && mips_breakable_sequence_p (insn)
18756 && INSN_P (SEQ_BEGIN (insn))
18757 && INSN_P (SEQ_END (insn))
18758 && ((next_active
18759 && INSN_P (next_active)
18760 && GET_CODE (PATTERN (next_active)) != SEQUENCE
18761 && get_attr_can_delay (next_active) == CAN_DELAY_YES)
18762 || !optimize_size))
18764 /* To hide a potential pipeline bubble, if we scan backwards
18765 from the current SEQUENCE and find that there is a load
18766 of a value that is used in the CTI and there are no
18767 dependencies between the CTI and instruction in the delay
18768 slot, break the sequence so the load delay is hidden. */
18769 HARD_REG_SET uses;
18770 CLEAR_HARD_REG_SET (uses);
18771 note_uses (&PATTERN (SEQ_BEGIN (insn)), record_hard_reg_uses,
18772 &uses);
18773 HARD_REG_SET delay_sets;
18774 CLEAR_HARD_REG_SET (delay_sets);
18775 note_stores (PATTERN (SEQ_END (insn)), record_hard_reg_sets,
18776 &delay_sets);
18778 rtx_insn *prev = prev_active_insn (insn);
18779 if (prev
18780 && GET_CODE (PATTERN (prev)) == SET
18781 && MEM_P (SET_SRC (PATTERN (prev))))
18783 HARD_REG_SET sets;
18784 CLEAR_HARD_REG_SET (sets);
18785 note_stores (PATTERN (prev), record_hard_reg_sets,
18786 &sets);
18788 /* Re-order if safe. */
18789 if (!hard_reg_set_intersect_p (delay_sets, uses)
18790 && hard_reg_set_intersect_p (uses, sets))
18792 next_insn = mips_break_sequence (insn);
18793 /* Need to process the hazards of the newly
18794 introduced instructions. */
18795 continue;
18799 /* If we find an orphaned high-part relocation in a delay
18800 slot then we can convert to a compact branch and get
18801 the orphaned high part deleted. */
18802 if (mips_orphaned_high_part_p (&htab, SEQ_END (insn)))
18804 next_insn = mips_break_sequence (insn);
18805 /* Need to process the hazards of the newly
18806 introduced instructions. */
18807 continue;
18811 /* If we find an orphaned high-part relocation in a delay
18812 slot, it's easier to turn that instruction into a NOP than
18813 to delete it. The delay slot will be a NOP either way. */
18814 FOR_EACH_SUBINSN (subinsn, insn)
18815 if (INSN_P (subinsn))
18817 if (mips_orphaned_high_part_p (&htab, subinsn))
18819 PATTERN (subinsn) = gen_nop ();
18820 INSN_CODE (subinsn) = CODE_FOR_nop;
18822 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
18823 &delayed_reg, lo_reg, &fs_delay);
18825 last_insn = insn;
18827 else
18829 /* INSN is a single instruction. Delete it if it's an
18830 orphaned high-part relocation. */
18831 if (mips_orphaned_high_part_p (&htab, insn))
18832 delete_insn (insn);
18833 /* Also delete cache barriers if the last instruction
18834 was an annulled branch. INSN will not be speculatively
18835 executed. */
18836 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
18837 && last_insn
18838 && JUMP_P (SEQ_BEGIN (last_insn))
18839 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
18840 delete_insn (insn);
18841 else
18843 mips_avoid_hazard (last_insn, insn, &hilo_delay,
18844 &delayed_reg, lo_reg, &fs_delay);
18845 /* When a compact branch introduces a forbidden slot hazard
18846 and the next useful instruction is a SEQUENCE of a jump
18847 and a non-nop instruction in the delay slot, remove the
18848 sequence and replace it with the delay slot instruction
18849 then the jump to clear the forbidden slot hazard. */
18851 if (fs_delay)
18853 /* Search onwards from the current position looking for
18854 a SEQUENCE. We are looking for pipeline hazards here
18855 and do not need to worry about labels or barriers as
18856 the optimization only undoes delay slot filling which
18857 only affects the order of the branch and its delay
18858 slot. */
18859 rtx_insn *next = next_active_insn (insn);
18860 if (next
18861 && USEFUL_INSN_P (next)
18862 && GET_CODE (PATTERN (next)) == SEQUENCE
18863 && mips_breakable_sequence_p (next))
18865 last_insn = insn;
18866 next_insn = mips_break_sequence (next);
18867 /* Need to process the hazards of the newly
18868 introduced instructions. */
18869 continue;
18872 last_insn = insn;
18879 /* Return true if the function has a long branch instruction. */
18881 static bool
18882 mips_has_long_branch_p (void)
18884 rtx_insn *insn, *subinsn;
18885 int normal_length;
18887 /* We need up-to-date instruction lengths. */
18888 shorten_branches (get_insns ());
18890 /* Look for a branch that is longer than normal. The normal length for
18891 non-MIPS16 branches is 8, because the length includes the delay slot.
18892 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
18893 but they have no delay slot. */
18894 normal_length = (TARGET_MIPS16 ? 4 : 8);
18895 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
18896 FOR_EACH_SUBINSN (subinsn, insn)
18897 if (JUMP_P (subinsn)
18898 && get_attr_length (subinsn) > normal_length
18899 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
18900 return true;
18902 return false;
18905 /* If we are using a GOT, but have not decided to use a global pointer yet,
18906 see whether we need one to implement long branches. Convert the ghost
18907 global-pointer instructions into real ones if so. */
18909 static bool
18910 mips_expand_ghost_gp_insns (void)
18912 /* Quick exit if we already know that we will or won't need a
18913 global pointer. */
18914 if (!TARGET_USE_GOT
18915 || cfun->machine->global_pointer == INVALID_REGNUM
18916 || mips_must_initialize_gp_p ())
18917 return false;
18919 /* Run a full check for long branches. */
18920 if (!mips_has_long_branch_p ())
18921 return false;
18923 /* We've now established that we need $gp. */
18924 cfun->machine->must_initialize_gp_p = true;
18925 split_all_insns_noflow ();
18927 return true;
18930 /* Subroutine of mips_reorg to manage passes that require DF. */
18932 static void
18933 mips_df_reorg (void)
18935 /* Create def-use chains. */
18936 df_set_flags (DF_EQ_NOTES);
18937 df_chain_add_problem (DF_UD_CHAIN);
18938 df_analyze ();
18940 if (TARGET_RELAX_PIC_CALLS)
18941 mips_annotate_pic_calls ();
18943 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
18944 r10k_insert_cache_barriers ();
18946 df_finish_pass (false);
18949 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
18950 called very late in mips_reorg, but the caller is required to run
18951 mips16_lay_out_constants on the result. */
18953 static void
18954 mips16_load_branch_target (rtx dest, rtx src)
18956 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
18958 rtx page, low;
18960 if (mips_cfun_has_cprestore_slot_p ())
18961 mips_emit_move (dest, mips_cprestore_slot (dest, true));
18962 else
18963 mips_emit_move (dest, pic_offset_table_rtx);
18964 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
18965 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
18966 emit_insn (gen_rtx_SET (dest,
18967 PMODE_INSN (gen_unspec_got, (dest, page))));
18968 emit_insn (gen_rtx_SET (dest, gen_rtx_LO_SUM (Pmode, dest, low)));
18970 else
18972 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
18973 mips_emit_move (dest, src);
18977 /* If we're compiling a MIPS16 function, look for and split any long branches.
18978 This must be called after all other instruction modifications in
18979 mips_reorg. */
18981 static void
18982 mips16_split_long_branches (void)
18984 bool something_changed;
18986 if (!TARGET_MIPS16)
18987 return;
18989 /* Loop until the alignments for all targets are sufficient. */
18992 rtx_insn *insn;
18993 rtx_jump_insn *jump_insn;
18995 shorten_branches (get_insns ());
18996 something_changed = false;
18997 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
18998 if ((jump_insn = dyn_cast <rtx_jump_insn *> (insn))
18999 && get_attr_length (jump_insn) > 4
19000 && (any_condjump_p (jump_insn) || any_uncondjump_p (jump_insn)))
19002 rtx old_label, temp, saved_temp;
19003 rtx_code_label *new_label;
19004 rtx target;
19005 rtx_insn *jump, *jump_sequence;
19007 start_sequence ();
19009 /* Free up a MIPS16 register by saving it in $1. */
19010 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
19011 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
19012 emit_move_insn (saved_temp, temp);
19014 /* Load the branch target into TEMP. */
19015 old_label = JUMP_LABEL (jump_insn);
19016 target = gen_rtx_LABEL_REF (Pmode, old_label);
19017 mips16_load_branch_target (temp, target);
19019 /* Jump to the target and restore the register's
19020 original value. */
19021 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
19022 (temp, temp, saved_temp)));
19023 JUMP_LABEL (jump) = old_label;
19024 LABEL_NUSES (old_label)++;
19026 /* Rewrite any symbolic references that are supposed to use
19027 a PC-relative constant pool. */
19028 mips16_lay_out_constants (false);
19030 if (simplejump_p (jump_insn))
19031 /* We're going to replace INSN with a longer form. */
19032 new_label = NULL;
19033 else
19035 /* Create a branch-around label for the original
19036 instruction. */
19037 new_label = gen_label_rtx ();
19038 emit_label (new_label);
19041 jump_sequence = get_insns ();
19042 end_sequence ();
19044 emit_insn_after (jump_sequence, jump_insn);
19045 if (new_label)
19046 invert_jump (jump_insn, new_label, false);
19047 else
19048 delete_insn (jump_insn);
19049 something_changed = true;
19052 while (something_changed);
19055 /* Insert a `.insn' assembly pseudo-op after any labels followed by
19056 a MIPS16 constant pool or no insn at all. This is needed so that
19057 targets that have been optimized away are still marked as code
19058 and therefore branches that remained and point to them are known
19059 to retain the ISA mode and as such can be successfully assembled. */
19061 static void
19062 mips_insert_insn_pseudos (void)
19064 bool insn_pseudo_needed = TRUE;
19065 rtx_insn *insn;
19067 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
19068 switch (GET_CODE (insn))
19070 case INSN:
19071 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
19072 && XINT (PATTERN (insn), 1) == UNSPEC_CONSTTABLE)
19074 insn_pseudo_needed = TRUE;
19075 break;
19077 /* Fall through. */
19078 case JUMP_INSN:
19079 case CALL_INSN:
19080 case JUMP_TABLE_DATA:
19081 insn_pseudo_needed = FALSE;
19082 break;
19083 case CODE_LABEL:
19084 if (insn_pseudo_needed)
19086 emit_insn_after (gen_insn_pseudo (), insn);
19087 insn_pseudo_needed = FALSE;
19089 break;
19090 default:
19091 break;
19095 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
19097 static void
19098 mips_reorg (void)
19100 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
19101 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
19102 to date if the CFG is available. */
19103 if (mips_cfg_in_reorg ())
19104 compute_bb_for_insn ();
19105 mips16_lay_out_constants (true);
19106 if (mips_cfg_in_reorg ())
19108 mips_df_reorg ();
19109 free_bb_for_insn ();
19113 /* We use a machine specific pass to do a second machine dependent reorg
19114 pass after delay branch scheduling. */
19116 static unsigned int
19117 mips_machine_reorg2 (void)
19119 mips_reorg_process_insns ();
19120 if (!TARGET_MIPS16
19121 && TARGET_EXPLICIT_RELOCS
19122 && TUNE_MIPS4130
19123 && TARGET_VR4130_ALIGN)
19124 vr4130_align_insns ();
19125 if (mips_expand_ghost_gp_insns ())
19126 /* The expansion could invalidate some of the VR4130 alignment
19127 optimizations, but this should be an extremely rare case anyhow. */
19128 mips_reorg_process_insns ();
19129 mips16_split_long_branches ();
19130 mips_insert_insn_pseudos ();
19131 return 0;
19134 namespace {
19136 const pass_data pass_data_mips_machine_reorg2 =
19138 RTL_PASS, /* type */
19139 "mach2", /* name */
19140 OPTGROUP_NONE, /* optinfo_flags */
19141 TV_MACH_DEP, /* tv_id */
19142 0, /* properties_required */
19143 0, /* properties_provided */
19144 0, /* properties_destroyed */
19145 0, /* todo_flags_start */
19146 0, /* todo_flags_finish */
19149 class pass_mips_machine_reorg2 : public rtl_opt_pass
19151 public:
19152 pass_mips_machine_reorg2(gcc::context *ctxt)
19153 : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt)
19156 /* opt_pass methods: */
19157 virtual unsigned int execute (function *) { return mips_machine_reorg2 (); }
19159 }; // class pass_mips_machine_reorg2
19161 } // anon namespace
19163 rtl_opt_pass *
19164 make_pass_mips_machine_reorg2 (gcc::context *ctxt)
19166 return new pass_mips_machine_reorg2 (ctxt);
19170 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
19171 in order to avoid duplicating too much logic from elsewhere. */
19173 static void
19174 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
19175 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
19176 tree function)
19178 rtx this_rtx, temp1, temp2, fnaddr;
19179 rtx_insn *insn;
19180 bool use_sibcall_p;
19182 /* Pretend to be a post-reload pass while generating rtl. */
19183 reload_completed = 1;
19185 /* Mark the end of the (empty) prologue. */
19186 emit_note (NOTE_INSN_PROLOGUE_END);
19188 /* Determine if we can use a sibcall to call FUNCTION directly. */
19189 fnaddr = XEXP (DECL_RTL (function), 0);
19190 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
19191 && const_call_insn_operand (fnaddr, Pmode));
19193 /* Determine if we need to load FNADDR from the GOT. */
19194 if (!use_sibcall_p
19195 && (mips_got_symbol_type_p
19196 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
19198 /* Pick a global pointer. Use a call-clobbered register if
19199 TARGET_CALL_SAVED_GP. */
19200 cfun->machine->global_pointer
19201 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
19202 cfun->machine->must_initialize_gp_p = true;
19203 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
19205 /* Set up the global pointer for n32 or n64 abicalls. */
19206 mips_emit_loadgp ();
19209 /* We need two temporary registers in some cases. */
19210 temp1 = gen_rtx_REG (Pmode, 2);
19211 temp2 = gen_rtx_REG (Pmode, 3);
19213 /* Find out which register contains the "this" pointer. */
19214 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
19215 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
19216 else
19217 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
19219 /* Add DELTA to THIS_RTX. */
19220 if (delta != 0)
19222 rtx offset = GEN_INT (delta);
19223 if (!SMALL_OPERAND (delta))
19225 mips_emit_move (temp1, offset);
19226 offset = temp1;
19228 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
19231 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
19232 if (vcall_offset != 0)
19234 rtx addr;
19236 /* Set TEMP1 to *THIS_RTX. */
19237 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
19239 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
19240 addr = mips_add_offset (temp2, temp1, vcall_offset);
19242 /* Load the offset and add it to THIS_RTX. */
19243 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
19244 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
19247 /* Jump to the target function. Use a sibcall if direct jumps are
19248 allowed, otherwise load the address into a register first. */
19249 if (use_sibcall_p)
19251 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
19252 SIBLING_CALL_P (insn) = 1;
19254 else
19256 /* This is messy. GAS treats "la $25,foo" as part of a call
19257 sequence and may allow a global "foo" to be lazily bound.
19258 The general move patterns therefore reject this combination.
19260 In this context, lazy binding would actually be OK
19261 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
19262 TARGET_CALL_SAVED_GP; see mips_load_call_address.
19263 We must therefore load the address via a temporary
19264 register if mips_dangerous_for_la25_p.
19266 If we jump to the temporary register rather than $25,
19267 the assembler can use the move insn to fill the jump's
19268 delay slot.
19270 We can use the same technique for MIPS16 code, where $25
19271 is not a valid JR register. */
19272 if (TARGET_USE_PIC_FN_ADDR_REG
19273 && !TARGET_MIPS16
19274 && !mips_dangerous_for_la25_p (fnaddr))
19275 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
19276 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
19278 if (TARGET_USE_PIC_FN_ADDR_REG
19279 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
19280 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
19281 emit_jump_insn (gen_indirect_jump (temp1));
19284 /* Run just enough of rest_of_compilation. This sequence was
19285 "borrowed" from alpha.c. */
19286 insn = get_insns ();
19287 split_all_insns_noflow ();
19288 mips16_lay_out_constants (true);
19289 shorten_branches (insn);
19290 final_start_function (insn, file, 1);
19291 final (insn, file, 1);
19292 final_end_function ();
19294 /* Clean up the vars set above. Note that final_end_function resets
19295 the global pointer for us. */
19296 reload_completed = 0;
19300 /* The last argument passed to mips_set_compression_mode,
19301 or negative if the function hasn't been called yet. */
19302 static unsigned int old_compression_mode = -1;
19304 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
19305 which is either MASK_MIPS16 or MASK_MICROMIPS. */
19307 static void
19308 mips_set_compression_mode (unsigned int compression_mode)
19311 if (compression_mode == old_compression_mode)
19312 return;
19314 /* Restore base settings of various flags. */
19315 target_flags = mips_base_target_flags;
19316 flag_schedule_insns = mips_base_schedule_insns;
19317 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
19318 flag_move_loop_invariants = mips_base_move_loop_invariants;
19319 align_loops = mips_base_align_loops;
19320 align_jumps = mips_base_align_jumps;
19321 align_functions = mips_base_align_functions;
19322 target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS);
19323 target_flags |= compression_mode;
19325 if (compression_mode & MASK_MIPS16)
19327 /* Switch to MIPS16 mode. */
19328 target_flags |= MASK_MIPS16;
19330 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
19331 target_flags &= ~MASK_SYNCI;
19333 /* Don't run the scheduler before reload, since it tends to
19334 increase register pressure. */
19335 flag_schedule_insns = 0;
19337 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
19338 the whole function to be in a single section. */
19339 flag_reorder_blocks_and_partition = 0;
19341 /* Don't move loop invariants, because it tends to increase
19342 register pressure. It also introduces an extra move in cases
19343 where the constant is the first operand in a two-operand binary
19344 instruction, or when it forms a register argument to a functon
19345 call. */
19346 flag_move_loop_invariants = 0;
19348 target_flags |= MASK_EXPLICIT_RELOCS;
19350 /* Experiments suggest we get the best overall section-anchor
19351 results from using the range of an unextended LW or SW. Code
19352 that makes heavy use of byte or short accesses can do better
19353 with ranges of 0...31 and 0...63 respectively, but most code is
19354 sensitive to the range of LW and SW instead. */
19355 targetm.min_anchor_offset = 0;
19356 targetm.max_anchor_offset = 127;
19358 targetm.const_anchor = 0;
19360 /* MIPS16 has no BAL instruction. */
19361 target_flags &= ~MASK_RELAX_PIC_CALLS;
19363 /* The R4000 errata don't apply to any known MIPS16 cores.
19364 It's simpler to make the R4000 fixes and MIPS16 mode
19365 mutually exclusive. */
19366 target_flags &= ~MASK_FIX_R4000;
19368 if (flag_pic && !TARGET_OLDABI)
19369 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
19371 if (TARGET_XGOT)
19372 sorry ("MIPS16 -mxgot code");
19374 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
19375 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
19377 if (TARGET_MSA)
19378 sorry ("MSA MIPS16 code");
19380 else
19382 /* Switch to microMIPS or the standard encoding. */
19384 if (TARGET_MICROMIPS)
19385 /* Avoid branch likely. */
19386 target_flags &= ~MASK_BRANCHLIKELY;
19388 /* Provide default values for align_* for 64-bit targets. */
19389 if (TARGET_64BIT)
19391 if (align_loops == 0)
19392 align_loops = 8;
19393 if (align_jumps == 0)
19394 align_jumps = 8;
19395 if (align_functions == 0)
19396 align_functions = 8;
19399 targetm.min_anchor_offset = -32768;
19400 targetm.max_anchor_offset = 32767;
19402 targetm.const_anchor = 0x8000;
19405 /* (Re)initialize MIPS target internals for new ISA. */
19406 mips_init_relocs ();
19408 if (compression_mode & MASK_MIPS16)
19410 if (!mips16_globals)
19411 mips16_globals = save_target_globals_default_opts ();
19412 else
19413 restore_target_globals (mips16_globals);
19415 else if (compression_mode & MASK_MICROMIPS)
19417 if (!micromips_globals)
19418 micromips_globals = save_target_globals_default_opts ();
19419 else
19420 restore_target_globals (micromips_globals);
19422 else
19423 restore_target_globals (&default_target_globals);
19425 old_compression_mode = compression_mode;
19428 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
19429 function should use the MIPS16 or microMIPS ISA and switch modes
19430 accordingly. */
19432 static void
19433 mips_set_current_function (tree fndecl)
19435 mips_set_compression_mode (mips_get_compress_mode (fndecl));
19438 /* Allocate a chunk of memory for per-function machine-dependent data. */
19440 static struct machine_function *
19441 mips_init_machine_status (void)
19443 return ggc_cleared_alloc<machine_function> ();
19446 /* Return the processor associated with the given ISA level, or null
19447 if the ISA isn't valid. */
19449 static const struct mips_cpu_info *
19450 mips_cpu_info_from_isa (int isa)
19452 unsigned int i;
19454 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
19455 if (mips_cpu_info_table[i].isa == isa)
19456 return mips_cpu_info_table + i;
19458 return NULL;
19461 /* Return a mips_cpu_info entry determined by an option valued
19462 OPT. */
19464 static const struct mips_cpu_info *
19465 mips_cpu_info_from_opt (int opt)
19467 switch (opt)
19469 case MIPS_ARCH_OPTION_FROM_ABI:
19470 /* 'from-abi' selects the most compatible architecture for the
19471 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
19472 ABIs. For the EABIs, we have to decide whether we're using
19473 the 32-bit or 64-bit version. */
19474 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
19475 : ABI_NEEDS_64BIT_REGS ? 3
19476 : (TARGET_64BIT ? 3 : 1));
19478 case MIPS_ARCH_OPTION_NATIVE:
19479 gcc_unreachable ();
19481 default:
19482 return &mips_cpu_info_table[opt];
19486 /* Return a default mips_cpu_info entry, given that no -march= option
19487 was explicitly specified. */
19489 static const struct mips_cpu_info *
19490 mips_default_arch (void)
19492 #if defined (MIPS_CPU_STRING_DEFAULT)
19493 unsigned int i;
19494 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
19495 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
19496 return mips_cpu_info_table + i;
19497 gcc_unreachable ();
19498 #elif defined (MIPS_ISA_DEFAULT)
19499 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
19500 #else
19501 /* 'from-abi' makes a good default: you get whatever the ABI
19502 requires. */
19503 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
19504 #endif
19507 /* Set up globals to generate code for the ISA or processor
19508 described by INFO. */
19510 static void
19511 mips_set_architecture (const struct mips_cpu_info *info)
19513 if (info != 0)
19515 mips_arch_info = info;
19516 mips_arch = info->cpu;
19517 mips_isa = info->isa;
19518 if (mips_isa < 32)
19519 mips_isa_rev = 0;
19520 else
19521 mips_isa_rev = (mips_isa & 31) + 1;
19525 /* Likewise for tuning. */
19527 static void
19528 mips_set_tune (const struct mips_cpu_info *info)
19530 if (info != 0)
19532 mips_tune_info = info;
19533 mips_tune = info->cpu;
19537 /* Implement TARGET_OPTION_OVERRIDE. */
19539 static void
19540 mips_option_override (void)
19542 int i, start, regno, mode;
19544 if (global_options_set.x_mips_isa_option)
19545 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
19547 #ifdef SUBTARGET_OVERRIDE_OPTIONS
19548 SUBTARGET_OVERRIDE_OPTIONS;
19549 #endif
19551 /* MIPS16 and microMIPS cannot coexist. */
19552 if (TARGET_MICROMIPS && TARGET_MIPS16)
19553 error ("unsupported combination: %s", "-mips16 -mmicromips");
19555 /* Prohibit Paired-Single and MSA combination. This is software restriction
19556 rather than architectural. */
19557 if (ISA_HAS_MSA && TARGET_PAIRED_SINGLE_FLOAT)
19558 error ("unsupported combination: %s", "-mmsa -mpaired-single");
19560 /* Save the base compression state and process flags as though we
19561 were generating uncompressed code. */
19562 mips_base_compression_flags = TARGET_COMPRESSION;
19563 target_flags &= ~TARGET_COMPRESSION;
19565 /* -mno-float overrides -mhard-float and -msoft-float. */
19566 if (TARGET_NO_FLOAT)
19568 target_flags |= MASK_SOFT_FLOAT_ABI;
19569 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
19572 if (TARGET_FLIP_MIPS16)
19573 TARGET_INTERLINK_COMPRESSED = 1;
19575 /* Set the small data limit. */
19576 mips_small_data_threshold = (global_options_set.x_g_switch_value
19577 ? g_switch_value
19578 : MIPS_DEFAULT_GVALUE);
19580 /* The following code determines the architecture and register size.
19581 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
19582 The GAS and GCC code should be kept in sync as much as possible. */
19584 if (global_options_set.x_mips_arch_option)
19585 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
19587 if (mips_isa_option_info != 0)
19589 if (mips_arch_info == 0)
19590 mips_set_architecture (mips_isa_option_info);
19591 else if (mips_arch_info->isa != mips_isa_option_info->isa)
19592 error ("%<-%s%> conflicts with the other architecture options, "
19593 "which specify a %s processor",
19594 mips_isa_option_info->name,
19595 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
19598 if (mips_arch_info == 0)
19599 mips_set_architecture (mips_default_arch ());
19601 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
19602 error ("%<-march=%s%> is not compatible with the selected ABI",
19603 mips_arch_info->name);
19605 /* Optimize for mips_arch, unless -mtune selects a different processor. */
19606 if (global_options_set.x_mips_tune_option)
19607 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
19609 if (mips_tune_info == 0)
19610 mips_set_tune (mips_arch_info);
19612 if ((target_flags_explicit & MASK_64BIT) != 0)
19614 /* The user specified the size of the integer registers. Make sure
19615 it agrees with the ABI and ISA. */
19616 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
19617 error ("%<-mgp64%> used with a 32-bit processor");
19618 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
19619 error ("%<-mgp32%> used with a 64-bit ABI");
19620 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
19621 error ("%<-mgp64%> used with a 32-bit ABI");
19623 else
19625 /* Infer the integer register size from the ABI and processor.
19626 Restrict ourselves to 32-bit registers if that's all the
19627 processor has, or if the ABI cannot handle 64-bit registers. */
19628 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
19629 target_flags &= ~MASK_64BIT;
19630 else
19631 target_flags |= MASK_64BIT;
19634 if ((target_flags_explicit & MASK_FLOAT64) != 0)
19636 if (mips_isa_rev >= 6 && !TARGET_FLOAT64)
19637 error ("the %qs architecture does not support %<-mfp32%>",
19638 mips_arch_info->name);
19639 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
19640 error ("unsupported combination: %s", "-mfp64 -msingle-float");
19641 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
19642 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
19643 else if (!TARGET_64BIT && TARGET_FLOAT64)
19645 if (!ISA_HAS_MXHC1)
19646 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
19647 " the target supports the mfhc1 and mthc1 instructions");
19648 else if (mips_abi != ABI_32)
19649 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
19650 " the o32 ABI");
19653 else
19655 /* -msingle-float selects 32-bit float registers. On r6 and later,
19656 -mdouble-float selects 64-bit float registers, since the old paired
19657 register model is not supported. In other cases the float registers
19658 should be the same size as the integer ones. */
19659 if (mips_isa_rev >= 6 && TARGET_DOUBLE_FLOAT && !TARGET_FLOATXX)
19660 target_flags |= MASK_FLOAT64;
19661 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
19662 target_flags |= MASK_FLOAT64;
19663 else if (mips_abi == ABI_32 && ISA_HAS_MSA && !TARGET_FLOATXX)
19664 target_flags |= MASK_FLOAT64;
19665 else
19666 target_flags &= ~MASK_FLOAT64;
19669 if (mips_abi != ABI_32 && TARGET_FLOATXX)
19670 error ("%<-mfpxx%> can only be used with the o32 ABI");
19671 else if (TARGET_FLOAT64 && TARGET_FLOATXX)
19672 error ("unsupported combination: %s", "-mfp64 -mfpxx");
19673 else if (ISA_MIPS1 && !TARGET_FLOAT32)
19674 error ("%<-march=%s%> requires %<-mfp32%>", mips_arch_info->name);
19675 else if (TARGET_FLOATXX && !mips_lra_flag)
19676 error ("%<-mfpxx%> requires %<-mlra%>");
19678 /* End of code shared with GAS. */
19680 /* The R5900 FPU only supports single precision. */
19681 if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
19682 error ("unsupported combination: %s",
19683 "-march=r5900 -mhard-float -mdouble-float");
19685 /* If a -mlong* option was given, check that it matches the ABI,
19686 otherwise infer the -mlong* setting from the other options. */
19687 if ((target_flags_explicit & MASK_LONG64) != 0)
19689 if (TARGET_LONG64)
19691 if (mips_abi == ABI_N32)
19692 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
19693 else if (mips_abi == ABI_32)
19694 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
19695 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
19696 /* We have traditionally allowed non-abicalls code to use
19697 an LP64 form of o64. However, it would take a bit more
19698 effort to support the combination of 32-bit GOT entries
19699 and 64-bit pointers, so we treat the abicalls case as
19700 an error. */
19701 error ("the combination of %qs and %qs is incompatible with %qs",
19702 "-mabi=o64", "-mabicalls", "-mlong64");
19704 else
19706 if (mips_abi == ABI_64)
19707 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
19710 else
19712 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
19713 target_flags |= MASK_LONG64;
19714 else
19715 target_flags &= ~MASK_LONG64;
19718 if (!TARGET_OLDABI)
19719 flag_pcc_struct_return = 0;
19721 /* Decide which rtx_costs structure to use. */
19722 if (optimize_size)
19723 mips_cost = &mips_rtx_cost_optimize_size;
19724 else
19725 mips_cost = &mips_rtx_cost_data[mips_tune];
19727 /* If the user hasn't specified a branch cost, use the processor's
19728 default. */
19729 if (mips_branch_cost == 0)
19730 mips_branch_cost = mips_cost->branch_cost;
19732 /* If neither -mbranch-likely nor -mno-branch-likely was given
19733 on the command line, set MASK_BRANCHLIKELY based on the target
19734 architecture and tuning flags. Annulled delay slots are a
19735 size win, so we only consider the processor-specific tuning
19736 for !optimize_size. */
19737 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
19739 if (ISA_HAS_BRANCHLIKELY
19740 && ((optimize_size
19741 && (mips_tune_info->tune_flags
19742 & PTF_AVOID_BRANCHLIKELY_SIZE) == 0)
19743 || (!optimize_size
19744 && optimize > 0
19745 && (mips_tune_info->tune_flags
19746 & PTF_AVOID_BRANCHLIKELY_SPEED) == 0)
19747 || (mips_tune_info->tune_flags
19748 & PTF_AVOID_BRANCHLIKELY_ALWAYS) == 0))
19749 target_flags |= MASK_BRANCHLIKELY;
19750 else
19751 target_flags &= ~MASK_BRANCHLIKELY;
19753 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
19754 warning (0, "the %qs architecture does not support branch-likely"
19755 " instructions", mips_arch_info->name);
19757 /* If the user hasn't specified -mimadd or -mno-imadd set
19758 MASK_IMADD based on the target architecture and tuning
19759 flags. */
19760 if ((target_flags_explicit & MASK_IMADD) == 0)
19762 if (ISA_HAS_MADD_MSUB &&
19763 (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
19764 target_flags |= MASK_IMADD;
19765 else
19766 target_flags &= ~MASK_IMADD;
19768 else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
19769 warning (0, "the %qs architecture does not support madd or msub"
19770 " instructions", mips_arch_info->name);
19772 /* If neither -modd-spreg nor -mno-odd-spreg was given on the command
19773 line, set MASK_ODD_SPREG based on the ISA and ABI. */
19774 if ((target_flags_explicit & MASK_ODD_SPREG) == 0)
19776 /* Disable TARGET_ODD_SPREG when using the o32 FPXX ABI. */
19777 if (!ISA_HAS_ODD_SPREG || TARGET_FLOATXX)
19778 target_flags &= ~MASK_ODD_SPREG;
19779 else
19780 target_flags |= MASK_ODD_SPREG;
19782 else if (TARGET_ODD_SPREG && !ISA_HAS_ODD_SPREG)
19783 warning (0, "the %qs architecture does not support odd single-precision"
19784 " registers", mips_arch_info->name);
19786 if (!TARGET_ODD_SPREG && TARGET_64BIT)
19788 error ("unsupported combination: %s", "-mgp64 -mno-odd-spreg");
19789 /* Allow compilation to continue further even though invalid output
19790 will be produced. */
19791 target_flags |= MASK_ODD_SPREG;
19794 if (!ISA_HAS_COMPACT_BRANCHES && mips_cb == MIPS_CB_ALWAYS)
19796 error ("unsupported combination: %qs%s %s",
19797 mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
19798 "-mcompact-branches=always");
19800 else if (!ISA_HAS_DELAY_SLOTS && mips_cb == MIPS_CB_NEVER)
19802 error ("unsupported combination: %qs%s %s",
19803 mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
19804 "-mcompact-branches=never");
19807 /* Require explicit relocs for MIPS R6 onwards. This enables simplification
19808 of the compact branch and jump support through the backend. */
19809 if (!TARGET_EXPLICIT_RELOCS && mips_isa_rev >= 6)
19811 error ("unsupported combination: %qs %s",
19812 mips_arch_info->name, "-mno-explicit-relocs");
19815 /* The effect of -mabicalls isn't defined for the EABI. */
19816 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
19818 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
19819 target_flags &= ~MASK_ABICALLS;
19822 /* PIC requires -mabicalls. */
19823 if (flag_pic)
19825 if (mips_abi == ABI_EABI)
19826 error ("cannot generate position-independent code for %qs",
19827 "-mabi=eabi");
19828 else if (!TARGET_ABICALLS)
19829 error ("position-independent code requires %qs", "-mabicalls");
19832 if (TARGET_ABICALLS_PIC2)
19833 /* We need to set flag_pic for executables as well as DSOs
19834 because we may reference symbols that are not defined in
19835 the final executable. (MIPS does not use things like
19836 copy relocs, for example.)
19838 There is a body of code that uses __PIC__ to distinguish
19839 between -mabicalls and -mno-abicalls code. The non-__PIC__
19840 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
19841 long as any indirect jumps use $25. */
19842 flag_pic = 1;
19844 /* -mvr4130-align is a "speed over size" optimization: it usually produces
19845 faster code, but at the expense of more nops. Enable it at -O3 and
19846 above. */
19847 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
19848 target_flags |= MASK_VR4130_ALIGN;
19850 /* Prefer a call to memcpy over inline code when optimizing for size,
19851 though see MOVE_RATIO in mips.h. */
19852 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
19853 target_flags |= MASK_MEMCPY;
19855 /* If we have a nonzero small-data limit, check that the -mgpopt
19856 setting is consistent with the other target flags. */
19857 if (mips_small_data_threshold > 0)
19859 if (!TARGET_GPOPT)
19861 if (!TARGET_EXPLICIT_RELOCS)
19862 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
19864 TARGET_LOCAL_SDATA = false;
19865 TARGET_EXTERN_SDATA = false;
19867 else
19869 if (TARGET_VXWORKS_RTP)
19870 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
19872 if (TARGET_ABICALLS)
19873 warning (0, "cannot use small-data accesses for %qs",
19874 "-mabicalls");
19878 /* Set NaN and ABS defaults. */
19879 if (mips_nan == MIPS_IEEE_754_DEFAULT && !ISA_HAS_IEEE_754_LEGACY)
19880 mips_nan = MIPS_IEEE_754_2008;
19881 if (mips_abs == MIPS_IEEE_754_DEFAULT && !ISA_HAS_IEEE_754_LEGACY)
19882 mips_abs = MIPS_IEEE_754_2008;
19884 /* Check for IEEE 754 legacy/2008 support. */
19885 if ((mips_nan == MIPS_IEEE_754_LEGACY
19886 || mips_abs == MIPS_IEEE_754_LEGACY)
19887 && !ISA_HAS_IEEE_754_LEGACY)
19888 warning (0, "the %qs architecture does not support %<-m%s=legacy%>",
19889 mips_arch_info->name,
19890 mips_nan == MIPS_IEEE_754_LEGACY ? "nan" : "abs");
19892 if ((mips_nan == MIPS_IEEE_754_2008
19893 || mips_abs == MIPS_IEEE_754_2008)
19894 && !ISA_HAS_IEEE_754_2008)
19895 warning (0, "the %qs architecture does not support %<-m%s=2008%>",
19896 mips_arch_info->name,
19897 mips_nan == MIPS_IEEE_754_2008 ? "nan" : "abs");
19899 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
19900 for all its floating point. */
19901 if (mips_nan != MIPS_IEEE_754_2008)
19903 REAL_MODE_FORMAT (SFmode) = &mips_single_format;
19904 REAL_MODE_FORMAT (DFmode) = &mips_double_format;
19905 REAL_MODE_FORMAT (TFmode) = &mips_quad_format;
19908 /* Make sure that the user didn't turn off paired single support when
19909 MIPS-3D support is requested. */
19910 if (TARGET_MIPS3D
19911 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
19912 && !TARGET_PAIRED_SINGLE_FLOAT)
19913 error ("%<-mips3d%> requires %<-mpaired-single%>");
19915 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
19916 if (TARGET_MIPS3D)
19917 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
19919 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
19920 and TARGET_HARD_FLOAT_ABI are both true. */
19921 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
19923 error ("%qs must be used with %qs",
19924 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
19925 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
19926 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
19927 TARGET_MIPS3D = 0;
19930 /* Make sure that when ISA_HAS_MSA is true, TARGET_FLOAT64 and
19931 TARGET_HARD_FLOAT_ABI and both true. */
19932 if (ISA_HAS_MSA && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
19933 error ("%<-mmsa%> must be used with %<-mfp64%> and %<-mhard-float%>");
19935 /* Make sure that -mpaired-single is only used on ISAs that support it.
19936 We must disable it otherwise since it relies on other ISA properties
19937 like ISA_HAS_8CC having their normal values. */
19938 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
19940 error ("the %qs architecture does not support paired-single"
19941 " instructions", mips_arch_info->name);
19942 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
19943 TARGET_MIPS3D = 0;
19946 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
19947 && !TARGET_CACHE_BUILTIN)
19949 error ("%qs requires a target that provides the %qs instruction",
19950 "-mr10k-cache-barrier", "cache");
19951 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
19954 /* If TARGET_DSPR2, enable TARGET_DSP. */
19955 if (TARGET_DSPR2)
19956 TARGET_DSP = true;
19958 if (TARGET_DSP && mips_isa_rev >= 6)
19960 error ("the %qs architecture does not support DSP instructions",
19961 mips_arch_info->name);
19962 TARGET_DSP = false;
19963 TARGET_DSPR2 = false;
19966 /* .eh_frame addresses should be the same width as a C pointer.
19967 Most MIPS ABIs support only one pointer size, so the assembler
19968 will usually know exactly how big an .eh_frame address is.
19970 Unfortunately, this is not true of the 64-bit EABI. The ABI was
19971 originally defined to use 64-bit pointers (i.e. it is LP64), and
19972 this is still the default mode. However, we also support an n32-like
19973 ILP32 mode, which is selected by -mlong32. The problem is that the
19974 assembler has traditionally not had an -mlong option, so it has
19975 traditionally not known whether we're using the ILP32 or LP64 form.
19977 As it happens, gas versions up to and including 2.19 use _32-bit_
19978 addresses for EABI64 .cfi_* directives. This is wrong for the
19979 default LP64 mode, so we can't use the directives by default.
19980 Moreover, since gas's current behavior is at odds with gcc's
19981 default behavior, it seems unwise to rely on future versions
19982 of gas behaving the same way. We therefore avoid using .cfi
19983 directives for -mlong32 as well. */
19984 if (mips_abi == ABI_EABI && TARGET_64BIT)
19985 flag_dwarf2_cfi_asm = 0;
19987 /* .cfi_* directives generate a read-only section, so fall back on
19988 manual .eh_frame creation if we need the section to be writable. */
19989 if (TARGET_WRITABLE_EH_FRAME)
19990 flag_dwarf2_cfi_asm = 0;
19992 mips_init_print_operand_punct ();
19994 /* Set up array to map GCC register number to debug register number.
19995 Ignore the special purpose register numbers. */
19997 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
19999 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
20000 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
20001 mips_dwarf_regno[i] = i;
20002 else
20003 mips_dwarf_regno[i] = INVALID_REGNUM;
20006 start = GP_DBX_FIRST - GP_REG_FIRST;
20007 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
20008 mips_dbx_regno[i] = i + start;
20010 start = FP_DBX_FIRST - FP_REG_FIRST;
20011 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
20012 mips_dbx_regno[i] = i + start;
20014 /* Accumulator debug registers use big-endian ordering. */
20015 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
20016 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
20017 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
20018 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
20019 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
20021 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
20022 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
20025 /* Set up mips_hard_regno_mode_ok. */
20026 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
20027 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
20028 mips_hard_regno_mode_ok[mode][regno]
20029 = mips_hard_regno_mode_ok_p (regno, (machine_mode) mode);
20031 /* Function to allocate machine-dependent function status. */
20032 init_machine_status = &mips_init_machine_status;
20034 /* Default to working around R4000 errata only if the processor
20035 was selected explicitly. */
20036 if ((target_flags_explicit & MASK_FIX_R4000) == 0
20037 && strcmp (mips_arch_info->name, "r4000") == 0)
20038 target_flags |= MASK_FIX_R4000;
20040 /* Default to working around R4400 errata only if the processor
20041 was selected explicitly. */
20042 if ((target_flags_explicit & MASK_FIX_R4400) == 0
20043 && strcmp (mips_arch_info->name, "r4400") == 0)
20044 target_flags |= MASK_FIX_R4400;
20046 /* Default to working around R10000 errata only if the processor
20047 was selected explicitly. */
20048 if ((target_flags_explicit & MASK_FIX_R10000) == 0
20049 && strcmp (mips_arch_info->name, "r10000") == 0)
20050 target_flags |= MASK_FIX_R10000;
20052 /* Make sure that branch-likely instructions available when using
20053 -mfix-r10000. The instructions are not available if either:
20055 1. -mno-branch-likely was passed.
20056 2. The selected ISA does not support branch-likely and
20057 the command line does not include -mbranch-likely. */
20058 if (TARGET_FIX_R10000
20059 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
20060 ? !ISA_HAS_BRANCHLIKELY
20061 : !TARGET_BRANCHLIKELY))
20062 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
20064 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
20066 warning (0, "the %qs architecture does not support the synci "
20067 "instruction", mips_arch_info->name);
20068 target_flags &= ~MASK_SYNCI;
20071 /* Only optimize PIC indirect calls if they are actually required. */
20072 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
20073 target_flags &= ~MASK_RELAX_PIC_CALLS;
20075 /* Save base state of options. */
20076 mips_base_target_flags = target_flags;
20077 mips_base_schedule_insns = flag_schedule_insns;
20078 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
20079 mips_base_move_loop_invariants = flag_move_loop_invariants;
20080 mips_base_align_loops = align_loops;
20081 mips_base_align_jumps = align_jumps;
20082 mips_base_align_functions = align_functions;
20084 /* Now select the ISA mode.
20086 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
20087 later if required. */
20088 mips_set_compression_mode (0);
20090 /* We register a second machine specific reorg pass after delay slot
20091 filling. Registering the pass must be done at start up. It's
20092 convenient to do it here. */
20093 opt_pass *new_pass = make_pass_mips_machine_reorg2 (g);
20094 struct register_pass_info insert_pass_mips_machine_reorg2 =
20096 new_pass, /* pass */
20097 "dbr", /* reference_pass_name */
20098 1, /* ref_pass_instance_number */
20099 PASS_POS_INSERT_AFTER /* po_op */
20101 register_pass (&insert_pass_mips_machine_reorg2);
20103 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
20104 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
20106 mips_register_frame_header_opt ();
20109 /* Swap the register information for registers I and I + 1, which
20110 currently have the wrong endianness. Note that the registers'
20111 fixedness and call-clobberedness might have been set on the
20112 command line. */
20114 static void
20115 mips_swap_registers (unsigned int i)
20117 int tmpi;
20118 const char *tmps;
20120 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
20121 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
20123 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
20124 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
20125 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
20126 SWAP_STRING (reg_names[i], reg_names[i + 1]);
20128 #undef SWAP_STRING
20129 #undef SWAP_INT
20132 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
20134 static void
20135 mips_conditional_register_usage (void)
20138 if (ISA_HAS_DSP)
20140 /* These DSP control register fields are global. */
20141 global_regs[CCDSP_PO_REGNUM] = 1;
20142 global_regs[CCDSP_SC_REGNUM] = 1;
20144 else
20145 AND_COMPL_HARD_REG_SET (accessible_reg_set,
20146 reg_class_contents[(int) DSP_ACC_REGS]);
20148 if (!ISA_HAS_HILO)
20149 AND_COMPL_HARD_REG_SET (accessible_reg_set,
20150 reg_class_contents[(int) MD_REGS]);
20152 if (!TARGET_HARD_FLOAT)
20154 AND_COMPL_HARD_REG_SET (accessible_reg_set,
20155 reg_class_contents[(int) FP_REGS]);
20156 AND_COMPL_HARD_REG_SET (accessible_reg_set,
20157 reg_class_contents[(int) ST_REGS]);
20159 else if (!ISA_HAS_8CC)
20161 /* We only have a single condition-code register. We implement
20162 this by fixing all the condition-code registers and generating
20163 RTL that refers directly to ST_REG_FIRST. */
20164 AND_COMPL_HARD_REG_SET (accessible_reg_set,
20165 reg_class_contents[(int) ST_REGS]);
20166 if (!ISA_HAS_CCF)
20167 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
20168 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
20170 if (TARGET_MIPS16)
20172 /* In MIPS16 mode, we prohibit the unused $s registers, since they
20173 are call-saved, and saving them via a MIPS16 register would
20174 probably waste more time than just reloading the value.
20176 We permit the $t temporary registers when optimizing for speed
20177 but not when optimizing for space because using them results in
20178 code that is larger (but faster) then not using them. We do
20179 allow $24 (t8) because it is used in CMP and CMPI instructions
20180 and $25 (t9) because it is used as the function call address in
20181 SVR4 PIC code. */
20183 fixed_regs[18] = call_used_regs[18] = 1;
20184 fixed_regs[19] = call_used_regs[19] = 1;
20185 fixed_regs[20] = call_used_regs[20] = 1;
20186 fixed_regs[21] = call_used_regs[21] = 1;
20187 fixed_regs[22] = call_used_regs[22] = 1;
20188 fixed_regs[23] = call_used_regs[23] = 1;
20189 fixed_regs[26] = call_used_regs[26] = 1;
20190 fixed_regs[27] = call_used_regs[27] = 1;
20191 fixed_regs[30] = call_used_regs[30] = 1;
20192 if (optimize_size)
20194 fixed_regs[8] = call_used_regs[8] = 1;
20195 fixed_regs[9] = call_used_regs[9] = 1;
20196 fixed_regs[10] = call_used_regs[10] = 1;
20197 fixed_regs[11] = call_used_regs[11] = 1;
20198 fixed_regs[12] = call_used_regs[12] = 1;
20199 fixed_regs[13] = call_used_regs[13] = 1;
20200 fixed_regs[14] = call_used_regs[14] = 1;
20201 fixed_regs[15] = call_used_regs[15] = 1;
20204 /* Do not allow HI and LO to be treated as register operands.
20205 There are no MTHI or MTLO instructions (or any real need
20206 for them) and one-way registers cannot easily be reloaded. */
20207 AND_COMPL_HARD_REG_SET (operand_reg_set,
20208 reg_class_contents[(int) MD_REGS]);
20210 /* $f20-$f23 are call-clobbered for n64. */
20211 if (mips_abi == ABI_64)
20213 int regno;
20214 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
20215 call_really_used_regs[regno] = call_used_regs[regno] = 1;
20217 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
20218 for n32 and o32 FP64. */
20219 if (mips_abi == ABI_N32
20220 || (mips_abi == ABI_32
20221 && TARGET_FLOAT64))
20223 int regno;
20224 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
20225 call_really_used_regs[regno] = call_used_regs[regno] = 1;
20227 /* Make sure that double-register accumulator values are correctly
20228 ordered for the current endianness. */
20229 if (TARGET_LITTLE_ENDIAN)
20231 unsigned int regno;
20233 mips_swap_registers (MD_REG_FIRST);
20234 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
20235 mips_swap_registers (regno);
20239 /* Implement EH_USES. */
20241 bool
20242 mips_eh_uses (unsigned int regno)
20244 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
20246 /* We need to force certain registers to be live in order to handle
20247 PIC long branches correctly. See mips_must_initialize_gp_p for
20248 details. */
20249 if (mips_cfun_has_cprestore_slot_p ())
20251 if (regno == CPRESTORE_SLOT_REGNUM)
20252 return true;
20254 else
20256 if (cfun->machine->global_pointer == regno)
20257 return true;
20261 return false;
20264 /* Implement EPILOGUE_USES. */
20266 bool
20267 mips_epilogue_uses (unsigned int regno)
20269 /* Say that the epilogue uses the return address register. Note that
20270 in the case of sibcalls, the values "used by the epilogue" are
20271 considered live at the start of the called function. */
20272 if (regno == RETURN_ADDR_REGNUM)
20273 return true;
20275 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
20276 See the comment above load_call<mode> for details. */
20277 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
20278 return true;
20280 /* An interrupt handler must preserve some registers that are
20281 ordinarily call-clobbered. */
20282 if (cfun->machine->interrupt_handler_p
20283 && mips_interrupt_extra_call_saved_reg_p (regno))
20284 return true;
20286 return false;
20289 /* Return true if INSN needs to be wrapped in ".set noat".
20290 INSN has NOPERANDS operands, stored in OPVEC. */
20292 static bool
20293 mips_need_noat_wrapper_p (rtx_insn *insn, rtx *opvec, int noperands)
20295 if (recog_memoized (insn) >= 0)
20297 subrtx_iterator::array_type array;
20298 for (int i = 0; i < noperands; i++)
20299 FOR_EACH_SUBRTX (iter, array, opvec[i], NONCONST)
20300 if (REG_P (*iter) && REGNO (*iter) == AT_REGNUM)
20301 return true;
20303 return false;
20306 /* Implement FINAL_PRESCAN_INSN. Mark MIPS16 inline constant pools
20307 as data for the purpose of disassembly. For simplicity embed the
20308 pool's initial label number in the local symbol produced so that
20309 multiple pools within a single function end up marked with unique
20310 symbols. The label number is carried by the `consttable' insn
20311 emitted at the beginning of each pool. */
20313 void
20314 mips_final_prescan_insn (rtx_insn *insn, rtx *opvec, int noperands)
20316 if (INSN_P (insn)
20317 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
20318 && XINT (PATTERN (insn), 1) == UNSPEC_CONSTTABLE)
20319 mips_set_text_contents_type (asm_out_file, "__pool_",
20320 XINT (XVECEXP (PATTERN (insn), 0, 0), 0),
20321 FALSE);
20323 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
20324 mips_push_asm_switch (&mips_noat);
20327 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. Reset text marking to
20328 code after a MIPS16 inline constant pool. Like with the beginning
20329 of a pool table use the pool's initial label number to keep symbols
20330 unique. The label number is carried by the `consttable_end' insn
20331 emitted at the end of each pool. */
20333 static void
20334 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx_insn *insn,
20335 rtx *opvec, int noperands)
20337 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
20338 mips_pop_asm_switch (&mips_noat);
20340 if (INSN_P (insn)
20341 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
20342 && XINT (PATTERN (insn), 1) == UNSPEC_CONSTTABLE_END)
20343 mips_set_text_contents_type (asm_out_file, "__pend_",
20344 XINT (XVECEXP (PATTERN (insn), 0, 0), 0),
20345 TRUE);
20348 /* Return the function that is used to expand the <u>mulsidi3 pattern.
20349 EXT_CODE is the code of the extension used. Return NULL if widening
20350 multiplication shouldn't be used. */
20352 mulsidi3_gen_fn
20353 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
20355 bool signed_p;
20357 signed_p = ext_code == SIGN_EXTEND;
20358 if (TARGET_64BIT)
20360 /* Don't use widening multiplication with MULT when we have DMUL. Even
20361 with the extension of its input operands DMUL is faster. Note that
20362 the extension is not needed for signed multiplication. In order to
20363 ensure that we always remove the redundant sign-extension in this
20364 case we still expand mulsidi3 for DMUL. */
20365 if (ISA_HAS_R6DMUL)
20366 return signed_p ? gen_mulsidi3_64bit_r6dmul : NULL;
20367 if (ISA_HAS_DMUL3)
20368 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
20369 if (TARGET_MIPS16)
20370 return (signed_p
20371 ? gen_mulsidi3_64bit_mips16
20372 : gen_umulsidi3_64bit_mips16);
20373 if (TARGET_FIX_R4000)
20374 return NULL;
20375 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
20377 else
20379 if (ISA_HAS_R6MUL)
20380 return (signed_p ? gen_mulsidi3_32bit_r6 : gen_umulsidi3_32bit_r6);
20381 if (TARGET_MIPS16)
20382 return (signed_p
20383 ? gen_mulsidi3_32bit_mips16
20384 : gen_umulsidi3_32bit_mips16);
20385 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
20386 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
20387 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
20391 /* Return true if PATTERN matches the kind of instruction generated by
20392 umips_build_save_restore. SAVE_P is true for store. */
20394 bool
20395 umips_save_restore_pattern_p (bool save_p, rtx pattern)
20397 int n;
20398 unsigned int i;
20399 HOST_WIDE_INT first_offset = 0;
20400 rtx first_base = 0;
20401 unsigned int regmask = 0;
20403 for (n = 0; n < XVECLEN (pattern, 0); n++)
20405 rtx set, reg, mem, this_base;
20406 HOST_WIDE_INT this_offset;
20408 /* Check that we have a SET. */
20409 set = XVECEXP (pattern, 0, n);
20410 if (GET_CODE (set) != SET)
20411 return false;
20413 /* Check that the SET is a load (if restoring) or a store
20414 (if saving). */
20415 mem = save_p ? SET_DEST (set) : SET_SRC (set);
20416 if (!MEM_P (mem) || MEM_VOLATILE_P (mem))
20417 return false;
20419 /* Check that the address is the sum of base and a possibly-zero
20420 constant offset. Determine if the offset is in range. */
20421 mips_split_plus (XEXP (mem, 0), &this_base, &this_offset);
20422 if (!REG_P (this_base))
20423 return false;
20425 if (n == 0)
20427 if (!UMIPS_12BIT_OFFSET_P (this_offset))
20428 return false;
20429 first_base = this_base;
20430 first_offset = this_offset;
20432 else
20434 /* Check that the save slots are consecutive. */
20435 if (REGNO (this_base) != REGNO (first_base)
20436 || this_offset != first_offset + UNITS_PER_WORD * n)
20437 return false;
20440 /* Check that SET's other operand is a register. */
20441 reg = save_p ? SET_SRC (set) : SET_DEST (set);
20442 if (!REG_P (reg))
20443 return false;
20445 regmask |= 1 << REGNO (reg);
20448 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
20449 if (regmask == umips_swm_mask[i])
20450 return true;
20452 return false;
20455 /* Return the assembly instruction for microMIPS LWM or SWM.
20456 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
20458 const char *
20459 umips_output_save_restore (bool save_p, rtx pattern)
20461 static char buffer[300];
20462 char *s;
20463 int n;
20464 HOST_WIDE_INT offset;
20465 rtx base, mem, set, last_set, last_reg;
20467 /* Parse the pattern. */
20468 gcc_assert (umips_save_restore_pattern_p (save_p, pattern));
20470 s = strcpy (buffer, save_p ? "swm\t" : "lwm\t");
20471 s += strlen (s);
20472 n = XVECLEN (pattern, 0);
20474 set = XVECEXP (pattern, 0, 0);
20475 mem = save_p ? SET_DEST (set) : SET_SRC (set);
20476 mips_split_plus (XEXP (mem, 0), &base, &offset);
20478 last_set = XVECEXP (pattern, 0, n - 1);
20479 last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set);
20481 if (REGNO (last_reg) == 31)
20482 n--;
20484 gcc_assert (n <= 9);
20485 if (n == 0)
20487 else if (n == 1)
20488 s += sprintf (s, "%s,", reg_names[16]);
20489 else if (n < 9)
20490 s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]);
20491 else if (n == 9)
20492 s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23],
20493 reg_names[30]);
20495 if (REGNO (last_reg) == 31)
20496 s += sprintf (s, "%s,", reg_names[31]);
20498 s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]);
20499 return buffer;
20502 /* Return true if MEM1 and MEM2 use the same base register, and the
20503 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
20504 register into (from) which the contents of MEM1 will be loaded
20505 (stored), depending on the value of LOAD_P.
20506 SWAP_P is true when the 1st and 2nd instructions are swapped. */
20508 static bool
20509 umips_load_store_pair_p_1 (bool load_p, bool swap_p,
20510 rtx first_reg, rtx mem1, rtx mem2)
20512 rtx base1, base2;
20513 HOST_WIDE_INT offset1, offset2;
20515 if (!MEM_P (mem1) || !MEM_P (mem2))
20516 return false;
20518 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
20519 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
20521 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
20522 return false;
20524 /* Avoid invalid load pair instructions. */
20525 if (load_p && REGNO (first_reg) == REGNO (base1))
20526 return false;
20528 /* We must avoid this case for anti-dependence.
20529 Ex: lw $3, 4($3)
20530 lw $2, 0($3)
20531 first_reg is $2, but the base is $3. */
20532 if (load_p
20533 && swap_p
20534 && REGNO (first_reg) + 1 == REGNO (base1))
20535 return false;
20537 if (offset2 != offset1 + 4)
20538 return false;
20540 if (!UMIPS_12BIT_OFFSET_P (offset1))
20541 return false;
20543 return true;
20546 bool
20547 mips_load_store_bonding_p (rtx *operands, machine_mode mode, bool load_p)
20549 rtx reg1, reg2, mem1, mem2, base1, base2;
20550 enum reg_class rc1, rc2;
20551 HOST_WIDE_INT offset1, offset2;
20553 if (load_p)
20555 reg1 = operands[0];
20556 reg2 = operands[2];
20557 mem1 = operands[1];
20558 mem2 = operands[3];
20560 else
20562 reg1 = operands[1];
20563 reg2 = operands[3];
20564 mem1 = operands[0];
20565 mem2 = operands[2];
20568 if (mips_address_insns (XEXP (mem1, 0), mode, false) == 0
20569 || mips_address_insns (XEXP (mem2, 0), mode, false) == 0)
20570 return false;
20572 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
20573 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
20575 /* Base regs do not match. */
20576 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
20577 return false;
20579 /* Either of the loads is clobbering base register. It is legitimate to bond
20580 loads if second load clobbers base register. However, hardware does not
20581 support such bonding. */
20582 if (load_p
20583 && (REGNO (reg1) == REGNO (base1)
20584 || (REGNO (reg2) == REGNO (base1))))
20585 return false;
20587 /* Loading in same registers. */
20588 if (load_p
20589 && REGNO (reg1) == REGNO (reg2))
20590 return false;
20592 /* The loads/stores are not of same type. */
20593 rc1 = REGNO_REG_CLASS (REGNO (reg1));
20594 rc2 = REGNO_REG_CLASS (REGNO (reg2));
20595 if (rc1 != rc2
20596 && !reg_class_subset_p (rc1, rc2)
20597 && !reg_class_subset_p (rc2, rc1))
20598 return false;
20600 if (abs (offset1 - offset2) != GET_MODE_SIZE (mode))
20601 return false;
20603 return true;
20606 /* OPERANDS describes the operands to a pair of SETs, in the order
20607 dest1, src1, dest2, src2. Return true if the operands can be used
20608 in an LWP or SWP instruction; LOAD_P says which. */
20610 bool
20611 umips_load_store_pair_p (bool load_p, rtx *operands)
20613 rtx reg1, reg2, mem1, mem2;
20615 if (load_p)
20617 reg1 = operands[0];
20618 reg2 = operands[2];
20619 mem1 = operands[1];
20620 mem2 = operands[3];
20622 else
20624 reg1 = operands[1];
20625 reg2 = operands[3];
20626 mem1 = operands[0];
20627 mem2 = operands[2];
20630 if (REGNO (reg2) == REGNO (reg1) + 1)
20631 return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2);
20633 if (REGNO (reg1) == REGNO (reg2) + 1)
20634 return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1);
20636 return false;
20639 /* Return the assembly instruction for a microMIPS LWP or SWP in which
20640 the first register is REG and the first memory slot is MEM.
20641 LOAD_P is true for LWP. */
20643 static void
20644 umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem)
20646 rtx ops[] = {reg, mem};
20648 if (load_p)
20649 output_asm_insn ("lwp\t%0,%1", ops);
20650 else
20651 output_asm_insn ("swp\t%0,%1", ops);
20654 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
20655 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
20657 void
20658 umips_output_load_store_pair (bool load_p, rtx *operands)
20660 rtx reg1, reg2, mem1, mem2;
20661 if (load_p)
20663 reg1 = operands[0];
20664 reg2 = operands[2];
20665 mem1 = operands[1];
20666 mem2 = operands[3];
20668 else
20670 reg1 = operands[1];
20671 reg2 = operands[3];
20672 mem1 = operands[0];
20673 mem2 = operands[2];
20676 if (REGNO (reg2) == REGNO (reg1) + 1)
20678 umips_output_load_store_pair_1 (load_p, reg1, mem1);
20679 return;
20682 gcc_assert (REGNO (reg1) == REGNO (reg2) + 1);
20683 umips_output_load_store_pair_1 (load_p, reg2, mem2);
20686 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
20688 bool
20689 umips_movep_target_p (rtx reg1, rtx reg2)
20691 int regno1, regno2, pair;
20692 unsigned int i;
20693 static const int match[8] = {
20694 0x00000060, /* 5, 6 */
20695 0x000000a0, /* 5, 7 */
20696 0x000000c0, /* 6, 7 */
20697 0x00200010, /* 4, 21 */
20698 0x00400010, /* 4, 22 */
20699 0x00000030, /* 4, 5 */
20700 0x00000050, /* 4, 6 */
20701 0x00000090 /* 4, 7 */
20704 if (!REG_P (reg1) || !REG_P (reg2))
20705 return false;
20707 regno1 = REGNO (reg1);
20708 regno2 = REGNO (reg2);
20710 if (!GP_REG_P (regno1) || !GP_REG_P (regno2))
20711 return false;
20713 pair = (1 << regno1) | (1 << regno2);
20715 for (i = 0; i < ARRAY_SIZE (match); i++)
20716 if (pair == match[i])
20717 return true;
20719 return false;
20722 /* Return the size in bytes of the trampoline code, padded to
20723 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
20724 function address immediately follow. */
20727 mips_trampoline_code_size (void)
20729 if (TARGET_USE_PIC_FN_ADDR_REG)
20730 return 4 * 4;
20731 else if (ptr_mode == DImode)
20732 return 8 * 4;
20733 else if (ISA_HAS_LOAD_DELAY)
20734 return 6 * 4;
20735 else
20736 return 4 * 4;
20739 /* Implement TARGET_TRAMPOLINE_INIT. */
20741 static void
20742 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
20744 rtx addr, end_addr, high, low, opcode, mem;
20745 rtx trampoline[8];
20746 unsigned int i, j;
20747 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
20749 /* Work out the offsets of the pointers from the start of the
20750 trampoline code. */
20751 end_addr_offset = mips_trampoline_code_size ();
20752 static_chain_offset = end_addr_offset;
20753 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
20755 /* Get pointers to the beginning and end of the code block. */
20756 addr = force_reg (Pmode, XEXP (m_tramp, 0));
20757 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
20759 #define OP(X) gen_int_mode (X, SImode)
20761 /* Build up the code in TRAMPOLINE. */
20762 i = 0;
20763 if (TARGET_USE_PIC_FN_ADDR_REG)
20765 /* $25 contains the address of the trampoline. Emit code of the form:
20767 l[wd] $1, target_function_offset($25)
20768 l[wd] $static_chain, static_chain_offset($25)
20769 jr $1
20770 move $25,$1. */
20771 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
20772 target_function_offset,
20773 PIC_FUNCTION_ADDR_REGNUM));
20774 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
20775 static_chain_offset,
20776 PIC_FUNCTION_ADDR_REGNUM));
20777 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
20778 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
20780 else if (ptr_mode == DImode)
20782 /* It's too cumbersome to create the full 64-bit address, so let's
20783 instead use:
20785 move $1, $31
20786 bal 1f
20788 1: l[wd] $25, target_function_offset - 12($31)
20789 l[wd] $static_chain, static_chain_offset - 12($31)
20790 jr $25
20791 move $31, $1
20793 where 12 is the offset of "1:" from the start of the code block. */
20794 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
20795 trampoline[i++] = OP (MIPS_BAL (1));
20796 trampoline[i++] = OP (MIPS_NOP);
20797 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
20798 target_function_offset - 12,
20799 RETURN_ADDR_REGNUM));
20800 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
20801 static_chain_offset - 12,
20802 RETURN_ADDR_REGNUM));
20803 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
20804 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
20806 else
20808 /* If the target has load delays, emit:
20810 lui $1, %hi(end_addr)
20811 lw $25, %lo(end_addr + ...)($1)
20812 lw $static_chain, %lo(end_addr + ...)($1)
20813 jr $25
20816 Otherwise emit:
20818 lui $1, %hi(end_addr)
20819 lw $25, %lo(end_addr + ...)($1)
20820 jr $25
20821 lw $static_chain, %lo(end_addr + ...)($1). */
20823 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
20824 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
20825 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
20826 NULL, false, OPTAB_WIDEN);
20827 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
20828 NULL, false, OPTAB_WIDEN);
20829 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
20831 /* Emit the LUI. */
20832 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
20833 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
20834 NULL, false, OPTAB_WIDEN);
20836 /* Emit the load of the target function. */
20837 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
20838 target_function_offset - end_addr_offset,
20839 AT_REGNUM));
20840 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
20841 NULL, false, OPTAB_WIDEN);
20843 /* Emit the JR here, if we can. */
20844 if (!ISA_HAS_LOAD_DELAY)
20845 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
20847 /* Emit the load of the static chain register. */
20848 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
20849 static_chain_offset - end_addr_offset,
20850 AT_REGNUM));
20851 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
20852 NULL, false, OPTAB_WIDEN);
20854 /* Emit the JR, if we couldn't above. */
20855 if (ISA_HAS_LOAD_DELAY)
20857 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
20858 trampoline[i++] = OP (MIPS_NOP);
20862 #undef OP
20864 /* If we are using compact branches we don't have delay slots so
20865 place the instruction that was in the delay slot before the JRC
20866 instruction. */
20868 if (TARGET_CB_ALWAYS)
20870 rtx temp;
20871 temp = trampoline[i-2];
20872 trampoline[i-2] = trampoline[i-1];
20873 trampoline[i-1] = temp;
20876 /* Copy the trampoline code. Leave any padding uninitialized. */
20877 for (j = 0; j < i; j++)
20879 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
20880 mips_emit_move (mem, trampoline[j]);
20883 /* Set up the static chain pointer field. */
20884 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
20885 mips_emit_move (mem, chain_value);
20887 /* Set up the target function field. */
20888 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
20889 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
20891 /* Flush the code part of the trampoline. */
20892 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
20893 emit_insn (gen_clear_cache (addr, end_addr));
20896 /* Implement FUNCTION_PROFILER. */
20898 void mips_function_profiler (FILE *file)
20900 if (TARGET_MIPS16)
20901 sorry ("mips16 function profiling");
20902 if (TARGET_LONG_CALLS)
20904 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
20905 if (Pmode == DImode)
20906 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
20907 else
20908 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
20910 mips_push_asm_switch (&mips_noat);
20911 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
20912 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
20913 /* _mcount treats $2 as the static chain register. */
20914 if (cfun->static_chain_decl != NULL)
20915 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
20916 reg_names[STATIC_CHAIN_REGNUM]);
20917 if (TARGET_MCOUNT_RA_ADDRESS)
20919 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
20920 ra save location. */
20921 if (cfun->machine->frame.ra_fp_offset == 0)
20922 /* ra not saved, pass zero. */
20923 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
20924 else
20925 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
20926 Pmode == DImode ? "dla" : "la", reg_names[12],
20927 cfun->machine->frame.ra_fp_offset,
20928 reg_names[STACK_POINTER_REGNUM]);
20930 if (!TARGET_NEWABI)
20931 fprintf (file,
20932 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
20933 TARGET_64BIT ? "dsubu" : "subu",
20934 reg_names[STACK_POINTER_REGNUM],
20935 reg_names[STACK_POINTER_REGNUM],
20936 Pmode == DImode ? 16 : 8);
20938 if (TARGET_LONG_CALLS)
20939 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
20940 else
20941 fprintf (file, "\tjal\t_mcount\n");
20942 mips_pop_asm_switch (&mips_noat);
20943 /* _mcount treats $2 as the static chain register. */
20944 if (cfun->static_chain_decl != NULL)
20945 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
20946 reg_names[2]);
20949 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
20950 behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
20951 when TARGET_LOONGSON_VECTORS is true. */
20953 static unsigned HOST_WIDE_INT
20954 mips_shift_truncation_mask (machine_mode mode)
20956 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
20957 return 0;
20959 return GET_MODE_BITSIZE (mode) - 1;
20962 /* Implement TARGET_PREPARE_PCH_SAVE. */
20964 static void
20965 mips_prepare_pch_save (void)
20967 /* We are called in a context where the current compression vs.
20968 non-compression setting should be irrelevant. The question then is:
20969 which setting makes most sense at load time?
20971 The PCH is loaded before the first token is read. We should never have
20972 switched into a compression mode by that point, and thus should not have
20973 populated mips16_globals or micromips_globals. Nor can we load the
20974 entire contents of mips16_globals or micromips_globals from the PCH file,
20975 because they contain a combination of GGC and non-GGC data.
20977 There is therefore no point in trying save the GGC part of
20978 mips16_globals/micromips_globals to the PCH file, or to preserve a
20979 compression setting across the PCH save and load. The loading compiler
20980 would not have access to the non-GGC parts of mips16_globals or
20981 micromips_globals (either from the PCH file, or from a copy that the
20982 loading compiler generated itself) and would have to call target_reinit
20983 anyway.
20985 It therefore seems best to switch back to non-MIPS16 mode and
20986 non-microMIPS mode to save time, and to ensure that mips16_globals and
20987 micromips_globals remain null after a PCH load. */
20988 mips_set_compression_mode (0);
20989 mips16_globals = 0;
20990 micromips_globals = 0;
20993 /* Generate or test for an insn that supports a constant permutation. */
20995 #define MAX_VECT_LEN 16
20997 struct expand_vec_perm_d
20999 rtx target, op0, op1;
21000 unsigned char perm[MAX_VECT_LEN];
21001 machine_mode vmode;
21002 unsigned char nelt;
21003 bool one_vector_p;
21004 bool testing_p;
21007 /* Construct (set target (vec_select op0 (parallel perm))) and
21008 return true if that's a valid instruction in the active ISA. */
21010 static bool
21011 mips_expand_vselect (rtx target, rtx op0,
21012 const unsigned char *perm, unsigned nelt)
21014 rtx rperm[MAX_VECT_LEN], x;
21015 rtx_insn *insn;
21016 unsigned i;
21018 for (i = 0; i < nelt; ++i)
21019 rperm[i] = GEN_INT (perm[i]);
21021 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
21022 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
21023 x = gen_rtx_SET (target, x);
21025 insn = emit_insn (x);
21026 if (recog_memoized (insn) < 0)
21028 remove_insn (insn);
21029 return false;
21031 return true;
21034 /* Similar, but generate a vec_concat from op0 and op1 as well. */
21036 static bool
21037 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
21038 const unsigned char *perm, unsigned nelt)
21040 machine_mode v2mode;
21041 rtx x;
21043 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
21044 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
21045 return mips_expand_vselect (target, x, perm, nelt);
21048 /* Recognize patterns for even-odd extraction. */
21050 static bool
21051 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
21053 unsigned i, odd, nelt = d->nelt;
21054 rtx t0, t1, t2, t3;
21056 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
21057 return false;
21058 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
21059 if (nelt < 4)
21060 return false;
21062 odd = d->perm[0];
21063 if (odd > 1)
21064 return false;
21065 for (i = 1; i < nelt; ++i)
21066 if (d->perm[i] != i * 2 + odd)
21067 return false;
21069 if (d->testing_p)
21070 return true;
21072 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
21073 t0 = gen_reg_rtx (d->vmode);
21074 t1 = gen_reg_rtx (d->vmode);
21075 switch (d->vmode)
21077 case V4HImode:
21078 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
21079 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
21080 if (odd)
21081 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
21082 else
21083 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
21084 break;
21086 case V8QImode:
21087 t2 = gen_reg_rtx (d->vmode);
21088 t3 = gen_reg_rtx (d->vmode);
21089 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
21090 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
21091 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
21092 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
21093 if (odd)
21094 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
21095 else
21096 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
21097 break;
21099 default:
21100 gcc_unreachable ();
21102 return true;
21105 /* Recognize patterns for the Loongson PSHUFH instruction. */
21107 static bool
21108 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
21110 unsigned i, mask;
21111 rtx rmask;
21113 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
21114 return false;
21115 if (d->vmode != V4HImode)
21116 return false;
21117 if (d->testing_p)
21118 return true;
21120 /* Convert the selector into the packed 8-bit form for pshufh. */
21121 /* Recall that loongson is little-endian only. No big-endian
21122 adjustment required. */
21123 for (i = mask = 0; i < 4; i++)
21124 mask |= (d->perm[i] & 3) << (i * 2);
21125 rmask = force_reg (SImode, GEN_INT (mask));
21127 if (d->one_vector_p)
21128 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
21129 else
21131 rtx t0, t1, x, merge, rmerge[4];
21133 t0 = gen_reg_rtx (V4HImode);
21134 t1 = gen_reg_rtx (V4HImode);
21135 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
21136 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
21138 for (i = 0; i < 4; ++i)
21139 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
21140 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
21141 merge = force_reg (V4HImode, merge);
21143 x = gen_rtx_AND (V4HImode, merge, t1);
21144 emit_insn (gen_rtx_SET (t1, x));
21146 x = gen_rtx_NOT (V4HImode, merge);
21147 x = gen_rtx_AND (V4HImode, x, t0);
21148 emit_insn (gen_rtx_SET (t0, x));
21150 x = gen_rtx_IOR (V4HImode, t0, t1);
21151 emit_insn (gen_rtx_SET (d->target, x));
21154 return true;
21157 /* Recognize broadcast patterns for the Loongson. */
21159 static bool
21160 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
21162 unsigned i, elt;
21163 rtx t0, t1;
21165 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
21166 return false;
21167 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
21168 if (d->vmode != V8QImode)
21169 return false;
21170 if (!d->one_vector_p)
21171 return false;
21173 elt = d->perm[0];
21174 for (i = 1; i < 8; ++i)
21175 if (d->perm[i] != elt)
21176 return false;
21178 if (d->testing_p)
21179 return true;
21181 /* With one interleave we put two of the desired element adjacent. */
21182 t0 = gen_reg_rtx (V8QImode);
21183 if (elt < 4)
21184 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
21185 else
21186 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
21188 /* Shuffle that one HImode element into all locations. */
21189 elt &= 3;
21190 elt *= 0x55;
21191 t1 = gen_reg_rtx (V4HImode);
21192 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
21193 force_reg (SImode, GEN_INT (elt))));
21195 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
21196 return true;
21199 /* Construct (set target (vec_select op0 (parallel selector))) and
21200 return true if that's a valid instruction in the active ISA. */
21202 static bool
21203 mips_expand_msa_shuffle (struct expand_vec_perm_d *d)
21205 rtx x, elts[MAX_VECT_LEN];
21206 rtvec v;
21207 rtx_insn *insn;
21208 unsigned i;
21210 if (!ISA_HAS_MSA)
21211 return false;
21213 for (i = 0; i < d->nelt; i++)
21214 elts[i] = GEN_INT (d->perm[i]);
21216 v = gen_rtvec_v (d->nelt, elts);
21217 x = gen_rtx_PARALLEL (VOIDmode, v);
21219 if (!mips_const_vector_shuffle_set_p (x, d->vmode))
21220 return false;
21222 x = gen_rtx_VEC_SELECT (d->vmode, d->op0, x);
21223 x = gen_rtx_SET (d->target, x);
21225 insn = emit_insn (x);
21226 if (recog_memoized (insn) < 0)
21228 remove_insn (insn);
21229 return false;
21231 return true;
21234 static bool
21235 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
21237 unsigned int i, nelt = d->nelt;
21238 unsigned char perm2[MAX_VECT_LEN];
21240 if (d->one_vector_p)
21242 /* Try interleave with alternating operands. */
21243 memcpy (perm2, d->perm, sizeof(perm2));
21244 for (i = 1; i < nelt; i += 2)
21245 perm2[i] += nelt;
21246 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
21247 return true;
21249 else
21251 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
21252 d->perm, nelt))
21253 return true;
21255 /* Try again with swapped operands. */
21256 for (i = 0; i < nelt; ++i)
21257 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
21258 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
21259 return true;
21262 if (mips_expand_vpc_loongson_even_odd (d))
21263 return true;
21264 if (mips_expand_vpc_loongson_pshufh (d))
21265 return true;
21266 if (mips_expand_vpc_loongson_bcast (d))
21267 return true;
21268 if (mips_expand_msa_shuffle (d))
21269 return true;
21270 return false;
21273 /* Expand a vec_perm_const pattern. */
21275 bool
21276 mips_expand_vec_perm_const (rtx operands[4])
21278 struct expand_vec_perm_d d;
21279 int i, nelt, which;
21280 unsigned char orig_perm[MAX_VECT_LEN];
21281 rtx sel;
21282 bool ok;
21284 d.target = operands[0];
21285 d.op0 = operands[1];
21286 d.op1 = operands[2];
21287 sel = operands[3];
21289 d.vmode = GET_MODE (d.target);
21290 gcc_assert (VECTOR_MODE_P (d.vmode));
21291 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
21292 d.testing_p = false;
21294 for (i = which = 0; i < nelt; ++i)
21296 rtx e = XVECEXP (sel, 0, i);
21297 int ei = INTVAL (e) & (2 * nelt - 1);
21298 which |= (ei < nelt ? 1 : 2);
21299 orig_perm[i] = ei;
21301 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
21303 switch (which)
21305 default:
21306 gcc_unreachable();
21308 case 3:
21309 d.one_vector_p = false;
21310 if (!rtx_equal_p (d.op0, d.op1))
21311 break;
21312 /* FALLTHRU */
21314 case 2:
21315 for (i = 0; i < nelt; ++i)
21316 d.perm[i] &= nelt - 1;
21317 d.op0 = d.op1;
21318 d.one_vector_p = true;
21319 break;
21321 case 1:
21322 d.op1 = d.op0;
21323 d.one_vector_p = true;
21324 break;
21327 ok = mips_expand_vec_perm_const_1 (&d);
21329 /* If we were given a two-vector permutation which just happened to
21330 have both input vectors equal, we folded this into a one-vector
21331 permutation. There are several loongson patterns that are matched
21332 via direct vec_select+vec_concat expansion, but we do not have
21333 support in mips_expand_vec_perm_const_1 to guess the adjustment
21334 that should be made for a single operand. Just try again with
21335 the original permutation. */
21336 if (!ok && which == 3)
21338 d.op0 = operands[1];
21339 d.op1 = operands[2];
21340 d.one_vector_p = false;
21341 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
21342 ok = mips_expand_vec_perm_const_1 (&d);
21345 return ok;
21348 /* Implement TARGET_SCHED_REASSOCIATION_WIDTH. */
21350 static int
21351 mips_sched_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
21352 machine_mode mode)
21354 if (MSA_SUPPORTED_MODE_P (mode))
21355 return 2;
21356 return 1;
21359 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
21361 static bool
21362 mips_vectorize_vec_perm_const_ok (machine_mode vmode,
21363 const unsigned char *sel)
21365 struct expand_vec_perm_d d;
21366 unsigned int i, nelt, which;
21367 bool ret;
21369 d.vmode = vmode;
21370 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
21371 d.testing_p = true;
21372 memcpy (d.perm, sel, nelt);
21374 /* Categorize the set of elements in the selector. */
21375 for (i = which = 0; i < nelt; ++i)
21377 unsigned char e = d.perm[i];
21378 gcc_assert (e < 2 * nelt);
21379 which |= (e < nelt ? 1 : 2);
21382 /* For all elements from second vector, fold the elements to first. */
21383 if (which == 2)
21384 for (i = 0; i < nelt; ++i)
21385 d.perm[i] -= nelt;
21387 /* Check whether the mask can be applied to the vector type. */
21388 d.one_vector_p = (which != 3);
21390 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
21391 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
21392 if (!d.one_vector_p)
21393 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
21395 start_sequence ();
21396 ret = mips_expand_vec_perm_const_1 (&d);
21397 end_sequence ();
21399 return ret;
21402 /* Expand an integral vector unpack operation. */
21404 void
21405 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
21407 machine_mode imode = GET_MODE (operands[1]);
21408 rtx (*unpack) (rtx, rtx, rtx);
21409 rtx (*cmpFunc) (rtx, rtx, rtx);
21410 rtx tmp, dest, zero;
21412 if (ISA_HAS_MSA)
21414 switch (imode)
21416 case V4SImode:
21417 if (BYTES_BIG_ENDIAN != high_p)
21418 unpack = gen_msa_ilvl_w;
21419 else
21420 unpack = gen_msa_ilvr_w;
21422 cmpFunc = gen_msa_clt_s_w;
21423 break;
21425 case V8HImode:
21426 if (BYTES_BIG_ENDIAN != high_p)
21427 unpack = gen_msa_ilvl_h;
21428 else
21429 unpack = gen_msa_ilvr_h;
21431 cmpFunc = gen_msa_clt_s_h;
21432 break;
21434 case V16QImode:
21435 if (BYTES_BIG_ENDIAN != high_p)
21436 unpack = gen_msa_ilvl_b;
21437 else
21438 unpack = gen_msa_ilvr_b;
21440 cmpFunc = gen_msa_clt_s_b;
21441 break;
21443 default:
21444 gcc_unreachable ();
21445 break;
21448 if (!unsigned_p)
21450 /* Extract sign extention for each element comparing each element
21451 with immediate zero. */
21452 tmp = gen_reg_rtx (imode);
21453 emit_insn (cmpFunc (tmp, operands[1], CONST0_RTX (imode)));
21455 else
21456 tmp = force_reg (imode, CONST0_RTX (imode));
21458 dest = gen_reg_rtx (imode);
21460 emit_insn (unpack (dest, operands[1], tmp));
21461 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
21462 return;
21465 switch (imode)
21467 case V8QImode:
21468 if (high_p)
21469 unpack = gen_loongson_punpckhbh;
21470 else
21471 unpack = gen_loongson_punpcklbh;
21472 cmpFunc = gen_loongson_pcmpgtb;
21473 break;
21474 case V4HImode:
21475 if (high_p)
21476 unpack = gen_loongson_punpckhhw;
21477 else
21478 unpack = gen_loongson_punpcklhw;
21479 cmpFunc = gen_loongson_pcmpgth;
21480 break;
21481 default:
21482 gcc_unreachable ();
21485 zero = force_reg (imode, CONST0_RTX (imode));
21486 if (unsigned_p)
21487 tmp = zero;
21488 else
21490 tmp = gen_reg_rtx (imode);
21491 emit_insn (cmpFunc (tmp, zero, operands[1]));
21494 dest = gen_reg_rtx (imode);
21495 emit_insn (unpack (dest, operands[1], tmp));
21497 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
21500 /* Construct and return PARALLEL RTX with CONST_INTs for HIGH (high_p == TRUE)
21501 or LOW (high_p == FALSE) half of a vector for mode MODE. */
21504 mips_msa_vec_parallel_const_half (machine_mode mode, bool high_p)
21506 int nunits = GET_MODE_NUNITS (mode);
21507 rtvec v = rtvec_alloc (nunits / 2);
21508 int base;
21509 int i;
21511 if (BYTES_BIG_ENDIAN)
21512 base = high_p ? 0 : nunits / 2;
21513 else
21514 base = high_p ? nunits / 2 : 0;
21516 for (i = 0; i < nunits / 2; i++)
21517 RTVEC_ELT (v, i) = GEN_INT (base + i);
21519 return gen_rtx_PARALLEL (VOIDmode, v);
21522 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
21524 static inline bool
21525 mips_constant_elt_p (rtx x)
21527 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
21530 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
21532 static void
21533 mips_expand_vi_broadcast (machine_mode vmode, rtx target, rtx elt)
21535 struct expand_vec_perm_d d;
21536 rtx t1;
21537 bool ok;
21539 if (elt != const0_rtx)
21540 elt = force_reg (GET_MODE_INNER (vmode), elt);
21541 if (REG_P (elt))
21542 elt = gen_lowpart (DImode, elt);
21544 t1 = gen_reg_rtx (vmode);
21545 switch (vmode)
21547 case V8QImode:
21548 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
21549 break;
21550 case V4HImode:
21551 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
21552 break;
21553 default:
21554 gcc_unreachable ();
21557 memset (&d, 0, sizeof (d));
21558 d.target = target;
21559 d.op0 = t1;
21560 d.op1 = t1;
21561 d.vmode = vmode;
21562 d.nelt = GET_MODE_NUNITS (vmode);
21563 d.one_vector_p = true;
21565 ok = mips_expand_vec_perm_const_1 (&d);
21566 gcc_assert (ok);
21569 /* Return a const_int vector of VAL with mode MODE. */
21572 mips_gen_const_int_vector (machine_mode mode, int val)
21574 int nunits = GET_MODE_NUNITS (mode);
21575 rtvec v = rtvec_alloc (nunits);
21576 int i;
21578 for (i = 0; i < nunits; i++)
21579 RTVEC_ELT (v, i) = gen_int_mode (val, GET_MODE_INNER (mode));
21581 return gen_rtx_CONST_VECTOR (mode, v);
21584 /* Return a vector of repeated 4-element sets generated from
21585 immediate VAL in mode MODE. */
21587 static rtx
21588 mips_gen_const_int_vector_shuffle (machine_mode mode, int val)
21590 int nunits = GET_MODE_NUNITS (mode);
21591 int nsets = nunits / 4;
21592 rtx elts[MAX_VECT_LEN];
21593 int set = 0;
21594 int i, j;
21596 /* Generate a const_int vector replicating the same 4-element set
21597 from an immediate. */
21598 for (j = 0; j < nsets; j++, set = 4 * j)
21599 for (i = 0; i < 4; i++)
21600 elts[set + i] = GEN_INT (set + ((val >> (2 * i)) & 0x3));
21602 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nunits, elts));
21605 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
21606 elements of VALS with zeros, copy the constant vector to TARGET. */
21608 static void
21609 mips_expand_vi_constant (machine_mode vmode, unsigned nelt,
21610 rtx target, rtx vals)
21612 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
21613 unsigned i;
21615 for (i = 0; i < nelt; ++i)
21617 rtx elem = RTVEC_ELT (vec, i);
21618 if (!mips_constant_elt_p (elem))
21619 RTVEC_ELT (vec, i) = CONST0_RTX (GET_MODE (elem));
21622 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
21626 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
21628 static void
21629 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
21631 mips_expand_vi_constant (V4HImode, 4, target, vals);
21633 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
21634 GEN_INT (one_var)));
21637 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
21639 static void
21640 mips_expand_vi_general (machine_mode vmode, machine_mode imode,
21641 unsigned nelt, unsigned nvar, rtx target, rtx vals)
21643 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
21644 unsigned int i, isize = GET_MODE_SIZE (imode);
21646 if (nvar < nelt)
21647 mips_expand_vi_constant (vmode, nelt, mem, vals);
21649 for (i = 0; i < nelt; ++i)
21651 rtx x = XVECEXP (vals, 0, i);
21652 if (!mips_constant_elt_p (x))
21653 emit_move_insn (adjust_address (mem, imode, i * isize), x);
21656 emit_move_insn (target, mem);
21659 /* Expand a vector initialization. */
21661 void
21662 mips_expand_vector_init (rtx target, rtx vals)
21664 machine_mode vmode = GET_MODE (target);
21665 machine_mode imode = GET_MODE_INNER (vmode);
21666 unsigned i, nelt = GET_MODE_NUNITS (vmode);
21667 unsigned nvar = 0, one_var = -1u;
21668 bool all_same = true;
21669 rtx x;
21671 for (i = 0; i < nelt; ++i)
21673 x = XVECEXP (vals, 0, i);
21674 if (!mips_constant_elt_p (x))
21675 nvar++, one_var = i;
21676 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
21677 all_same = false;
21680 if (ISA_HAS_MSA)
21682 if (all_same)
21684 rtx same = XVECEXP (vals, 0, 0);
21685 rtx temp, temp2;
21687 if (CONST_INT_P (same) && nvar == 0
21688 && mips_signed_immediate_p (INTVAL (same), 10, 0))
21690 switch (vmode)
21692 case V16QImode:
21693 case V8HImode:
21694 case V4SImode:
21695 case V2DImode:
21696 emit_move_insn (target, same);
21697 return;
21699 default:
21700 break;
21703 temp = gen_reg_rtx (imode);
21704 if (imode == GET_MODE (same))
21705 temp2 = same;
21706 else if (GET_MODE_SIZE (imode) >= UNITS_PER_WORD)
21707 temp2 = simplify_gen_subreg (imode, same, GET_MODE (same), 0);
21708 else
21709 temp2 = lowpart_subreg (imode, same, GET_MODE (same));
21710 emit_move_insn (temp, temp2);
21712 switch (vmode)
21714 case V16QImode:
21715 case V8HImode:
21716 case V4SImode:
21717 case V2DImode:
21718 mips_emit_move (target, gen_rtx_VEC_DUPLICATE (vmode, temp));
21719 break;
21721 case V4SFmode:
21722 emit_insn (gen_msa_splati_w_f_scalar (target, temp));
21723 break;
21725 case V2DFmode:
21726 emit_insn (gen_msa_splati_d_f_scalar (target, temp));
21727 break;
21729 default:
21730 gcc_unreachable ();
21733 else
21735 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
21737 for (i = 0; i < nelt; ++i)
21738 RTVEC_ELT (vec, i) = CONST0_RTX (imode);
21740 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
21742 for (i = 0; i < nelt; ++i)
21744 rtx temp = gen_reg_rtx (imode);
21745 emit_move_insn (temp, XVECEXP (vals, 0, i));
21746 switch (vmode)
21748 case V16QImode:
21749 emit_insn (gen_vec_setv16qi (target, temp, GEN_INT (i)));
21750 break;
21752 case V8HImode:
21753 emit_insn (gen_vec_setv8hi (target, temp, GEN_INT (i)));
21754 break;
21756 case V4SImode:
21757 emit_insn (gen_vec_setv4si (target, temp, GEN_INT (i)));
21758 break;
21760 case V2DImode:
21761 emit_insn (gen_vec_setv2di (target, temp, GEN_INT (i)));
21762 break;
21764 case V4SFmode:
21765 emit_insn (gen_vec_setv4sf (target, temp, GEN_INT (i)));
21766 break;
21768 case V2DFmode:
21769 emit_insn (gen_vec_setv2df (target, temp, GEN_INT (i)));
21770 break;
21772 default:
21773 gcc_unreachable ();
21777 return;
21780 /* Load constants from the pool, or whatever's handy. */
21781 if (nvar == 0)
21783 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
21784 return;
21787 /* For two-part initialization, always use CONCAT. */
21788 if (nelt == 2)
21790 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
21791 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
21792 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
21793 emit_insn (gen_rtx_SET (target, x));
21794 return;
21797 /* Loongson is the only cpu with vectors with more elements. */
21798 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
21800 /* If all values are identical, broadcast the value. */
21801 if (all_same)
21803 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
21804 return;
21807 /* If we've only got one non-variable V4HImode, use PINSRH. */
21808 if (nvar == 1 && vmode == V4HImode)
21810 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
21811 return;
21814 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
21817 /* Expand a vector reduction. */
21819 void
21820 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
21822 machine_mode vmode = GET_MODE (in);
21823 unsigned char perm2[2];
21824 rtx last, next, fold, x;
21825 bool ok;
21827 last = in;
21828 fold = gen_reg_rtx (vmode);
21829 switch (vmode)
21831 case V2SFmode:
21832 /* Use PUL/PLU to produce { L, H } op { H, L }.
21833 By reversing the pair order, rather than a pure interleave high,
21834 we avoid erroneous exceptional conditions that we might otherwise
21835 produce from the computation of H op H. */
21836 perm2[0] = 1;
21837 perm2[1] = 2;
21838 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
21839 gcc_assert (ok);
21840 break;
21842 case V2SImode:
21843 /* Use interleave to produce { H, L } op { H, H }. */
21844 emit_insn (gen_loongson_punpckhwd (fold, last, last));
21845 break;
21847 case V4HImode:
21848 /* Perform the first reduction with interleave,
21849 and subsequent reductions with shifts. */
21850 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
21852 next = gen_reg_rtx (vmode);
21853 emit_insn (gen (next, last, fold));
21854 last = next;
21856 fold = gen_reg_rtx (vmode);
21857 x = force_reg (SImode, GEN_INT (16));
21858 emit_insn (gen_vec_shr_v4hi (fold, last, x));
21859 break;
21861 case V8QImode:
21862 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
21864 next = gen_reg_rtx (vmode);
21865 emit_insn (gen (next, last, fold));
21866 last = next;
21868 fold = gen_reg_rtx (vmode);
21869 x = force_reg (SImode, GEN_INT (16));
21870 emit_insn (gen_vec_shr_v8qi (fold, last, x));
21872 next = gen_reg_rtx (vmode);
21873 emit_insn (gen (next, last, fold));
21874 last = next;
21876 fold = gen_reg_rtx (vmode);
21877 x = force_reg (SImode, GEN_INT (8));
21878 emit_insn (gen_vec_shr_v8qi (fold, last, x));
21879 break;
21881 default:
21882 gcc_unreachable ();
21885 emit_insn (gen (target, last, fold));
21888 /* Expand a vector minimum/maximum. */
21890 void
21891 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
21892 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
21894 machine_mode vmode = GET_MODE (target);
21895 rtx tc, t0, t1, x;
21897 tc = gen_reg_rtx (vmode);
21898 t0 = gen_reg_rtx (vmode);
21899 t1 = gen_reg_rtx (vmode);
21901 /* op0 > op1 */
21902 emit_insn (cmp (tc, op0, op1));
21904 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
21905 emit_insn (gen_rtx_SET (t0, x));
21907 x = gen_rtx_NOT (vmode, tc);
21908 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
21909 emit_insn (gen_rtx_SET (t1, x));
21911 x = gen_rtx_IOR (vmode, t0, t1);
21912 emit_insn (gen_rtx_SET (target, x));
21915 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
21917 machine_mode
21918 mips_hard_regno_caller_save_mode (unsigned int regno,
21919 unsigned int nregs,
21920 machine_mode mode)
21922 /* For performance, avoid saving/restoring upper parts of a register
21923 by returning MODE as save mode when the mode is known. */
21924 if (mode == VOIDmode)
21925 return choose_hard_reg_mode (regno, nregs, false);
21926 else
21927 return mode;
21930 /* Generate RTL for comparing CMP_OP0 and CMP_OP1 using condition COND and
21931 store the result -1 or 0 in DEST. */
21933 static void
21934 mips_expand_msa_cmp (rtx dest, enum rtx_code cond, rtx op0, rtx op1)
21936 machine_mode cmp_mode = GET_MODE (op0);
21937 int unspec = -1;
21938 bool negate = false;
21940 switch (cmp_mode)
21942 case V16QImode:
21943 case V8HImode:
21944 case V4SImode:
21945 case V2DImode:
21946 switch (cond)
21948 case NE:
21949 cond = reverse_condition (cond);
21950 negate = true;
21951 break;
21952 case EQ:
21953 case LT:
21954 case LE:
21955 case LTU:
21956 case LEU:
21957 break;
21958 case GE:
21959 case GT:
21960 case GEU:
21961 case GTU:
21962 std::swap (op0, op1);
21963 cond = swap_condition (cond);
21964 break;
21965 default:
21966 gcc_unreachable ();
21968 mips_emit_binary (cond, dest, op0, op1);
21969 if (negate)
21970 emit_move_insn (dest, gen_rtx_NOT (GET_MODE (dest), dest));
21971 break;
21973 case V4SFmode:
21974 case V2DFmode:
21975 switch (cond)
21977 case UNORDERED:
21978 case ORDERED:
21979 case EQ:
21980 case NE:
21981 case UNEQ:
21982 case UNLE:
21983 case UNLT:
21984 break;
21985 case LTGT: cond = NE; break;
21986 case UNGE: cond = UNLE; std::swap (op0, op1); break;
21987 case UNGT: cond = UNLT; std::swap (op0, op1); break;
21988 case LE: unspec = UNSPEC_MSA_FSLE; break;
21989 case LT: unspec = UNSPEC_MSA_FSLT; break;
21990 case GE: unspec = UNSPEC_MSA_FSLE; std::swap (op0, op1); break;
21991 case GT: unspec = UNSPEC_MSA_FSLT; std::swap (op0, op1); break;
21992 default:
21993 gcc_unreachable ();
21995 if (unspec < 0)
21996 mips_emit_binary (cond, dest, op0, op1);
21997 else
21999 rtx x = gen_rtx_UNSPEC (GET_MODE (dest),
22000 gen_rtvec (2, op0, op1), unspec);
22001 emit_insn (gen_rtx_SET (dest, x));
22003 break;
22005 default:
22006 gcc_unreachable ();
22007 break;
22011 /* Expand VEC_COND_EXPR, where:
22012 MODE is mode of the result
22013 VIMODE equivalent integer mode
22014 OPERANDS operands of VEC_COND_EXPR. */
22016 void
22017 mips_expand_vec_cond_expr (machine_mode mode, machine_mode vimode,
22018 rtx *operands)
22020 rtx cond = operands[3];
22021 rtx cmp_op0 = operands[4];
22022 rtx cmp_op1 = operands[5];
22023 rtx cmp_res = gen_reg_rtx (vimode);
22025 mips_expand_msa_cmp (cmp_res, GET_CODE (cond), cmp_op0, cmp_op1);
22027 /* We handle the following cases:
22028 1) r = a CMP b ? -1 : 0
22029 2) r = a CMP b ? -1 : v
22030 3) r = a CMP b ? v : 0
22031 4) r = a CMP b ? v1 : v2 */
22033 /* Case (1) above. We only move the results. */
22034 if (operands[1] == CONSTM1_RTX (vimode)
22035 && operands[2] == CONST0_RTX (vimode))
22036 emit_move_insn (operands[0], cmp_res);
22037 else
22039 rtx src1 = gen_reg_rtx (vimode);
22040 rtx src2 = gen_reg_rtx (vimode);
22041 rtx mask = gen_reg_rtx (vimode);
22042 rtx bsel;
22044 /* Move the vector result to use it as a mask. */
22045 emit_move_insn (mask, cmp_res);
22047 if (register_operand (operands[1], mode))
22049 rtx xop1 = operands[1];
22050 if (mode != vimode)
22052 xop1 = gen_reg_rtx (vimode);
22053 emit_move_insn (xop1, gen_rtx_SUBREG (vimode, operands[1], 0));
22055 emit_move_insn (src1, xop1);
22057 else
22059 gcc_assert (operands[1] == CONSTM1_RTX (vimode));
22060 /* Case (2) if the below doesn't move the mask to src2. */
22061 emit_move_insn (src1, mask);
22064 if (register_operand (operands[2], mode))
22066 rtx xop2 = operands[2];
22067 if (mode != vimode)
22069 xop2 = gen_reg_rtx (vimode);
22070 emit_move_insn (xop2, gen_rtx_SUBREG (vimode, operands[2], 0));
22072 emit_move_insn (src2, xop2);
22074 else
22076 gcc_assert (operands[2] == CONST0_RTX (mode));
22077 /* Case (3) if the above didn't move the mask to src1. */
22078 emit_move_insn (src2, mask);
22081 /* We deal with case (4) if the mask wasn't moved to either src1 or src2.
22082 In any case, we eventually do vector mask-based copy. */
22083 bsel = gen_rtx_IOR (vimode,
22084 gen_rtx_AND (vimode,
22085 gen_rtx_NOT (vimode, mask), src2),
22086 gen_rtx_AND (vimode, mask, src1));
22087 /* The result is placed back to a register with the mask. */
22088 emit_insn (gen_rtx_SET (mask, bsel));
22089 emit_move_insn (operands[0], gen_rtx_SUBREG (mode, mask, 0));
22093 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
22095 unsigned int
22096 mips_case_values_threshold (void)
22098 /* In MIPS16 mode using a larger case threshold generates smaller code. */
22099 if (TARGET_MIPS16 && optimize_size)
22100 return 10;
22101 else
22102 return default_case_values_threshold ();
22105 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
22107 static void
22108 mips_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
22110 if (!TARGET_HARD_FLOAT_ABI)
22111 return;
22112 tree exceptions_var = create_tmp_var_raw (MIPS_ATYPE_USI);
22113 tree fcsr_orig_var = create_tmp_var_raw (MIPS_ATYPE_USI);
22114 tree fcsr_mod_var = create_tmp_var_raw (MIPS_ATYPE_USI);
22115 tree get_fcsr = mips_builtin_decls[MIPS_GET_FCSR];
22116 tree set_fcsr = mips_builtin_decls[MIPS_SET_FCSR];
22117 tree get_fcsr_hold_call = build_call_expr (get_fcsr, 0);
22118 tree hold_assign_orig = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
22119 fcsr_orig_var, get_fcsr_hold_call);
22120 tree hold_mod_val = build2 (BIT_AND_EXPR, MIPS_ATYPE_USI, fcsr_orig_var,
22121 build_int_cst (MIPS_ATYPE_USI, 0xfffff003));
22122 tree hold_assign_mod = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
22123 fcsr_mod_var, hold_mod_val);
22124 tree set_fcsr_hold_call = build_call_expr (set_fcsr, 1, fcsr_mod_var);
22125 tree hold_all = build2 (COMPOUND_EXPR, MIPS_ATYPE_USI,
22126 hold_assign_orig, hold_assign_mod);
22127 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_all,
22128 set_fcsr_hold_call);
22130 *clear = build_call_expr (set_fcsr, 1, fcsr_mod_var);
22132 tree get_fcsr_update_call = build_call_expr (get_fcsr, 0);
22133 *update = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
22134 exceptions_var, get_fcsr_update_call);
22135 tree set_fcsr_update_call = build_call_expr (set_fcsr, 1, fcsr_orig_var);
22136 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
22137 set_fcsr_update_call);
22138 tree atomic_feraiseexcept
22139 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
22140 tree int_exceptions_var = fold_convert (integer_type_node,
22141 exceptions_var);
22142 tree atomic_feraiseexcept_call = build_call_expr (atomic_feraiseexcept,
22143 1, int_exceptions_var);
22144 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
22145 atomic_feraiseexcept_call);
22148 /* Implement TARGET_SPILL_CLASS. */
22150 static reg_class_t
22151 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED,
22152 machine_mode mode ATTRIBUTE_UNUSED)
22154 if (TARGET_MIPS16)
22155 return SPILL_REGS;
22156 return NO_REGS;
22159 /* Implement TARGET_LRA_P. */
22161 static bool
22162 mips_lra_p (void)
22164 return mips_lra_flag;
22167 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. */
22169 static reg_class_t
22170 mips_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class,
22171 reg_class_t best_class ATTRIBUTE_UNUSED)
22173 /* LRA will allocate an FPR for an integer mode pseudo instead of spilling
22174 to memory if an FPR is present in the allocno class. It is rare that
22175 we actually need to place an integer mode value in an FPR so where
22176 possible limit the allocation to GR_REGS. This will slightly pessimize
22177 code that involves integer to/from float conversions as these will have
22178 to reload into FPRs in LRA. Such reloads are sometimes eliminated and
22179 sometimes only partially eliminated. We choose to take this penalty
22180 in order to eliminate usage of FPRs in code that does not use floating
22181 point data.
22183 This change has a similar effect to increasing the cost of FPR->GPR
22184 register moves for integer modes so that they are higher than the cost
22185 of memory but changing the allocno class is more reliable.
22187 This is also similar to forbidding integer mode values in FPRs entirely
22188 but this would lead to an inconsistency in the integer to/from float
22189 instructions that say integer mode values must be placed in FPRs. */
22190 if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno)) && allocno_class == ALL_REGS)
22191 return GR_REGS;
22192 return allocno_class;
22195 /* Implement TARGET_PROMOTE_FUNCTION_MODE */
22197 /* This function is equivalent to default_promote_function_mode_always_promote
22198 except that it returns a promoted mode even if type is NULL_TREE. This is
22199 needed by libcalls which have no type (only a mode) such as fixed conversion
22200 routines that take a signed or unsigned char/short argument and convert it
22201 to a fixed type. */
22203 static machine_mode
22204 mips_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
22205 machine_mode mode,
22206 int *punsignedp ATTRIBUTE_UNUSED,
22207 const_tree fntype ATTRIBUTE_UNUSED,
22208 int for_return ATTRIBUTE_UNUSED)
22210 int unsignedp;
22212 if (type != NULL_TREE)
22213 return promote_mode (type, mode, punsignedp);
22215 unsignedp = *punsignedp;
22216 PROMOTE_MODE (mode, unsignedp, type);
22217 *punsignedp = unsignedp;
22218 return mode;
22221 /* Initialize the GCC target structure. */
22222 #undef TARGET_ASM_ALIGNED_HI_OP
22223 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
22224 #undef TARGET_ASM_ALIGNED_SI_OP
22225 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
22226 #undef TARGET_ASM_ALIGNED_DI_OP
22227 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
22229 #undef TARGET_OPTION_OVERRIDE
22230 #define TARGET_OPTION_OVERRIDE mips_option_override
22232 #undef TARGET_LEGITIMIZE_ADDRESS
22233 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
22235 #undef TARGET_ASM_FUNCTION_PROLOGUE
22236 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
22237 #undef TARGET_ASM_FUNCTION_EPILOGUE
22238 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
22239 #undef TARGET_ASM_SELECT_RTX_SECTION
22240 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
22241 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
22242 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
22244 #undef TARGET_SCHED_INIT
22245 #define TARGET_SCHED_INIT mips_sched_init
22246 #undef TARGET_SCHED_REORDER
22247 #define TARGET_SCHED_REORDER mips_sched_reorder
22248 #undef TARGET_SCHED_REORDER2
22249 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
22250 #undef TARGET_SCHED_VARIABLE_ISSUE
22251 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
22252 #undef TARGET_SCHED_ADJUST_COST
22253 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
22254 #undef TARGET_SCHED_ISSUE_RATE
22255 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
22256 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
22257 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
22258 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
22259 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
22260 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
22261 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
22262 mips_multipass_dfa_lookahead
22263 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
22264 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
22265 mips_small_register_classes_for_mode_p
22267 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
22268 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
22270 #undef TARGET_INSERT_ATTRIBUTES
22271 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
22272 #undef TARGET_MERGE_DECL_ATTRIBUTES
22273 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
22274 #undef TARGET_CAN_INLINE_P
22275 #define TARGET_CAN_INLINE_P mips_can_inline_p
22276 #undef TARGET_SET_CURRENT_FUNCTION
22277 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
22279 #undef TARGET_VALID_POINTER_MODE
22280 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
22281 #undef TARGET_REGISTER_MOVE_COST
22282 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
22283 #undef TARGET_REGISTER_PRIORITY
22284 #define TARGET_REGISTER_PRIORITY mips_register_priority
22285 #undef TARGET_MEMORY_MOVE_COST
22286 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
22287 #undef TARGET_RTX_COSTS
22288 #define TARGET_RTX_COSTS mips_rtx_costs
22289 #undef TARGET_ADDRESS_COST
22290 #define TARGET_ADDRESS_COST mips_address_cost
22292 #undef TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P
22293 #define TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P mips_no_speculation_in_delay_slots_p
22295 #undef TARGET_IN_SMALL_DATA_P
22296 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
22298 #undef TARGET_MACHINE_DEPENDENT_REORG
22299 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
22301 #undef TARGET_PREFERRED_RELOAD_CLASS
22302 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
22304 #undef TARGET_EXPAND_TO_RTL_HOOK
22305 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
22306 #undef TARGET_ASM_FILE_START
22307 #define TARGET_ASM_FILE_START mips_file_start
22308 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
22309 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
22310 #undef TARGET_ASM_CODE_END
22311 #define TARGET_ASM_CODE_END mips_code_end
22313 #undef TARGET_INIT_LIBFUNCS
22314 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
22316 #undef TARGET_BUILD_BUILTIN_VA_LIST
22317 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
22318 #undef TARGET_EXPAND_BUILTIN_VA_START
22319 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
22320 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
22321 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
22323 #undef TARGET_PROMOTE_FUNCTION_MODE
22324 #define TARGET_PROMOTE_FUNCTION_MODE mips_promote_function_mode
22325 #undef TARGET_FUNCTION_VALUE
22326 #define TARGET_FUNCTION_VALUE mips_function_value
22327 #undef TARGET_LIBCALL_VALUE
22328 #define TARGET_LIBCALL_VALUE mips_libcall_value
22329 #undef TARGET_FUNCTION_VALUE_REGNO_P
22330 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
22331 #undef TARGET_RETURN_IN_MEMORY
22332 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
22333 #undef TARGET_RETURN_IN_MSB
22334 #define TARGET_RETURN_IN_MSB mips_return_in_msb
22336 #undef TARGET_ASM_OUTPUT_MI_THUNK
22337 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
22338 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
22339 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
22341 #undef TARGET_PRINT_OPERAND
22342 #define TARGET_PRINT_OPERAND mips_print_operand
22343 #undef TARGET_PRINT_OPERAND_ADDRESS
22344 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
22345 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
22346 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
22348 #undef TARGET_SETUP_INCOMING_VARARGS
22349 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
22350 #undef TARGET_STRICT_ARGUMENT_NAMING
22351 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
22352 #undef TARGET_MUST_PASS_IN_STACK
22353 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
22354 #undef TARGET_PASS_BY_REFERENCE
22355 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
22356 #undef TARGET_CALLEE_COPIES
22357 #define TARGET_CALLEE_COPIES mips_callee_copies
22358 #undef TARGET_ARG_PARTIAL_BYTES
22359 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
22360 #undef TARGET_FUNCTION_ARG
22361 #define TARGET_FUNCTION_ARG mips_function_arg
22362 #undef TARGET_FUNCTION_ARG_ADVANCE
22363 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
22364 #undef TARGET_FUNCTION_ARG_BOUNDARY
22365 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
22366 #undef TARGET_GET_RAW_RESULT_MODE
22367 #define TARGET_GET_RAW_RESULT_MODE mips_get_reg_raw_mode
22368 #undef TARGET_GET_RAW_ARG_MODE
22369 #define TARGET_GET_RAW_ARG_MODE mips_get_reg_raw_mode
22371 #undef TARGET_MODE_REP_EXTENDED
22372 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
22374 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
22375 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
22376 mips_builtin_vectorized_function
22377 #undef TARGET_VECTOR_MODE_SUPPORTED_P
22378 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
22380 #undef TARGET_SCALAR_MODE_SUPPORTED_P
22381 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
22383 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
22384 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
22385 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
22386 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
22387 mips_autovectorize_vector_sizes
22389 #undef TARGET_INIT_BUILTINS
22390 #define TARGET_INIT_BUILTINS mips_init_builtins
22391 #undef TARGET_BUILTIN_DECL
22392 #define TARGET_BUILTIN_DECL mips_builtin_decl
22393 #undef TARGET_EXPAND_BUILTIN
22394 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
22396 #undef TARGET_HAVE_TLS
22397 #define TARGET_HAVE_TLS HAVE_AS_TLS
22399 #undef TARGET_CANNOT_FORCE_CONST_MEM
22400 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
22402 #undef TARGET_LEGITIMATE_CONSTANT_P
22403 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
22405 #undef TARGET_ENCODE_SECTION_INFO
22406 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
22408 #undef TARGET_ATTRIBUTE_TABLE
22409 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
22410 /* All our function attributes are related to how out-of-line copies should
22411 be compiled or called. They don't in themselves prevent inlining. */
22412 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
22413 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
22415 #undef TARGET_EXTRA_LIVE_ON_ENTRY
22416 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
22418 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
22419 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
22420 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
22421 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
22423 #undef TARGET_COMP_TYPE_ATTRIBUTES
22424 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
22426 #ifdef HAVE_AS_DTPRELWORD
22427 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
22428 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
22429 #endif
22430 #undef TARGET_DWARF_REGISTER_SPAN
22431 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
22432 #undef TARGET_DWARF_FRAME_REG_MODE
22433 #define TARGET_DWARF_FRAME_REG_MODE mips_dwarf_frame_reg_mode
22435 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
22436 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
22438 #undef TARGET_LEGITIMATE_ADDRESS_P
22439 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
22441 #undef TARGET_FRAME_POINTER_REQUIRED
22442 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
22444 #undef TARGET_CAN_ELIMINATE
22445 #define TARGET_CAN_ELIMINATE mips_can_eliminate
22447 #undef TARGET_CONDITIONAL_REGISTER_USAGE
22448 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
22450 #undef TARGET_TRAMPOLINE_INIT
22451 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
22453 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
22454 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
22456 #undef TARGET_SHIFT_TRUNCATION_MASK
22457 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
22459 #undef TARGET_PREPARE_PCH_SAVE
22460 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
22462 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
22463 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
22465 #undef TARGET_SCHED_REASSOCIATION_WIDTH
22466 #define TARGET_SCHED_REASSOCIATION_WIDTH mips_sched_reassociation_width
22468 #undef TARGET_CASE_VALUES_THRESHOLD
22469 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
22471 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
22472 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
22474 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
22475 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
22477 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
22478 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
22479 mips_use_by_pieces_infrastructure_p
22481 #undef TARGET_SPILL_CLASS
22482 #define TARGET_SPILL_CLASS mips_spill_class
22483 #undef TARGET_LRA_P
22484 #define TARGET_LRA_P mips_lra_p
22485 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
22486 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class
22488 #undef TARGET_HARD_REGNO_SCRATCH_OK
22489 #define TARGET_HARD_REGNO_SCRATCH_OK mips_hard_regno_scratch_ok
22491 /* The architecture reserves bit 0 for MIPS16 so use bit 1 for descriptors. */
22492 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
22493 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 2
22495 struct gcc_target targetm = TARGET_INITIALIZER;
22497 #include "gt-mips.h"