1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
97 #ifndef ACCUMULATE_OUTGOING_ARGS
98 #define ACCUMULATE_OUTGOING_ARGS 0
101 /* Supply a default definition for PUSH_ARGS. */
104 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
110 /* It is not safe to use ordinary gen_lowpart in combine.
111 Use gen_lowpart_for_combine instead. See comments there. */
112 #define gen_lowpart dont_use_gen_lowpart_you_dummy
114 /* Number of attempts to combine instructions in this function. */
116 static int combine_attempts
;
118 /* Number of attempts that got as far as substitution in this function. */
120 static int combine_merges
;
122 /* Number of instructions combined with added SETs in this function. */
124 static int combine_extras
;
126 /* Number of instructions combined in this function. */
128 static int combine_successes
;
130 /* Totals over entire compilation. */
132 static int total_attempts
, total_merges
, total_extras
, total_successes
;
134 /* Define a default value for REVERSIBLE_CC_MODE.
135 We can never assume that a condition code mode is safe to reverse unless
136 the md tells us so. */
137 #ifndef REVERSIBLE_CC_MODE
138 #define REVERSIBLE_CC_MODE(MODE) 0
141 /* Vector mapping INSN_UIDs to cuids.
142 The cuids are like uids but increase monotonically always.
143 Combine always uses cuids so that it can compare them.
144 But actually renumbering the uids, which we used to do,
145 proves to be a bad idea because it makes it hard to compare
146 the dumps produced by earlier passes with those from later passes. */
148 static int *uid_cuid
;
149 static int max_uid_cuid
;
151 /* Get the cuid of an insn. */
153 #define INSN_CUID(INSN) \
154 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
156 /* Maximum register number, which is the size of the tables below. */
158 static unsigned int combine_max_regno
;
160 /* Record last point of death of (hard or pseudo) register n. */
162 static rtx
*reg_last_death
;
164 /* Record last point of modification of (hard or pseudo) register n. */
166 static rtx
*reg_last_set
;
168 /* Record the cuid of the last insn that invalidated memory
169 (anything that writes memory, and subroutine calls, but not pushes). */
171 static int mem_last_set
;
173 /* Record the cuid of the last CALL_INSN
174 so we can tell whether a potential combination crosses any calls. */
176 static int last_call_cuid
;
178 /* When `subst' is called, this is the insn that is being modified
179 (by combining in a previous insn). The PATTERN of this insn
180 is still the old pattern partially modified and it should not be
181 looked at, but this may be used to examine the successors of the insn
182 to judge whether a simplification is valid. */
184 static rtx subst_insn
;
186 /* This is an insn that belongs before subst_insn, but is not currently
187 on the insn chain. */
189 static rtx subst_prev_insn
;
191 /* This is the lowest CUID that `subst' is currently dealing with.
192 get_last_value will not return a value if the register was set at or
193 after this CUID. If not for this mechanism, we could get confused if
194 I2 or I1 in try_combine were an insn that used the old value of a register
195 to obtain a new value. In that case, we might erroneously get the
196 new value of the register when we wanted the old one. */
198 static int subst_low_cuid
;
200 /* This contains any hard registers that are used in newpat; reg_dead_at_p
201 must consider all these registers to be always live. */
203 static HARD_REG_SET newpat_used_regs
;
205 /* This is an insn to which a LOG_LINKS entry has been added. If this
206 insn is the earlier than I2 or I3, combine should rescan starting at
209 static rtx added_links_insn
;
211 /* Basic block number of the block in which we are performing combines. */
212 static int this_basic_block
;
214 /* A bitmap indicating which blocks had registers go dead at entry.
215 After combine, we'll need to re-do global life analysis with
216 those blocks as starting points. */
217 static sbitmap refresh_blocks
;
218 static int need_refresh
;
220 /* The next group of arrays allows the recording of the last value assigned
221 to (hard or pseudo) register n. We use this information to see if a
222 operation being processed is redundant given a prior operation performed
223 on the register. For example, an `and' with a constant is redundant if
224 all the zero bits are already known to be turned off.
226 We use an approach similar to that used by cse, but change it in the
229 (1) We do not want to reinitialize at each label.
230 (2) It is useful, but not critical, to know the actual value assigned
231 to a register. Often just its form is helpful.
233 Therefore, we maintain the following arrays:
235 reg_last_set_value the last value assigned
236 reg_last_set_label records the value of label_tick when the
237 register was assigned
238 reg_last_set_table_tick records the value of label_tick when a
239 value using the register is assigned
240 reg_last_set_invalid set to non-zero when it is not valid
241 to use the value of this register in some
244 To understand the usage of these tables, it is important to understand
245 the distinction between the value in reg_last_set_value being valid
246 and the register being validly contained in some other expression in the
249 Entry I in reg_last_set_value is valid if it is non-zero, and either
250 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
252 Register I may validly appear in any expression returned for the value
253 of another register if reg_n_sets[i] is 1. It may also appear in the
254 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
255 reg_last_set_invalid[j] is zero.
257 If an expression is found in the table containing a register which may
258 not validly appear in an expression, the register is replaced by
259 something that won't match, (clobber (const_int 0)).
261 reg_last_set_invalid[i] is set non-zero when register I is being assigned
262 to and reg_last_set_table_tick[i] == label_tick. */
264 /* Record last value assigned to (hard or pseudo) register n. */
266 static rtx
*reg_last_set_value
;
268 /* Record the value of label_tick when the value for register n is placed in
269 reg_last_set_value[n]. */
271 static int *reg_last_set_label
;
273 /* Record the value of label_tick when an expression involving register n
274 is placed in reg_last_set_value. */
276 static int *reg_last_set_table_tick
;
278 /* Set non-zero if references to register n in expressions should not be
281 static char *reg_last_set_invalid
;
283 /* Incremented for each label. */
285 static int label_tick
;
287 /* Some registers that are set more than once and used in more than one
288 basic block are nevertheless always set in similar ways. For example,
289 a QImode register may be loaded from memory in two places on a machine
290 where byte loads zero extend.
292 We record in the following array what we know about the nonzero
293 bits of a register, specifically which bits are known to be zero.
295 If an entry is zero, it means that we don't know anything special. */
297 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
299 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
300 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
302 static enum machine_mode nonzero_bits_mode
;
304 /* Nonzero if we know that a register has some leading bits that are always
305 equal to the sign bit. */
307 static unsigned char *reg_sign_bit_copies
;
309 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
310 It is zero while computing them and after combine has completed. This
311 former test prevents propagating values based on previously set values,
312 which can be incorrect if a variable is modified in a loop. */
314 static int nonzero_sign_valid
;
316 /* These arrays are maintained in parallel with reg_last_set_value
317 and are used to store the mode in which the register was last set,
318 the bits that were known to be zero when it was last set, and the
319 number of sign bits copies it was known to have when it was last set. */
321 static enum machine_mode
*reg_last_set_mode
;
322 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
323 static char *reg_last_set_sign_bit_copies
;
325 /* Record one modification to rtl structure
326 to be undone by storing old_contents into *where.
327 is_int is 1 if the contents are an int. */
333 union {rtx r
; unsigned int i
;} old_contents
;
334 union {rtx
*r
; unsigned int *i
;} where
;
337 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
338 num_undo says how many are currently recorded.
340 other_insn is nonzero if we have modified some other insn in the process
341 of working on subst_insn. It must be verified too.
343 previous_undos is the value of undobuf.undos when we started processing
344 this substitution. This will prevent gen_rtx_combine from re-used a piece
345 from the previous expression. Doing so can produce circular rtl
352 struct undo
*previous_undos
;
356 static struct undobuf undobuf
;
358 /* Number of times the pseudo being substituted for
359 was found and replaced. */
361 static int n_occurrences
;
363 static void do_SUBST
PARAMS ((rtx
*, rtx
));
364 static void do_SUBST_INT
PARAMS ((unsigned int *,
366 static void init_reg_last_arrays
PARAMS ((void));
367 static void setup_incoming_promotions
PARAMS ((void));
368 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
369 static int cant_combine_insn_p
PARAMS ((rtx
));
370 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
371 static int sets_function_arg_p
PARAMS ((rtx
));
372 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
373 static int contains_muldiv
PARAMS ((rtx
));
374 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
375 static void undo_all
PARAMS ((void));
376 static void undo_commit
PARAMS ((void));
377 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
378 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
379 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
380 static rtx simplify_if_then_else
PARAMS ((rtx
));
381 static rtx simplify_set
PARAMS ((rtx
));
382 static rtx simplify_logical
PARAMS ((rtx
, int));
383 static rtx expand_compound_operation
PARAMS ((rtx
));
384 static rtx expand_field_assignment
PARAMS ((rtx
));
385 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
386 rtx
, unsigned HOST_WIDE_INT
, int,
388 static rtx extract_left_shift
PARAMS ((rtx
, int));
389 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
390 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
391 unsigned HOST_WIDE_INT
*));
392 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
393 unsigned HOST_WIDE_INT
, rtx
, int));
394 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
395 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
396 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
397 static rtx make_field_assignment
PARAMS ((rtx
));
398 static rtx apply_distributive_law
PARAMS ((rtx
));
399 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
400 unsigned HOST_WIDE_INT
));
401 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
402 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
403 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
404 enum rtx_code
, HOST_WIDE_INT
,
405 enum machine_mode
, int *));
406 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
408 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
409 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
410 static rtx gen_rtx_combine
PARAMS ((enum rtx_code code
, enum machine_mode mode
,
412 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
414 static rtx gen_unary
PARAMS ((enum rtx_code
, enum machine_mode
,
415 enum machine_mode
, rtx
));
416 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
417 static int reversible_comparison_p
PARAMS ((rtx
));
418 static void update_table_tick
PARAMS ((rtx
));
419 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
420 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
421 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
422 static void record_dead_and_set_regs
PARAMS ((rtx
));
423 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
424 static rtx get_last_value
PARAMS ((rtx
));
425 static int use_crosses_set_p
PARAMS ((rtx
, int));
426 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
427 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
428 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
429 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
430 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
431 static void distribute_links
PARAMS ((rtx
));
432 static void mark_used_regs_combine
PARAMS ((rtx
));
433 static int insn_cuid
PARAMS ((rtx
));
434 static void record_promoted_value
PARAMS ((rtx
, rtx
));
436 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
437 insn. The substitution can be undone by undo_all. If INTO is already
438 set to NEWVAL, do not record this change. Because computing NEWVAL might
439 also call SUBST, we have to compute it before we put anything into
443 do_SUBST (into
, newval
)
449 if (oldval
== newval
)
453 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
455 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
459 buf
->old_contents
.r
= oldval
;
462 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
465 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
467 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
468 for the value of a HOST_WIDE_INT value (including CONST_INT) is
472 do_SUBST_INT (into
, newval
)
473 unsigned int *into
, newval
;
476 unsigned int oldval
= *into
;
478 if (oldval
== newval
)
482 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
484 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
488 buf
->old_contents
.i
= oldval
;
491 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
494 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
496 /* Main entry point for combiner. F is the first insn of the function.
497 NREGS is the first unused pseudo-reg number.
499 Return non-zero if the combiner has turned an indirect jump
500 instruction into a direct jump. */
502 combine_instructions (f
, nregs
)
506 register rtx insn
, next
;
511 register rtx links
, nextlinks
;
513 int new_direct_jump_p
= 0;
515 combine_attempts
= 0;
518 combine_successes
= 0;
520 combine_max_regno
= nregs
;
522 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
523 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
525 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
527 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
528 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
530 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
531 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
532 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
534 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
535 reg_last_set_nonzero_bits
536 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
537 reg_last_set_sign_bit_copies
538 = (char *) xmalloc (nregs
* sizeof (char));
540 init_reg_last_arrays ();
542 init_recog_no_volatile ();
544 /* Compute maximum uid value so uid_cuid can be allocated. */
546 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
547 if (INSN_UID (insn
) > i
)
550 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
553 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
555 /* Don't use reg_nonzero_bits when computing it. This can cause problems
556 when, for example, we have j <<= 1 in a loop. */
558 nonzero_sign_valid
= 0;
560 /* Compute the mapping from uids to cuids.
561 Cuids are numbers assigned to insns, like uids,
562 except that cuids increase monotonically through the code.
564 Scan all SETs and see if we can deduce anything about what
565 bits are known to be zero for some registers and how many copies
566 of the sign bit are known to exist for those registers.
568 Also set any known values so that we can use it while searching
569 for what bits are known to be set. */
573 /* We need to initialize it here, because record_dead_and_set_regs may call
575 subst_prev_insn
= NULL_RTX
;
577 setup_incoming_promotions ();
579 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
580 sbitmap_zero (refresh_blocks
);
583 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
585 uid_cuid
[INSN_UID (insn
)] = ++i
;
591 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
593 record_dead_and_set_regs (insn
);
596 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
597 if (REG_NOTE_KIND (links
) == REG_INC
)
598 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
603 if (GET_CODE (insn
) == CODE_LABEL
)
607 nonzero_sign_valid
= 1;
609 /* Now scan all the insns in forward order. */
611 this_basic_block
= -1;
615 init_reg_last_arrays ();
616 setup_incoming_promotions ();
618 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
622 /* If INSN starts a new basic block, update our basic block number. */
623 if (this_basic_block
+ 1 < n_basic_blocks
624 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
627 if (GET_CODE (insn
) == CODE_LABEL
)
630 else if (INSN_P (insn
))
632 /* See if we know about function return values before this
633 insn based upon SUBREG flags. */
634 check_promoted_subreg (insn
, PATTERN (insn
));
636 /* Try this insn with each insn it links back to. */
638 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
639 if ((next
= try_combine (insn
, XEXP (links
, 0),
640 NULL_RTX
, &new_direct_jump_p
)) != 0)
643 /* Try each sequence of three linked insns ending with this one. */
645 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
647 rtx link
= XEXP (links
, 0);
649 /* If the linked insn has been replaced by a note, then there
650 is no point in persuing this chain any further. */
651 if (GET_CODE (link
) == NOTE
)
654 for (nextlinks
= LOG_LINKS (link
);
656 nextlinks
= XEXP (nextlinks
, 1))
657 if ((next
= try_combine (insn
, XEXP (links
, 0),
659 &new_direct_jump_p
)) != 0)
664 /* Try to combine a jump insn that uses CC0
665 with a preceding insn that sets CC0, and maybe with its
666 logical predecessor as well.
667 This is how we make decrement-and-branch insns.
668 We need this special code because data flow connections
669 via CC0 do not get entered in LOG_LINKS. */
671 if (GET_CODE (insn
) == JUMP_INSN
672 && (prev
= prev_nonnote_insn (insn
)) != 0
673 && GET_CODE (prev
) == INSN
674 && sets_cc0_p (PATTERN (prev
)))
676 if ((next
= try_combine (insn
, prev
,
677 NULL_RTX
, &new_direct_jump_p
)) != 0)
680 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
681 nextlinks
= XEXP (nextlinks
, 1))
682 if ((next
= try_combine (insn
, prev
,
684 &new_direct_jump_p
)) != 0)
688 /* Do the same for an insn that explicitly references CC0. */
689 if (GET_CODE (insn
) == INSN
690 && (prev
= prev_nonnote_insn (insn
)) != 0
691 && GET_CODE (prev
) == INSN
692 && sets_cc0_p (PATTERN (prev
))
693 && GET_CODE (PATTERN (insn
)) == SET
694 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
696 if ((next
= try_combine (insn
, prev
,
697 NULL_RTX
, &new_direct_jump_p
)) != 0)
700 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
701 nextlinks
= XEXP (nextlinks
, 1))
702 if ((next
= try_combine (insn
, prev
,
704 &new_direct_jump_p
)) != 0)
708 /* Finally, see if any of the insns that this insn links to
709 explicitly references CC0. If so, try this insn, that insn,
710 and its predecessor if it sets CC0. */
711 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
712 if (GET_CODE (XEXP (links
, 0)) == INSN
713 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
714 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
715 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
716 && GET_CODE (prev
) == INSN
717 && sets_cc0_p (PATTERN (prev
))
718 && (next
= try_combine (insn
, XEXP (links
, 0),
719 prev
, &new_direct_jump_p
)) != 0)
723 /* Try combining an insn with two different insns whose results it
725 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
726 for (nextlinks
= XEXP (links
, 1); nextlinks
;
727 nextlinks
= XEXP (nextlinks
, 1))
728 if ((next
= try_combine (insn
, XEXP (links
, 0),
730 &new_direct_jump_p
)) != 0)
733 if (GET_CODE (insn
) != NOTE
)
734 record_dead_and_set_regs (insn
);
743 compute_bb_for_insn (get_max_uid ());
744 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
749 sbitmap_free (refresh_blocks
);
750 free (reg_nonzero_bits
);
751 free (reg_sign_bit_copies
);
752 free (reg_last_death
);
754 free (reg_last_set_value
);
755 free (reg_last_set_table_tick
);
756 free (reg_last_set_label
);
757 free (reg_last_set_invalid
);
758 free (reg_last_set_mode
);
759 free (reg_last_set_nonzero_bits
);
760 free (reg_last_set_sign_bit_copies
);
764 struct undo
*undo
, *next
;
765 for (undo
= undobuf
.frees
; undo
; undo
= next
)
773 total_attempts
+= combine_attempts
;
774 total_merges
+= combine_merges
;
775 total_extras
+= combine_extras
;
776 total_successes
+= combine_successes
;
778 nonzero_sign_valid
= 0;
780 /* Make recognizer allow volatile MEMs again. */
783 return new_direct_jump_p
;
786 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
789 init_reg_last_arrays ()
791 unsigned int nregs
= combine_max_regno
;
793 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
794 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
795 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
796 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
797 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
798 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
799 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
800 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
801 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
804 /* Set up any promoted values for incoming argument registers. */
807 setup_incoming_promotions ()
809 #ifdef PROMOTE_FUNCTION_ARGS
812 enum machine_mode mode
;
814 rtx first
= get_insns ();
816 #ifndef OUTGOING_REGNO
817 #define OUTGOING_REGNO(N) N
819 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
820 /* Check whether this register can hold an incoming pointer
821 argument. FUNCTION_ARG_REGNO_P tests outgoing register
822 numbers, so translate if necessary due to register windows. */
823 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
824 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
827 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
830 gen_rtx_CLOBBER (mode
, const0_rtx
)));
835 /* Called via note_stores. If X is a pseudo that is narrower than
836 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
838 If we are setting only a portion of X and we can't figure out what
839 portion, assume all bits will be used since we don't know what will
842 Similarly, set how many bits of X are known to be copies of the sign bit
843 at all locations in the function. This is the smallest number implied
847 set_nonzero_bits_and_sign_copies (x
, set
, data
)
850 void *data ATTRIBUTE_UNUSED
;
854 if (GET_CODE (x
) == REG
855 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
856 /* If this register is undefined at the start of the file, we can't
857 say what its contents were. */
858 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
859 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
861 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
863 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
864 reg_sign_bit_copies
[REGNO (x
)] = 1;
868 /* If this is a complex assignment, see if we can convert it into a
869 simple assignment. */
870 set
= expand_field_assignment (set
);
872 /* If this is a simple assignment, or we have a paradoxical SUBREG,
873 set what we know about X. */
875 if (SET_DEST (set
) == x
876 || (GET_CODE (SET_DEST (set
)) == SUBREG
877 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
878 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
879 && SUBREG_REG (SET_DEST (set
)) == x
))
881 rtx src
= SET_SRC (set
);
883 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
884 /* If X is narrower than a word and SRC is a non-negative
885 constant that would appear negative in the mode of X,
886 sign-extend it for use in reg_nonzero_bits because some
887 machines (maybe most) will actually do the sign-extension
888 and this is the conservative approach.
890 ??? For 2.5, try to tighten up the MD files in this regard
891 instead of this kludge. */
893 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
894 && GET_CODE (src
) == CONST_INT
896 && 0 != (INTVAL (src
)
898 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
899 src
= GEN_INT (INTVAL (src
)
900 | ((HOST_WIDE_INT
) (-1)
901 << GET_MODE_BITSIZE (GET_MODE (x
))));
904 reg_nonzero_bits
[REGNO (x
)]
905 |= nonzero_bits (src
, nonzero_bits_mode
);
906 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
907 if (reg_sign_bit_copies
[REGNO (x
)] == 0
908 || reg_sign_bit_copies
[REGNO (x
)] > num
)
909 reg_sign_bit_copies
[REGNO (x
)] = num
;
913 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
914 reg_sign_bit_copies
[REGNO (x
)] = 1;
919 /* See if INSN can be combined into I3. PRED and SUCC are optionally
920 insns that were previously combined into I3 or that will be combined
921 into the merger of INSN and I3.
923 Return 0 if the combination is not allowed for any reason.
925 If the combination is allowed, *PDEST will be set to the single
926 destination of INSN and *PSRC to the single source, and this function
930 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
933 rtx pred ATTRIBUTE_UNUSED
;
938 rtx set
= 0, src
, dest
;
943 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
944 && next_active_insn (succ
) == i3
)
945 : next_active_insn (insn
) == i3
);
947 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
948 or a PARALLEL consisting of such a SET and CLOBBERs.
950 If INSN has CLOBBER parallel parts, ignore them for our processing.
951 By definition, these happen during the execution of the insn. When it
952 is merged with another insn, all bets are off. If they are, in fact,
953 needed and aren't also supplied in I3, they may be added by
954 recog_for_combine. Otherwise, it won't match.
956 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
959 Get the source and destination of INSN. If more than one, can't
962 if (GET_CODE (PATTERN (insn
)) == SET
)
963 set
= PATTERN (insn
);
964 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
965 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
967 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
969 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
971 switch (GET_CODE (elt
))
973 /* This is important to combine floating point insns
976 /* Combining an isolated USE doesn't make sense.
977 We depend here on combinable_i3_pat to reject them. */
978 /* The code below this loop only verifies that the inputs of
979 the SET in INSN do not change. We call reg_set_between_p
980 to verify that the REG in the USE does not change betweeen
982 If the USE in INSN was for a pseudo register, the matching
983 insn pattern will likely match any register; combining this
984 with any other USE would only be safe if we knew that the
985 used registers have identical values, or if there was
986 something to tell them apart, e.g. different modes. For
987 now, we forgo such compilcated tests and simply disallow
988 combining of USES of pseudo registers with any other USE. */
989 if (GET_CODE (XEXP (elt
, 0)) == REG
990 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
992 rtx i3pat
= PATTERN (i3
);
993 int i
= XVECLEN (i3pat
, 0) - 1;
994 unsigned int regno
= REGNO (XEXP (elt
, 0));
998 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1000 if (GET_CODE (i3elt
) == USE
1001 && GET_CODE (XEXP (i3elt
, 0)) == REG
1002 && (REGNO (XEXP (i3elt
, 0)) == regno
1003 ? reg_set_between_p (XEXP (elt
, 0),
1004 PREV_INSN (insn
), i3
)
1005 : regno
>= FIRST_PSEUDO_REGISTER
))
1012 /* We can ignore CLOBBERs. */
1017 /* Ignore SETs whose result isn't used but not those that
1018 have side-effects. */
1019 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1020 && ! side_effects_p (elt
))
1023 /* If we have already found a SET, this is a second one and
1024 so we cannot combine with this insn. */
1032 /* Anything else means we can't combine. */
1038 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1039 so don't do anything with it. */
1040 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1049 set
= expand_field_assignment (set
);
1050 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1052 /* Don't eliminate a store in the stack pointer. */
1053 if (dest
== stack_pointer_rtx
1054 /* If we couldn't eliminate a field assignment, we can't combine. */
1055 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1056 /* Don't combine with an insn that sets a register to itself if it has
1057 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1058 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1059 /* Can't merge an ASM_OPERANDS. */
1060 || GET_CODE (src
) == ASM_OPERANDS
1061 /* Can't merge a function call. */
1062 || GET_CODE (src
) == CALL
1063 /* Don't eliminate a function call argument. */
1064 || (GET_CODE (i3
) == CALL_INSN
1065 && (find_reg_fusage (i3
, USE
, dest
)
1066 || (GET_CODE (dest
) == REG
1067 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1068 && global_regs
[REGNO (dest
)])))
1069 /* Don't substitute into an incremented register. */
1070 || FIND_REG_INC_NOTE (i3
, dest
)
1071 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1073 /* Don't combine the end of a libcall into anything. */
1074 /* ??? This gives worse code, and appears to be unnecessary, since no
1075 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1076 use REG_RETVAL notes for noconflict blocks, but other code here
1077 makes sure that those insns don't disappear. */
1078 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1080 /* Make sure that DEST is not used after SUCC but before I3. */
1081 || (succ
&& ! all_adjacent
1082 && reg_used_between_p (dest
, succ
, i3
))
1083 /* Make sure that the value that is to be substituted for the register
1084 does not use any registers whose values alter in between. However,
1085 If the insns are adjacent, a use can't cross a set even though we
1086 think it might (this can happen for a sequence of insns each setting
1087 the same destination; reg_last_set of that register might point to
1088 a NOTE). If INSN has a REG_EQUIV note, the register is always
1089 equivalent to the memory so the substitution is valid even if there
1090 are intervening stores. Also, don't move a volatile asm or
1091 UNSPEC_VOLATILE across any other insns. */
1093 && (((GET_CODE (src
) != MEM
1094 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1095 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1096 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1097 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1098 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1099 better register allocation by not doing the combine. */
1100 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1101 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1102 /* Don't combine across a CALL_INSN, because that would possibly
1103 change whether the life span of some REGs crosses calls or not,
1104 and it is a pain to update that information.
1105 Exception: if source is a constant, moving it later can't hurt.
1106 Accept that special case, because it helps -fforce-addr a lot. */
1107 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1110 /* DEST must either be a REG or CC0. */
1111 if (GET_CODE (dest
) == REG
)
1113 /* If register alignment is being enforced for multi-word items in all
1114 cases except for parameters, it is possible to have a register copy
1115 insn referencing a hard register that is not allowed to contain the
1116 mode being copied and which would not be valid as an operand of most
1117 insns. Eliminate this problem by not combining with such an insn.
1119 Also, on some machines we don't want to extend the life of a hard
1122 if (GET_CODE (src
) == REG
1123 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1124 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1125 /* Don't extend the life of a hard register unless it is
1126 user variable (if we have few registers) or it can't
1127 fit into the desired register (meaning something special
1129 Also avoid substituting a return register into I3, because
1130 reload can't handle a conflict with constraints of other
1132 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1133 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1136 else if (GET_CODE (dest
) != CC0
)
1139 /* Don't substitute for a register intended as a clobberable operand.
1140 Similarly, don't substitute an expression containing a register that
1141 will be clobbered in I3. */
1142 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1143 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1144 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1145 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1147 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1150 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1151 or not), reject, unless nothing volatile comes between it and I3 */
1153 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1155 /* Make sure succ doesn't contain a volatile reference. */
1156 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1159 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1160 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1164 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1165 to be an explicit register variable, and was chosen for a reason. */
1167 if (GET_CODE (src
) == ASM_OPERANDS
1168 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1171 /* If there are any volatile insns between INSN and I3, reject, because
1172 they might affect machine state. */
1174 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1175 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1178 /* If INSN or I2 contains an autoincrement or autodecrement,
1179 make sure that register is not used between there and I3,
1180 and not already used in I3 either.
1181 Also insist that I3 not be a jump; if it were one
1182 and the incremented register were spilled, we would lose. */
1185 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1186 if (REG_NOTE_KIND (link
) == REG_INC
1187 && (GET_CODE (i3
) == JUMP_INSN
1188 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1189 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1194 /* Don't combine an insn that follows a CC0-setting insn.
1195 An insn that uses CC0 must not be separated from the one that sets it.
1196 We do, however, allow I2 to follow a CC0-setting insn if that insn
1197 is passed as I1; in that case it will be deleted also.
1198 We also allow combining in this case if all the insns are adjacent
1199 because that would leave the two CC0 insns adjacent as well.
1200 It would be more logical to test whether CC0 occurs inside I1 or I2,
1201 but that would be much slower, and this ought to be equivalent. */
1203 p
= prev_nonnote_insn (insn
);
1204 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1209 /* If we get here, we have passed all the tests and the combination is
1218 /* Check if PAT is an insn - or a part of it - used to set up an
1219 argument for a function in a hard register. */
1222 sets_function_arg_p (pat
)
1228 switch (GET_CODE (pat
))
1231 return sets_function_arg_p (PATTERN (pat
));
1234 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1235 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1241 inner_dest
= SET_DEST (pat
);
1242 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1243 || GET_CODE (inner_dest
) == SUBREG
1244 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1245 inner_dest
= XEXP (inner_dest
, 0);
1247 return (GET_CODE (inner_dest
) == REG
1248 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1249 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1258 /* LOC is the location within I3 that contains its pattern or the component
1259 of a PARALLEL of the pattern. We validate that it is valid for combining.
1261 One problem is if I3 modifies its output, as opposed to replacing it
1262 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1263 so would produce an insn that is not equivalent to the original insns.
1267 (set (reg:DI 101) (reg:DI 100))
1268 (set (subreg:SI (reg:DI 101) 0) <foo>)
1270 This is NOT equivalent to:
1272 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1273 (set (reg:DI 101) (reg:DI 100))])
1275 Not only does this modify 100 (in which case it might still be valid
1276 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1278 We can also run into a problem if I2 sets a register that I1
1279 uses and I1 gets directly substituted into I3 (not via I2). In that
1280 case, we would be getting the wrong value of I2DEST into I3, so we
1281 must reject the combination. This case occurs when I2 and I1 both
1282 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1283 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1284 of a SET must prevent combination from occurring.
1286 Before doing the above check, we first try to expand a field assignment
1287 into a set of logical operations.
1289 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1290 we place a register that is both set and used within I3. If more than one
1291 such register is detected, we fail.
1293 Return 1 if the combination is valid, zero otherwise. */
1296 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1302 rtx
*pi3dest_killed
;
1306 if (GET_CODE (x
) == SET
)
1308 rtx set
= expand_field_assignment (x
);
1309 rtx dest
= SET_DEST (set
);
1310 rtx src
= SET_SRC (set
);
1311 rtx inner_dest
= dest
;
1314 rtx inner_src
= src
;
1319 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1320 || GET_CODE (inner_dest
) == SUBREG
1321 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1322 inner_dest
= XEXP (inner_dest
, 0);
1324 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1327 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1328 || GET_CODE (inner_src
) == SUBREG
1329 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1330 inner_src
= XEXP (inner_src
, 0);
1332 /* If it is better that two different modes keep two different pseudos,
1333 avoid combining them. This avoids producing the following pattern
1335 (set (subreg:SI (reg/v:QI 21) 0)
1336 (lshiftrt:SI (reg/v:SI 20)
1338 If that were made, reload could not handle the pair of
1339 reg 20/21, since it would try to get any GENERAL_REGS
1340 but some of them don't handle QImode. */
1342 if (rtx_equal_p (inner_src
, i2dest
)
1343 && GET_CODE (inner_dest
) == REG
1344 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1348 /* Check for the case where I3 modifies its output, as
1350 if ((inner_dest
!= dest
1351 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1352 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1354 /* This is the same test done in can_combine_p except we can't test
1355 all_adjacent; we don't have to, since this instruction will stay
1356 in place, thus we are not considering increasing the lifetime of
1359 Also, if this insn sets a function argument, combining it with
1360 something that might need a spill could clobber a previous
1361 function argument; the all_adjacent test in can_combine_p also
1362 checks this; here, we do a more specific test for this case. */
1364 || (GET_CODE (inner_dest
) == REG
1365 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1366 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1367 GET_MODE (inner_dest
))))
1368 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1371 /* If DEST is used in I3, it is being killed in this insn,
1372 so record that for later.
1373 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1374 STACK_POINTER_REGNUM, since these are always considered to be
1375 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1376 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1377 && reg_referenced_p (dest
, PATTERN (i3
))
1378 && REGNO (dest
) != FRAME_POINTER_REGNUM
1379 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1380 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1382 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1383 && (REGNO (dest
) != ARG_POINTER_REGNUM
1384 || ! fixed_regs
[REGNO (dest
)])
1386 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1388 if (*pi3dest_killed
)
1391 *pi3dest_killed
= dest
;
1395 else if (GET_CODE (x
) == PARALLEL
)
1399 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1400 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1401 i1_not_in_src
, pi3dest_killed
))
1408 /* Return 1 if X is an arithmetic expression that contains a multiplication
1409 and division. We don't count multiplications by powers of two here. */
1415 switch (GET_CODE (x
))
1417 case MOD
: case DIV
: case UMOD
: case UDIV
:
1421 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1422 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1424 switch (GET_RTX_CLASS (GET_CODE (x
)))
1426 case 'c': case '<': case '2':
1427 return contains_muldiv (XEXP (x
, 0))
1428 || contains_muldiv (XEXP (x
, 1));
1431 return contains_muldiv (XEXP (x
, 0));
1439 /* Determine whether INSN can be used in a combination. Return nonzero if
1440 not. This is used in try_combine to detect early some cases where we
1441 can't perform combinations. */
1444 cant_combine_insn_p (insn
)
1450 /* If this isn't really an insn, we can't do anything.
1451 This can occur when flow deletes an insn that it has merged into an
1452 auto-increment address. */
1453 if (! INSN_P (insn
))
1456 /* Never combine loads and stores involving hard regs. The register
1457 allocator can usually handle such reg-reg moves by tying. If we allow
1458 the combiner to make substitutions of hard regs, we risk aborting in
1459 reload on machines that have SMALL_REGISTER_CLASSES.
1460 As an exception, we allow combinations involving fixed regs; these are
1461 not available to the register allocator so there's no risk involved. */
1463 set
= single_set (insn
);
1466 src
= SET_SRC (set
);
1467 dest
= SET_DEST (set
);
1468 if (GET_CODE (src
) == SUBREG
)
1469 src
= SUBREG_REG (src
);
1470 if (GET_CODE (dest
) == SUBREG
)
1471 dest
= SUBREG_REG (dest
);
1472 if (REG_P (src
) && REG_P (dest
)
1473 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1474 && ! fixed_regs
[REGNO (src
)])
1475 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1476 && ! fixed_regs
[REGNO (dest
)])))
1482 /* Try to combine the insns I1 and I2 into I3.
1483 Here I1 and I2 appear earlier than I3.
1484 I1 can be zero; then we combine just I2 into I3.
1486 It we are combining three insns and the resulting insn is not recognized,
1487 try splitting it into two insns. If that happens, I2 and I3 are retained
1488 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1491 Return 0 if the combination does not work. Then nothing is changed.
1492 If we did the combination, return the insn at which combine should
1495 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1496 new direct jump instruction. */
1499 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1500 register rtx i3
, i2
, i1
;
1501 register int *new_direct_jump_p
;
1503 /* New patterns for I3 and I2, respectively. */
1504 rtx newpat
, newi2pat
= 0;
1505 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1506 int added_sets_1
, added_sets_2
;
1507 /* Total number of SETs to put into I3. */
1509 /* Nonzero is I2's body now appears in I3. */
1511 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1512 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1513 /* Contains I3 if the destination of I3 is used in its source, which means
1514 that the old life of I3 is being killed. If that usage is placed into
1515 I2 and not in I3, a REG_DEAD note must be made. */
1516 rtx i3dest_killed
= 0;
1517 /* SET_DEST and SET_SRC of I2 and I1. */
1518 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1519 /* PATTERN (I2), or a copy of it in certain cases. */
1521 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1522 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1523 int i1_feeds_i3
= 0;
1524 /* Notes that must be added to REG_NOTES in I3 and I2. */
1525 rtx new_i3_notes
, new_i2_notes
;
1526 /* Notes that we substituted I3 into I2 instead of the normal case. */
1527 int i3_subst_into_i2
= 0;
1528 /* Notes that I1, I2 or I3 is a MULT operation. */
1536 /* Exit early if one of the insns involved can't be used for
1538 if (cant_combine_insn_p (i3
)
1539 || cant_combine_insn_p (i2
)
1540 || (i1
&& cant_combine_insn_p (i1
))
1541 /* We also can't do anything if I3 has a
1542 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1545 /* ??? This gives worse code, and appears to be unnecessary, since no
1546 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1547 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1553 undobuf
.other_insn
= 0;
1555 /* Reset the hard register usage information. */
1556 CLEAR_HARD_REG_SET (newpat_used_regs
);
1558 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1559 code below, set I1 to be the earlier of the two insns. */
1560 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1561 temp
= i1
, i1
= i2
, i2
= temp
;
1563 added_links_insn
= 0;
1565 /* First check for one important special-case that the code below will
1566 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1567 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1568 we may be able to replace that destination with the destination of I3.
1569 This occurs in the common code where we compute both a quotient and
1570 remainder into a structure, in which case we want to do the computation
1571 directly into the structure to avoid register-register copies.
1573 We make very conservative checks below and only try to handle the
1574 most common cases of this. For example, we only handle the case
1575 where I2 and I3 are adjacent to avoid making difficult register
1578 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1579 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1580 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1581 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1582 && GET_CODE (PATTERN (i2
)) == PARALLEL
1583 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1584 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1585 below would need to check what is inside (and reg_overlap_mentioned_p
1586 doesn't support those codes anyway). Don't allow those destinations;
1587 the resulting insn isn't likely to be recognized anyway. */
1588 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1589 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1590 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1591 SET_DEST (PATTERN (i3
)))
1592 && next_real_insn (i2
) == i3
)
1594 rtx p2
= PATTERN (i2
);
1596 /* Make sure that the destination of I3,
1597 which we are going to substitute into one output of I2,
1598 is not used within another output of I2. We must avoid making this:
1599 (parallel [(set (mem (reg 69)) ...)
1600 (set (reg 69) ...)])
1601 which is not well-defined as to order of actions.
1602 (Besides, reload can't handle output reloads for this.)
1604 The problem can also happen if the dest of I3 is a memory ref,
1605 if another dest in I2 is an indirect memory ref. */
1606 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1607 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1608 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1609 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1610 SET_DEST (XVECEXP (p2
, 0, i
))))
1613 if (i
== XVECLEN (p2
, 0))
1614 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1615 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1616 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1617 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1622 subst_low_cuid
= INSN_CUID (i2
);
1624 added_sets_2
= added_sets_1
= 0;
1625 i2dest
= SET_SRC (PATTERN (i3
));
1627 /* Replace the dest in I2 with our dest and make the resulting
1628 insn the new pattern for I3. Then skip to where we
1629 validate the pattern. Everything was set up above. */
1630 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1631 SET_DEST (PATTERN (i3
)));
1634 i3_subst_into_i2
= 1;
1635 goto validate_replacement
;
1639 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1640 one of those words to another constant, merge them by making a new
1643 && (temp
= single_set (i2
)) != 0
1644 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1645 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1646 && GET_CODE (SET_DEST (temp
)) == REG
1647 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1648 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1649 && GET_CODE (PATTERN (i3
)) == SET
1650 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1651 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1652 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1653 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1654 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1656 HOST_WIDE_INT lo
, hi
;
1658 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1659 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1662 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1663 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1666 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1667 lo
= INTVAL (SET_SRC (PATTERN (i3
)));
1669 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1673 subst_low_cuid
= INSN_CUID (i2
);
1674 added_sets_2
= added_sets_1
= 0;
1675 i2dest
= SET_DEST (temp
);
1677 SUBST (SET_SRC (temp
),
1678 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1680 newpat
= PATTERN (i2
);
1681 i3_subst_into_i2
= 1;
1682 goto validate_replacement
;
1686 /* If we have no I1 and I2 looks like:
1687 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1689 make up a dummy I1 that is
1692 (set (reg:CC X) (compare:CC Y (const_int 0)))
1694 (We can ignore any trailing CLOBBERs.)
1696 This undoes a previous combination and allows us to match a branch-and-
1699 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1700 && XVECLEN (PATTERN (i2
), 0) >= 2
1701 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1702 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1704 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1705 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1706 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1707 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1708 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1709 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1711 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1712 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1717 /* We make I1 with the same INSN_UID as I2. This gives it
1718 the same INSN_CUID for value tracking. Our fake I1 will
1719 never appear in the insn stream so giving it the same INSN_UID
1720 as I2 will not cause a problem. */
1722 subst_prev_insn
= i1
1723 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1724 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1727 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1728 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1729 SET_DEST (PATTERN (i1
)));
1734 /* Verify that I2 and I1 are valid for combining. */
1735 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1736 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1742 /* Record whether I2DEST is used in I2SRC and similarly for the other
1743 cases. Knowing this will help in register status updating below. */
1744 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1745 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1746 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1748 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1750 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1752 /* Ensure that I3's pattern can be the destination of combines. */
1753 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1754 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1761 /* See if any of the insns is a MULT operation. Unless one is, we will
1762 reject a combination that is, since it must be slower. Be conservative
1764 if (GET_CODE (i2src
) == MULT
1765 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1766 || (GET_CODE (PATTERN (i3
)) == SET
1767 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1770 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1771 We used to do this EXCEPT in one case: I3 has a post-inc in an
1772 output operand. However, that exception can give rise to insns like
1774 which is a famous insn on the PDP-11 where the value of r3 used as the
1775 source was model-dependent. Avoid this sort of thing. */
1778 if (!(GET_CODE (PATTERN (i3
)) == SET
1779 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1780 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1781 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1782 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1783 /* It's not the exception. */
1786 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1787 if (REG_NOTE_KIND (link
) == REG_INC
1788 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1790 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1797 /* See if the SETs in I1 or I2 need to be kept around in the merged
1798 instruction: whenever the value set there is still needed past I3.
1799 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1801 For the SET in I1, we have two cases: If I1 and I2 independently
1802 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1803 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1804 in I1 needs to be kept around unless I1DEST dies or is set in either
1805 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1806 I1DEST. If so, we know I1 feeds into I2. */
1808 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1811 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1812 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1814 /* If the set in I2 needs to be kept around, we must make a copy of
1815 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1816 PATTERN (I2), we are only substituting for the original I1DEST, not into
1817 an already-substituted copy. This also prevents making self-referential
1818 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1821 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1822 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1826 i2pat
= copy_rtx (i2pat
);
1830 /* Substitute in the latest insn for the regs set by the earlier ones. */
1832 maxreg
= max_reg_num ();
1836 /* It is possible that the source of I2 or I1 may be performing an
1837 unneeded operation, such as a ZERO_EXTEND of something that is known
1838 to have the high part zero. Handle that case by letting subst look at
1839 the innermost one of them.
1841 Another way to do this would be to have a function that tries to
1842 simplify a single insn instead of merging two or more insns. We don't
1843 do this because of the potential of infinite loops and because
1844 of the potential extra memory required. However, doing it the way
1845 we are is a bit of a kludge and doesn't catch all cases.
1847 But only do this if -fexpensive-optimizations since it slows things down
1848 and doesn't usually win. */
1850 if (flag_expensive_optimizations
)
1852 /* Pass pc_rtx so no substitutions are done, just simplifications.
1853 The cases that we are interested in here do not involve the few
1854 cases were is_replaced is checked. */
1857 subst_low_cuid
= INSN_CUID (i1
);
1858 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1862 subst_low_cuid
= INSN_CUID (i2
);
1863 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1866 undobuf
.previous_undos
= undobuf
.undos
;
1870 /* Many machines that don't use CC0 have insns that can both perform an
1871 arithmetic operation and set the condition code. These operations will
1872 be represented as a PARALLEL with the first element of the vector
1873 being a COMPARE of an arithmetic operation with the constant zero.
1874 The second element of the vector will set some pseudo to the result
1875 of the same arithmetic operation. If we simplify the COMPARE, we won't
1876 match such a pattern and so will generate an extra insn. Here we test
1877 for this case, where both the comparison and the operation result are
1878 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1879 I2SRC. Later we will make the PARALLEL that contains I2. */
1881 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1882 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1883 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1884 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1886 #ifdef EXTRA_CC_MODES
1888 enum machine_mode compare_mode
;
1891 newpat
= PATTERN (i3
);
1892 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1896 #ifdef EXTRA_CC_MODES
1897 /* See if a COMPARE with the operand we substituted in should be done
1898 with the mode that is currently being used. If not, do the same
1899 processing we do in `subst' for a SET; namely, if the destination
1900 is used only once, try to replace it with a register of the proper
1901 mode and also replace the COMPARE. */
1902 if (undobuf
.other_insn
== 0
1903 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1904 &undobuf
.other_insn
))
1905 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1907 != GET_MODE (SET_DEST (newpat
))))
1909 unsigned int regno
= REGNO (SET_DEST (newpat
));
1910 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1912 if (regno
< FIRST_PSEUDO_REGISTER
1913 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1914 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1916 if (regno
>= FIRST_PSEUDO_REGISTER
)
1917 SUBST (regno_reg_rtx
[regno
], new_dest
);
1919 SUBST (SET_DEST (newpat
), new_dest
);
1920 SUBST (XEXP (*cc_use
, 0), new_dest
);
1921 SUBST (SET_SRC (newpat
),
1922 gen_rtx_combine (COMPARE
, compare_mode
,
1923 i2src
, const0_rtx
));
1926 undobuf
.other_insn
= 0;
1933 n_occurrences
= 0; /* `subst' counts here */
1935 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1936 need to make a unique copy of I2SRC each time we substitute it
1937 to avoid self-referential rtl. */
1939 subst_low_cuid
= INSN_CUID (i2
);
1940 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1941 ! i1_feeds_i3
&& i1dest_in_i1src
);
1942 undobuf
.previous_undos
= undobuf
.undos
;
1944 /* Record whether i2's body now appears within i3's body. */
1945 i2_is_used
= n_occurrences
;
1948 /* If we already got a failure, don't try to do more. Otherwise,
1949 try to substitute in I1 if we have it. */
1951 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1953 /* Before we can do this substitution, we must redo the test done
1954 above (see detailed comments there) that ensures that I1DEST
1955 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1957 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1965 subst_low_cuid
= INSN_CUID (i1
);
1966 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1967 undobuf
.previous_undos
= undobuf
.undos
;
1970 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1971 to count all the ways that I2SRC and I1SRC can be used. */
1972 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1973 && i2_is_used
+ added_sets_2
> 1)
1974 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1975 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1977 /* Fail if we tried to make a new register (we used to abort, but there's
1978 really no reason to). */
1979 || max_reg_num () != maxreg
1980 /* Fail if we couldn't do something and have a CLOBBER. */
1981 || GET_CODE (newpat
) == CLOBBER
1982 /* Fail if this new pattern is a MULT and we didn't have one before
1983 at the outer level. */
1984 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1991 /* If the actions of the earlier insns must be kept
1992 in addition to substituting them into the latest one,
1993 we must make a new PARALLEL for the latest insn
1994 to hold additional the SETs. */
1996 if (added_sets_1
|| added_sets_2
)
2000 if (GET_CODE (newpat
) == PARALLEL
)
2002 rtvec old
= XVEC (newpat
, 0);
2003 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2004 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2005 bcopy ((char *) &old
->elem
[0], (char *) XVEC (newpat
, 0)->elem
,
2006 sizeof (old
->elem
[0]) * old
->num_elem
);
2011 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2012 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2013 XVECEXP (newpat
, 0, 0) = old
;
2017 XVECEXP (newpat
, 0, --total_sets
)
2018 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2019 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2023 /* If there is no I1, use I2's body as is. We used to also not do
2024 the subst call below if I2 was substituted into I3,
2025 but that could lose a simplification. */
2027 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2029 /* See comment where i2pat is assigned. */
2030 XVECEXP (newpat
, 0, --total_sets
)
2031 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2035 /* We come here when we are replacing a destination in I2 with the
2036 destination of I3. */
2037 validate_replacement
:
2039 /* Note which hard regs this insn has as inputs. */
2040 mark_used_regs_combine (newpat
);
2042 /* Is the result of combination a valid instruction? */
2043 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2045 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2046 the second SET's destination is a register that is unused. In that case,
2047 we just need the first SET. This can occur when simplifying a divmod
2048 insn. We *must* test for this case here because the code below that
2049 splits two independent SETs doesn't handle this case correctly when it
2050 updates the register status. Also check the case where the first
2051 SET's destination is unused. That would not cause incorrect code, but
2052 does cause an unneeded insn to remain. */
2054 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2055 && XVECLEN (newpat
, 0) == 2
2056 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2057 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2058 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2059 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2060 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2061 && asm_noperands (newpat
) < 0)
2063 newpat
= XVECEXP (newpat
, 0, 0);
2064 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2067 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2068 && XVECLEN (newpat
, 0) == 2
2069 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2070 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2071 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2072 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2073 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2074 && asm_noperands (newpat
) < 0)
2076 newpat
= XVECEXP (newpat
, 0, 1);
2077 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2080 /* If we were combining three insns and the result is a simple SET
2081 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2082 insns. There are two ways to do this. It can be split using a
2083 machine-specific method (like when you have an addition of a large
2084 constant) or by combine in the function find_split_point. */
2086 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2087 && asm_noperands (newpat
) < 0)
2089 rtx m_split
, *split
;
2090 rtx ni2dest
= i2dest
;
2092 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2093 use I2DEST as a scratch register will help. In the latter case,
2094 convert I2DEST to the mode of the source of NEWPAT if we can. */
2096 m_split
= split_insns (newpat
, i3
);
2098 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2099 inputs of NEWPAT. */
2101 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2102 possible to try that as a scratch reg. This would require adding
2103 more code to make it work though. */
2105 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2107 /* If I2DEST is a hard register or the only use of a pseudo,
2108 we can change its mode. */
2109 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2110 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2111 && GET_CODE (i2dest
) == REG
2112 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2113 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2114 && ! REG_USERVAR_P (i2dest
))))
2115 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2118 m_split
= split_insns (gen_rtx_PARALLEL
2120 gen_rtvec (2, newpat
,
2121 gen_rtx_CLOBBER (VOIDmode
,
2126 if (m_split
&& GET_CODE (m_split
) != SEQUENCE
)
2128 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2129 if (insn_code_number
>= 0)
2132 else if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2133 && XVECLEN (m_split
, 0) == 2
2134 && (next_real_insn (i2
) == i3
2135 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2139 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2140 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2142 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2143 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2145 /* In case we changed the mode of I2DEST, replace it in the
2146 pseudo-register table here. We can't do it above in case this
2147 code doesn't get executed and we do a split the other way. */
2149 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2150 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2152 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2154 /* If I2 or I3 has multiple SETs, we won't know how to track
2155 register status, so don't use these insns. If I2's destination
2156 is used between I2 and I3, we also can't use these insns. */
2158 if (i2_code_number
>= 0 && i2set
&& i3set
2159 && (next_real_insn (i2
) == i3
2160 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2161 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2163 if (insn_code_number
>= 0)
2166 /* It is possible that both insns now set the destination of I3.
2167 If so, we must show an extra use of it. */
2169 if (insn_code_number
>= 0)
2171 rtx new_i3_dest
= SET_DEST (i3set
);
2172 rtx new_i2_dest
= SET_DEST (i2set
);
2174 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2175 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2176 || GET_CODE (new_i3_dest
) == SUBREG
)
2177 new_i3_dest
= XEXP (new_i3_dest
, 0);
2179 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2180 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2181 || GET_CODE (new_i2_dest
) == SUBREG
)
2182 new_i2_dest
= XEXP (new_i2_dest
, 0);
2184 if (GET_CODE (new_i3_dest
) == REG
2185 && GET_CODE (new_i2_dest
) == REG
2186 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2187 REG_N_SETS (REGNO (new_i2_dest
))++;
2191 /* If we can split it and use I2DEST, go ahead and see if that
2192 helps things be recognized. Verify that none of the registers
2193 are set between I2 and I3. */
2194 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2196 && GET_CODE (i2dest
) == REG
2198 /* We need I2DEST in the proper mode. If it is a hard register
2199 or the only use of a pseudo, we can change its mode. */
2200 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2201 || GET_MODE (*split
) == VOIDmode
2202 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2203 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2204 && ! REG_USERVAR_P (i2dest
)))
2205 && (next_real_insn (i2
) == i3
2206 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2207 /* We can't overwrite I2DEST if its value is still used by
2209 && ! reg_referenced_p (i2dest
, newpat
))
2211 rtx newdest
= i2dest
;
2212 enum rtx_code split_code
= GET_CODE (*split
);
2213 enum machine_mode split_mode
= GET_MODE (*split
);
2215 /* Get NEWDEST as a register in the proper mode. We have already
2216 validated that we can do this. */
2217 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2219 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2221 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2222 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2225 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2226 an ASHIFT. This can occur if it was inside a PLUS and hence
2227 appeared to be a memory address. This is a kludge. */
2228 if (split_code
== MULT
2229 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2230 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2232 SUBST (*split
, gen_rtx_combine (ASHIFT
, split_mode
,
2233 XEXP (*split
, 0), GEN_INT (i
)));
2234 /* Update split_code because we may not have a multiply
2236 split_code
= GET_CODE (*split
);
2239 #ifdef INSN_SCHEDULING
2240 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2241 be written as a ZERO_EXTEND. */
2242 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2243 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, split_mode
,
2247 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
2248 SUBST (*split
, newdest
);
2249 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2251 /* If the split point was a MULT and we didn't have one before,
2252 don't use one now. */
2253 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2254 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2258 /* Check for a case where we loaded from memory in a narrow mode and
2259 then sign extended it, but we need both registers. In that case,
2260 we have a PARALLEL with both loads from the same memory location.
2261 We can split this into a load from memory followed by a register-register
2262 copy. This saves at least one insn, more if register allocation can
2265 We cannot do this if the destination of the second assignment is
2266 a register that we have already assumed is zero-extended. Similarly
2267 for a SUBREG of such a register. */
2269 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2270 && GET_CODE (newpat
) == PARALLEL
2271 && XVECLEN (newpat
, 0) == 2
2272 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2273 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2274 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2275 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2276 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2277 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2279 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2280 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2281 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2282 (GET_CODE (temp
) == REG
2283 && reg_nonzero_bits
[REGNO (temp
)] != 0
2284 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2285 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2286 && (reg_nonzero_bits
[REGNO (temp
)]
2287 != GET_MODE_MASK (word_mode
))))
2288 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2289 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2290 (GET_CODE (temp
) == REG
2291 && reg_nonzero_bits
[REGNO (temp
)] != 0
2292 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2293 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2294 && (reg_nonzero_bits
[REGNO (temp
)]
2295 != GET_MODE_MASK (word_mode
)))))
2296 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2297 SET_SRC (XVECEXP (newpat
, 0, 1)))
2298 && ! find_reg_note (i3
, REG_UNUSED
,
2299 SET_DEST (XVECEXP (newpat
, 0, 0))))
2303 newi2pat
= XVECEXP (newpat
, 0, 0);
2304 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2305 newpat
= XVECEXP (newpat
, 0, 1);
2306 SUBST (SET_SRC (newpat
),
2307 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2308 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2310 if (i2_code_number
>= 0)
2311 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2313 if (insn_code_number
>= 0)
2318 /* If we will be able to accept this, we have made a change to the
2319 destination of I3. This can invalidate a LOG_LINKS pointing
2320 to I3. No other part of combine.c makes such a transformation.
2322 The new I3 will have a destination that was previously the
2323 destination of I1 or I2 and which was used in i2 or I3. Call
2324 distribute_links to make a LOG_LINK from the next use of
2325 that destination. */
2327 PATTERN (i3
) = newpat
;
2328 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2330 /* I3 now uses what used to be its destination and which is
2331 now I2's destination. That means we need a LOG_LINK from
2332 I3 to I2. But we used to have one, so we still will.
2334 However, some later insn might be using I2's dest and have
2335 a LOG_LINK pointing at I3. We must remove this link.
2336 The simplest way to remove the link is to point it at I1,
2337 which we know will be a NOTE. */
2339 for (insn
= NEXT_INSN (i3
);
2340 insn
&& (this_basic_block
== n_basic_blocks
- 1
2341 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2342 insn
= NEXT_INSN (insn
))
2344 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2346 for (link
= LOG_LINKS (insn
); link
;
2347 link
= XEXP (link
, 1))
2348 if (XEXP (link
, 0) == i3
)
2349 XEXP (link
, 0) = i1
;
2357 /* Similarly, check for a case where we have a PARALLEL of two independent
2358 SETs but we started with three insns. In this case, we can do the sets
2359 as two separate insns. This case occurs when some SET allows two
2360 other insns to combine, but the destination of that SET is still live. */
2362 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2363 && GET_CODE (newpat
) == PARALLEL
2364 && XVECLEN (newpat
, 0) == 2
2365 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2366 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2367 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2368 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2369 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2370 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2371 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2373 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2374 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2375 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2376 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2377 XVECEXP (newpat
, 0, 0))
2378 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2379 XVECEXP (newpat
, 0, 1))
2380 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2381 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2383 /* Normally, it doesn't matter which of the two is done first,
2384 but it does if one references cc0. In that case, it has to
2387 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2389 newi2pat
= XVECEXP (newpat
, 0, 0);
2390 newpat
= XVECEXP (newpat
, 0, 1);
2395 newi2pat
= XVECEXP (newpat
, 0, 1);
2396 newpat
= XVECEXP (newpat
, 0, 0);
2399 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2401 if (i2_code_number
>= 0)
2402 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2405 /* If it still isn't recognized, fail and change things back the way they
2407 if ((insn_code_number
< 0
2408 /* Is the result a reasonable ASM_OPERANDS? */
2409 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2415 /* If we had to change another insn, make sure it is valid also. */
2416 if (undobuf
.other_insn
)
2418 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2419 rtx new_other_notes
;
2422 CLEAR_HARD_REG_SET (newpat_used_regs
);
2424 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2427 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2433 PATTERN (undobuf
.other_insn
) = other_pat
;
2435 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2436 are still valid. Then add any non-duplicate notes added by
2437 recog_for_combine. */
2438 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2440 next
= XEXP (note
, 1);
2442 if (REG_NOTE_KIND (note
) == REG_UNUSED
2443 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2445 if (GET_CODE (XEXP (note
, 0)) == REG
)
2446 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2448 remove_note (undobuf
.other_insn
, note
);
2452 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2453 if (GET_CODE (XEXP (note
, 0)) == REG
)
2454 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2456 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2457 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2460 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2461 they are adjacent to each other or not. */
2463 rtx p
= prev_nonnote_insn (i3
);
2464 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2465 && sets_cc0_p (newi2pat
))
2473 /* We now know that we can do this combination. Merge the insns and
2474 update the status of registers and LOG_LINKS. */
2477 rtx i3notes
, i2notes
, i1notes
= 0;
2478 rtx i3links
, i2links
, i1links
= 0;
2481 /* Compute which registers we expect to eliminate. newi2pat may be setting
2482 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2483 same as i3dest, in which case newi2pat may be setting i1dest. */
2484 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2485 || i2dest_in_i2src
|| i2dest_in_i1src
2487 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2488 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2491 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2493 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2494 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2496 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2498 /* Ensure that we do not have something that should not be shared but
2499 occurs multiple times in the new insns. Check this by first
2500 resetting all the `used' flags and then copying anything is shared. */
2502 reset_used_flags (i3notes
);
2503 reset_used_flags (i2notes
);
2504 reset_used_flags (i1notes
);
2505 reset_used_flags (newpat
);
2506 reset_used_flags (newi2pat
);
2507 if (undobuf
.other_insn
)
2508 reset_used_flags (PATTERN (undobuf
.other_insn
));
2510 i3notes
= copy_rtx_if_shared (i3notes
);
2511 i2notes
= copy_rtx_if_shared (i2notes
);
2512 i1notes
= copy_rtx_if_shared (i1notes
);
2513 newpat
= copy_rtx_if_shared (newpat
);
2514 newi2pat
= copy_rtx_if_shared (newi2pat
);
2515 if (undobuf
.other_insn
)
2516 reset_used_flags (PATTERN (undobuf
.other_insn
));
2518 INSN_CODE (i3
) = insn_code_number
;
2519 PATTERN (i3
) = newpat
;
2520 if (undobuf
.other_insn
)
2521 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2523 /* We had one special case above where I2 had more than one set and
2524 we replaced a destination of one of those sets with the destination
2525 of I3. In that case, we have to update LOG_LINKS of insns later
2526 in this basic block. Note that this (expensive) case is rare.
2528 Also, in this case, we must pretend that all REG_NOTEs for I2
2529 actually came from I3, so that REG_UNUSED notes from I2 will be
2530 properly handled. */
2532 if (i3_subst_into_i2
&& GET_CODE (PATTERN (i2
)) == PARALLEL
)
2534 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2535 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2536 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2537 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2538 && ! find_reg_note (i2
, REG_UNUSED
,
2539 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2540 for (temp
= NEXT_INSN (i2
);
2541 temp
&& (this_basic_block
== n_basic_blocks
- 1
2542 || BLOCK_HEAD (this_basic_block
) != temp
);
2543 temp
= NEXT_INSN (temp
))
2544 if (temp
!= i3
&& INSN_P (temp
))
2545 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2546 if (XEXP (link
, 0) == i2
)
2547 XEXP (link
, 0) = i3
;
2552 while (XEXP (link
, 1))
2553 link
= XEXP (link
, 1);
2554 XEXP (link
, 1) = i2notes
;
2568 INSN_CODE (i2
) = i2_code_number
;
2569 PATTERN (i2
) = newi2pat
;
2573 PUT_CODE (i2
, NOTE
);
2574 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2575 NOTE_SOURCE_FILE (i2
) = 0;
2582 PUT_CODE (i1
, NOTE
);
2583 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2584 NOTE_SOURCE_FILE (i1
) = 0;
2587 /* Get death notes for everything that is now used in either I3 or
2588 I2 and used to die in a previous insn. If we built two new
2589 patterns, move from I1 to I2 then I2 to I3 so that we get the
2590 proper movement on registers that I2 modifies. */
2594 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2595 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2598 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2601 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2603 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2606 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2609 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2612 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2615 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2616 know these are REG_UNUSED and want them to go to the desired insn,
2617 so we always pass it as i3. We have not counted the notes in
2618 reg_n_deaths yet, so we need to do so now. */
2620 if (newi2pat
&& new_i2_notes
)
2622 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2623 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2624 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2626 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2631 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2632 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2633 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2635 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2638 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2639 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2640 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2641 in that case, it might delete I2. Similarly for I2 and I1.
2642 Show an additional death due to the REG_DEAD note we make here. If
2643 we discard it in distribute_notes, we will decrement it again. */
2647 if (GET_CODE (i3dest_killed
) == REG
)
2648 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2650 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2651 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2653 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2655 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2657 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2661 if (i2dest_in_i2src
)
2663 if (GET_CODE (i2dest
) == REG
)
2664 REG_N_DEATHS (REGNO (i2dest
))++;
2666 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2667 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2668 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2670 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2671 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2672 NULL_RTX
, NULL_RTX
);
2675 if (i1dest_in_i1src
)
2677 if (GET_CODE (i1dest
) == REG
)
2678 REG_N_DEATHS (REGNO (i1dest
))++;
2680 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2681 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2682 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2684 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2685 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2686 NULL_RTX
, NULL_RTX
);
2689 distribute_links (i3links
);
2690 distribute_links (i2links
);
2691 distribute_links (i1links
);
2693 if (GET_CODE (i2dest
) == REG
)
2696 rtx i2_insn
= 0, i2_val
= 0, set
;
2698 /* The insn that used to set this register doesn't exist, and
2699 this life of the register may not exist either. See if one of
2700 I3's links points to an insn that sets I2DEST. If it does,
2701 that is now the last known value for I2DEST. If we don't update
2702 this and I2 set the register to a value that depended on its old
2703 contents, we will get confused. If this insn is used, thing
2704 will be set correctly in combine_instructions. */
2706 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2707 if ((set
= single_set (XEXP (link
, 0))) != 0
2708 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2709 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2711 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2713 /* If the reg formerly set in I2 died only once and that was in I3,
2714 zero its use count so it won't make `reload' do any work. */
2716 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2717 && ! i2dest_in_i2src
)
2719 regno
= REGNO (i2dest
);
2720 REG_N_SETS (regno
)--;
2724 if (i1
&& GET_CODE (i1dest
) == REG
)
2727 rtx i1_insn
= 0, i1_val
= 0, set
;
2729 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2730 if ((set
= single_set (XEXP (link
, 0))) != 0
2731 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2732 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2734 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2736 regno
= REGNO (i1dest
);
2737 if (! added_sets_1
&& ! i1dest_in_i1src
)
2738 REG_N_SETS (regno
)--;
2741 /* Update reg_nonzero_bits et al for any changes that may have been made
2742 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2743 important. Because newi2pat can affect nonzero_bits of newpat */
2745 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2746 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2748 /* Set new_direct_jump_p if a new return or simple jump instruction
2751 If I3 is now an unconditional jump, ensure that it has a
2752 BARRIER following it since it may have initially been a
2753 conditional jump. It may also be the last nonnote insn. */
2755 if (GET_CODE (newpat
) == RETURN
|| any_uncondjump_p (i3
))
2757 *new_direct_jump_p
= 1;
2759 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2760 || GET_CODE (temp
) != BARRIER
)
2761 emit_barrier_after (i3
);
2765 combine_successes
++;
2768 /* Clear this here, so that subsequent get_last_value calls are not
2770 subst_prev_insn
= NULL_RTX
;
2772 if (added_links_insn
2773 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2774 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2775 return added_links_insn
;
2777 return newi2pat
? i2
: i3
;
2780 /* Undo all the modifications recorded in undobuf. */
2785 struct undo
*undo
, *next
;
2787 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2791 *undo
->where
.i
= undo
->old_contents
.i
;
2793 *undo
->where
.r
= undo
->old_contents
.r
;
2795 undo
->next
= undobuf
.frees
;
2796 undobuf
.frees
= undo
;
2799 undobuf
.undos
= undobuf
.previous_undos
= 0;
2801 /* Clear this here, so that subsequent get_last_value calls are not
2803 subst_prev_insn
= NULL_RTX
;
2806 /* We've committed to accepting the changes we made. Move all
2807 of the undos to the free list. */
2812 struct undo
*undo
, *next
;
2814 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2817 undo
->next
= undobuf
.frees
;
2818 undobuf
.frees
= undo
;
2820 undobuf
.undos
= undobuf
.previous_undos
= 0;
2824 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2825 where we have an arithmetic expression and return that point. LOC will
2828 try_combine will call this function to see if an insn can be split into
2832 find_split_point (loc
, insn
)
2837 enum rtx_code code
= GET_CODE (x
);
2839 unsigned HOST_WIDE_INT len
= 0;
2840 HOST_WIDE_INT pos
= 0;
2842 rtx inner
= NULL_RTX
;
2844 /* First special-case some codes. */
2848 #ifdef INSN_SCHEDULING
2849 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2851 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2854 return find_split_point (&SUBREG_REG (x
), insn
);
2858 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2859 using LO_SUM and HIGH. */
2860 if (GET_CODE (XEXP (x
, 0)) == CONST
2861 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2864 gen_rtx_combine (LO_SUM
, Pmode
,
2865 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
2867 return &XEXP (XEXP (x
, 0), 0);
2871 /* If we have a PLUS whose second operand is a constant and the
2872 address is not valid, perhaps will can split it up using
2873 the machine-specific way to split large constants. We use
2874 the first pseudo-reg (one of the virtual regs) as a placeholder;
2875 it will not remain in the result. */
2876 if (GET_CODE (XEXP (x
, 0)) == PLUS
2877 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2878 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2880 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2881 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2884 /* This should have produced two insns, each of which sets our
2885 placeholder. If the source of the second is a valid address,
2886 we can make put both sources together and make a split point
2889 if (seq
&& XVECLEN (seq
, 0) == 2
2890 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2891 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2892 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2893 && ! reg_mentioned_p (reg
,
2894 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2895 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2896 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2897 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2898 && memory_address_p (GET_MODE (x
),
2899 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2901 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2902 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2904 /* Replace the placeholder in SRC2 with SRC1. If we can
2905 find where in SRC2 it was placed, that can become our
2906 split point and we can replace this address with SRC2.
2907 Just try two obvious places. */
2909 src2
= replace_rtx (src2
, reg
, src1
);
2911 if (XEXP (src2
, 0) == src1
)
2912 split
= &XEXP (src2
, 0);
2913 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2914 && XEXP (XEXP (src2
, 0), 0) == src1
)
2915 split
= &XEXP (XEXP (src2
, 0), 0);
2919 SUBST (XEXP (x
, 0), src2
);
2924 /* If that didn't work, perhaps the first operand is complex and
2925 needs to be computed separately, so make a split point there.
2926 This will occur on machines that just support REG + CONST
2927 and have a constant moved through some previous computation. */
2929 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2930 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2931 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2933 return &XEXP (XEXP (x
, 0), 0);
2939 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2940 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2941 we need to put the operand into a register. So split at that
2944 if (SET_DEST (x
) == cc0_rtx
2945 && GET_CODE (SET_SRC (x
)) != COMPARE
2946 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2947 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2948 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2949 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2950 return &SET_SRC (x
);
2953 /* See if we can split SET_SRC as it stands. */
2954 split
= find_split_point (&SET_SRC (x
), insn
);
2955 if (split
&& split
!= &SET_SRC (x
))
2958 /* See if we can split SET_DEST as it stands. */
2959 split
= find_split_point (&SET_DEST (x
), insn
);
2960 if (split
&& split
!= &SET_DEST (x
))
2963 /* See if this is a bitfield assignment with everything constant. If
2964 so, this is an IOR of an AND, so split it into that. */
2965 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2966 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2967 <= HOST_BITS_PER_WIDE_INT
)
2968 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2969 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2970 && GET_CODE (SET_SRC (x
)) == CONST_INT
2971 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2972 + INTVAL (XEXP (SET_DEST (x
), 2)))
2973 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2974 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2976 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2977 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2978 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2979 rtx dest
= XEXP (SET_DEST (x
), 0);
2980 enum machine_mode mode
= GET_MODE (dest
);
2981 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2983 if (BITS_BIG_ENDIAN
)
2984 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2988 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
2991 gen_binary (IOR
, mode
,
2992 gen_binary (AND
, mode
, dest
,
2993 GEN_INT (~(mask
<< pos
)
2994 & GET_MODE_MASK (mode
))),
2995 GEN_INT (src
<< pos
)));
2997 SUBST (SET_DEST (x
), dest
);
2999 split
= find_split_point (&SET_SRC (x
), insn
);
3000 if (split
&& split
!= &SET_SRC (x
))
3004 /* Otherwise, see if this is an operation that we can split into two.
3005 If so, try to split that. */
3006 code
= GET_CODE (SET_SRC (x
));
3011 /* If we are AND'ing with a large constant that is only a single
3012 bit and the result is only being used in a context where we
3013 need to know if it is zero or non-zero, replace it with a bit
3014 extraction. This will avoid the large constant, which might
3015 have taken more than one insn to make. If the constant were
3016 not a valid argument to the AND but took only one insn to make,
3017 this is no worse, but if it took more than one insn, it will
3020 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3021 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3022 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3023 && GET_CODE (SET_DEST (x
)) == REG
3024 && (split
= find_single_use (SET_DEST (x
), insn
, NULL_PTR
)) != 0
3025 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3026 && XEXP (*split
, 0) == SET_DEST (x
)
3027 && XEXP (*split
, 1) == const0_rtx
)
3029 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3030 XEXP (SET_SRC (x
), 0),
3031 pos
, NULL_RTX
, 1, 1, 0, 0);
3032 if (extraction
!= 0)
3034 SUBST (SET_SRC (x
), extraction
);
3035 return find_split_point (loc
, insn
);
3041 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3042 is known to be on, this can be converted into a NEG of a shift. */
3043 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3044 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3045 && 1 <= (pos
= exact_log2
3046 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3047 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3049 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3052 gen_rtx_combine (NEG
, mode
,
3053 gen_rtx_combine (LSHIFTRT
, mode
,
3054 XEXP (SET_SRC (x
), 0),
3057 split
= find_split_point (&SET_SRC (x
), insn
);
3058 if (split
&& split
!= &SET_SRC (x
))
3064 inner
= XEXP (SET_SRC (x
), 0);
3066 /* We can't optimize if either mode is a partial integer
3067 mode as we don't know how many bits are significant
3069 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3070 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3074 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3080 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3081 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3083 inner
= XEXP (SET_SRC (x
), 0);
3084 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3085 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3087 if (BITS_BIG_ENDIAN
)
3088 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3089 unsignedp
= (code
== ZERO_EXTRACT
);
3097 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3099 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3101 /* For unsigned, we have a choice of a shift followed by an
3102 AND or two shifts. Use two shifts for field sizes where the
3103 constant might be too large. We assume here that we can
3104 always at least get 8-bit constants in an AND insn, which is
3105 true for every current RISC. */
3107 if (unsignedp
&& len
<= 8)
3112 gen_rtx_combine (LSHIFTRT
, mode
,
3113 gen_lowpart_for_combine (mode
, inner
),
3115 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3117 split
= find_split_point (&SET_SRC (x
), insn
);
3118 if (split
&& split
!= &SET_SRC (x
))
3125 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3126 gen_rtx_combine (ASHIFT
, mode
,
3127 gen_lowpart_for_combine (mode
, inner
),
3128 GEN_INT (GET_MODE_BITSIZE (mode
)
3130 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3132 split
= find_split_point (&SET_SRC (x
), insn
);
3133 if (split
&& split
!= &SET_SRC (x
))
3138 /* See if this is a simple operation with a constant as the second
3139 operand. It might be that this constant is out of range and hence
3140 could be used as a split point. */
3141 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3142 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3143 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3144 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3145 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3146 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3147 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3149 return &XEXP (SET_SRC (x
), 1);
3151 /* Finally, see if this is a simple operation with its first operand
3152 not in a register. The operation might require this operand in a
3153 register, so return it as a split point. We can always do this
3154 because if the first operand were another operation, we would have
3155 already found it as a split point. */
3156 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3157 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3158 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3159 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3160 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3161 return &XEXP (SET_SRC (x
), 0);
3167 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3168 it is better to write this as (not (ior A B)) so we can split it.
3169 Similarly for IOR. */
3170 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3173 gen_rtx_combine (NOT
, GET_MODE (x
),
3174 gen_rtx_combine (code
== IOR
? AND
: IOR
,
3176 XEXP (XEXP (x
, 0), 0),
3177 XEXP (XEXP (x
, 1), 0))));
3178 return find_split_point (loc
, insn
);
3181 /* Many RISC machines have a large set of logical insns. If the
3182 second operand is a NOT, put it first so we will try to split the
3183 other operand first. */
3184 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3186 rtx tem
= XEXP (x
, 0);
3187 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3188 SUBST (XEXP (x
, 1), tem
);
3196 /* Otherwise, select our actions depending on our rtx class. */
3197 switch (GET_RTX_CLASS (code
))
3199 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3201 split
= find_split_point (&XEXP (x
, 2), insn
);
3204 /* ... fall through ... */
3208 split
= find_split_point (&XEXP (x
, 1), insn
);
3211 /* ... fall through ... */
3213 /* Some machines have (and (shift ...) ...) insns. If X is not
3214 an AND, but XEXP (X, 0) is, use it as our split point. */
3215 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3216 return &XEXP (x
, 0);
3218 split
= find_split_point (&XEXP (x
, 0), insn
);
3224 /* Otherwise, we don't have a split point. */
3228 /* Throughout X, replace FROM with TO, and return the result.
3229 The result is TO if X is FROM;
3230 otherwise the result is X, but its contents may have been modified.
3231 If they were modified, a record was made in undobuf so that
3232 undo_all will (among other things) return X to its original state.
3234 If the number of changes necessary is too much to record to undo,
3235 the excess changes are not made, so the result is invalid.
3236 The changes already made can still be undone.
3237 undobuf.num_undo is incremented for such changes, so by testing that
3238 the caller can tell whether the result is valid.
3240 `n_occurrences' is incremented each time FROM is replaced.
3242 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3244 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3245 by copying if `n_occurrences' is non-zero. */
3248 subst (x
, from
, to
, in_dest
, unique_copy
)
3249 register rtx x
, from
, to
;
3253 register enum rtx_code code
= GET_CODE (x
);
3254 enum machine_mode op0_mode
= VOIDmode
;
3255 register const char *fmt
;
3256 register int len
, i
;
3259 /* Two expressions are equal if they are identical copies of a shared
3260 RTX or if they are both registers with the same register number
3263 #define COMBINE_RTX_EQUAL_P(X,Y) \
3265 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3266 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3268 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3271 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3274 /* If X and FROM are the same register but different modes, they will
3275 not have been seen as equal above. However, flow.c will make a
3276 LOG_LINKS entry for that case. If we do nothing, we will try to
3277 rerecognize our original insn and, when it succeeds, we will
3278 delete the feeding insn, which is incorrect.
3280 So force this insn not to match in this (rare) case. */
3281 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3282 && REGNO (x
) == REGNO (from
))
3283 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3285 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3286 of which may contain things that can be combined. */
3287 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3290 /* It is possible to have a subexpression appear twice in the insn.
3291 Suppose that FROM is a register that appears within TO.
3292 Then, after that subexpression has been scanned once by `subst',
3293 the second time it is scanned, TO may be found. If we were
3294 to scan TO here, we would find FROM within it and create a
3295 self-referent rtl structure which is completely wrong. */
3296 if (COMBINE_RTX_EQUAL_P (x
, to
))
3299 /* Parallel asm_operands need special attention because all of the
3300 inputs are shared across the arms. Furthermore, unsharing the
3301 rtl results in recognition failures. Failure to handle this case
3302 specially can result in circular rtl.
3304 Solve this by doing a normal pass across the first entry of the
3305 parallel, and only processing the SET_DESTs of the subsequent
3308 if (code
== PARALLEL
3309 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3310 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3312 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3314 /* If this substitution failed, this whole thing fails. */
3315 if (GET_CODE (new) == CLOBBER
3316 && XEXP (new, 0) == const0_rtx
)
3319 SUBST (XVECEXP (x
, 0, 0), new);
3321 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3323 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3325 if (GET_CODE (dest
) != REG
3326 && GET_CODE (dest
) != CC0
3327 && GET_CODE (dest
) != PC
)
3329 new = subst (dest
, from
, to
, 0, unique_copy
);
3331 /* If this substitution failed, this whole thing fails. */
3332 if (GET_CODE (new) == CLOBBER
3333 && XEXP (new, 0) == const0_rtx
)
3336 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3342 len
= GET_RTX_LENGTH (code
);
3343 fmt
= GET_RTX_FORMAT (code
);
3345 /* We don't need to process a SET_DEST that is a register, CC0,
3346 or PC, so set up to skip this common case. All other cases
3347 where we want to suppress replacing something inside a
3348 SET_SRC are handled via the IN_DEST operand. */
3350 && (GET_CODE (SET_DEST (x
)) == REG
3351 || GET_CODE (SET_DEST (x
)) == CC0
3352 || GET_CODE (SET_DEST (x
)) == PC
))
3355 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3358 op0_mode
= GET_MODE (XEXP (x
, 0));
3360 for (i
= 0; i
< len
; i
++)
3365 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3367 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3369 new = (unique_copy
&& n_occurrences
3370 ? copy_rtx (to
) : to
);
3375 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3378 /* If this substitution failed, this whole thing
3380 if (GET_CODE (new) == CLOBBER
3381 && XEXP (new, 0) == const0_rtx
)
3385 SUBST (XVECEXP (x
, i
, j
), new);
3388 else if (fmt
[i
] == 'e')
3390 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3392 /* In general, don't install a subreg involving two
3393 modes not tieable. It can worsen register
3394 allocation, and can even make invalid reload
3395 insns, since the reg inside may need to be copied
3396 from in the outside mode, and that may be invalid
3397 if it is an fp reg copied in integer mode.
3399 We allow two exceptions to this: It is valid if
3400 it is inside another SUBREG and the mode of that
3401 SUBREG and the mode of the inside of TO is
3402 tieable and it is valid if X is a SET that copies
3405 if (GET_CODE (to
) == SUBREG
3406 && ! MODES_TIEABLE_P (GET_MODE (to
),
3407 GET_MODE (SUBREG_REG (to
)))
3408 && ! (code
== SUBREG
3409 && MODES_TIEABLE_P (GET_MODE (x
),
3410 GET_MODE (SUBREG_REG (to
))))
3412 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3415 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3417 #ifdef CLASS_CANNOT_CHANGE_MODE
3419 && GET_CODE (to
) == REG
3420 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3421 && (TEST_HARD_REG_BIT
3422 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3424 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3426 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3429 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3433 /* If we are in a SET_DEST, suppress most cases unless we
3434 have gone inside a MEM, in which case we want to
3435 simplify the address. We assume here that things that
3436 are actually part of the destination have their inner
3437 parts in the first expression. This is true for SUBREG,
3438 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3439 things aside from REG and MEM that should appear in a
3441 new = subst (XEXP (x
, i
), from
, to
,
3443 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3444 || code
== ZERO_EXTRACT
))
3446 && i
== 0), unique_copy
);
3448 /* If we found that we will have to reject this combination,
3449 indicate that by returning the CLOBBER ourselves, rather than
3450 an expression containing it. This will speed things up as
3451 well as prevent accidents where two CLOBBERs are considered
3452 to be equal, thus producing an incorrect simplification. */
3454 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3457 SUBST (XEXP (x
, i
), new);
3462 /* Try to simplify X. If the simplification changed the code, it is likely
3463 that further simplification will help, so loop, but limit the number
3464 of repetitions that will be performed. */
3466 for (i
= 0; i
< 4; i
++)
3468 /* If X is sufficiently simple, don't bother trying to do anything
3470 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3471 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3473 if (GET_CODE (x
) == code
)
3476 code
= GET_CODE (x
);
3478 /* We no longer know the original mode of operand 0 since we
3479 have changed the form of X) */
3480 op0_mode
= VOIDmode
;
3486 /* Simplify X, a piece of RTL. We just operate on the expression at the
3487 outer level; call `subst' to simplify recursively. Return the new
3490 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3491 will be the iteration even if an expression with a code different from
3492 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3495 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3497 enum machine_mode op0_mode
;
3501 enum rtx_code code
= GET_CODE (x
);
3502 enum machine_mode mode
= GET_MODE (x
);
3506 /* If this is a commutative operation, put a constant last and a complex
3507 expression first. We don't need to do this for comparisons here. */
3508 if (GET_RTX_CLASS (code
) == 'c'
3509 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3510 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
3511 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
3512 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3513 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
3514 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
3517 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3518 SUBST (XEXP (x
, 1), temp
);
3521 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3522 sign extension of a PLUS with a constant, reverse the order of the sign
3523 extension and the addition. Note that this not the same as the original
3524 code, but overflow is undefined for signed values. Also note that the
3525 PLUS will have been partially moved "inside" the sign-extension, so that
3526 the first operand of X will really look like:
3527 (ashiftrt (plus (ashift A C4) C5) C4).
3529 (plus (ashiftrt (ashift A C4) C2) C4)
3530 and replace the first operand of X with that expression. Later parts
3531 of this function may simplify the expression further.
3533 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3534 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3535 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3537 We do this to simplify address expressions. */
3539 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3540 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3541 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3542 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3543 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3544 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3545 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3546 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3547 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3548 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3549 XEXP (XEXP (x
, 0), 1))) != 0)
3552 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3553 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3554 INTVAL (XEXP (XEXP (x
, 0), 1)));
3556 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3557 INTVAL (XEXP (XEXP (x
, 0), 1)));
3559 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3562 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3563 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3564 things. Check for cases where both arms are testing the same
3567 Don't do anything if all operands are very simple. */
3569 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3570 || GET_RTX_CLASS (code
) == '<')
3571 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3572 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3573 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3575 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3576 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3577 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3579 || (GET_RTX_CLASS (code
) == '1'
3580 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3581 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3582 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3585 rtx cond
, true, false;
3587 cond
= if_then_else_cond (x
, &true, &false);
3589 /* If everything is a comparison, what we have is highly unlikely
3590 to be simpler, so don't use it. */
3591 && ! (GET_RTX_CLASS (code
) == '<'
3592 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3593 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3595 rtx cop1
= const0_rtx
;
3596 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3598 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3601 /* Simplify the alternative arms; this may collapse the true and
3602 false arms to store-flag values. */
3603 true = subst (true, pc_rtx
, pc_rtx
, 0, 0);
3604 false = subst (false, pc_rtx
, pc_rtx
, 0, 0);
3606 /* If true and false are not general_operands, an if_then_else
3607 is unlikely to be simpler. */
3608 if (general_operand (true, VOIDmode
)
3609 && general_operand (false, VOIDmode
))
3611 /* Restarting if we generate a store-flag expression will cause
3612 us to loop. Just drop through in this case. */
3614 /* If the result values are STORE_FLAG_VALUE and zero, we can
3615 just make the comparison operation. */
3616 if (true == const_true_rtx
&& false == const0_rtx
)
3617 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3618 else if (true == const0_rtx
&& false == const_true_rtx
)
3619 x
= gen_binary (reverse_condition (cond_code
),
3622 /* Likewise, we can make the negate of a comparison operation
3623 if the result values are - STORE_FLAG_VALUE and zero. */
3624 else if (GET_CODE (true) == CONST_INT
3625 && INTVAL (true) == - STORE_FLAG_VALUE
3626 && false == const0_rtx
)
3627 x
= gen_unary (NEG
, mode
, mode
,
3628 gen_binary (cond_code
, mode
, cond
, cop1
));
3629 else if (GET_CODE (false) == CONST_INT
3630 && INTVAL (false) == - STORE_FLAG_VALUE
3631 && true == const0_rtx
)
3632 x
= gen_unary (NEG
, mode
, mode
,
3633 gen_binary (reverse_condition (cond_code
),
3636 return gen_rtx_IF_THEN_ELSE (mode
,
3637 gen_binary (cond_code
, VOIDmode
,
3641 code
= GET_CODE (x
);
3642 op0_mode
= VOIDmode
;
3647 /* Try to fold this expression in case we have constants that weren't
3650 switch (GET_RTX_CLASS (code
))
3653 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3657 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3658 if (cmp_mode
== VOIDmode
)
3659 cmp_mode
= GET_MODE (XEXP (x
, 1));
3660 temp
= simplify_relational_operation (code
, cmp_mode
,
3661 XEXP (x
, 0), XEXP (x
, 1));
3663 #ifdef FLOAT_STORE_FLAG_VALUE
3664 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3666 if (temp
== const0_rtx
)
3667 temp
= CONST0_RTX (mode
);
3669 temp
= immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode
), mode
);
3675 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3679 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3680 XEXP (x
, 1), XEXP (x
, 2));
3685 x
= temp
, code
= GET_CODE (temp
);
3687 /* First see if we can apply the inverse distributive law. */
3688 if (code
== PLUS
|| code
== MINUS
3689 || code
== AND
|| code
== IOR
|| code
== XOR
)
3691 x
= apply_distributive_law (x
);
3692 code
= GET_CODE (x
);
3695 /* If CODE is an associative operation not otherwise handled, see if we
3696 can associate some operands. This can win if they are constants or
3697 if they are logically related (i.e. (a & b) & a. */
3698 if ((code
== PLUS
|| code
== MINUS
3699 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3700 || code
== DIV
|| code
== UDIV
3701 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3702 && INTEGRAL_MODE_P (mode
))
3704 if (GET_CODE (XEXP (x
, 0)) == code
)
3706 rtx other
= XEXP (XEXP (x
, 0), 0);
3707 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3708 rtx inner_op1
= XEXP (x
, 1);
3711 /* Make sure we pass the constant operand if any as the second
3712 one if this is a commutative operation. */
3713 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3715 rtx tem
= inner_op0
;
3716 inner_op0
= inner_op1
;
3719 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3720 : code
== DIV
? MULT
3721 : code
== UDIV
? MULT
3723 mode
, inner_op0
, inner_op1
);
3725 /* For commutative operations, try the other pair if that one
3727 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3729 other
= XEXP (XEXP (x
, 0), 1);
3730 inner
= simplify_binary_operation (code
, mode
,
3731 XEXP (XEXP (x
, 0), 0),
3736 return gen_binary (code
, mode
, other
, inner
);
3740 /* A little bit of algebraic simplification here. */
3744 /* Ensure that our address has any ASHIFTs converted to MULT in case
3745 address-recognizing predicates are called later. */
3746 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3747 SUBST (XEXP (x
, 0), temp
);
3751 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3752 is paradoxical. If we can't do that safely, then it becomes
3753 something nonsensical so that this combination won't take place. */
3755 if (GET_CODE (SUBREG_REG (x
)) == MEM
3756 && (GET_MODE_SIZE (mode
)
3757 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3759 rtx inner
= SUBREG_REG (x
);
3760 int endian_offset
= 0;
3761 /* Don't change the mode of the MEM
3762 if that would change the meaning of the address. */
3763 if (MEM_VOLATILE_P (SUBREG_REG (x
))
3764 || mode_dependent_address_p (XEXP (inner
, 0)))
3765 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3767 if (BYTES_BIG_ENDIAN
)
3769 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3770 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
3771 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
3772 endian_offset
-= (UNITS_PER_WORD
3773 - GET_MODE_SIZE (GET_MODE (inner
)));
3775 /* Note if the plus_constant doesn't make a valid address
3776 then this combination won't be accepted. */
3777 x
= gen_rtx_MEM (mode
,
3778 plus_constant (XEXP (inner
, 0),
3779 (SUBREG_WORD (x
) * UNITS_PER_WORD
3781 MEM_COPY_ATTRIBUTES (x
, inner
);
3785 /* If we are in a SET_DEST, these other cases can't apply. */
3789 /* Changing mode twice with SUBREG => just change it once,
3790 or not at all if changing back to starting mode. */
3791 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
3793 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
3794 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
3795 return SUBREG_REG (SUBREG_REG (x
));
3797 SUBST_INT (SUBREG_WORD (x
),
3798 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
3799 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
3802 /* SUBREG of a hard register => just change the register number
3803 and/or mode. If the hard register is not valid in that mode,
3804 suppress this combination. If the hard register is the stack,
3805 frame, or argument pointer, leave this as a SUBREG. */
3807 if (GET_CODE (SUBREG_REG (x
)) == REG
3808 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
3809 && REGNO (SUBREG_REG (x
)) != FRAME_POINTER_REGNUM
3810 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3811 && REGNO (SUBREG_REG (x
)) != HARD_FRAME_POINTER_REGNUM
3813 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3814 && REGNO (SUBREG_REG (x
)) != ARG_POINTER_REGNUM
3816 && REGNO (SUBREG_REG (x
)) != STACK_POINTER_REGNUM
)
3818 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
3820 return gen_rtx_REG (mode
,
3821 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
3823 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3826 /* For a constant, try to pick up the part we want. Handle a full
3827 word and low-order part. Only do this if we are narrowing
3828 the constant; if it is being widened, we have no idea what
3829 the extra bits will have been set to. */
3831 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
3832 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
3833 && GET_MODE_SIZE (op0_mode
) > UNITS_PER_WORD
3834 && GET_MODE_CLASS (mode
) == MODE_INT
)
3836 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
3842 /* If we want a subreg of a constant, at offset 0,
3843 take the low bits. On a little-endian machine, that's
3844 always valid. On a big-endian machine, it's valid
3845 only if the constant's mode fits in one word. Note that we
3846 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3847 if (CONSTANT_P (SUBREG_REG (x
))
3848 && ((GET_MODE_SIZE (op0_mode
) <= UNITS_PER_WORD
3849 || ! WORDS_BIG_ENDIAN
)
3850 ? SUBREG_WORD (x
) == 0
3852 == ((GET_MODE_SIZE (op0_mode
)
3853 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
3855 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (op0_mode
)
3856 && (! WORDS_BIG_ENDIAN
3857 || GET_MODE_BITSIZE (op0_mode
) <= BITS_PER_WORD
))
3858 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3860 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3861 since we are saying that the high bits don't matter. */
3862 if (CONSTANT_P (SUBREG_REG (x
)) && GET_MODE (SUBREG_REG (x
)) == VOIDmode
3863 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (op0_mode
))
3865 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
3866 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
3867 return operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
), 0, mode
);
3868 return SUBREG_REG (x
);
3871 /* Note that we cannot do any narrowing for non-constants since
3872 we might have been counting on using the fact that some bits were
3873 zero. We now do this in the SET. */
3878 /* (not (plus X -1)) can become (neg X). */
3879 if (GET_CODE (XEXP (x
, 0)) == PLUS
3880 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3881 return gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
3883 /* Similarly, (not (neg X)) is (plus X -1). */
3884 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3885 return gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3888 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3889 if (GET_CODE (XEXP (x
, 0)) == XOR
3890 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3891 && (temp
= simplify_unary_operation (NOT
, mode
,
3892 XEXP (XEXP (x
, 0), 1),
3894 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3896 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3897 other than 1, but that is not valid. We could do a similar
3898 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3899 but this doesn't seem common enough to bother with. */
3900 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3901 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3902 return gen_rtx_ROTATE (mode
, gen_unary (NOT
, mode
, mode
, const1_rtx
),
3903 XEXP (XEXP (x
, 0), 1));
3905 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3906 && subreg_lowpart_p (XEXP (x
, 0))
3907 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3908 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3909 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3910 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3912 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3914 x
= gen_rtx_ROTATE (inner_mode
,
3915 gen_unary (NOT
, inner_mode
, inner_mode
,
3917 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3918 return gen_lowpart_for_combine (mode
, x
);
3921 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3922 reversing the comparison code if valid. */
3923 if (STORE_FLAG_VALUE
== -1
3924 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3925 && reversible_comparison_p (XEXP (x
, 0)))
3926 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3927 mode
, XEXP (XEXP (x
, 0), 0),
3928 XEXP (XEXP (x
, 0), 1));
3930 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3931 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3932 perform the above simplification. */
3934 if (STORE_FLAG_VALUE
== -1
3935 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3936 && XEXP (x
, 1) == const1_rtx
3937 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3938 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3939 return gen_rtx_combine (GE
, mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3941 /* Apply De Morgan's laws to reduce number of patterns for machines
3942 with negating logical insns (and-not, nand, etc.). If result has
3943 only one NOT, put it first, since that is how the patterns are
3946 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3948 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3949 enum machine_mode op_mode
;
3951 op_mode
= GET_MODE (in1
);
3952 in1
= gen_unary (NOT
, op_mode
, op_mode
, in1
);
3954 op_mode
= GET_MODE (in2
);
3955 if (op_mode
== VOIDmode
)
3957 in2
= gen_unary (NOT
, op_mode
, op_mode
, in2
);
3959 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3962 in2
= in1
; in1
= tem
;
3965 return gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3971 /* (neg (plus X 1)) can become (not X). */
3972 if (GET_CODE (XEXP (x
, 0)) == PLUS
3973 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3974 return gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
3976 /* Similarly, (neg (not X)) is (plus X 1). */
3977 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3978 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3980 /* (neg (minus X Y)) can become (minus Y X). */
3981 if (GET_CODE (XEXP (x
, 0)) == MINUS
3982 && (! FLOAT_MODE_P (mode
)
3983 /* x-y != -(y-x) with IEEE floating point. */
3984 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3986 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3987 XEXP (XEXP (x
, 0), 0));
3989 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3990 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3991 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3992 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3994 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3995 if we can then eliminate the NEG (e.g.,
3996 if the operand is a constant). */
3998 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
4000 temp
= simplify_unary_operation (NEG
, mode
,
4001 XEXP (XEXP (x
, 0), 0), mode
);
4004 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
4009 temp
= expand_compound_operation (XEXP (x
, 0));
4011 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4012 replaced by (lshiftrt X C). This will convert
4013 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4015 if (GET_CODE (temp
) == ASHIFTRT
4016 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4017 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4018 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4019 INTVAL (XEXP (temp
, 1)));
4021 /* If X has only a single bit that might be nonzero, say, bit I, convert
4022 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4023 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4024 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4025 or a SUBREG of one since we'd be making the expression more
4026 complex if it was just a register. */
4028 if (GET_CODE (temp
) != REG
4029 && ! (GET_CODE (temp
) == SUBREG
4030 && GET_CODE (SUBREG_REG (temp
)) == REG
)
4031 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4033 rtx temp1
= simplify_shift_const
4034 (NULL_RTX
, ASHIFTRT
, mode
,
4035 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4036 GET_MODE_BITSIZE (mode
) - 1 - i
),
4037 GET_MODE_BITSIZE (mode
) - 1 - i
);
4039 /* If all we did was surround TEMP with the two shifts, we
4040 haven't improved anything, so don't use it. Otherwise,
4041 we are better off with TEMP1. */
4042 if (GET_CODE (temp1
) != ASHIFTRT
4043 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4044 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4050 /* We can't handle truncation to a partial integer mode here
4051 because we don't know the real bitsize of the partial
4053 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4056 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4057 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4058 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4060 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4061 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4063 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4064 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4065 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4066 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4067 return XEXP (XEXP (x
, 0), 0);
4069 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4070 (OP:SI foo:SI) if OP is NEG or ABS. */
4071 if ((GET_CODE (XEXP (x
, 0)) == ABS
4072 || GET_CODE (XEXP (x
, 0)) == NEG
)
4073 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4074 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4075 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4076 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
4077 XEXP (XEXP (XEXP (x
, 0), 0), 0));
4079 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4081 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4082 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4083 && subreg_lowpart_p (XEXP (x
, 0)))
4084 return SUBREG_REG (XEXP (x
, 0));
4086 /* If we know that the value is already truncated, we can
4087 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4088 is nonzero for the corresponding modes. But don't do this
4089 for an (LSHIFTRT (MULT ...)) since this will cause problems
4090 with the umulXi3_highpart patterns. */
4091 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4092 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4093 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4094 >= GET_MODE_BITSIZE (mode
) + 1
4095 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4096 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4097 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4099 /* A truncate of a comparison can be replaced with a subreg if
4100 STORE_FLAG_VALUE permits. This is like the previous test,
4101 but it works even if the comparison is done in a mode larger
4102 than HOST_BITS_PER_WIDE_INT. */
4103 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4104 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4105 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4106 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4108 /* Similarly, a truncate of a register whose value is a
4109 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4111 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4112 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4113 && (temp
= get_last_value (XEXP (x
, 0)))
4114 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4115 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4119 case FLOAT_TRUNCATE
:
4120 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4121 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4122 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4123 return XEXP (XEXP (x
, 0), 0);
4125 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4126 (OP:SF foo:SF) if OP is NEG or ABS. */
4127 if ((GET_CODE (XEXP (x
, 0)) == ABS
4128 || GET_CODE (XEXP (x
, 0)) == NEG
)
4129 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4130 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4131 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
4132 XEXP (XEXP (XEXP (x
, 0), 0), 0));
4134 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4135 is (float_truncate:SF x). */
4136 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4137 && subreg_lowpart_p (XEXP (x
, 0))
4138 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4139 return SUBREG_REG (XEXP (x
, 0));
4144 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4145 using cc0, in which case we want to leave it as a COMPARE
4146 so we can distinguish it from a register-register-copy. */
4147 if (XEXP (x
, 1) == const0_rtx
)
4150 /* In IEEE floating point, x-0 is not the same as x. */
4151 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4152 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
4154 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4160 /* (const (const X)) can become (const X). Do it this way rather than
4161 returning the inner CONST since CONST can be shared with a
4163 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4164 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4169 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4170 can add in an offset. find_split_point will split this address up
4171 again if it doesn't match. */
4172 if (GET_CODE (XEXP (x
, 0)) == HIGH
4173 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4179 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4180 outermost. That's because that's the way indexed addresses are
4181 supposed to appear. This code used to check many more cases, but
4182 they are now checked elsewhere. */
4183 if (GET_CODE (XEXP (x
, 0)) == PLUS
4184 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4185 return gen_binary (PLUS
, mode
,
4186 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4188 XEXP (XEXP (x
, 0), 1));
4190 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4191 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4192 bit-field and can be replaced by either a sign_extend or a
4193 sign_extract. The `and' may be a zero_extend and the two
4194 <c>, -<c> constants may be reversed. */
4195 if (GET_CODE (XEXP (x
, 0)) == XOR
4196 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4197 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4198 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4199 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4200 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4201 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4202 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4203 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4204 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4205 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4206 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4207 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4208 == (unsigned int) i
+ 1))))
4209 return simplify_shift_const
4210 (NULL_RTX
, ASHIFTRT
, mode
,
4211 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4212 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4213 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4214 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4216 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4217 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4218 is 1. This produces better code than the alternative immediately
4220 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4221 && reversible_comparison_p (XEXP (x
, 0))
4222 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4223 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
)))
4225 gen_unary (NEG
, mode
, mode
,
4226 gen_binary (reverse_condition (GET_CODE (XEXP (x
, 0))),
4227 mode
, XEXP (XEXP (x
, 0), 0),
4228 XEXP (XEXP (x
, 0), 1)));
4230 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4231 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4232 the bitsize of the mode - 1. This allows simplification of
4233 "a = (b & 8) == 0;" */
4234 if (XEXP (x
, 1) == constm1_rtx
4235 && GET_CODE (XEXP (x
, 0)) != REG
4236 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4237 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4238 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4239 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4240 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4241 gen_rtx_combine (XOR
, mode
,
4242 XEXP (x
, 0), const1_rtx
),
4243 GET_MODE_BITSIZE (mode
) - 1),
4244 GET_MODE_BITSIZE (mode
) - 1);
4246 /* If we are adding two things that have no bits in common, convert
4247 the addition into an IOR. This will often be further simplified,
4248 for example in cases like ((a & 1) + (a & 2)), which can
4251 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4252 && (nonzero_bits (XEXP (x
, 0), mode
)
4253 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4255 /* Try to simplify the expression further. */
4256 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4257 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4259 /* If we could, great. If not, do not go ahead with the IOR
4260 replacement, since PLUS appears in many special purpose
4261 address arithmetic instructions. */
4262 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4268 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4269 by reversing the comparison code if valid. */
4270 if (STORE_FLAG_VALUE
== 1
4271 && XEXP (x
, 0) == const1_rtx
4272 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4273 && reversible_comparison_p (XEXP (x
, 1)))
4274 return gen_binary (reverse_condition (GET_CODE (XEXP (x
, 1))), mode
,
4275 XEXP (XEXP (x
, 1), 0),
4276 XEXP (XEXP (x
, 1), 1));
4278 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4279 (and <foo> (const_int pow2-1)) */
4280 if (GET_CODE (XEXP (x
, 1)) == AND
4281 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4282 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4283 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4284 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4285 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4287 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4289 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4290 return gen_binary (MINUS
, mode
,
4291 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4292 XEXP (XEXP (x
, 1), 0)),
4293 XEXP (XEXP (x
, 1), 1));
4297 /* If we have (mult (plus A B) C), apply the distributive law and then
4298 the inverse distributive law to see if things simplify. This
4299 occurs mostly in addresses, often when unrolling loops. */
4301 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4303 x
= apply_distributive_law
4304 (gen_binary (PLUS
, mode
,
4305 gen_binary (MULT
, mode
,
4306 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4307 gen_binary (MULT
, mode
,
4308 XEXP (XEXP (x
, 0), 1),
4309 copy_rtx (XEXP (x
, 1)))));
4311 if (GET_CODE (x
) != MULT
)
4317 /* If this is a divide by a power of two, treat it as a shift if
4318 its first operand is a shift. */
4319 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4320 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4321 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4322 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4323 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4324 || GET_CODE (XEXP (x
, 0)) == ROTATE
4325 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4326 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4330 case GT
: case GTU
: case GE
: case GEU
:
4331 case LT
: case LTU
: case LE
: case LEU
:
4332 /* If the first operand is a condition code, we can't do anything
4334 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4335 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4337 && XEXP (x
, 0) != cc0_rtx
4341 rtx op0
= XEXP (x
, 0);
4342 rtx op1
= XEXP (x
, 1);
4343 enum rtx_code new_code
;
4345 if (GET_CODE (op0
) == COMPARE
)
4346 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4348 /* Simplify our comparison, if possible. */
4349 new_code
= simplify_comparison (code
, &op0
, &op1
);
4351 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4352 if only the low-order bit is possibly nonzero in X (such as when
4353 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4354 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4355 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4358 Remove any ZERO_EXTRACT we made when thinking this was a
4359 comparison. It may now be simpler to use, e.g., an AND. If a
4360 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4361 the call to make_compound_operation in the SET case. */
4363 if (STORE_FLAG_VALUE
== 1
4364 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4365 && op1
== const0_rtx
4366 && mode
== GET_MODE (op0
)
4367 && nonzero_bits (op0
, mode
) == 1)
4368 return gen_lowpart_for_combine (mode
,
4369 expand_compound_operation (op0
));
4371 else if (STORE_FLAG_VALUE
== 1
4372 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4373 && op1
== const0_rtx
4374 && mode
== GET_MODE (op0
)
4375 && (num_sign_bit_copies (op0
, mode
)
4376 == GET_MODE_BITSIZE (mode
)))
4378 op0
= expand_compound_operation (op0
);
4379 return gen_unary (NEG
, mode
, mode
,
4380 gen_lowpart_for_combine (mode
, op0
));
4383 else if (STORE_FLAG_VALUE
== 1
4384 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4385 && op1
== const0_rtx
4386 && mode
== GET_MODE (op0
)
4387 && nonzero_bits (op0
, mode
) == 1)
4389 op0
= expand_compound_operation (op0
);
4390 return gen_binary (XOR
, mode
,
4391 gen_lowpart_for_combine (mode
, op0
),
4395 else if (STORE_FLAG_VALUE
== 1
4396 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4397 && op1
== const0_rtx
4398 && mode
== GET_MODE (op0
)
4399 && (num_sign_bit_copies (op0
, mode
)
4400 == GET_MODE_BITSIZE (mode
)))
4402 op0
= expand_compound_operation (op0
);
4403 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4406 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4408 if (STORE_FLAG_VALUE
== -1
4409 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4410 && op1
== const0_rtx
4411 && (num_sign_bit_copies (op0
, mode
)
4412 == GET_MODE_BITSIZE (mode
)))
4413 return gen_lowpart_for_combine (mode
,
4414 expand_compound_operation (op0
));
4416 else if (STORE_FLAG_VALUE
== -1
4417 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4418 && op1
== const0_rtx
4419 && mode
== GET_MODE (op0
)
4420 && nonzero_bits (op0
, mode
) == 1)
4422 op0
= expand_compound_operation (op0
);
4423 return gen_unary (NEG
, mode
, mode
,
4424 gen_lowpart_for_combine (mode
, op0
));
4427 else if (STORE_FLAG_VALUE
== -1
4428 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4429 && op1
== const0_rtx
4430 && mode
== GET_MODE (op0
)
4431 && (num_sign_bit_copies (op0
, mode
)
4432 == GET_MODE_BITSIZE (mode
)))
4434 op0
= expand_compound_operation (op0
);
4435 return gen_unary (NOT
, mode
, mode
,
4436 gen_lowpart_for_combine (mode
, op0
));
4439 /* If X is 0/1, (eq X 0) is X-1. */
4440 else if (STORE_FLAG_VALUE
== -1
4441 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4442 && op1
== const0_rtx
4443 && mode
== GET_MODE (op0
)
4444 && nonzero_bits (op0
, mode
) == 1)
4446 op0
= expand_compound_operation (op0
);
4447 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4450 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4451 one bit that might be nonzero, we can convert (ne x 0) to
4452 (ashift x c) where C puts the bit in the sign bit. Remove any
4453 AND with STORE_FLAG_VALUE when we are done, since we are only
4454 going to test the sign bit. */
4455 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4456 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4457 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4458 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4459 && op1
== const0_rtx
4460 && mode
== GET_MODE (op0
)
4461 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4463 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4464 expand_compound_operation (op0
),
4465 GET_MODE_BITSIZE (mode
) - 1 - i
);
4466 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4472 /* If the code changed, return a whole new comparison. */
4473 if (new_code
!= code
)
4474 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
4476 /* Otherwise, keep this operation, but maybe change its operands.
4477 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4478 SUBST (XEXP (x
, 0), op0
);
4479 SUBST (XEXP (x
, 1), op1
);
4484 return simplify_if_then_else (x
);
4490 /* If we are processing SET_DEST, we are done. */
4494 return expand_compound_operation (x
);
4497 return simplify_set (x
);
4502 return simplify_logical (x
, last
);
4505 /* (abs (neg <foo>)) -> (abs <foo>) */
4506 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4507 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4509 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4511 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4514 /* If operand is something known to be positive, ignore the ABS. */
4515 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4516 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4517 <= HOST_BITS_PER_WIDE_INT
)
4518 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4519 & ((HOST_WIDE_INT
) 1
4520 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4524 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4525 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4526 return gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
4531 /* (ffs (*_extend <X>)) = (ffs <X>) */
4532 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4533 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4534 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4538 /* (float (sign_extend <X>)) = (float <X>). */
4539 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4540 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4548 /* If this is a shift by a constant amount, simplify it. */
4549 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4550 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4551 INTVAL (XEXP (x
, 1)));
4553 #ifdef SHIFT_COUNT_TRUNCATED
4554 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4556 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4558 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4567 rtx op0
= XEXP (x
, 0);
4568 rtx op1
= XEXP (x
, 1);
4571 if (GET_CODE (op1
) != PARALLEL
)
4573 len
= XVECLEN (op1
, 0);
4575 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4576 && GET_CODE (op0
) == VEC_CONCAT
)
4578 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4580 /* Try to find the element in the VEC_CONCAT. */
4583 if (GET_MODE (op0
) == GET_MODE (x
))
4585 if (GET_CODE (op0
) == VEC_CONCAT
)
4587 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4588 if (op0_size
< offset
)
4589 op0
= XEXP (op0
, 0);
4593 op0
= XEXP (op0
, 1);
4611 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4614 simplify_if_then_else (x
)
4617 enum machine_mode mode
= GET_MODE (x
);
4618 rtx cond
= XEXP (x
, 0);
4619 rtx
true = XEXP (x
, 1);
4620 rtx
false = XEXP (x
, 2);
4621 enum rtx_code true_code
= GET_CODE (cond
);
4622 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4626 /* Simplify storing of the truth value. */
4627 if (comparison_p
&& true == const_true_rtx
&& false == const0_rtx
)
4628 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4630 /* Also when the truth value has to be reversed. */
4631 if (comparison_p
&& reversible_comparison_p (cond
)
4632 && true == const0_rtx
&& false == const_true_rtx
)
4633 return gen_binary (reverse_condition (true_code
),
4634 mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4636 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4637 in it is being compared against certain values. Get the true and false
4638 comparisons and see if that says anything about the value of each arm. */
4640 if (comparison_p
&& reversible_comparison_p (cond
)
4641 && GET_CODE (XEXP (cond
, 0)) == REG
)
4644 rtx from
= XEXP (cond
, 0);
4645 enum rtx_code false_code
= reverse_condition (true_code
);
4646 rtx true_val
= XEXP (cond
, 1);
4647 rtx false_val
= true_val
;
4650 /* If FALSE_CODE is EQ, swap the codes and arms. */
4652 if (false_code
== EQ
)
4654 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4655 temp
= true, true = false, false = temp
;
4658 /* If we are comparing against zero and the expression being tested has
4659 only a single bit that might be nonzero, that is its value when it is
4660 not equal to zero. Similarly if it is known to be -1 or 0. */
4662 if (true_code
== EQ
&& true_val
== const0_rtx
4663 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4664 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4665 else if (true_code
== EQ
&& true_val
== const0_rtx
4666 && (num_sign_bit_copies (from
, GET_MODE (from
))
4667 == GET_MODE_BITSIZE (GET_MODE (from
))))
4668 false_code
= EQ
, false_val
= constm1_rtx
;
4670 /* Now simplify an arm if we know the value of the register in the
4671 branch and it is used in the arm. Be careful due to the potential
4672 of locally-shared RTL. */
4674 if (reg_mentioned_p (from
, true))
4675 true = subst (known_cond (copy_rtx (true), true_code
, from
, true_val
),
4676 pc_rtx
, pc_rtx
, 0, 0);
4677 if (reg_mentioned_p (from
, false))
4678 false = subst (known_cond (copy_rtx (false), false_code
,
4680 pc_rtx
, pc_rtx
, 0, 0);
4682 SUBST (XEXP (x
, 1), swapped
? false : true);
4683 SUBST (XEXP (x
, 2), swapped
? true : false);
4685 true = XEXP (x
, 1), false = XEXP (x
, 2), true_code
= GET_CODE (cond
);
4688 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4689 reversed, do so to avoid needing two sets of patterns for
4690 subtract-and-branch insns. Similarly if we have a constant in the true
4691 arm, the false arm is the same as the first operand of the comparison, or
4692 the false arm is more complicated than the true arm. */
4694 if (comparison_p
&& reversible_comparison_p (cond
)
4696 || (CONSTANT_P (true)
4697 && GET_CODE (false) != CONST_INT
&& false != pc_rtx
)
4698 || true == const0_rtx
4699 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4700 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4701 || (GET_CODE (true) == SUBREG
4702 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4703 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4704 || reg_mentioned_p (true, false)
4705 || rtx_equal_p (false, XEXP (cond
, 0))))
4707 true_code
= reverse_condition (true_code
);
4709 gen_binary (true_code
, GET_MODE (cond
), XEXP (cond
, 0),
4712 SUBST (XEXP (x
, 1), false);
4713 SUBST (XEXP (x
, 2), true);
4715 temp
= true, true = false, false = temp
, cond
= XEXP (x
, 0);
4717 /* It is possible that the conditional has been simplified out. */
4718 true_code
= GET_CODE (cond
);
4719 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4722 /* If the two arms are identical, we don't need the comparison. */
4724 if (rtx_equal_p (true, false) && ! side_effects_p (cond
))
4727 /* Convert a == b ? b : a to "a". */
4728 if (true_code
== EQ
&& ! side_effects_p (cond
)
4729 && (! FLOAT_MODE_P (mode
) || flag_fast_math
)
4730 && rtx_equal_p (XEXP (cond
, 0), false)
4731 && rtx_equal_p (XEXP (cond
, 1), true))
4733 else if (true_code
== NE
&& ! side_effects_p (cond
)
4734 && (! FLOAT_MODE_P (mode
) || flag_fast_math
)
4735 && rtx_equal_p (XEXP (cond
, 0), true)
4736 && rtx_equal_p (XEXP (cond
, 1), false))
4739 /* Look for cases where we have (abs x) or (neg (abs X)). */
4741 if (GET_MODE_CLASS (mode
) == MODE_INT
4742 && GET_CODE (false) == NEG
4743 && rtx_equal_p (true, XEXP (false, 0))
4745 && rtx_equal_p (true, XEXP (cond
, 0))
4746 && ! side_effects_p (true))
4751 return gen_unary (ABS
, mode
, mode
, true);
4754 return gen_unary (NEG
, mode
, mode
, gen_unary (ABS
, mode
, mode
, true));
4759 /* Look for MIN or MAX. */
4761 if ((! FLOAT_MODE_P (mode
) || flag_fast_math
)
4763 && rtx_equal_p (XEXP (cond
, 0), true)
4764 && rtx_equal_p (XEXP (cond
, 1), false)
4765 && ! side_effects_p (cond
))
4770 return gen_binary (SMAX
, mode
, true, false);
4773 return gen_binary (SMIN
, mode
, true, false);
4776 return gen_binary (UMAX
, mode
, true, false);
4779 return gen_binary (UMIN
, mode
, true, false);
4784 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4785 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4786 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4787 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4788 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4789 neither 1 or -1, but it isn't worth checking for. */
4791 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4792 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4794 rtx t
= make_compound_operation (true, SET
);
4795 rtx f
= make_compound_operation (false, SET
);
4796 rtx cond_op0
= XEXP (cond
, 0);
4797 rtx cond_op1
= XEXP (cond
, 1);
4798 enum rtx_code op
= NIL
, extend_op
= NIL
;
4799 enum machine_mode m
= mode
;
4800 rtx z
= 0, c1
= NULL_RTX
;
4802 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4803 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4804 || GET_CODE (t
) == ASHIFT
4805 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4806 && rtx_equal_p (XEXP (t
, 0), f
))
4807 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4809 /* If an identity-zero op is commutative, check whether there
4810 would be a match if we swapped the operands. */
4811 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4812 || GET_CODE (t
) == XOR
)
4813 && rtx_equal_p (XEXP (t
, 1), f
))
4814 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4815 else if (GET_CODE (t
) == SIGN_EXTEND
4816 && (GET_CODE (XEXP (t
, 0)) == PLUS
4817 || GET_CODE (XEXP (t
, 0)) == MINUS
4818 || GET_CODE (XEXP (t
, 0)) == IOR
4819 || GET_CODE (XEXP (t
, 0)) == XOR
4820 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4821 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4822 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4823 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4824 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4825 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4826 && (num_sign_bit_copies (f
, GET_MODE (f
))
4827 > (GET_MODE_BITSIZE (mode
)
4828 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4830 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4831 extend_op
= SIGN_EXTEND
;
4832 m
= GET_MODE (XEXP (t
, 0));
4834 else if (GET_CODE (t
) == SIGN_EXTEND
4835 && (GET_CODE (XEXP (t
, 0)) == PLUS
4836 || GET_CODE (XEXP (t
, 0)) == IOR
4837 || GET_CODE (XEXP (t
, 0)) == XOR
)
4838 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4839 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4840 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4841 && (num_sign_bit_copies (f
, GET_MODE (f
))
4842 > (GET_MODE_BITSIZE (mode
)
4843 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4845 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4846 extend_op
= SIGN_EXTEND
;
4847 m
= GET_MODE (XEXP (t
, 0));
4849 else if (GET_CODE (t
) == ZERO_EXTEND
4850 && (GET_CODE (XEXP (t
, 0)) == PLUS
4851 || GET_CODE (XEXP (t
, 0)) == MINUS
4852 || GET_CODE (XEXP (t
, 0)) == IOR
4853 || GET_CODE (XEXP (t
, 0)) == XOR
4854 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4855 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4856 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4857 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4858 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4859 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4860 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4861 && ((nonzero_bits (f
, GET_MODE (f
))
4862 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4865 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4866 extend_op
= ZERO_EXTEND
;
4867 m
= GET_MODE (XEXP (t
, 0));
4869 else if (GET_CODE (t
) == ZERO_EXTEND
4870 && (GET_CODE (XEXP (t
, 0)) == PLUS
4871 || GET_CODE (XEXP (t
, 0)) == IOR
4872 || GET_CODE (XEXP (t
, 0)) == XOR
)
4873 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4874 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4875 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4876 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4877 && ((nonzero_bits (f
, GET_MODE (f
))
4878 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4881 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4882 extend_op
= ZERO_EXTEND
;
4883 m
= GET_MODE (XEXP (t
, 0));
4888 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4889 pc_rtx
, pc_rtx
, 0, 0);
4890 temp
= gen_binary (MULT
, m
, temp
,
4891 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4892 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4893 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4895 if (extend_op
!= NIL
)
4896 temp
= gen_unary (extend_op
, mode
, m
, temp
);
4902 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4903 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4904 negation of a single bit, we can convert this operation to a shift. We
4905 can actually do this more generally, but it doesn't seem worth it. */
4907 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4908 && false == const0_rtx
&& GET_CODE (true) == CONST_INT
4909 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4910 && (i
= exact_log2 (INTVAL (true))) >= 0)
4911 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4912 == GET_MODE_BITSIZE (mode
))
4913 && (i
= exact_log2 (-INTVAL (true))) >= 0)))
4915 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4916 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4921 /* Simplify X, a SET expression. Return the new expression. */
4927 rtx src
= SET_SRC (x
);
4928 rtx dest
= SET_DEST (x
);
4929 enum machine_mode mode
4930 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4934 /* (set (pc) (return)) gets written as (return). */
4935 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4938 /* Now that we know for sure which bits of SRC we are using, see if we can
4939 simplify the expression for the object knowing that we only need the
4942 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4944 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4945 SUBST (SET_SRC (x
), src
);
4948 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4949 the comparison result and try to simplify it unless we already have used
4950 undobuf.other_insn. */
4951 if ((GET_CODE (src
) == COMPARE
4956 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4957 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4958 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4959 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4961 enum rtx_code old_code
= GET_CODE (*cc_use
);
4962 enum rtx_code new_code
;
4964 int other_changed
= 0;
4965 enum machine_mode compare_mode
= GET_MODE (dest
);
4967 if (GET_CODE (src
) == COMPARE
)
4968 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4970 op0
= src
, op1
= const0_rtx
;
4972 /* Simplify our comparison, if possible. */
4973 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4975 #ifdef EXTRA_CC_MODES
4976 /* If this machine has CC modes other than CCmode, check to see if we
4977 need to use a different CC mode here. */
4978 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4979 #endif /* EXTRA_CC_MODES */
4981 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4982 /* If the mode changed, we have to change SET_DEST, the mode in the
4983 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4984 a hard register, just build new versions with the proper mode. If it
4985 is a pseudo, we lose unless it is only time we set the pseudo, in
4986 which case we can safely change its mode. */
4987 if (compare_mode
!= GET_MODE (dest
))
4989 unsigned int regno
= REGNO (dest
);
4990 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
4992 if (regno
< FIRST_PSEUDO_REGISTER
4993 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
4995 if (regno
>= FIRST_PSEUDO_REGISTER
)
4996 SUBST (regno_reg_rtx
[regno
], new_dest
);
4998 SUBST (SET_DEST (x
), new_dest
);
4999 SUBST (XEXP (*cc_use
, 0), new_dest
);
5007 /* If the code changed, we have to build a new comparison in
5008 undobuf.other_insn. */
5009 if (new_code
!= old_code
)
5011 unsigned HOST_WIDE_INT mask
;
5013 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
5016 /* If the only change we made was to change an EQ into an NE or
5017 vice versa, OP0 has only one bit that might be nonzero, and OP1
5018 is zero, check if changing the user of the condition code will
5019 produce a valid insn. If it won't, we can keep the original code
5020 in that insn by surrounding our operation with an XOR. */
5022 if (((old_code
== NE
&& new_code
== EQ
)
5023 || (old_code
== EQ
&& new_code
== NE
))
5024 && ! other_changed
&& op1
== const0_rtx
5025 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5026 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5028 rtx pat
= PATTERN (other_insn
), note
= 0;
5030 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5031 && ! check_asm_operands (pat
)))
5033 PUT_CODE (*cc_use
, old_code
);
5036 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5044 undobuf
.other_insn
= other_insn
;
5047 /* If we are now comparing against zero, change our source if
5048 needed. If we do not use cc0, we always have a COMPARE. */
5049 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5051 SUBST (SET_SRC (x
), op0
);
5057 /* Otherwise, if we didn't previously have a COMPARE in the
5058 correct mode, we need one. */
5059 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5062 gen_rtx_combine (COMPARE
, compare_mode
, op0
, op1
));
5067 /* Otherwise, update the COMPARE if needed. */
5068 SUBST (XEXP (src
, 0), op0
);
5069 SUBST (XEXP (src
, 1), op1
);
5074 /* Get SET_SRC in a form where we have placed back any
5075 compound expressions. Then do the checks below. */
5076 src
= make_compound_operation (src
, SET
);
5077 SUBST (SET_SRC (x
), src
);
5080 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5081 and X being a REG or (subreg (reg)), we may be able to convert this to
5082 (set (subreg:m2 x) (op)).
5084 We can always do this if M1 is narrower than M2 because that means that
5085 we only care about the low bits of the result.
5087 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5088 perform a narrower operation than requested since the high-order bits will
5089 be undefined. On machine where it is defined, this transformation is safe
5090 as long as M1 and M2 have the same number of words. */
5092 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5093 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5094 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5096 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5097 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5098 #ifndef WORD_REGISTER_OPERATIONS
5099 && (GET_MODE_SIZE (GET_MODE (src
))
5100 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5102 #ifdef CLASS_CANNOT_CHANGE_MODE
5103 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5104 && (TEST_HARD_REG_BIT
5105 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5107 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5108 GET_MODE (SUBREG_REG (src
))))
5110 && (GET_CODE (dest
) == REG
5111 || (GET_CODE (dest
) == SUBREG
5112 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5114 SUBST (SET_DEST (x
),
5115 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5117 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5119 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5122 #ifdef LOAD_EXTEND_OP
5123 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5124 would require a paradoxical subreg. Replace the subreg with a
5125 zero_extend to avoid the reload that would otherwise be required. */
5127 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5128 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5129 && SUBREG_WORD (src
) == 0
5130 && (GET_MODE_SIZE (GET_MODE (src
))
5131 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5132 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5135 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5136 GET_MODE (src
), XEXP (src
, 0)));
5142 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5143 are comparing an item known to be 0 or -1 against 0, use a logical
5144 operation instead. Check for one of the arms being an IOR of the other
5145 arm with some value. We compute three terms to be IOR'ed together. In
5146 practice, at most two will be nonzero. Then we do the IOR's. */
5148 if (GET_CODE (dest
) != PC
5149 && GET_CODE (src
) == IF_THEN_ELSE
5150 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5151 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5152 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5153 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5154 #ifdef HAVE_conditional_move
5155 && ! can_conditionally_move_p (GET_MODE (src
))
5157 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5158 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5159 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5160 && ! side_effects_p (src
))
5162 rtx
true = (GET_CODE (XEXP (src
, 0)) == NE
5163 ? XEXP (src
, 1) : XEXP (src
, 2));
5164 rtx
false = (GET_CODE (XEXP (src
, 0)) == NE
5165 ? XEXP (src
, 2) : XEXP (src
, 1));
5166 rtx term1
= const0_rtx
, term2
, term3
;
5168 if (GET_CODE (true) == IOR
&& rtx_equal_p (XEXP (true, 0), false))
5169 term1
= false, true = XEXP (true, 1), false = const0_rtx
;
5170 else if (GET_CODE (true) == IOR
5171 && rtx_equal_p (XEXP (true, 1), false))
5172 term1
= false, true = XEXP (true, 0), false = const0_rtx
;
5173 else if (GET_CODE (false) == IOR
5174 && rtx_equal_p (XEXP (false, 0), true))
5175 term1
= true, false = XEXP (false, 1), true = const0_rtx
;
5176 else if (GET_CODE (false) == IOR
5177 && rtx_equal_p (XEXP (false, 1), true))
5178 term1
= true, false = XEXP (false, 0), true = const0_rtx
;
5180 term2
= gen_binary (AND
, GET_MODE (src
), XEXP (XEXP (src
, 0), 0), true);
5181 term3
= gen_binary (AND
, GET_MODE (src
),
5182 gen_unary (NOT
, GET_MODE (src
), GET_MODE (src
),
5183 XEXP (XEXP (src
, 0), 0)),
5187 gen_binary (IOR
, GET_MODE (src
),
5188 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5194 #ifdef HAVE_conditional_arithmetic
5195 /* If we have conditional arithmetic and the operand of a SET is
5196 a conditional expression, replace this with an IF_THEN_ELSE.
5197 We can either have a conditional expression or a MULT of that expression
5199 if ((GET_RTX_CLASS (GET_CODE (src
)) == '1'
5200 || GET_RTX_CLASS (GET_CODE (src
)) == '2'
5201 || GET_RTX_CLASS (GET_CODE (src
)) == 'c')
5202 && (GET_RTX_CLASS (GET_CODE (XEXP (src
, 0))) == '<'
5203 || (GET_CODE (XEXP (src
, 0)) == MULT
5204 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src
, 0), 0))) == '<'
5205 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
)))
5207 rtx cond
= XEXP (src
, 0);
5208 rtx true_val
= const1_rtx
;
5209 rtx false_arm
, true_arm
;
5211 if (GET_CODE (cond
) == MULT
)
5213 true_val
= XEXP (cond
, 1);
5214 cond
= XEXP (cond
, 0);
5217 if (GET_RTX_CLASS (GET_CODE (src
)) == '1')
5219 true_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
5220 GET_MODE (XEXP (src
, 0)), true_val
);
5221 false_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
5222 GET_MODE (XEXP (src
, 0)), const0_rtx
);
5226 true_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
5227 true_val
, XEXP (src
, 1));
5228 false_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
5229 const0_rtx
, XEXP (src
, 1));
5232 /* Canonicalize if true_arm is the simpler one. */
5233 if (GET_RTX_CLASS (GET_CODE (true_arm
)) == 'o'
5234 && GET_RTX_CLASS (GET_CODE (false_arm
)) != 'o'
5235 && reversible_comparison_p (cond
))
5237 rtx temp
= true_arm
;
5239 true_arm
= false_arm
;
5242 cond
= gen_rtx_combine (reverse_condition (GET_CODE (cond
)),
5243 GET_MODE (cond
), XEXP (cond
, 0),
5247 src
= gen_rtx_combine (IF_THEN_ELSE
, GET_MODE (src
),
5248 gen_rtx_combine (GET_CODE (cond
), VOIDmode
,
5251 true_arm
, false_arm
);
5252 SUBST (SET_SRC (x
), src
);
5256 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5257 whole thing fail. */
5258 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5260 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5263 /* Convert this into a field assignment operation, if possible. */
5264 return make_field_assignment (x
);
5267 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5268 result. LAST is nonzero if this is the last retry. */
5271 simplify_logical (x
, last
)
5275 enum machine_mode mode
= GET_MODE (x
);
5276 rtx op0
= XEXP (x
, 0);
5277 rtx op1
= XEXP (x
, 1);
5279 switch (GET_CODE (x
))
5282 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5283 insn (and may simplify more). */
5284 if (GET_CODE (op0
) == XOR
5285 && rtx_equal_p (XEXP (op0
, 0), op1
)
5286 && ! side_effects_p (op1
))
5287 x
= gen_binary (AND
, mode
,
5288 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)), op1
);
5290 if (GET_CODE (op0
) == XOR
5291 && rtx_equal_p (XEXP (op0
, 1), op1
)
5292 && ! side_effects_p (op1
))
5293 x
= gen_binary (AND
, mode
,
5294 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)), op1
);
5296 /* Similarly for (~(A ^ B)) & A. */
5297 if (GET_CODE (op0
) == NOT
5298 && GET_CODE (XEXP (op0
, 0)) == XOR
5299 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5300 && ! side_effects_p (op1
))
5301 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5303 if (GET_CODE (op0
) == NOT
5304 && GET_CODE (XEXP (op0
, 0)) == XOR
5305 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5306 && ! side_effects_p (op1
))
5307 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5309 /* We can call simplify_and_const_int only if we don't lose
5310 any (sign) bits when converting INTVAL (op1) to
5311 "unsigned HOST_WIDE_INT". */
5312 if (GET_CODE (op1
) == CONST_INT
5313 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5314 || INTVAL (op1
) > 0))
5316 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5318 /* If we have (ior (and (X C1) C2)) and the next restart would be
5319 the last, simplify this by making C1 as small as possible
5322 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5323 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5324 && GET_CODE (op1
) == CONST_INT
)
5325 return gen_binary (IOR
, mode
,
5326 gen_binary (AND
, mode
, XEXP (op0
, 0),
5327 GEN_INT (INTVAL (XEXP (op0
, 1))
5328 & ~INTVAL (op1
))), op1
);
5330 if (GET_CODE (x
) != AND
)
5333 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5334 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5335 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5338 /* Convert (A | B) & A to A. */
5339 if (GET_CODE (op0
) == IOR
5340 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5341 || rtx_equal_p (XEXP (op0
, 1), op1
))
5342 && ! side_effects_p (XEXP (op0
, 0))
5343 && ! side_effects_p (XEXP (op0
, 1)))
5346 /* In the following group of tests (and those in case IOR below),
5347 we start with some combination of logical operations and apply
5348 the distributive law followed by the inverse distributive law.
5349 Most of the time, this results in no change. However, if some of
5350 the operands are the same or inverses of each other, simplifications
5353 For example, (and (ior A B) (not B)) can occur as the result of
5354 expanding a bit field assignment. When we apply the distributive
5355 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5356 which then simplifies to (and (A (not B))).
5358 If we have (and (ior A B) C), apply the distributive law and then
5359 the inverse distributive law to see if things simplify. */
5361 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5363 x
= apply_distributive_law
5364 (gen_binary (GET_CODE (op0
), mode
,
5365 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5366 gen_binary (AND
, mode
, XEXP (op0
, 1),
5368 if (GET_CODE (x
) != AND
)
5372 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5373 return apply_distributive_law
5374 (gen_binary (GET_CODE (op1
), mode
,
5375 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5376 gen_binary (AND
, mode
, XEXP (op1
, 1),
5379 /* Similarly, taking advantage of the fact that
5380 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5382 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5383 return apply_distributive_law
5384 (gen_binary (XOR
, mode
,
5385 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5386 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5389 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5390 return apply_distributive_law
5391 (gen_binary (XOR
, mode
,
5392 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5393 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5397 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5398 if (GET_CODE (op1
) == CONST_INT
5399 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5400 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5403 /* Convert (A & B) | A to A. */
5404 if (GET_CODE (op0
) == AND
5405 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5406 || rtx_equal_p (XEXP (op0
, 1), op1
))
5407 && ! side_effects_p (XEXP (op0
, 0))
5408 && ! side_effects_p (XEXP (op0
, 1)))
5411 /* If we have (ior (and A B) C), apply the distributive law and then
5412 the inverse distributive law to see if things simplify. */
5414 if (GET_CODE (op0
) == AND
)
5416 x
= apply_distributive_law
5417 (gen_binary (AND
, mode
,
5418 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5419 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5422 if (GET_CODE (x
) != IOR
)
5426 if (GET_CODE (op1
) == AND
)
5428 x
= apply_distributive_law
5429 (gen_binary (AND
, mode
,
5430 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5431 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5434 if (GET_CODE (x
) != IOR
)
5438 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5439 mode size to (rotate A CX). */
5441 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5442 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5443 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5444 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5445 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5446 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5447 == GET_MODE_BITSIZE (mode
)))
5448 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5449 (GET_CODE (op0
) == ASHIFT
5450 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5452 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5453 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5454 does not affect any of the bits in OP1, it can really be done
5455 as a PLUS and we can associate. We do this by seeing if OP1
5456 can be safely shifted left C bits. */
5457 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5458 && GET_CODE (XEXP (op0
, 0)) == PLUS
5459 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5460 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5461 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5463 int count
= INTVAL (XEXP (op0
, 1));
5464 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5466 if (mask
>> count
== INTVAL (op1
)
5467 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5469 SUBST (XEXP (XEXP (op0
, 0), 1),
5470 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5477 /* If we are XORing two things that have no bits in common,
5478 convert them into an IOR. This helps to detect rotation encoded
5479 using those methods and possibly other simplifications. */
5481 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5482 && (nonzero_bits (op0
, mode
)
5483 & nonzero_bits (op1
, mode
)) == 0)
5484 return (gen_binary (IOR
, mode
, op0
, op1
));
5486 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5487 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5490 int num_negated
= 0;
5492 if (GET_CODE (op0
) == NOT
)
5493 num_negated
++, op0
= XEXP (op0
, 0);
5494 if (GET_CODE (op1
) == NOT
)
5495 num_negated
++, op1
= XEXP (op1
, 0);
5497 if (num_negated
== 2)
5499 SUBST (XEXP (x
, 0), op0
);
5500 SUBST (XEXP (x
, 1), op1
);
5502 else if (num_negated
== 1)
5503 return gen_unary (NOT
, mode
, mode
, gen_binary (XOR
, mode
, op0
, op1
));
5506 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5507 correspond to a machine insn or result in further simplifications
5508 if B is a constant. */
5510 if (GET_CODE (op0
) == AND
5511 && rtx_equal_p (XEXP (op0
, 1), op1
)
5512 && ! side_effects_p (op1
))
5513 return gen_binary (AND
, mode
,
5514 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)),
5517 else if (GET_CODE (op0
) == AND
5518 && rtx_equal_p (XEXP (op0
, 0), op1
)
5519 && ! side_effects_p (op1
))
5520 return gen_binary (AND
, mode
,
5521 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)),
5524 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5525 comparison if STORE_FLAG_VALUE is 1. */
5526 if (STORE_FLAG_VALUE
== 1
5527 && op1
== const1_rtx
5528 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5529 && reversible_comparison_p (op0
))
5530 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
5531 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
5533 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5534 is (lt foo (const_int 0)), so we can perform the above
5535 simplification if STORE_FLAG_VALUE is 1. */
5537 if (STORE_FLAG_VALUE
== 1
5538 && op1
== const1_rtx
5539 && GET_CODE (op0
) == LSHIFTRT
5540 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5541 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5542 return gen_rtx_combine (GE
, mode
, XEXP (op0
, 0), const0_rtx
);
5544 /* (xor (comparison foo bar) (const_int sign-bit))
5545 when STORE_FLAG_VALUE is the sign bit. */
5546 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5547 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5548 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5549 && op1
== const_true_rtx
5550 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5551 && reversible_comparison_p (op0
))
5552 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
5553 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
5564 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5565 operations" because they can be replaced with two more basic operations.
5566 ZERO_EXTEND is also considered "compound" because it can be replaced with
5567 an AND operation, which is simpler, though only one operation.
5569 The function expand_compound_operation is called with an rtx expression
5570 and will convert it to the appropriate shifts and AND operations,
5571 simplifying at each stage.
5573 The function make_compound_operation is called to convert an expression
5574 consisting of shifts and ANDs into the equivalent compound expression.
5575 It is the inverse of this function, loosely speaking. */
5578 expand_compound_operation (x
)
5581 unsigned HOST_WIDE_INT pos
= 0, len
;
5583 unsigned int modewidth
;
5586 switch (GET_CODE (x
))
5591 /* We can't necessarily use a const_int for a multiword mode;
5592 it depends on implicitly extending the value.
5593 Since we don't know the right way to extend it,
5594 we can't tell whether the implicit way is right.
5596 Even for a mode that is no wider than a const_int,
5597 we can't win, because we need to sign extend one of its bits through
5598 the rest of it, and we don't know which bit. */
5599 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5602 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5603 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5604 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5605 reloaded. If not for that, MEM's would very rarely be safe.
5607 Reject MODEs bigger than a word, because we might not be able
5608 to reference a two-register group starting with an arbitrary register
5609 (and currently gen_lowpart might crash for a SUBREG). */
5611 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5614 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5615 /* If the inner object has VOIDmode (the only way this can happen
5616 is if it is a ASM_OPERANDS), we can't do anything since we don't
5617 know how much masking to do. */
5626 /* If the operand is a CLOBBER, just return it. */
5627 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5630 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5631 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5632 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5635 len
= INTVAL (XEXP (x
, 1));
5636 pos
= INTVAL (XEXP (x
, 2));
5638 /* If this goes outside the object being extracted, replace the object
5639 with a (use (mem ...)) construct that only combine understands
5640 and is used only for this purpose. */
5641 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5642 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5644 if (BITS_BIG_ENDIAN
)
5645 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5652 /* Convert sign extension to zero extension, if we know that the high
5653 bit is not set, as this is easier to optimize. It will be converted
5654 back to cheaper alternative in make_extraction. */
5655 if (GET_CODE (x
) == SIGN_EXTEND
5656 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5657 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5658 & ~(((unsigned HOST_WIDE_INT
)
5659 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5663 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5664 return expand_compound_operation (temp
);
5667 /* We can optimize some special cases of ZERO_EXTEND. */
5668 if (GET_CODE (x
) == ZERO_EXTEND
)
5670 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5671 know that the last value didn't have any inappropriate bits
5673 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5674 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5675 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5676 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5677 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5678 return XEXP (XEXP (x
, 0), 0);
5680 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5681 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5682 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5683 && subreg_lowpart_p (XEXP (x
, 0))
5684 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5685 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5686 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5687 return SUBREG_REG (XEXP (x
, 0));
5689 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5690 is a comparison and STORE_FLAG_VALUE permits. This is like
5691 the first case, but it works even when GET_MODE (x) is larger
5692 than HOST_WIDE_INT. */
5693 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5694 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5695 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5696 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5697 <= HOST_BITS_PER_WIDE_INT
)
5698 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5699 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5700 return XEXP (XEXP (x
, 0), 0);
5702 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5703 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5704 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5705 && subreg_lowpart_p (XEXP (x
, 0))
5706 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5707 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5708 <= HOST_BITS_PER_WIDE_INT
)
5709 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5710 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5711 return SUBREG_REG (XEXP (x
, 0));
5715 /* If we reach here, we want to return a pair of shifts. The inner
5716 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5717 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5718 logical depending on the value of UNSIGNEDP.
5720 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5721 converted into an AND of a shift.
5723 We must check for the case where the left shift would have a negative
5724 count. This can happen in a case like (x >> 31) & 255 on machines
5725 that can't shift by a constant. On those machines, we would first
5726 combine the shift with the AND to produce a variable-position
5727 extraction. Then the constant of 31 would be substituted in to produce
5728 a such a position. */
5730 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5731 if (modewidth
+ len
>= pos
)
5732 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5734 simplify_shift_const (NULL_RTX
, ASHIFT
,
5737 modewidth
- pos
- len
),
5740 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5741 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5742 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5745 ((HOST_WIDE_INT
) 1 << len
) - 1);
5747 /* Any other cases we can't handle. */
5750 /* If we couldn't do this for some reason, return the original
5752 if (GET_CODE (tem
) == CLOBBER
)
5758 /* X is a SET which contains an assignment of one object into
5759 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5760 or certain SUBREGS). If possible, convert it into a series of
5763 We half-heartedly support variable positions, but do not at all
5764 support variable lengths. */
5767 expand_field_assignment (x
)
5771 rtx pos
; /* Always counts from low bit. */
5774 enum machine_mode compute_mode
;
5776 /* Loop until we find something we can't simplify. */
5779 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5780 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5782 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5783 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5784 pos
= GEN_INT (BITS_PER_WORD
* SUBREG_WORD (XEXP (SET_DEST (x
), 0)));
5786 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5787 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5789 inner
= XEXP (SET_DEST (x
), 0);
5790 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5791 pos
= XEXP (SET_DEST (x
), 2);
5793 /* If the position is constant and spans the width of INNER,
5794 surround INNER with a USE to indicate this. */
5795 if (GET_CODE (pos
) == CONST_INT
5796 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5797 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5799 if (BITS_BIG_ENDIAN
)
5801 if (GET_CODE (pos
) == CONST_INT
)
5802 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5804 else if (GET_CODE (pos
) == MINUS
5805 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5806 && (INTVAL (XEXP (pos
, 1))
5807 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5808 /* If position is ADJUST - X, new position is X. */
5809 pos
= XEXP (pos
, 0);
5811 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5812 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5818 /* A SUBREG between two modes that occupy the same numbers of words
5819 can be done by moving the SUBREG to the source. */
5820 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5821 /* We need SUBREGs to compute nonzero_bits properly. */
5822 && nonzero_sign_valid
5823 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5824 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5825 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5826 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5828 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5829 gen_lowpart_for_combine
5830 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5837 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5838 inner
= SUBREG_REG (inner
);
5840 compute_mode
= GET_MODE (inner
);
5842 /* Don't attempt bitwise arithmetic on non-integral modes. */
5843 if (! INTEGRAL_MODE_P (compute_mode
))
5845 enum machine_mode imode
;
5847 /* Something is probably seriously wrong if this matches. */
5848 if (! FLOAT_MODE_P (compute_mode
))
5851 /* Try to find an integral mode to pun with. */
5852 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5853 if (imode
== BLKmode
)
5856 compute_mode
= imode
;
5857 inner
= gen_lowpart_for_combine (imode
, inner
);
5860 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5861 if (len
< HOST_BITS_PER_WIDE_INT
)
5862 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5866 /* Now compute the equivalent expression. Make a copy of INNER
5867 for the SET_DEST in case it is a MEM into which we will substitute;
5868 we don't want shared RTL in that case. */
5870 (VOIDmode
, copy_rtx (inner
),
5871 gen_binary (IOR
, compute_mode
,
5872 gen_binary (AND
, compute_mode
,
5873 gen_unary (NOT
, compute_mode
,
5879 gen_binary (ASHIFT
, compute_mode
,
5880 gen_binary (AND
, compute_mode
,
5881 gen_lowpart_for_combine
5882 (compute_mode
, SET_SRC (x
)),
5890 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5891 it is an RTX that represents a variable starting position; otherwise,
5892 POS is the (constant) starting bit position (counted from the LSB).
5894 INNER may be a USE. This will occur when we started with a bitfield
5895 that went outside the boundary of the object in memory, which is
5896 allowed on most machines. To isolate this case, we produce a USE
5897 whose mode is wide enough and surround the MEM with it. The only
5898 code that understands the USE is this routine. If it is not removed,
5899 it will cause the resulting insn not to match.
5901 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5904 IN_DEST is non-zero if this is a reference in the destination of a
5905 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5906 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5909 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5910 ZERO_EXTRACT should be built even for bits starting at bit 0.
5912 MODE is the desired mode of the result (if IN_DEST == 0).
5914 The result is an RTX for the extraction or NULL_RTX if the target
5918 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5919 unsignedp
, in_dest
, in_compare
)
5920 enum machine_mode mode
;
5924 unsigned HOST_WIDE_INT len
;
5926 int in_dest
, in_compare
;
5928 /* This mode describes the size of the storage area
5929 to fetch the overall value from. Within that, we
5930 ignore the POS lowest bits, etc. */
5931 enum machine_mode is_mode
= GET_MODE (inner
);
5932 enum machine_mode inner_mode
;
5933 enum machine_mode wanted_inner_mode
= byte_mode
;
5934 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5935 enum machine_mode pos_mode
= word_mode
;
5936 enum machine_mode extraction_mode
= word_mode
;
5937 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5940 rtx orig_pos_rtx
= pos_rtx
;
5941 HOST_WIDE_INT orig_pos
;
5943 /* Get some information about INNER and get the innermost object. */
5944 if (GET_CODE (inner
) == USE
)
5945 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5946 /* We don't need to adjust the position because we set up the USE
5947 to pretend that it was a full-word object. */
5948 spans_byte
= 1, inner
= XEXP (inner
, 0);
5949 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5951 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5952 consider just the QI as the memory to extract from.
5953 The subreg adds or removes high bits; its mode is
5954 irrelevant to the meaning of this extraction,
5955 since POS and LEN count from the lsb. */
5956 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5957 is_mode
= GET_MODE (SUBREG_REG (inner
));
5958 inner
= SUBREG_REG (inner
);
5961 inner_mode
= GET_MODE (inner
);
5963 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5964 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5966 /* See if this can be done without an extraction. We never can if the
5967 width of the field is not the same as that of some integer mode. For
5968 registers, we can only avoid the extraction if the position is at the
5969 low-order bit and this is either not in the destination or we have the
5970 appropriate STRICT_LOW_PART operation available.
5972 For MEM, we can avoid an extract if the field starts on an appropriate
5973 boundary and we can change the mode of the memory reference. However,
5974 we cannot directly access the MEM if we have a USE and the underlying
5975 MEM is not TMODE. This combination means that MEM was being used in a
5976 context where bits outside its mode were being referenced; that is only
5977 valid in bit-field insns. */
5979 if (tmode
!= BLKmode
5980 && ! (spans_byte
&& inner_mode
!= tmode
)
5981 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5982 && GET_CODE (inner
) != MEM
5984 || (GET_CODE (inner
) == REG
5985 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
5986 != CODE_FOR_nothing
))))
5987 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5989 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5990 : BITS_PER_UNIT
)) == 0
5991 /* We can't do this if we are widening INNER_MODE (it
5992 may not be aligned, for one thing). */
5993 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5994 && (inner_mode
== tmode
5995 || (! mode_dependent_address_p (XEXP (inner
, 0))
5996 && ! MEM_VOLATILE_P (inner
))))))
5998 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5999 field. If the original and current mode are the same, we need not
6000 adjust the offset. Otherwise, we do if bytes big endian.
6002 If INNER is not a MEM, get a piece consisting of just the field
6003 of interest (in this case POS % BITS_PER_WORD must be 0). */
6005 if (GET_CODE (inner
) == MEM
)
6008 /* POS counts from lsb, but make OFFSET count in memory order. */
6009 if (BYTES_BIG_ENDIAN
)
6010 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6012 offset
= pos
/ BITS_PER_UNIT
;
6014 new = gen_rtx_MEM (tmode
, plus_constant (XEXP (inner
, 0), offset
));
6015 MEM_COPY_ATTRIBUTES (new, inner
);
6017 else if (GET_CODE (inner
) == REG
)
6019 /* We can't call gen_lowpart_for_combine here since we always want
6020 a SUBREG and it would sometimes return a new hard register. */
6021 if (tmode
!= inner_mode
)
6022 new = gen_rtx_SUBREG (tmode
, inner
,
6024 && (GET_MODE_SIZE (inner_mode
)
6026 ? (((GET_MODE_SIZE (inner_mode
)
6027 - GET_MODE_SIZE (tmode
))
6029 - pos
/ BITS_PER_WORD
)
6030 : pos
/ BITS_PER_WORD
));
6035 new = force_to_mode (inner
, tmode
,
6036 len
>= HOST_BITS_PER_WIDE_INT
6037 ? ~(unsigned HOST_WIDE_INT
) 0
6038 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6041 /* If this extraction is going into the destination of a SET,
6042 make a STRICT_LOW_PART unless we made a MEM. */
6045 return (GET_CODE (new) == MEM
? new
6046 : (GET_CODE (new) != SUBREG
6047 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6048 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
6053 /* If we know that no extraneous bits are set, and that the high
6054 bit is not set, convert the extraction to the cheaper of
6055 sign and zero extension, that are equivalent in these cases. */
6056 if (flag_expensive_optimizations
6057 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6058 && ((nonzero_bits (new, tmode
)
6059 & ~(((unsigned HOST_WIDE_INT
)
6060 GET_MODE_MASK (tmode
))
6064 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6065 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6067 /* Prefer ZERO_EXTENSION, since it gives more information to
6069 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6074 /* Otherwise, sign- or zero-extend unless we already are in the
6077 return (gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6081 /* Unless this is a COMPARE or we have a funny memory reference,
6082 don't do anything with zero-extending field extracts starting at
6083 the low-order bit since they are simple AND operations. */
6084 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6085 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6088 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6089 we would be spanning bytes or if the position is not a constant and the
6090 length is not 1. In all other cases, we would only be going outside
6091 our object in cases when an original shift would have been
6093 if (! spans_byte
&& GET_CODE (inner
) == MEM
6094 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6095 || (pos_rtx
!= 0 && len
!= 1)))
6098 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6099 and the mode for the result. */
6103 wanted_inner_reg_mode
6104 = insn_data
[(int) CODE_FOR_insv
].operand
[0].mode
;
6105 if (wanted_inner_reg_mode
== VOIDmode
)
6106 wanted_inner_reg_mode
= word_mode
;
6108 pos_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[2].mode
;
6109 if (pos_mode
== VOIDmode
)
6110 pos_mode
= word_mode
;
6112 extraction_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
6113 if (extraction_mode
== VOIDmode
)
6114 extraction_mode
= word_mode
;
6119 if (! in_dest
&& unsignedp
)
6121 wanted_inner_reg_mode
6122 = insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
6123 if (wanted_inner_reg_mode
== VOIDmode
)
6124 wanted_inner_reg_mode
= word_mode
;
6126 pos_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[3].mode
;
6127 if (pos_mode
== VOIDmode
)
6128 pos_mode
= word_mode
;
6130 extraction_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
6131 if (extraction_mode
== VOIDmode
)
6132 extraction_mode
= word_mode
;
6137 if (! in_dest
&& ! unsignedp
)
6139 wanted_inner_reg_mode
6140 = insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
6141 if (wanted_inner_reg_mode
== VOIDmode
)
6142 wanted_inner_reg_mode
= word_mode
;
6144 pos_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[3].mode
;
6145 if (pos_mode
== VOIDmode
)
6146 pos_mode
= word_mode
;
6148 extraction_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
6149 if (extraction_mode
== VOIDmode
)
6150 extraction_mode
= word_mode
;
6154 /* Never narrow an object, since that might not be safe. */
6156 if (mode
!= VOIDmode
6157 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6158 extraction_mode
= mode
;
6160 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6161 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6162 pos_mode
= GET_MODE (pos_rtx
);
6164 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6165 if we have to change the mode of memory and cannot, the desired mode is
6167 if (GET_CODE (inner
) != MEM
)
6168 wanted_inner_mode
= wanted_inner_reg_mode
;
6169 else if (inner_mode
!= wanted_inner_mode
6170 && (mode_dependent_address_p (XEXP (inner
, 0))
6171 || MEM_VOLATILE_P (inner
)))
6172 wanted_inner_mode
= extraction_mode
;
6176 if (BITS_BIG_ENDIAN
)
6178 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6179 BITS_BIG_ENDIAN style. If position is constant, compute new
6180 position. Otherwise, build subtraction.
6181 Note that POS is relative to the mode of the original argument.
6182 If it's a MEM we need to recompute POS relative to that.
6183 However, if we're extracting from (or inserting into) a register,
6184 we want to recompute POS relative to wanted_inner_mode. */
6185 int width
= (GET_CODE (inner
) == MEM
6186 ? GET_MODE_BITSIZE (is_mode
)
6187 : GET_MODE_BITSIZE (wanted_inner_mode
));
6190 pos
= width
- len
- pos
;
6193 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
6194 GEN_INT (width
- len
), pos_rtx
);
6195 /* POS may be less than 0 now, but we check for that below.
6196 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6199 /* If INNER has a wider mode, make it smaller. If this is a constant
6200 extract, try to adjust the byte to point to the byte containing
6202 if (wanted_inner_mode
!= VOIDmode
6203 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6204 && ((GET_CODE (inner
) == MEM
6205 && (inner_mode
== wanted_inner_mode
6206 || (! mode_dependent_address_p (XEXP (inner
, 0))
6207 && ! MEM_VOLATILE_P (inner
))))))
6211 /* The computations below will be correct if the machine is big
6212 endian in both bits and bytes or little endian in bits and bytes.
6213 If it is mixed, we must adjust. */
6215 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6216 adjust OFFSET to compensate. */
6217 if (BYTES_BIG_ENDIAN
6219 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6220 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6222 /* If this is a constant position, we can move to the desired byte. */
6225 offset
+= pos
/ BITS_PER_UNIT
;
6226 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6229 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6231 && is_mode
!= wanted_inner_mode
)
6232 offset
= (GET_MODE_SIZE (is_mode
)
6233 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6235 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6237 rtx newmem
= gen_rtx_MEM (wanted_inner_mode
,
6238 plus_constant (XEXP (inner
, 0), offset
));
6240 MEM_COPY_ATTRIBUTES (newmem
, inner
);
6245 /* If INNER is not memory, we can always get it into the proper mode. If we
6246 are changing its mode, POS must be a constant and smaller than the size
6248 else if (GET_CODE (inner
) != MEM
)
6250 if (GET_MODE (inner
) != wanted_inner_mode
6252 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6255 inner
= force_to_mode (inner
, wanted_inner_mode
,
6257 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6258 ? ~(unsigned HOST_WIDE_INT
) 0
6259 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6264 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6265 have to zero extend. Otherwise, we can just use a SUBREG. */
6267 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6269 rtx temp
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
6271 /* If we know that no extraneous bits are set, and that the high
6272 bit is not set, convert extraction to cheaper one - eighter
6273 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6275 if (flag_expensive_optimizations
6276 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6277 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6278 & ~(((unsigned HOST_WIDE_INT
)
6279 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6283 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6285 /* Prefer ZERO_EXTENSION, since it gives more information to
6287 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6292 else if (pos_rtx
!= 0
6293 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6294 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6296 /* Make POS_RTX unless we already have it and it is correct. If we don't
6297 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6299 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6300 pos_rtx
= orig_pos_rtx
;
6302 else if (pos_rtx
== 0)
6303 pos_rtx
= GEN_INT (pos
);
6305 /* Make the required operation. See if we can use existing rtx. */
6306 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6307 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6309 new = gen_lowpart_for_combine (mode
, new);
6314 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6315 with any other operations in X. Return X without that shift if so. */
6318 extract_left_shift (x
, count
)
6322 enum rtx_code code
= GET_CODE (x
);
6323 enum machine_mode mode
= GET_MODE (x
);
6329 /* This is the shift itself. If it is wide enough, we will return
6330 either the value being shifted if the shift count is equal to
6331 COUNT or a shift for the difference. */
6332 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6333 && INTVAL (XEXP (x
, 1)) >= count
)
6334 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6335 INTVAL (XEXP (x
, 1)) - count
);
6339 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6340 return gen_unary (code
, mode
, mode
, tem
);
6344 case PLUS
: case IOR
: case XOR
: case AND
:
6345 /* If we can safely shift this constant and we find the inner shift,
6346 make a new operation. */
6347 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6348 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6349 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6350 return gen_binary (code
, mode
, tem
,
6351 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6362 /* Look at the expression rooted at X. Look for expressions
6363 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6364 Form these expressions.
6366 Return the new rtx, usually just X.
6368 Also, for machines like the Vax that don't have logical shift insns,
6369 try to convert logical to arithmetic shift operations in cases where
6370 they are equivalent. This undoes the canonicalizations to logical
6371 shifts done elsewhere.
6373 We try, as much as possible, to re-use rtl expressions to save memory.
6375 IN_CODE says what kind of expression we are processing. Normally, it is
6376 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6377 being kludges), it is MEM. When processing the arguments of a comparison
6378 or a COMPARE against zero, it is COMPARE. */
6381 make_compound_operation (x
, in_code
)
6383 enum rtx_code in_code
;
6385 enum rtx_code code
= GET_CODE (x
);
6386 enum machine_mode mode
= GET_MODE (x
);
6387 int mode_width
= GET_MODE_BITSIZE (mode
);
6389 enum rtx_code next_code
;
6395 /* Select the code to be used in recursive calls. Once we are inside an
6396 address, we stay there. If we have a comparison, set to COMPARE,
6397 but once inside, go back to our default of SET. */
6399 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6400 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6401 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6402 : in_code
== COMPARE
? SET
: in_code
);
6404 /* Process depending on the code of this operation. If NEW is set
6405 non-zero, it will be returned. */
6410 /* Convert shifts by constants into multiplications if inside
6412 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6413 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6414 && INTVAL (XEXP (x
, 1)) >= 0)
6416 new = make_compound_operation (XEXP (x
, 0), next_code
);
6417 new = gen_rtx_combine (MULT
, mode
, new,
6418 GEN_INT ((HOST_WIDE_INT
) 1
6419 << INTVAL (XEXP (x
, 1))));
6424 /* If the second operand is not a constant, we can't do anything
6426 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6429 /* If the constant is a power of two minus one and the first operand
6430 is a logical right shift, make an extraction. */
6431 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6432 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6434 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6435 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6436 0, in_code
== COMPARE
);
6439 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6440 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6441 && subreg_lowpart_p (XEXP (x
, 0))
6442 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6443 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6445 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6447 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6448 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6449 0, in_code
== COMPARE
);
6451 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6452 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6453 || GET_CODE (XEXP (x
, 0)) == IOR
)
6454 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6455 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6456 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6458 /* Apply the distributive law, and then try to make extractions. */
6459 new = gen_rtx_combine (GET_CODE (XEXP (x
, 0)), mode
,
6460 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6462 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6464 new = make_compound_operation (new, in_code
);
6467 /* If we are have (and (rotate X C) M) and C is larger than the number
6468 of bits in M, this is an extraction. */
6470 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6471 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6472 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6473 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6475 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6476 new = make_extraction (mode
, new,
6477 (GET_MODE_BITSIZE (mode
)
6478 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6479 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6482 /* On machines without logical shifts, if the operand of the AND is
6483 a logical shift and our mask turns off all the propagated sign
6484 bits, we can replace the logical shift with an arithmetic shift. */
6485 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6486 && (lshr_optab
->handlers
[(int) mode
].insn_code
6487 == CODE_FOR_nothing
)
6488 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6489 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6490 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6491 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6492 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6494 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6496 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6497 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6499 gen_rtx_combine (ASHIFTRT
, mode
,
6500 make_compound_operation (XEXP (XEXP (x
, 0), 0),
6502 XEXP (XEXP (x
, 0), 1)));
6505 /* If the constant is one less than a power of two, this might be
6506 representable by an extraction even if no shift is present.
6507 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6508 we are in a COMPARE. */
6509 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6510 new = make_extraction (mode
,
6511 make_compound_operation (XEXP (x
, 0),
6513 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6515 /* If we are in a comparison and this is an AND with a power of two,
6516 convert this into the appropriate bit extract. */
6517 else if (in_code
== COMPARE
6518 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6519 new = make_extraction (mode
,
6520 make_compound_operation (XEXP (x
, 0),
6522 i
, NULL_RTX
, 1, 1, 0, 1);
6527 /* If the sign bit is known to be zero, replace this with an
6528 arithmetic shift. */
6529 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
6530 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6531 && mode_width
<= HOST_BITS_PER_WIDE_INT
6532 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6534 new = gen_rtx_combine (ASHIFTRT
, mode
,
6535 make_compound_operation (XEXP (x
, 0),
6541 /* ... fall through ... */
6547 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6548 this is a SIGN_EXTRACT. */
6549 if (GET_CODE (rhs
) == CONST_INT
6550 && GET_CODE (lhs
) == ASHIFT
6551 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6552 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6554 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6555 new = make_extraction (mode
, new,
6556 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6557 NULL_RTX
, mode_width
- INTVAL (rhs
),
6558 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6562 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6563 If so, try to merge the shifts into a SIGN_EXTEND. We could
6564 also do this for some cases of SIGN_EXTRACT, but it doesn't
6565 seem worth the effort; the case checked for occurs on Alpha. */
6567 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6568 && ! (GET_CODE (lhs
) == SUBREG
6569 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6570 && GET_CODE (rhs
) == CONST_INT
6571 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6572 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6573 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6574 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6575 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6580 /* Call ourselves recursively on the inner expression. If we are
6581 narrowing the object and it has a different RTL code from
6582 what it originally did, do this SUBREG as a force_to_mode. */
6584 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6585 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6586 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6587 && subreg_lowpart_p (x
))
6589 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6592 /* If we have something other than a SUBREG, we might have
6593 done an expansion, so rerun outselves. */
6594 if (GET_CODE (newer
) != SUBREG
)
6595 newer
= make_compound_operation (newer
, in_code
);
6600 /* If this is a paradoxical subreg, and the new code is a sign or
6601 zero extension, omit the subreg and widen the extension. If it
6602 is a regular subreg, we can still get rid of the subreg by not
6603 widening so much, or in fact removing the extension entirely. */
6604 if ((GET_CODE (tem
) == SIGN_EXTEND
6605 || GET_CODE (tem
) == ZERO_EXTEND
)
6606 && subreg_lowpart_p (x
))
6608 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6609 || (GET_MODE_SIZE (mode
) >
6610 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6611 tem
= gen_rtx_combine (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6613 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6624 x
= gen_lowpart_for_combine (mode
, new);
6625 code
= GET_CODE (x
);
6628 /* Now recursively process each operand of this operation. */
6629 fmt
= GET_RTX_FORMAT (code
);
6630 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6633 new = make_compound_operation (XEXP (x
, i
), next_code
);
6634 SUBST (XEXP (x
, i
), new);
6640 /* Given M see if it is a value that would select a field of bits
6641 within an item, but not the entire word. Return -1 if not.
6642 Otherwise, return the starting position of the field, where 0 is the
6645 *PLEN is set to the length of the field. */
6648 get_pos_from_mask (m
, plen
)
6649 unsigned HOST_WIDE_INT m
;
6650 unsigned HOST_WIDE_INT
*plen
;
6652 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6653 int pos
= exact_log2 (m
& -m
);
6659 /* Now shift off the low-order zero bits and see if we have a power of
6661 len
= exact_log2 ((m
>> pos
) + 1);
6670 /* See if X can be simplified knowing that we will only refer to it in
6671 MODE and will only refer to those bits that are nonzero in MASK.
6672 If other bits are being computed or if masking operations are done
6673 that select a superset of the bits in MASK, they can sometimes be
6676 Return a possibly simplified expression, but always convert X to
6677 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6679 Also, if REG is non-zero and X is a register equal in value to REG,
6682 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6683 are all off in X. This is used when X will be complemented, by either
6684 NOT, NEG, or XOR. */
6687 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6689 enum machine_mode mode
;
6690 unsigned HOST_WIDE_INT mask
;
6694 enum rtx_code code
= GET_CODE (x
);
6695 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6696 enum machine_mode op_mode
;
6697 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6700 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6701 code below will do the wrong thing since the mode of such an
6702 expression is VOIDmode.
6704 Also do nothing if X is a CLOBBER; this can happen if X was
6705 the return value from a call to gen_lowpart_for_combine. */
6706 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6709 /* We want to perform the operation is its present mode unless we know
6710 that the operation is valid in MODE, in which case we do the operation
6712 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6713 && code_to_optab
[(int) code
] != 0
6714 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
6715 != CODE_FOR_nothing
))
6716 ? mode
: GET_MODE (x
));
6718 /* It is not valid to do a right-shift in a narrower mode
6719 than the one it came in with. */
6720 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6721 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6722 op_mode
= GET_MODE (x
);
6724 /* Truncate MASK to fit OP_MODE. */
6726 mask
&= GET_MODE_MASK (op_mode
);
6728 /* When we have an arithmetic operation, or a shift whose count we
6729 do not know, we need to assume that all bit the up to the highest-order
6730 bit in MASK will be needed. This is how we form such a mask. */
6732 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6733 ? GET_MODE_MASK (op_mode
)
6734 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6737 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6739 /* Determine what bits of X are guaranteed to be (non)zero. */
6740 nonzero
= nonzero_bits (x
, mode
);
6742 /* If none of the bits in X are needed, return a zero. */
6743 if (! just_select
&& (nonzero
& mask
) == 0)
6746 /* If X is a CONST_INT, return a new one. Do this here since the
6747 test below will fail. */
6748 if (GET_CODE (x
) == CONST_INT
)
6750 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6751 int width
= GET_MODE_BITSIZE (mode
);
6753 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6754 number, sign extend it. */
6755 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6756 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6757 cval
|= (HOST_WIDE_INT
) -1 << width
;
6759 return GEN_INT (cval
);
6762 /* If X is narrower than MODE and we want all the bits in X's mode, just
6763 get X in the proper mode. */
6764 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6765 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6766 return gen_lowpart_for_combine (mode
, x
);
6768 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6769 MASK are already known to be zero in X, we need not do anything. */
6770 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6776 /* If X is a (clobber (const_int)), return it since we know we are
6777 generating something that won't match. */
6781 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6782 spanned the boundary of the MEM. If we are now masking so it is
6783 within that boundary, we don't need the USE any more. */
6784 if (! BITS_BIG_ENDIAN
6785 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6786 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6793 x
= expand_compound_operation (x
);
6794 if (GET_CODE (x
) != code
)
6795 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6799 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6800 || rtx_equal_p (reg
, get_last_value (x
))))
6805 if (subreg_lowpart_p (x
)
6806 /* We can ignore the effect of this SUBREG if it narrows the mode or
6807 if the constant masks to zero all the bits the mode doesn't
6809 && ((GET_MODE_SIZE (GET_MODE (x
))
6810 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6812 & GET_MODE_MASK (GET_MODE (x
))
6813 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6814 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6818 /* If this is an AND with a constant, convert it into an AND
6819 whose constant is the AND of that constant with MASK. If it
6820 remains an AND of MASK, delete it since it is redundant. */
6822 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6824 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6825 mask
& INTVAL (XEXP (x
, 1)));
6827 /* If X is still an AND, see if it is an AND with a mask that
6828 is just some low-order bits. If so, and it is MASK, we don't
6831 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6832 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6835 /* If it remains an AND, try making another AND with the bits
6836 in the mode mask that aren't in MASK turned on. If the
6837 constant in the AND is wide enough, this might make a
6838 cheaper constant. */
6840 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6841 && GET_MODE_MASK (GET_MODE (x
)) != mask
6842 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6844 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6845 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6846 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6849 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6850 number, sign extend it. */
6851 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6852 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6853 cval
|= (HOST_WIDE_INT
) -1 << width
;
6855 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6856 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6866 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6867 low-order bits (as in an alignment operation) and FOO is already
6868 aligned to that boundary, mask C1 to that boundary as well.
6869 This may eliminate that PLUS and, later, the AND. */
6872 unsigned int width
= GET_MODE_BITSIZE (mode
);
6873 unsigned HOST_WIDE_INT smask
= mask
;
6875 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6876 number, sign extend it. */
6878 if (width
< HOST_BITS_PER_WIDE_INT
6879 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6880 smask
|= (HOST_WIDE_INT
) -1 << width
;
6882 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6883 && exact_log2 (- smask
) >= 0)
6887 && (XEXP (x
, 0) == stack_pointer_rtx
6888 || XEXP (x
, 0) == frame_pointer_rtx
))
6890 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6891 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6893 sp_mask
&= ~(sp_alignment
- 1);
6894 if ((sp_mask
& ~smask
) == 0
6895 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~smask
) != 0)
6896 return force_to_mode (plus_constant (XEXP (x
, 0),
6897 ((INTVAL (XEXP (x
, 1)) -
6898 STACK_BIAS
) & smask
)
6900 mode
, smask
, reg
, next_select
);
6903 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6904 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6905 return force_to_mode (plus_constant (XEXP (x
, 0),
6906 (INTVAL (XEXP (x
, 1))
6908 mode
, smask
, reg
, next_select
);
6912 /* ... fall through ... */
6915 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6916 most significant bit in MASK since carries from those bits will
6917 affect the bits we are interested in. */
6922 /* If X is (minus C Y) where C's least set bit is larger than any bit
6923 in the mask, then we may replace with (neg Y). */
6924 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6925 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6926 & -INTVAL (XEXP (x
, 0))))
6929 x
= gen_unary (NEG
, GET_MODE (x
), GET_MODE (x
), XEXP (x
, 1));
6930 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6933 /* Similarly, if C contains every bit in the mask, then we may
6934 replace with (not Y). */
6935 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6936 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6937 == INTVAL (XEXP (x
, 0))))
6939 x
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), XEXP (x
, 1));
6940 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6948 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6949 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6950 operation which may be a bitfield extraction. Ensure that the
6951 constant we form is not wider than the mode of X. */
6953 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6954 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6955 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6956 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6957 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6958 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6959 + floor_log2 (INTVAL (XEXP (x
, 1))))
6960 < GET_MODE_BITSIZE (GET_MODE (x
)))
6961 && (INTVAL (XEXP (x
, 1))
6962 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6964 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6965 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6966 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6967 XEXP (XEXP (x
, 0), 0), temp
);
6968 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6969 XEXP (XEXP (x
, 0), 1));
6970 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6974 /* For most binary operations, just propagate into the operation and
6975 change the mode if we have an operation of that mode. */
6977 op0
= gen_lowpart_for_combine (op_mode
,
6978 force_to_mode (XEXP (x
, 0), mode
, mask
,
6980 op1
= gen_lowpart_for_combine (op_mode
,
6981 force_to_mode (XEXP (x
, 1), mode
, mask
,
6984 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6985 MASK since OP1 might have been sign-extended but we never want
6986 to turn on extra bits, since combine might have previously relied
6987 on them being off. */
6988 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
6989 && (INTVAL (op1
) & mask
) != 0)
6990 op1
= GEN_INT (INTVAL (op1
) & mask
);
6992 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6993 x
= gen_binary (code
, op_mode
, op0
, op1
);
6997 /* For left shifts, do the same, but just for the first operand.
6998 However, we cannot do anything with shifts where we cannot
6999 guarantee that the counts are smaller than the size of the mode
7000 because such a count will have a different meaning in a
7003 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7004 && INTVAL (XEXP (x
, 1)) >= 0
7005 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7006 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7007 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7008 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7011 /* If the shift count is a constant and we can do arithmetic in
7012 the mode of the shift, refine which bits we need. Otherwise, use the
7013 conservative form of the mask. */
7014 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7015 && INTVAL (XEXP (x
, 1)) >= 0
7016 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7017 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7018 mask
>>= INTVAL (XEXP (x
, 1));
7022 op0
= gen_lowpart_for_combine (op_mode
,
7023 force_to_mode (XEXP (x
, 0), op_mode
,
7024 mask
, reg
, next_select
));
7026 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7027 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7031 /* Here we can only do something if the shift count is a constant,
7032 this shift constant is valid for the host, and we can do arithmetic
7035 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7036 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7037 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7039 rtx inner
= XEXP (x
, 0);
7040 unsigned HOST_WIDE_INT inner_mask
;
7042 /* Select the mask of the bits we need for the shift operand. */
7043 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7045 /* We can only change the mode of the shift if we can do arithmetic
7046 in the mode of the shift and INNER_MASK is no wider than the
7047 width of OP_MODE. */
7048 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7049 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7050 op_mode
= GET_MODE (x
);
7052 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7054 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7055 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7058 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7059 shift and AND produces only copies of the sign bit (C2 is one less
7060 than a power of two), we can do this with just a shift. */
7062 if (GET_CODE (x
) == LSHIFTRT
7063 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7064 /* The shift puts one of the sign bit copies in the least significant
7066 && ((INTVAL (XEXP (x
, 1))
7067 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7068 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7069 && exact_log2 (mask
+ 1) >= 0
7070 /* Number of bits left after the shift must be more than the mask
7072 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7073 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7074 /* Must be more sign bit copies than the mask needs. */
7075 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7076 >= exact_log2 (mask
+ 1)))
7077 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7078 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7079 - exact_log2 (mask
+ 1)));
7084 /* If we are just looking for the sign bit, we don't need this shift at
7085 all, even if it has a variable count. */
7086 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7087 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7088 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7089 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7091 /* If this is a shift by a constant, get a mask that contains those bits
7092 that are not copies of the sign bit. We then have two cases: If
7093 MASK only includes those bits, this can be a logical shift, which may
7094 allow simplifications. If MASK is a single-bit field not within
7095 those bits, we are requesting a copy of the sign bit and hence can
7096 shift the sign bit to the appropriate location. */
7098 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7099 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7103 /* If the considered data is wider then HOST_WIDE_INT, we can't
7104 represent a mask for all its bits in a single scalar.
7105 But we only care about the lower bits, so calculate these. */
7107 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7109 nonzero
= ~(HOST_WIDE_INT
) 0;
7111 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7112 is the number of bits a full-width mask would have set.
7113 We need only shift if these are fewer than nonzero can
7114 hold. If not, we must keep all bits set in nonzero. */
7116 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7117 < HOST_BITS_PER_WIDE_INT
)
7118 nonzero
>>= INTVAL (XEXP (x
, 1))
7119 + HOST_BITS_PER_WIDE_INT
7120 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7124 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7125 nonzero
>>= INTVAL (XEXP (x
, 1));
7128 if ((mask
& ~nonzero
) == 0
7129 || (i
= exact_log2 (mask
)) >= 0)
7131 x
= simplify_shift_const
7132 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7133 i
< 0 ? INTVAL (XEXP (x
, 1))
7134 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7136 if (GET_CODE (x
) != ASHIFTRT
)
7137 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7141 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7142 even if the shift count isn't a constant. */
7144 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7148 /* If this is a zero- or sign-extension operation that just affects bits
7149 we don't care about, remove it. Be sure the call above returned
7150 something that is still a shift. */
7152 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7153 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7154 && INTVAL (XEXP (x
, 1)) >= 0
7155 && (INTVAL (XEXP (x
, 1))
7156 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7157 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7158 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7159 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7160 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7167 /* If the shift count is constant and we can do computations
7168 in the mode of X, compute where the bits we care about are.
7169 Otherwise, we can't do anything. Don't change the mode of
7170 the shift or propagate MODE into the shift, though. */
7171 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7172 && INTVAL (XEXP (x
, 1)) >= 0)
7174 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7175 GET_MODE (x
), GEN_INT (mask
),
7177 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7179 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7180 INTVAL (temp
), reg
, next_select
));
7185 /* If we just want the low-order bit, the NEG isn't needed since it
7186 won't change the low-order bit. */
7188 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7190 /* We need any bits less significant than the most significant bit in
7191 MASK since carries from those bits will affect the bits we are
7197 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7198 same as the XOR case above. Ensure that the constant we form is not
7199 wider than the mode of X. */
7201 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7202 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7203 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7204 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7205 < GET_MODE_BITSIZE (GET_MODE (x
)))
7206 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7208 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7209 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7210 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7212 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7215 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7216 use the full mask inside the NOT. */
7220 op0
= gen_lowpart_for_combine (op_mode
,
7221 force_to_mode (XEXP (x
, 0), mode
, mask
,
7223 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7224 x
= gen_unary (code
, op_mode
, op_mode
, op0
);
7228 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7229 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7230 which is equal to STORE_FLAG_VALUE. */
7231 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7232 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7233 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7234 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7239 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7240 written in a narrower mode. We play it safe and do not do so. */
7243 gen_lowpart_for_combine (GET_MODE (x
),
7244 force_to_mode (XEXP (x
, 1), mode
,
7245 mask
, reg
, next_select
)));
7247 gen_lowpart_for_combine (GET_MODE (x
),
7248 force_to_mode (XEXP (x
, 2), mode
,
7249 mask
, reg
,next_select
)));
7256 /* Ensure we return a value of the proper mode. */
7257 return gen_lowpart_for_combine (mode
, x
);
7260 /* Return nonzero if X is an expression that has one of two values depending on
7261 whether some other value is zero or nonzero. In that case, we return the
7262 value that is being tested, *PTRUE is set to the value if the rtx being
7263 returned has a nonzero value, and *PFALSE is set to the other alternative.
7265 If we return zero, we set *PTRUE and *PFALSE to X. */
7268 if_then_else_cond (x
, ptrue
, pfalse
)
7270 rtx
*ptrue
, *pfalse
;
7272 enum machine_mode mode
= GET_MODE (x
);
7273 enum rtx_code code
= GET_CODE (x
);
7274 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7275 unsigned HOST_WIDE_INT nz
;
7277 /* If we are comparing a value against zero, we are done. */
7278 if ((code
== NE
|| code
== EQ
)
7279 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7281 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7282 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7286 /* If this is a unary operation whose operand has one of two values, apply
7287 our opcode to compute those values. */
7288 else if (GET_RTX_CLASS (code
) == '1'
7289 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7291 *ptrue
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), true0
);
7292 *pfalse
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), false0
);
7296 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7297 make can't possibly match and would suppress other optimizations. */
7298 else if (code
== COMPARE
)
7301 /* If this is a binary operation, see if either side has only one of two
7302 values. If either one does or if both do and they are conditional on
7303 the same value, compute the new true and false values. */
7304 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7305 || GET_RTX_CLASS (code
) == '<')
7307 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7308 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7310 if ((cond0
!= 0 || cond1
!= 0)
7311 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7313 /* If if_then_else_cond returned zero, then true/false are the
7314 same rtl. We must copy one of them to prevent invalid rtl
7317 true0
= copy_rtx (true0
);
7318 else if (cond1
== 0)
7319 true1
= copy_rtx (true1
);
7321 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7322 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7323 return cond0
? cond0
: cond1
;
7326 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7327 operands is zero when the other is non-zero, and vice-versa,
7328 and STORE_FLAG_VALUE is 1 or -1. */
7330 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7331 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7333 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7335 rtx op0
= XEXP (XEXP (x
, 0), 1);
7336 rtx op1
= XEXP (XEXP (x
, 1), 1);
7338 cond0
= XEXP (XEXP (x
, 0), 0);
7339 cond1
= XEXP (XEXP (x
, 1), 0);
7341 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7342 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7343 && reversible_comparison_p (cond1
)
7344 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
7345 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7346 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7347 || ((swap_condition (GET_CODE (cond0
))
7348 == reverse_condition (GET_CODE (cond1
)))
7349 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7350 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7351 && ! side_effects_p (x
))
7353 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7354 *pfalse
= gen_binary (MULT
, mode
,
7356 ? gen_unary (NEG
, mode
, mode
, op1
) : op1
),
7362 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7364 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7365 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7366 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7368 cond0
= XEXP (XEXP (x
, 0), 0);
7369 cond1
= XEXP (XEXP (x
, 1), 0);
7371 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7372 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7373 && reversible_comparison_p (cond1
)
7374 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
7375 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7376 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7377 || ((swap_condition (GET_CODE (cond0
))
7378 == reverse_condition (GET_CODE (cond1
)))
7379 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7380 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7381 && ! side_effects_p (x
))
7383 *ptrue
= *pfalse
= const0_rtx
;
7389 else if (code
== IF_THEN_ELSE
)
7391 /* If we have IF_THEN_ELSE already, extract the condition and
7392 canonicalize it if it is NE or EQ. */
7393 cond0
= XEXP (x
, 0);
7394 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7395 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7396 return XEXP (cond0
, 0);
7397 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7399 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7400 return XEXP (cond0
, 0);
7406 /* If X is a normal SUBREG with both inner and outer modes integral,
7407 we can narrow both the true and false values of the inner expression,
7408 if there is a condition. */
7409 else if (code
== SUBREG
&& GET_MODE_CLASS (mode
) == MODE_INT
7410 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_INT
7411 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
7412 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7415 if ((GET_CODE (SUBREG_REG (x
)) == REG
7416 || GET_CODE (SUBREG_REG (x
)) == MEM
7417 || CONSTANT_P (SUBREG_REG (x
)))
7418 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
7419 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
7421 true0
= operand_subword (true0
, SUBREG_WORD (x
), 0, mode
);
7422 false0
= operand_subword (false0
, SUBREG_WORD (x
), 0, mode
);
7424 *ptrue
= force_to_mode (true0
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
7426 = force_to_mode (false0
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
7431 /* If X is a constant, this isn't special and will cause confusions
7432 if we treat it as such. Likewise if it is equivalent to a constant. */
7433 else if (CONSTANT_P (x
)
7434 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7437 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7438 will be least confusing to the rest of the compiler. */
7439 else if (mode
== BImode
)
7441 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7445 /* If X is known to be either 0 or -1, those are the true and
7446 false values when testing X. */
7447 else if (x
== constm1_rtx
|| x
== const0_rtx
7448 || (mode
!= VOIDmode
7449 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7451 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7455 /* Likewise for 0 or a single bit. */
7456 else if (mode
!= VOIDmode
7457 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7458 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7460 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7464 /* Otherwise fail; show no condition with true and false values the same. */
7465 *ptrue
= *pfalse
= x
;
7469 /* Return the value of expression X given the fact that condition COND
7470 is known to be true when applied to REG as its first operand and VAL
7471 as its second. X is known to not be shared and so can be modified in
7474 We only handle the simplest cases, and specifically those cases that
7475 arise with IF_THEN_ELSE expressions. */
7478 known_cond (x
, cond
, reg
, val
)
7483 enum rtx_code code
= GET_CODE (x
);
7488 if (side_effects_p (x
))
7491 if (cond
== EQ
&& rtx_equal_p (x
, reg
))
7494 /* If X is (abs REG) and we know something about REG's relationship
7495 with zero, we may be able to simplify this. */
7497 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7500 case GE
: case GT
: case EQ
:
7503 return gen_unary (NEG
, GET_MODE (XEXP (x
, 0)), GET_MODE (XEXP (x
, 0)),
7509 /* The only other cases we handle are MIN, MAX, and comparisons if the
7510 operands are the same as REG and VAL. */
7512 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7514 if (rtx_equal_p (XEXP (x
, 0), val
))
7515 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7517 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7519 if (GET_RTX_CLASS (code
) == '<')
7521 if (comparison_dominates_p (cond
, code
))
7522 return const_true_rtx
;
7524 code
= reverse_condition (code
);
7526 && comparison_dominates_p (cond
, code
))
7531 else if (code
== SMAX
|| code
== SMIN
7532 || code
== UMIN
|| code
== UMAX
)
7534 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7536 if (code
== SMAX
|| code
== UMAX
)
7537 cond
= reverse_condition (cond
);
7542 return unsignedp
? x
: XEXP (x
, 1);
7544 return unsignedp
? x
: XEXP (x
, 0);
7546 return unsignedp
? XEXP (x
, 1) : x
;
7548 return unsignedp
? XEXP (x
, 0) : x
;
7556 fmt
= GET_RTX_FORMAT (code
);
7557 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7560 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7561 else if (fmt
[i
] == 'E')
7562 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7563 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7570 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7571 assignment as a field assignment. */
7574 rtx_equal_for_field_assignment_p (x
, y
)
7578 if (x
== y
|| rtx_equal_p (x
, y
))
7581 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7584 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7585 Note that all SUBREGs of MEM are paradoxical; otherwise they
7586 would have been rewritten. */
7587 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7588 && GET_CODE (SUBREG_REG (y
)) == MEM
7589 && rtx_equal_p (SUBREG_REG (y
),
7590 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7593 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7594 && GET_CODE (SUBREG_REG (x
)) == MEM
7595 && rtx_equal_p (SUBREG_REG (x
),
7596 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7599 /* We used to see if get_last_value of X and Y were the same but that's
7600 not correct. In one direction, we'll cause the assignment to have
7601 the wrong destination and in the case, we'll import a register into this
7602 insn that might have already have been dead. So fail if none of the
7603 above cases are true. */
7607 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7608 Return that assignment if so.
7610 We only handle the most common cases. */
7613 make_field_assignment (x
)
7616 rtx dest
= SET_DEST (x
);
7617 rtx src
= SET_SRC (x
);
7622 unsigned HOST_WIDE_INT len
;
7624 enum machine_mode mode
;
7626 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7627 a clear of a one-bit field. We will have changed it to
7628 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7631 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7632 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7633 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7634 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7636 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7639 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7643 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7644 && subreg_lowpart_p (XEXP (src
, 0))
7645 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7646 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7647 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7648 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7649 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7651 assign
= make_extraction (VOIDmode
, dest
, 0,
7652 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7655 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7659 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7661 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7662 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7663 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7665 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7668 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7672 /* The other case we handle is assignments into a constant-position
7673 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7674 a mask that has all one bits except for a group of zero bits and
7675 OTHER is known to have zeros where C1 has ones, this is such an
7676 assignment. Compute the position and length from C1. Shift OTHER
7677 to the appropriate position, force it to the required mode, and
7678 make the extraction. Check for the AND in both operands. */
7680 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7683 rhs
= expand_compound_operation (XEXP (src
, 0));
7684 lhs
= expand_compound_operation (XEXP (src
, 1));
7686 if (GET_CODE (rhs
) == AND
7687 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7688 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7689 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7690 else if (GET_CODE (lhs
) == AND
7691 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7692 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7693 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7697 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7698 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7699 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7700 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7703 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7707 /* The mode to use for the source is the mode of the assignment, or of
7708 what is inside a possible STRICT_LOW_PART. */
7709 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7710 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7712 /* Shift OTHER right POS places and make it the source, restricting it
7713 to the proper length and mode. */
7715 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7716 GET_MODE (src
), other
, pos
),
7718 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7719 ? ~(unsigned HOST_WIDE_INT
) 0
7720 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7723 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
7726 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7730 apply_distributive_law (x
)
7733 enum rtx_code code
= GET_CODE (x
);
7734 rtx lhs
, rhs
, other
;
7736 enum rtx_code inner_code
;
7738 /* Distributivity is not true for floating point.
7739 It can change the value. So don't do it.
7740 -- rms and moshier@world.std.com. */
7741 if (FLOAT_MODE_P (GET_MODE (x
)))
7744 /* The outer operation can only be one of the following: */
7745 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7746 && code
!= PLUS
&& code
!= MINUS
)
7749 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7751 /* If either operand is a primitive we can't do anything, so get out
7753 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7754 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7757 lhs
= expand_compound_operation (lhs
);
7758 rhs
= expand_compound_operation (rhs
);
7759 inner_code
= GET_CODE (lhs
);
7760 if (inner_code
!= GET_CODE (rhs
))
7763 /* See if the inner and outer operations distribute. */
7770 /* These all distribute except over PLUS. */
7771 if (code
== PLUS
|| code
== MINUS
)
7776 if (code
!= PLUS
&& code
!= MINUS
)
7781 /* This is also a multiply, so it distributes over everything. */
7785 /* Non-paradoxical SUBREGs distributes over all operations, provided
7786 the inner modes and word numbers are the same, this is an extraction
7787 of a low-order part, we don't convert an fp operation to int or
7788 vice versa, and we would not be converting a single-word
7789 operation into a multi-word operation. The latter test is not
7790 required, but it prevents generating unneeded multi-word operations.
7791 Some of the previous tests are redundant given the latter test, but
7792 are retained because they are required for correctness.
7794 We produce the result slightly differently in this case. */
7796 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7797 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
7798 || ! subreg_lowpart_p (lhs
)
7799 || (GET_MODE_CLASS (GET_MODE (lhs
))
7800 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7801 || (GET_MODE_SIZE (GET_MODE (lhs
))
7802 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7803 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7806 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7807 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7808 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7814 /* Set LHS and RHS to the inner operands (A and B in the example
7815 above) and set OTHER to the common operand (C in the example).
7816 These is only one way to do this unless the inner operation is
7818 if (GET_RTX_CLASS (inner_code
) == 'c'
7819 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7820 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7821 else if (GET_RTX_CLASS (inner_code
) == 'c'
7822 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7823 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7824 else if (GET_RTX_CLASS (inner_code
) == 'c'
7825 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7826 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7827 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7828 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7832 /* Form the new inner operation, seeing if it simplifies first. */
7833 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7835 /* There is one exception to the general way of distributing:
7836 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7837 if (code
== XOR
&& inner_code
== IOR
)
7840 other
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), other
);
7843 /* We may be able to continuing distributing the result, so call
7844 ourselves recursively on the inner operation before forming the
7845 outer operation, which we return. */
7846 return gen_binary (inner_code
, GET_MODE (x
),
7847 apply_distributive_law (tem
), other
);
7850 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7853 Return an equivalent form, if different from X. Otherwise, return X. If
7854 X is zero, we are to always construct the equivalent form. */
7857 simplify_and_const_int (x
, mode
, varop
, constop
)
7859 enum machine_mode mode
;
7861 unsigned HOST_WIDE_INT constop
;
7863 unsigned HOST_WIDE_INT nonzero
;
7866 /* Simplify VAROP knowing that we will be only looking at some of the
7868 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7870 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7871 CONST_INT, we are done. */
7872 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7875 /* See what bits may be nonzero in VAROP. Unlike the general case of
7876 a call to nonzero_bits, here we don't care about bits outside
7879 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7880 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7882 /* Turn off all bits in the constant that are known to already be zero.
7883 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7884 which is tested below. */
7888 /* If we don't have any bits left, return zero. */
7892 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7893 a power of two, we can replace this with a ASHIFT. */
7894 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7895 && (i
= exact_log2 (constop
)) >= 0)
7896 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7898 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7899 or XOR, then try to apply the distributive law. This may eliminate
7900 operations if either branch can be simplified because of the AND.
7901 It may also make some cases more complex, but those cases probably
7902 won't match a pattern either with or without this. */
7904 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7906 gen_lowpart_for_combine
7908 apply_distributive_law
7909 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7910 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7911 XEXP (varop
, 0), constop
),
7912 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7913 XEXP (varop
, 1), constop
))));
7915 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7916 if we already had one (just check for the simplest cases). */
7917 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7918 && GET_MODE (XEXP (x
, 0)) == mode
7919 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7920 varop
= XEXP (x
, 0);
7922 varop
= gen_lowpart_for_combine (mode
, varop
);
7924 /* If we can't make the SUBREG, try to return what we were given. */
7925 if (GET_CODE (varop
) == CLOBBER
)
7926 return x
? x
: varop
;
7928 /* If we are only masking insignificant bits, return VAROP. */
7929 if (constop
== nonzero
)
7932 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7933 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7934 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7938 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7939 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7940 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7942 SUBST (XEXP (x
, 0), varop
);
7948 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7949 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7950 is less useful. We can't allow both, because that results in exponential
7951 run time recursion. There is a nullstone testcase that triggered
7952 this. This macro avoids accidental uses of num_sign_bit_copies. */
7953 #define num_sign_bit_copies()
7955 /* Given an expression, X, compute which bits in X can be non-zero.
7956 We don't care about bits outside of those defined in MODE.
7958 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7959 a shift, AND, or zero_extract, we can do better. */
7961 static unsigned HOST_WIDE_INT
7962 nonzero_bits (x
, mode
)
7964 enum machine_mode mode
;
7966 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
7967 unsigned HOST_WIDE_INT inner_nz
;
7969 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
7972 /* For floating-point values, assume all bits are needed. */
7973 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
7976 /* If X is wider than MODE, use its mode instead. */
7977 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
7979 mode
= GET_MODE (x
);
7980 nonzero
= GET_MODE_MASK (mode
);
7981 mode_width
= GET_MODE_BITSIZE (mode
);
7984 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
7985 /* Our only callers in this case look for single bit values. So
7986 just return the mode mask. Those tests will then be false. */
7989 #ifndef WORD_REGISTER_OPERATIONS
7990 /* If MODE is wider than X, but both are a single word for both the host
7991 and target machines, we can compute this from which bits of the
7992 object might be nonzero in its own mode, taking into account the fact
7993 that on many CISC machines, accessing an object in a wider mode
7994 causes the high-order bits to become undefined. So they are
7995 not known to be zero. */
7997 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
7998 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
7999 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8000 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8002 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
8003 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8008 code
= GET_CODE (x
);
8012 #ifdef POINTERS_EXTEND_UNSIGNED
8013 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8014 all the bits above ptr_mode are known to be zero. */
8015 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8017 nonzero
&= GET_MODE_MASK (ptr_mode
);
8020 #ifdef STACK_BOUNDARY
8021 /* If this is the stack pointer, we may know something about its
8022 alignment. If PUSH_ROUNDING is defined, it is possible for the
8023 stack to be momentarily aligned only to that amount, so we pick
8024 the least alignment. */
8026 /* We can't check for arg_pointer_rtx here, because it is not
8027 guaranteed to have as much alignment as the stack pointer.
8028 In particular, in the Irix6 n64 ABI, the stack has 128 bit
8029 alignment but the argument pointer has only 64 bit alignment. */
8031 if ((x
== frame_pointer_rtx
8032 || x
== stack_pointer_rtx
8033 || x
== hard_frame_pointer_rtx
8034 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
8035 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
8041 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8043 #ifdef PUSH_ROUNDING
8044 if (REGNO (x
) == STACK_POINTER_REGNUM
&& PUSH_ARGS
)
8045 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
8048 /* We must return here, otherwise we may get a worse result from
8049 one of the choices below. There is nothing useful below as
8050 far as the stack pointer is concerned. */
8051 return nonzero
&= ~(sp_alignment
- 1);
8055 /* If X is a register whose nonzero bits value is current, use it.
8056 Otherwise, if X is a register whose value we can find, use that
8057 value. Otherwise, use the previously-computed global nonzero bits
8058 for this register. */
8060 if (reg_last_set_value
[REGNO (x
)] != 0
8061 && reg_last_set_mode
[REGNO (x
)] == mode
8062 && (reg_last_set_label
[REGNO (x
)] == label_tick
8063 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8064 && REG_N_SETS (REGNO (x
)) == 1
8065 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8067 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8068 return reg_last_set_nonzero_bits
[REGNO (x
)];
8070 tem
= get_last_value (x
);
8074 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8075 /* If X is narrower than MODE and TEM is a non-negative
8076 constant that would appear negative in the mode of X,
8077 sign-extend it for use in reg_nonzero_bits because some
8078 machines (maybe most) will actually do the sign-extension
8079 and this is the conservative approach.
8081 ??? For 2.5, try to tighten up the MD files in this regard
8082 instead of this kludge. */
8084 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8085 && GET_CODE (tem
) == CONST_INT
8087 && 0 != (INTVAL (tem
)
8088 & ((HOST_WIDE_INT
) 1
8089 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8090 tem
= GEN_INT (INTVAL (tem
)
8091 | ((HOST_WIDE_INT
) (-1)
8092 << GET_MODE_BITSIZE (GET_MODE (x
))));
8094 return nonzero_bits (tem
, mode
);
8096 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8097 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
8102 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8103 /* If X is negative in MODE, sign-extend the value. */
8104 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8105 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8106 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8112 #ifdef LOAD_EXTEND_OP
8113 /* In many, if not most, RISC machines, reading a byte from memory
8114 zeros the rest of the register. Noticing that fact saves a lot
8115 of extra zero-extends. */
8116 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8117 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8127 /* If this produces an integer result, we know which bits are set.
8128 Code here used to clear bits outside the mode of X, but that is
8131 if (GET_MODE_CLASS (mode
) == MODE_INT
8132 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8133 nonzero
= STORE_FLAG_VALUE
;
8138 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8139 and num_sign_bit_copies. */
8140 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8141 == GET_MODE_BITSIZE (GET_MODE (x
)))
8145 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8146 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8151 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8152 and num_sign_bit_copies. */
8153 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8154 == GET_MODE_BITSIZE (GET_MODE (x
)))
8160 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8164 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8165 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8166 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8170 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8171 Otherwise, show all the bits in the outer mode but not the inner
8173 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8174 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8176 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8178 & (((HOST_WIDE_INT
) 1
8179 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8180 inner_nz
|= (GET_MODE_MASK (mode
)
8181 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8184 nonzero
&= inner_nz
;
8188 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8189 & nonzero_bits (XEXP (x
, 1), mode
));
8193 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8194 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8195 | nonzero_bits (XEXP (x
, 1), mode
));
8198 case PLUS
: case MINUS
:
8200 case DIV
: case UDIV
:
8201 case MOD
: case UMOD
:
8202 /* We can apply the rules of arithmetic to compute the number of
8203 high- and low-order zero bits of these operations. We start by
8204 computing the width (position of the highest-order non-zero bit)
8205 and the number of low-order zero bits for each value. */
8207 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8208 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8209 int width0
= floor_log2 (nz0
) + 1;
8210 int width1
= floor_log2 (nz1
) + 1;
8211 int low0
= floor_log2 (nz0
& -nz0
);
8212 int low1
= floor_log2 (nz1
& -nz1
);
8213 HOST_WIDE_INT op0_maybe_minusp
8214 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8215 HOST_WIDE_INT op1_maybe_minusp
8216 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8217 unsigned int result_width
= mode_width
;
8225 && (XEXP (x
, 0) == stack_pointer_rtx
8226 || XEXP (x
, 0) == frame_pointer_rtx
)
8227 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8229 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8231 nz0
= (GET_MODE_MASK (mode
) & ~(sp_alignment
- 1));
8232 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
8233 width0
= floor_log2 (nz0
) + 1;
8234 width1
= floor_log2 (nz1
) + 1;
8235 low0
= floor_log2 (nz0
& -nz0
);
8236 low1
= floor_log2 (nz1
& -nz1
);
8239 result_width
= MAX (width0
, width1
) + 1;
8240 result_low
= MIN (low0
, low1
);
8243 result_low
= MIN (low0
, low1
);
8246 result_width
= width0
+ width1
;
8247 result_low
= low0
+ low1
;
8250 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8251 result_width
= width0
;
8254 result_width
= width0
;
8257 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8258 result_width
= MIN (width0
, width1
);
8259 result_low
= MIN (low0
, low1
);
8262 result_width
= MIN (width0
, width1
);
8263 result_low
= MIN (low0
, low1
);
8269 if (result_width
< mode_width
)
8270 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8273 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8278 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8279 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8280 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8284 /* If this is a SUBREG formed for a promoted variable that has
8285 been zero-extended, we know that at least the high-order bits
8286 are zero, though others might be too. */
8288 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
8289 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8290 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8292 /* If the inner mode is a single word for both the host and target
8293 machines, we can compute this from which bits of the inner
8294 object might be nonzero. */
8295 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8296 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8297 <= HOST_BITS_PER_WIDE_INT
))
8299 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8301 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8302 /* If this is a typical RISC machine, we only have to worry
8303 about the way loads are extended. */
8304 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8306 & (((unsigned HOST_WIDE_INT
) 1
8307 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8309 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8312 /* On many CISC machines, accessing an object in a wider mode
8313 causes the high-order bits to become undefined. So they are
8314 not known to be zero. */
8315 if (GET_MODE_SIZE (GET_MODE (x
))
8316 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8317 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8318 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8327 /* The nonzero bits are in two classes: any bits within MODE
8328 that aren't in GET_MODE (x) are always significant. The rest of the
8329 nonzero bits are those that are significant in the operand of
8330 the shift when shifted the appropriate number of bits. This
8331 shows that high-order bits are cleared by the right shift and
8332 low-order bits by left shifts. */
8333 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8334 && INTVAL (XEXP (x
, 1)) >= 0
8335 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8337 enum machine_mode inner_mode
= GET_MODE (x
);
8338 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8339 int count
= INTVAL (XEXP (x
, 1));
8340 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8341 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8342 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8343 unsigned HOST_WIDE_INT outer
= 0;
8345 if (mode_width
> width
)
8346 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8348 if (code
== LSHIFTRT
)
8350 else if (code
== ASHIFTRT
)
8354 /* If the sign bit may have been nonzero before the shift, we
8355 need to mark all the places it could have been copied to
8356 by the shift as possibly nonzero. */
8357 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8358 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8360 else if (code
== ASHIFT
)
8363 inner
= ((inner
<< (count
% width
)
8364 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8366 nonzero
&= (outer
| inner
);
8371 /* This is at most the number of bits in the mode. */
8372 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8376 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8377 | nonzero_bits (XEXP (x
, 2), mode
));
8387 /* See the macro definition above. */
8388 #undef num_sign_bit_copies
8390 /* Return the number of bits at the high-order end of X that are known to
8391 be equal to the sign bit. X will be used in mode MODE; if MODE is
8392 VOIDmode, X will be used in its own mode. The returned value will always
8393 be between 1 and the number of bits in MODE. */
8396 num_sign_bit_copies (x
, mode
)
8398 enum machine_mode mode
;
8400 enum rtx_code code
= GET_CODE (x
);
8401 unsigned int bitwidth
;
8402 int num0
, num1
, result
;
8403 unsigned HOST_WIDE_INT nonzero
;
8406 /* If we weren't given a mode, use the mode of X. If the mode is still
8407 VOIDmode, we don't know anything. Likewise if one of the modes is
8410 if (mode
== VOIDmode
)
8411 mode
= GET_MODE (x
);
8413 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8416 bitwidth
= GET_MODE_BITSIZE (mode
);
8418 /* For a smaller object, just ignore the high bits. */
8419 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8421 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8423 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8426 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8428 #ifndef WORD_REGISTER_OPERATIONS
8429 /* If this machine does not do all register operations on the entire
8430 register and MODE is wider than the mode of X, we can say nothing
8431 at all about the high-order bits. */
8434 /* Likewise on machines that do, if the mode of the object is smaller
8435 than a word and loads of that size don't sign extend, we can say
8436 nothing about the high order bits. */
8437 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8438 #ifdef LOAD_EXTEND_OP
8439 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8450 #ifdef POINTERS_EXTEND_UNSIGNED
8451 /* If pointers extend signed and this is a pointer in Pmode, say that
8452 all the bits above ptr_mode are known to be sign bit copies. */
8453 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8455 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8458 if (reg_last_set_value
[REGNO (x
)] != 0
8459 && reg_last_set_mode
[REGNO (x
)] == mode
8460 && (reg_last_set_label
[REGNO (x
)] == label_tick
8461 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8462 && REG_N_SETS (REGNO (x
)) == 1
8463 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8465 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8466 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8468 tem
= get_last_value (x
);
8470 return num_sign_bit_copies (tem
, mode
);
8472 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8473 return reg_sign_bit_copies
[REGNO (x
)];
8477 #ifdef LOAD_EXTEND_OP
8478 /* Some RISC machines sign-extend all loads of smaller than a word. */
8479 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8480 return MAX (1, ((int) bitwidth
8481 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8486 /* If the constant is negative, take its 1's complement and remask.
8487 Then see how many zero bits we have. */
8488 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8489 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8490 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8491 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8493 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8496 /* If this is a SUBREG for a promoted object that is sign-extended
8497 and we are looking at it in a wider mode, we know that at least the
8498 high-order bits are known to be sign bit copies. */
8500 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8502 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8503 return MAX ((int) bitwidth
8504 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8508 /* For a smaller object, just ignore the high bits. */
8509 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8511 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8512 return MAX (1, (num0
8513 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8517 #ifdef WORD_REGISTER_OPERATIONS
8518 #ifdef LOAD_EXTEND_OP
8519 /* For paradoxical SUBREGs on machines where all register operations
8520 affect the entire register, just look inside. Note that we are
8521 passing MODE to the recursive call, so the number of sign bit copies
8522 will remain relative to that mode, not the inner mode. */
8524 /* This works only if loads sign extend. Otherwise, if we get a
8525 reload for the inner part, it may be loaded from the stack, and
8526 then we lose all sign bit copies that existed before the store
8529 if ((GET_MODE_SIZE (GET_MODE (x
))
8530 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8531 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8532 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8538 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8539 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8543 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8544 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8547 /* For a smaller object, just ignore the high bits. */
8548 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8549 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8553 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8555 case ROTATE
: case ROTATERT
:
8556 /* If we are rotating left by a number of bits less than the number
8557 of sign bit copies, we can just subtract that amount from the
8559 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8560 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
8562 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8563 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8564 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8569 /* In general, this subtracts one sign bit copy. But if the value
8570 is known to be positive, the number of sign bit copies is the
8571 same as that of the input. Finally, if the input has just one bit
8572 that might be nonzero, all the bits are copies of the sign bit. */
8573 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8574 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8575 return num0
> 1 ? num0
- 1 : 1;
8577 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8582 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8587 case IOR
: case AND
: case XOR
:
8588 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8589 /* Logical operations will preserve the number of sign-bit copies.
8590 MIN and MAX operations always return one of the operands. */
8591 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8592 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8593 return MIN (num0
, num1
);
8595 case PLUS
: case MINUS
:
8596 /* For addition and subtraction, we can have a 1-bit carry. However,
8597 if we are subtracting 1 from a positive number, there will not
8598 be such a carry. Furthermore, if the positive number is known to
8599 be 0 or 1, we know the result is either -1 or 0. */
8601 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8602 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8604 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8605 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8606 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8607 : bitwidth
- floor_log2 (nonzero
) - 1);
8610 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8611 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8612 return MAX (1, MIN (num0
, num1
) - 1);
8615 /* The number of bits of the product is the sum of the number of
8616 bits of both terms. However, unless one of the terms if known
8617 to be positive, we must allow for an additional bit since negating
8618 a negative number can remove one sign bit copy. */
8620 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8621 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8623 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8625 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8626 || (((nonzero_bits (XEXP (x
, 0), mode
)
8627 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8628 && ((nonzero_bits (XEXP (x
, 1), mode
)
8629 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8632 return MAX (1, result
);
8635 /* The result must be <= the first operand. If the first operand
8636 has the high bit set, we know nothing about the number of sign
8638 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8640 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8641 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8644 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8647 /* The result must be <= the scond operand. */
8648 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8651 /* Similar to unsigned division, except that we have to worry about
8652 the case where the divisor is negative, in which case we have
8654 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8656 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8657 || (nonzero_bits (XEXP (x
, 1), mode
)
8658 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8664 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8666 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8667 || (nonzero_bits (XEXP (x
, 1), mode
)
8668 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8674 /* Shifts by a constant add to the number of bits equal to the
8676 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8677 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8678 && INTVAL (XEXP (x
, 1)) > 0)
8679 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8684 /* Left shifts destroy copies. */
8685 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8686 || INTVAL (XEXP (x
, 1)) < 0
8687 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
8690 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8691 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8694 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8695 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8696 return MIN (num0
, num1
);
8698 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8699 case GEU
: case GTU
: case LEU
: case LTU
:
8700 if (STORE_FLAG_VALUE
== -1)
8708 /* If we haven't been able to figure it out by one of the above rules,
8709 see if some of the high-order bits are known to be zero. If so,
8710 count those bits and return one less than that amount. If we can't
8711 safely compute the mask for this mode, always return BITWIDTH. */
8713 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8716 nonzero
= nonzero_bits (x
, mode
);
8717 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8718 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8721 /* Return the number of "extended" bits there are in X, when interpreted
8722 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8723 unsigned quantities, this is the number of high-order zero bits.
8724 For signed quantities, this is the number of copies of the sign bit
8725 minus 1. In both case, this function returns the number of "spare"
8726 bits. For example, if two quantities for which this function returns
8727 at least 1 are added, the addition is known not to overflow.
8729 This function will always return 0 unless called during combine, which
8730 implies that it must be called from a define_split. */
8733 extended_count (x
, mode
, unsignedp
)
8735 enum machine_mode mode
;
8738 if (nonzero_sign_valid
== 0)
8742 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8743 ? (GET_MODE_BITSIZE (mode
) - 1
8744 - floor_log2 (nonzero_bits (x
, mode
)))
8746 : num_sign_bit_copies (x
, mode
) - 1);
8749 /* This function is called from `simplify_shift_const' to merge two
8750 outer operations. Specifically, we have already found that we need
8751 to perform operation *POP0 with constant *PCONST0 at the outermost
8752 position. We would now like to also perform OP1 with constant CONST1
8753 (with *POP0 being done last).
8755 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8756 the resulting operation. *PCOMP_P is set to 1 if we would need to
8757 complement the innermost operand, otherwise it is unchanged.
8759 MODE is the mode in which the operation will be done. No bits outside
8760 the width of this mode matter. It is assumed that the width of this mode
8761 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8763 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8764 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8765 result is simply *PCONST0.
8767 If the resulting operation cannot be expressed as one operation, we
8768 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8771 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8772 enum rtx_code
*pop0
;
8773 HOST_WIDE_INT
*pconst0
;
8775 HOST_WIDE_INT const1
;
8776 enum machine_mode mode
;
8779 enum rtx_code op0
= *pop0
;
8780 HOST_WIDE_INT const0
= *pconst0
;
8782 const0
&= GET_MODE_MASK (mode
);
8783 const1
&= GET_MODE_MASK (mode
);
8785 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8789 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8792 if (op1
== NIL
|| op0
== SET
)
8795 else if (op0
== NIL
)
8796 op0
= op1
, const0
= const1
;
8798 else if (op0
== op1
)
8822 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8823 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8826 /* If the two constants aren't the same, we can't do anything. The
8827 remaining six cases can all be done. */
8828 else if (const0
!= const1
)
8836 /* (a & b) | b == b */
8838 else /* op1 == XOR */
8839 /* (a ^ b) | b == a | b */
8845 /* (a & b) ^ b == (~a) & b */
8846 op0
= AND
, *pcomp_p
= 1;
8847 else /* op1 == IOR */
8848 /* (a | b) ^ b == a & ~b */
8849 op0
= AND
, *pconst0
= ~const0
;
8854 /* (a | b) & b == b */
8856 else /* op1 == XOR */
8857 /* (a ^ b) & b) == (~a) & b */
8864 /* Check for NO-OP cases. */
8865 const0
&= GET_MODE_MASK (mode
);
8867 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8869 else if (const0
== 0 && op0
== AND
)
8871 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8875 /* ??? Slightly redundant with the above mask, but not entirely.
8876 Moving this above means we'd have to sign-extend the mode mask
8877 for the final test. */
8878 const0
= trunc_int_for_mode (const0
, mode
);
8886 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8887 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8888 that we started with.
8890 The shift is normally computed in the widest mode we find in VAROP, as
8891 long as it isn't a different number of words than RESULT_MODE. Exceptions
8892 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8895 simplify_shift_const (x
, code
, result_mode
, varop
, input_count
)
8898 enum machine_mode result_mode
;
8902 enum rtx_code orig_code
= code
;
8903 int orig_count
= input_count
;
8906 enum machine_mode mode
= result_mode
;
8907 enum machine_mode shift_mode
, tmode
;
8908 unsigned int mode_words
8909 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8910 /* We form (outer_op (code varop count) (outer_const)). */
8911 enum rtx_code outer_op
= NIL
;
8912 HOST_WIDE_INT outer_const
= 0;
8914 int complement_p
= 0;
8917 /* If we were given an invalid count, don't do anything except exactly
8918 what was requested. */
8920 if (input_count
< 0 || input_count
> (int) GET_MODE_BITSIZE (mode
))
8925 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (input_count
));
8928 count
= input_count
;
8930 /* Make sure and truncate the "natural" shift on the way in. We don't
8931 want to do this inside the loop as it makes it more difficult to
8933 #ifdef SHIFT_COUNT_TRUNCATED
8934 if (SHIFT_COUNT_TRUNCATED
)
8935 count
%= GET_MODE_BITSIZE (mode
);
8938 /* Unless one of the branches of the `if' in this loop does a `continue',
8939 we will `break' the loop after the `if'. */
8943 /* If we have an operand of (clobber (const_int 0)), just return that
8945 if (GET_CODE (varop
) == CLOBBER
)
8948 /* If we discovered we had to complement VAROP, leave. Making a NOT
8949 here would cause an infinite loop. */
8953 /* Convert ROTATERT to ROTATE. */
8954 if (code
== ROTATERT
)
8955 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
8957 /* We need to determine what mode we will do the shift in. If the
8958 shift is a right shift or a ROTATE, we must always do it in the mode
8959 it was originally done in. Otherwise, we can do it in MODE, the
8960 widest mode encountered. */
8962 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8963 ? result_mode
: mode
);
8965 /* Handle cases where the count is greater than the size of the mode
8966 minus 1. For ASHIFT, use the size minus one as the count (this can
8967 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8968 take the count modulo the size. For other shifts, the result is
8971 Since these shifts are being produced by the compiler by combining
8972 multiple operations, each of which are defined, we know what the
8973 result is supposed to be. */
8975 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
8977 if (code
== ASHIFTRT
)
8978 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8979 else if (code
== ROTATE
|| code
== ROTATERT
)
8980 count
%= GET_MODE_BITSIZE (shift_mode
);
8983 /* We can't simply return zero because there may be an
8991 /* An arithmetic right shift of a quantity known to be -1 or 0
8993 if (code
== ASHIFTRT
8994 && (num_sign_bit_copies (varop
, shift_mode
)
8995 == GET_MODE_BITSIZE (shift_mode
)))
9001 /* If we are doing an arithmetic right shift and discarding all but
9002 the sign bit copies, this is equivalent to doing a shift by the
9003 bitsize minus one. Convert it into that shift because it will often
9004 allow other simplifications. */
9006 if (code
== ASHIFTRT
9007 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9008 >= GET_MODE_BITSIZE (shift_mode
)))
9009 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9011 /* We simplify the tests below and elsewhere by converting
9012 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9013 `make_compound_operation' will convert it to a ASHIFTRT for
9014 those machines (such as Vax) that don't have a LSHIFTRT. */
9015 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9017 && ((nonzero_bits (varop
, shift_mode
)
9018 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9022 switch (GET_CODE (varop
))
9028 new = expand_compound_operation (varop
);
9037 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9038 minus the width of a smaller mode, we can do this with a
9039 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9040 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9041 && ! mode_dependent_address_p (XEXP (varop
, 0))
9042 && ! MEM_VOLATILE_P (varop
)
9043 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9044 MODE_INT
, 1)) != BLKmode
)
9046 if (BYTES_BIG_ENDIAN
)
9047 new = gen_rtx_MEM (tmode
, XEXP (varop
, 0));
9049 new = gen_rtx_MEM (tmode
,
9050 plus_constant (XEXP (varop
, 0),
9051 count
/ BITS_PER_UNIT
));
9053 MEM_COPY_ATTRIBUTES (new, varop
);
9054 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
9055 : ZERO_EXTEND
, mode
, new);
9062 /* Similar to the case above, except that we can only do this if
9063 the resulting mode is the same as that of the underlying
9064 MEM and adjust the address depending on the *bits* endianness
9065 because of the way that bit-field extract insns are defined. */
9066 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9067 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9068 MODE_INT
, 1)) != BLKmode
9069 && tmode
== GET_MODE (XEXP (varop
, 0)))
9071 if (BITS_BIG_ENDIAN
)
9072 new = XEXP (varop
, 0);
9075 new = copy_rtx (XEXP (varop
, 0));
9076 SUBST (XEXP (new, 0),
9077 plus_constant (XEXP (new, 0),
9078 count
/ BITS_PER_UNIT
));
9081 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
9082 : ZERO_EXTEND
, mode
, new);
9089 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9090 the same number of words as what we've seen so far. Then store
9091 the widest mode in MODE. */
9092 if (subreg_lowpart_p (varop
)
9093 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9094 > GET_MODE_SIZE (GET_MODE (varop
)))
9095 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9096 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9099 varop
= SUBREG_REG (varop
);
9100 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9101 mode
= GET_MODE (varop
);
9107 /* Some machines use MULT instead of ASHIFT because MULT
9108 is cheaper. But it is still better on those machines to
9109 merge two shifts into one. */
9110 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9111 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9114 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9115 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9121 /* Similar, for when divides are cheaper. */
9122 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9123 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9126 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9127 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9133 /* If we are extracting just the sign bit of an arithmetic right
9134 shift, that shift is not needed. */
9135 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1)
9137 varop
= XEXP (varop
, 0);
9141 /* ... fall through ... */
9146 /* Here we have two nested shifts. The result is usually the
9147 AND of a new shift with a mask. We compute the result below. */
9148 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9149 && INTVAL (XEXP (varop
, 1)) >= 0
9150 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9151 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9152 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9154 enum rtx_code first_code
= GET_CODE (varop
);
9155 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9156 unsigned HOST_WIDE_INT mask
;
9159 /* We have one common special case. We can't do any merging if
9160 the inner code is an ASHIFTRT of a smaller mode. However, if
9161 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9162 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9163 we can convert it to
9164 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9165 This simplifies certain SIGN_EXTEND operations. */
9166 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9167 && (GET_MODE_BITSIZE (result_mode
)
9168 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
9170 /* C3 has the low-order C1 bits zero. */
9172 mask
= (GET_MODE_MASK (mode
)
9173 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9175 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9176 XEXP (varop
, 0), mask
);
9177 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9179 count
= first_count
;
9184 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9185 than C1 high-order bits equal to the sign bit, we can convert
9186 this to either an ASHIFT or a ASHIFTRT depending on the
9189 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9191 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9192 && GET_MODE (varop
) == shift_mode
9193 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9196 varop
= XEXP (varop
, 0);
9198 signed_count
= count
- first_count
;
9199 if (signed_count
< 0)
9200 count
= -signed_count
, code
= ASHIFT
;
9202 count
= signed_count
;
9207 /* There are some cases we can't do. If CODE is ASHIFTRT,
9208 we can only do this if FIRST_CODE is also ASHIFTRT.
9210 We can't do the case when CODE is ROTATE and FIRST_CODE is
9213 If the mode of this shift is not the mode of the outer shift,
9214 we can't do this if either shift is a right shift or ROTATE.
9216 Finally, we can't do any of these if the mode is too wide
9217 unless the codes are the same.
9219 Handle the case where the shift codes are the same
9222 if (code
== first_code
)
9224 if (GET_MODE (varop
) != result_mode
9225 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9229 count
+= first_count
;
9230 varop
= XEXP (varop
, 0);
9234 if (code
== ASHIFTRT
9235 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9236 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9237 || (GET_MODE (varop
) != result_mode
9238 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9239 || first_code
== ROTATE
9240 || code
== ROTATE
)))
9243 /* To compute the mask to apply after the shift, shift the
9244 nonzero bits of the inner shift the same way the
9245 outer shift will. */
9247 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9250 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9253 /* Give up if we can't compute an outer operation to use. */
9255 || GET_CODE (mask_rtx
) != CONST_INT
9256 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9258 result_mode
, &complement_p
))
9261 /* If the shifts are in the same direction, we add the
9262 counts. Otherwise, we subtract them. */
9263 signed_count
= count
;
9264 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9265 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9266 signed_count
+= first_count
;
9268 signed_count
-= first_count
;
9270 /* If COUNT is positive, the new shift is usually CODE,
9271 except for the two exceptions below, in which case it is
9272 FIRST_CODE. If the count is negative, FIRST_CODE should
9274 if (signed_count
> 0
9275 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9276 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9277 code
= first_code
, count
= signed_count
;
9278 else if (signed_count
< 0)
9279 code
= first_code
, count
= -signed_count
;
9281 count
= signed_count
;
9283 varop
= XEXP (varop
, 0);
9287 /* If we have (A << B << C) for any shift, we can convert this to
9288 (A << C << B). This wins if A is a constant. Only try this if
9289 B is not a constant. */
9291 else if (GET_CODE (varop
) == code
9292 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9294 = simplify_binary_operation (code
, mode
,
9298 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
9305 /* Make this fit the case below. */
9306 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
9307 GEN_INT (GET_MODE_MASK (mode
)));
9313 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9314 with C the size of VAROP - 1 and the shift is logical if
9315 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9316 we have an (le X 0) operation. If we have an arithmetic shift
9317 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9318 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9320 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9321 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9322 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9323 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9324 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9325 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9328 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
9331 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9332 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9337 /* If we have (shift (logical)), move the logical to the outside
9338 to allow it to possibly combine with another logical and the
9339 shift to combine with another shift. This also canonicalizes to
9340 what a ZERO_EXTRACT looks like. Also, some machines have
9341 (and (shift)) insns. */
9343 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9344 && (new = simplify_binary_operation (code
, result_mode
,
9346 GEN_INT (count
))) != 0
9347 && GET_CODE (new) == CONST_INT
9348 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9349 INTVAL (new), result_mode
, &complement_p
))
9351 varop
= XEXP (varop
, 0);
9355 /* If we can't do that, try to simplify the shift in each arm of the
9356 logical expression, make a new logical expression, and apply
9357 the inverse distributive law. */
9359 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9360 XEXP (varop
, 0), count
);
9361 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9362 XEXP (varop
, 1), count
);
9364 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9365 varop
= apply_distributive_law (varop
);
9372 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9373 says that the sign bit can be tested, FOO has mode MODE, C is
9374 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9375 that may be nonzero. */
9376 if (code
== LSHIFTRT
9377 && XEXP (varop
, 1) == const0_rtx
9378 && GET_MODE (XEXP (varop
, 0)) == result_mode
9379 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9380 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9381 && ((STORE_FLAG_VALUE
9382 & ((HOST_WIDE_INT
) 1
9383 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9384 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9385 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9386 (HOST_WIDE_INT
) 1, result_mode
,
9389 varop
= XEXP (varop
, 0);
9396 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9397 than the number of bits in the mode is equivalent to A. */
9398 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9399 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9401 varop
= XEXP (varop
, 0);
9406 /* NEG commutes with ASHIFT since it is multiplication. Move the
9407 NEG outside to allow shifts to combine. */
9409 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9410 (HOST_WIDE_INT
) 0, result_mode
,
9413 varop
= XEXP (varop
, 0);
9419 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9420 is one less than the number of bits in the mode is
9421 equivalent to (xor A 1). */
9422 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9423 && XEXP (varop
, 1) == constm1_rtx
9424 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9425 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9426 (HOST_WIDE_INT
) 1, result_mode
,
9430 varop
= XEXP (varop
, 0);
9434 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9435 that might be nonzero in BAR are those being shifted out and those
9436 bits are known zero in FOO, we can replace the PLUS with FOO.
9437 Similarly in the other operand order. This code occurs when
9438 we are computing the size of a variable-size array. */
9440 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9441 && count
< HOST_BITS_PER_WIDE_INT
9442 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9443 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9444 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9446 varop
= XEXP (varop
, 0);
9449 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9450 && count
< HOST_BITS_PER_WIDE_INT
9451 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9452 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9454 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9455 & nonzero_bits (XEXP (varop
, 1),
9458 varop
= XEXP (varop
, 1);
9462 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9464 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9465 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9467 GEN_INT (count
))) != 0
9468 && GET_CODE (new) == CONST_INT
9469 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9470 INTVAL (new), result_mode
, &complement_p
))
9472 varop
= XEXP (varop
, 0);
9478 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9479 with C the size of VAROP - 1 and the shift is logical if
9480 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9481 we have a (gt X 0) operation. If the shift is arithmetic with
9482 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9483 we have a (neg (gt X 0)) operation. */
9485 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9486 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9487 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9488 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9489 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9490 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9491 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9494 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
9497 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9498 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9505 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9506 if the truncate does not affect the value. */
9507 if (code
== LSHIFTRT
9508 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9509 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9510 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9511 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9512 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9514 rtx varop_inner
= XEXP (varop
, 0);
9517 = gen_rtx_combine (LSHIFTRT
, GET_MODE (varop_inner
),
9518 XEXP (varop_inner
, 0),
9520 + INTVAL (XEXP (varop_inner
, 1))));
9521 varop
= gen_rtx_combine (TRUNCATE
, GET_MODE (varop
),
9535 /* We need to determine what mode to do the shift in. If the shift is
9536 a right shift or ROTATE, we must always do it in the mode it was
9537 originally done in. Otherwise, we can do it in MODE, the widest mode
9538 encountered. The code we care about is that of the shift that will
9539 actually be done, not the shift that was originally requested. */
9541 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9542 ? result_mode
: mode
);
9544 /* We have now finished analyzing the shift. The result should be
9545 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9546 OUTER_OP is non-NIL, it is an operation that needs to be applied
9547 to the result of the shift. OUTER_CONST is the relevant constant,
9548 but we must turn off all bits turned off in the shift.
9550 If we were passed a value for X, see if we can use any pieces of
9551 it. If not, make new rtx. */
9553 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9554 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9555 && INTVAL (XEXP (x
, 1)) == count
)
9556 const_rtx
= XEXP (x
, 1);
9558 const_rtx
= GEN_INT (count
);
9560 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9561 && GET_MODE (XEXP (x
, 0)) == shift_mode
9562 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9563 varop
= XEXP (x
, 0);
9564 else if (GET_MODE (varop
) != shift_mode
)
9565 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9567 /* If we can't make the SUBREG, try to return what we were given. */
9568 if (GET_CODE (varop
) == CLOBBER
)
9569 return x
? x
: varop
;
9571 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9576 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9577 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
9579 SUBST (XEXP (x
, 0), varop
);
9580 SUBST (XEXP (x
, 1), const_rtx
);
9583 /* If we have an outer operation and we just made a shift, it is
9584 possible that we could have simplified the shift were it not
9585 for the outer operation. So try to do the simplification
9588 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9589 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9590 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9591 INTVAL (XEXP (x
, 1)));
9593 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9594 turn off all the bits that the shift would have turned off. */
9595 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9596 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9597 GET_MODE_MASK (result_mode
) >> orig_count
);
9599 /* Do the remainder of the processing in RESULT_MODE. */
9600 x
= gen_lowpart_for_combine (result_mode
, x
);
9602 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9605 x
= gen_unary (NOT
, result_mode
, result_mode
, x
);
9607 if (outer_op
!= NIL
)
9609 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9610 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9612 if (outer_op
== AND
)
9613 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9614 else if (outer_op
== SET
)
9615 /* This means that we have determined that the result is
9616 equivalent to a constant. This should be rare. */
9617 x
= GEN_INT (outer_const
);
9618 else if (GET_RTX_CLASS (outer_op
) == '1')
9619 x
= gen_unary (outer_op
, result_mode
, result_mode
, x
);
9621 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9627 /* Like recog, but we receive the address of a pointer to a new pattern.
9628 We try to match the rtx that the pointer points to.
9629 If that fails, we may try to modify or replace the pattern,
9630 storing the replacement into the same pointer object.
9632 Modifications include deletion or addition of CLOBBERs.
9634 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9635 the CLOBBERs are placed.
9637 The value is the final insn code from the pattern ultimately matched,
9641 recog_for_combine (pnewpat
, insn
, pnotes
)
9646 register rtx pat
= *pnewpat
;
9647 int insn_code_number
;
9648 int num_clobbers_to_add
= 0;
9653 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9654 we use to indicate that something didn't match. If we find such a
9655 thing, force rejection. */
9656 if (GET_CODE (pat
) == PARALLEL
)
9657 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9658 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9659 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9662 /* Remove the old notes prior to trying to recognize the new pattern. */
9663 old_notes
= REG_NOTES (insn
);
9664 REG_NOTES (insn
) = 0;
9666 /* Is the result of combination a valid instruction? */
9667 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9669 /* If it isn't, there is the possibility that we previously had an insn
9670 that clobbered some register as a side effect, but the combined
9671 insn doesn't need to do that. So try once more without the clobbers
9672 unless this represents an ASM insn. */
9674 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9675 && GET_CODE (pat
) == PARALLEL
)
9679 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9680 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9683 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9687 SUBST_INT (XVECLEN (pat
, 0), pos
);
9690 pat
= XVECEXP (pat
, 0, 0);
9692 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9695 REG_NOTES (insn
) = old_notes
;
9697 /* If we had any clobbers to add, make a new pattern than contains
9698 them. Then check to make sure that all of them are dead. */
9699 if (num_clobbers_to_add
)
9701 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9702 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9704 + num_clobbers_to_add
)
9705 : num_clobbers_to_add
+ 1));
9707 if (GET_CODE (pat
) == PARALLEL
)
9708 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9709 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9711 XVECEXP (newpat
, 0, 0) = pat
;
9713 add_clobbers (newpat
, insn_code_number
);
9715 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9716 i
< XVECLEN (newpat
, 0); i
++)
9718 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9719 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9721 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9722 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9730 return insn_code_number
;
9733 /* Like gen_lowpart but for use by combine. In combine it is not possible
9734 to create any new pseudoregs. However, it is safe to create
9735 invalid memory addresses, because combine will try to recognize
9736 them and all they will do is make the combine attempt fail.
9738 If for some reason this cannot do its job, an rtx
9739 (clobber (const_int 0)) is returned.
9740 An insn containing that will not be recognized. */
9745 gen_lowpart_for_combine (mode
, x
)
9746 enum machine_mode mode
;
9751 if (GET_MODE (x
) == mode
)
9754 /* We can only support MODE being wider than a word if X is a
9755 constant integer or has a mode the same size. */
9757 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9758 && ! ((GET_MODE (x
) == VOIDmode
9759 && (GET_CODE (x
) == CONST_INT
9760 || GET_CODE (x
) == CONST_DOUBLE
))
9761 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9762 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9764 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9765 won't know what to do. So we will strip off the SUBREG here and
9766 process normally. */
9767 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9770 if (GET_MODE (x
) == mode
)
9774 result
= gen_lowpart_common (mode
, x
);
9775 #ifdef CLASS_CANNOT_CHANGE_MODE
9777 && GET_CODE (result
) == SUBREG
9778 && GET_CODE (SUBREG_REG (result
)) == REG
9779 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9780 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9781 GET_MODE (SUBREG_REG (result
))))
9782 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9788 if (GET_CODE (x
) == MEM
)
9790 register int offset
= 0;
9793 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9795 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9796 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9798 /* If we want to refer to something bigger than the original memref,
9799 generate a perverse subreg instead. That will force a reload
9800 of the original memref X. */
9801 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9802 return gen_rtx_SUBREG (mode
, x
, 0);
9804 if (WORDS_BIG_ENDIAN
)
9805 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9806 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9808 if (BYTES_BIG_ENDIAN
)
9810 /* Adjust the address so that the address-after-the-data is
9812 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9813 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9815 new = gen_rtx_MEM (mode
, plus_constant (XEXP (x
, 0), offset
));
9816 MEM_COPY_ATTRIBUTES (new, x
);
9820 /* If X is a comparison operator, rewrite it in a new mode. This
9821 probably won't match, but may allow further simplifications. */
9822 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9823 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9825 /* If we couldn't simplify X any other way, just enclose it in a
9826 SUBREG. Normally, this SUBREG won't match, but some patterns may
9827 include an explicit SUBREG or we may simplify it further in combine. */
9832 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
9833 word
= ((GET_MODE_SIZE (GET_MODE (x
))
9834 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
9836 return gen_rtx_SUBREG (mode
, x
, word
);
9840 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9841 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9843 If the identical expression was previously in the insn (in the undobuf),
9844 it will be returned. Only if it is not found will a new expression
9849 gen_rtx_combine
VPARAMS ((enum rtx_code code
, enum machine_mode mode
, ...))
9851 #ifndef ANSI_PROTOTYPES
9853 enum machine_mode mode
;
9865 #ifndef ANSI_PROTOTYPES
9866 code
= va_arg (p
, enum rtx_code
);
9867 mode
= va_arg (p
, enum machine_mode
);
9870 n_args
= GET_RTX_LENGTH (code
);
9871 fmt
= GET_RTX_FORMAT (code
);
9873 if (n_args
== 0 || n_args
> 3)
9876 /* Get each arg and verify that it is supposed to be an expression. */
9877 for (j
= 0; j
< n_args
; j
++)
9882 args
[j
] = va_arg (p
, rtx
);
9887 /* See if this is in undobuf. Be sure we don't use objects that came
9888 from another insn; this could produce circular rtl structures. */
9890 for (undo
= undobuf
.undos
; undo
!= undobuf
.previous_undos
; undo
= undo
->next
)
9892 && GET_CODE (undo
->old_contents
.r
) == code
9893 && GET_MODE (undo
->old_contents
.r
) == mode
)
9895 for (j
= 0; j
< n_args
; j
++)
9896 if (XEXP (undo
->old_contents
.r
, j
) != args
[j
])
9900 return undo
->old_contents
.r
;
9903 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9904 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9905 rt
= rtx_alloc (code
);
9906 PUT_MODE (rt
, mode
);
9907 XEXP (rt
, 0) = args
[0];
9910 XEXP (rt
, 1) = args
[1];
9912 XEXP (rt
, 2) = args
[2];
9917 /* These routines make binary and unary operations by first seeing if they
9918 fold; if not, a new expression is allocated. */
9921 gen_binary (code
, mode
, op0
, op1
)
9923 enum machine_mode mode
;
9929 if (GET_RTX_CLASS (code
) == 'c'
9930 && (GET_CODE (op0
) == CONST_INT
9931 || (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)))
9932 tem
= op0
, op0
= op1
, op1
= tem
;
9934 if (GET_RTX_CLASS (code
) == '<')
9936 enum machine_mode op_mode
= GET_MODE (op0
);
9938 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9939 just (REL_OP X Y). */
9940 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9942 op1
= XEXP (op0
, 1);
9943 op0
= XEXP (op0
, 0);
9944 op_mode
= GET_MODE (op0
);
9947 if (op_mode
== VOIDmode
)
9948 op_mode
= GET_MODE (op1
);
9949 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9952 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9957 /* Put complex operands first and constants second. */
9958 if (GET_RTX_CLASS (code
) == 'c'
9959 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
9960 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
9961 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
9962 || (GET_CODE (op0
) == SUBREG
9963 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
9964 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
9965 return gen_rtx_combine (code
, mode
, op1
, op0
);
9967 /* If we are turning off bits already known off in OP0, we need not do
9969 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9970 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9971 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9974 return gen_rtx_combine (code
, mode
, op0
, op1
);
9978 gen_unary (code
, mode
, op0_mode
, op0
)
9980 enum machine_mode mode
, op0_mode
;
9983 rtx result
= simplify_unary_operation (code
, mode
, op0
, op0_mode
);
9988 return gen_rtx_combine (code
, mode
, op0
);
9991 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9992 comparison code that will be tested.
9994 The result is a possibly different comparison code to use. *POP0 and
9995 *POP1 may be updated.
9997 It is possible that we might detect that a comparison is either always
9998 true or always false. However, we do not perform general constant
9999 folding in combine, so this knowledge isn't useful. Such tautologies
10000 should have been detected earlier. Hence we ignore all such cases. */
10002 static enum rtx_code
10003 simplify_comparison (code
, pop0
, pop1
)
10004 enum rtx_code code
;
10012 enum machine_mode mode
, tmode
;
10014 /* Try a few ways of applying the same transformation to both operands. */
10017 #ifndef WORD_REGISTER_OPERATIONS
10018 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10019 so check specially. */
10020 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10021 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10022 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10023 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10024 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10025 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10026 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10027 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10028 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10029 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
10030 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10031 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
10032 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
10033 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
10034 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
10035 && (INTVAL (XEXP (op0
, 1))
10036 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10037 - (GET_MODE_BITSIZE
10038 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10040 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10041 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10045 /* If both operands are the same constant shift, see if we can ignore the
10046 shift. We can if the shift is a rotate or if the bits shifted out of
10047 this shift are known to be zero for both inputs and if the type of
10048 comparison is compatible with the shift. */
10049 if (GET_CODE (op0
) == GET_CODE (op1
)
10050 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10051 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10052 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10053 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10054 || (GET_CODE (op0
) == ASHIFTRT
10055 && (code
!= GTU
&& code
!= LTU
10056 && code
!= GEU
&& code
!= GEU
)))
10057 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10058 && INTVAL (XEXP (op0
, 1)) >= 0
10059 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10060 && XEXP (op0
, 1) == XEXP (op1
, 1))
10062 enum machine_mode mode
= GET_MODE (op0
);
10063 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10064 int shift_count
= INTVAL (XEXP (op0
, 1));
10066 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10067 mask
&= (mask
>> shift_count
) << shift_count
;
10068 else if (GET_CODE (op0
) == ASHIFT
)
10069 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10071 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10072 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10073 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10078 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10079 SUBREGs are of the same mode, and, in both cases, the AND would
10080 be redundant if the comparison was done in the narrower mode,
10081 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10082 and the operand's possibly nonzero bits are 0xffffff01; in that case
10083 if we only care about QImode, we don't need the AND). This case
10084 occurs if the output mode of an scc insn is not SImode and
10085 STORE_FLAG_VALUE == 1 (e.g., the 386).
10087 Similarly, check for a case where the AND's are ZERO_EXTEND
10088 operations from some narrower mode even though a SUBREG is not
10091 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10092 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10093 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10095 rtx inner_op0
= XEXP (op0
, 0);
10096 rtx inner_op1
= XEXP (op1
, 0);
10097 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10098 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10101 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10102 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10103 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10104 && (GET_MODE (SUBREG_REG (inner_op0
))
10105 == GET_MODE (SUBREG_REG (inner_op1
)))
10106 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10107 <= HOST_BITS_PER_WIDE_INT
)
10108 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10109 GET_MODE (SUBREG_REG (inner_op0
)))))
10110 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10111 GET_MODE (SUBREG_REG (inner_op1
))))))
10113 op0
= SUBREG_REG (inner_op0
);
10114 op1
= SUBREG_REG (inner_op1
);
10116 /* The resulting comparison is always unsigned since we masked
10117 off the original sign bit. */
10118 code
= unsigned_condition (code
);
10124 for (tmode
= GET_CLASS_NARROWEST_MODE
10125 (GET_MODE_CLASS (GET_MODE (op0
)));
10126 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10127 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10129 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10130 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10131 code
= unsigned_condition (code
);
10140 /* If both operands are NOT, we can strip off the outer operation
10141 and adjust the comparison code for swapped operands; similarly for
10142 NEG, except that this must be an equality comparison. */
10143 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10144 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10145 && (code
== EQ
|| code
== NE
)))
10146 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10152 /* If the first operand is a constant, swap the operands and adjust the
10153 comparison code appropriately, but don't do this if the second operand
10154 is already a constant integer. */
10155 if (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
10157 tem
= op0
, op0
= op1
, op1
= tem
;
10158 code
= swap_condition (code
);
10161 /* We now enter a loop during which we will try to simplify the comparison.
10162 For the most part, we only are concerned with comparisons with zero,
10163 but some things may really be comparisons with zero but not start
10164 out looking that way. */
10166 while (GET_CODE (op1
) == CONST_INT
)
10168 enum machine_mode mode
= GET_MODE (op0
);
10169 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10170 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10171 int equality_comparison_p
;
10172 int sign_bit_comparison_p
;
10173 int unsigned_comparison_p
;
10174 HOST_WIDE_INT const_op
;
10176 /* We only want to handle integral modes. This catches VOIDmode,
10177 CCmode, and the floating-point modes. An exception is that we
10178 can handle VOIDmode if OP0 is a COMPARE or a comparison
10181 if (GET_MODE_CLASS (mode
) != MODE_INT
10182 && ! (mode
== VOIDmode
10183 && (GET_CODE (op0
) == COMPARE
10184 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10187 /* Get the constant we are comparing against and turn off all bits
10188 not on in our mode. */
10189 const_op
= trunc_int_for_mode (INTVAL (op1
), mode
);
10191 /* If we are comparing against a constant power of two and the value
10192 being compared can only have that single bit nonzero (e.g., it was
10193 `and'ed with that bit), we can replace this with a comparison
10196 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10197 || code
== LT
|| code
== LTU
)
10198 && mode_width
<= HOST_BITS_PER_WIDE_INT
10199 && exact_log2 (const_op
) >= 0
10200 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10202 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10203 op1
= const0_rtx
, const_op
= 0;
10206 /* Similarly, if we are comparing a value known to be either -1 or
10207 0 with -1, change it to the opposite comparison against zero. */
10210 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10211 || code
== GEU
|| code
== LTU
)
10212 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10214 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10215 op1
= const0_rtx
, const_op
= 0;
10218 /* Do some canonicalizations based on the comparison code. We prefer
10219 comparisons against zero and then prefer equality comparisons.
10220 If we can reduce the size of a constant, we will do that too. */
10225 /* < C is equivalent to <= (C - 1) */
10229 op1
= GEN_INT (const_op
);
10231 /* ... fall through to LE case below. */
10237 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10241 op1
= GEN_INT (const_op
);
10245 /* If we are doing a <= 0 comparison on a value known to have
10246 a zero sign bit, we can replace this with == 0. */
10247 else if (const_op
== 0
10248 && mode_width
<= HOST_BITS_PER_WIDE_INT
10249 && (nonzero_bits (op0
, mode
)
10250 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10255 /* >= C is equivalent to > (C - 1). */
10259 op1
= GEN_INT (const_op
);
10261 /* ... fall through to GT below. */
10267 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10271 op1
= GEN_INT (const_op
);
10275 /* If we are doing a > 0 comparison on a value known to have
10276 a zero sign bit, we can replace this with != 0. */
10277 else if (const_op
== 0
10278 && mode_width
<= HOST_BITS_PER_WIDE_INT
10279 && (nonzero_bits (op0
, mode
)
10280 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10285 /* < C is equivalent to <= (C - 1). */
10289 op1
= GEN_INT (const_op
);
10291 /* ... fall through ... */
10294 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10295 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10296 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10298 const_op
= 0, op1
= const0_rtx
;
10306 /* unsigned <= 0 is equivalent to == 0 */
10310 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10311 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10312 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10314 const_op
= 0, op1
= const0_rtx
;
10320 /* >= C is equivalent to < (C - 1). */
10324 op1
= GEN_INT (const_op
);
10326 /* ... fall through ... */
10329 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10330 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10331 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10333 const_op
= 0, op1
= const0_rtx
;
10341 /* unsigned > 0 is equivalent to != 0 */
10345 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10346 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10347 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10349 const_op
= 0, op1
= const0_rtx
;
10358 /* Compute some predicates to simplify code below. */
10360 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10361 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10362 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10365 /* If this is a sign bit comparison and we can do arithmetic in
10366 MODE, say that we will only be needing the sign bit of OP0. */
10367 if (sign_bit_comparison_p
10368 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10369 op0
= force_to_mode (op0
, mode
,
10371 << (GET_MODE_BITSIZE (mode
) - 1)),
10374 /* Now try cases based on the opcode of OP0. If none of the cases
10375 does a "continue", we exit this loop immediately after the
10378 switch (GET_CODE (op0
))
10381 /* If we are extracting a single bit from a variable position in
10382 a constant that has only a single bit set and are comparing it
10383 with zero, we can convert this into an equality comparison
10384 between the position and the location of the single bit. */
10386 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10387 && XEXP (op0
, 1) == const1_rtx
10388 && equality_comparison_p
&& const_op
== 0
10389 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10391 if (BITS_BIG_ENDIAN
)
10394 mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
10395 if (mode
== VOIDmode
)
10397 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10399 i
= BITS_PER_WORD
- 1 - i
;
10403 op0
= XEXP (op0
, 2);
10407 /* Result is nonzero iff shift count is equal to I. */
10408 code
= reverse_condition (code
);
10412 /* ... fall through ... */
10415 tem
= expand_compound_operation (op0
);
10424 /* If testing for equality, we can take the NOT of the constant. */
10425 if (equality_comparison_p
10426 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10428 op0
= XEXP (op0
, 0);
10433 /* If just looking at the sign bit, reverse the sense of the
10435 if (sign_bit_comparison_p
)
10437 op0
= XEXP (op0
, 0);
10438 code
= (code
== GE
? LT
: GE
);
10444 /* If testing for equality, we can take the NEG of the constant. */
10445 if (equality_comparison_p
10446 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10448 op0
= XEXP (op0
, 0);
10453 /* The remaining cases only apply to comparisons with zero. */
10457 /* When X is ABS or is known positive,
10458 (neg X) is < 0 if and only if X != 0. */
10460 if (sign_bit_comparison_p
10461 && (GET_CODE (XEXP (op0
, 0)) == ABS
10462 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10463 && (nonzero_bits (XEXP (op0
, 0), mode
)
10464 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10466 op0
= XEXP (op0
, 0);
10467 code
= (code
== LT
? NE
: EQ
);
10471 /* If we have NEG of something whose two high-order bits are the
10472 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10473 if (num_sign_bit_copies (op0
, mode
) >= 2)
10475 op0
= XEXP (op0
, 0);
10476 code
= swap_condition (code
);
10482 /* If we are testing equality and our count is a constant, we
10483 can perform the inverse operation on our RHS. */
10484 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10485 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10486 op1
, XEXP (op0
, 1))) != 0)
10488 op0
= XEXP (op0
, 0);
10493 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10494 a particular bit. Convert it to an AND of a constant of that
10495 bit. This will be converted into a ZERO_EXTRACT. */
10496 if (const_op
== 0 && sign_bit_comparison_p
10497 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10498 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10500 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10503 - INTVAL (XEXP (op0
, 1)))));
10504 code
= (code
== LT
? NE
: EQ
);
10508 /* Fall through. */
10511 /* ABS is ignorable inside an equality comparison with zero. */
10512 if (const_op
== 0 && equality_comparison_p
)
10514 op0
= XEXP (op0
, 0);
10520 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10521 to (compare FOO CONST) if CONST fits in FOO's mode and we
10522 are either testing inequality or have an unsigned comparison
10523 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10524 if (! unsigned_comparison_p
10525 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10526 <= HOST_BITS_PER_WIDE_INT
)
10527 && ((unsigned HOST_WIDE_INT
) const_op
10528 < (((unsigned HOST_WIDE_INT
) 1
10529 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10531 op0
= XEXP (op0
, 0);
10537 /* Check for the case where we are comparing A - C1 with C2,
10538 both constants are smaller than 1/2 the maximum positive
10539 value in MODE, and the comparison is equality or unsigned.
10540 In that case, if A is either zero-extended to MODE or has
10541 sufficient sign bits so that the high-order bit in MODE
10542 is a copy of the sign in the inner mode, we can prove that it is
10543 safe to do the operation in the wider mode. This simplifies
10544 many range checks. */
10546 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10547 && subreg_lowpart_p (op0
)
10548 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10549 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10550 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10551 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10552 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10553 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10554 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10555 GET_MODE (SUBREG_REG (op0
)))
10556 & ~GET_MODE_MASK (mode
))
10557 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10558 GET_MODE (SUBREG_REG (op0
)))
10559 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10560 - GET_MODE_BITSIZE (mode
)))))
10562 op0
= SUBREG_REG (op0
);
10566 /* If the inner mode is narrower and we are extracting the low part,
10567 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10568 if (subreg_lowpart_p (op0
)
10569 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10570 /* Fall through */ ;
10574 /* ... fall through ... */
10577 if ((unsigned_comparison_p
|| equality_comparison_p
)
10578 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10579 <= HOST_BITS_PER_WIDE_INT
)
10580 && ((unsigned HOST_WIDE_INT
) const_op
10581 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10583 op0
= XEXP (op0
, 0);
10589 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10590 this for equality comparisons due to pathological cases involving
10592 if (equality_comparison_p
10593 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10594 op1
, XEXP (op0
, 1))))
10596 op0
= XEXP (op0
, 0);
10601 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10602 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10603 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10605 op0
= XEXP (XEXP (op0
, 0), 0);
10606 code
= (code
== LT
? EQ
: NE
);
10612 /* We used to optimize signed comparisons against zero, but that
10613 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10614 arrive here as equality comparisons, or (GEU, LTU) are
10615 optimized away. No need to special-case them. */
10617 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10618 (eq B (minus A C)), whichever simplifies. We can only do
10619 this for equality comparisons due to pathological cases involving
10621 if (equality_comparison_p
10622 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10623 XEXP (op0
, 1), op1
)))
10625 op0
= XEXP (op0
, 0);
10630 if (equality_comparison_p
10631 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10632 XEXP (op0
, 0), op1
)))
10634 op0
= XEXP (op0
, 1);
10639 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10640 of bits in X minus 1, is one iff X > 0. */
10641 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10642 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10643 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10644 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10646 op0
= XEXP (op0
, 1);
10647 code
= (code
== GE
? LE
: GT
);
10653 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10654 if C is zero or B is a constant. */
10655 if (equality_comparison_p
10656 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10657 XEXP (op0
, 1), op1
)))
10659 op0
= XEXP (op0
, 0);
10666 case LT
: case LTU
: case LE
: case LEU
:
10667 case GT
: case GTU
: case GE
: case GEU
:
10668 /* We can't do anything if OP0 is a condition code value, rather
10669 than an actual data value. */
10672 || XEXP (op0
, 0) == cc0_rtx
10674 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10677 /* Get the two operands being compared. */
10678 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10679 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10681 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10683 /* Check for the cases where we simply want the result of the
10684 earlier test or the opposite of that result. */
10686 || (code
== EQ
&& reversible_comparison_p (op0
))
10687 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10688 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10689 && (STORE_FLAG_VALUE
10690 & (((HOST_WIDE_INT
) 1
10691 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10693 || (code
== GE
&& reversible_comparison_p (op0
)))))
10695 code
= (code
== LT
|| code
== NE
10696 ? GET_CODE (op0
) : reverse_condition (GET_CODE (op0
)));
10697 op0
= tem
, op1
= tem1
;
10703 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10705 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10706 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10707 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10709 op0
= XEXP (op0
, 1);
10710 code
= (code
== GE
? GT
: LE
);
10716 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10717 will be converted to a ZERO_EXTRACT later. */
10718 if (const_op
== 0 && equality_comparison_p
10719 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10720 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10722 op0
= simplify_and_const_int
10723 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10725 XEXP (XEXP (op0
, 0), 1)),
10726 (HOST_WIDE_INT
) 1);
10730 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10731 zero and X is a comparison and C1 and C2 describe only bits set
10732 in STORE_FLAG_VALUE, we can compare with X. */
10733 if (const_op
== 0 && equality_comparison_p
10734 && mode_width
<= HOST_BITS_PER_WIDE_INT
10735 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10736 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10737 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10738 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10739 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10741 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10742 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10743 if ((~STORE_FLAG_VALUE
& mask
) == 0
10744 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10745 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10746 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10748 op0
= XEXP (XEXP (op0
, 0), 0);
10753 /* If we are doing an equality comparison of an AND of a bit equal
10754 to the sign bit, replace this with a LT or GE comparison of
10755 the underlying value. */
10756 if (equality_comparison_p
10758 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10759 && mode_width
<= HOST_BITS_PER_WIDE_INT
10760 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10761 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10763 op0
= XEXP (op0
, 0);
10764 code
= (code
== EQ
? GE
: LT
);
10768 /* If this AND operation is really a ZERO_EXTEND from a narrower
10769 mode, the constant fits within that mode, and this is either an
10770 equality or unsigned comparison, try to do this comparison in
10771 the narrower mode. */
10772 if ((equality_comparison_p
|| unsigned_comparison_p
)
10773 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10774 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10775 & GET_MODE_MASK (mode
))
10777 && const_op
>> i
== 0
10778 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10780 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10784 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10785 in both M1 and M2 and the SUBREG is either paradoxical or
10786 represents the low part, permute the SUBREG and the AND and
10788 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10790 #ifdef WORD_REGISTER_OPERATIONS
10792 > (GET_MODE_BITSIZE
10793 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10794 && mode_width
<= BITS_PER_WORD
)
10797 <= (GET_MODE_BITSIZE
10798 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10799 && subreg_lowpart_p (XEXP (op0
, 0))))
10800 #ifndef WORD_REGISTER_OPERATIONS
10801 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10802 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10803 As originally written the upper bits have a defined value
10804 due to the AND operation. However, if we commute the AND
10805 inside the SUBREG then they no longer have defined values
10806 and the meaning of the code has been changed. */
10807 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10808 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10810 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10811 && mode_width
<= HOST_BITS_PER_WIDE_INT
10812 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10813 <= HOST_BITS_PER_WIDE_INT
)
10814 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10815 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10816 & INTVAL (XEXP (op0
, 1)))
10817 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10818 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10819 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10823 = gen_lowpart_for_combine
10825 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10826 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10830 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10831 (eq (and (lshiftrt X) 1) 0). */
10832 if (const_op
== 0 && equality_comparison_p
10833 && XEXP (op0
, 1) == const1_rtx
10834 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10835 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10837 op0
= simplify_and_const_int
10838 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10839 XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10840 XEXP (XEXP (op0
, 0), 1)),
10841 (HOST_WIDE_INT
) 1);
10842 code
= (code
== NE
? EQ
: NE
);
10848 /* If we have (compare (ashift FOO N) (const_int C)) and
10849 the high order N bits of FOO (N+1 if an inequality comparison)
10850 are known to be zero, we can do this by comparing FOO with C
10851 shifted right N bits so long as the low-order N bits of C are
10853 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10854 && INTVAL (XEXP (op0
, 1)) >= 0
10855 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10856 < HOST_BITS_PER_WIDE_INT
)
10858 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10859 && mode_width
<= HOST_BITS_PER_WIDE_INT
10860 && (nonzero_bits (XEXP (op0
, 0), mode
)
10861 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10862 + ! equality_comparison_p
))) == 0)
10864 /* We must perform a logical shift, not an arithmetic one,
10865 as we want the top N bits of C to be zero. */
10866 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10868 temp
>>= INTVAL (XEXP (op0
, 1));
10869 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10870 op0
= XEXP (op0
, 0);
10874 /* If we are doing a sign bit comparison, it means we are testing
10875 a particular bit. Convert it to the appropriate AND. */
10876 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10877 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10879 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10882 - INTVAL (XEXP (op0
, 1)))));
10883 code
= (code
== LT
? NE
: EQ
);
10887 /* If this an equality comparison with zero and we are shifting
10888 the low bit to the sign bit, we can convert this to an AND of the
10890 if (const_op
== 0 && equality_comparison_p
10891 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10892 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10894 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10895 (HOST_WIDE_INT
) 1);
10901 /* If this is an equality comparison with zero, we can do this
10902 as a logical shift, which might be much simpler. */
10903 if (equality_comparison_p
&& const_op
== 0
10904 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10906 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10908 INTVAL (XEXP (op0
, 1)));
10912 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10913 do the comparison in a narrower mode. */
10914 if (! unsigned_comparison_p
10915 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10916 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10917 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10918 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10919 MODE_INT
, 1)) != BLKmode
10920 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10921 || ((unsigned HOST_WIDE_INT
) -const_op
10922 <= GET_MODE_MASK (tmode
))))
10924 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10928 /* Likewise if OP0 is a PLUS of a sign extension with a
10929 constant, which is usually represented with the PLUS
10930 between the shifts. */
10931 if (! unsigned_comparison_p
10932 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10933 && GET_CODE (XEXP (op0
, 0)) == PLUS
10934 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10935 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10936 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10937 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10938 MODE_INT
, 1)) != BLKmode
10939 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10940 || ((unsigned HOST_WIDE_INT
) -const_op
10941 <= GET_MODE_MASK (tmode
))))
10943 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10944 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10945 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10948 op0
= gen_binary (PLUS
, tmode
,
10949 gen_lowpart_for_combine (tmode
, inner
),
10954 /* ... fall through ... */
10956 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10957 the low order N bits of FOO are known to be zero, we can do this
10958 by comparing FOO with C shifted left N bits so long as no
10959 overflow occurs. */
10960 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10961 && INTVAL (XEXP (op0
, 1)) >= 0
10962 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10963 && mode_width
<= HOST_BITS_PER_WIDE_INT
10964 && (nonzero_bits (XEXP (op0
, 0), mode
)
10965 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10967 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
10970 const_op
<<= INTVAL (XEXP (op0
, 1));
10971 op1
= GEN_INT (const_op
);
10972 op0
= XEXP (op0
, 0);
10976 /* If we are using this shift to extract just the sign bit, we
10977 can replace this with an LT or GE comparison. */
10979 && (equality_comparison_p
|| sign_bit_comparison_p
)
10980 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10981 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10983 op0
= XEXP (op0
, 0);
10984 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10996 /* Now make any compound operations involved in this comparison. Then,
10997 check for an outmost SUBREG on OP0 that is not doing anything or is
10998 paradoxical. The latter case can only occur when it is known that the
10999 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
11000 We can never remove a SUBREG for a non-equality comparison because the
11001 sign bit is in a different place in the underlying object. */
11003 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11004 op1
= make_compound_operation (op1
, SET
);
11006 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11007 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11008 && (code
== NE
|| code
== EQ
)
11009 && ((GET_MODE_SIZE (GET_MODE (op0
))
11010 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
11012 op0
= SUBREG_REG (op0
);
11013 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11016 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11017 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11018 && (code
== NE
|| code
== EQ
)
11019 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11020 <= HOST_BITS_PER_WIDE_INT
)
11021 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
11022 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0
11023 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
11025 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11026 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0))
11027 op0
= SUBREG_REG (op0
), op1
= tem
;
11029 /* We now do the opposite procedure: Some machines don't have compare
11030 insns in all modes. If OP0's mode is an integer mode smaller than a
11031 word and we can't do a compare in that mode, see if there is a larger
11032 mode for which we can do the compare. There are a number of cases in
11033 which we can use the wider mode. */
11035 mode
= GET_MODE (op0
);
11036 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11037 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11038 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
11039 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11041 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11042 tmode
= GET_MODE_WIDER_MODE (tmode
))
11043 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
11045 /* If the only nonzero bits in OP0 and OP1 are those in the
11046 narrower mode and this is an equality or unsigned comparison,
11047 we can use the wider mode. Similarly for sign-extended
11048 values, in which case it is true for all comparisons. */
11049 if (((code
== EQ
|| code
== NE
11050 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
11051 && (nonzero_bits (op0
, tmode
) & ~GET_MODE_MASK (mode
)) == 0
11052 && (nonzero_bits (op1
, tmode
) & ~GET_MODE_MASK (mode
)) == 0)
11053 || ((num_sign_bit_copies (op0
, tmode
)
11054 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
11055 && (num_sign_bit_copies (op1
, tmode
)
11056 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
11058 /* If OP0 is an AND and we don't have an AND in MODE either,
11059 make a new AND in the proper mode. */
11060 if (GET_CODE (op0
) == AND
11061 && (add_optab
->handlers
[(int) mode
].insn_code
11062 == CODE_FOR_nothing
))
11063 op0
= gen_binary (AND
, tmode
,
11064 gen_lowpart_for_combine (tmode
,
11066 gen_lowpart_for_combine (tmode
,
11069 op0
= gen_lowpart_for_combine (tmode
, op0
);
11070 op1
= gen_lowpart_for_combine (tmode
, op1
);
11074 /* If this is a test for negative, we can make an explicit
11075 test of the sign bit. */
11077 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11078 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11080 op0
= gen_binary (AND
, tmode
,
11081 gen_lowpart_for_combine (tmode
, op0
),
11082 GEN_INT ((HOST_WIDE_INT
) 1
11083 << (GET_MODE_BITSIZE (mode
) - 1)));
11084 code
= (code
== LT
) ? NE
: EQ
;
11089 #ifdef CANONICALIZE_COMPARISON
11090 /* If this machine only supports a subset of valid comparisons, see if we
11091 can convert an unsupported one into a supported one. */
11092 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11101 /* Return 1 if we know that X, a comparison operation, is not operating
11102 on a floating-point value or is EQ or NE, meaning that we can safely
11106 reversible_comparison_p (x
)
11109 if (TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
11111 || GET_CODE (x
) == NE
|| GET_CODE (x
) == EQ
11112 || GET_CODE (x
) == UNORDERED
|| GET_CODE (x
) == ORDERED
)
11115 switch (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))))
11118 case MODE_PARTIAL_INT
:
11119 case MODE_COMPLEX_INT
:
11123 /* If the mode of the condition codes tells us that this is safe,
11124 we need look no further. */
11125 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x
, 0))))
11128 /* Otherwise try and find where the condition codes were last set and
11130 x
= get_last_value (XEXP (x
, 0));
11131 return (x
&& GET_CODE (x
) == COMPARE
11132 && ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0))));
11139 /* Utility function for following routine. Called when X is part of a value
11140 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11141 for each register mentioned. Similar to mention_regs in cse.c */
11144 update_table_tick (x
)
11147 register enum rtx_code code
= GET_CODE (x
);
11148 register const char *fmt
= GET_RTX_FORMAT (code
);
11153 unsigned int regno
= REGNO (x
);
11154 unsigned int endregno
11155 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11156 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11159 for (r
= regno
; r
< endregno
; r
++)
11160 reg_last_set_table_tick
[r
] = label_tick
;
11165 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11166 /* Note that we can't have an "E" in values stored; see
11167 get_last_value_validate. */
11169 update_table_tick (XEXP (x
, i
));
11172 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11173 are saying that the register is clobbered and we no longer know its
11174 value. If INSN is zero, don't update reg_last_set; this is only permitted
11175 with VALUE also zero and is used to invalidate the register. */
11178 record_value_for_reg (reg
, insn
, value
)
11183 unsigned int regno
= REGNO (reg
);
11184 unsigned int endregno
11185 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11186 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11189 /* If VALUE contains REG and we have a previous value for REG, substitute
11190 the previous value. */
11191 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11195 /* Set things up so get_last_value is allowed to see anything set up to
11197 subst_low_cuid
= INSN_CUID (insn
);
11198 tem
= get_last_value (reg
);
11200 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11201 it isn't going to be useful and will take a lot of time to process,
11202 so just use the CLOBBER. */
11206 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11207 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11208 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11209 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11210 tem
= XEXP (tem
, 0);
11212 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11216 /* For each register modified, show we don't know its value, that
11217 we don't know about its bitwise content, that its value has been
11218 updated, and that we don't know the location of the death of the
11220 for (i
= regno
; i
< endregno
; i
++)
11223 reg_last_set
[i
] = insn
;
11225 reg_last_set_value
[i
] = 0;
11226 reg_last_set_mode
[i
] = 0;
11227 reg_last_set_nonzero_bits
[i
] = 0;
11228 reg_last_set_sign_bit_copies
[i
] = 0;
11229 reg_last_death
[i
] = 0;
11232 /* Mark registers that are being referenced in this value. */
11234 update_table_tick (value
);
11236 /* Now update the status of each register being set.
11237 If someone is using this register in this block, set this register
11238 to invalid since we will get confused between the two lives in this
11239 basic block. This makes using this register always invalid. In cse, we
11240 scan the table to invalidate all entries using this register, but this
11241 is too much work for us. */
11243 for (i
= regno
; i
< endregno
; i
++)
11245 reg_last_set_label
[i
] = label_tick
;
11246 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11247 reg_last_set_invalid
[i
] = 1;
11249 reg_last_set_invalid
[i
] = 0;
11252 /* The value being assigned might refer to X (like in "x++;"). In that
11253 case, we must replace it with (clobber (const_int 0)) to prevent
11255 if (value
&& ! get_last_value_validate (&value
, insn
,
11256 reg_last_set_label
[regno
], 0))
11258 value
= copy_rtx (value
);
11259 if (! get_last_value_validate (&value
, insn
,
11260 reg_last_set_label
[regno
], 1))
11264 /* For the main register being modified, update the value, the mode, the
11265 nonzero bits, and the number of sign bit copies. */
11267 reg_last_set_value
[regno
] = value
;
11271 subst_low_cuid
= INSN_CUID (insn
);
11272 reg_last_set_mode
[regno
] = GET_MODE (reg
);
11273 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
11274 reg_last_set_sign_bit_copies
[regno
]
11275 = num_sign_bit_copies (value
, GET_MODE (reg
));
11279 /* Called via note_stores from record_dead_and_set_regs to handle one
11280 SET or CLOBBER in an insn. DATA is the instruction in which the
11281 set is occurring. */
11284 record_dead_and_set_regs_1 (dest
, setter
, data
)
11288 rtx record_dead_insn
= (rtx
) data
;
11290 if (GET_CODE (dest
) == SUBREG
)
11291 dest
= SUBREG_REG (dest
);
11293 if (GET_CODE (dest
) == REG
)
11295 /* If we are setting the whole register, we know its value. Otherwise
11296 show that we don't know the value. We can handle SUBREG in
11298 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11299 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11300 else if (GET_CODE (setter
) == SET
11301 && GET_CODE (SET_DEST (setter
)) == SUBREG
11302 && SUBREG_REG (SET_DEST (setter
)) == dest
11303 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11304 && subreg_lowpart_p (SET_DEST (setter
)))
11305 record_value_for_reg (dest
, record_dead_insn
,
11306 gen_lowpart_for_combine (GET_MODE (dest
),
11307 SET_SRC (setter
)));
11309 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11311 else if (GET_CODE (dest
) == MEM
11312 /* Ignore pushes, they clobber nothing. */
11313 && ! push_operand (dest
, GET_MODE (dest
)))
11314 mem_last_set
= INSN_CUID (record_dead_insn
);
11317 /* Update the records of when each REG was most recently set or killed
11318 for the things done by INSN. This is the last thing done in processing
11319 INSN in the combiner loop.
11321 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11322 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11323 and also the similar information mem_last_set (which insn most recently
11324 modified memory) and last_call_cuid (which insn was the most recent
11325 subroutine call). */
11328 record_dead_and_set_regs (insn
)
11334 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11336 if (REG_NOTE_KIND (link
) == REG_DEAD
11337 && GET_CODE (XEXP (link
, 0)) == REG
)
11339 unsigned int regno
= REGNO (XEXP (link
, 0));
11340 unsigned int endregno
11341 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11342 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11345 for (i
= regno
; i
< endregno
; i
++)
11346 reg_last_death
[i
] = insn
;
11348 else if (REG_NOTE_KIND (link
) == REG_INC
)
11349 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11352 if (GET_CODE (insn
) == CALL_INSN
)
11354 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11355 if (call_used_regs
[i
])
11357 reg_last_set_value
[i
] = 0;
11358 reg_last_set_mode
[i
] = 0;
11359 reg_last_set_nonzero_bits
[i
] = 0;
11360 reg_last_set_sign_bit_copies
[i
] = 0;
11361 reg_last_death
[i
] = 0;
11364 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11367 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11370 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11371 register present in the SUBREG, so for each such SUBREG go back and
11372 adjust nonzero and sign bit information of the registers that are
11373 known to have some zero/sign bits set.
11375 This is needed because when combine blows the SUBREGs away, the
11376 information on zero/sign bits is lost and further combines can be
11377 missed because of that. */
11380 record_promoted_value (insn
, subreg
)
11385 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11386 enum machine_mode mode
= GET_MODE (subreg
);
11388 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11391 for (links
= LOG_LINKS (insn
); links
;)
11393 insn
= XEXP (links
, 0);
11394 set
= single_set (insn
);
11396 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11397 || REGNO (SET_DEST (set
)) != regno
11398 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11400 links
= XEXP (links
, 1);
11404 if (reg_last_set
[regno
] == insn
)
11406 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
11407 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11410 if (GET_CODE (SET_SRC (set
)) == REG
)
11412 regno
= REGNO (SET_SRC (set
));
11413 links
= LOG_LINKS (insn
);
11420 /* Scan X for promoted SUBREGs. For each one found,
11421 note what it implies to the registers used in it. */
11424 check_promoted_subreg (insn
, x
)
11428 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11429 && GET_CODE (SUBREG_REG (x
)) == REG
)
11430 record_promoted_value (insn
, x
);
11433 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11436 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11440 check_promoted_subreg (insn
, XEXP (x
, i
));
11444 if (XVEC (x
, i
) != 0)
11445 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11446 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11452 /* Utility routine for the following function. Verify that all the registers
11453 mentioned in *LOC are valid when *LOC was part of a value set when
11454 label_tick == TICK. Return 0 if some are not.
11456 If REPLACE is non-zero, replace the invalid reference with
11457 (clobber (const_int 0)) and return 1. This replacement is useful because
11458 we often can get useful information about the form of a value (e.g., if
11459 it was produced by a shift that always produces -1 or 0) even though
11460 we don't know exactly what registers it was produced from. */
11463 get_last_value_validate (loc
, insn
, tick
, replace
)
11470 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11471 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11474 if (GET_CODE (x
) == REG
)
11476 unsigned int regno
= REGNO (x
);
11477 unsigned int endregno
11478 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11479 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11482 for (j
= regno
; j
< endregno
; j
++)
11483 if (reg_last_set_invalid
[j
]
11484 /* If this is a pseudo-register that was only set once and not
11485 live at the beginning of the function, it is always valid. */
11486 || (! (regno
>= FIRST_PSEUDO_REGISTER
11487 && REG_N_SETS (regno
) == 1
11488 && (! REGNO_REG_SET_P
11489 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))
11490 && reg_last_set_label
[j
] > tick
))
11493 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11499 /* If this is a memory reference, make sure that there were
11500 no stores after it that might have clobbered the value. We don't
11501 have alias info, so we assume any store invalidates it. */
11502 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11503 && INSN_CUID (insn
) <= mem_last_set
)
11506 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11510 for (i
= 0; i
< len
; i
++)
11512 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11513 /* Don't bother with these. They shouldn't occur anyway. */
11517 /* If we haven't found a reason for it to be invalid, it is valid. */
11521 /* Get the last value assigned to X, if known. Some registers
11522 in the value may be replaced with (clobber (const_int 0)) if their value
11523 is known longer known reliably. */
11529 unsigned int regno
;
11532 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11533 then convert it to the desired mode. If this is a paradoxical SUBREG,
11534 we cannot predict what values the "extra" bits might have. */
11535 if (GET_CODE (x
) == SUBREG
11536 && subreg_lowpart_p (x
)
11537 && (GET_MODE_SIZE (GET_MODE (x
))
11538 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11539 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11540 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11542 if (GET_CODE (x
) != REG
)
11546 value
= reg_last_set_value
[regno
];
11548 /* If we don't have a value, or if it isn't for this basic block and
11549 it's either a hard register, set more than once, or it's a live
11550 at the beginning of the function, return 0.
11552 Because if it's not live at the beginnning of the function then the reg
11553 is always set before being used (is never used without being set).
11554 And, if it's set only once, and it's always set before use, then all
11555 uses must have the same last value, even if it's not from this basic
11559 || (reg_last_set_label
[regno
] != label_tick
11560 && (regno
< FIRST_PSEUDO_REGISTER
11561 || REG_N_SETS (regno
) != 1
11562 || (REGNO_REG_SET_P
11563 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))))
11566 /* If the value was set in a later insn than the ones we are processing,
11567 we can't use it even if the register was only set once. */
11568 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11571 /* If the value has all its registers valid, return it. */
11572 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11573 reg_last_set_label
[regno
], 0))
11576 /* Otherwise, make a copy and replace any invalid register with
11577 (clobber (const_int 0)). If that fails for some reason, return 0. */
11579 value
= copy_rtx (value
);
11580 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11581 reg_last_set_label
[regno
], 1))
11587 /* Return nonzero if expression X refers to a REG or to memory
11588 that is set in an instruction more recent than FROM_CUID. */
11591 use_crosses_set_p (x
, from_cuid
)
11595 register const char *fmt
;
11597 register enum rtx_code code
= GET_CODE (x
);
11601 unsigned int regno
= REGNO (x
);
11602 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11603 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11605 #ifdef PUSH_ROUNDING
11606 /* Don't allow uses of the stack pointer to be moved,
11607 because we don't know whether the move crosses a push insn. */
11608 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11611 for (; regno
< endreg
; regno
++)
11612 if (reg_last_set
[regno
]
11613 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11618 if (code
== MEM
&& mem_last_set
> from_cuid
)
11621 fmt
= GET_RTX_FORMAT (code
);
11623 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11628 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11629 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11632 else if (fmt
[i
] == 'e'
11633 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11639 /* Define three variables used for communication between the following
11642 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11643 static int reg_dead_flag
;
11645 /* Function called via note_stores from reg_dead_at_p.
11647 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11648 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11651 reg_dead_at_p_1 (dest
, x
, data
)
11654 void *data ATTRIBUTE_UNUSED
;
11656 unsigned int regno
, endregno
;
11658 if (GET_CODE (dest
) != REG
)
11661 regno
= REGNO (dest
);
11662 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11663 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11665 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11666 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11669 /* Return non-zero if REG is known to be dead at INSN.
11671 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11672 referencing REG, it is dead. If we hit a SET referencing REG, it is
11673 live. Otherwise, see if it is live or dead at the start of the basic
11674 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11675 must be assumed to be always live. */
11678 reg_dead_at_p (reg
, insn
)
11685 /* Set variables for reg_dead_at_p_1. */
11686 reg_dead_regno
= REGNO (reg
);
11687 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11688 ? HARD_REGNO_NREGS (reg_dead_regno
,
11694 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11695 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11697 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11698 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11702 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11703 beginning of function. */
11704 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11705 insn
= prev_nonnote_insn (insn
))
11707 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11709 return reg_dead_flag
== 1 ? 1 : 0;
11711 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11715 /* Get the basic block number that we were in. */
11720 for (block
= 0; block
< n_basic_blocks
; block
++)
11721 if (insn
== BLOCK_HEAD (block
))
11724 if (block
== n_basic_blocks
)
11728 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11729 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11735 /* Note hard registers in X that are used. This code is similar to
11736 that in flow.c, but much simpler since we don't care about pseudos. */
11739 mark_used_regs_combine (x
)
11742 RTX_CODE code
= GET_CODE (x
);
11743 unsigned int regno
;
11755 case ADDR_DIFF_VEC
:
11758 /* CC0 must die in the insn after it is set, so we don't need to take
11759 special note of it here. */
11765 /* If we are clobbering a MEM, mark any hard registers inside the
11766 address as used. */
11767 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11768 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11773 /* A hard reg in a wide mode may really be multiple registers.
11774 If so, mark all of them just like the first. */
11775 if (regno
< FIRST_PSEUDO_REGISTER
)
11777 unsigned int endregno
, r
;
11779 /* None of this applies to the stack, frame or arg pointers */
11780 if (regno
== STACK_POINTER_REGNUM
11781 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11782 || regno
== HARD_FRAME_POINTER_REGNUM
11784 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11785 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11787 || regno
== FRAME_POINTER_REGNUM
)
11790 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11791 for (r
= regno
; r
< endregno
; r
++)
11792 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11798 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11800 register rtx testreg
= SET_DEST (x
);
11802 while (GET_CODE (testreg
) == SUBREG
11803 || GET_CODE (testreg
) == ZERO_EXTRACT
11804 || GET_CODE (testreg
) == SIGN_EXTRACT
11805 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11806 testreg
= XEXP (testreg
, 0);
11808 if (GET_CODE (testreg
) == MEM
)
11809 mark_used_regs_combine (XEXP (testreg
, 0));
11811 mark_used_regs_combine (SET_SRC (x
));
11819 /* Recursively scan the operands of this expression. */
11822 register const char *fmt
= GET_RTX_FORMAT (code
);
11824 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11827 mark_used_regs_combine (XEXP (x
, i
));
11828 else if (fmt
[i
] == 'E')
11832 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11833 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11839 /* Remove register number REGNO from the dead registers list of INSN.
11841 Return the note used to record the death, if there was one. */
11844 remove_death (regno
, insn
)
11845 unsigned int regno
;
11848 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11852 REG_N_DEATHS (regno
)--;
11853 remove_note (insn
, note
);
11859 /* For each register (hardware or pseudo) used within expression X, if its
11860 death is in an instruction with cuid between FROM_CUID (inclusive) and
11861 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11862 list headed by PNOTES.
11864 That said, don't move registers killed by maybe_kill_insn.
11866 This is done when X is being merged by combination into TO_INSN. These
11867 notes will then be distributed as needed. */
11870 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11872 rtx maybe_kill_insn
;
11877 register const char *fmt
;
11878 register int len
, i
;
11879 register enum rtx_code code
= GET_CODE (x
);
11883 unsigned int regno
= REGNO (x
);
11884 register rtx where_dead
= reg_last_death
[regno
];
11885 register rtx before_dead
, after_dead
;
11887 /* Don't move the register if it gets killed in between from and to */
11888 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11889 && ! reg_referenced_p (x
, maybe_kill_insn
))
11892 /* WHERE_DEAD could be a USE insn made by combine, so first we
11893 make sure that we have insns with valid INSN_CUID values. */
11894 before_dead
= where_dead
;
11895 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11896 before_dead
= PREV_INSN (before_dead
);
11898 after_dead
= where_dead
;
11899 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11900 after_dead
= NEXT_INSN (after_dead
);
11902 if (before_dead
&& after_dead
11903 && INSN_CUID (before_dead
) >= from_cuid
11904 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11905 || (where_dead
!= after_dead
11906 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11908 rtx note
= remove_death (regno
, where_dead
);
11910 /* It is possible for the call above to return 0. This can occur
11911 when reg_last_death points to I2 or I1 that we combined with.
11912 In that case make a new note.
11914 We must also check for the case where X is a hard register
11915 and NOTE is a death note for a range of hard registers
11916 including X. In that case, we must put REG_DEAD notes for
11917 the remaining registers in place of NOTE. */
11919 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11920 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11921 > GET_MODE_SIZE (GET_MODE (x
))))
11923 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11924 unsigned int deadend
11925 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11926 GET_MODE (XEXP (note
, 0))));
11927 unsigned int ourend
11928 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11931 for (i
= deadregno
; i
< deadend
; i
++)
11932 if (i
< regno
|| i
>= ourend
)
11933 REG_NOTES (where_dead
)
11934 = gen_rtx_EXPR_LIST (REG_DEAD
,
11935 gen_rtx_REG (reg_raw_mode
[i
], i
),
11936 REG_NOTES (where_dead
));
11939 /* If we didn't find any note, or if we found a REG_DEAD note that
11940 covers only part of the given reg, and we have a multi-reg hard
11941 register, then to be safe we must check for REG_DEAD notes
11942 for each register other than the first. They could have
11943 their own REG_DEAD notes lying around. */
11944 else if ((note
== 0
11946 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11947 < GET_MODE_SIZE (GET_MODE (x
)))))
11948 && regno
< FIRST_PSEUDO_REGISTER
11949 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11951 unsigned int ourend
11952 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11953 unsigned int i
, offset
;
11957 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11961 for (i
= regno
+ offset
; i
< ourend
; i
++)
11962 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11963 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11966 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11968 XEXP (note
, 1) = *pnotes
;
11972 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11974 REG_N_DEATHS (regno
)++;
11980 else if (GET_CODE (x
) == SET
)
11982 rtx dest
= SET_DEST (x
);
11984 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11986 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11987 that accesses one word of a multi-word item, some
11988 piece of everything register in the expression is used by
11989 this insn, so remove any old death. */
11991 if (GET_CODE (dest
) == ZERO_EXTRACT
11992 || GET_CODE (dest
) == STRICT_LOW_PART
11993 || (GET_CODE (dest
) == SUBREG
11994 && (((GET_MODE_SIZE (GET_MODE (dest
))
11995 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11996 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11997 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11999 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12003 /* If this is some other SUBREG, we know it replaces the entire
12004 value, so use that as the destination. */
12005 if (GET_CODE (dest
) == SUBREG
)
12006 dest
= SUBREG_REG (dest
);
12008 /* If this is a MEM, adjust deaths of anything used in the address.
12009 For a REG (the only other possibility), the entire value is
12010 being replaced so the old value is not used in this insn. */
12012 if (GET_CODE (dest
) == MEM
)
12013 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12018 else if (GET_CODE (x
) == CLOBBER
)
12021 len
= GET_RTX_LENGTH (code
);
12022 fmt
= GET_RTX_FORMAT (code
);
12024 for (i
= 0; i
< len
; i
++)
12029 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12030 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12033 else if (fmt
[i
] == 'e')
12034 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12038 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12039 pattern of an insn. X must be a REG. */
12042 reg_bitfield_target_p (x
, body
)
12048 if (GET_CODE (body
) == SET
)
12050 rtx dest
= SET_DEST (body
);
12052 unsigned int regno
, tregno
, endregno
, endtregno
;
12054 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12055 target
= XEXP (dest
, 0);
12056 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12057 target
= SUBREG_REG (XEXP (dest
, 0));
12061 if (GET_CODE (target
) == SUBREG
)
12062 target
= SUBREG_REG (target
);
12064 if (GET_CODE (target
) != REG
)
12067 tregno
= REGNO (target
), regno
= REGNO (x
);
12068 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12069 return target
== x
;
12071 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12072 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12074 return endregno
> tregno
&& regno
< endtregno
;
12077 else if (GET_CODE (body
) == PARALLEL
)
12078 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12079 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12085 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12086 as appropriate. I3 and I2 are the insns resulting from the combination
12087 insns including FROM (I2 may be zero).
12089 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12090 not need REG_DEAD notes because they are being substituted for. This
12091 saves searching in the most common cases.
12093 Each note in the list is either ignored or placed on some insns, depending
12094 on the type of note. */
12097 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
12101 rtx elim_i2
, elim_i1
;
12103 rtx note
, next_note
;
12106 for (note
= notes
; note
; note
= next_note
)
12108 rtx place
= 0, place2
= 0;
12110 /* If this NOTE references a pseudo register, ensure it references
12111 the latest copy of that register. */
12112 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12113 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12114 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12116 next_note
= XEXP (note
, 1);
12117 switch (REG_NOTE_KIND (note
))
12120 case REG_EXEC_COUNT
:
12121 /* Doesn't matter much where we put this, as long as it's somewhere.
12122 It is preferable to keep these notes on branches, which is most
12123 likely to be i3. */
12127 case REG_NON_LOCAL_GOTO
:
12128 if (GET_CODE (i3
) == JUMP_INSN
)
12130 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12136 case REG_EH_REGION
:
12137 case REG_EH_RETHROW
:
12139 /* These notes must remain with the call. It should not be
12140 possible for both I2 and I3 to be a call. */
12141 if (GET_CODE (i3
) == CALL_INSN
)
12143 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12150 /* Any clobbers for i3 may still exist, and so we must process
12151 REG_UNUSED notes from that insn.
12153 Any clobbers from i2 or i1 can only exist if they were added by
12154 recog_for_combine. In that case, recog_for_combine created the
12155 necessary REG_UNUSED notes. Trying to keep any original
12156 REG_UNUSED notes from these insns can cause incorrect output
12157 if it is for the same register as the original i3 dest.
12158 In that case, we will notice that the register is set in i3,
12159 and then add a REG_UNUSED note for the destination of i3, which
12160 is wrong. However, it is possible to have REG_UNUSED notes from
12161 i2 or i1 for register which were both used and clobbered, so
12162 we keep notes from i2 or i1 if they will turn into REG_DEAD
12165 /* If this register is set or clobbered in I3, put the note there
12166 unless there is one already. */
12167 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12169 if (from_insn
!= i3
)
12172 if (! (GET_CODE (XEXP (note
, 0)) == REG
12173 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12174 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12177 /* Otherwise, if this register is used by I3, then this register
12178 now dies here, so we must put a REG_DEAD note here unless there
12180 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12181 && ! (GET_CODE (XEXP (note
, 0)) == REG
12182 ? find_regno_note (i3
, REG_DEAD
,
12183 REGNO (XEXP (note
, 0)))
12184 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12186 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12194 /* These notes say something about results of an insn. We can
12195 only support them if they used to be on I3 in which case they
12196 remain on I3. Otherwise they are ignored.
12198 If the note refers to an expression that is not a constant, we
12199 must also ignore the note since we cannot tell whether the
12200 equivalence is still true. It might be possible to do
12201 slightly better than this (we only have a problem if I2DEST
12202 or I1DEST is present in the expression), but it doesn't
12203 seem worth the trouble. */
12205 if (from_insn
== i3
12206 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12211 case REG_NO_CONFLICT
:
12212 /* These notes say something about how a register is used. They must
12213 be present on any use of the register in I2 or I3. */
12214 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12217 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12227 /* This can show up in several ways -- either directly in the
12228 pattern, or hidden off in the constant pool with (or without?)
12229 a REG_EQUAL note. */
12230 /* ??? Ignore the without-reg_equal-note problem for now. */
12231 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12232 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12233 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12234 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12238 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12239 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12240 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12241 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12252 /* These notes say something about the value of a register prior
12253 to the execution of an insn. It is too much trouble to see
12254 if the note is still correct in all situations. It is better
12255 to simply delete it. */
12259 /* If the insn previously containing this note still exists,
12260 put it back where it was. Otherwise move it to the previous
12261 insn. Adjust the corresponding REG_LIBCALL note. */
12262 if (GET_CODE (from_insn
) != NOTE
)
12266 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12267 place
= prev_real_insn (from_insn
);
12269 XEXP (tem
, 0) = place
;
12270 /* If we're deleting the last remaining instruction of a
12271 libcall sequence, don't add the notes. */
12272 else if (XEXP (note
, 0) == from_insn
)
12278 /* This is handled similarly to REG_RETVAL. */
12279 if (GET_CODE (from_insn
) != NOTE
)
12283 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12284 place
= next_real_insn (from_insn
);
12286 XEXP (tem
, 0) = place
;
12287 /* If we're deleting the last remaining instruction of a
12288 libcall sequence, don't add the notes. */
12289 else if (XEXP (note
, 0) == from_insn
)
12295 /* If the register is used as an input in I3, it dies there.
12296 Similarly for I2, if it is non-zero and adjacent to I3.
12298 If the register is not used as an input in either I3 or I2
12299 and it is not one of the registers we were supposed to eliminate,
12300 there are two possibilities. We might have a non-adjacent I2
12301 or we might have somehow eliminated an additional register
12302 from a computation. For example, we might have had A & B where
12303 we discover that B will always be zero. In this case we will
12304 eliminate the reference to A.
12306 In both cases, we must search to see if we can find a previous
12307 use of A and put the death note there. */
12310 && GET_CODE (from_insn
) == CALL_INSN
12311 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12313 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12315 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12316 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12319 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12320 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12325 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12327 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12329 if (! INSN_P (tem
))
12331 if (tem
== bb
->head
)
12336 /* If the register is being set at TEM, see if that is all
12337 TEM is doing. If so, delete TEM. Otherwise, make this
12338 into a REG_UNUSED note instead. */
12339 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12341 rtx set
= single_set (tem
);
12342 rtx inner_dest
= 0;
12344 rtx cc0_setter
= NULL_RTX
;
12348 for (inner_dest
= SET_DEST (set
);
12349 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12350 || GET_CODE (inner_dest
) == SUBREG
12351 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12352 inner_dest
= XEXP (inner_dest
, 0))
12355 /* Verify that it was the set, and not a clobber that
12356 modified the register.
12358 CC0 targets must be careful to maintain setter/user
12359 pairs. If we cannot delete the setter due to side
12360 effects, mark the user with an UNUSED note instead
12363 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12364 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12366 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12367 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12368 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12372 /* Move the notes and links of TEM elsewhere.
12373 This might delete other dead insns recursively.
12374 First set the pattern to something that won't use
12377 PATTERN (tem
) = pc_rtx
;
12379 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12380 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12381 distribute_links (LOG_LINKS (tem
));
12383 PUT_CODE (tem
, NOTE
);
12384 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12385 NOTE_SOURCE_FILE (tem
) = 0;
12388 /* Delete the setter too. */
12391 PATTERN (cc0_setter
) = pc_rtx
;
12393 distribute_notes (REG_NOTES (cc0_setter
),
12394 cc0_setter
, cc0_setter
,
12395 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12396 distribute_links (LOG_LINKS (cc0_setter
));
12398 PUT_CODE (cc0_setter
, NOTE
);
12399 NOTE_LINE_NUMBER (cc0_setter
)
12400 = NOTE_INSN_DELETED
;
12401 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12405 /* If the register is both set and used here, put the
12406 REG_DEAD note here, but place a REG_UNUSED note
12407 here too unless there already is one. */
12408 else if (reg_referenced_p (XEXP (note
, 0),
12413 if (! find_regno_note (tem
, REG_UNUSED
,
12414 REGNO (XEXP (note
, 0))))
12416 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12421 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12423 /* If there isn't already a REG_UNUSED note, put one
12425 if (! find_regno_note (tem
, REG_UNUSED
,
12426 REGNO (XEXP (note
, 0))))
12431 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12432 || (GET_CODE (tem
) == CALL_INSN
12433 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12437 /* If we are doing a 3->2 combination, and we have a
12438 register which formerly died in i3 and was not used
12439 by i2, which now no longer dies in i3 and is used in
12440 i2 but does not die in i2, and place is between i2
12441 and i3, then we may need to move a link from place to
12443 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12444 && INSN_CUID (place
) > INSN_CUID (i2
)
12446 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12447 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12449 rtx links
= LOG_LINKS (place
);
12450 LOG_LINKS (place
) = 0;
12451 distribute_links (links
);
12456 if (tem
== bb
->head
)
12460 /* We haven't found an insn for the death note and it
12461 is still a REG_DEAD note, but we have hit the beginning
12462 of the block. If the existing life info says the reg
12463 was dead, there's nothing left to do. Otherwise, we'll
12464 need to do a global life update after combine. */
12465 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12466 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12467 REGNO (XEXP (note
, 0))))
12469 SET_BIT (refresh_blocks
, this_basic_block
);
12474 /* If the register is set or already dead at PLACE, we needn't do
12475 anything with this note if it is still a REG_DEAD note.
12476 We can here if it is set at all, not if is it totally replace,
12477 which is what `dead_or_set_p' checks, so also check for it being
12480 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12482 unsigned int regno
= REGNO (XEXP (note
, 0));
12484 if (dead_or_set_p (place
, XEXP (note
, 0))
12485 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12487 /* Unless the register previously died in PLACE, clear
12488 reg_last_death. [I no longer understand why this is
12490 if (reg_last_death
[regno
] != place
)
12491 reg_last_death
[regno
] = 0;
12495 reg_last_death
[regno
] = place
;
12497 /* If this is a death note for a hard reg that is occupying
12498 multiple registers, ensure that we are still using all
12499 parts of the object. If we find a piece of the object
12500 that is unused, we must arrange for an appropriate REG_DEAD
12501 note to be added for it. However, we can't just emit a USE
12502 and tag the note to it, since the register might actually
12503 be dead; so we recourse, and the recursive call then finds
12504 the previous insn that used this register. */
12506 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12507 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12509 unsigned int endregno
12510 = regno
+ HARD_REGNO_NREGS (regno
,
12511 GET_MODE (XEXP (note
, 0)));
12515 for (i
= regno
; i
< endregno
; i
++)
12516 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12517 && ! find_regno_fusage (place
, USE
, i
))
12518 || dead_or_set_regno_p (place
, i
))
12523 /* Put only REG_DEAD notes for pieces that are
12524 not already dead or set. */
12526 for (i
= regno
; i
< endregno
;
12527 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12529 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12530 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12532 if (! dead_or_set_p (place
, piece
)
12533 && ! reg_bitfield_target_p (piece
,
12537 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12539 distribute_notes (new_note
, place
, place
,
12540 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12542 else if (! refers_to_regno_p (i
, i
+ 1,
12543 PATTERN (place
), 0)
12544 && ! find_regno_fusage (place
, USE
, i
))
12545 for (tem
= PREV_INSN (place
); ;
12546 tem
= PREV_INSN (tem
))
12548 if (! INSN_P (tem
))
12550 if (tem
== bb
->head
)
12552 SET_BIT (refresh_blocks
,
12559 if (dead_or_set_p (tem
, piece
)
12560 || reg_bitfield_target_p (piece
,
12564 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12579 /* Any other notes should not be present at this point in the
12586 XEXP (note
, 1) = REG_NOTES (place
);
12587 REG_NOTES (place
) = note
;
12589 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12590 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12591 && GET_CODE (XEXP (note
, 0)) == REG
)
12592 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12596 if ((REG_NOTE_KIND (note
) == REG_DEAD
12597 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12598 && GET_CODE (XEXP (note
, 0)) == REG
)
12599 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12601 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12602 REG_NOTE_KIND (note
),
12604 REG_NOTES (place2
));
12609 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12610 I3, I2, and I1 to new locations. This is also called in one case to
12611 add a link pointing at I3 when I3's destination is changed. */
12614 distribute_links (links
)
12617 rtx link
, next_link
;
12619 for (link
= links
; link
; link
= next_link
)
12625 next_link
= XEXP (link
, 1);
12627 /* If the insn that this link points to is a NOTE or isn't a single
12628 set, ignore it. In the latter case, it isn't clear what we
12629 can do other than ignore the link, since we can't tell which
12630 register it was for. Such links wouldn't be used by combine
12633 It is not possible for the destination of the target of the link to
12634 have been changed by combine. The only potential of this is if we
12635 replace I3, I2, and I1 by I3 and I2. But in that case the
12636 destination of I2 also remains unchanged. */
12638 if (GET_CODE (XEXP (link
, 0)) == NOTE
12639 || (set
= single_set (XEXP (link
, 0))) == 0)
12642 reg
= SET_DEST (set
);
12643 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12644 || GET_CODE (reg
) == SIGN_EXTRACT
12645 || GET_CODE (reg
) == STRICT_LOW_PART
)
12646 reg
= XEXP (reg
, 0);
12648 /* A LOG_LINK is defined as being placed on the first insn that uses
12649 a register and points to the insn that sets the register. Start
12650 searching at the next insn after the target of the link and stop
12651 when we reach a set of the register or the end of the basic block.
12653 Note that this correctly handles the link that used to point from
12654 I3 to I2. Also note that not much searching is typically done here
12655 since most links don't point very far away. */
12657 for (insn
= NEXT_INSN (XEXP (link
, 0));
12658 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12659 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12660 insn
= NEXT_INSN (insn
))
12661 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12663 if (reg_referenced_p (reg
, PATTERN (insn
)))
12667 else if (GET_CODE (insn
) == CALL_INSN
12668 && find_reg_fusage (insn
, USE
, reg
))
12674 /* If we found a place to put the link, place it there unless there
12675 is already a link to the same insn as LINK at that point. */
12681 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12682 if (XEXP (link2
, 0) == XEXP (link
, 0))
12687 XEXP (link
, 1) = LOG_LINKS (place
);
12688 LOG_LINKS (place
) = link
;
12690 /* Set added_links_insn to the earliest insn we added a
12692 if (added_links_insn
== 0
12693 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12694 added_links_insn
= place
;
12700 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12706 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12707 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12708 insn
= NEXT_INSN (insn
);
12710 if (INSN_UID (insn
) > max_uid_cuid
)
12713 return INSN_CUID (insn
);
12717 dump_combine_stats (file
)
12722 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12723 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12727 dump_combine_total_stats (file
)
12732 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12733 total_attempts
, total_merges
, total_extras
, total_successes
);