1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "coretypes.h"
33 #include "insn-config.h"
38 #include "langhooks.h"
40 static void store_fixed_bit_field (rtx
, unsigned HOST_WIDE_INT
,
41 unsigned HOST_WIDE_INT
,
42 unsigned HOST_WIDE_INT
, rtx
);
43 static void store_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
44 unsigned HOST_WIDE_INT
, rtx
);
45 static rtx
extract_fixed_bit_field (enum machine_mode
, rtx
,
46 unsigned HOST_WIDE_INT
,
47 unsigned HOST_WIDE_INT
,
48 unsigned HOST_WIDE_INT
, rtx
, int);
49 static rtx
mask_rtx (enum machine_mode
, int, int, int);
50 static rtx
lshift_value (enum machine_mode
, rtx
, int, int);
51 static rtx
extract_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
, int);
53 static void do_cmp_and_jump (rtx
, rtx
, enum rtx_code
, enum machine_mode
, rtx
);
54 static rtx
expand_smod_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
55 static rtx
expand_sdiv_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
57 /* Nonzero means divides or modulus operations are relatively cheap for
58 powers of two, so don't use branches; emit the operation instead.
59 Usually, this will mean that the MD file will emit non-branch
62 static bool sdiv_pow2_cheap
[NUM_MACHINE_MODES
];
63 static bool smod_pow2_cheap
[NUM_MACHINE_MODES
];
65 #ifndef SLOW_UNALIGNED_ACCESS
66 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
69 /* For compilers that support multiple targets with different word sizes,
70 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
71 is the H8/300(H) compiler. */
73 #ifndef MAX_BITS_PER_WORD
74 #define MAX_BITS_PER_WORD BITS_PER_WORD
77 /* Reduce conditional compilation elsewhere. */
80 #define CODE_FOR_insv CODE_FOR_nothing
81 #define gen_insv(a,b,c,d) NULL_RTX
85 #define CODE_FOR_extv CODE_FOR_nothing
86 #define gen_extv(a,b,c,d) NULL_RTX
90 #define CODE_FOR_extzv CODE_FOR_nothing
91 #define gen_extzv(a,b,c,d) NULL_RTX
94 /* Cost of various pieces of RTL. Note that some of these are indexed by
95 shift count and some by mode. */
97 static int add_cost
[NUM_MACHINE_MODES
];
98 static int neg_cost
[NUM_MACHINE_MODES
];
99 static int shift_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
100 static int shiftadd_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
101 static int shiftsub_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
102 static int mul_cost
[NUM_MACHINE_MODES
];
103 static int div_cost
[NUM_MACHINE_MODES
];
104 static int mul_widen_cost
[NUM_MACHINE_MODES
];
105 static int mul_highpart_cost
[NUM_MACHINE_MODES
];
112 struct rtx_def reg
; rtunion reg_fld
[2];
113 struct rtx_def plus
; rtunion plus_fld1
;
115 struct rtx_def udiv
; rtunion udiv_fld1
;
116 struct rtx_def mult
; rtunion mult_fld1
;
117 struct rtx_def div
; rtunion div_fld1
;
118 struct rtx_def mod
; rtunion mod_fld1
;
120 struct rtx_def wide_mult
; rtunion wide_mult_fld1
;
121 struct rtx_def wide_lshr
; rtunion wide_lshr_fld1
;
122 struct rtx_def wide_trunc
;
123 struct rtx_def shift
; rtunion shift_fld1
;
124 struct rtx_def shift_mult
; rtunion shift_mult_fld1
;
125 struct rtx_def shift_add
; rtunion shift_add_fld1
;
126 struct rtx_def shift_sub
; rtunion shift_sub_fld1
;
129 rtx pow2
[MAX_BITS_PER_WORD
];
130 rtx cint
[MAX_BITS_PER_WORD
];
132 enum machine_mode mode
, wider_mode
;
134 zero_cost
= rtx_cost (const0_rtx
, 0);
136 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
138 pow2
[m
] = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
139 cint
[m
] = GEN_INT (m
);
142 memset (&all
, 0, sizeof all
);
144 PUT_CODE (&all
.reg
, REG
);
145 REGNO (&all
.reg
) = 10000;
147 PUT_CODE (&all
.plus
, PLUS
);
148 XEXP (&all
.plus
, 0) = &all
.reg
;
149 XEXP (&all
.plus
, 1) = &all
.reg
;
151 PUT_CODE (&all
.neg
, NEG
);
152 XEXP (&all
.neg
, 0) = &all
.reg
;
154 PUT_CODE (&all
.udiv
, UDIV
);
155 XEXP (&all
.udiv
, 0) = &all
.reg
;
156 XEXP (&all
.udiv
, 1) = &all
.reg
;
158 PUT_CODE (&all
.mult
, MULT
);
159 XEXP (&all
.mult
, 0) = &all
.reg
;
160 XEXP (&all
.mult
, 1) = &all
.reg
;
162 PUT_CODE (&all
.div
, DIV
);
163 XEXP (&all
.div
, 0) = &all
.reg
;
164 XEXP (&all
.div
, 1) = 32 < MAX_BITS_PER_WORD
? cint
[32] : GEN_INT (32);
166 PUT_CODE (&all
.mod
, MOD
);
167 XEXP (&all
.mod
, 0) = &all
.reg
;
168 XEXP (&all
.mod
, 1) = XEXP (&all
.div
, 1);
170 PUT_CODE (&all
.zext
, ZERO_EXTEND
);
171 XEXP (&all
.zext
, 0) = &all
.reg
;
173 PUT_CODE (&all
.wide_mult
, MULT
);
174 XEXP (&all
.wide_mult
, 0) = &all
.zext
;
175 XEXP (&all
.wide_mult
, 1) = &all
.zext
;
177 PUT_CODE (&all
.wide_lshr
, LSHIFTRT
);
178 XEXP (&all
.wide_lshr
, 0) = &all
.wide_mult
;
180 PUT_CODE (&all
.wide_trunc
, TRUNCATE
);
181 XEXP (&all
.wide_trunc
, 0) = &all
.wide_lshr
;
183 PUT_CODE (&all
.shift
, ASHIFT
);
184 XEXP (&all
.shift
, 0) = &all
.reg
;
186 PUT_CODE (&all
.shift_mult
, MULT
);
187 XEXP (&all
.shift_mult
, 0) = &all
.reg
;
189 PUT_CODE (&all
.shift_add
, PLUS
);
190 XEXP (&all
.shift_add
, 0) = &all
.shift_mult
;
191 XEXP (&all
.shift_add
, 1) = &all
.reg
;
193 PUT_CODE (&all
.shift_sub
, MINUS
);
194 XEXP (&all
.shift_sub
, 0) = &all
.shift_mult
;
195 XEXP (&all
.shift_sub
, 1) = &all
.reg
;
197 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
199 mode
= GET_MODE_WIDER_MODE (mode
))
201 PUT_MODE (&all
.reg
, mode
);
202 PUT_MODE (&all
.plus
, mode
);
203 PUT_MODE (&all
.neg
, mode
);
204 PUT_MODE (&all
.udiv
, mode
);
205 PUT_MODE (&all
.mult
, mode
);
206 PUT_MODE (&all
.div
, mode
);
207 PUT_MODE (&all
.mod
, mode
);
208 PUT_MODE (&all
.wide_trunc
, mode
);
209 PUT_MODE (&all
.shift
, mode
);
210 PUT_MODE (&all
.shift_mult
, mode
);
211 PUT_MODE (&all
.shift_add
, mode
);
212 PUT_MODE (&all
.shift_sub
, mode
);
214 add_cost
[mode
] = rtx_cost (&all
.plus
, SET
);
215 neg_cost
[mode
] = rtx_cost (&all
.neg
, SET
);
216 div_cost
[mode
] = rtx_cost (&all
.udiv
, SET
);
217 mul_cost
[mode
] = rtx_cost (&all
.mult
, SET
);
219 sdiv_pow2_cheap
[mode
] = (rtx_cost (&all
.div
, SET
) <= 2 * add_cost
[mode
]);
220 smod_pow2_cheap
[mode
] = (rtx_cost (&all
.mod
, SET
) <= 4 * add_cost
[mode
]);
222 wider_mode
= GET_MODE_WIDER_MODE (mode
);
223 if (wider_mode
!= VOIDmode
)
225 PUT_MODE (&all
.zext
, wider_mode
);
226 PUT_MODE (&all
.wide_mult
, wider_mode
);
227 PUT_MODE (&all
.wide_lshr
, wider_mode
);
228 XEXP (&all
.wide_lshr
, 1) = GEN_INT (GET_MODE_BITSIZE (mode
));
230 mul_widen_cost
[wider_mode
] = rtx_cost (&all
.wide_mult
, SET
);
231 mul_highpart_cost
[mode
] = rtx_cost (&all
.wide_trunc
, SET
);
234 shift_cost
[mode
][0] = 0;
235 shiftadd_cost
[mode
][0] = shiftsub_cost
[mode
][0] = add_cost
[mode
];
237 n
= MIN (MAX_BITS_PER_WORD
, GET_MODE_BITSIZE (mode
));
238 for (m
= 1; m
< n
; m
++)
240 XEXP (&all
.shift
, 1) = cint
[m
];
241 XEXP (&all
.shift_mult
, 1) = pow2
[m
];
243 shift_cost
[mode
][m
] = rtx_cost (&all
.shift
, SET
);
244 shiftadd_cost
[mode
][m
] = rtx_cost (&all
.shift_add
, SET
);
245 shiftsub_cost
[mode
][m
] = rtx_cost (&all
.shift_sub
, SET
);
250 /* Return an rtx representing minus the value of X.
251 MODE is the intended mode of the result,
252 useful if X is a CONST_INT. */
255 negate_rtx (enum machine_mode mode
, rtx x
)
257 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
260 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
265 /* Report on the availability of insv/extv/extzv and the desired mode
266 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
267 is false; else the mode of the specified operand. If OPNO is -1,
268 all the caller cares about is whether the insn is available. */
270 mode_for_extraction (enum extraction_pattern pattern
, int opno
)
272 const struct insn_data
*data
;
279 data
= &insn_data
[CODE_FOR_insv
];
282 return MAX_MACHINE_MODE
;
287 data
= &insn_data
[CODE_FOR_extv
];
290 return MAX_MACHINE_MODE
;
295 data
= &insn_data
[CODE_FOR_extzv
];
298 return MAX_MACHINE_MODE
;
307 /* Everyone who uses this function used to follow it with
308 if (result == VOIDmode) result = word_mode; */
309 if (data
->operand
[opno
].mode
== VOIDmode
)
311 return data
->operand
[opno
].mode
;
315 /* Generate code to store value from rtx VALUE
316 into a bit-field within structure STR_RTX
317 containing BITSIZE bits starting at bit BITNUM.
318 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
319 ALIGN is the alignment that STR_RTX is known to have.
320 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
322 /* ??? Note that there are two different ideas here for how
323 to determine the size to count bits within, for a register.
324 One is BITS_PER_WORD, and the other is the size of operand 3
327 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
328 else, we use the mode of operand 3. */
331 store_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
332 unsigned HOST_WIDE_INT bitnum
, enum machine_mode fieldmode
,
336 = (MEM_P (str_rtx
)) ? BITS_PER_UNIT
: BITS_PER_WORD
;
337 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
338 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
342 enum machine_mode op_mode
= mode_for_extraction (EP_insv
, 3);
344 while (GET_CODE (op0
) == SUBREG
)
346 /* The following line once was done only if WORDS_BIG_ENDIAN,
347 but I think that is a mistake. WORDS_BIG_ENDIAN is
348 meaningful at a much higher level; when structures are copied
349 between memory and regs, the higher-numbered regs
350 always get higher addresses. */
351 offset
+= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
);
352 /* We used to adjust BITPOS here, but now we do the whole adjustment
353 right after the loop. */
354 op0
= SUBREG_REG (op0
);
357 /* Use vec_set patterns for inserting parts of vectors whenever
359 if (VECTOR_MODE_P (GET_MODE (op0
))
361 && (vec_set_optab
->handlers
[GET_MODE (op0
)].insn_code
363 && fieldmode
== GET_MODE_INNER (GET_MODE (op0
))
364 && bitsize
== GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
365 && !(bitnum
% GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
367 enum machine_mode outermode
= GET_MODE (op0
);
368 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
369 int icode
= (int) vec_set_optab
->handlers
[outermode
].insn_code
;
370 int pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
371 rtx rtxpos
= GEN_INT (pos
);
375 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
376 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
377 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
381 if (! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
))
382 src
= copy_to_mode_reg (mode1
, src
);
384 if (! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
385 rtxpos
= copy_to_mode_reg (mode1
, rtxpos
);
387 /* We could handle this, but we should always be called with a pseudo
388 for our targets and all insns should take them as outputs. */
389 if (! (*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
)
390 || ! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
)
391 || ! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
393 pat
= GEN_FCN (icode
) (dest
, src
, rtxpos
);
406 int old_generating_concat_p
= generating_concat_p
;
407 generating_concat_p
= 0;
408 value
= force_not_mem (value
);
409 generating_concat_p
= old_generating_concat_p
;
412 /* If the target is a register, overwriting the entire object, or storing
413 a full-word or multi-word field can be done with just a SUBREG.
415 If the target is memory, storing any naturally aligned field can be
416 done with a simple store. For targets that support fast unaligned
417 memory, any naturally sized, unit aligned field can be done directly. */
419 byte_offset
= (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
420 + (offset
* UNITS_PER_WORD
);
423 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
425 ? ((GET_MODE_SIZE (fieldmode
) >= UNITS_PER_WORD
426 || GET_MODE_SIZE (GET_MODE (op0
)) == GET_MODE_SIZE (fieldmode
))
427 && byte_offset
% GET_MODE_SIZE (fieldmode
) == 0)
428 : (! SLOW_UNALIGNED_ACCESS (fieldmode
, MEM_ALIGN (op0
))
429 || (offset
* BITS_PER_UNIT
% bitsize
== 0
430 && MEM_ALIGN (op0
) % GET_MODE_BITSIZE (fieldmode
) == 0))))
432 if (GET_MODE (op0
) != fieldmode
)
434 if (GET_CODE (op0
) == SUBREG
)
436 if (GET_MODE (SUBREG_REG (op0
)) == fieldmode
437 || GET_MODE_CLASS (fieldmode
) == MODE_INT
438 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
)
439 op0
= SUBREG_REG (op0
);
441 /* Else we've got some float mode source being extracted into
442 a different float mode destination -- this combination of
443 subregs results in Severe Tire Damage. */
447 op0
= gen_rtx_SUBREG (fieldmode
, op0
, byte_offset
);
449 op0
= adjust_address (op0
, fieldmode
, offset
);
451 emit_move_insn (op0
, value
);
455 /* Make sure we are playing with integral modes. Pun with subregs
456 if we aren't. This must come after the entire register case above,
457 since that case is valid for any mode. The following cases are only
458 valid for integral modes. */
460 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
461 if (imode
!= GET_MODE (op0
))
464 op0
= adjust_address (op0
, imode
, 0);
465 else if (imode
!= BLKmode
)
466 op0
= gen_lowpart (imode
, op0
);
472 /* We may be accessing data outside the field, which means
473 we can alias adjacent data. */
476 op0
= shallow_copy_rtx (op0
);
477 set_mem_alias_set (op0
, 0);
478 set_mem_expr (op0
, 0);
481 /* If OP0 is a register, BITPOS must count within a word.
482 But as we have it, it counts within whatever size OP0 now has.
483 On a bigendian machine, these are not the same, so convert. */
486 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
487 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
489 /* Storing an lsb-aligned field in a register
490 can be done with a movestrict instruction. */
493 && (BYTES_BIG_ENDIAN
? bitpos
+ bitsize
== unit
: bitpos
== 0)
494 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
495 && (movstrict_optab
->handlers
[fieldmode
].insn_code
496 != CODE_FOR_nothing
))
498 int icode
= movstrict_optab
->handlers
[fieldmode
].insn_code
;
500 /* Get appropriate low part of the value being stored. */
501 if (GET_CODE (value
) == CONST_INT
|| REG_P (value
))
502 value
= gen_lowpart (fieldmode
, value
);
503 else if (!(GET_CODE (value
) == SYMBOL_REF
504 || GET_CODE (value
) == LABEL_REF
505 || GET_CODE (value
) == CONST
))
506 value
= convert_to_mode (fieldmode
, value
, 0);
508 if (! (*insn_data
[icode
].operand
[1].predicate
) (value
, fieldmode
))
509 value
= copy_to_mode_reg (fieldmode
, value
);
511 if (GET_CODE (op0
) == SUBREG
)
513 if (GET_MODE (SUBREG_REG (op0
)) == fieldmode
514 || GET_MODE_CLASS (fieldmode
) == MODE_INT
515 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
)
516 op0
= SUBREG_REG (op0
);
518 /* Else we've got some float mode source being extracted into
519 a different float mode destination -- this combination of
520 subregs results in Severe Tire Damage. */
524 emit_insn (GEN_FCN (icode
)
525 (gen_rtx_SUBREG (fieldmode
, op0
,
526 (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
527 + (offset
* UNITS_PER_WORD
)),
533 /* Handle fields bigger than a word. */
535 if (bitsize
> BITS_PER_WORD
)
537 /* Here we transfer the words of the field
538 in the order least significant first.
539 This is because the most significant word is the one which may
541 However, only do that if the value is not BLKmode. */
543 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
544 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
547 /* This is the mode we must force value to, so that there will be enough
548 subwords to extract. Note that fieldmode will often (always?) be
549 VOIDmode, because that is what store_field uses to indicate that this
550 is a bit field, but passing VOIDmode to operand_subword_force will
551 result in an abort. */
552 fieldmode
= GET_MODE (value
);
553 if (fieldmode
== VOIDmode
)
554 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
556 for (i
= 0; i
< nwords
; i
++)
558 /* If I is 0, use the low-order word in both field and target;
559 if I is 1, use the next to lowest word; and so on. */
560 unsigned int wordnum
= (backwards
? nwords
- i
- 1 : i
);
561 unsigned int bit_offset
= (backwards
562 ? MAX ((int) bitsize
- ((int) i
+ 1)
565 : (int) i
* BITS_PER_WORD
);
567 store_bit_field (op0
, MIN (BITS_PER_WORD
,
568 bitsize
- i
* BITS_PER_WORD
),
569 bitnum
+ bit_offset
, word_mode
,
570 operand_subword_force (value
, wordnum
, fieldmode
));
575 /* From here on we can assume that the field to be stored in is
576 a full-word (whatever type that is), since it is shorter than a word. */
578 /* OFFSET is the number of words or bytes (UNIT says which)
579 from STR_RTX to the first word or byte containing part of the field. */
584 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
588 /* Since this is a destination (lvalue), we can't copy it to a
589 pseudo. We can trivially remove a SUBREG that does not
590 change the size of the operand. Such a SUBREG may have been
591 added above. Otherwise, abort. */
592 if (GET_CODE (op0
) == SUBREG
593 && (GET_MODE_SIZE (GET_MODE (op0
))
594 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)))))
595 op0
= SUBREG_REG (op0
);
599 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
600 op0
, (offset
* UNITS_PER_WORD
));
605 /* If VALUE is a floating-point mode, access it as an integer of the
606 corresponding size. This can occur on a machine with 64 bit registers
607 that uses SFmode for float. This can also occur for unaligned float
609 if (GET_MODE_CLASS (GET_MODE (value
)) != MODE_INT
610 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_PARTIAL_INT
)
611 value
= gen_lowpart ((GET_MODE (value
) == VOIDmode
612 ? word_mode
: int_mode_for_mode (GET_MODE (value
))),
615 /* Now OFFSET is nonzero only if OP0 is memory
616 and is therefore always measured in bytes. */
619 && GET_MODE (value
) != BLKmode
620 && !(bitsize
== 1 && GET_CODE (value
) == CONST_INT
)
621 /* Ensure insv's size is wide enough for this field. */
622 && (GET_MODE_BITSIZE (op_mode
) >= bitsize
)
623 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
624 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (op_mode
))))
626 int xbitpos
= bitpos
;
629 rtx last
= get_last_insn ();
631 enum machine_mode maxmode
= mode_for_extraction (EP_insv
, 3);
632 int save_volatile_ok
= volatile_ok
;
636 /* If this machine's insv can only insert into a register, copy OP0
637 into a register and save it back later. */
638 /* This used to check flag_force_mem, but that was a serious
639 de-optimization now that flag_force_mem is enabled by -O2. */
641 && ! ((*insn_data
[(int) CODE_FOR_insv
].operand
[0].predicate
)
645 enum machine_mode bestmode
;
647 /* Get the mode to use for inserting into this field. If OP0 is
648 BLKmode, get the smallest mode consistent with the alignment. If
649 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
650 mode. Otherwise, use the smallest mode containing the field. */
652 if (GET_MODE (op0
) == BLKmode
653 || GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (maxmode
))
655 = get_best_mode (bitsize
, bitnum
, MEM_ALIGN (op0
), maxmode
,
656 MEM_VOLATILE_P (op0
));
658 bestmode
= GET_MODE (op0
);
660 if (bestmode
== VOIDmode
661 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (op0
))
662 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (op0
)))
665 /* Adjust address to point to the containing unit of that mode.
666 Compute offset as multiple of this unit, counting in bytes. */
667 unit
= GET_MODE_BITSIZE (bestmode
);
668 offset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
669 bitpos
= bitnum
% unit
;
670 op0
= adjust_address (op0
, bestmode
, offset
);
672 /* Fetch that unit, store the bitfield in it, then store
674 tempreg
= copy_to_reg (op0
);
675 store_bit_field (tempreg
, bitsize
, bitpos
, fieldmode
, value
);
676 emit_move_insn (op0
, tempreg
);
679 volatile_ok
= save_volatile_ok
;
681 /* Add OFFSET into OP0's address. */
683 xop0
= adjust_address (xop0
, byte_mode
, offset
);
685 /* If xop0 is a register, we need it in MAXMODE
686 to make it acceptable to the format of insv. */
687 if (GET_CODE (xop0
) == SUBREG
)
688 /* We can't just change the mode, because this might clobber op0,
689 and we will need the original value of op0 if insv fails. */
690 xop0
= gen_rtx_SUBREG (maxmode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
691 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
692 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
694 /* On big-endian machines, we count bits from the most significant.
695 If the bit field insn does not, we must invert. */
697 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
698 xbitpos
= unit
- bitsize
- xbitpos
;
700 /* We have been counting XBITPOS within UNIT.
701 Count instead within the size of the register. */
702 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
703 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
705 unit
= GET_MODE_BITSIZE (maxmode
);
707 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
709 if (GET_MODE (value
) != maxmode
)
711 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
713 /* Optimization: Don't bother really extending VALUE
714 if it has all the bits we will actually use. However,
715 if we must narrow it, be sure we do it correctly. */
717 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (maxmode
))
721 tmp
= simplify_subreg (maxmode
, value1
, GET_MODE (value
), 0);
723 tmp
= simplify_gen_subreg (maxmode
,
724 force_reg (GET_MODE (value
),
726 GET_MODE (value
), 0);
730 value1
= gen_lowpart (maxmode
, value1
);
732 else if (GET_CODE (value
) == CONST_INT
)
733 value1
= gen_int_mode (INTVAL (value
), maxmode
);
734 else if (!CONSTANT_P (value
))
735 /* Parse phase is supposed to make VALUE's data type
736 match that of the component reference, which is a type
737 at least as wide as the field; so VALUE should have
738 a mode that corresponds to that type. */
742 /* If this machine's insv insists on a register,
743 get VALUE1 into a register. */
744 if (! ((*insn_data
[(int) CODE_FOR_insv
].operand
[3].predicate
)
746 value1
= force_reg (maxmode
, value1
);
748 pat
= gen_insv (xop0
, GEN_INT (bitsize
), GEN_INT (xbitpos
), value1
);
753 delete_insns_since (last
);
754 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
759 /* Insv is not available; store using shifts and boolean ops. */
760 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
764 /* Use shifts and boolean operations to store VALUE
765 into a bit field of width BITSIZE
766 in a memory location specified by OP0 except offset by OFFSET bytes.
767 (OFFSET must be 0 if OP0 is a register.)
768 The field starts at position BITPOS within the byte.
769 (If OP0 is a register, it may be a full word or a narrower mode,
770 but BITPOS still counts within a full word,
771 which is significant on bigendian machines.) */
774 store_fixed_bit_field (rtx op0
, unsigned HOST_WIDE_INT offset
,
775 unsigned HOST_WIDE_INT bitsize
,
776 unsigned HOST_WIDE_INT bitpos
, rtx value
)
778 enum machine_mode mode
;
779 unsigned int total_bits
= BITS_PER_WORD
;
784 /* There is a case not handled here:
785 a structure with a known alignment of just a halfword
786 and a field split across two aligned halfwords within the structure.
787 Or likewise a structure with a known alignment of just a byte
788 and a field split across two bytes.
789 Such cases are not supposed to be able to occur. */
791 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
795 /* Special treatment for a bit field split across two registers. */
796 if (bitsize
+ bitpos
> BITS_PER_WORD
)
798 store_split_bit_field (op0
, bitsize
, bitpos
, value
);
804 /* Get the proper mode to use for this field. We want a mode that
805 includes the entire field. If such a mode would be larger than
806 a word, we won't be doing the extraction the normal way.
807 We don't want a mode bigger than the destination. */
809 mode
= GET_MODE (op0
);
810 if (GET_MODE_BITSIZE (mode
) == 0
811 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
813 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
814 MEM_ALIGN (op0
), mode
, MEM_VOLATILE_P (op0
));
816 if (mode
== VOIDmode
)
818 /* The only way this should occur is if the field spans word
820 store_split_bit_field (op0
, bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
825 total_bits
= GET_MODE_BITSIZE (mode
);
827 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
828 be in the range 0 to total_bits-1, and put any excess bytes in
830 if (bitpos
>= total_bits
)
832 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
833 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
837 /* Get ref to an aligned byte, halfword, or word containing the field.
838 Adjust BITPOS to be position within a word,
839 and OFFSET to be the offset of that word.
840 Then alter OP0 to refer to that word. */
841 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
842 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
843 op0
= adjust_address (op0
, mode
, offset
);
846 mode
= GET_MODE (op0
);
848 /* Now MODE is either some integral mode for a MEM as OP0,
849 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
850 The bit field is contained entirely within OP0.
851 BITPOS is the starting bit number within OP0.
852 (OP0's mode may actually be narrower than MODE.) */
854 if (BYTES_BIG_ENDIAN
)
855 /* BITPOS is the distance between our msb
856 and that of the containing datum.
857 Convert it to the distance from the lsb. */
858 bitpos
= total_bits
- bitsize
- bitpos
;
860 /* Now BITPOS is always the distance between our lsb
863 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
864 we must first convert its mode to MODE. */
866 if (GET_CODE (value
) == CONST_INT
)
868 HOST_WIDE_INT v
= INTVAL (value
);
870 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
871 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
875 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
876 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
877 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
880 value
= lshift_value (mode
, value
, bitpos
, bitsize
);
884 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
885 && bitpos
+ bitsize
!= GET_MODE_BITSIZE (mode
));
887 if (GET_MODE (value
) != mode
)
889 if ((REG_P (value
) || GET_CODE (value
) == SUBREG
)
890 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (value
)))
891 value
= gen_lowpart (mode
, value
);
893 value
= convert_to_mode (mode
, value
, 1);
897 value
= expand_binop (mode
, and_optab
, value
,
898 mask_rtx (mode
, 0, bitsize
, 0),
899 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
901 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
902 build_int_cst (NULL_TREE
,
903 bitpos
, 0), NULL_RTX
, 1);
906 /* Now clear the chosen bits in OP0,
907 except that if VALUE is -1 we need not bother. */
909 subtarget
= (REG_P (op0
) || ! flag_force_mem
) ? op0
: 0;
913 temp
= expand_binop (mode
, and_optab
, op0
,
914 mask_rtx (mode
, bitpos
, bitsize
, 1),
915 subtarget
, 1, OPTAB_LIB_WIDEN
);
921 /* Now logical-or VALUE into OP0, unless it is zero. */
924 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
925 subtarget
, 1, OPTAB_LIB_WIDEN
);
927 emit_move_insn (op0
, temp
);
930 /* Store a bit field that is split across multiple accessible memory objects.
932 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
933 BITSIZE is the field width; BITPOS the position of its first bit
935 VALUE is the value to store.
937 This does not yet handle fields wider than BITS_PER_WORD. */
940 store_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
941 unsigned HOST_WIDE_INT bitpos
, rtx value
)
944 unsigned int bitsdone
= 0;
946 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
948 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
949 unit
= BITS_PER_WORD
;
951 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
953 /* If VALUE is a constant other than a CONST_INT, get it into a register in
954 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
955 that VALUE might be a floating-point constant. */
956 if (CONSTANT_P (value
) && GET_CODE (value
) != CONST_INT
)
958 rtx word
= gen_lowpart_common (word_mode
, value
);
960 if (word
&& (value
!= word
))
963 value
= gen_lowpart_common (word_mode
,
964 force_reg (GET_MODE (value
) != VOIDmode
966 : word_mode
, value
));
969 while (bitsdone
< bitsize
)
971 unsigned HOST_WIDE_INT thissize
;
973 unsigned HOST_WIDE_INT thispos
;
974 unsigned HOST_WIDE_INT offset
;
976 offset
= (bitpos
+ bitsdone
) / unit
;
977 thispos
= (bitpos
+ bitsdone
) % unit
;
979 /* THISSIZE must not overrun a word boundary. Otherwise,
980 store_fixed_bit_field will call us again, and we will mutually
982 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
983 thissize
= MIN (thissize
, unit
- thispos
);
985 if (BYTES_BIG_ENDIAN
)
989 /* We must do an endian conversion exactly the same way as it is
990 done in extract_bit_field, so that the two calls to
991 extract_fixed_bit_field will have comparable arguments. */
992 if (!MEM_P (value
) || GET_MODE (value
) == BLKmode
)
993 total_bits
= BITS_PER_WORD
;
995 total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
997 /* Fetch successively less significant portions. */
998 if (GET_CODE (value
) == CONST_INT
)
999 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1000 >> (bitsize
- bitsdone
- thissize
))
1001 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1003 /* The args are chosen so that the last part includes the
1004 lsb. Give extract_bit_field the value it needs (with
1005 endianness compensation) to fetch the piece we want. */
1006 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
1007 total_bits
- bitsize
+ bitsdone
,
1012 /* Fetch successively more significant portions. */
1013 if (GET_CODE (value
) == CONST_INT
)
1014 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1016 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1018 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
1019 bitsdone
, NULL_RTX
, 1);
1022 /* If OP0 is a register, then handle OFFSET here.
1024 When handling multiword bitfields, extract_bit_field may pass
1025 down a word_mode SUBREG of a larger REG for a bitfield that actually
1026 crosses a word boundary. Thus, for a SUBREG, we must find
1027 the current word starting from the base register. */
1028 if (GET_CODE (op0
) == SUBREG
)
1030 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1031 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1032 GET_MODE (SUBREG_REG (op0
)));
1035 else if (REG_P (op0
))
1037 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1043 /* OFFSET is in UNITs, and UNIT is in bits.
1044 store_fixed_bit_field wants offset in bytes. */
1045 store_fixed_bit_field (word
, offset
* unit
/ BITS_PER_UNIT
, thissize
,
1047 bitsdone
+= thissize
;
1051 /* Generate code to extract a byte-field from STR_RTX
1052 containing BITSIZE bits, starting at BITNUM,
1053 and put it in TARGET if possible (if TARGET is nonzero).
1054 Regardless of TARGET, we return the rtx for where the value is placed.
1056 STR_RTX is the structure containing the byte (a REG or MEM).
1057 UNSIGNEDP is nonzero if this is an unsigned bit field.
1058 MODE is the natural mode of the field value once extracted.
1059 TMODE is the mode the caller would like the value to have;
1060 but the value may be returned with type MODE instead.
1062 TOTAL_SIZE is the size in bytes of the containing structure,
1065 If a TARGET is specified and we can store in it at no extra cost,
1066 we do so, and return TARGET.
1067 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1068 if they are equally easy. */
1071 extract_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1072 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1073 enum machine_mode mode
, enum machine_mode tmode
)
1076 = (MEM_P (str_rtx
)) ? BITS_PER_UNIT
: BITS_PER_WORD
;
1077 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
1078 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
1080 rtx spec_target
= target
;
1081 rtx spec_target_subreg
= 0;
1082 enum machine_mode int_mode
;
1083 enum machine_mode extv_mode
= mode_for_extraction (EP_extv
, 0);
1084 enum machine_mode extzv_mode
= mode_for_extraction (EP_extzv
, 0);
1085 enum machine_mode mode1
;
1088 if (tmode
== VOIDmode
)
1091 while (GET_CODE (op0
) == SUBREG
)
1093 bitpos
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
1096 offset
+= (bitpos
/ unit
);
1099 op0
= SUBREG_REG (op0
);
1103 && mode
== GET_MODE (op0
)
1105 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1107 /* We're trying to extract a full register from itself. */
1111 /* Use vec_extract patterns for extracting parts of vectors whenever
1113 if (VECTOR_MODE_P (GET_MODE (op0
))
1115 && (vec_extract_optab
->handlers
[GET_MODE (op0
)].insn_code
1116 != CODE_FOR_nothing
)
1117 && ((bitnum
+ bitsize
- 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
1118 == bitnum
/ GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
1120 enum machine_mode outermode
= GET_MODE (op0
);
1121 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
1122 int icode
= (int) vec_extract_optab
->handlers
[outermode
].insn_code
;
1123 unsigned HOST_WIDE_INT pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
1124 rtx rtxpos
= GEN_INT (pos
);
1126 rtx dest
= NULL
, pat
, seq
;
1127 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
1128 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
1129 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
1131 if (innermode
== tmode
|| innermode
== mode
)
1135 dest
= gen_reg_rtx (innermode
);
1139 if (! (*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
))
1140 dest
= copy_to_mode_reg (mode0
, dest
);
1142 if (! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
))
1143 src
= copy_to_mode_reg (mode1
, src
);
1145 if (! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
1146 rtxpos
= copy_to_mode_reg (mode1
, rtxpos
);
1148 /* We could handle this, but we should always be called with a pseudo
1149 for our targets and all insns should take them as outputs. */
1150 if (! (*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
)
1151 || ! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
)
1152 || ! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
1155 pat
= GEN_FCN (icode
) (dest
, src
, rtxpos
);
1166 /* Make sure we are playing with integral modes. Pun with subregs
1169 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1170 if (imode
!= GET_MODE (op0
))
1173 op0
= adjust_address (op0
, imode
, 0);
1174 else if (imode
!= BLKmode
)
1175 op0
= gen_lowpart (imode
, op0
);
1181 /* We may be accessing data outside the field, which means
1182 we can alias adjacent data. */
1185 op0
= shallow_copy_rtx (op0
);
1186 set_mem_alias_set (op0
, 0);
1187 set_mem_expr (op0
, 0);
1190 /* Extraction of a full-word or multi-word value from a structure
1191 in a register or aligned memory can be done with just a SUBREG.
1192 A subword value in the least significant part of a register
1193 can also be extracted with a SUBREG. For this, we need the
1194 byte offset of the value in op0. */
1196 byte_offset
= bitpos
/ BITS_PER_UNIT
+ offset
* UNITS_PER_WORD
;
1198 /* If OP0 is a register, BITPOS must count within a word.
1199 But as we have it, it counts within whatever size OP0 now has.
1200 On a bigendian machine, these are not the same, so convert. */
1201 if (BYTES_BIG_ENDIAN
1203 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
1204 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1206 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1207 If that's wrong, the solution is to test for it and set TARGET to 0
1210 /* Only scalar integer modes can be converted via subregs. There is an
1211 additional problem for FP modes here in that they can have a precision
1212 which is different from the size. mode_for_size uses precision, but
1213 we want a mode based on the size, so we must avoid calling it for FP
1215 mode1
= (SCALAR_INT_MODE_P (tmode
)
1216 ? mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0)
1219 if (((bitsize
>= BITS_PER_WORD
&& bitsize
== GET_MODE_BITSIZE (mode
)
1220 && bitpos
% BITS_PER_WORD
== 0)
1221 || (mode1
!= BLKmode
1222 /* ??? The big endian test here is wrong. This is correct
1223 if the value is in a register, and if mode_for_size is not
1224 the same mode as op0. This causes us to get unnecessarily
1225 inefficient code from the Thumb port when -mbig-endian. */
1226 && (BYTES_BIG_ENDIAN
1227 ? bitpos
+ bitsize
== BITS_PER_WORD
1230 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1231 GET_MODE_BITSIZE (GET_MODE (op0
)))
1232 && GET_MODE_SIZE (mode1
) != 0
1233 && byte_offset
% GET_MODE_SIZE (mode1
) == 0)
1235 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (op0
))
1236 || (offset
* BITS_PER_UNIT
% bitsize
== 0
1237 && MEM_ALIGN (op0
) % bitsize
== 0)))))
1239 if (mode1
!= GET_MODE (op0
))
1241 if (GET_CODE (op0
) == SUBREG
)
1243 if (GET_MODE (SUBREG_REG (op0
)) == mode1
1244 || GET_MODE_CLASS (mode1
) == MODE_INT
1245 || GET_MODE_CLASS (mode1
) == MODE_PARTIAL_INT
)
1246 op0
= SUBREG_REG (op0
);
1248 /* Else we've got some float mode source being extracted into
1249 a different float mode destination -- this combination of
1250 subregs results in Severe Tire Damage. */
1251 goto no_subreg_mode_swap
;
1254 op0
= gen_rtx_SUBREG (mode1
, op0
, byte_offset
);
1256 op0
= adjust_address (op0
, mode1
, offset
);
1259 return convert_to_mode (tmode
, op0
, unsignedp
);
1262 no_subreg_mode_swap
:
1264 /* Handle fields bigger than a word. */
1266 if (bitsize
> BITS_PER_WORD
)
1268 /* Here we transfer the words of the field
1269 in the order least significant first.
1270 This is because the most significant word is the one which may
1271 be less than full. */
1273 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1276 if (target
== 0 || !REG_P (target
))
1277 target
= gen_reg_rtx (mode
);
1279 /* Indicate for flow that the entire target reg is being set. */
1280 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
1282 for (i
= 0; i
< nwords
; i
++)
1284 /* If I is 0, use the low-order word in both field and target;
1285 if I is 1, use the next to lowest word; and so on. */
1286 /* Word number in TARGET to use. */
1287 unsigned int wordnum
1289 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1291 /* Offset from start of field in OP0. */
1292 unsigned int bit_offset
= (WORDS_BIG_ENDIAN
1293 ? MAX (0, ((int) bitsize
- ((int) i
+ 1)
1294 * (int) BITS_PER_WORD
))
1295 : (int) i
* BITS_PER_WORD
);
1296 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1298 = extract_bit_field (op0
, MIN (BITS_PER_WORD
,
1299 bitsize
- i
* BITS_PER_WORD
),
1300 bitnum
+ bit_offset
, 1, target_part
, mode
,
1303 if (target_part
== 0)
1306 if (result_part
!= target_part
)
1307 emit_move_insn (target_part
, result_part
);
1312 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1313 need to be zero'd out. */
1314 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1316 unsigned int i
, total_words
;
1318 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1319 for (i
= nwords
; i
< total_words
; i
++)
1321 (operand_subword (target
,
1322 WORDS_BIG_ENDIAN
? total_words
- i
- 1 : i
,
1329 /* Signed bit field: sign-extend with two arithmetic shifts. */
1330 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1331 build_int_cst (NULL_TREE
,
1332 GET_MODE_BITSIZE (mode
) - bitsize
,
1335 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1336 build_int_cst (NULL_TREE
,
1337 GET_MODE_BITSIZE (mode
) - bitsize
,
1342 /* From here on we know the desired field is smaller than a word. */
1344 /* Check if there is a correspondingly-sized integer field, so we can
1345 safely extract it as one size of integer, if necessary; then
1346 truncate or extend to the size that is wanted; then use SUBREGs or
1347 convert_to_mode to get one of the modes we really wanted. */
1349 int_mode
= int_mode_for_mode (tmode
);
1350 if (int_mode
== BLKmode
)
1351 int_mode
= int_mode_for_mode (mode
);
1352 if (int_mode
== BLKmode
)
1353 abort (); /* Should probably push op0 out to memory and then
1356 /* OFFSET is the number of words or bytes (UNIT says which)
1357 from STR_RTX to the first word or byte containing part of the field. */
1362 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1365 op0
= copy_to_reg (op0
);
1366 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
1367 op0
, (offset
* UNITS_PER_WORD
));
1372 /* Now OFFSET is nonzero only for memory operands. */
1377 && (GET_MODE_BITSIZE (extzv_mode
) >= bitsize
)
1378 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1379 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extzv_mode
))))
1381 unsigned HOST_WIDE_INT xbitpos
= bitpos
, xoffset
= offset
;
1382 rtx bitsize_rtx
, bitpos_rtx
;
1383 rtx last
= get_last_insn ();
1385 rtx xtarget
= target
;
1386 rtx xspec_target
= spec_target
;
1387 rtx xspec_target_subreg
= spec_target_subreg
;
1389 enum machine_mode maxmode
= mode_for_extraction (EP_extzv
, 0);
1393 int save_volatile_ok
= volatile_ok
;
1396 /* Is the memory operand acceptable? */
1397 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[1].predicate
)
1398 (xop0
, GET_MODE (xop0
))))
1400 /* No, load into a reg and extract from there. */
1401 enum machine_mode bestmode
;
1403 /* Get the mode to use for inserting into this field. If
1404 OP0 is BLKmode, get the smallest mode consistent with the
1405 alignment. If OP0 is a non-BLKmode object that is no
1406 wider than MAXMODE, use its mode. Otherwise, use the
1407 smallest mode containing the field. */
1409 if (GET_MODE (xop0
) == BLKmode
1410 || (GET_MODE_SIZE (GET_MODE (op0
))
1411 > GET_MODE_SIZE (maxmode
)))
1412 bestmode
= get_best_mode (bitsize
, bitnum
,
1413 MEM_ALIGN (xop0
), maxmode
,
1414 MEM_VOLATILE_P (xop0
));
1416 bestmode
= GET_MODE (xop0
);
1418 if (bestmode
== VOIDmode
1419 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1420 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1423 /* Compute offset as multiple of this unit,
1424 counting in bytes. */
1425 unit
= GET_MODE_BITSIZE (bestmode
);
1426 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1427 xbitpos
= bitnum
% unit
;
1428 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1430 /* Fetch it to a register in that size. */
1431 xop0
= force_reg (bestmode
, xop0
);
1433 /* XBITPOS counts within UNIT, which is what is expected. */
1436 /* Get ref to first byte containing part of the field. */
1437 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1439 volatile_ok
= save_volatile_ok
;
1442 /* If op0 is a register, we need it in MAXMODE (which is usually
1443 SImode). to make it acceptable to the format of extzv. */
1444 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1446 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
1447 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1449 /* On big-endian machines, we count bits from the most significant.
1450 If the bit field insn does not, we must invert. */
1451 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1452 xbitpos
= unit
- bitsize
- xbitpos
;
1454 /* Now convert from counting within UNIT to counting in MAXMODE. */
1455 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
1456 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
1458 unit
= GET_MODE_BITSIZE (maxmode
);
1461 || (flag_force_mem
&& MEM_P (xtarget
)))
1462 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1464 if (GET_MODE (xtarget
) != maxmode
)
1466 if (REG_P (xtarget
))
1468 int wider
= (GET_MODE_SIZE (maxmode
)
1469 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1470 xtarget
= gen_lowpart (maxmode
, xtarget
);
1472 xspec_target_subreg
= xtarget
;
1475 xtarget
= gen_reg_rtx (maxmode
);
1478 /* If this machine's extzv insists on a register target,
1479 make sure we have one. */
1480 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[0].predicate
)
1481 (xtarget
, maxmode
)))
1482 xtarget
= gen_reg_rtx (maxmode
);
1484 bitsize_rtx
= GEN_INT (bitsize
);
1485 bitpos_rtx
= GEN_INT (xbitpos
);
1487 pat
= gen_extzv (xtarget
, xop0
, bitsize_rtx
, bitpos_rtx
);
1492 spec_target
= xspec_target
;
1493 spec_target_subreg
= xspec_target_subreg
;
1497 delete_insns_since (last
);
1498 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1504 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1510 && (GET_MODE_BITSIZE (extv_mode
) >= bitsize
)
1511 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1512 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extv_mode
))))
1514 int xbitpos
= bitpos
, xoffset
= offset
;
1515 rtx bitsize_rtx
, bitpos_rtx
;
1516 rtx last
= get_last_insn ();
1517 rtx xop0
= op0
, xtarget
= target
;
1518 rtx xspec_target
= spec_target
;
1519 rtx xspec_target_subreg
= spec_target_subreg
;
1521 enum machine_mode maxmode
= mode_for_extraction (EP_extv
, 0);
1525 /* Is the memory operand acceptable? */
1526 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[1].predicate
)
1527 (xop0
, GET_MODE (xop0
))))
1529 /* No, load into a reg and extract from there. */
1530 enum machine_mode bestmode
;
1532 /* Get the mode to use for inserting into this field. If
1533 OP0 is BLKmode, get the smallest mode consistent with the
1534 alignment. If OP0 is a non-BLKmode object that is no
1535 wider than MAXMODE, use its mode. Otherwise, use the
1536 smallest mode containing the field. */
1538 if (GET_MODE (xop0
) == BLKmode
1539 || (GET_MODE_SIZE (GET_MODE (op0
))
1540 > GET_MODE_SIZE (maxmode
)))
1541 bestmode
= get_best_mode (bitsize
, bitnum
,
1542 MEM_ALIGN (xop0
), maxmode
,
1543 MEM_VOLATILE_P (xop0
));
1545 bestmode
= GET_MODE (xop0
);
1547 if (bestmode
== VOIDmode
1548 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1549 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1552 /* Compute offset as multiple of this unit,
1553 counting in bytes. */
1554 unit
= GET_MODE_BITSIZE (bestmode
);
1555 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1556 xbitpos
= bitnum
% unit
;
1557 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1559 /* Fetch it to a register in that size. */
1560 xop0
= force_reg (bestmode
, xop0
);
1562 /* XBITPOS counts within UNIT, which is what is expected. */
1565 /* Get ref to first byte containing part of the field. */
1566 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1569 /* If op0 is a register, we need it in MAXMODE (which is usually
1570 SImode) to make it acceptable to the format of extv. */
1571 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1573 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
1574 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1576 /* On big-endian machines, we count bits from the most significant.
1577 If the bit field insn does not, we must invert. */
1578 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1579 xbitpos
= unit
- bitsize
- xbitpos
;
1581 /* XBITPOS counts within a size of UNIT.
1582 Adjust to count within a size of MAXMODE. */
1583 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
1584 xbitpos
+= (GET_MODE_BITSIZE (maxmode
) - unit
);
1586 unit
= GET_MODE_BITSIZE (maxmode
);
1589 || (flag_force_mem
&& MEM_P (xtarget
)))
1590 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1592 if (GET_MODE (xtarget
) != maxmode
)
1594 if (REG_P (xtarget
))
1596 int wider
= (GET_MODE_SIZE (maxmode
)
1597 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1598 xtarget
= gen_lowpart (maxmode
, xtarget
);
1600 xspec_target_subreg
= xtarget
;
1603 xtarget
= gen_reg_rtx (maxmode
);
1606 /* If this machine's extv insists on a register target,
1607 make sure we have one. */
1608 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[0].predicate
)
1609 (xtarget
, maxmode
)))
1610 xtarget
= gen_reg_rtx (maxmode
);
1612 bitsize_rtx
= GEN_INT (bitsize
);
1613 bitpos_rtx
= GEN_INT (xbitpos
);
1615 pat
= gen_extv (xtarget
, xop0
, bitsize_rtx
, bitpos_rtx
);
1620 spec_target
= xspec_target
;
1621 spec_target_subreg
= xspec_target_subreg
;
1625 delete_insns_since (last
);
1626 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1632 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1635 if (target
== spec_target
)
1637 if (target
== spec_target_subreg
)
1639 if (GET_MODE (target
) != tmode
&& GET_MODE (target
) != mode
)
1641 /* If the target mode is floating-point, first convert to the
1642 integer mode of that size and then access it as a floating-point
1643 value via a SUBREG. */
1644 if (GET_MODE_CLASS (tmode
) != MODE_INT
1645 && GET_MODE_CLASS (tmode
) != MODE_PARTIAL_INT
)
1647 target
= convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode
),
1650 return gen_lowpart (tmode
, target
);
1653 return convert_to_mode (tmode
, target
, unsignedp
);
1658 /* Extract a bit field using shifts and boolean operations
1659 Returns an rtx to represent the value.
1660 OP0 addresses a register (word) or memory (byte).
1661 BITPOS says which bit within the word or byte the bit field starts in.
1662 OFFSET says how many bytes farther the bit field starts;
1663 it is 0 if OP0 is a register.
1664 BITSIZE says how many bits long the bit field is.
1665 (If OP0 is a register, it may be narrower than a full word,
1666 but BITPOS still counts within a full word,
1667 which is significant on bigendian machines.)
1669 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1670 If TARGET is nonzero, attempts to store the value there
1671 and return TARGET, but this is not guaranteed.
1672 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1675 extract_fixed_bit_field (enum machine_mode tmode
, rtx op0
,
1676 unsigned HOST_WIDE_INT offset
,
1677 unsigned HOST_WIDE_INT bitsize
,
1678 unsigned HOST_WIDE_INT bitpos
, rtx target
,
1681 unsigned int total_bits
= BITS_PER_WORD
;
1682 enum machine_mode mode
;
1684 if (GET_CODE (op0
) == SUBREG
|| REG_P (op0
))
1686 /* Special treatment for a bit field split across two registers. */
1687 if (bitsize
+ bitpos
> BITS_PER_WORD
)
1688 return extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
);
1692 /* Get the proper mode to use for this field. We want a mode that
1693 includes the entire field. If such a mode would be larger than
1694 a word, we won't be doing the extraction the normal way. */
1696 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
1697 MEM_ALIGN (op0
), word_mode
, MEM_VOLATILE_P (op0
));
1699 if (mode
== VOIDmode
)
1700 /* The only way this should occur is if the field spans word
1702 return extract_split_bit_field (op0
, bitsize
,
1703 bitpos
+ offset
* BITS_PER_UNIT
,
1706 total_bits
= GET_MODE_BITSIZE (mode
);
1708 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1709 be in the range 0 to total_bits-1, and put any excess bytes in
1711 if (bitpos
>= total_bits
)
1713 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
1714 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
1718 /* Get ref to an aligned byte, halfword, or word containing the field.
1719 Adjust BITPOS to be position within a word,
1720 and OFFSET to be the offset of that word.
1721 Then alter OP0 to refer to that word. */
1722 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
1723 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
1724 op0
= adjust_address (op0
, mode
, offset
);
1727 mode
= GET_MODE (op0
);
1729 if (BYTES_BIG_ENDIAN
)
1730 /* BITPOS is the distance between our msb and that of OP0.
1731 Convert it to the distance from the lsb. */
1732 bitpos
= total_bits
- bitsize
- bitpos
;
1734 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1735 We have reduced the big-endian case to the little-endian case. */
1741 /* If the field does not already start at the lsb,
1742 shift it so it does. */
1743 tree amount
= build_int_cst (NULL_TREE
, bitpos
, 0);
1744 /* Maybe propagate the target for the shift. */
1745 /* But not if we will return it--could confuse integrate.c. */
1746 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1747 if (tmode
!= mode
) subtarget
= 0;
1748 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1750 /* Convert the value to the desired mode. */
1752 op0
= convert_to_mode (tmode
, op0
, 1);
1754 /* Unless the msb of the field used to be the msb when we shifted,
1755 mask out the upper bits. */
1757 if (GET_MODE_BITSIZE (mode
) != bitpos
+ bitsize
)
1758 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1759 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1760 target
, 1, OPTAB_LIB_WIDEN
);
1764 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1765 then arithmetic-shift its lsb to the lsb of the word. */
1766 op0
= force_reg (mode
, op0
);
1770 /* Find the narrowest integer mode that contains the field. */
1772 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1773 mode
= GET_MODE_WIDER_MODE (mode
))
1774 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitpos
)
1776 op0
= convert_to_mode (mode
, op0
, 0);
1780 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitpos
))
1783 = build_int_cst (NULL_TREE
,
1784 GET_MODE_BITSIZE (mode
) - (bitsize
+ bitpos
), 0);
1785 /* Maybe propagate the target for the shift. */
1786 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1787 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1790 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1791 build_int_cst (NULL_TREE
,
1792 GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1796 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1797 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1798 complement of that if COMPLEMENT. The mask is truncated if
1799 necessary to the width of mode MODE. The mask is zero-extended if
1800 BITSIZE+BITPOS is too small for MODE. */
1803 mask_rtx (enum machine_mode mode
, int bitpos
, int bitsize
, int complement
)
1805 HOST_WIDE_INT masklow
, maskhigh
;
1809 else if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1810 masklow
= (HOST_WIDE_INT
) -1 << bitpos
;
1814 if (bitpos
+ bitsize
< HOST_BITS_PER_WIDE_INT
)
1815 masklow
&= ((unsigned HOST_WIDE_INT
) -1
1816 >> (HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1818 if (bitpos
<= HOST_BITS_PER_WIDE_INT
)
1821 maskhigh
= (HOST_WIDE_INT
) -1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
1825 else if (bitpos
+ bitsize
> HOST_BITS_PER_WIDE_INT
)
1826 maskhigh
&= ((unsigned HOST_WIDE_INT
) -1
1827 >> (2 * HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1833 maskhigh
= ~maskhigh
;
1837 return immed_double_const (masklow
, maskhigh
, mode
);
1840 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1841 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1844 lshift_value (enum machine_mode mode
, rtx value
, int bitpos
, int bitsize
)
1846 unsigned HOST_WIDE_INT v
= INTVAL (value
);
1847 HOST_WIDE_INT low
, high
;
1849 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1850 v
&= ~((HOST_WIDE_INT
) -1 << bitsize
);
1852 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1855 high
= (bitpos
> 0 ? (v
>> (HOST_BITS_PER_WIDE_INT
- bitpos
)) : 0);
1860 high
= v
<< (bitpos
- HOST_BITS_PER_WIDE_INT
);
1863 return immed_double_const (low
, high
, mode
);
1866 /* Extract a bit field that is split across two words
1867 and return an RTX for the result.
1869 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1870 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1871 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1874 extract_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1875 unsigned HOST_WIDE_INT bitpos
, int unsignedp
)
1878 unsigned int bitsdone
= 0;
1879 rtx result
= NULL_RTX
;
1882 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1884 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1885 unit
= BITS_PER_WORD
;
1887 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1889 while (bitsdone
< bitsize
)
1891 unsigned HOST_WIDE_INT thissize
;
1893 unsigned HOST_WIDE_INT thispos
;
1894 unsigned HOST_WIDE_INT offset
;
1896 offset
= (bitpos
+ bitsdone
) / unit
;
1897 thispos
= (bitpos
+ bitsdone
) % unit
;
1899 /* THISSIZE must not overrun a word boundary. Otherwise,
1900 extract_fixed_bit_field will call us again, and we will mutually
1902 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1903 thissize
= MIN (thissize
, unit
- thispos
);
1905 /* If OP0 is a register, then handle OFFSET here.
1907 When handling multiword bitfields, extract_bit_field may pass
1908 down a word_mode SUBREG of a larger REG for a bitfield that actually
1909 crosses a word boundary. Thus, for a SUBREG, we must find
1910 the current word starting from the base register. */
1911 if (GET_CODE (op0
) == SUBREG
)
1913 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1914 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1915 GET_MODE (SUBREG_REG (op0
)));
1918 else if (REG_P (op0
))
1920 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1926 /* Extract the parts in bit-counting order,
1927 whose meaning is determined by BYTES_PER_UNIT.
1928 OFFSET is in UNITs, and UNIT is in bits.
1929 extract_fixed_bit_field wants offset in bytes. */
1930 part
= extract_fixed_bit_field (word_mode
, word
,
1931 offset
* unit
/ BITS_PER_UNIT
,
1932 thissize
, thispos
, 0, 1);
1933 bitsdone
+= thissize
;
1935 /* Shift this part into place for the result. */
1936 if (BYTES_BIG_ENDIAN
)
1938 if (bitsize
!= bitsdone
)
1939 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1940 build_int_cst (NULL_TREE
,
1941 bitsize
- bitsdone
, 0), 0, 1);
1945 if (bitsdone
!= thissize
)
1946 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1947 build_int_cst (NULL_TREE
,
1948 bitsdone
- thissize
, 0), 0, 1);
1954 /* Combine the parts with bitwise or. This works
1955 because we extracted each part as an unsigned bit field. */
1956 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
1962 /* Unsigned bit field: we are done. */
1965 /* Signed bit field: sign-extend with two arithmetic shifts. */
1966 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
1967 build_int_cst (NULL_TREE
,
1968 BITS_PER_WORD
- bitsize
, 0),
1970 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
1971 build_int_cst (NULL_TREE
,
1972 BITS_PER_WORD
- bitsize
, 0), NULL_RTX
, 0);
1975 /* Add INC into TARGET. */
1978 expand_inc (rtx target
, rtx inc
)
1980 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
1982 target
, 0, OPTAB_LIB_WIDEN
);
1983 if (value
!= target
)
1984 emit_move_insn (target
, value
);
1987 /* Subtract DEC from TARGET. */
1990 expand_dec (rtx target
, rtx dec
)
1992 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
1994 target
, 0, OPTAB_LIB_WIDEN
);
1995 if (value
!= target
)
1996 emit_move_insn (target
, value
);
1999 /* Output a shift instruction for expression code CODE,
2000 with SHIFTED being the rtx for the value to shift,
2001 and AMOUNT the tree for the amount to shift by.
2002 Store the result in the rtx TARGET, if that is convenient.
2003 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2004 Return the rtx for where the value is. */
2007 expand_shift (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2008 tree amount
, rtx target
, int unsignedp
)
2011 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
2012 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
2015 /* Previously detected shift-counts computed by NEGATE_EXPR
2016 and shifted in the other direction; but that does not work
2019 op1
= expand_expr (amount
, NULL_RTX
, VOIDmode
, 0);
2021 if (SHIFT_COUNT_TRUNCATED
)
2023 if (GET_CODE (op1
) == CONST_INT
2024 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
2025 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
)))
2026 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
2027 % GET_MODE_BITSIZE (mode
));
2028 else if (GET_CODE (op1
) == SUBREG
2029 && subreg_lowpart_p (op1
))
2030 op1
= SUBREG_REG (op1
);
2033 if (op1
== const0_rtx
)
2036 /* Check whether its cheaper to implement a left shift by a constant
2037 bit count by a sequence of additions. */
2038 if (code
== LSHIFT_EXPR
2039 && GET_CODE (op1
) == CONST_INT
2041 && INTVAL (op1
) < GET_MODE_BITSIZE (mode
)
2042 && shift_cost
[mode
][INTVAL (op1
)] > INTVAL (op1
) * add_cost
[mode
])
2045 for (i
= 0; i
< INTVAL (op1
); i
++)
2047 temp
= force_reg (mode
, shifted
);
2048 shifted
= expand_binop (mode
, add_optab
, temp
, temp
, NULL_RTX
,
2049 unsignedp
, OPTAB_LIB_WIDEN
);
2054 for (try = 0; temp
== 0 && try < 3; try++)
2056 enum optab_methods methods
;
2059 methods
= OPTAB_DIRECT
;
2061 methods
= OPTAB_WIDEN
;
2063 methods
= OPTAB_LIB_WIDEN
;
2067 /* Widening does not work for rotation. */
2068 if (methods
== OPTAB_WIDEN
)
2070 else if (methods
== OPTAB_LIB_WIDEN
)
2072 /* If we have been unable to open-code this by a rotation,
2073 do it as the IOR of two shifts. I.e., to rotate A
2074 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2075 where C is the bitsize of A.
2077 It is theoretically possible that the target machine might
2078 not be able to perform either shift and hence we would
2079 be making two libcalls rather than just the one for the
2080 shift (similarly if IOR could not be done). We will allow
2081 this extremely unlikely lossage to avoid complicating the
2084 rtx subtarget
= target
== shifted
? 0 : target
;
2086 tree type
= TREE_TYPE (amount
);
2087 tree new_amount
= make_tree (type
, op1
);
2089 = fold (build2 (MINUS_EXPR
, type
, convert
2090 (type
, build_int_cst
2091 (NULL_TREE
, GET_MODE_BITSIZE (mode
), 0)),
2094 shifted
= force_reg (mode
, shifted
);
2096 temp
= expand_shift (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
2097 mode
, shifted
, new_amount
, subtarget
, 1);
2098 temp1
= expand_shift (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
2099 mode
, shifted
, other_amount
, 0, 1);
2100 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
2101 unsignedp
, methods
);
2104 temp
= expand_binop (mode
,
2105 left
? rotl_optab
: rotr_optab
,
2106 shifted
, op1
, target
, unsignedp
, methods
);
2108 /* If we don't have the rotate, but we are rotating by a constant
2109 that is in range, try a rotate in the opposite direction. */
2111 if (temp
== 0 && GET_CODE (op1
) == CONST_INT
2113 && (unsigned int) INTVAL (op1
) < GET_MODE_BITSIZE (mode
))
2114 temp
= expand_binop (mode
,
2115 left
? rotr_optab
: rotl_optab
,
2117 GEN_INT (GET_MODE_BITSIZE (mode
)
2119 target
, unsignedp
, methods
);
2122 temp
= expand_binop (mode
,
2123 left
? ashl_optab
: lshr_optab
,
2124 shifted
, op1
, target
, unsignedp
, methods
);
2126 /* Do arithmetic shifts.
2127 Also, if we are going to widen the operand, we can just as well
2128 use an arithmetic right-shift instead of a logical one. */
2129 if (temp
== 0 && ! rotate
2130 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2132 enum optab_methods methods1
= methods
;
2134 /* If trying to widen a log shift to an arithmetic shift,
2135 don't accept an arithmetic shift of the same size. */
2137 methods1
= OPTAB_MUST_WIDEN
;
2139 /* Arithmetic shift */
2141 temp
= expand_binop (mode
,
2142 left
? ashl_optab
: ashr_optab
,
2143 shifted
, op1
, target
, unsignedp
, methods1
);
2146 /* We used to try extzv here for logical right shifts, but that was
2147 only useful for one machine, the VAX, and caused poor code
2148 generation there for lshrdi3, so the code was deleted and a
2149 define_expand for lshrsi3 was added to vax.md. */
2157 enum alg_code
{ alg_zero
, alg_m
, alg_shift
,
2158 alg_add_t_m2
, alg_sub_t_m2
,
2159 alg_add_factor
, alg_sub_factor
,
2160 alg_add_t2_m
, alg_sub_t2_m
,
2161 alg_add
, alg_subtract
, alg_factor
, alg_shiftop
};
2163 /* This structure records a sequence of operations.
2164 `ops' is the number of operations recorded.
2165 `cost' is their total cost.
2166 The operations are stored in `op' and the corresponding
2167 logarithms of the integer coefficients in `log'.
2169 These are the operations:
2170 alg_zero total := 0;
2171 alg_m total := multiplicand;
2172 alg_shift total := total * coeff
2173 alg_add_t_m2 total := total + multiplicand * coeff;
2174 alg_sub_t_m2 total := total - multiplicand * coeff;
2175 alg_add_factor total := total * coeff + total;
2176 alg_sub_factor total := total * coeff - total;
2177 alg_add_t2_m total := total * coeff + multiplicand;
2178 alg_sub_t2_m total := total * coeff - multiplicand;
2180 The first operand must be either alg_zero or alg_m. */
2186 /* The size of the OP and LOG fields are not directly related to the
2187 word size, but the worst-case algorithms will be if we have few
2188 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2189 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2190 in total wordsize operations. */
2191 enum alg_code op
[MAX_BITS_PER_WORD
];
2192 char log
[MAX_BITS_PER_WORD
];
2195 /* Indicates the type of fixup needed after a constant multiplication.
2196 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2197 the result should be negated, and ADD_VARIANT means that the
2198 multiplicand should be added to the result. */
2199 enum mult_variant
{basic_variant
, negate_variant
, add_variant
};
2201 static void synth_mult (struct algorithm
*, unsigned HOST_WIDE_INT
,
2202 int, enum machine_mode mode
);
2203 static bool choose_mult_variant (enum machine_mode
, HOST_WIDE_INT
,
2204 struct algorithm
*, enum mult_variant
*, int);
2205 static rtx
expand_mult_const (enum machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
2206 const struct algorithm
*, enum mult_variant
);
2207 static unsigned HOST_WIDE_INT
choose_multiplier (unsigned HOST_WIDE_INT
, int,
2208 int, unsigned HOST_WIDE_INT
*,
2210 static unsigned HOST_WIDE_INT
invert_mod2n (unsigned HOST_WIDE_INT
, int);
2211 static rtx
extract_high_half (enum machine_mode
, rtx
);
2212 static rtx
expand_mult_highpart_optab (enum machine_mode
, rtx
, rtx
, rtx
,
2214 /* Compute and return the best algorithm for multiplying by T.
2215 The algorithm must cost less than cost_limit
2216 If retval.cost >= COST_LIMIT, no algorithm was found and all
2217 other field of the returned struct are undefined.
2218 MODE is the machine mode of the multiplication. */
2221 synth_mult (struct algorithm
*alg_out
, unsigned HOST_WIDE_INT t
,
2222 int cost_limit
, enum machine_mode mode
)
2225 struct algorithm
*alg_in
, *best_alg
;
2227 unsigned HOST_WIDE_INT q
;
2228 int maxm
= MIN (BITS_PER_WORD
, GET_MODE_BITSIZE (mode
));
2230 /* Indicate that no algorithm is yet found. If no algorithm
2231 is found, this value will be returned and indicate failure. */
2232 alg_out
->cost
= cost_limit
;
2234 if (cost_limit
<= 0)
2237 /* Restrict the bits of "t" to the multiplication's mode. */
2238 t
&= GET_MODE_MASK (mode
);
2240 /* t == 1 can be done in zero cost. */
2245 alg_out
->op
[0] = alg_m
;
2249 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2253 if (zero_cost
>= cost_limit
)
2258 alg_out
->cost
= zero_cost
;
2259 alg_out
->op
[0] = alg_zero
;
2264 /* We'll be needing a couple extra algorithm structures now. */
2266 alg_in
= alloca (sizeof (struct algorithm
));
2267 best_alg
= alloca (sizeof (struct algorithm
));
2269 /* If we have a group of zero bits at the low-order part of T, try
2270 multiplying by the remaining bits and then doing a shift. */
2274 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2278 /* The function expand_shift will choose between a shift and
2279 a sequence of additions, so the observed cost is given as
2280 MIN (m * add_cost[mode], shift_cost[mode][m]). */
2281 cost
= m
* add_cost
[mode
];
2282 if (shift_cost
[mode
][m
] < cost
)
2283 cost
= shift_cost
[mode
][m
];
2284 synth_mult (alg_in
, q
, cost_limit
- cost
, mode
);
2286 cost
+= alg_in
->cost
;
2287 if (cost
< cost_limit
)
2289 struct algorithm
*x
;
2290 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2291 best_alg
->log
[best_alg
->ops
] = m
;
2292 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2298 /* If we have an odd number, add or subtract one. */
2301 unsigned HOST_WIDE_INT w
;
2303 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2305 /* If T was -1, then W will be zero after the loop. This is another
2306 case where T ends with ...111. Handling this with (T + 1) and
2307 subtract 1 produces slightly better code and results in algorithm
2308 selection much faster than treating it like the ...0111 case
2312 /* Reject the case where t is 3.
2313 Thus we prefer addition in that case. */
2316 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2318 cost
= add_cost
[mode
];
2319 synth_mult (alg_in
, t
+ 1, cost_limit
- cost
, mode
);
2321 cost
+= alg_in
->cost
;
2322 if (cost
< cost_limit
)
2324 struct algorithm
*x
;
2325 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2326 best_alg
->log
[best_alg
->ops
] = 0;
2327 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2333 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2335 cost
= add_cost
[mode
];
2336 synth_mult (alg_in
, t
- 1, cost_limit
- cost
, mode
);
2338 cost
+= alg_in
->cost
;
2339 if (cost
< cost_limit
)
2341 struct algorithm
*x
;
2342 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2343 best_alg
->log
[best_alg
->ops
] = 0;
2344 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2350 /* Look for factors of t of the form
2351 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2352 If we find such a factor, we can multiply by t using an algorithm that
2353 multiplies by q, shift the result by m and add/subtract it to itself.
2355 We search for large factors first and loop down, even if large factors
2356 are less probable than small; if we find a large factor we will find a
2357 good sequence quickly, and therefore be able to prune (by decreasing
2358 COST_LIMIT) the search. */
2360 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2362 unsigned HOST_WIDE_INT d
;
2364 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2365 if (t
% d
== 0 && t
> d
&& m
< maxm
)
2367 cost
= add_cost
[mode
] + shift_cost
[mode
][m
];
2368 if (shiftadd_cost
[mode
][m
] < cost
)
2369 cost
= shiftadd_cost
[mode
][m
];
2370 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
, mode
);
2372 cost
+= alg_in
->cost
;
2373 if (cost
< cost_limit
)
2375 struct algorithm
*x
;
2376 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2377 best_alg
->log
[best_alg
->ops
] = m
;
2378 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2381 /* Other factors will have been taken care of in the recursion. */
2385 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2386 if (t
% d
== 0 && t
> d
&& m
< maxm
)
2388 cost
= add_cost
[mode
] + shift_cost
[mode
][m
];
2389 if (shiftsub_cost
[mode
][m
] < cost
)
2390 cost
= shiftsub_cost
[mode
][m
];
2391 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
, mode
);
2393 cost
+= alg_in
->cost
;
2394 if (cost
< cost_limit
)
2396 struct algorithm
*x
;
2397 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2398 best_alg
->log
[best_alg
->ops
] = m
;
2399 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2406 /* Try shift-and-add (load effective address) instructions,
2407 i.e. do a*3, a*5, a*9. */
2413 if (m
>= 0 && m
< maxm
)
2415 cost
= shiftadd_cost
[mode
][m
];
2416 synth_mult (alg_in
, (t
- 1) >> m
, cost_limit
- cost
, mode
);
2418 cost
+= alg_in
->cost
;
2419 if (cost
< cost_limit
)
2421 struct algorithm
*x
;
2422 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2423 best_alg
->log
[best_alg
->ops
] = m
;
2424 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2432 if (m
>= 0 && m
< maxm
)
2434 cost
= shiftsub_cost
[mode
][m
];
2435 synth_mult (alg_in
, (t
+ 1) >> m
, cost_limit
- cost
, mode
);
2437 cost
+= alg_in
->cost
;
2438 if (cost
< cost_limit
)
2440 struct algorithm
*x
;
2441 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2442 best_alg
->log
[best_alg
->ops
] = m
;
2443 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2449 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2450 we have not found any algorithm. */
2451 if (cost_limit
== alg_out
->cost
)
2454 /* If we are getting a too long sequence for `struct algorithm'
2455 to record, make this search fail. */
2456 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2459 /* Copy the algorithm from temporary space to the space at alg_out.
2460 We avoid using structure assignment because the majority of
2461 best_alg is normally undefined, and this is a critical function. */
2462 alg_out
->ops
= best_alg
->ops
+ 1;
2463 alg_out
->cost
= cost_limit
;
2464 memcpy (alg_out
->op
, best_alg
->op
,
2465 alg_out
->ops
* sizeof *alg_out
->op
);
2466 memcpy (alg_out
->log
, best_alg
->log
,
2467 alg_out
->ops
* sizeof *alg_out
->log
);
2470 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2471 Try three variations:
2473 - a shift/add sequence based on VAL itself
2474 - a shift/add sequence based on -VAL, followed by a negation
2475 - a shift/add sequence based on VAL - 1, followed by an addition.
2477 Return true if the cheapest of these cost less than MULT_COST,
2478 describing the algorithm in *ALG and final fixup in *VARIANT. */
2481 choose_mult_variant (enum machine_mode mode
, HOST_WIDE_INT val
,
2482 struct algorithm
*alg
, enum mult_variant
*variant
,
2485 struct algorithm alg2
;
2487 *variant
= basic_variant
;
2488 synth_mult (alg
, val
, mult_cost
, mode
);
2490 /* This works only if the inverted value actually fits in an
2492 if (HOST_BITS_PER_INT
>= GET_MODE_BITSIZE (mode
))
2494 synth_mult (&alg2
, -val
, MIN (alg
->cost
, mult_cost
) - neg_cost
[mode
],
2496 alg2
.cost
+= neg_cost
[mode
];
2497 if (alg2
.cost
< alg
->cost
)
2498 *alg
= alg2
, *variant
= negate_variant
;
2501 /* This proves very useful for division-by-constant. */
2502 synth_mult (&alg2
, val
- 1, MIN (alg
->cost
, mult_cost
) - add_cost
[mode
],
2504 alg2
.cost
+= add_cost
[mode
];
2505 if (alg2
.cost
< alg
->cost
)
2506 *alg
= alg2
, *variant
= add_variant
;
2508 return alg
->cost
< mult_cost
;
2511 /* A subroutine of expand_mult, used for constant multiplications.
2512 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2513 convenient. Use the shift/add sequence described by ALG and apply
2514 the final fixup specified by VARIANT. */
2517 expand_mult_const (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT val
,
2518 rtx target
, const struct algorithm
*alg
,
2519 enum mult_variant variant
)
2521 HOST_WIDE_INT val_so_far
;
2522 rtx insn
, accum
, tem
;
2524 enum machine_mode nmode
;
2526 /* Avoid referencing memory over and over.
2527 For speed, but also for correctness when mem is volatile. */
2529 op0
= force_reg (mode
, op0
);
2531 /* ACCUM starts out either as OP0 or as a zero, depending on
2532 the first operation. */
2534 if (alg
->op
[0] == alg_zero
)
2536 accum
= copy_to_mode_reg (mode
, const0_rtx
);
2539 else if (alg
->op
[0] == alg_m
)
2541 accum
= copy_to_mode_reg (mode
, op0
);
2547 for (opno
= 1; opno
< alg
->ops
; opno
++)
2549 int log
= alg
->log
[opno
];
2550 int preserve
= preserve_subexpressions_p ();
2551 rtx shift_subtarget
= preserve
? 0 : accum
;
2553 = (opno
== alg
->ops
- 1 && target
!= 0 && variant
!= add_variant
2556 rtx accum_target
= preserve
? 0 : accum
;
2558 switch (alg
->op
[opno
])
2561 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2562 build_int_cst (NULL_TREE
, log
, 0),
2568 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2569 build_int_cst (NULL_TREE
, log
, 0),
2571 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2572 add_target
? add_target
: accum_target
);
2573 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2577 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2578 build_int_cst (NULL_TREE
, log
, 0),
2580 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2581 add_target
? add_target
: accum_target
);
2582 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2586 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2587 build_int_cst (NULL_TREE
, log
, 0),
2590 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2591 add_target
? add_target
: accum_target
);
2592 val_so_far
= (val_so_far
<< log
) + 1;
2596 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2597 build_int_cst (NULL_TREE
, log
, 0),
2598 shift_subtarget
, 0);
2599 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2600 add_target
? add_target
: accum_target
);
2601 val_so_far
= (val_so_far
<< log
) - 1;
2604 case alg_add_factor
:
2605 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2606 build_int_cst (NULL_TREE
, log
, 0),
2608 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2609 add_target
? add_target
: accum_target
);
2610 val_so_far
+= val_so_far
<< log
;
2613 case alg_sub_factor
:
2614 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2615 build_int_cst (NULL_TREE
, log
, 0),
2617 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
2618 (add_target
? add_target
2619 : preserve
? 0 : tem
));
2620 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2627 /* Write a REG_EQUAL note on the last insn so that we can cse
2628 multiplication sequences. Note that if ACCUM is a SUBREG,
2629 we've set the inner register and must properly indicate
2632 tem
= op0
, nmode
= mode
;
2633 if (GET_CODE (accum
) == SUBREG
)
2635 nmode
= GET_MODE (SUBREG_REG (accum
));
2636 tem
= gen_lowpart (nmode
, op0
);
2639 insn
= get_last_insn ();
2640 set_unique_reg_note (insn
, REG_EQUAL
,
2641 gen_rtx_MULT (nmode
, tem
, GEN_INT (val_so_far
)));
2644 if (variant
== negate_variant
)
2646 val_so_far
= -val_so_far
;
2647 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
2649 else if (variant
== add_variant
)
2651 val_so_far
= val_so_far
+ 1;
2652 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
2655 /* Compare only the bits of val and val_so_far that are significant
2656 in the result mode, to avoid sign-/zero-extension confusion. */
2657 val
&= GET_MODE_MASK (mode
);
2658 val_so_far
&= GET_MODE_MASK (mode
);
2659 if (val
!= val_so_far
)
2665 /* Perform a multiplication and return an rtx for the result.
2666 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2667 TARGET is a suggestion for where to store the result (an rtx).
2669 We check specially for a constant integer as OP1.
2670 If you want this check for OP0 as well, then before calling
2671 you should swap the two operands if OP0 would be constant. */
2674 expand_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
2677 rtx const_op1
= op1
;
2678 enum mult_variant variant
;
2679 struct algorithm algorithm
;
2681 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2682 less than or equal in size to `unsigned int' this doesn't matter.
2683 If the mode is larger than `unsigned int', then synth_mult works only
2684 if the constant value exactly fits in an `unsigned int' without any
2685 truncation. This means that multiplying by negative values does
2686 not work; results are off by 2^32 on a 32 bit machine. */
2688 /* If we are multiplying in DImode, it may still be a win
2689 to try to work with shifts and adds. */
2690 if (GET_CODE (op1
) == CONST_DOUBLE
2691 && GET_MODE_CLASS (GET_MODE (op1
)) == MODE_INT
2692 && HOST_BITS_PER_INT
>= BITS_PER_WORD
2693 && CONST_DOUBLE_HIGH (op1
) == 0)
2694 const_op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
2695 else if (HOST_BITS_PER_INT
< GET_MODE_BITSIZE (mode
)
2696 && GET_CODE (op1
) == CONST_INT
2697 && INTVAL (op1
) < 0)
2700 /* We used to test optimize here, on the grounds that it's better to
2701 produce a smaller program when -O is not used.
2702 But this causes such a terrible slowdown sometimes
2703 that it seems better to use synth_mult always. */
2705 if (const_op1
&& GET_CODE (const_op1
) == CONST_INT
2706 && (unsignedp
|| !flag_trapv
))
2708 int mult_cost
= rtx_cost (gen_rtx_MULT (mode
, op0
, op1
), SET
);
2710 if (choose_mult_variant (mode
, INTVAL (const_op1
), &algorithm
, &variant
,
2712 return expand_mult_const (mode
, op0
, INTVAL (const_op1
), target
,
2713 &algorithm
, variant
);
2716 if (GET_CODE (op0
) == CONST_DOUBLE
)
2723 /* Expand x*2.0 as x+x. */
2724 if (GET_CODE (op1
) == CONST_DOUBLE
2725 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2728 REAL_VALUE_FROM_CONST_DOUBLE (d
, op1
);
2730 if (REAL_VALUES_EQUAL (d
, dconst2
))
2732 op0
= force_reg (GET_MODE (op0
), op0
);
2733 return expand_binop (mode
, add_optab
, op0
, op0
,
2734 target
, unsignedp
, OPTAB_LIB_WIDEN
);
2738 /* This used to use umul_optab if unsigned, but for non-widening multiply
2739 there is no difference between signed and unsigned. */
2740 op0
= expand_binop (mode
,
2742 && flag_trapv
&& (GET_MODE_CLASS(mode
) == MODE_INT
)
2743 ? smulv_optab
: smul_optab
,
2744 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
2750 /* Return the smallest n such that 2**n >= X. */
2753 ceil_log2 (unsigned HOST_WIDE_INT x
)
2755 return floor_log2 (x
- 1) + 1;
2758 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2759 replace division by D, and put the least significant N bits of the result
2760 in *MULTIPLIER_PTR and return the most significant bit.
2762 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2763 needed precision is in PRECISION (should be <= N).
2765 PRECISION should be as small as possible so this function can choose
2766 multiplier more freely.
2768 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2769 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2771 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2772 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2775 unsigned HOST_WIDE_INT
2776 choose_multiplier (unsigned HOST_WIDE_INT d
, int n
, int precision
,
2777 unsigned HOST_WIDE_INT
*multiplier_ptr
,
2778 int *post_shift_ptr
, int *lgup_ptr
)
2780 HOST_WIDE_INT mhigh_hi
, mlow_hi
;
2781 unsigned HOST_WIDE_INT mhigh_lo
, mlow_lo
;
2782 int lgup
, post_shift
;
2784 unsigned HOST_WIDE_INT nl
, dummy1
;
2785 HOST_WIDE_INT nh
, dummy2
;
2787 /* lgup = ceil(log2(divisor)); */
2788 lgup
= ceil_log2 (d
);
2794 pow2
= n
+ lgup
- precision
;
2796 if (pow
== 2 * HOST_BITS_PER_WIDE_INT
)
2798 /* We could handle this with some effort, but this case is much better
2799 handled directly with a scc insn, so rely on caller using that. */
2803 /* mlow = 2^(N + lgup)/d */
2804 if (pow
>= HOST_BITS_PER_WIDE_INT
)
2806 nh
= (HOST_WIDE_INT
) 1 << (pow
- HOST_BITS_PER_WIDE_INT
);
2812 nl
= (unsigned HOST_WIDE_INT
) 1 << pow
;
2814 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
2815 &mlow_lo
, &mlow_hi
, &dummy1
, &dummy2
);
2817 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2818 if (pow2
>= HOST_BITS_PER_WIDE_INT
)
2819 nh
|= (HOST_WIDE_INT
) 1 << (pow2
- HOST_BITS_PER_WIDE_INT
);
2821 nl
|= (unsigned HOST_WIDE_INT
) 1 << pow2
;
2822 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
2823 &mhigh_lo
, &mhigh_hi
, &dummy1
, &dummy2
);
2825 if (mhigh_hi
&& nh
- d
>= d
)
2827 if (mhigh_hi
> 1 || mlow_hi
> 1)
2829 /* Assert that mlow < mhigh. */
2830 if (! (mlow_hi
< mhigh_hi
|| (mlow_hi
== mhigh_hi
&& mlow_lo
< mhigh_lo
)))
2833 /* If precision == N, then mlow, mhigh exceed 2^N
2834 (but they do not exceed 2^(N+1)). */
2836 /* Reduce to lowest terms. */
2837 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
2839 unsigned HOST_WIDE_INT ml_lo
= (mlow_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mlow_lo
>> 1);
2840 unsigned HOST_WIDE_INT mh_lo
= (mhigh_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mhigh_lo
>> 1);
2850 *post_shift_ptr
= post_shift
;
2852 if (n
< HOST_BITS_PER_WIDE_INT
)
2854 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
2855 *multiplier_ptr
= mhigh_lo
& mask
;
2856 return mhigh_lo
>= mask
;
2860 *multiplier_ptr
= mhigh_lo
;
2865 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2866 congruent to 1 (mod 2**N). */
2868 static unsigned HOST_WIDE_INT
2869 invert_mod2n (unsigned HOST_WIDE_INT x
, int n
)
2871 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2873 /* The algorithm notes that the choice y = x satisfies
2874 x*y == 1 mod 2^3, since x is assumed odd.
2875 Each iteration doubles the number of bits of significance in y. */
2877 unsigned HOST_WIDE_INT mask
;
2878 unsigned HOST_WIDE_INT y
= x
;
2881 mask
= (n
== HOST_BITS_PER_WIDE_INT
2882 ? ~(unsigned HOST_WIDE_INT
) 0
2883 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
2887 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
2893 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2894 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2895 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2896 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2899 The result is put in TARGET if that is convenient.
2901 MODE is the mode of operation. */
2904 expand_mult_highpart_adjust (enum machine_mode mode
, rtx adj_operand
, rtx op0
,
2905 rtx op1
, rtx target
, int unsignedp
)
2908 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
2910 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
2911 build_int_cst (NULL_TREE
,
2912 GET_MODE_BITSIZE (mode
) - 1, 0),
2914 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
2916 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
2919 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
2920 build_int_cst (NULL_TREE
,
2921 GET_MODE_BITSIZE (mode
) - 1, 0),
2923 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
2924 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
2930 /* Subroutine of expand_mult_highpart. Return the MODE high part of OP. */
2933 extract_high_half (enum machine_mode mode
, rtx op
)
2935 enum machine_mode wider_mode
;
2937 if (mode
== word_mode
)
2938 return gen_highpart (mode
, op
);
2940 wider_mode
= GET_MODE_WIDER_MODE (mode
);
2941 op
= expand_shift (RSHIFT_EXPR
, wider_mode
, op
,
2942 build_int_cst (NULL_TREE
,
2943 GET_MODE_BITSIZE (mode
), 0), 0, 1);
2944 return convert_modes (mode
, wider_mode
, op
, 0);
2947 /* Like expand_mult_highpart, but only consider using a multiplication
2948 optab. OP1 is an rtx for the constant operand. */
2951 expand_mult_highpart_optab (enum machine_mode mode
, rtx op0
, rtx op1
,
2952 rtx target
, int unsignedp
, int max_cost
)
2954 rtx narrow_op1
= gen_int_mode (INTVAL (op1
), mode
);
2955 enum machine_mode wider_mode
;
2960 wider_mode
= GET_MODE_WIDER_MODE (mode
);
2961 size
= GET_MODE_BITSIZE (mode
);
2963 /* Firstly, try using a multiplication insn that only generates the needed
2964 high part of the product, and in the sign flavor of unsignedp. */
2965 if (mul_highpart_cost
[mode
] < max_cost
)
2967 moptab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
2968 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
2969 unsignedp
, OPTAB_DIRECT
);
2974 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2975 Need to adjust the result after the multiplication. */
2976 if (size
- 1 < BITS_PER_WORD
2977 && (mul_highpart_cost
[mode
] + 2 * shift_cost
[mode
][size
-1]
2978 + 4 * add_cost
[mode
] < max_cost
))
2980 moptab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
2981 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
2982 unsignedp
, OPTAB_DIRECT
);
2984 /* We used the wrong signedness. Adjust the result. */
2985 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
2989 /* Try widening multiplication. */
2990 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
2991 if (moptab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
2992 && mul_widen_cost
[wider_mode
] < max_cost
)
2994 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
, 0,
2995 unsignedp
, OPTAB_WIDEN
);
2997 return extract_high_half (mode
, tem
);
3000 /* Try widening the mode and perform a non-widening multiplication. */
3001 moptab
= smul_optab
;
3002 if (smul_optab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
3003 && size
- 1 < BITS_PER_WORD
3004 && mul_cost
[wider_mode
] + shift_cost
[mode
][size
-1] < max_cost
)
3006 tem
= expand_binop (wider_mode
, moptab
, op0
, op1
, 0,
3007 unsignedp
, OPTAB_WIDEN
);
3009 return extract_high_half (mode
, tem
);
3012 /* Try widening multiplication of opposite signedness, and adjust. */
3013 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
3014 if (moptab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
3015 && size
- 1 < BITS_PER_WORD
3016 && (mul_widen_cost
[wider_mode
] + 2 * shift_cost
[mode
][size
-1]
3017 + 4 * add_cost
[mode
] < max_cost
))
3019 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
,
3020 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
3023 tem
= extract_high_half (mode
, tem
);
3024 /* We used the wrong signedness. Adjust the result. */
3025 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3033 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
3034 in TARGET if that is convenient, and return where the result is. If the
3035 operation can not be performed, 0 is returned.
3037 MODE is the mode of operation and result.
3039 UNSIGNEDP nonzero means unsigned multiply.
3041 MAX_COST is the total allowed cost for the expanded RTL. */
3044 expand_mult_highpart (enum machine_mode mode
, rtx op0
,
3045 unsigned HOST_WIDE_INT cnst1
, rtx target
,
3046 int unsignedp
, int max_cost
)
3048 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
3050 bool sign_adjust
= false;
3051 enum mult_variant variant
;
3052 struct algorithm alg
;
3055 /* We can't support modes wider than HOST_BITS_PER_INT. */
3056 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
3059 op1
= gen_int_mode (cnst1
, wider_mode
);
3060 cnst1
&= GET_MODE_MASK (mode
);
3062 /* We can't optimize modes wider than BITS_PER_WORD.
3063 ??? We might be able to perform double-word arithmetic if
3064 mode == word_mode, however all the cost calculations in
3065 synth_mult etc. assume single-word operations. */
3066 if (GET_MODE_BITSIZE (wider_mode
) > BITS_PER_WORD
)
3067 return expand_mult_highpart_optab (mode
, op0
, op1
, target
,
3068 unsignedp
, max_cost
);
3070 extra_cost
= shift_cost
[mode
][GET_MODE_BITSIZE (mode
) - 1];
3072 /* Check whether we try to multiply by a negative constant. */
3073 if (!unsignedp
&& ((cnst1
>> (GET_MODE_BITSIZE (mode
) - 1)) & 1))
3076 extra_cost
+= add_cost
[mode
];
3079 /* See whether shift/add multiplication is cheap enough. */
3080 if (choose_mult_variant (wider_mode
, cnst1
, &alg
, &variant
,
3081 max_cost
- extra_cost
))
3083 /* See whether the specialized multiplication optabs are
3084 cheaper than the shift/add version. */
3085 tem
= expand_mult_highpart_optab (mode
, op0
, op1
, target
,
3086 unsignedp
, alg
.cost
+ extra_cost
);
3090 tem
= convert_to_mode (wider_mode
, op0
, unsignedp
);
3091 tem
= expand_mult_const (wider_mode
, tem
, cnst1
, 0, &alg
, variant
);
3092 tem
= extract_high_half (mode
, tem
);
3094 /* Adjust result for signedness. */
3096 tem
= force_operand (gen_rtx_MINUS (mode
, tem
, op0
), tem
);
3100 return expand_mult_highpart_optab (mode
, op0
, op1
, target
,
3101 unsignedp
, max_cost
);
3105 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3108 expand_smod_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3110 unsigned HOST_WIDE_INT mask
;
3111 rtx result
, temp
, shift
, label
;
3114 logd
= floor_log2 (d
);
3115 result
= gen_reg_rtx (mode
);
3117 /* Avoid conditional branches when they're expensive. */
3118 if (BRANCH_COST
>= 2
3121 rtx signmask
= emit_store_flag (result
, LT
, op0
, const0_rtx
,
3125 signmask
= force_reg (mode
, signmask
);
3126 mask
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3127 shift
= GEN_INT (GET_MODE_BITSIZE (mode
) - logd
);
3129 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3130 which instruction sequence to use. If logical right shifts
3131 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3132 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3134 temp
= gen_rtx_LSHIFTRT (mode
, result
, shift
);
3135 if (lshr_optab
->handlers
[mode
].insn_code
== CODE_FOR_nothing
3136 || rtx_cost (temp
, SET
) > COSTS_N_INSNS (2))
3138 temp
= expand_binop (mode
, xor_optab
, op0
, signmask
,
3139 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3140 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3141 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3142 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (mask
),
3143 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3144 temp
= expand_binop (mode
, xor_optab
, temp
, signmask
,
3145 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3146 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3147 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3151 signmask
= expand_binop (mode
, lshr_optab
, signmask
, shift
,
3152 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3153 signmask
= force_reg (mode
, signmask
);
3155 temp
= expand_binop (mode
, add_optab
, op0
, signmask
,
3156 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3157 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (mask
),
3158 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3159 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3160 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3166 /* Mask contains the mode's signbit and the significant bits of the
3167 modulus. By including the signbit in the operation, many targets
3168 can avoid an explicit compare operation in the following comparison
3171 mask
= (HOST_WIDE_INT
) -1 << (GET_MODE_BITSIZE (mode
) - 1)
3172 | (((HOST_WIDE_INT
) 1 << logd
) - 1);
3174 temp
= expand_binop (mode
, and_optab
, op0
, GEN_INT (mask
), result
,
3175 1, OPTAB_LIB_WIDEN
);
3177 emit_move_insn (result
, temp
);
3179 label
= gen_label_rtx ();
3180 do_cmp_and_jump (result
, const0_rtx
, GE
, mode
, label
);
3182 temp
= expand_binop (mode
, sub_optab
, result
, const1_rtx
, result
,
3183 0, OPTAB_LIB_WIDEN
);
3184 mask
= (HOST_WIDE_INT
) -1 << logd
;
3185 temp
= expand_binop (mode
, ior_optab
, temp
, GEN_INT (mask
), result
,
3186 1, OPTAB_LIB_WIDEN
);
3187 temp
= expand_binop (mode
, add_optab
, temp
, const1_rtx
, result
,
3188 0, OPTAB_LIB_WIDEN
);
3190 emit_move_insn (result
, temp
);
3195 /* Expand signed division of OP0 by a power of two D in mode MODE.
3196 This routine is only called for positive values of D. */
3199 expand_sdiv_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3205 logd
= floor_log2 (d
);
3206 shift
= build_int_cst (NULL_TREE
, logd
, 0);
3208 if (d
== 2 && BRANCH_COST
>= 1)
3210 temp
= gen_reg_rtx (mode
);
3211 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, 1);
3212 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3213 0, OPTAB_LIB_WIDEN
);
3214 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3217 #ifdef HAVE_conditional_move
3218 if (BRANCH_COST
>= 2)
3223 temp2
= copy_to_mode_reg (mode
, op0
);
3224 temp
= expand_binop (mode
, add_optab
, temp2
, GEN_INT (d
-1),
3225 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3226 temp
= force_reg (mode
, temp
);
3228 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3229 temp2
= emit_conditional_move (temp2
, LT
, temp2
, const0_rtx
,
3230 mode
, temp
, temp2
, mode
, 0);
3233 rtx seq
= get_insns ();
3236 return expand_shift (RSHIFT_EXPR
, mode
, temp2
, shift
, NULL_RTX
, 0);
3242 if (BRANCH_COST
>= 2)
3244 int ushift
= GET_MODE_BITSIZE (mode
) - logd
;
3246 temp
= gen_reg_rtx (mode
);
3247 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, -1);
3248 if (shift_cost
[mode
][ushift
] > COSTS_N_INSNS (1))
3249 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (d
- 1),
3250 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3252 temp
= expand_shift (RSHIFT_EXPR
, mode
, temp
,
3253 build_int_cst (NULL_TREE
, ushift
, 0),
3255 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3256 0, OPTAB_LIB_WIDEN
);
3257 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3260 label
= gen_label_rtx ();
3261 temp
= copy_to_mode_reg (mode
, op0
);
3262 do_cmp_and_jump (temp
, const0_rtx
, GE
, mode
, label
);
3263 expand_inc (temp
, GEN_INT (d
- 1));
3265 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3268 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3269 if that is convenient, and returning where the result is.
3270 You may request either the quotient or the remainder as the result;
3271 specify REM_FLAG nonzero to get the remainder.
3273 CODE is the expression code for which kind of division this is;
3274 it controls how rounding is done. MODE is the machine mode to use.
3275 UNSIGNEDP nonzero means do unsigned division. */
3277 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3278 and then correct it by or'ing in missing high bits
3279 if result of ANDI is nonzero.
3280 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3281 This could optimize to a bfexts instruction.
3282 But C doesn't use these operations, so their optimizations are
3284 /* ??? For modulo, we don't actually need the highpart of the first product,
3285 the low part will do nicely. And for small divisors, the second multiply
3286 can also be a low-part only multiply or even be completely left out.
3287 E.g. to calculate the remainder of a division by 3 with a 32 bit
3288 multiply, multiply with 0x55555556 and extract the upper two bits;
3289 the result is exact for inputs up to 0x1fffffff.
3290 The input range can be reduced by using cross-sum rules.
3291 For odd divisors >= 3, the following table gives right shift counts
3292 so that if a number is shifted by an integer multiple of the given
3293 amount, the remainder stays the same:
3294 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3295 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3296 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3297 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3298 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3300 Cross-sum rules for even numbers can be derived by leaving as many bits
3301 to the right alone as the divisor has zeros to the right.
3302 E.g. if x is an unsigned 32 bit number:
3303 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3306 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
3309 expand_divmod (int rem_flag
, enum tree_code code
, enum machine_mode mode
,
3310 rtx op0
, rtx op1
, rtx target
, int unsignedp
)
3312 enum machine_mode compute_mode
;
3314 rtx quotient
= 0, remainder
= 0;
3318 optab optab1
, optab2
;
3319 int op1_is_constant
, op1_is_pow2
= 0;
3320 int max_cost
, extra_cost
;
3321 static HOST_WIDE_INT last_div_const
= 0;
3322 static HOST_WIDE_INT ext_op1
;
3324 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3325 if (op1_is_constant
)
3327 ext_op1
= INTVAL (op1
);
3329 ext_op1
&= GET_MODE_MASK (mode
);
3330 op1_is_pow2
= ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1
)
3331 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1
))));
3335 This is the structure of expand_divmod:
3337 First comes code to fix up the operands so we can perform the operations
3338 correctly and efficiently.
3340 Second comes a switch statement with code specific for each rounding mode.
3341 For some special operands this code emits all RTL for the desired
3342 operation, for other cases, it generates only a quotient and stores it in
3343 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3344 to indicate that it has not done anything.
3346 Last comes code that finishes the operation. If QUOTIENT is set and
3347 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3348 QUOTIENT is not set, it is computed using trunc rounding.
3350 We try to generate special code for division and remainder when OP1 is a
3351 constant. If |OP1| = 2**n we can use shifts and some other fast
3352 operations. For other values of OP1, we compute a carefully selected
3353 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3356 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3357 half of the product. Different strategies for generating the product are
3358 implemented in expand_mult_highpart.
3360 If what we actually want is the remainder, we generate that by another
3361 by-constant multiplication and a subtraction. */
3363 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3364 code below will malfunction if we are, so check here and handle
3365 the special case if so. */
3366 if (op1
== const1_rtx
)
3367 return rem_flag
? const0_rtx
: op0
;
3369 /* When dividing by -1, we could get an overflow.
3370 negv_optab can handle overflows. */
3371 if (! unsignedp
&& op1
== constm1_rtx
)
3375 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS(mode
) == MODE_INT
3376 ? negv_optab
: neg_optab
, op0
, target
, 0);
3380 /* Don't use the function value register as a target
3381 since we have to read it as well as write it,
3382 and function-inlining gets confused by this. */
3383 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
3384 /* Don't clobber an operand while doing a multi-step calculation. */
3385 || ((rem_flag
|| op1_is_constant
)
3386 && (reg_mentioned_p (target
, op0
)
3387 || (MEM_P (op0
) && MEM_P (target
))))
3388 || reg_mentioned_p (target
, op1
)
3389 || (MEM_P (op1
) && MEM_P (target
))))
3392 /* Get the mode in which to perform this computation. Normally it will
3393 be MODE, but sometimes we can't do the desired operation in MODE.
3394 If so, pick a wider mode in which we can do the operation. Convert
3395 to that mode at the start to avoid repeated conversions.
3397 First see what operations we need. These depend on the expression
3398 we are evaluating. (We assume that divxx3 insns exist under the
3399 same conditions that modxx3 insns and that these insns don't normally
3400 fail. If these assumptions are not correct, we may generate less
3401 efficient code in some cases.)
3403 Then see if we find a mode in which we can open-code that operation
3404 (either a division, modulus, or shift). Finally, check for the smallest
3405 mode for which we can do the operation with a library call. */
3407 /* We might want to refine this now that we have division-by-constant
3408 optimization. Since expand_mult_highpart tries so many variants, it is
3409 not straightforward to generalize this. Maybe we should make an array
3410 of possible modes in init_expmed? Save this for GCC 2.7. */
3412 optab1
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3413 ? (unsignedp
? lshr_optab
: ashr_optab
)
3414 : (unsignedp
? udiv_optab
: sdiv_optab
));
3415 optab2
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3417 : (unsignedp
? udivmod_optab
: sdivmod_optab
));
3419 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3420 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3421 if (optab1
->handlers
[compute_mode
].insn_code
!= CODE_FOR_nothing
3422 || optab2
->handlers
[compute_mode
].insn_code
!= CODE_FOR_nothing
)
3425 if (compute_mode
== VOIDmode
)
3426 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3427 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3428 if (optab1
->handlers
[compute_mode
].libfunc
3429 || optab2
->handlers
[compute_mode
].libfunc
)
3432 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3434 if (compute_mode
== VOIDmode
)
3435 compute_mode
= mode
;
3437 if (target
&& GET_MODE (target
) == compute_mode
)
3440 tquotient
= gen_reg_rtx (compute_mode
);
3442 size
= GET_MODE_BITSIZE (compute_mode
);
3444 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3445 (mode), and thereby get better code when OP1 is a constant. Do that
3446 later. It will require going over all usages of SIZE below. */
3447 size
= GET_MODE_BITSIZE (mode
);
3450 /* Only deduct something for a REM if the last divide done was
3451 for a different constant. Then set the constant of the last
3453 max_cost
= div_cost
[compute_mode
]
3454 - (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3455 && INTVAL (op1
) == last_div_const
)
3456 ? mul_cost
[compute_mode
] + add_cost
[compute_mode
]
3459 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3461 /* Now convert to the best mode to use. */
3462 if (compute_mode
!= mode
)
3464 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
3465 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
3467 /* convert_modes may have placed op1 into a register, so we
3468 must recompute the following. */
3469 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3470 op1_is_pow2
= (op1_is_constant
3471 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3473 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
)))))) ;
3476 /* If one of the operands is a volatile MEM, copy it into a register. */
3478 if (MEM_P (op0
) && MEM_VOLATILE_P (op0
))
3479 op0
= force_reg (compute_mode
, op0
);
3480 if (MEM_P (op1
) && MEM_VOLATILE_P (op1
))
3481 op1
= force_reg (compute_mode
, op1
);
3483 /* If we need the remainder or if OP1 is constant, we need to
3484 put OP0 in a register in case it has any queued subexpressions. */
3485 if (rem_flag
|| op1_is_constant
)
3486 op0
= force_reg (compute_mode
, op0
);
3488 last
= get_last_insn ();
3490 /* Promote floor rounding to trunc rounding for unsigned operations. */
3493 if (code
== FLOOR_DIV_EXPR
)
3494 code
= TRUNC_DIV_EXPR
;
3495 if (code
== FLOOR_MOD_EXPR
)
3496 code
= TRUNC_MOD_EXPR
;
3497 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
3498 code
= TRUNC_DIV_EXPR
;
3501 if (op1
!= const0_rtx
)
3504 case TRUNC_MOD_EXPR
:
3505 case TRUNC_DIV_EXPR
:
3506 if (op1_is_constant
)
3510 unsigned HOST_WIDE_INT mh
, ml
;
3511 int pre_shift
, post_shift
;
3513 unsigned HOST_WIDE_INT d
= (INTVAL (op1
)
3514 & GET_MODE_MASK (compute_mode
));
3516 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3518 pre_shift
= floor_log2 (d
);
3522 = expand_binop (compute_mode
, and_optab
, op0
,
3523 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3527 return gen_lowpart (mode
, remainder
);
3529 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3530 build_int_cst (NULL_TREE
,
3534 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3536 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
3538 /* Most significant bit of divisor is set; emit an scc
3540 quotient
= emit_store_flag (tquotient
, GEU
, op0
, op1
,
3541 compute_mode
, 1, 1);
3547 /* Find a suitable multiplier and right shift count
3548 instead of multiplying with D. */
3550 mh
= choose_multiplier (d
, size
, size
,
3551 &ml
, &post_shift
, &dummy
);
3553 /* If the suggested multiplier is more than SIZE bits,
3554 we can do better for even divisors, using an
3555 initial right shift. */
3556 if (mh
!= 0 && (d
& 1) == 0)
3558 pre_shift
= floor_log2 (d
& -d
);
3559 mh
= choose_multiplier (d
>> pre_shift
, size
,
3561 &ml
, &post_shift
, &dummy
);
3572 if (post_shift
- 1 >= BITS_PER_WORD
)
3576 = (shift_cost
[compute_mode
][post_shift
- 1]
3577 + shift_cost
[compute_mode
][1]
3578 + 2 * add_cost
[compute_mode
]);
3579 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3581 max_cost
- extra_cost
);
3584 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
3588 (RSHIFT_EXPR
, compute_mode
, t2
,
3589 build_int_cst (NULL_TREE
, 1, 0),
3591 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
3594 quotient
= expand_shift
3595 (RSHIFT_EXPR
, compute_mode
, t4
,
3596 build_int_cst (NULL_TREE
,
3604 if (pre_shift
>= BITS_PER_WORD
3605 || post_shift
>= BITS_PER_WORD
)
3609 (RSHIFT_EXPR
, compute_mode
, op0
,
3610 build_int_cst (NULL_TREE
, pre_shift
, 0),
3613 = (shift_cost
[compute_mode
][pre_shift
]
3614 + shift_cost
[compute_mode
][post_shift
]);
3615 t2
= expand_mult_highpart (compute_mode
, t1
, ml
,
3617 max_cost
- extra_cost
);
3620 quotient
= expand_shift
3621 (RSHIFT_EXPR
, compute_mode
, t2
,
3622 build_int_cst (NULL_TREE
,
3628 else /* Too wide mode to use tricky code */
3631 insn
= get_last_insn ();
3633 && (set
= single_set (insn
)) != 0
3634 && SET_DEST (set
) == quotient
)
3635 set_unique_reg_note (insn
,
3637 gen_rtx_UDIV (compute_mode
, op0
, op1
));
3639 else /* TRUNC_DIV, signed */
3641 unsigned HOST_WIDE_INT ml
;
3642 int lgup
, post_shift
;
3643 HOST_WIDE_INT d
= INTVAL (op1
);
3644 unsigned HOST_WIDE_INT abs_d
= d
>= 0 ? d
: -d
;
3646 /* n rem d = n rem -d */
3647 if (rem_flag
&& d
< 0)
3650 op1
= gen_int_mode (abs_d
, compute_mode
);
3656 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
3658 else if (abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
3660 /* This case is not handled correctly below. */
3661 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
3662 compute_mode
, 1, 1);
3666 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
3667 && (rem_flag
? smod_pow2_cheap
[compute_mode
]
3668 : sdiv_pow2_cheap
[compute_mode
])
3669 /* We assume that cheap metric is true if the
3670 optab has an expander for this mode. */
3671 && (((rem_flag
? smod_optab
: sdiv_optab
)
3672 ->handlers
[compute_mode
].insn_code
3673 != CODE_FOR_nothing
)
3674 || (sdivmod_optab
->handlers
[compute_mode
]
3675 .insn_code
!= CODE_FOR_nothing
)))
3677 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
3681 remainder
= expand_smod_pow2 (compute_mode
, op0
, d
);
3683 return gen_lowpart (mode
, remainder
);
3685 quotient
= expand_sdiv_pow2 (compute_mode
, op0
, abs_d
);
3687 /* We have computed OP0 / abs(OP1). If OP1 is negative,
3688 negate the quotient. */
3691 insn
= get_last_insn ();
3693 && (set
= single_set (insn
)) != 0
3694 && SET_DEST (set
) == quotient
3695 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
3696 << (HOST_BITS_PER_WIDE_INT
- 1)))
3697 set_unique_reg_note (insn
,
3699 gen_rtx_DIV (compute_mode
,
3706 quotient
= expand_unop (compute_mode
, neg_optab
,
3707 quotient
, quotient
, 0);
3710 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3712 choose_multiplier (abs_d
, size
, size
- 1,
3713 &ml
, &post_shift
, &lgup
);
3714 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
3718 if (post_shift
>= BITS_PER_WORD
3719 || size
- 1 >= BITS_PER_WORD
)
3722 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
3723 + shift_cost
[compute_mode
][size
- 1]
3724 + add_cost
[compute_mode
]);
3725 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3727 max_cost
- extra_cost
);
3731 (RSHIFT_EXPR
, compute_mode
, t1
,
3732 build_int_cst (NULL_TREE
, post_shift
, 0),
3735 (RSHIFT_EXPR
, compute_mode
, op0
,
3736 build_int_cst (NULL_TREE
, size
- 1, 0),
3740 = force_operand (gen_rtx_MINUS (compute_mode
,
3745 = force_operand (gen_rtx_MINUS (compute_mode
,
3753 if (post_shift
>= BITS_PER_WORD
3754 || size
- 1 >= BITS_PER_WORD
)
3757 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
3758 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
3759 + shift_cost
[compute_mode
][size
- 1]
3760 + 2 * add_cost
[compute_mode
]);
3761 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3763 max_cost
- extra_cost
);
3766 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
3770 (RSHIFT_EXPR
, compute_mode
, t2
,
3771 build_int_cst (NULL_TREE
, post_shift
, 0),
3774 (RSHIFT_EXPR
, compute_mode
, op0
,
3775 build_int_cst (NULL_TREE
, size
- 1, 0),
3779 = force_operand (gen_rtx_MINUS (compute_mode
,
3784 = force_operand (gen_rtx_MINUS (compute_mode
,
3789 else /* Too wide mode to use tricky code */
3792 insn
= get_last_insn ();
3794 && (set
= single_set (insn
)) != 0
3795 && SET_DEST (set
) == quotient
)
3796 set_unique_reg_note (insn
,
3798 gen_rtx_DIV (compute_mode
, op0
, op1
));
3803 delete_insns_since (last
);
3806 case FLOOR_DIV_EXPR
:
3807 case FLOOR_MOD_EXPR
:
3808 /* We will come here only for signed operations. */
3809 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
3811 unsigned HOST_WIDE_INT mh
, ml
;
3812 int pre_shift
, lgup
, post_shift
;
3813 HOST_WIDE_INT d
= INTVAL (op1
);
3817 /* We could just as easily deal with negative constants here,
3818 but it does not seem worth the trouble for GCC 2.6. */
3819 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3821 pre_shift
= floor_log2 (d
);
3824 remainder
= expand_binop (compute_mode
, and_optab
, op0
,
3825 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3826 remainder
, 0, OPTAB_LIB_WIDEN
);
3828 return gen_lowpart (mode
, remainder
);
3830 quotient
= expand_shift
3831 (RSHIFT_EXPR
, compute_mode
, op0
,
3832 build_int_cst (NULL_TREE
, pre_shift
, 0),
3839 mh
= choose_multiplier (d
, size
, size
- 1,
3840 &ml
, &post_shift
, &lgup
);
3844 if (post_shift
< BITS_PER_WORD
3845 && size
- 1 < BITS_PER_WORD
)
3848 (RSHIFT_EXPR
, compute_mode
, op0
,
3849 build_int_cst (NULL_TREE
, size
- 1, 0),
3851 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
3852 NULL_RTX
, 0, OPTAB_WIDEN
);
3853 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
3854 + shift_cost
[compute_mode
][size
- 1]
3855 + 2 * add_cost
[compute_mode
]);
3856 t3
= expand_mult_highpart (compute_mode
, t2
, ml
,
3858 max_cost
- extra_cost
);
3862 (RSHIFT_EXPR
, compute_mode
, t3
,
3863 build_int_cst (NULL_TREE
, post_shift
, 0),
3865 quotient
= expand_binop (compute_mode
, xor_optab
,
3866 t4
, t1
, tquotient
, 0,
3874 rtx nsign
, t1
, t2
, t3
, t4
;
3875 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
3876 op0
, constm1_rtx
), NULL_RTX
);
3877 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
3879 nsign
= expand_shift
3880 (RSHIFT_EXPR
, compute_mode
, t2
,
3881 build_int_cst (NULL_TREE
, size
- 1, 0),
3883 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
3885 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
3890 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
3892 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3901 delete_insns_since (last
);
3903 /* Try using an instruction that produces both the quotient and
3904 remainder, using truncation. We can easily compensate the quotient
3905 or remainder to get floor rounding, once we have the remainder.
3906 Notice that we compute also the final remainder value here,
3907 and return the result right away. */
3908 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3909 target
= gen_reg_rtx (compute_mode
);
3914 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
3915 quotient
= gen_reg_rtx (compute_mode
);
3920 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
3921 remainder
= gen_reg_rtx (compute_mode
);
3924 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
3925 quotient
, remainder
, 0))
3927 /* This could be computed with a branch-less sequence.
3928 Save that for later. */
3930 rtx label
= gen_label_rtx ();
3931 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
3932 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3933 NULL_RTX
, 0, OPTAB_WIDEN
);
3934 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
3935 expand_dec (quotient
, const1_rtx
);
3936 expand_inc (remainder
, op1
);
3938 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3941 /* No luck with division elimination or divmod. Have to do it
3942 by conditionally adjusting op0 *and* the result. */
3944 rtx label1
, label2
, label3
, label4
, label5
;
3948 quotient
= gen_reg_rtx (compute_mode
);
3949 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3950 label1
= gen_label_rtx ();
3951 label2
= gen_label_rtx ();
3952 label3
= gen_label_rtx ();
3953 label4
= gen_label_rtx ();
3954 label5
= gen_label_rtx ();
3955 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
3956 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
3957 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3958 quotient
, 0, OPTAB_LIB_WIDEN
);
3959 if (tem
!= quotient
)
3960 emit_move_insn (quotient
, tem
);
3961 emit_jump_insn (gen_jump (label5
));
3963 emit_label (label1
);
3964 expand_inc (adjusted_op0
, const1_rtx
);
3965 emit_jump_insn (gen_jump (label4
));
3967 emit_label (label2
);
3968 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
3969 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3970 quotient
, 0, OPTAB_LIB_WIDEN
);
3971 if (tem
!= quotient
)
3972 emit_move_insn (quotient
, tem
);
3973 emit_jump_insn (gen_jump (label5
));
3975 emit_label (label3
);
3976 expand_dec (adjusted_op0
, const1_rtx
);
3977 emit_label (label4
);
3978 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3979 quotient
, 0, OPTAB_LIB_WIDEN
);
3980 if (tem
!= quotient
)
3981 emit_move_insn (quotient
, tem
);
3982 expand_dec (quotient
, const1_rtx
);
3983 emit_label (label5
);
3991 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
3994 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3995 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3996 build_int_cst (NULL_TREE
,
3999 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4001 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4002 t3
= gen_reg_rtx (compute_mode
);
4003 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4004 compute_mode
, 1, 1);
4008 lab
= gen_label_rtx ();
4009 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4010 expand_inc (t1
, const1_rtx
);
4015 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4021 /* Try using an instruction that produces both the quotient and
4022 remainder, using truncation. We can easily compensate the
4023 quotient or remainder to get ceiling rounding, once we have the
4024 remainder. Notice that we compute also the final remainder
4025 value here, and return the result right away. */
4026 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4027 target
= gen_reg_rtx (compute_mode
);
4031 remainder
= (REG_P (target
)
4032 ? target
: gen_reg_rtx (compute_mode
));
4033 quotient
= gen_reg_rtx (compute_mode
);
4037 quotient
= (REG_P (target
)
4038 ? target
: gen_reg_rtx (compute_mode
));
4039 remainder
= gen_reg_rtx (compute_mode
);
4042 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
4045 /* This could be computed with a branch-less sequence.
4046 Save that for later. */
4047 rtx label
= gen_label_rtx ();
4048 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4049 compute_mode
, label
);
4050 expand_inc (quotient
, const1_rtx
);
4051 expand_dec (remainder
, op1
);
4053 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4056 /* No luck with division elimination or divmod. Have to do it
4057 by conditionally adjusting op0 *and* the result. */
4060 rtx adjusted_op0
, tem
;
4062 quotient
= gen_reg_rtx (compute_mode
);
4063 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4064 label1
= gen_label_rtx ();
4065 label2
= gen_label_rtx ();
4066 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
4067 compute_mode
, label1
);
4068 emit_move_insn (quotient
, const0_rtx
);
4069 emit_jump_insn (gen_jump (label2
));
4071 emit_label (label1
);
4072 expand_dec (adjusted_op0
, const1_rtx
);
4073 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
4074 quotient
, 1, OPTAB_LIB_WIDEN
);
4075 if (tem
!= quotient
)
4076 emit_move_insn (quotient
, tem
);
4077 expand_inc (quotient
, const1_rtx
);
4078 emit_label (label2
);
4083 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4084 && INTVAL (op1
) >= 0)
4086 /* This is extremely similar to the code for the unsigned case
4087 above. For 2.7 we should merge these variants, but for
4088 2.6.1 I don't want to touch the code for unsigned since that
4089 get used in C. The signed case will only be used by other
4093 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4094 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4095 build_int_cst (NULL_TREE
,
4098 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4100 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4101 t3
= gen_reg_rtx (compute_mode
);
4102 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4103 compute_mode
, 1, 1);
4107 lab
= gen_label_rtx ();
4108 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4109 expand_inc (t1
, const1_rtx
);
4114 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4120 /* Try using an instruction that produces both the quotient and
4121 remainder, using truncation. We can easily compensate the
4122 quotient or remainder to get ceiling rounding, once we have the
4123 remainder. Notice that we compute also the final remainder
4124 value here, and return the result right away. */
4125 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4126 target
= gen_reg_rtx (compute_mode
);
4129 remainder
= (REG_P (target
)
4130 ? target
: gen_reg_rtx (compute_mode
));
4131 quotient
= gen_reg_rtx (compute_mode
);
4135 quotient
= (REG_P (target
)
4136 ? target
: gen_reg_rtx (compute_mode
));
4137 remainder
= gen_reg_rtx (compute_mode
);
4140 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
4143 /* This could be computed with a branch-less sequence.
4144 Save that for later. */
4146 rtx label
= gen_label_rtx ();
4147 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4148 compute_mode
, label
);
4149 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4150 NULL_RTX
, 0, OPTAB_WIDEN
);
4151 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
4152 expand_inc (quotient
, const1_rtx
);
4153 expand_dec (remainder
, op1
);
4155 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4158 /* No luck with division elimination or divmod. Have to do it
4159 by conditionally adjusting op0 *and* the result. */
4161 rtx label1
, label2
, label3
, label4
, label5
;
4165 quotient
= gen_reg_rtx (compute_mode
);
4166 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4167 label1
= gen_label_rtx ();
4168 label2
= gen_label_rtx ();
4169 label3
= gen_label_rtx ();
4170 label4
= gen_label_rtx ();
4171 label5
= gen_label_rtx ();
4172 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4173 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
4174 compute_mode
, label1
);
4175 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4176 quotient
, 0, OPTAB_LIB_WIDEN
);
4177 if (tem
!= quotient
)
4178 emit_move_insn (quotient
, tem
);
4179 emit_jump_insn (gen_jump (label5
));
4181 emit_label (label1
);
4182 expand_dec (adjusted_op0
, const1_rtx
);
4183 emit_jump_insn (gen_jump (label4
));
4185 emit_label (label2
);
4186 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
4187 compute_mode
, label3
);
4188 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4189 quotient
, 0, OPTAB_LIB_WIDEN
);
4190 if (tem
!= quotient
)
4191 emit_move_insn (quotient
, tem
);
4192 emit_jump_insn (gen_jump (label5
));
4194 emit_label (label3
);
4195 expand_inc (adjusted_op0
, const1_rtx
);
4196 emit_label (label4
);
4197 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4198 quotient
, 0, OPTAB_LIB_WIDEN
);
4199 if (tem
!= quotient
)
4200 emit_move_insn (quotient
, tem
);
4201 expand_inc (quotient
, const1_rtx
);
4202 emit_label (label5
);
4207 case EXACT_DIV_EXPR
:
4208 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4210 HOST_WIDE_INT d
= INTVAL (op1
);
4211 unsigned HOST_WIDE_INT ml
;
4215 pre_shift
= floor_log2 (d
& -d
);
4216 ml
= invert_mod2n (d
>> pre_shift
, size
);
4217 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4218 build_int_cst (NULL_TREE
, pre_shift
, 0),
4219 NULL_RTX
, unsignedp
);
4220 quotient
= expand_mult (compute_mode
, t1
,
4221 gen_int_mode (ml
, compute_mode
),
4224 insn
= get_last_insn ();
4225 set_unique_reg_note (insn
,
4227 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
4233 case ROUND_DIV_EXPR
:
4234 case ROUND_MOD_EXPR
:
4239 label
= gen_label_rtx ();
4240 quotient
= gen_reg_rtx (compute_mode
);
4241 remainder
= gen_reg_rtx (compute_mode
);
4242 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
4245 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
4246 quotient
, 1, OPTAB_LIB_WIDEN
);
4247 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
4248 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4249 remainder
, 1, OPTAB_LIB_WIDEN
);
4251 tem
= plus_constant (op1
, -1);
4252 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4253 build_int_cst (NULL_TREE
, 1, 0),
4255 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
4256 expand_inc (quotient
, const1_rtx
);
4257 expand_dec (remainder
, op1
);
4262 rtx abs_rem
, abs_op1
, tem
, mask
;
4264 label
= gen_label_rtx ();
4265 quotient
= gen_reg_rtx (compute_mode
);
4266 remainder
= gen_reg_rtx (compute_mode
);
4267 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
4270 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
4271 quotient
, 0, OPTAB_LIB_WIDEN
);
4272 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
4273 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4274 remainder
, 0, OPTAB_LIB_WIDEN
);
4276 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
4277 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
4278 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
4279 build_int_cst (NULL_TREE
, 1, 0),
4281 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
4282 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4283 NULL_RTX
, 0, OPTAB_WIDEN
);
4284 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4285 build_int_cst (NULL_TREE
, size
- 1, 0),
4287 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
4288 NULL_RTX
, 0, OPTAB_WIDEN
);
4289 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4290 NULL_RTX
, 0, OPTAB_WIDEN
);
4291 expand_inc (quotient
, tem
);
4292 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
4293 NULL_RTX
, 0, OPTAB_WIDEN
);
4294 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4295 NULL_RTX
, 0, OPTAB_WIDEN
);
4296 expand_dec (remainder
, tem
);
4299 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4307 if (target
&& GET_MODE (target
) != compute_mode
)
4312 /* Try to produce the remainder without producing the quotient.
4313 If we seem to have a divmod pattern that does not require widening,
4314 don't try widening here. We should really have a WIDEN argument
4315 to expand_twoval_binop, since what we'd really like to do here is
4316 1) try a mod insn in compute_mode
4317 2) try a divmod insn in compute_mode
4318 3) try a div insn in compute_mode and multiply-subtract to get
4320 4) try the same things with widening allowed. */
4322 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4325 ((optab2
->handlers
[compute_mode
].insn_code
4326 != CODE_FOR_nothing
)
4327 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4330 /* No luck there. Can we do remainder and divide at once
4331 without a library call? */
4332 remainder
= gen_reg_rtx (compute_mode
);
4333 if (! expand_twoval_binop ((unsignedp
4337 NULL_RTX
, remainder
, unsignedp
))
4342 return gen_lowpart (mode
, remainder
);
4345 /* Produce the quotient. Try a quotient insn, but not a library call.
4346 If we have a divmod in this mode, use it in preference to widening
4347 the div (for this test we assume it will not fail). Note that optab2
4348 is set to the one of the two optabs that the call below will use. */
4350 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
4351 op0
, op1
, rem_flag
? NULL_RTX
: target
,
4353 ((optab2
->handlers
[compute_mode
].insn_code
4354 != CODE_FOR_nothing
)
4355 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4359 /* No luck there. Try a quotient-and-remainder insn,
4360 keeping the quotient alone. */
4361 quotient
= gen_reg_rtx (compute_mode
);
4362 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
4364 quotient
, NULL_RTX
, unsignedp
))
4368 /* Still no luck. If we are not computing the remainder,
4369 use a library call for the quotient. */
4370 quotient
= sign_expand_binop (compute_mode
,
4371 udiv_optab
, sdiv_optab
,
4373 unsignedp
, OPTAB_LIB_WIDEN
);
4380 if (target
&& GET_MODE (target
) != compute_mode
)
4385 /* No divide instruction either. Use library for remainder. */
4386 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4388 unsignedp
, OPTAB_LIB_WIDEN
);
4389 /* No remainder function. Try a quotient-and-remainder
4390 function, keeping the remainder. */
4393 remainder
= gen_reg_rtx (compute_mode
);
4394 if (!expand_twoval_binop_libfunc
4395 (unsignedp
? udivmod_optab
: sdivmod_optab
,
4397 NULL_RTX
, remainder
,
4398 unsignedp
? UMOD
: MOD
))
4399 remainder
= NULL_RTX
;
4404 /* We divided. Now finish doing X - Y * (X / Y). */
4405 remainder
= expand_mult (compute_mode
, quotient
, op1
,
4406 NULL_RTX
, unsignedp
);
4407 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
4408 remainder
, target
, unsignedp
,
4413 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4416 /* Return a tree node with data type TYPE, describing the value of X.
4417 Usually this is an VAR_DECL, if there is no obvious better choice.
4418 X may be an expression, however we only support those expressions
4419 generated by loop.c. */
4422 make_tree (tree type
, rtx x
)
4426 switch (GET_CODE (x
))
4430 HOST_WIDE_INT hi
= 0;
4433 && !(TYPE_UNSIGNED (type
)
4434 && (GET_MODE_BITSIZE (TYPE_MODE (type
))
4435 < HOST_BITS_PER_WIDE_INT
)))
4438 t
= build_int_cst (type
, INTVAL (x
), hi
);
4444 if (GET_MODE (x
) == VOIDmode
)
4445 t
= build_int_cst (type
, CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
4450 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4451 t
= build_real (type
, d
);
4462 units
= CONST_VECTOR_NUNITS (x
);
4464 /* Build a tree with vector elements. */
4465 for (i
= units
- 1; i
>= 0; --i
)
4467 elt
= CONST_VECTOR_ELT (x
, i
);
4468 t
= tree_cons (NULL_TREE
, make_tree (type
, elt
), t
);
4471 return build_vector (type
, t
);
4475 return fold (build2 (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4476 make_tree (type
, XEXP (x
, 1))));
4479 return fold (build2 (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4480 make_tree (type
, XEXP (x
, 1))));
4483 return fold (build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0))));
4486 return fold (build2 (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4487 make_tree (type
, XEXP (x
, 1))));
4490 return fold (build2 (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4491 make_tree (type
, XEXP (x
, 1))));
4494 t
= lang_hooks
.types
.unsigned_type (type
);
4495 return fold (convert (type
,
4496 build2 (RSHIFT_EXPR
, t
,
4497 make_tree (t
, XEXP (x
, 0)),
4498 make_tree (type
, XEXP (x
, 1)))));
4501 t
= lang_hooks
.types
.signed_type (type
);
4502 return fold (convert (type
,
4503 build2 (RSHIFT_EXPR
, t
,
4504 make_tree (t
, XEXP (x
, 0)),
4505 make_tree (type
, XEXP (x
, 1)))));
4508 if (TREE_CODE (type
) != REAL_TYPE
)
4509 t
= lang_hooks
.types
.signed_type (type
);
4513 return fold (convert (type
,
4514 build2 (TRUNC_DIV_EXPR
, t
,
4515 make_tree (t
, XEXP (x
, 0)),
4516 make_tree (t
, XEXP (x
, 1)))));
4518 t
= lang_hooks
.types
.unsigned_type (type
);
4519 return fold (convert (type
,
4520 build2 (TRUNC_DIV_EXPR
, t
,
4521 make_tree (t
, XEXP (x
, 0)),
4522 make_tree (t
, XEXP (x
, 1)))));
4526 t
= lang_hooks
.types
.type_for_mode (GET_MODE (XEXP (x
, 0)),
4527 GET_CODE (x
) == ZERO_EXTEND
);
4528 return fold (convert (type
, make_tree (t
, XEXP (x
, 0))));
4531 t
= build_decl (VAR_DECL
, NULL_TREE
, type
);
4533 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4534 ptr_mode. So convert. */
4535 if (POINTER_TYPE_P (type
))
4536 x
= convert_memory_address (TYPE_MODE (type
), x
);
4538 /* Note that we do *not* use SET_DECL_RTL here, because we do not
4539 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
4546 /* Check whether the multiplication X * MULT + ADD overflows.
4547 X, MULT and ADD must be CONST_*.
4548 MODE is the machine mode for the computation.
4549 X and MULT must have mode MODE. ADD may have a different mode.
4550 So can X (defaults to same as MODE).
4551 UNSIGNEDP is nonzero to do unsigned multiplication. */
4554 const_mult_add_overflow_p (rtx x
, rtx mult
, rtx add
, enum machine_mode mode
, int unsignedp
)
4556 tree type
, mult_type
, add_type
, result
;
4558 type
= lang_hooks
.types
.type_for_mode (mode
, unsignedp
);
4560 /* In order to get a proper overflow indication from an unsigned
4561 type, we have to pretend that it's a sizetype. */
4565 mult_type
= copy_node (type
);
4566 TYPE_IS_SIZETYPE (mult_type
) = 1;
4569 add_type
= (GET_MODE (add
) == VOIDmode
? mult_type
4570 : lang_hooks
.types
.type_for_mode (GET_MODE (add
), unsignedp
));
4572 result
= fold (build2 (PLUS_EXPR
, mult_type
,
4573 fold (build2 (MULT_EXPR
, mult_type
,
4574 make_tree (mult_type
, x
),
4575 make_tree (mult_type
, mult
))),
4576 make_tree (add_type
, add
)));
4578 return TREE_CONSTANT_OVERFLOW (result
);
4581 /* Return an rtx representing the value of X * MULT + ADD.
4582 TARGET is a suggestion for where to store the result (an rtx).
4583 MODE is the machine mode for the computation.
4584 X and MULT must have mode MODE. ADD may have a different mode.
4585 So can X (defaults to same as MODE).
4586 UNSIGNEDP is nonzero to do unsigned multiplication.
4587 This may emit insns. */
4590 expand_mult_add (rtx x
, rtx target
, rtx mult
, rtx add
, enum machine_mode mode
,
4593 tree type
= lang_hooks
.types
.type_for_mode (mode
, unsignedp
);
4594 tree add_type
= (GET_MODE (add
) == VOIDmode
4595 ? type
: lang_hooks
.types
.type_for_mode (GET_MODE (add
),
4597 tree result
= fold (build2 (PLUS_EXPR
, type
,
4598 fold (build2 (MULT_EXPR
, type
,
4599 make_tree (type
, x
),
4600 make_tree (type
, mult
))),
4601 make_tree (add_type
, add
)));
4603 return expand_expr (result
, target
, VOIDmode
, 0);
4606 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4607 and returning TARGET.
4609 If TARGET is 0, a pseudo-register or constant is returned. */
4612 expand_and (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
)
4616 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
4617 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
4619 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
4623 else if (tem
!= target
)
4624 emit_move_insn (target
, tem
);
4628 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4629 and storing in TARGET. Normally return TARGET.
4630 Return 0 if that cannot be done.
4632 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4633 it is VOIDmode, they cannot both be CONST_INT.
4635 UNSIGNEDP is for the case where we have to widen the operands
4636 to perform the operation. It says to use zero-extension.
4638 NORMALIZEP is 1 if we should convert the result to be either zero
4639 or one. Normalize is -1 if we should convert the result to be
4640 either zero or -1. If NORMALIZEP is zero, the result will be left
4641 "raw" out of the scc insn. */
4644 emit_store_flag (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4645 enum machine_mode mode
, int unsignedp
, int normalizep
)
4648 enum insn_code icode
;
4649 enum machine_mode compare_mode
;
4650 enum machine_mode target_mode
= GET_MODE (target
);
4652 rtx last
= get_last_insn ();
4653 rtx pattern
, comparison
;
4656 code
= unsigned_condition (code
);
4658 /* If one operand is constant, make it the second one. Only do this
4659 if the other operand is not constant as well. */
4661 if (swap_commutative_operands_p (op0
, op1
))
4666 code
= swap_condition (code
);
4669 if (mode
== VOIDmode
)
4670 mode
= GET_MODE (op0
);
4672 /* For some comparisons with 1 and -1, we can convert this to
4673 comparisons with zero. This will often produce more opportunities for
4674 store-flag insns. */
4679 if (op1
== const1_rtx
)
4680 op1
= const0_rtx
, code
= LE
;
4683 if (op1
== constm1_rtx
)
4684 op1
= const0_rtx
, code
= LT
;
4687 if (op1
== const1_rtx
)
4688 op1
= const0_rtx
, code
= GT
;
4691 if (op1
== constm1_rtx
)
4692 op1
= const0_rtx
, code
= GE
;
4695 if (op1
== const1_rtx
)
4696 op1
= const0_rtx
, code
= NE
;
4699 if (op1
== const1_rtx
)
4700 op1
= const0_rtx
, code
= EQ
;
4706 /* If we are comparing a double-word integer with zero or -1, we can
4707 convert the comparison into one involving a single word. */
4708 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
4709 && GET_MODE_CLASS (mode
) == MODE_INT
4710 && (!MEM_P (op0
) || ! MEM_VOLATILE_P (op0
)))
4712 if ((code
== EQ
|| code
== NE
)
4713 && (op1
== const0_rtx
|| op1
== constm1_rtx
))
4715 rtx op00
, op01
, op0both
;
4717 /* Do a logical OR or AND of the two words and compare the result. */
4718 op00
= simplify_gen_subreg (word_mode
, op0
, mode
, 0);
4719 op01
= simplify_gen_subreg (word_mode
, op0
, mode
, UNITS_PER_WORD
);
4720 op0both
= expand_binop (word_mode
,
4721 op1
== const0_rtx
? ior_optab
: and_optab
,
4722 op00
, op01
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
4725 return emit_store_flag (target
, code
, op0both
, op1
, word_mode
,
4726 unsignedp
, normalizep
);
4728 else if ((code
== LT
|| code
== GE
) && op1
== const0_rtx
)
4732 /* If testing the sign bit, can just test on high word. */
4733 op0h
= simplify_gen_subreg (word_mode
, op0
, mode
,
4734 subreg_highpart_offset (word_mode
, mode
));
4735 return emit_store_flag (target
, code
, op0h
, op1
, word_mode
,
4736 unsignedp
, normalizep
);
4740 /* From now on, we won't change CODE, so set ICODE now. */
4741 icode
= setcc_gen_code
[(int) code
];
4743 /* If this is A < 0 or A >= 0, we can do this by taking the ones
4744 complement of A (for GE) and shifting the sign bit to the low bit. */
4745 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
4746 && GET_MODE_CLASS (mode
) == MODE_INT
4747 && (normalizep
|| STORE_FLAG_VALUE
== 1
4748 || (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4749 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4750 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))))
4754 /* If the result is to be wider than OP0, it is best to convert it
4755 first. If it is to be narrower, it is *incorrect* to convert it
4757 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
4759 op0
= convert_modes (target_mode
, mode
, op0
, 0);
4763 if (target_mode
!= mode
)
4767 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
4768 ((STORE_FLAG_VALUE
== 1 || normalizep
)
4769 ? 0 : subtarget
), 0);
4771 if (STORE_FLAG_VALUE
== 1 || normalizep
)
4772 /* If we are supposed to produce a 0/1 value, we want to do
4773 a logical shift from the sign bit to the low-order bit; for
4774 a -1/0 value, we do an arithmetic shift. */
4775 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
4776 size_int (GET_MODE_BITSIZE (mode
) - 1),
4777 subtarget
, normalizep
!= -1);
4779 if (mode
!= target_mode
)
4780 op0
= convert_modes (target_mode
, mode
, op0
, 0);
4785 if (icode
!= CODE_FOR_nothing
)
4787 insn_operand_predicate_fn pred
;
4789 /* We think we may be able to do this with a scc insn. Emit the
4790 comparison and then the scc insn. */
4792 do_pending_stack_adjust ();
4793 last
= get_last_insn ();
4796 = compare_from_rtx (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
);
4797 if (CONSTANT_P (comparison
))
4799 if (GET_CODE (comparison
) == CONST_INT
)
4801 if (comparison
== const0_rtx
)
4804 #ifdef FLOAT_STORE_FLAG_VALUE
4805 else if (GET_CODE (comparison
) == CONST_DOUBLE
)
4807 if (comparison
== CONST0_RTX (GET_MODE (comparison
)))
4813 if (normalizep
== 1)
4815 if (normalizep
== -1)
4817 return const_true_rtx
;
4820 /* The code of COMPARISON may not match CODE if compare_from_rtx
4821 decided to swap its operands and reverse the original code.
4823 We know that compare_from_rtx returns either a CONST_INT or
4824 a new comparison code, so it is safe to just extract the
4825 code from COMPARISON. */
4826 code
= GET_CODE (comparison
);
4828 /* Get a reference to the target in the proper mode for this insn. */
4829 compare_mode
= insn_data
[(int) icode
].operand
[0].mode
;
4831 pred
= insn_data
[(int) icode
].operand
[0].predicate
;
4832 if (preserve_subexpressions_p ()
4833 || ! (*pred
) (subtarget
, compare_mode
))
4834 subtarget
= gen_reg_rtx (compare_mode
);
4836 pattern
= GEN_FCN (icode
) (subtarget
);
4839 emit_insn (pattern
);
4841 /* If we are converting to a wider mode, first convert to
4842 TARGET_MODE, then normalize. This produces better combining
4843 opportunities on machines that have a SIGN_EXTRACT when we are
4844 testing a single bit. This mostly benefits the 68k.
4846 If STORE_FLAG_VALUE does not have the sign bit set when
4847 interpreted in COMPARE_MODE, we can do this conversion as
4848 unsigned, which is usually more efficient. */
4849 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (compare_mode
))
4851 convert_move (target
, subtarget
,
4852 (GET_MODE_BITSIZE (compare_mode
)
4853 <= HOST_BITS_PER_WIDE_INT
)
4854 && 0 == (STORE_FLAG_VALUE
4855 & ((HOST_WIDE_INT
) 1
4856 << (GET_MODE_BITSIZE (compare_mode
) -1))));
4858 compare_mode
= target_mode
;
4863 /* If we want to keep subexpressions around, don't reuse our
4866 if (preserve_subexpressions_p ())
4869 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4870 we don't have to do anything. */
4871 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
4873 /* STORE_FLAG_VALUE might be the most negative number, so write
4874 the comparison this way to avoid a compiler-time warning. */
4875 else if (- normalizep
== STORE_FLAG_VALUE
)
4876 op0
= expand_unop (compare_mode
, neg_optab
, op0
, subtarget
, 0);
4878 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4879 makes it hard to use a value of just the sign bit due to
4880 ANSI integer constant typing rules. */
4881 else if (GET_MODE_BITSIZE (compare_mode
) <= HOST_BITS_PER_WIDE_INT
4882 && (STORE_FLAG_VALUE
4883 & ((HOST_WIDE_INT
) 1
4884 << (GET_MODE_BITSIZE (compare_mode
) - 1))))
4885 op0
= expand_shift (RSHIFT_EXPR
, compare_mode
, op0
,
4886 size_int (GET_MODE_BITSIZE (compare_mode
) - 1),
4887 subtarget
, normalizep
== 1);
4888 else if (STORE_FLAG_VALUE
& 1)
4890 op0
= expand_and (compare_mode
, op0
, const1_rtx
, subtarget
);
4891 if (normalizep
== -1)
4892 op0
= expand_unop (compare_mode
, neg_optab
, op0
, op0
, 0);
4897 /* If we were converting to a smaller mode, do the
4899 if (target_mode
!= compare_mode
)
4901 convert_move (target
, op0
, 0);
4909 delete_insns_since (last
);
4911 /* If expensive optimizations, use different pseudo registers for each
4912 insn, instead of reusing the same pseudo. This leads to better CSE,
4913 but slows down the compiler, since there are more pseudos */
4914 subtarget
= (!flag_expensive_optimizations
4915 && (target_mode
== mode
)) ? target
: NULL_RTX
;
4917 /* If we reached here, we can't do this with a scc insn. However, there
4918 are some comparisons that can be done directly. For example, if
4919 this is an equality comparison of integers, we can try to exclusive-or
4920 (or subtract) the two operands and use a recursive call to try the
4921 comparison with zero. Don't do any of these cases if branches are
4925 && GET_MODE_CLASS (mode
) == MODE_INT
&& (code
== EQ
|| code
== NE
)
4926 && op1
!= const0_rtx
)
4928 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
4932 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
4935 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
4936 mode
, unsignedp
, normalizep
);
4938 delete_insns_since (last
);
4942 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4943 the constant zero. Reject all other comparisons at this point. Only
4944 do LE and GT if branches are expensive since they are expensive on
4945 2-operand machines. */
4947 if (BRANCH_COST
== 0
4948 || GET_MODE_CLASS (mode
) != MODE_INT
|| op1
!= const0_rtx
4949 || (code
!= EQ
&& code
!= NE
4950 && (BRANCH_COST
<= 1 || (code
!= LE
&& code
!= GT
))))
4953 /* See what we need to return. We can only return a 1, -1, or the
4956 if (normalizep
== 0)
4958 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4959 normalizep
= STORE_FLAG_VALUE
;
4961 else if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4962 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4963 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))
4969 /* Try to put the result of the comparison in the sign bit. Assume we can't
4970 do the necessary operation below. */
4974 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4975 the sign bit set. */
4979 /* This is destructive, so SUBTARGET can't be OP0. */
4980 if (rtx_equal_p (subtarget
, op0
))
4983 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
4986 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
4990 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4991 number of bits in the mode of OP0, minus one. */
4995 if (rtx_equal_p (subtarget
, op0
))
4998 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
4999 size_int (GET_MODE_BITSIZE (mode
) - 1),
5001 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
5005 if (code
== EQ
|| code
== NE
)
5007 /* For EQ or NE, one way to do the comparison is to apply an operation
5008 that converts the operand into a positive number if it is nonzero
5009 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5010 for NE we negate. This puts the result in the sign bit. Then we
5011 normalize with a shift, if needed.
5013 Two operations that can do the above actions are ABS and FFS, so try
5014 them. If that doesn't work, and MODE is smaller than a full word,
5015 we can use zero-extension to the wider mode (an unsigned conversion)
5016 as the operation. */
5018 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5019 that is compensated by the subsequent overflow when subtracting
5022 if (abs_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
)
5023 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
5024 else if (ffs_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
)
5025 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
5026 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5028 tem
= convert_modes (word_mode
, mode
, op0
, 1);
5035 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
5038 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
5041 /* If we couldn't do it that way, for NE we can "or" the two's complement
5042 of the value with itself. For EQ, we take the one's complement of
5043 that "or", which is an extra insn, so we only handle EQ if branches
5046 if (tem
== 0 && (code
== NE
|| BRANCH_COST
> 1))
5048 if (rtx_equal_p (subtarget
, op0
))
5051 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
5052 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
5055 if (tem
&& code
== EQ
)
5056 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
5060 if (tem
&& normalizep
)
5061 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
5062 size_int (GET_MODE_BITSIZE (mode
) - 1),
5063 subtarget
, normalizep
== 1);
5067 if (GET_MODE (tem
) != target_mode
)
5069 convert_move (target
, tem
, 0);
5072 else if (!subtarget
)
5074 emit_move_insn (target
, tem
);
5079 delete_insns_since (last
);
5084 /* Like emit_store_flag, but always succeeds. */
5087 emit_store_flag_force (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5088 enum machine_mode mode
, int unsignedp
, int normalizep
)
5092 /* First see if emit_store_flag can do the job. */
5093 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
5097 if (normalizep
== 0)
5100 /* If this failed, we have to do this with set/compare/jump/set code. */
5103 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
5104 target
= gen_reg_rtx (GET_MODE (target
));
5106 emit_move_insn (target
, const1_rtx
);
5107 label
= gen_label_rtx ();
5108 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
,
5111 emit_move_insn (target
, const0_rtx
);
5117 /* Perform possibly multi-word comparison and conditional jump to LABEL
5118 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
5120 The algorithm is based on the code in expr.c:do_jump.
5122 Note that this does not perform a general comparison. Only variants
5123 generated within expmed.c are correctly handled, others abort (but could
5124 be handled if needed). */
5127 do_cmp_and_jump (rtx arg1
, rtx arg2
, enum rtx_code op
, enum machine_mode mode
,
5130 /* If this mode is an integer too wide to compare properly,
5131 compare word by word. Rely on cse to optimize constant cases. */
5133 if (GET_MODE_CLASS (mode
) == MODE_INT
5134 && ! can_compare_p (op
, mode
, ccp_jump
))
5136 rtx label2
= gen_label_rtx ();
5141 do_jump_by_parts_greater_rtx (mode
, 1, arg2
, arg1
, label2
, label
);
5145 do_jump_by_parts_greater_rtx (mode
, 1, arg1
, arg2
, label
, label2
);
5149 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label2
, label
);
5153 do_jump_by_parts_greater_rtx (mode
, 0, arg1
, arg2
, label2
, label
);
5157 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label
, label2
);
5160 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
5161 that's the only equality operations we do */
5163 if (arg2
!= const0_rtx
|| mode
!= GET_MODE(arg1
))
5165 do_jump_by_parts_equality_rtx (arg1
, label2
, label
);
5169 if (arg2
!= const0_rtx
|| mode
!= GET_MODE(arg1
))
5171 do_jump_by_parts_equality_rtx (arg1
, label
, label2
);
5178 emit_label (label2
);
5181 emit_cmp_and_jump_insns (arg1
, arg2
, op
, NULL_RTX
, mode
, 0, label
);