gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_notes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 \f
 127 /* Vector mapping INSN_UIDs to cuids.
 128    The cuids are like uids but increase monotonically always.
 129    Combine always uses cuids so that it can compare them.
 130    But actually renumbering the uids, which we used to do,
 131    proves to be a bad idea because it makes it hard to compare
 132    the dumps produced by earlier passes with those from later passes.  */
 133
 134 static int *uid_cuid;
 135 static int max_uid_cuid;
 136
 137 /* Get the cuid of an insn.  */
 138
 139 #define INSN_CUID(INSN) \
 140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 141
 142 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
 143    BITS_PER_WORD would invoke undefined behavior.  Work around it.  */
 144
 145 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
 146   (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
 147
 148 /* Maximum register number, which is the size of the tables below.  */
 149
 150 static unsigned int combine_max_regno;
 151
 152 struct reg_stat {
 153   /* Record last point of death of (hard or pseudo) register n.  */
 154   rtx                           last_death;
 155
 156   /* Record last point of modification of (hard or pseudo) register n.  */
 157   rtx                           last_set;
 158
 159   /* The next group of fields allows the recording of the last value assigned
 160      to (hard or pseudo) register n.  We use this information to see if an
 161      operation being processed is redundant given a prior operation performed
 162      on the register.  For example, an `and' with a constant is redundant if
 163      all the zero bits are already known to be turned off.
 164
 165      We use an approach similar to that used by cse, but change it in the
 166      following ways:
 167
 168      (1) We do not want to reinitialize at each label.
 169      (2) It is useful, but not critical, to know the actual value assigned
 170          to a register.  Often just its form is helpful.
 171
 172      Therefore, we maintain the following fields:
 173
 174      last_set_value             the last value assigned
 175      last_set_label             records the value of label_tick when the
 176                                 register was assigned
 177      last_set_table_tick        records the value of label_tick when a
 178                                 value using the register is assigned
 179      last_set_invalid           set to nonzero when it is not valid
 180                                 to use the value of this register in some
 181                                 register's value
 182
 183      To understand the usage of these tables, it is important to understand
 184      the distinction between the value in last_set_value being valid and
 185      the register being validly contained in some other expression in the
 186      table.
 187
 188      (The next two parameters are out of date).
 189
 190      reg_stat[i].last_set_value is valid if it is nonzero, and either
 191      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 192
 193      Register I may validly appear in any expression returned for the value
 194      of another register if reg_n_sets[i] is 1.  It may also appear in the
 195      value for register J if reg_stat[j].last_set_invalid is zero, or
 196      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 197
 198      If an expression is found in the table containing a register which may
 199      not validly appear in an expression, the register is replaced by
 200      something that won't match, (clobber (const_int 0)).  */
 201
 202   /* Record last value assigned to (hard or pseudo) register n.  */
 203
 204   rtx                           last_set_value;
 205
 206   /* Record the value of label_tick when an expression involving register n
 207      is placed in last_set_value.  */
 208
 209   int                           last_set_table_tick;
 210
 211   /* Record the value of label_tick when the value for register n is placed in
 212      last_set_value.  */
 213
 214   int                           last_set_label;
 215
 216   /* These fields are maintained in parallel with last_set_value and are
 217      used to store the mode in which the register was last set, the bits
 218      that were known to be zero when it was last set, and the number of
 219      sign bits copies it was known to have when it was last set.  */
 220
 221   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 222   char                          last_set_sign_bit_copies;
 223   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 224
 225   /* Set nonzero if references to register n in expressions should not be
 226      used.  last_set_invalid is set nonzero when this register is being
 227      assigned to and last_set_table_tick == label_tick.  */
 228
 229   char                          last_set_invalid;
 230
 231   /* Some registers that are set more than once and used in more than one
 232      basic block are nevertheless always set in similar ways.  For example,
 233      a QImode register may be loaded from memory in two places on a machine
 234      where byte loads zero extend.
 235
 236      We record in the following fields if a register has some leading bits
 237      that are always equal to the sign bit, and what we know about the
 238      nonzero bits of a register, specifically which bits are known to be
 239      zero.
 240
 241      If an entry is zero, it means that we don't know anything special.  */
 242
 243   unsigned char                 sign_bit_copies;
 244
 245   unsigned HOST_WIDE_INT        nonzero_bits;
 246
 247   /* Record the value of the label_tick when the last truncation
 248      happened.  The field truncated_to_mode is only valid if
 249      truncation_label == label_tick.  */
 250
 251   int                           truncation_label;
 252
 253   /* Record the last truncation seen for this register.  If truncation
 254      is not a nop to this mode we might be able to save an explicit
 255      truncation if we know that value already contains a truncated
 256      value.  */
 257
 258   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 259 };
 260
 261 static struct reg_stat *reg_stat;
 262
 263 /* Record the cuid of the last insn that invalidated memory
 264    (anything that writes memory, and subroutine calls, but not pushes).  */
 265
 266 static int mem_last_set;
 267
 268 /* Record the cuid of the last CALL_INSN
 269    so we can tell whether a potential combination crosses any calls.  */
 270
 271 static int last_call_cuid;
 272
 273 /* When `subst' is called, this is the insn that is being modified
 274    (by combining in a previous insn).  The PATTERN of this insn
 275    is still the old pattern partially modified and it should not be
 276    looked at, but this may be used to examine the successors of the insn
 277    to judge whether a simplification is valid.  */
 278
 279 static rtx subst_insn;
 280
 281 /* This is the lowest CUID that `subst' is currently dealing with.
 282    get_last_value will not return a value if the register was set at or
 283    after this CUID.  If not for this mechanism, we could get confused if
 284    I2 or I1 in try_combine were an insn that used the old value of a register
 285    to obtain a new value.  In that case, we might erroneously get the
 286    new value of the register when we wanted the old one.  */
 287
 288 static int subst_low_cuid;
 289
 290 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 291    must consider all these registers to be always live.  */
 292
 293 static HARD_REG_SET newpat_used_regs;
 294
 295 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 296    insn is the earlier than I2 or I3, combine should rescan starting at
 297    that location.  */
 298
 299 static rtx added_links_insn;
 300
 301 /* Basic block in which we are performing combines.  */
 302 static basic_block this_basic_block;
 303
 304 /* A bitmap indicating which blocks had registers go dead at entry.
 305    After combine, we'll need to re-do global life analysis with
 306    those blocks as starting points.  */
 307 static sbitmap refresh_blocks;
 308 \f
 309 /* The following array records the insn_rtx_cost for every insn
 310    in the instruction stream.  */
 311
 312 static int *uid_insn_cost;
 313
 314 /* Length of the currently allocated uid_insn_cost array.  */
 315
 316 static int last_insn_cost;
 317
 318 /* Incremented for each label.  */
 319
 320 static int label_tick;
 321
 322 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 323    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 324
 325 static enum machine_mode nonzero_bits_mode;
 326
 327 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 328    be safely used.  It is zero while computing them and after combine has
 329    completed.  This former test prevents propagating values based on
 330    previously set values, which can be incorrect if a variable is modified
 331    in a loop.  */
 332
 333 static int nonzero_sign_valid;
 334
 335 \f
 336 /* Record one modification to rtl structure
 337    to be undone by storing old_contents into *where.  */
 338
 339 struct undo
 340 {
 341   struct undo *next;
 342   enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
 343   union { rtx r; int i; enum machine_mode m; } old_contents;
 344   union { rtx *r; int *i; } where;
 345 };
 346
 347 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 348    num_undo says how many are currently recorded.
 349
 350    other_insn is nonzero if we have modified some other insn in the process
 351    of working on subst_insn.  It must be verified too.  */
 352
 353 struct undobuf
 354 {
 355   struct undo *undos;
 356   struct undo *frees;
 357   rtx other_insn;
 358 };
 359
 360 static struct undobuf undobuf;
 361
 362 /* Number of times the pseudo being substituted for
 363    was found and replaced.  */
 364
 365 static int n_occurrences;
 366
 367 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 368                                          enum machine_mode,
 369                                          unsigned HOST_WIDE_INT,
 370                                          unsigned HOST_WIDE_INT *);
 371 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 372                                                 enum machine_mode,
 373                                                 unsigned int, unsigned int *);
 374 static void do_SUBST (rtx *, rtx);
 375 static void do_SUBST_INT (int *, int);
 376 static void init_reg_last (void);
 377 static void setup_incoming_promotions (void);
 378 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 379 static int cant_combine_insn_p (rtx);
 380 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 381 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 382 static int contains_muldiv (rtx);
 383 static rtx try_combine (rtx, rtx, rtx, int *);
 384 static void undo_all (void);
 385 static void undo_commit (void);
 386 static rtx *find_split_point (rtx *, rtx);
 387 static rtx subst (rtx, rtx, rtx, int, int);
 388 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 389 static rtx simplify_if_then_else (rtx);
 390 static rtx simplify_set (rtx);
 391 static rtx simplify_logical (rtx);
 392 static rtx expand_compound_operation (rtx);
 393 static rtx expand_field_assignment (rtx);
 394 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 395                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 396 static rtx extract_left_shift (rtx, int);
 397 static rtx make_compound_operation (rtx, enum rtx_code);
 398 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 399                               unsigned HOST_WIDE_INT *);
 400 static rtx canon_reg_for_combine (rtx, rtx);
 401 static rtx force_to_mode (rtx, enum machine_mode,
 402                           unsigned HOST_WIDE_INT, int);
 403 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 404 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 405 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 406 static rtx make_field_assignment (rtx);
 407 static rtx apply_distributive_law (rtx);
 408 static rtx distribute_and_simplify_rtx (rtx, int);
 409 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 410                                      unsigned HOST_WIDE_INT);
 411 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 412                                    unsigned HOST_WIDE_INT);
 413 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 414                             HOST_WIDE_INT, enum machine_mode, int *);
 415 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 416 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 417                                  int);
 418 static int recog_for_combine (rtx *, rtx, rtx *);
 419 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 420 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 421 static void update_table_tick (rtx);
 422 static void record_value_for_reg (rtx, rtx, rtx);
 423 static void check_conversions (rtx, rtx);
 424 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 425 static void record_dead_and_set_regs (rtx);
 426 static int get_last_value_validate (rtx *, rtx, int, int);
 427 static rtx get_last_value (rtx);
 428 static int use_crosses_set_p (rtx, int);
 429 static void reg_dead_at_p_1 (rtx, rtx, void *);
 430 static int reg_dead_at_p (rtx, rtx);
 431 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 432 static int reg_bitfield_target_p (rtx, rtx);
 433 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 434 static void distribute_links (rtx);
 435 static void mark_used_regs_combine (rtx);
 436 static int insn_cuid (rtx);
 437 static void record_promoted_value (rtx, rtx);
 438 static int unmentioned_reg_p_1 (rtx *, void *);
 439 static bool unmentioned_reg_p (rtx, rtx);
 440 static void record_truncated_value (rtx);
 441 static bool reg_truncated_to_mode (enum machine_mode, rtx);
 442 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 443 \f
 444
 445 /* It is not safe to use ordinary gen_lowpart in combine.
 446    See comments in gen_lowpart_for_combine.  */
 447 #undef RTL_HOOKS_GEN_LOWPART
 448 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 449
 450 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 451 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 452 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 453
 454 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 455 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 456
 457 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 458 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 459
 460 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 461 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 462
 463 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 464
 465 \f
 466 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 467    insn.  The substitution can be undone by undo_all.  If INTO is already
 468    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 469    also call SUBST, we have to compute it before we put anything into
 470    the undo table.  */
 471
 472 static void
 473 do_SUBST (rtx *into, rtx newval)
 474 {
 475   struct undo *buf;
 476   rtx oldval = *into;
 477
 478   if (oldval == newval)
 479     return;
 480
 481   /* We'd like to catch as many invalid transformations here as
 482      possible.  Unfortunately, there are way too many mode changes
 483      that are perfectly valid, so we'd waste too much effort for
 484      little gain doing the checks here.  Focus on catching invalid
 485      transformations involving integer constants.  */
 486   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 487       && GET_CODE (newval) == CONST_INT)
 488     {
 489       /* Sanity check that we're replacing oldval with a CONST_INT
 490          that is a valid sign-extension for the original mode.  */
 491       gcc_assert (INTVAL (newval)
 492                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 493
 494       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 495          CONST_INT is not valid, because after the replacement, the
 496          original mode would be gone.  Unfortunately, we can't tell
 497          when do_SUBST is called to replace the operand thereof, so we
 498          perform this test on oldval instead, checking whether an
 499          invalid replacement took place before we got here.  */
 500       gcc_assert (!(GET_CODE (oldval) == SUBREG
 501                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 502       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 503                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 504     }
 505
 506   if (undobuf.frees)
 507     buf = undobuf.frees, undobuf.frees = buf->next;
 508   else
 509     buf = XNEW (struct undo);
 510
 511   buf->kind = UNDO_RTX;
 512   buf->where.r = into;
 513   buf->old_contents.r = oldval;
 514   *into = newval;
 515
 516   buf->next = undobuf.undos, undobuf.undos = buf;
 517 }
 518
 519 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 520
 521 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 522    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 523    not safe.  */
 524
 525 static void
 526 do_SUBST_INT (int *into, int newval)
 527 {
 528   struct undo *buf;
 529   int oldval = *into;
 530
 531   if (oldval == newval)
 532     return;
 533
 534   if (undobuf.frees)
 535     buf = undobuf.frees, undobuf.frees = buf->next;
 536   else
 537     buf = XNEW (struct undo);
 538
 539   buf->kind = UNDO_INT;
 540   buf->where.i = into;
 541   buf->old_contents.i = oldval;
 542   *into = newval;
 543
 544   buf->next = undobuf.undos, undobuf.undos = buf;
 545 }
 546
 547 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 548
 549 /* Similar to SUBST, but just substitute the mode.  This is used when
 550    changing the mode of a pseudo-register, so that any other
 551    references to the entry in the regno_reg_rtx array will change as
 552    well.  */
 553
 554 static void
 555 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 556 {
 557   struct undo *buf;
 558   enum machine_mode oldval = GET_MODE (*into);
 559
 560   if (oldval == newval)
 561     return;
 562
 563   if (undobuf.frees)
 564     buf = undobuf.frees, undobuf.frees = buf->next;
 565   else
 566     buf = XNEW (struct undo);
 567
 568   buf->kind = UNDO_MODE;
 569   buf->where.r = into;
 570   buf->old_contents.m = oldval;
 571   PUT_MODE (*into, newval);
 572
 573   buf->next = undobuf.undos, undobuf.undos = buf;
 574 }
 575
 576 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 577 \f
 578 /* Subroutine of try_combine.  Determine whether the combine replacement
 579    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 580    that the original instruction sequence I1, I2 and I3.  Note that I1
 581    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 582    costs of all instructions can be estimated, and the replacements are
 583    more expensive than the original sequence.  */
 584
 585 static bool
 586 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 587 {
 588   int i1_cost, i2_cost, i3_cost;
 589   int new_i2_cost, new_i3_cost;
 590   int old_cost, new_cost;
 591
 592   /* Lookup the original insn_rtx_costs.  */
 593   i2_cost = INSN_UID (i2) <= last_insn_cost
 594             ? uid_insn_cost[INSN_UID (i2)] : 0;
 595   i3_cost = INSN_UID (i3) <= last_insn_cost
 596             ? uid_insn_cost[INSN_UID (i3)] : 0;
 597
 598   if (i1)
 599     {
 600       i1_cost = INSN_UID (i1) <= last_insn_cost
 601                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 602       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 603                  ? i1_cost + i2_cost + i3_cost : 0;
 604     }
 605   else
 606     {
 607       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 608       i1_cost = 0;
 609     }
 610
 611   /* Calculate the replacement insn_rtx_costs.  */
 612   new_i3_cost = insn_rtx_cost (newpat);
 613   if (newi2pat)
 614     {
 615       new_i2_cost = insn_rtx_cost (newi2pat);
 616       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 617                  ? new_i2_cost + new_i3_cost : 0;
 618     }
 619   else
 620     {
 621       new_cost = new_i3_cost;
 622       new_i2_cost = 0;
 623     }
 624
 625   if (undobuf.other_insn)
 626     {
 627       int old_other_cost, new_other_cost;
 628
 629       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 630                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 631       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 632       if (old_other_cost > 0 && new_other_cost > 0)
 633         {
 634           old_cost += old_other_cost;
 635           new_cost += new_other_cost;
 636         }
 637       else
 638         old_cost = 0;
 639     }
 640
 641   /* Disallow this recombination if both new_cost and old_cost are
 642      greater than zero, and new_cost is greater than old cost.  */
 643   if (old_cost > 0
 644       && new_cost > old_cost)
 645     {
 646       if (dump_file)
 647         {
 648           if (i1)
 649             {
 650               fprintf (dump_file,
 651                        "rejecting combination of insns %d, %d and %d\n",
 652                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 653               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 654                        i1_cost, i2_cost, i3_cost, old_cost);
 655             }
 656           else
 657             {
 658               fprintf (dump_file,
 659                        "rejecting combination of insns %d and %d\n",
 660                        INSN_UID (i2), INSN_UID (i3));
 661               fprintf (dump_file, "original costs %d + %d = %d\n",
 662                        i2_cost, i3_cost, old_cost);
 663             }
 664
 665           if (newi2pat)
 666             {
 667               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 668                        new_i2_cost, new_i3_cost, new_cost);
 669             }
 670           else
 671             fprintf (dump_file, "replacement cost %d\n", new_cost);
 672         }
 673
 674       return false;
 675     }
 676
 677   /* Update the uid_insn_cost array with the replacement costs.  */
 678   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 679   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 680   if (i1)
 681     uid_insn_cost[INSN_UID (i1)] = 0;
 682
 683   return true;
 684 }
 685 \f
 686 /* Main entry point for combiner.  F is the first insn of the function.
 687    NREGS is the first unused pseudo-reg number.
 688
 689    Return nonzero if the combiner has turned an indirect jump
 690    instruction into a direct jump.  */
 691 static int
 692 combine_instructions (rtx f, unsigned int nregs)
 693 {
 694   rtx insn, next;
 695 #ifdef HAVE_cc0
 696   rtx prev;
 697 #endif
 698   int i;
 699   unsigned int j = 0;
 700   rtx links, nextlinks;
 701   sbitmap_iterator sbi;
 702
 703   int new_direct_jump_p = 0;
 704
 705   combine_attempts = 0;
 706   combine_merges = 0;
 707   combine_extras = 0;
 708   combine_successes = 0;
 709
 710   combine_max_regno = nregs;
 711
 712   rtl_hooks = combine_rtl_hooks;
 713
 714   reg_stat = XCNEWVEC (struct reg_stat, nregs);
 715
 716   init_recog_no_volatile ();
 717
 718   /* Compute maximum uid value so uid_cuid can be allocated.  */
 719
 720   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 721     if (INSN_UID (insn) > i)
 722       i = INSN_UID (insn);
 723
 724   uid_cuid = XNEWVEC (int, i + 1);
 725   max_uid_cuid = i;
 726
 727   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 728
 729   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 730      problems when, for example, we have j <<= 1 in a loop.  */
 731
 732   nonzero_sign_valid = 0;
 733
 734   /* Compute the mapping from uids to cuids.
 735      Cuids are numbers assigned to insns, like uids,
 736      except that cuids increase monotonically through the code.
 737
 738      Scan all SETs and see if we can deduce anything about what
 739      bits are known to be zero for some registers and how many copies
 740      of the sign bit are known to exist for those registers.
 741
 742      Also set any known values so that we can use it while searching
 743      for what bits are known to be set.  */
 744
 745   label_tick = 1;
 746
 747   setup_incoming_promotions ();
 748
 749   refresh_blocks = sbitmap_alloc (last_basic_block);
 750   sbitmap_zero (refresh_blocks);
 751
 752   /* Allocate array of current insn_rtx_costs.  */
 753   uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1);
 754   last_insn_cost = max_uid_cuid;
 755
 756   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 757     {
 758       uid_cuid[INSN_UID (insn)] = ++i;
 759       subst_low_cuid = i;
 760       subst_insn = insn;
 761
 762       if (INSN_P (insn))
 763         {
 764           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 765                        NULL);
 766           record_dead_and_set_regs (insn);
 767
 768 #ifdef AUTO_INC_DEC
 769           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 770             if (REG_NOTE_KIND (links) == REG_INC)
 771               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 772                                                 NULL);
 773 #endif
 774
 775           /* Record the current insn_rtx_cost of this instruction.  */
 776           if (NONJUMP_INSN_P (insn))
 777             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 778           if (dump_file)
 779             fprintf(dump_file, "insn_cost %d: %d\n",
 780                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 781         }
 782
 783       if (LABEL_P (insn))
 784         label_tick++;
 785     }
 786
 787   nonzero_sign_valid = 1;
 788
 789   /* Now scan all the insns in forward order.  */
 790
 791   label_tick = 1;
 792   last_call_cuid = 0;
 793   mem_last_set = 0;
 794   init_reg_last ();
 795   setup_incoming_promotions ();
 796
 797   FOR_EACH_BB (this_basic_block)
 798     {
 799       for (insn = BB_HEAD (this_basic_block);
 800            insn != NEXT_INSN (BB_END (this_basic_block));
 801            insn = next ? next : NEXT_INSN (insn))
 802         {
 803           next = 0;
 804
 805           if (LABEL_P (insn))
 806             label_tick++;
 807
 808           else if (INSN_P (insn))
 809             {
 810               /* See if we know about function return values before this
 811                  insn based upon SUBREG flags.  */
 812               check_conversions (insn, PATTERN (insn));
 813
 814               /* Try this insn with each insn it links back to.  */
 815
 816               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 817                 if ((next = try_combine (insn, XEXP (links, 0),
 818                                          NULL_RTX, &new_direct_jump_p)) != 0)
 819                   goto retry;
 820
 821               /* Try each sequence of three linked insns ending with this one.  */
 822
 823               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 824                 {
 825                   rtx link = XEXP (links, 0);
 826
 827                   /* If the linked insn has been replaced by a note, then there
 828                      is no point in pursuing this chain any further.  */
 829                   if (NOTE_P (link))
 830                     continue;
 831
 832                   for (nextlinks = LOG_LINKS (link);
 833                        nextlinks;
 834                        nextlinks = XEXP (nextlinks, 1))
 835                     if ((next = try_combine (insn, link,
 836                                              XEXP (nextlinks, 0),
 837                                              &new_direct_jump_p)) != 0)
 838                       goto retry;
 839                 }
 840
 841 #ifdef HAVE_cc0
 842               /* Try to combine a jump insn that uses CC0
 843                  with a preceding insn that sets CC0, and maybe with its
 844                  logical predecessor as well.
 845                  This is how we make decrement-and-branch insns.
 846                  We need this special code because data flow connections
 847                  via CC0 do not get entered in LOG_LINKS.  */
 848
 849               if (JUMP_P (insn)
 850                   && (prev = prev_nonnote_insn (insn)) != 0
 851                   && NONJUMP_INSN_P (prev)
 852                   && sets_cc0_p (PATTERN (prev)))
 853                 {
 854                   if ((next = try_combine (insn, prev,
 855                                            NULL_RTX, &new_direct_jump_p)) != 0)
 856                     goto retry;
 857
 858                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 859                        nextlinks = XEXP (nextlinks, 1))
 860                     if ((next = try_combine (insn, prev,
 861                                              XEXP (nextlinks, 0),
 862                                              &new_direct_jump_p)) != 0)
 863                       goto retry;
 864                 }
 865
 866               /* Do the same for an insn that explicitly references CC0.  */
 867               if (NONJUMP_INSN_P (insn)
 868                   && (prev = prev_nonnote_insn (insn)) != 0
 869                   && NONJUMP_INSN_P (prev)
 870                   && sets_cc0_p (PATTERN (prev))
 871                   && GET_CODE (PATTERN (insn)) == SET
 872                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 873                 {
 874                   if ((next = try_combine (insn, prev,
 875                                            NULL_RTX, &new_direct_jump_p)) != 0)
 876                     goto retry;
 877
 878                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 879                        nextlinks = XEXP (nextlinks, 1))
 880                     if ((next = try_combine (insn, prev,
 881                                              XEXP (nextlinks, 0),
 882                                              &new_direct_jump_p)) != 0)
 883                       goto retry;
 884                 }
 885
 886               /* Finally, see if any of the insns that this insn links to
 887                  explicitly references CC0.  If so, try this insn, that insn,
 888                  and its predecessor if it sets CC0.  */
 889               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 890                 if (NONJUMP_INSN_P (XEXP (links, 0))
 891                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 892                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 893                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 894                     && NONJUMP_INSN_P (prev)
 895                     && sets_cc0_p (PATTERN (prev))
 896                     && (next = try_combine (insn, XEXP (links, 0),
 897                                             prev, &new_direct_jump_p)) != 0)
 898                   goto retry;
 899 #endif
 900
 901               /* Try combining an insn with two different insns whose results it
 902                  uses.  */
 903               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 904                 for (nextlinks = XEXP (links, 1); nextlinks;
 905                      nextlinks = XEXP (nextlinks, 1))
 906                   if ((next = try_combine (insn, XEXP (links, 0),
 907                                            XEXP (nextlinks, 0),
 908                                            &new_direct_jump_p)) != 0)
 909                     goto retry;
 910
 911               /* Try this insn with each REG_EQUAL note it links back to.  */
 912               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 913                 {
 914                   rtx set, note;
 915                   rtx temp = XEXP (links, 0);
 916                   if ((set = single_set (temp)) != 0
 917                       && (note = find_reg_equal_equiv_note (temp)) != 0
 918                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 919                       /* Avoid using a register that may already been marked
 920                          dead by an earlier instruction.  */
 921                       && ! unmentioned_reg_p (note, SET_SRC (set))
 922                       && (GET_MODE (note) == VOIDmode
 923                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 924                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 925                     {
 926                       /* Temporarily replace the set's source with the
 927                          contents of the REG_EQUAL note.  The insn will
 928                          be deleted or recognized by try_combine.  */
 929                       rtx orig = SET_SRC (set);
 930                       SET_SRC (set) = note;
 931                       next = try_combine (insn, temp, NULL_RTX,
 932                                           &new_direct_jump_p);
 933                       if (next)
 934                         goto retry;
 935                       SET_SRC (set) = orig;
 936                     }
 937                 }
 938
 939               if (!NOTE_P (insn))
 940                 record_dead_and_set_regs (insn);
 941
 942             retry:
 943               ;
 944             }
 945         }
 946     }
 947   clear_bb_flags ();
 948
 949   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 950     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 951   new_direct_jump_p |= purge_all_dead_edges ();
 952   delete_noop_moves ();
 953
 954   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 955                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 956                                     | PROP_KILL_DEAD_CODE);
 957
 958   /* Clean up.  */
 959   sbitmap_free (refresh_blocks);
 960   free (uid_insn_cost);
 961   free (reg_stat);
 962   free (uid_cuid);
 963
 964   {
 965     struct undo *undo, *next;
 966     for (undo = undobuf.frees; undo; undo = next)
 967       {
 968         next = undo->next;
 969         free (undo);
 970       }
 971     undobuf.frees = 0;
 972   }
 973
 974   total_attempts += combine_attempts;
 975   total_merges += combine_merges;
 976   total_extras += combine_extras;
 977   total_successes += combine_successes;
 978
 979   nonzero_sign_valid = 0;
 980   rtl_hooks = general_rtl_hooks;
 981
 982   /* Make recognizer allow volatile MEMs again.  */
 983   init_recog ();
 984
 985   return new_direct_jump_p;
 986 }
 987
 988 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
 989
 990 static void
 991 init_reg_last (void)
 992 {
 993   unsigned int i;
 994   for (i = 0; i < combine_max_regno; i++)
 995     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
 996 }
 997 \f
 998 /* Set up any promoted values for incoming argument registers.  */
 999
1000 static void
1001 setup_incoming_promotions (void)
1002 {
1003   unsigned int regno;
1004   rtx reg;
1005   enum machine_mode mode;
1006   int unsignedp;
1007   rtx first = get_insns ();
1008
1009   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1010     {
1011       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1012         /* Check whether this register can hold an incoming pointer
1013            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
1014            numbers, so translate if necessary due to register windows.  */
1015         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1016             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1017           {
1018             record_value_for_reg
1019               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1020                                            : SIGN_EXTEND),
1021                                           GET_MODE (reg),
1022                                           gen_rtx_CLOBBER (mode, const0_rtx)));
1023           }
1024     }
1025 }
1026 \f
1027 /* Called via note_stores.  If X is a pseudo that is narrower than
1028    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1029
1030    If we are setting only a portion of X and we can't figure out what
1031    portion, assume all bits will be used since we don't know what will
1032    be happening.
1033
1034    Similarly, set how many bits of X are known to be copies of the sign bit
1035    at all locations in the function.  This is the smallest number implied
1036    by any set of X.  */
1037
1038 static void
1039 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1040                                   void *data ATTRIBUTE_UNUSED)
1041 {
1042   unsigned int num;
1043
1044   if (REG_P (x)
1045       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1046       /* If this register is undefined at the start of the file, we can't
1047          say what its contents were.  */
1048       && ! REGNO_REG_SET_P
1049          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1050       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1051     {
1052       if (set == 0 || GET_CODE (set) == CLOBBER)
1053         {
1054           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1055           reg_stat[REGNO (x)].sign_bit_copies = 1;
1056           return;
1057         }
1058
1059       /* If this is a complex assignment, see if we can convert it into a
1060          simple assignment.  */
1061       set = expand_field_assignment (set);
1062
1063       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1064          set what we know about X.  */
1065
1066       if (SET_DEST (set) == x
1067           || (GET_CODE (SET_DEST (set)) == SUBREG
1068               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1069                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1070               && SUBREG_REG (SET_DEST (set)) == x))
1071         {
1072           rtx src = SET_SRC (set);
1073
1074 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1075           /* If X is narrower than a word and SRC is a non-negative
1076              constant that would appear negative in the mode of X,
1077              sign-extend it for use in reg_stat[].nonzero_bits because some
1078              machines (maybe most) will actually do the sign-extension
1079              and this is the conservative approach.
1080
1081              ??? For 2.5, try to tighten up the MD files in this regard
1082              instead of this kludge.  */
1083
1084           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1085               && GET_CODE (src) == CONST_INT
1086               && INTVAL (src) > 0
1087               && 0 != (INTVAL (src)
1088                        & ((HOST_WIDE_INT) 1
1089                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1090             src = GEN_INT (INTVAL (src)
1091                            | ((HOST_WIDE_INT) (-1)
1092                               << GET_MODE_BITSIZE (GET_MODE (x))));
1093 #endif
1094
1095           /* Don't call nonzero_bits if it cannot change anything.  */
1096           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1097             reg_stat[REGNO (x)].nonzero_bits
1098               |= nonzero_bits (src, nonzero_bits_mode);
1099           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1100           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1101               || reg_stat[REGNO (x)].sign_bit_copies > num)
1102             reg_stat[REGNO (x)].sign_bit_copies = num;
1103         }
1104       else
1105         {
1106           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1107           reg_stat[REGNO (x)].sign_bit_copies = 1;
1108         }
1109     }
1110 }
1111 \f
1112 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1113    insns that were previously combined into I3 or that will be combined
1114    into the merger of INSN and I3.
1115
1116    Return 0 if the combination is not allowed for any reason.
1117
1118    If the combination is allowed, *PDEST will be set to the single
1119    destination of INSN and *PSRC to the single source, and this function
1120    will return 1.  */
1121
1122 static int
1123 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1124                rtx *pdest, rtx *psrc)
1125 {
1126   int i;
1127   rtx set = 0, src, dest;
1128   rtx p;
1129 #ifdef AUTO_INC_DEC
1130   rtx link;
1131 #endif
1132   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1133                               && next_active_insn (succ) == i3)
1134                       : next_active_insn (insn) == i3);
1135
1136   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1137      or a PARALLEL consisting of such a SET and CLOBBERs.
1138
1139      If INSN has CLOBBER parallel parts, ignore them for our processing.
1140      By definition, these happen during the execution of the insn.  When it
1141      is merged with another insn, all bets are off.  If they are, in fact,
1142      needed and aren't also supplied in I3, they may be added by
1143      recog_for_combine.  Otherwise, it won't match.
1144
1145      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1146      note.
1147
1148      Get the source and destination of INSN.  If more than one, can't
1149      combine.  */
1150
1151   if (GET_CODE (PATTERN (insn)) == SET)
1152     set = PATTERN (insn);
1153   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1154            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1155     {
1156       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1157         {
1158           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1159           rtx note;
1160
1161           switch (GET_CODE (elt))
1162             {
1163             /* This is important to combine floating point insns
1164                for the SH4 port.  */
1165             case USE:
1166               /* Combining an isolated USE doesn't make sense.
1167                  We depend here on combinable_i3pat to reject them.  */
1168               /* The code below this loop only verifies that the inputs of
1169                  the SET in INSN do not change.  We call reg_set_between_p
1170                  to verify that the REG in the USE does not change between
1171                  I3 and INSN.
1172                  If the USE in INSN was for a pseudo register, the matching
1173                  insn pattern will likely match any register; combining this
1174                  with any other USE would only be safe if we knew that the
1175                  used registers have identical values, or if there was
1176                  something to tell them apart, e.g. different modes.  For
1177                  now, we forgo such complicated tests and simply disallow
1178                  combining of USES of pseudo registers with any other USE.  */
1179               if (REG_P (XEXP (elt, 0))
1180                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1181                 {
1182                   rtx i3pat = PATTERN (i3);
1183                   int i = XVECLEN (i3pat, 0) - 1;
1184                   unsigned int regno = REGNO (XEXP (elt, 0));
1185
1186                   do
1187                     {
1188                       rtx i3elt = XVECEXP (i3pat, 0, i);
1189
1190                       if (GET_CODE (i3elt) == USE
1191                           && REG_P (XEXP (i3elt, 0))
1192                           && (REGNO (XEXP (i3elt, 0)) == regno
1193                               ? reg_set_between_p (XEXP (elt, 0),
1194                                                    PREV_INSN (insn), i3)
1195                               : regno >= FIRST_PSEUDO_REGISTER))
1196                         return 0;
1197                     }
1198                   while (--i >= 0);
1199                 }
1200               break;
1201
1202               /* We can ignore CLOBBERs.  */
1203             case CLOBBER:
1204               break;
1205
1206             case SET:
1207               /* Ignore SETs whose result isn't used but not those that
1208                  have side-effects.  */
1209               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1210                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1211                       || INTVAL (XEXP (note, 0)) <= 0)
1212                   && ! side_effects_p (elt))
1213                 break;
1214
1215               /* If we have already found a SET, this is a second one and
1216                  so we cannot combine with this insn.  */
1217               if (set)
1218                 return 0;
1219
1220               set = elt;
1221               break;
1222
1223             default:
1224               /* Anything else means we can't combine.  */
1225               return 0;
1226             }
1227         }
1228
1229       if (set == 0
1230           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1231              so don't do anything with it.  */
1232           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1233         return 0;
1234     }
1235   else
1236     return 0;
1237
1238   if (set == 0)
1239     return 0;
1240
1241   set = expand_field_assignment (set);
1242   src = SET_SRC (set), dest = SET_DEST (set);
1243
1244   /* Don't eliminate a store in the stack pointer.  */
1245   if (dest == stack_pointer_rtx
1246       /* Don't combine with an insn that sets a register to itself if it has
1247          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1248       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1249       /* Can't merge an ASM_OPERANDS.  */
1250       || GET_CODE (src) == ASM_OPERANDS
1251       /* Can't merge a function call.  */
1252       || GET_CODE (src) == CALL
1253       /* Don't eliminate a function call argument.  */
1254       || (CALL_P (i3)
1255           && (find_reg_fusage (i3, USE, dest)
1256               || (REG_P (dest)
1257                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1258                   && global_regs[REGNO (dest)])))
1259       /* Don't substitute into an incremented register.  */
1260       || FIND_REG_INC_NOTE (i3, dest)
1261       || (succ && FIND_REG_INC_NOTE (succ, dest))
1262       /* Don't substitute into a non-local goto, this confuses CFG.  */
1263       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1264 #if 0
1265       /* Don't combine the end of a libcall into anything.  */
1266       /* ??? This gives worse code, and appears to be unnecessary, since no
1267          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1268          use REG_RETVAL notes for noconflict blocks, but other code here
1269          makes sure that those insns don't disappear.  */
1270       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1271 #endif
1272       /* Make sure that DEST is not used after SUCC but before I3.  */
1273       || (succ && ! all_adjacent
1274           && reg_used_between_p (dest, succ, i3))
1275       /* Make sure that the value that is to be substituted for the register
1276          does not use any registers whose values alter in between.  However,
1277          If the insns are adjacent, a use can't cross a set even though we
1278          think it might (this can happen for a sequence of insns each setting
1279          the same destination; last_set of that register might point to
1280          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1281          equivalent to the memory so the substitution is valid even if there
1282          are intervening stores.  Also, don't move a volatile asm or
1283          UNSPEC_VOLATILE across any other insns.  */
1284       || (! all_adjacent
1285           && (((!MEM_P (src)
1286                 || ! find_reg_note (insn, REG_EQUIV, src))
1287                && use_crosses_set_p (src, INSN_CUID (insn)))
1288               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1289               || GET_CODE (src) == UNSPEC_VOLATILE))
1290       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1291          better register allocation by not doing the combine.  */
1292       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1293       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1294       /* Don't combine across a CALL_INSN, because that would possibly
1295          change whether the life span of some REGs crosses calls or not,
1296          and it is a pain to update that information.
1297          Exception: if source is a constant, moving it later can't hurt.
1298          Accept that special case, because it helps -fforce-addr a lot.  */
1299       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1300     return 0;
1301
1302   /* DEST must either be a REG or CC0.  */
1303   if (REG_P (dest))
1304     {
1305       /* If register alignment is being enforced for multi-word items in all
1306          cases except for parameters, it is possible to have a register copy
1307          insn referencing a hard register that is not allowed to contain the
1308          mode being copied and which would not be valid as an operand of most
1309          insns.  Eliminate this problem by not combining with such an insn.
1310
1311          Also, on some machines we don't want to extend the life of a hard
1312          register.  */
1313
1314       if (REG_P (src)
1315           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1316                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1317               /* Don't extend the life of a hard register unless it is
1318                  user variable (if we have few registers) or it can't
1319                  fit into the desired register (meaning something special
1320                  is going on).
1321                  Also avoid substituting a return register into I3, because
1322                  reload can't handle a conflict with constraints of other
1323                  inputs.  */
1324               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1325                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1326         return 0;
1327     }
1328   else if (GET_CODE (dest) != CC0)
1329     return 0;
1330
1331
1332   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1333     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1334       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1335         {
1336           /* Don't substitute for a register intended as a clobberable
1337              operand.  */
1338           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1339           if (rtx_equal_p (reg, dest))
1340             return 0;
1341
1342           /* If the clobber represents an earlyclobber operand, we must not
1343              substitute an expression containing the clobbered register.
1344              As we do not analyze the constraint strings here, we have to
1345              make the conservative assumption.  However, if the register is
1346              a fixed hard reg, the clobber cannot represent any operand;
1347              we leave it up to the machine description to either accept or
1348              reject use-and-clobber patterns.  */
1349           if (!REG_P (reg)
1350               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1351               || !fixed_regs[REGNO (reg)])
1352             if (reg_overlap_mentioned_p (reg, src))
1353               return 0;
1354         }
1355
1356   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1357      or not), reject, unless nothing volatile comes between it and I3 */
1358
1359   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1360     {
1361       /* Make sure succ doesn't contain a volatile reference.  */
1362       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1363         return 0;
1364
1365       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1366         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1367           return 0;
1368     }
1369
1370   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1371      to be an explicit register variable, and was chosen for a reason.  */
1372
1373   if (GET_CODE (src) == ASM_OPERANDS
1374       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1375     return 0;
1376
1377   /* If there are any volatile insns between INSN and I3, reject, because
1378      they might affect machine state.  */
1379
1380   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1381     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1382       return 0;
1383
1384   /* If INSN contains an autoincrement or autodecrement, make sure that
1385      register is not used between there and I3, and not already used in
1386      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1387      Also insist that I3 not be a jump; if it were one
1388      and the incremented register were spilled, we would lose.  */
1389
1390 #ifdef AUTO_INC_DEC
1391   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1392     if (REG_NOTE_KIND (link) == REG_INC
1393         && (JUMP_P (i3)
1394             || reg_used_between_p (XEXP (link, 0), insn, i3)
1395             || (pred != NULL_RTX
1396                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1397             || (succ != NULL_RTX
1398                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1399             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1400       return 0;
1401 #endif
1402
1403 #ifdef HAVE_cc0
1404   /* Don't combine an insn that follows a CC0-setting insn.
1405      An insn that uses CC0 must not be separated from the one that sets it.
1406      We do, however, allow I2 to follow a CC0-setting insn if that insn
1407      is passed as I1; in that case it will be deleted also.
1408      We also allow combining in this case if all the insns are adjacent
1409      because that would leave the two CC0 insns adjacent as well.
1410      It would be more logical to test whether CC0 occurs inside I1 or I2,
1411      but that would be much slower, and this ought to be equivalent.  */
1412
1413   p = prev_nonnote_insn (insn);
1414   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1415       && ! all_adjacent)
1416     return 0;
1417 #endif
1418
1419   /* If we get here, we have passed all the tests and the combination is
1420      to be allowed.  */
1421
1422   *pdest = dest;
1423   *psrc = src;
1424
1425   return 1;
1426 }
1427 \f
1428 /* LOC is the location within I3 that contains its pattern or the component
1429    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1430
1431    One problem is if I3 modifies its output, as opposed to replacing it
1432    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1433    so would produce an insn that is not equivalent to the original insns.
1434
1435    Consider:
1436
1437          (set (reg:DI 101) (reg:DI 100))
1438          (set (subreg:SI (reg:DI 101) 0) <foo>)
1439
1440    This is NOT equivalent to:
1441
1442          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1443                     (set (reg:DI 101) (reg:DI 100))])
1444
1445    Not only does this modify 100 (in which case it might still be valid
1446    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1447
1448    We can also run into a problem if I2 sets a register that I1
1449    uses and I1 gets directly substituted into I3 (not via I2).  In that
1450    case, we would be getting the wrong value of I2DEST into I3, so we
1451    must reject the combination.  This case occurs when I2 and I1 both
1452    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1453    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1454    of a SET must prevent combination from occurring.
1455
1456    Before doing the above check, we first try to expand a field assignment
1457    into a set of logical operations.
1458
1459    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1460    we place a register that is both set and used within I3.  If more than one
1461    such register is detected, we fail.
1462
1463    Return 1 if the combination is valid, zero otherwise.  */
1464
1465 static int
1466 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1467                   int i1_not_in_src, rtx *pi3dest_killed)
1468 {
1469   rtx x = *loc;
1470
1471   if (GET_CODE (x) == SET)
1472     {
1473       rtx set = x ;
1474       rtx dest = SET_DEST (set);
1475       rtx src = SET_SRC (set);
1476       rtx inner_dest = dest;
1477       rtx subdest;
1478
1479       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1480              || GET_CODE (inner_dest) == SUBREG
1481              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1482         inner_dest = XEXP (inner_dest, 0);
1483
1484       /* Check for the case where I3 modifies its output, as discussed
1485          above.  We don't want to prevent pseudos from being combined
1486          into the address of a MEM, so only prevent the combination if
1487          i1 or i2 set the same MEM.  */
1488       if ((inner_dest != dest &&
1489            (!MEM_P (inner_dest)
1490             || rtx_equal_p (i2dest, inner_dest)
1491             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1492            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1493                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1494
1495           /* This is the same test done in can_combine_p except we can't test
1496              all_adjacent; we don't have to, since this instruction will stay
1497              in place, thus we are not considering increasing the lifetime of
1498              INNER_DEST.
1499
1500              Also, if this insn sets a function argument, combining it with
1501              something that might need a spill could clobber a previous
1502              function argument; the all_adjacent test in can_combine_p also
1503              checks this; here, we do a more specific test for this case.  */
1504
1505           || (REG_P (inner_dest)
1506               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1507               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1508                                         GET_MODE (inner_dest))))
1509           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1510         return 0;
1511
1512       /* If DEST is used in I3, it is being killed in this insn, so
1513          record that for later.  We have to consider paradoxical
1514          subregs here, since they kill the whole register, but we
1515          ignore partial subregs, STRICT_LOW_PART, etc.
1516          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1517          STACK_POINTER_REGNUM, since these are always considered to be
1518          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1519       subdest = dest;
1520       if (GET_CODE (subdest) == SUBREG
1521           && (GET_MODE_SIZE (GET_MODE (subdest))
1522               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1523         subdest = SUBREG_REG (subdest);
1524       if (pi3dest_killed
1525           && REG_P (subdest)
1526           && reg_referenced_p (subdest, PATTERN (i3))
1527           && REGNO (subdest) != FRAME_POINTER_REGNUM
1528 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1529           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1530 #endif
1531 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1532           && (REGNO (subdest) != ARG_POINTER_REGNUM
1533               || ! fixed_regs [REGNO (subdest)])
1534 #endif
1535           && REGNO (subdest) != STACK_POINTER_REGNUM)
1536         {
1537           if (*pi3dest_killed)
1538             return 0;
1539
1540           *pi3dest_killed = subdest;
1541         }
1542     }
1543
1544   else if (GET_CODE (x) == PARALLEL)
1545     {
1546       int i;
1547
1548       for (i = 0; i < XVECLEN (x, 0); i++)
1549         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1550                                 i1_not_in_src, pi3dest_killed))
1551           return 0;
1552     }
1553
1554   return 1;
1555 }
1556 \f
1557 /* Return 1 if X is an arithmetic expression that contains a multiplication
1558    and division.  We don't count multiplications by powers of two here.  */
1559
1560 static int
1561 contains_muldiv (rtx x)
1562 {
1563   switch (GET_CODE (x))
1564     {
1565     case MOD:  case DIV:  case UMOD:  case UDIV:
1566       return 1;
1567
1568     case MULT:
1569       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1570                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1571     default:
1572       if (BINARY_P (x))
1573         return contains_muldiv (XEXP (x, 0))
1574             || contains_muldiv (XEXP (x, 1));
1575
1576       if (UNARY_P (x))
1577         return contains_muldiv (XEXP (x, 0));
1578
1579       return 0;
1580     }
1581 }
1582 \f
1583 /* Determine whether INSN can be used in a combination.  Return nonzero if
1584    not.  This is used in try_combine to detect early some cases where we
1585    can't perform combinations.  */
1586
1587 static int
1588 cant_combine_insn_p (rtx insn)
1589 {
1590   rtx set;
1591   rtx src, dest;
1592
1593   /* If this isn't really an insn, we can't do anything.
1594      This can occur when flow deletes an insn that it has merged into an
1595      auto-increment address.  */
1596   if (! INSN_P (insn))
1597     return 1;
1598
1599   /* Never combine loads and stores involving hard regs that are likely
1600      to be spilled.  The register allocator can usually handle such
1601      reg-reg moves by tying.  If we allow the combiner to make
1602      substitutions of likely-spilled regs, reload might die.
1603      As an exception, we allow combinations involving fixed regs; these are
1604      not available to the register allocator so there's no risk involved.  */
1605
1606   set = single_set (insn);
1607   if (! set)
1608     return 0;
1609   src = SET_SRC (set);
1610   dest = SET_DEST (set);
1611   if (GET_CODE (src) == SUBREG)
1612     src = SUBREG_REG (src);
1613   if (GET_CODE (dest) == SUBREG)
1614     dest = SUBREG_REG (dest);
1615   if (REG_P (src) && REG_P (dest)
1616       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1617            && ! fixed_regs[REGNO (src)]
1618            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1619           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1620               && ! fixed_regs[REGNO (dest)]
1621               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1622     return 1;
1623
1624   return 0;
1625 }
1626
1627 struct likely_spilled_retval_info
1628 {
1629   unsigned regno, nregs;
1630   unsigned mask;
1631 };
1632
1633 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1634    hard registers that are known to be written to / clobbered in full.  */
1635 static void
1636 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1637 {
1638   struct likely_spilled_retval_info *info = data;
1639   unsigned regno, nregs;
1640   unsigned new_mask;
1641
1642   if (!REG_P (XEXP (set, 0)))
1643     return;
1644   regno = REGNO (x);
1645   if (regno >= info->regno + info->nregs)
1646     return;
1647   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1648   if (regno + nregs <= info->regno)
1649     return;
1650   new_mask = (2U << (nregs - 1)) - 1;
1651   if (regno < info->regno)
1652     new_mask >>= info->regno - regno;
1653   else
1654     new_mask <<= regno - info->regno;
1655   info->mask &= new_mask;
1656 }
1657
1658 /* Return nonzero iff part of the return value is live during INSN, and
1659    it is likely spilled.  This can happen when more than one insn is needed
1660    to copy the return value, e.g. when we consider to combine into the
1661    second copy insn for a complex value.  */
1662
1663 static int
1664 likely_spilled_retval_p (rtx insn)
1665 {
1666   rtx use = BB_END (this_basic_block);
1667   rtx reg, p;
1668   unsigned regno, nregs;
1669   /* We assume here that no machine mode needs more than
1670      32 hard registers when the value overlaps with a register
1671      for which FUNCTION_VALUE_REGNO_P is true.  */
1672   unsigned mask;
1673   struct likely_spilled_retval_info info;
1674
1675   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1676     return 0;
1677   reg = XEXP (PATTERN (use), 0);
1678   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1679     return 0;
1680   regno = REGNO (reg);
1681   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1682   if (nregs == 1)
1683     return 0;
1684   mask = (2U << (nregs - 1)) - 1;
1685
1686   /* Disregard parts of the return value that are set later.  */
1687   info.regno = regno;
1688   info.nregs = nregs;
1689   info.mask = mask;
1690   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1691     note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1692   mask = info.mask;
1693
1694   /* Check if any of the (probably) live return value registers is
1695      likely spilled.  */
1696   nregs --;
1697   do
1698     {
1699       if ((mask & 1 << nregs)
1700           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1701         return 1;
1702     } while (nregs--);
1703   return 0;
1704 }
1705
1706 /* Adjust INSN after we made a change to its destination.
1707
1708    Changing the destination can invalidate notes that say something about
1709    the results of the insn and a LOG_LINK pointing to the insn.  */
1710
1711 static void
1712 adjust_for_new_dest (rtx insn)
1713 {
1714   rtx *loc;
1715
1716   /* For notes, be conservative and simply remove them.  */
1717   loc = &REG_NOTES (insn);
1718   while (*loc)
1719     {
1720       enum reg_note kind = REG_NOTE_KIND (*loc);
1721       if (kind == REG_EQUAL || kind == REG_EQUIV)
1722         *loc = XEXP (*loc, 1);
1723       else
1724         loc = &XEXP (*loc, 1);
1725     }
1726
1727   /* The new insn will have a destination that was previously the destination
1728      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1729      the next use of that destination.  */
1730   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1731 }
1732
1733 /* Return TRUE if combine can reuse reg X in mode MODE.
1734    ADDED_SETS is nonzero if the original set is still required.  */
1735 static bool
1736 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1737 {
1738   unsigned int regno;
1739
1740   if (!REG_P(x))
1741     return false;
1742
1743   regno = REGNO (x);
1744   /* Allow hard registers if the new mode is legal, and occupies no more
1745      registers than the old mode.  */
1746   if (regno < FIRST_PSEUDO_REGISTER)
1747     return (HARD_REGNO_MODE_OK (regno, mode)
1748             && (hard_regno_nregs[regno][GET_MODE (x)]
1749                 >= hard_regno_nregs[regno][mode]));
1750
1751   /* Or a pseudo that is only used once.  */
1752   return (REG_N_SETS (regno) == 1 && !added_sets
1753           && !REG_USERVAR_P (x));
1754 }
1755
1756
1757 /* Check whether X, the destination of a set, refers to part of
1758    the register specified by REG.  */
1759
1760 static bool
1761 reg_subword_p (rtx x, rtx reg)
1762 {
1763   /* Check that reg is an integer mode register.  */
1764   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1765     return false;
1766
1767   if (GET_CODE (x) == STRICT_LOW_PART
1768       || GET_CODE (x) == ZERO_EXTRACT)
1769     x = XEXP (x, 0);
1770
1771   return GET_CODE (x) == SUBREG
1772          && SUBREG_REG (x) == reg
1773          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1774 }
1775
1776
1777 /* Try to combine the insns I1 and I2 into I3.
1778    Here I1 and I2 appear earlier than I3.
1779    I1 can be zero; then we combine just I2 into I3.
1780
1781    If we are combining three insns and the resulting insn is not recognized,
1782    try splitting it into two insns.  If that happens, I2 and I3 are retained
1783    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1784    are pseudo-deleted.
1785
1786    Return 0 if the combination does not work.  Then nothing is changed.
1787    If we did the combination, return the insn at which combine should
1788    resume scanning.
1789
1790    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1791    new direct jump instruction.  */
1792
1793 static rtx
1794 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1795 {
1796   /* New patterns for I3 and I2, respectively.  */
1797   rtx newpat, newi2pat = 0;
1798   rtvec newpat_vec_with_clobbers = 0;
1799   int substed_i2 = 0, substed_i1 = 0;
1800   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1801   int added_sets_1, added_sets_2;
1802   /* Total number of SETs to put into I3.  */
1803   int total_sets;
1804   /* Nonzero if I2's body now appears in I3.  */
1805   int i2_is_used;
1806   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1807   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1808   /* Contains I3 if the destination of I3 is used in its source, which means
1809      that the old life of I3 is being killed.  If that usage is placed into
1810      I2 and not in I3, a REG_DEAD note must be made.  */
1811   rtx i3dest_killed = 0;
1812   /* SET_DEST and SET_SRC of I2 and I1.  */
1813   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1814   /* PATTERN (I2), or a copy of it in certain cases.  */
1815   rtx i2pat;
1816   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1817   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1818   int i2dest_killed = 0, i1dest_killed = 0;
1819   int i1_feeds_i3 = 0;
1820   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1821   rtx new_i3_notes, new_i2_notes;
1822   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1823   int i3_subst_into_i2 = 0;
1824   /* Notes that I1, I2 or I3 is a MULT operation.  */
1825   int have_mult = 0;
1826   int swap_i2i3 = 0;
1827
1828   int maxreg;
1829   rtx temp;
1830   rtx link;
1831   int i;
1832
1833   /* Exit early if one of the insns involved can't be used for
1834      combinations.  */
1835   if (cant_combine_insn_p (i3)
1836       || cant_combine_insn_p (i2)
1837       || (i1 && cant_combine_insn_p (i1))
1838       || likely_spilled_retval_p (i3)
1839       /* We also can't do anything if I3 has a
1840          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1841          libcall.  */
1842 #if 0
1843       /* ??? This gives worse code, and appears to be unnecessary, since no
1844          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1845       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1846 #endif
1847       )
1848     return 0;
1849
1850   combine_attempts++;
1851   undobuf.other_insn = 0;
1852
1853   /* Reset the hard register usage information.  */
1854   CLEAR_HARD_REG_SET (newpat_used_regs);
1855
1856   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1857      code below, set I1 to be the earlier of the two insns.  */
1858   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1859     temp = i1, i1 = i2, i2 = temp;
1860
1861   added_links_insn = 0;
1862
1863   /* First check for one important special-case that the code below will
1864      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1865      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1866      we may be able to replace that destination with the destination of I3.
1867      This occurs in the common code where we compute both a quotient and
1868      remainder into a structure, in which case we want to do the computation
1869      directly into the structure to avoid register-register copies.
1870
1871      Note that this case handles both multiple sets in I2 and also
1872      cases where I2 has a number of CLOBBER or PARALLELs.
1873
1874      We make very conservative checks below and only try to handle the
1875      most common cases of this.  For example, we only handle the case
1876      where I2 and I3 are adjacent to avoid making difficult register
1877      usage tests.  */
1878
1879   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1880       && REG_P (SET_SRC (PATTERN (i3)))
1881       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1882       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1883       && GET_CODE (PATTERN (i2)) == PARALLEL
1884       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1885       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1886          below would need to check what is inside (and reg_overlap_mentioned_p
1887          doesn't support those codes anyway).  Don't allow those destinations;
1888          the resulting insn isn't likely to be recognized anyway.  */
1889       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1890       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1891       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1892                                     SET_DEST (PATTERN (i3)))
1893       && next_real_insn (i2) == i3)
1894     {
1895       rtx p2 = PATTERN (i2);
1896
1897       /* Make sure that the destination of I3,
1898          which we are going to substitute into one output of I2,
1899          is not used within another output of I2.  We must avoid making this:
1900          (parallel [(set (mem (reg 69)) ...)
1901                     (set (reg 69) ...)])
1902          which is not well-defined as to order of actions.
1903          (Besides, reload can't handle output reloads for this.)
1904
1905          The problem can also happen if the dest of I3 is a memory ref,
1906          if another dest in I2 is an indirect memory ref.  */
1907       for (i = 0; i < XVECLEN (p2, 0); i++)
1908         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1909              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1910             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1911                                         SET_DEST (XVECEXP (p2, 0, i))))
1912           break;
1913
1914       if (i == XVECLEN (p2, 0))
1915         for (i = 0; i < XVECLEN (p2, 0); i++)
1916           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1917                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1918               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1919             {
1920               combine_merges++;
1921
1922               subst_insn = i3;
1923               subst_low_cuid = INSN_CUID (i2);
1924
1925               added_sets_2 = added_sets_1 = 0;
1926               i2dest = SET_SRC (PATTERN (i3));
1927               i2dest_killed = dead_or_set_p (i2, i2dest);
1928
1929               /* Replace the dest in I2 with our dest and make the resulting
1930                  insn the new pattern for I3.  Then skip to where we
1931                  validate the pattern.  Everything was set up above.  */
1932               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1933                      SET_DEST (PATTERN (i3)));
1934
1935               newpat = p2;
1936               i3_subst_into_i2 = 1;
1937               goto validate_replacement;
1938             }
1939     }
1940
1941   /* If I2 is setting a pseudo to a constant and I3 is setting some
1942      sub-part of it to another constant, merge them by making a new
1943      constant.  */
1944   if (i1 == 0
1945       && (temp = single_set (i2)) != 0
1946       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1947           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1948       && GET_CODE (PATTERN (i3)) == SET
1949       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1950           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1951       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1952     {
1953       rtx dest = SET_DEST (PATTERN (i3));
1954       int offset = -1;
1955       int width = 0;
1956
1957       if (GET_CODE (dest) == ZERO_EXTRACT)
1958         {
1959           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1960               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1961             {
1962               width = INTVAL (XEXP (dest, 1));
1963               offset = INTVAL (XEXP (dest, 2));
1964               dest = XEXP (dest, 0);
1965               if (BITS_BIG_ENDIAN)
1966                 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
1967             }
1968         }
1969       else
1970         {
1971           if (GET_CODE (dest) == STRICT_LOW_PART)
1972             dest = XEXP (dest, 0);
1973           width = GET_MODE_BITSIZE (GET_MODE (dest));
1974           offset = 0;
1975         }
1976
1977       if (offset >= 0)
1978         {
1979           /* If this is the low part, we're done.  */
1980           if (subreg_lowpart_p (dest))
1981             ;
1982           /* Handle the case where inner is twice the size of outer.  */
1983           else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1984                    == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1985             offset += GET_MODE_BITSIZE (GET_MODE (dest));
1986           /* Otherwise give up for now.  */
1987           else
1988             offset = -1;
1989         }
1990
1991       if (offset >= 0)
1992         {
1993           HOST_WIDE_INT mhi, ohi, ihi;
1994           HOST_WIDE_INT mlo, olo, ilo;
1995           rtx inner = SET_SRC (PATTERN (i3));
1996           rtx outer = SET_SRC (temp);
1997
1998           if (GET_CODE (outer) == CONST_INT)
1999             {
2000               olo = INTVAL (outer);
2001               ohi = olo < 0 ? -1 : 0;
2002             }
2003           else
2004             {
2005               olo = CONST_DOUBLE_LOW (outer);
2006               ohi = CONST_DOUBLE_HIGH (outer);
2007             }
2008
2009           if (GET_CODE (inner) == CONST_INT)
2010             {
2011               ilo = INTVAL (inner);
2012               ihi = ilo < 0 ? -1 : 0;
2013             }
2014           else
2015             {
2016               ilo = CONST_DOUBLE_LOW (inner);
2017               ihi = CONST_DOUBLE_HIGH (inner);
2018             }
2019
2020           if (width < HOST_BITS_PER_WIDE_INT)
2021             {
2022               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2023               mhi = 0;
2024             }
2025           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2026             {
2027               mhi = ((unsigned HOST_WIDE_INT) 1
2028                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2029               mlo = -1;
2030             }
2031           else
2032             {
2033               mlo = -1;
2034               mhi = -1;
2035             }
2036
2037           ilo &= mlo;
2038           ihi &= mhi;
2039
2040           if (offset >= HOST_BITS_PER_WIDE_INT)
2041             {
2042               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2043               mlo = 0;
2044               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2045               ilo = 0;
2046             }
2047           else if (offset > 0)
2048             {
2049               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2050                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2051               mlo = mlo << offset;
2052               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2053                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2054               ilo = ilo << offset;
2055             }
2056
2057           olo = (olo & ~mlo) | ilo;
2058           ohi = (ohi & ~mhi) | ihi;
2059
2060           combine_merges++;
2061           subst_insn = i3;
2062           subst_low_cuid = INSN_CUID (i2);
2063           added_sets_2 = added_sets_1 = 0;
2064           i2dest = SET_DEST (temp);
2065           i2dest_killed = dead_or_set_p (i2, i2dest);
2066
2067           SUBST (SET_SRC (temp),
2068                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2069
2070           newpat = PATTERN (i2);
2071           goto validate_replacement;
2072         }
2073     }
2074
2075 #ifndef HAVE_cc0
2076   /* If we have no I1 and I2 looks like:
2077         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2078                    (set Y OP)])
2079      make up a dummy I1 that is
2080         (set Y OP)
2081      and change I2 to be
2082         (set (reg:CC X) (compare:CC Y (const_int 0)))
2083
2084      (We can ignore any trailing CLOBBERs.)
2085
2086      This undoes a previous combination and allows us to match a branch-and-
2087      decrement insn.  */
2088
2089   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2090       && XVECLEN (PATTERN (i2), 0) >= 2
2091       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2092       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2093           == MODE_CC)
2094       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2095       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2096       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2097       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2098       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2099                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2100     {
2101       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2102         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2103           break;
2104
2105       if (i == 1)
2106         {
2107           /* We make I1 with the same INSN_UID as I2.  This gives it
2108              the same INSN_CUID for value tracking.  Our fake I1 will
2109              never appear in the insn stream so giving it the same INSN_UID
2110              as I2 will not cause a problem.  */
2111
2112           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2113                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2114                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2115                              NULL_RTX);
2116
2117           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2118           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2119                  SET_DEST (PATTERN (i1)));
2120         }
2121     }
2122 #endif
2123
2124   /* Verify that I2 and I1 are valid for combining.  */
2125   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2126       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2127     {
2128       undo_all ();
2129       return 0;
2130     }
2131
2132   /* Record whether I2DEST is used in I2SRC and similarly for the other
2133      cases.  Knowing this will help in register status updating below.  */
2134   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2135   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2136   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2137   i2dest_killed = dead_or_set_p (i2, i2dest);
2138   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2139
2140   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2141      in I2SRC.  */
2142   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2143
2144   /* Ensure that I3's pattern can be the destination of combines.  */
2145   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2146                           i1 && i2dest_in_i1src && i1_feeds_i3,
2147                           &i3dest_killed))
2148     {
2149       undo_all ();
2150       return 0;
2151     }
2152
2153   /* See if any of the insns is a MULT operation.  Unless one is, we will
2154      reject a combination that is, since it must be slower.  Be conservative
2155      here.  */
2156   if (GET_CODE (i2src) == MULT
2157       || (i1 != 0 && GET_CODE (i1src) == MULT)
2158       || (GET_CODE (PATTERN (i3)) == SET
2159           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2160     have_mult = 1;
2161
2162   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2163      We used to do this EXCEPT in one case: I3 has a post-inc in an
2164      output operand.  However, that exception can give rise to insns like
2165         mov r3,(r3)+
2166      which is a famous insn on the PDP-11 where the value of r3 used as the
2167      source was model-dependent.  Avoid this sort of thing.  */
2168
2169 #if 0
2170   if (!(GET_CODE (PATTERN (i3)) == SET
2171         && REG_P (SET_SRC (PATTERN (i3)))
2172         && MEM_P (SET_DEST (PATTERN (i3)))
2173         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2174             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2175     /* It's not the exception.  */
2176 #endif
2177 #ifdef AUTO_INC_DEC
2178     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2179       if (REG_NOTE_KIND (link) == REG_INC
2180           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2181               || (i1 != 0
2182                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2183         {
2184           undo_all ();
2185           return 0;
2186         }
2187 #endif
2188
2189   /* See if the SETs in I1 or I2 need to be kept around in the merged
2190      instruction: whenever the value set there is still needed past I3.
2191      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2192
2193      For the SET in I1, we have two cases:  If I1 and I2 independently
2194      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2195      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2196      in I1 needs to be kept around unless I1DEST dies or is set in either
2197      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2198      I1DEST.  If so, we know I1 feeds into I2.  */
2199
2200   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2201
2202   added_sets_1
2203     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2204                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2205
2206   /* If the set in I2 needs to be kept around, we must make a copy of
2207      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2208      PATTERN (I2), we are only substituting for the original I1DEST, not into
2209      an already-substituted copy.  This also prevents making self-referential
2210      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2211      I2DEST.  */
2212
2213   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2214            ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2215            : PATTERN (i2));
2216
2217   if (added_sets_2)
2218     i2pat = copy_rtx (i2pat);
2219
2220   combine_merges++;
2221
2222   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2223
2224   maxreg = max_reg_num ();
2225
2226   subst_insn = i3;
2227
2228 #ifndef HAVE_cc0
2229   /* Many machines that don't use CC0 have insns that can both perform an
2230      arithmetic operation and set the condition code.  These operations will
2231      be represented as a PARALLEL with the first element of the vector
2232      being a COMPARE of an arithmetic operation with the constant zero.
2233      The second element of the vector will set some pseudo to the result
2234      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2235      match such a pattern and so will generate an extra insn.   Here we test
2236      for this case, where both the comparison and the operation result are
2237      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2238      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2239
2240   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2241       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2242       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2243       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2244     {
2245 #ifdef SELECT_CC_MODE
2246       rtx *cc_use;
2247       enum machine_mode compare_mode;
2248 #endif
2249
2250       newpat = PATTERN (i3);
2251       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2252
2253       i2_is_used = 1;
2254
2255 #ifdef SELECT_CC_MODE
2256       /* See if a COMPARE with the operand we substituted in should be done
2257          with the mode that is currently being used.  If not, do the same
2258          processing we do in `subst' for a SET; namely, if the destination
2259          is used only once, try to replace it with a register of the proper
2260          mode and also replace the COMPARE.  */
2261       if (undobuf.other_insn == 0
2262           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2263                                         &undobuf.other_insn))
2264           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2265                                               i2src, const0_rtx))
2266               != GET_MODE (SET_DEST (newpat))))
2267         {
2268           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2269                                    compare_mode))
2270             {
2271               unsigned int regno = REGNO (SET_DEST (newpat));
2272               rtx new_dest;
2273
2274               if (regno < FIRST_PSEUDO_REGISTER)
2275                 new_dest = gen_rtx_REG (compare_mode, regno);
2276               else
2277                 {
2278                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2279                   new_dest = regno_reg_rtx[regno];
2280                 }
2281
2282               SUBST (SET_DEST (newpat), new_dest);
2283               SUBST (XEXP (*cc_use, 0), new_dest);
2284               SUBST (SET_SRC (newpat),
2285                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2286             }
2287           else
2288             undobuf.other_insn = 0;
2289         }
2290 #endif
2291     }
2292   else
2293 #endif
2294     {
2295       /* It is possible that the source of I2 or I1 may be performing
2296          an unneeded operation, such as a ZERO_EXTEND of something
2297          that is known to have the high part zero.  Handle that case
2298          by letting subst look at the innermost one of them.
2299
2300          Another way to do this would be to have a function that tries
2301          to simplify a single insn instead of merging two or more
2302          insns.  We don't do this because of the potential of infinite
2303          loops and because of the potential extra memory required.
2304          However, doing it the way we are is a bit of a kludge and
2305          doesn't catch all cases.
2306
2307          But only do this if -fexpensive-optimizations since it slows
2308          things down and doesn't usually win.
2309
2310          This is not done in the COMPARE case above because the
2311          unmodified I2PAT is used in the PARALLEL and so a pattern
2312          with a modified I2SRC would not match.  */
2313
2314       if (flag_expensive_optimizations)
2315         {
2316           /* Pass pc_rtx so no substitutions are done, just
2317              simplifications.  */
2318           if (i1)
2319             {
2320               subst_low_cuid = INSN_CUID (i1);
2321               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2322             }
2323           else
2324             {
2325               subst_low_cuid = INSN_CUID (i2);
2326               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2327             }
2328         }
2329
2330       n_occurrences = 0;                /* `subst' counts here */
2331
2332       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2333          need to make a unique copy of I2SRC each time we substitute it
2334          to avoid self-referential rtl.  */
2335
2336       subst_low_cuid = INSN_CUID (i2);
2337       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2338                       ! i1_feeds_i3 && i1dest_in_i1src);
2339       substed_i2 = 1;
2340
2341       /* Record whether i2's body now appears within i3's body.  */
2342       i2_is_used = n_occurrences;
2343     }
2344
2345   /* If we already got a failure, don't try to do more.  Otherwise,
2346      try to substitute in I1 if we have it.  */
2347
2348   if (i1 && GET_CODE (newpat) != CLOBBER)
2349     {
2350       /* Before we can do this substitution, we must redo the test done
2351          above (see detailed comments there) that ensures  that I1DEST
2352          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2353
2354       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2355                               0, (rtx*) 0))
2356         {
2357           undo_all ();
2358           return 0;
2359         }
2360
2361       n_occurrences = 0;
2362       subst_low_cuid = INSN_CUID (i1);
2363       newpat = subst (newpat, i1dest, i1src, 0, 0);
2364       substed_i1 = 1;
2365     }
2366
2367   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2368      to count all the ways that I2SRC and I1SRC can be used.  */
2369   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2370        && i2_is_used + added_sets_2 > 1)
2371       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2372           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2373               > 1))
2374       /* Fail if we tried to make a new register.  */
2375       || max_reg_num () != maxreg
2376       /* Fail if we couldn't do something and have a CLOBBER.  */
2377       || GET_CODE (newpat) == CLOBBER
2378       /* Fail if this new pattern is a MULT and we didn't have one before
2379          at the outer level.  */
2380       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2381           && ! have_mult))
2382     {
2383       undo_all ();
2384       return 0;
2385     }
2386
2387   /* If the actions of the earlier insns must be kept
2388      in addition to substituting them into the latest one,
2389      we must make a new PARALLEL for the latest insn
2390      to hold additional the SETs.  */
2391
2392   if (added_sets_1 || added_sets_2)
2393     {
2394       combine_extras++;
2395
2396       if (GET_CODE (newpat) == PARALLEL)
2397         {
2398           rtvec old = XVEC (newpat, 0);
2399           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2400           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2401           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2402                   sizeof (old->elem[0]) * old->num_elem);
2403         }
2404       else
2405         {
2406           rtx old = newpat;
2407           total_sets = 1 + added_sets_1 + added_sets_2;
2408           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2409           XVECEXP (newpat, 0, 0) = old;
2410         }
2411
2412       if (added_sets_1)
2413         XVECEXP (newpat, 0, --total_sets)
2414           = (GET_CODE (PATTERN (i1)) == PARALLEL
2415              ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2416
2417       if (added_sets_2)
2418         {
2419           /* If there is no I1, use I2's body as is.  We used to also not do
2420              the subst call below if I2 was substituted into I3,
2421              but that could lose a simplification.  */
2422           if (i1 == 0)
2423             XVECEXP (newpat, 0, --total_sets) = i2pat;
2424           else
2425             /* See comment where i2pat is assigned.  */
2426             XVECEXP (newpat, 0, --total_sets)
2427               = subst (i2pat, i1dest, i1src, 0, 0);
2428         }
2429     }
2430
2431   /* We come here when we are replacing a destination in I2 with the
2432      destination of I3.  */
2433  validate_replacement:
2434
2435   /* Note which hard regs this insn has as inputs.  */
2436   mark_used_regs_combine (newpat);
2437
2438   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2439      consider splitting this pattern, we might need these clobbers.  */
2440   if (i1 && GET_CODE (newpat) == PARALLEL
2441       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2442     {
2443       int len = XVECLEN (newpat, 0);
2444
2445       newpat_vec_with_clobbers = rtvec_alloc (len);
2446       for (i = 0; i < len; i++)
2447         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2448     }
2449
2450   /* Is the result of combination a valid instruction?  */
2451   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2452
2453   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2454      the second SET's destination is a register that is unused and isn't
2455      marked as an instruction that might trap in an EH region.  In that case,
2456      we just need the first SET.   This can occur when simplifying a divmod
2457      insn.  We *must* test for this case here because the code below that
2458      splits two independent SETs doesn't handle this case correctly when it
2459      updates the register status.
2460
2461      It's pointless doing this if we originally had two sets, one from
2462      i3, and one from i2.  Combining then splitting the parallel results
2463      in the original i2 again plus an invalid insn (which we delete).
2464      The net effect is only to move instructions around, which makes
2465      debug info less accurate.
2466
2467      Also check the case where the first SET's destination is unused.
2468      That would not cause incorrect code, but does cause an unneeded
2469      insn to remain.  */
2470
2471   if (insn_code_number < 0
2472       && !(added_sets_2 && i1 == 0)
2473       && GET_CODE (newpat) == PARALLEL
2474       && XVECLEN (newpat, 0) == 2
2475       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2476       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2477       && asm_noperands (newpat) < 0)
2478     {
2479       rtx set0 = XVECEXP (newpat, 0, 0);
2480       rtx set1 = XVECEXP (newpat, 0, 1);
2481       rtx note;
2482
2483       if (((REG_P (SET_DEST (set1))
2484             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2485            || (GET_CODE (SET_DEST (set1)) == SUBREG
2486                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2487           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2488               || INTVAL (XEXP (note, 0)) <= 0)
2489           && ! side_effects_p (SET_SRC (set1)))
2490         {
2491           newpat = set0;
2492           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2493         }
2494
2495       else if (((REG_P (SET_DEST (set0))
2496                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2497                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2498                     && find_reg_note (i3, REG_UNUSED,
2499                                       SUBREG_REG (SET_DEST (set0)))))
2500                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2501                    || INTVAL (XEXP (note, 0)) <= 0)
2502                && ! side_effects_p (SET_SRC (set0)))
2503         {
2504           newpat = set1;
2505           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2506
2507           if (insn_code_number >= 0)
2508             {
2509               /* If we will be able to accept this, we have made a
2510                  change to the destination of I3.  This requires us to
2511                  do a few adjustments.  */
2512
2513               PATTERN (i3) = newpat;
2514               adjust_for_new_dest (i3);
2515             }
2516         }
2517     }
2518
2519   /* If we were combining three insns and the result is a simple SET
2520      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2521      insns.  There are two ways to do this.  It can be split using a
2522      machine-specific method (like when you have an addition of a large
2523      constant) or by combine in the function find_split_point.  */
2524
2525   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2526       && asm_noperands (newpat) < 0)
2527     {
2528       rtx m_split, *split;
2529
2530       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2531          use I2DEST as a scratch register will help.  In the latter case,
2532          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2533
2534       m_split = split_insns (newpat, i3);
2535
2536       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2537          inputs of NEWPAT.  */
2538
2539       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2540          possible to try that as a scratch reg.  This would require adding
2541          more code to make it work though.  */
2542
2543       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2544         {
2545           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2546
2547           /* First try to split using the original register as a
2548              scratch register.  */
2549           m_split = split_insns (gen_rtx_PARALLEL
2550                                  (VOIDmode,
2551                                   gen_rtvec (2, newpat,
2552                                              gen_rtx_CLOBBER (VOIDmode,
2553                                                               i2dest))),
2554                                  i3);
2555
2556           /* If that didn't work, try changing the mode of I2DEST if
2557              we can.  */
2558           if (m_split == 0
2559               && new_mode != GET_MODE (i2dest)
2560               && new_mode != VOIDmode
2561               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2562             {
2563               enum machine_mode old_mode = GET_MODE (i2dest);
2564               rtx ni2dest;
2565
2566               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2567                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2568               else
2569                 {
2570                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2571                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
2572                 }
2573
2574               m_split = split_insns (gen_rtx_PARALLEL
2575                                      (VOIDmode,
2576                                       gen_rtvec (2, newpat,
2577                                                  gen_rtx_CLOBBER (VOIDmode,
2578                                                                   ni2dest))),
2579                                      i3);
2580
2581               if (m_split == 0
2582                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2583                 {
2584                   struct undo *buf;
2585
2586                   PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2587                   buf = undobuf.undos;
2588                   undobuf.undos = buf->next;
2589                   buf->next = undobuf.frees;
2590                   undobuf.frees = buf;
2591                 }
2592             }
2593         }
2594
2595       /* If recog_for_combine has discarded clobbers, try to use them
2596          again for the split.  */
2597       if (m_split == 0 && newpat_vec_with_clobbers)
2598         m_split
2599           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2600                                            newpat_vec_with_clobbers), i3);
2601
2602       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2603         {
2604           m_split = PATTERN (m_split);
2605           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2606           if (insn_code_number >= 0)
2607             newpat = m_split;
2608         }
2609       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2610                && (next_real_insn (i2) == i3
2611                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2612         {
2613           rtx i2set, i3set;
2614           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2615           newi2pat = PATTERN (m_split);
2616
2617           i3set = single_set (NEXT_INSN (m_split));
2618           i2set = single_set (m_split);
2619
2620           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2621
2622           /* If I2 or I3 has multiple SETs, we won't know how to track
2623              register status, so don't use these insns.  If I2's destination
2624              is used between I2 and I3, we also can't use these insns.  */
2625
2626           if (i2_code_number >= 0 && i2set && i3set
2627               && (next_real_insn (i2) == i3
2628                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2629             insn_code_number = recog_for_combine (&newi3pat, i3,
2630                                                   &new_i3_notes);
2631           if (insn_code_number >= 0)
2632             newpat = newi3pat;
2633
2634           /* It is possible that both insns now set the destination of I3.
2635              If so, we must show an extra use of it.  */
2636
2637           if (insn_code_number >= 0)
2638             {
2639               rtx new_i3_dest = SET_DEST (i3set);
2640               rtx new_i2_dest = SET_DEST (i2set);
2641
2642               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2643                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2644                      || GET_CODE (new_i3_dest) == SUBREG)
2645                 new_i3_dest = XEXP (new_i3_dest, 0);
2646
2647               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2648                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2649                      || GET_CODE (new_i2_dest) == SUBREG)
2650                 new_i2_dest = XEXP (new_i2_dest, 0);
2651
2652               if (REG_P (new_i3_dest)
2653                   && REG_P (new_i2_dest)
2654                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2655                 REG_N_SETS (REGNO (new_i2_dest))++;
2656             }
2657         }
2658
2659       /* If we can split it and use I2DEST, go ahead and see if that
2660          helps things be recognized.  Verify that none of the registers
2661          are set between I2 and I3.  */
2662       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2663 #ifdef HAVE_cc0
2664           && REG_P (i2dest)
2665 #endif
2666           /* We need I2DEST in the proper mode.  If it is a hard register
2667              or the only use of a pseudo, we can change its mode.
2668              Make sure we don't change a hard register to have a mode that
2669              isn't valid for it, or change the number of registers.  */
2670           && (GET_MODE (*split) == GET_MODE (i2dest)
2671               || GET_MODE (*split) == VOIDmode
2672               || can_change_dest_mode (i2dest, added_sets_2,
2673                                        GET_MODE (*split)))
2674           && (next_real_insn (i2) == i3
2675               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2676           /* We can't overwrite I2DEST if its value is still used by
2677              NEWPAT.  */
2678           && ! reg_referenced_p (i2dest, newpat))
2679         {
2680           rtx newdest = i2dest;
2681           enum rtx_code split_code = GET_CODE (*split);
2682           enum machine_mode split_mode = GET_MODE (*split);
2683           bool subst_done = false;
2684           newi2pat = NULL_RTX;
2685
2686           /* Get NEWDEST as a register in the proper mode.  We have already
2687              validated that we can do this.  */
2688           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2689             {
2690               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2691                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2692               else
2693                 {
2694                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2695                   newdest = regno_reg_rtx[REGNO (i2dest)];
2696                 }
2697             }
2698
2699           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2700              an ASHIFT.  This can occur if it was inside a PLUS and hence
2701              appeared to be a memory address.  This is a kludge.  */
2702           if (split_code == MULT
2703               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2704               && INTVAL (XEXP (*split, 1)) > 0
2705               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2706             {
2707               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2708                                              XEXP (*split, 0), GEN_INT (i)));
2709               /* Update split_code because we may not have a multiply
2710                  anymore.  */
2711               split_code = GET_CODE (*split);
2712             }
2713
2714 #ifdef INSN_SCHEDULING
2715           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2716              be written as a ZERO_EXTEND.  */
2717           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2718             {
2719 #ifdef LOAD_EXTEND_OP
2720               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2721                  what it really is.  */
2722               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2723                   == SIGN_EXTEND)
2724                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2725                                                     SUBREG_REG (*split)));
2726               else
2727 #endif
2728                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2729                                                     SUBREG_REG (*split)));
2730             }
2731 #endif
2732
2733           /* Attempt to split binary operators using arithmetic identities.  */
2734           if (BINARY_P (SET_SRC (newpat))
2735               && split_mode == GET_MODE (SET_SRC (newpat))
2736               && ! side_effects_p (SET_SRC (newpat)))
2737             {
2738               rtx setsrc = SET_SRC (newpat);
2739               enum machine_mode mode = GET_MODE (setsrc);
2740               enum rtx_code code = GET_CODE (setsrc);
2741               rtx src_op0 = XEXP (setsrc, 0);
2742               rtx src_op1 = XEXP (setsrc, 1);
2743
2744               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
2745               if (rtx_equal_p (src_op0, src_op1))
2746                 {
2747                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2748                   SUBST (XEXP (setsrc, 0), newdest);
2749                   SUBST (XEXP (setsrc, 1), newdest);
2750                   subst_done = true;
2751                 }
2752               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
2753               else if ((code == PLUS || code == MULT)
2754                        && GET_CODE (src_op0) == code
2755                        && GET_CODE (XEXP (src_op0, 0)) == code
2756                        && (INTEGRAL_MODE_P (mode)
2757                            || (FLOAT_MODE_P (mode)
2758                                && flag_unsafe_math_optimizations)))
2759                 {
2760                   rtx p = XEXP (XEXP (src_op0, 0), 0);
2761                   rtx q = XEXP (XEXP (src_op0, 0), 1);
2762                   rtx r = XEXP (src_op0, 1);
2763                   rtx s = src_op1;
2764
2765                   /* Split both "((X op Y) op X) op Y" and
2766                      "((X op Y) op Y) op X" as "T op T" where T is
2767                      "X op Y".  */
2768                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2769                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2770                     {
2771                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
2772                                               XEXP (src_op0, 0));
2773                       SUBST (XEXP (setsrc, 0), newdest);
2774                       SUBST (XEXP (setsrc, 1), newdest);
2775                       subst_done = true;
2776                     }
2777                   /* Split "((X op X) op Y) op Y)" as "T op T" where
2778                      T is "X op Y".  */
2779                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2780                     {
2781                       rtx tmp = simplify_gen_binary (code, mode, p, r);
2782                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2783                       SUBST (XEXP (setsrc, 0), newdest);
2784                       SUBST (XEXP (setsrc, 1), newdest);
2785                       subst_done = true;
2786                     }
2787                 }
2788             }
2789
2790           if (!subst_done)
2791             {
2792               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2793               SUBST (*split, newdest);
2794             }
2795
2796           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2797
2798           /* recog_for_combine might have added CLOBBERs to newi2pat.
2799              Make sure NEWPAT does not depend on the clobbered regs.  */
2800           if (GET_CODE (newi2pat) == PARALLEL)
2801             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2802               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2803                 {
2804                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2805                   if (reg_overlap_mentioned_p (reg, newpat))
2806                     {
2807                       undo_all ();
2808                       return 0;
2809                     }
2810                 }
2811
2812           /* If the split point was a MULT and we didn't have one before,
2813              don't use one now.  */
2814           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2815             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2816         }
2817     }
2818
2819   /* Check for a case where we loaded from memory in a narrow mode and
2820      then sign extended it, but we need both registers.  In that case,
2821      we have a PARALLEL with both loads from the same memory location.
2822      We can split this into a load from memory followed by a register-register
2823      copy.  This saves at least one insn, more if register allocation can
2824      eliminate the copy.
2825
2826      We cannot do this if the destination of the first assignment is a
2827      condition code register or cc0.  We eliminate this case by making sure
2828      the SET_DEST and SET_SRC have the same mode.
2829
2830      We cannot do this if the destination of the second assignment is
2831      a register that we have already assumed is zero-extended.  Similarly
2832      for a SUBREG of such a register.  */
2833
2834   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2835            && GET_CODE (newpat) == PARALLEL
2836            && XVECLEN (newpat, 0) == 2
2837            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2838            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2839            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2840                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2841            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2842            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2843                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2844            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2845                                    INSN_CUID (i2))
2846            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2847            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2848            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2849                  (REG_P (temp)
2850                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2851                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2852                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2853                   && (reg_stat[REGNO (temp)].nonzero_bits
2854                       != GET_MODE_MASK (word_mode))))
2855            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2856                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2857                      (REG_P (temp)
2858                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2859                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2860                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2861                       && (reg_stat[REGNO (temp)].nonzero_bits
2862                           != GET_MODE_MASK (word_mode)))))
2863            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2864                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2865            && ! find_reg_note (i3, REG_UNUSED,
2866                                SET_DEST (XVECEXP (newpat, 0, 0))))
2867     {
2868       rtx ni2dest;
2869
2870       newi2pat = XVECEXP (newpat, 0, 0);
2871       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2872       newpat = XVECEXP (newpat, 0, 1);
2873       SUBST (SET_SRC (newpat),
2874              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2875       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2876
2877       if (i2_code_number >= 0)
2878         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2879
2880       if (insn_code_number >= 0)
2881         swap_i2i3 = 1;
2882     }
2883
2884   /* Similarly, check for a case where we have a PARALLEL of two independent
2885      SETs but we started with three insns.  In this case, we can do the sets
2886      as two separate insns.  This case occurs when some SET allows two
2887      other insns to combine, but the destination of that SET is still live.  */
2888
2889   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2890            && GET_CODE (newpat) == PARALLEL
2891            && XVECLEN (newpat, 0) == 2
2892            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2893            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2894            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2895            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2896            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2897            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2898            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2899                                    INSN_CUID (i2))
2900            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2901                                   XVECEXP (newpat, 0, 0))
2902            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2903                                   XVECEXP (newpat, 0, 1))
2904            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2905                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2906     {
2907       /* Normally, it doesn't matter which of the two is done first,
2908          but it does if one references cc0.  In that case, it has to
2909          be first.  */
2910 #ifdef HAVE_cc0
2911       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2912         {
2913           newi2pat = XVECEXP (newpat, 0, 0);
2914           newpat = XVECEXP (newpat, 0, 1);
2915         }
2916       else
2917 #endif
2918         {
2919           newi2pat = XVECEXP (newpat, 0, 1);
2920           newpat = XVECEXP (newpat, 0, 0);
2921         }
2922
2923       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2924
2925       if (i2_code_number >= 0)
2926         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2927     }
2928
2929   /* If it still isn't recognized, fail and change things back the way they
2930      were.  */
2931   if ((insn_code_number < 0
2932        /* Is the result a reasonable ASM_OPERANDS?  */
2933        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2934     {
2935       undo_all ();
2936       return 0;
2937     }
2938
2939   /* If we had to change another insn, make sure it is valid also.  */
2940   if (undobuf.other_insn)
2941     {
2942       rtx other_pat = PATTERN (undobuf.other_insn);
2943       rtx new_other_notes;
2944       rtx note, next;
2945
2946       CLEAR_HARD_REG_SET (newpat_used_regs);
2947
2948       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2949                                              &new_other_notes);
2950
2951       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2952         {
2953           undo_all ();
2954           return 0;
2955         }
2956
2957       PATTERN (undobuf.other_insn) = other_pat;
2958
2959       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2960          are still valid.  Then add any non-duplicate notes added by
2961          recog_for_combine.  */
2962       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2963         {
2964           next = XEXP (note, 1);
2965
2966           if (REG_NOTE_KIND (note) == REG_UNUSED
2967               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2968             {
2969               if (REG_P (XEXP (note, 0)))
2970                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2971
2972               remove_note (undobuf.other_insn, note);
2973             }
2974         }
2975
2976       for (note = new_other_notes; note; note = XEXP (note, 1))
2977         if (REG_P (XEXP (note, 0)))
2978           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2979
2980       distribute_notes (new_other_notes, undobuf.other_insn,
2981                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2982     }
2983 #ifdef HAVE_cc0
2984   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2985      they are adjacent to each other or not.  */
2986   {
2987     rtx p = prev_nonnote_insn (i3);
2988     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2989         && sets_cc0_p (newi2pat))
2990       {
2991         undo_all ();
2992         return 0;
2993       }
2994   }
2995 #endif
2996
2997   /* Only allow this combination if insn_rtx_costs reports that the
2998      replacement instructions are cheaper than the originals.  */
2999   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
3000     {
3001       undo_all ();
3002       return 0;
3003     }
3004
3005   /* We now know that we can do this combination.  Merge the insns and
3006      update the status of registers and LOG_LINKS.  */
3007
3008   if (swap_i2i3)
3009     {
3010       rtx insn;
3011       rtx link;
3012       rtx ni2dest;
3013
3014       /* I3 now uses what used to be its destination and which is now
3015          I2's destination.  This requires us to do a few adjustments.  */
3016       PATTERN (i3) = newpat;
3017       adjust_for_new_dest (i3);
3018
3019       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3020          so we still will.
3021
3022          However, some later insn might be using I2's dest and have
3023          a LOG_LINK pointing at I3.  We must remove this link.
3024          The simplest way to remove the link is to point it at I1,
3025          which we know will be a NOTE.  */
3026
3027       /* newi2pat is usually a SET here; however, recog_for_combine might
3028          have added some clobbers.  */
3029       if (GET_CODE (newi2pat) == PARALLEL)
3030         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3031       else
3032         ni2dest = SET_DEST (newi2pat);
3033
3034       for (insn = NEXT_INSN (i3);
3035            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3036                     || insn != BB_HEAD (this_basic_block->next_bb));
3037            insn = NEXT_INSN (insn))
3038         {
3039           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3040             {
3041               for (link = LOG_LINKS (insn); link;
3042                    link = XEXP (link, 1))
3043                 if (XEXP (link, 0) == i3)
3044                   XEXP (link, 0) = i1;
3045
3046               break;
3047             }
3048         }
3049     }
3050
3051   {
3052     rtx i3notes, i2notes, i1notes = 0;
3053     rtx i3links, i2links, i1links = 0;
3054     rtx midnotes = 0;
3055     unsigned int regno;
3056     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3057        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3058        same as i3dest, in which case newi2pat may be setting i1dest.  */
3059     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3060                    || i2dest_in_i2src || i2dest_in_i1src
3061                    || !i2dest_killed
3062                    ? 0 : i2dest);
3063     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3064                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3065                    || !i1dest_killed
3066                    ? 0 : i1dest);
3067
3068     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3069        clear them.  */
3070     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3071     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3072     if (i1)
3073       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3074
3075     /* Ensure that we do not have something that should not be shared but
3076        occurs multiple times in the new insns.  Check this by first
3077        resetting all the `used' flags and then copying anything is shared.  */
3078
3079     reset_used_flags (i3notes);
3080     reset_used_flags (i2notes);
3081     reset_used_flags (i1notes);
3082     reset_used_flags (newpat);
3083     reset_used_flags (newi2pat);
3084     if (undobuf.other_insn)
3085       reset_used_flags (PATTERN (undobuf.other_insn));
3086
3087     i3notes = copy_rtx_if_shared (i3notes);
3088     i2notes = copy_rtx_if_shared (i2notes);
3089     i1notes = copy_rtx_if_shared (i1notes);
3090     newpat = copy_rtx_if_shared (newpat);
3091     newi2pat = copy_rtx_if_shared (newi2pat);
3092     if (undobuf.other_insn)
3093       reset_used_flags (PATTERN (undobuf.other_insn));
3094
3095     INSN_CODE (i3) = insn_code_number;
3096     PATTERN (i3) = newpat;
3097
3098     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3099       {
3100         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3101
3102         reset_used_flags (call_usage);
3103         call_usage = copy_rtx (call_usage);
3104
3105         if (substed_i2)
3106           replace_rtx (call_usage, i2dest, i2src);
3107
3108         if (substed_i1)
3109           replace_rtx (call_usage, i1dest, i1src);
3110
3111         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3112       }
3113
3114     if (undobuf.other_insn)
3115       INSN_CODE (undobuf.other_insn) = other_code_number;
3116
3117     /* We had one special case above where I2 had more than one set and
3118        we replaced a destination of one of those sets with the destination
3119        of I3.  In that case, we have to update LOG_LINKS of insns later
3120        in this basic block.  Note that this (expensive) case is rare.
3121
3122        Also, in this case, we must pretend that all REG_NOTEs for I2
3123        actually came from I3, so that REG_UNUSED notes from I2 will be
3124        properly handled.  */
3125
3126     if (i3_subst_into_i2)
3127       {
3128         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3129           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3130                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3131               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3132               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3133               && ! find_reg_note (i2, REG_UNUSED,
3134                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3135             for (temp = NEXT_INSN (i2);
3136                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3137                           || BB_HEAD (this_basic_block) != temp);
3138                  temp = NEXT_INSN (temp))
3139               if (temp != i3 && INSN_P (temp))
3140                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3141                   if (XEXP (link, 0) == i2)
3142                     XEXP (link, 0) = i3;
3143
3144         if (i3notes)
3145           {
3146             rtx link = i3notes;
3147             while (XEXP (link, 1))
3148               link = XEXP (link, 1);
3149             XEXP (link, 1) = i2notes;
3150           }
3151         else
3152           i3notes = i2notes;
3153         i2notes = 0;
3154       }
3155
3156     LOG_LINKS (i3) = 0;
3157     REG_NOTES (i3) = 0;
3158     LOG_LINKS (i2) = 0;
3159     REG_NOTES (i2) = 0;
3160
3161     if (newi2pat)
3162       {
3163         INSN_CODE (i2) = i2_code_number;
3164         PATTERN (i2) = newi2pat;
3165       }
3166     else
3167       SET_INSN_DELETED (i2);
3168
3169     if (i1)
3170       {
3171         LOG_LINKS (i1) = 0;
3172         REG_NOTES (i1) = 0;
3173         SET_INSN_DELETED (i1);
3174       }
3175
3176     /* Get death notes for everything that is now used in either I3 or
3177        I2 and used to die in a previous insn.  If we built two new
3178        patterns, move from I1 to I2 then I2 to I3 so that we get the
3179        proper movement on registers that I2 modifies.  */
3180
3181     if (newi2pat)
3182       {
3183         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3184         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3185       }
3186     else
3187       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3188                    i3, &midnotes);
3189
3190     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3191     if (i3notes)
3192       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3193                         elim_i2, elim_i1);
3194     if (i2notes)
3195       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3196                         elim_i2, elim_i1);
3197     if (i1notes)
3198       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3199                         elim_i2, elim_i1);
3200     if (midnotes)
3201       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3202                         elim_i2, elim_i1);
3203
3204     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3205        know these are REG_UNUSED and want them to go to the desired insn,
3206        so we always pass it as i3.  We have not counted the notes in
3207        reg_n_deaths yet, so we need to do so now.  */
3208
3209     if (newi2pat && new_i2_notes)
3210       {
3211         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3212           if (REG_P (XEXP (temp, 0)))
3213             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3214
3215         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3216       }
3217
3218     if (new_i3_notes)
3219       {
3220         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3221           if (REG_P (XEXP (temp, 0)))
3222             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3223
3224         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3225       }
3226
3227     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3228        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3229        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3230        in that case, it might delete I2.  Similarly for I2 and I1.
3231        Show an additional death due to the REG_DEAD note we make here.  If
3232        we discard it in distribute_notes, we will decrement it again.  */
3233
3234     if (i3dest_killed)
3235       {
3236         if (REG_P (i3dest_killed))
3237           REG_N_DEATHS (REGNO (i3dest_killed))++;
3238
3239         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3240           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3241                                                NULL_RTX),
3242                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3243         else
3244           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3245                                                NULL_RTX),
3246                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3247                             elim_i2, elim_i1);
3248       }
3249
3250     if (i2dest_in_i2src)
3251       {
3252         if (REG_P (i2dest))
3253           REG_N_DEATHS (REGNO (i2dest))++;
3254
3255         if (newi2pat && reg_set_p (i2dest, newi2pat))
3256           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3257                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3258         else
3259           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3260                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3261                             NULL_RTX, NULL_RTX);
3262       }
3263
3264     if (i1dest_in_i1src)
3265       {
3266         if (REG_P (i1dest))
3267           REG_N_DEATHS (REGNO (i1dest))++;
3268
3269         if (newi2pat && reg_set_p (i1dest, newi2pat))
3270           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3271                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3272         else
3273           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3274                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3275                             NULL_RTX, NULL_RTX);
3276       }
3277
3278     distribute_links (i3links);
3279     distribute_links (i2links);
3280     distribute_links (i1links);
3281
3282     if (REG_P (i2dest))
3283       {
3284         rtx link;
3285         rtx i2_insn = 0, i2_val = 0, set;
3286
3287         /* The insn that used to set this register doesn't exist, and
3288            this life of the register may not exist either.  See if one of
3289            I3's links points to an insn that sets I2DEST.  If it does,
3290            that is now the last known value for I2DEST. If we don't update
3291            this and I2 set the register to a value that depended on its old
3292            contents, we will get confused.  If this insn is used, thing
3293            will be set correctly in combine_instructions.  */
3294
3295         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3296           if ((set = single_set (XEXP (link, 0))) != 0
3297               && rtx_equal_p (i2dest, SET_DEST (set)))
3298             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3299
3300         record_value_for_reg (i2dest, i2_insn, i2_val);
3301
3302         /* If the reg formerly set in I2 died only once and that was in I3,
3303            zero its use count so it won't make `reload' do any work.  */
3304         if (! added_sets_2
3305             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3306             && ! i2dest_in_i2src)
3307           {
3308             regno = REGNO (i2dest);
3309             REG_N_SETS (regno)--;
3310           }
3311       }
3312
3313     if (i1 && REG_P (i1dest))
3314       {
3315         rtx link;
3316         rtx i1_insn = 0, i1_val = 0, set;
3317
3318         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3319           if ((set = single_set (XEXP (link, 0))) != 0
3320               && rtx_equal_p (i1dest, SET_DEST (set)))
3321             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3322
3323         record_value_for_reg (i1dest, i1_insn, i1_val);
3324
3325         regno = REGNO (i1dest);
3326         if (! added_sets_1 && ! i1dest_in_i1src)
3327           REG_N_SETS (regno)--;
3328       }
3329
3330     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3331        been made to this insn.  The order of
3332        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3333        can affect nonzero_bits of newpat */
3334     if (newi2pat)
3335       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3336     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3337
3338     /* Set new_direct_jump_p if a new return or simple jump instruction
3339        has been created.
3340
3341        If I3 is now an unconditional jump, ensure that it has a
3342        BARRIER following it since it may have initially been a
3343        conditional jump.  It may also be the last nonnote insn.  */
3344
3345     if (returnjump_p (i3) || any_uncondjump_p (i3))
3346       {
3347         *new_direct_jump_p = 1;
3348         mark_jump_label (PATTERN (i3), i3, 0);
3349
3350         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3351             || !BARRIER_P (temp))
3352           emit_barrier_after (i3);
3353       }
3354
3355     if (undobuf.other_insn != NULL_RTX
3356         && (returnjump_p (undobuf.other_insn)
3357             || any_uncondjump_p (undobuf.other_insn)))
3358       {
3359         *new_direct_jump_p = 1;
3360
3361         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3362             || !BARRIER_P (temp))
3363           emit_barrier_after (undobuf.other_insn);
3364       }
3365
3366     /* An NOOP jump does not need barrier, but it does need cleaning up
3367        of CFG.  */
3368     if (GET_CODE (newpat) == SET
3369         && SET_SRC (newpat) == pc_rtx
3370         && SET_DEST (newpat) == pc_rtx)
3371       *new_direct_jump_p = 1;
3372   }
3373
3374   combine_successes++;
3375   undo_commit ();
3376
3377   if (added_links_insn
3378       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3379       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3380     return added_links_insn;
3381   else
3382     return newi2pat ? i2 : i3;
3383 }
3384 \f
3385 /* Undo all the modifications recorded in undobuf.  */
3386
3387 static void
3388 undo_all (void)
3389 {
3390   struct undo *undo, *next;
3391
3392   for (undo = undobuf.undos; undo; undo = next)
3393     {
3394       next = undo->next;
3395       switch (undo->kind)
3396         {
3397         case UNDO_RTX:
3398           *undo->where.r = undo->old_contents.r;
3399           break;
3400         case UNDO_INT:
3401           *undo->where.i = undo->old_contents.i;
3402           break;
3403         case UNDO_MODE:
3404           PUT_MODE (*undo->where.r, undo->old_contents.m);
3405           break;
3406         default:
3407           gcc_unreachable ();
3408         }
3409
3410       undo->next = undobuf.frees;
3411       undobuf.frees = undo;
3412     }
3413
3414   undobuf.undos = 0;
3415 }
3416
3417 /* We've committed to accepting the changes we made.  Move all
3418    of the undos to the free list.  */
3419
3420 static void
3421 undo_commit (void)
3422 {
3423   struct undo *undo, *next;
3424
3425   for (undo = undobuf.undos; undo; undo = next)
3426     {
3427       next = undo->next;
3428       undo->next = undobuf.frees;
3429       undobuf.frees = undo;
3430     }
3431   undobuf.undos = 0;
3432 }
3433
3434 \f
3435 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3436    where we have an arithmetic expression and return that point.  LOC will
3437    be inside INSN.
3438
3439    try_combine will call this function to see if an insn can be split into
3440    two insns.  */
3441
3442 static rtx *
3443 find_split_point (rtx *loc, rtx insn)
3444 {
3445   rtx x = *loc;
3446   enum rtx_code code = GET_CODE (x);
3447   rtx *split;
3448   unsigned HOST_WIDE_INT len = 0;
3449   HOST_WIDE_INT pos = 0;
3450   int unsignedp = 0;
3451   rtx inner = NULL_RTX;
3452
3453   /* First special-case some codes.  */
3454   switch (code)
3455     {
3456     case SUBREG:
3457 #ifdef INSN_SCHEDULING
3458       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3459          point.  */
3460       if (MEM_P (SUBREG_REG (x)))
3461         return loc;
3462 #endif
3463       return find_split_point (&SUBREG_REG (x), insn);
3464
3465     case MEM:
3466 #ifdef HAVE_lo_sum
3467       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3468          using LO_SUM and HIGH.  */
3469       if (GET_CODE (XEXP (x, 0)) == CONST
3470           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3471         {
3472           SUBST (XEXP (x, 0),
3473                  gen_rtx_LO_SUM (Pmode,
3474                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3475                                  XEXP (x, 0)));
3476           return &XEXP (XEXP (x, 0), 0);
3477         }
3478 #endif
3479
3480       /* If we have a PLUS whose second operand is a constant and the
3481          address is not valid, perhaps will can split it up using
3482          the machine-specific way to split large constants.  We use
3483          the first pseudo-reg (one of the virtual regs) as a placeholder;
3484          it will not remain in the result.  */
3485       if (GET_CODE (XEXP (x, 0)) == PLUS
3486           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3487           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3488         {
3489           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3490           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3491                                  subst_insn);
3492
3493           /* This should have produced two insns, each of which sets our
3494              placeholder.  If the source of the second is a valid address,
3495              we can make put both sources together and make a split point
3496              in the middle.  */
3497
3498           if (seq
3499               && NEXT_INSN (seq) != NULL_RTX
3500               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3501               && NONJUMP_INSN_P (seq)
3502               && GET_CODE (PATTERN (seq)) == SET
3503               && SET_DEST (PATTERN (seq)) == reg
3504               && ! reg_mentioned_p (reg,
3505                                     SET_SRC (PATTERN (seq)))
3506               && NONJUMP_INSN_P (NEXT_INSN (seq))
3507               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3508               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3509               && memory_address_p (GET_MODE (x),
3510                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3511             {
3512               rtx src1 = SET_SRC (PATTERN (seq));
3513               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3514
3515               /* Replace the placeholder in SRC2 with SRC1.  If we can
3516                  find where in SRC2 it was placed, that can become our
3517                  split point and we can replace this address with SRC2.
3518                  Just try two obvious places.  */
3519
3520               src2 = replace_rtx (src2, reg, src1);
3521               split = 0;
3522               if (XEXP (src2, 0) == src1)
3523                 split = &XEXP (src2, 0);
3524               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3525                        && XEXP (XEXP (src2, 0), 0) == src1)
3526                 split = &XEXP (XEXP (src2, 0), 0);
3527
3528               if (split)
3529                 {
3530                   SUBST (XEXP (x, 0), src2);
3531                   return split;
3532                 }
3533             }
3534
3535           /* If that didn't work, perhaps the first operand is complex and
3536              needs to be computed separately, so make a split point there.
3537              This will occur on machines that just support REG + CONST
3538              and have a constant moved through some previous computation.  */
3539
3540           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3541                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3542                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3543             return &XEXP (XEXP (x, 0), 0);
3544         }
3545       break;
3546
3547     case SET:
3548 #ifdef HAVE_cc0
3549       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3550          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3551          we need to put the operand into a register.  So split at that
3552          point.  */
3553
3554       if (SET_DEST (x) == cc0_rtx
3555           && GET_CODE (SET_SRC (x)) != COMPARE
3556           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3557           && !OBJECT_P (SET_SRC (x))
3558           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3559                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3560         return &SET_SRC (x);
3561 #endif
3562
3563       /* See if we can split SET_SRC as it stands.  */
3564       split = find_split_point (&SET_SRC (x), insn);
3565       if (split && split != &SET_SRC (x))
3566         return split;
3567
3568       /* See if we can split SET_DEST as it stands.  */
3569       split = find_split_point (&SET_DEST (x), insn);
3570       if (split && split != &SET_DEST (x))
3571         return split;
3572
3573       /* See if this is a bitfield assignment with everything constant.  If
3574          so, this is an IOR of an AND, so split it into that.  */
3575       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3576           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3577               <= HOST_BITS_PER_WIDE_INT)
3578           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3579           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3580           && GET_CODE (SET_SRC (x)) == CONST_INT
3581           && ((INTVAL (XEXP (SET_DEST (x), 1))
3582                + INTVAL (XEXP (SET_DEST (x), 2)))
3583               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3584           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3585         {
3586           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3587           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3588           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3589           rtx dest = XEXP (SET_DEST (x), 0);
3590           enum machine_mode mode = GET_MODE (dest);
3591           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3592           rtx or_mask;
3593
3594           if (BITS_BIG_ENDIAN)
3595             pos = GET_MODE_BITSIZE (mode) - len - pos;
3596
3597           or_mask = gen_int_mode (src << pos, mode);
3598           if (src == mask)
3599             SUBST (SET_SRC (x),
3600                    simplify_gen_binary (IOR, mode, dest, or_mask));
3601           else
3602             {
3603               rtx negmask = gen_int_mode (~(mask << pos), mode);
3604               SUBST (SET_SRC (x),
3605                      simplify_gen_binary (IOR, mode,
3606                                           simplify_gen_binary (AND, mode,
3607                                                                dest, negmask),
3608                                           or_mask));
3609             }
3610
3611           SUBST (SET_DEST (x), dest);
3612
3613           split = find_split_point (&SET_SRC (x), insn);
3614           if (split && split != &SET_SRC (x))
3615             return split;
3616         }
3617
3618       /* Otherwise, see if this is an operation that we can split into two.
3619          If so, try to split that.  */
3620       code = GET_CODE (SET_SRC (x));
3621
3622       switch (code)
3623         {
3624         case AND:
3625           /* If we are AND'ing with a large constant that is only a single
3626              bit and the result is only being used in a context where we
3627              need to know if it is zero or nonzero, replace it with a bit
3628              extraction.  This will avoid the large constant, which might
3629              have taken more than one insn to make.  If the constant were
3630              not a valid argument to the AND but took only one insn to make,
3631              this is no worse, but if it took more than one insn, it will
3632              be better.  */
3633
3634           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3635               && REG_P (XEXP (SET_SRC (x), 0))
3636               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3637               && REG_P (SET_DEST (x))
3638               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3639               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3640               && XEXP (*split, 0) == SET_DEST (x)
3641               && XEXP (*split, 1) == const0_rtx)
3642             {
3643               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3644                                                 XEXP (SET_SRC (x), 0),
3645                                                 pos, NULL_RTX, 1, 1, 0, 0);
3646               if (extraction != 0)
3647                 {
3648                   SUBST (SET_SRC (x), extraction);
3649                   return find_split_point (loc, insn);
3650                 }
3651             }
3652           break;
3653
3654         case NE:
3655           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3656              is known to be on, this can be converted into a NEG of a shift.  */
3657           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3658               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3659               && 1 <= (pos = exact_log2
3660                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3661                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3662             {
3663               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3664
3665               SUBST (SET_SRC (x),
3666                      gen_rtx_NEG (mode,
3667                                   gen_rtx_LSHIFTRT (mode,
3668                                                     XEXP (SET_SRC (x), 0),
3669                                                     GEN_INT (pos))));
3670
3671               split = find_split_point (&SET_SRC (x), insn);
3672               if (split && split != &SET_SRC (x))
3673                 return split;
3674             }
3675           break;
3676
3677         case SIGN_EXTEND:
3678           inner = XEXP (SET_SRC (x), 0);
3679
3680           /* We can't optimize if either mode is a partial integer
3681              mode as we don't know how many bits are significant
3682              in those modes.  */
3683           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3684               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3685             break;
3686
3687           pos = 0;
3688           len = GET_MODE_BITSIZE (GET_MODE (inner));
3689           unsignedp = 0;
3690           break;
3691
3692         case SIGN_EXTRACT:
3693         case ZERO_EXTRACT:
3694           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3695               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3696             {
3697               inner = XEXP (SET_SRC (x), 0);
3698               len = INTVAL (XEXP (SET_SRC (x), 1));
3699               pos = INTVAL (XEXP (SET_SRC (x), 2));
3700
3701               if (BITS_BIG_ENDIAN)
3702                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3703               unsignedp = (code == ZERO_EXTRACT);
3704             }
3705           break;
3706
3707         default:
3708           break;
3709         }
3710
3711       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3712         {
3713           enum machine_mode mode = GET_MODE (SET_SRC (x));
3714
3715           /* For unsigned, we have a choice of a shift followed by an
3716              AND or two shifts.  Use two shifts for field sizes where the
3717              constant might be too large.  We assume here that we can
3718              always at least get 8-bit constants in an AND insn, which is
3719              true for every current RISC.  */
3720
3721           if (unsignedp && len <= 8)
3722             {
3723               SUBST (SET_SRC (x),
3724                      gen_rtx_AND (mode,
3725                                   gen_rtx_LSHIFTRT
3726                                   (mode, gen_lowpart (mode, inner),
3727                                    GEN_INT (pos)),
3728                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3729
3730               split = find_split_point (&SET_SRC (x), insn);
3731               if (split && split != &SET_SRC (x))
3732                 return split;
3733             }
3734           else
3735             {
3736               SUBST (SET_SRC (x),
3737                      gen_rtx_fmt_ee
3738                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3739                       gen_rtx_ASHIFT (mode,
3740                                       gen_lowpart (mode, inner),
3741                                       GEN_INT (GET_MODE_BITSIZE (mode)
3742                                                - len - pos)),
3743                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3744
3745               split = find_split_point (&SET_SRC (x), insn);
3746               if (split && split != &SET_SRC (x))
3747                 return split;
3748             }
3749         }
3750
3751       /* See if this is a simple operation with a constant as the second
3752          operand.  It might be that this constant is out of range and hence
3753          could be used as a split point.  */
3754       if (BINARY_P (SET_SRC (x))
3755           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3756           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3757               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3758                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3759         return &XEXP (SET_SRC (x), 1);
3760
3761       /* Finally, see if this is a simple operation with its first operand
3762          not in a register.  The operation might require this operand in a
3763          register, so return it as a split point.  We can always do this
3764          because if the first operand were another operation, we would have
3765          already found it as a split point.  */
3766       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3767           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3768         return &XEXP (SET_SRC (x), 0);
3769
3770       return 0;
3771
3772     case AND:
3773     case IOR:
3774       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3775          it is better to write this as (not (ior A B)) so we can split it.
3776          Similarly for IOR.  */
3777       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3778         {
3779           SUBST (*loc,
3780                  gen_rtx_NOT (GET_MODE (x),
3781                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3782                                               GET_MODE (x),
3783                                               XEXP (XEXP (x, 0), 0),
3784                                               XEXP (XEXP (x, 1), 0))));
3785           return find_split_point (loc, insn);
3786         }
3787
3788       /* Many RISC machines have a large set of logical insns.  If the
3789          second operand is a NOT, put it first so we will try to split the
3790          other operand first.  */
3791       if (GET_CODE (XEXP (x, 1)) == NOT)
3792         {
3793           rtx tem = XEXP (x, 0);
3794           SUBST (XEXP (x, 0), XEXP (x, 1));
3795           SUBST (XEXP (x, 1), tem);
3796         }
3797       break;
3798
3799     default:
3800       break;
3801     }
3802
3803   /* Otherwise, select our actions depending on our rtx class.  */
3804   switch (GET_RTX_CLASS (code))
3805     {
3806     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3807     case RTX_TERNARY:
3808       split = find_split_point (&XEXP (x, 2), insn);
3809       if (split)
3810         return split;
3811       /* ... fall through ...  */
3812     case RTX_BIN_ARITH:
3813     case RTX_COMM_ARITH:
3814     case RTX_COMPARE:
3815     case RTX_COMM_COMPARE:
3816       split = find_split_point (&XEXP (x, 1), insn);
3817       if (split)
3818         return split;
3819       /* ... fall through ...  */
3820     case RTX_UNARY:
3821       /* Some machines have (and (shift ...) ...) insns.  If X is not
3822          an AND, but XEXP (X, 0) is, use it as our split point.  */
3823       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3824         return &XEXP (x, 0);
3825
3826       split = find_split_point (&XEXP (x, 0), insn);
3827       if (split)
3828         return split;
3829       return loc;
3830
3831     default:
3832       /* Otherwise, we don't have a split point.  */
3833       return 0;
3834     }
3835 }
3836 \f
3837 /* Throughout X, replace FROM with TO, and return the result.
3838    The result is TO if X is FROM;
3839    otherwise the result is X, but its contents may have been modified.
3840    If they were modified, a record was made in undobuf so that
3841    undo_all will (among other things) return X to its original state.
3842
3843    If the number of changes necessary is too much to record to undo,
3844    the excess changes are not made, so the result is invalid.
3845    The changes already made can still be undone.
3846    undobuf.num_undo is incremented for such changes, so by testing that
3847    the caller can tell whether the result is valid.
3848
3849    `n_occurrences' is incremented each time FROM is replaced.
3850
3851    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3852
3853    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3854    by copying if `n_occurrences' is nonzero.  */
3855
3856 static rtx
3857 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3858 {
3859   enum rtx_code code = GET_CODE (x);
3860   enum machine_mode op0_mode = VOIDmode;
3861   const char *fmt;
3862   int len, i;
3863   rtx new;
3864
3865 /* Two expressions are equal if they are identical copies of a shared
3866    RTX or if they are both registers with the same register number
3867    and mode.  */
3868
3869 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3870   ((X) == (Y)                                           \
3871    || (REG_P (X) && REG_P (Y)   \
3872        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3873
3874   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3875     {
3876       n_occurrences++;
3877       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3878     }
3879
3880   /* If X and FROM are the same register but different modes, they will
3881      not have been seen as equal above.  However, flow.c will make a
3882      LOG_LINKS entry for that case.  If we do nothing, we will try to
3883      rerecognize our original insn and, when it succeeds, we will
3884      delete the feeding insn, which is incorrect.
3885
3886      So force this insn not to match in this (rare) case.  */
3887   if (! in_dest && code == REG && REG_P (from)
3888       && REGNO (x) == REGNO (from))
3889     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3890
3891   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3892      of which may contain things that can be combined.  */
3893   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3894     return x;
3895
3896   /* It is possible to have a subexpression appear twice in the insn.
3897      Suppose that FROM is a register that appears within TO.
3898      Then, after that subexpression has been scanned once by `subst',
3899      the second time it is scanned, TO may be found.  If we were
3900      to scan TO here, we would find FROM within it and create a
3901      self-referent rtl structure which is completely wrong.  */
3902   if (COMBINE_RTX_EQUAL_P (x, to))
3903     return to;
3904
3905   /* Parallel asm_operands need special attention because all of the
3906      inputs are shared across the arms.  Furthermore, unsharing the
3907      rtl results in recognition failures.  Failure to handle this case
3908      specially can result in circular rtl.
3909
3910      Solve this by doing a normal pass across the first entry of the
3911      parallel, and only processing the SET_DESTs of the subsequent
3912      entries.  Ug.  */
3913
3914   if (code == PARALLEL
3915       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3916       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3917     {
3918       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3919
3920       /* If this substitution failed, this whole thing fails.  */
3921       if (GET_CODE (new) == CLOBBER
3922           && XEXP (new, 0) == const0_rtx)
3923         return new;
3924
3925       SUBST (XVECEXP (x, 0, 0), new);
3926
3927       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3928         {
3929           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3930
3931           if (!REG_P (dest)
3932               && GET_CODE (dest) != CC0
3933               && GET_CODE (dest) != PC)
3934             {
3935               new = subst (dest, from, to, 0, unique_copy);
3936
3937               /* If this substitution failed, this whole thing fails.  */
3938               if (GET_CODE (new) == CLOBBER
3939                   && XEXP (new, 0) == const0_rtx)
3940                 return new;
3941
3942               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3943             }
3944         }
3945     }
3946   else
3947     {
3948       len = GET_RTX_LENGTH (code);
3949       fmt = GET_RTX_FORMAT (code);
3950
3951       /* We don't need to process a SET_DEST that is a register, CC0,
3952          or PC, so set up to skip this common case.  All other cases
3953          where we want to suppress replacing something inside a
3954          SET_SRC are handled via the IN_DEST operand.  */
3955       if (code == SET
3956           && (REG_P (SET_DEST (x))
3957               || GET_CODE (SET_DEST (x)) == CC0
3958               || GET_CODE (SET_DEST (x)) == PC))
3959         fmt = "ie";
3960
3961       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3962          constant.  */
3963       if (fmt[0] == 'e')
3964         op0_mode = GET_MODE (XEXP (x, 0));
3965
3966       for (i = 0; i < len; i++)
3967         {
3968           if (fmt[i] == 'E')
3969             {
3970               int j;
3971               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3972                 {
3973                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3974                     {
3975                       new = (unique_copy && n_occurrences
3976                              ? copy_rtx (to) : to);
3977                       n_occurrences++;
3978                     }
3979                   else
3980                     {
3981                       new = subst (XVECEXP (x, i, j), from, to, 0,
3982                                    unique_copy);
3983
3984                       /* If this substitution failed, this whole thing
3985                          fails.  */
3986                       if (GET_CODE (new) == CLOBBER
3987                           && XEXP (new, 0) == const0_rtx)
3988                         return new;
3989                     }
3990
3991                   SUBST (XVECEXP (x, i, j), new);
3992                 }
3993             }
3994           else if (fmt[i] == 'e')
3995             {
3996               /* If this is a register being set, ignore it.  */
3997               new = XEXP (x, i);
3998               if (in_dest
3999                   && i == 0
4000                   && (((code == SUBREG || code == ZERO_EXTRACT)
4001                        && REG_P (new))
4002                       || code == STRICT_LOW_PART))
4003                 ;
4004
4005               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4006                 {
4007                   /* In general, don't install a subreg involving two
4008                      modes not tieable.  It can worsen register
4009                      allocation, and can even make invalid reload
4010                      insns, since the reg inside may need to be copied
4011                      from in the outside mode, and that may be invalid
4012                      if it is an fp reg copied in integer mode.
4013
4014                      We allow two exceptions to this: It is valid if
4015                      it is inside another SUBREG and the mode of that
4016                      SUBREG and the mode of the inside of TO is
4017                      tieable and it is valid if X is a SET that copies
4018                      FROM to CC0.  */
4019
4020                   if (GET_CODE (to) == SUBREG
4021                       && ! MODES_TIEABLE_P (GET_MODE (to),
4022                                             GET_MODE (SUBREG_REG (to)))
4023                       && ! (code == SUBREG
4024                             && MODES_TIEABLE_P (GET_MODE (x),
4025                                                 GET_MODE (SUBREG_REG (to))))
4026 #ifdef HAVE_cc0
4027                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4028 #endif
4029                       )
4030                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4031
4032 #ifdef CANNOT_CHANGE_MODE_CLASS
4033                   if (code == SUBREG
4034                       && REG_P (to)
4035                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4036                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4037                                                    GET_MODE (to),
4038                                                    GET_MODE (x)))
4039                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4040 #endif
4041
4042                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4043                   n_occurrences++;
4044                 }
4045               else
4046                 /* If we are in a SET_DEST, suppress most cases unless we
4047                    have gone inside a MEM, in which case we want to
4048                    simplify the address.  We assume here that things that
4049                    are actually part of the destination have their inner
4050                    parts in the first expression.  This is true for SUBREG,
4051                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4052                    things aside from REG and MEM that should appear in a
4053                    SET_DEST.  */
4054                 new = subst (XEXP (x, i), from, to,
4055                              (((in_dest
4056                                 && (code == SUBREG || code == STRICT_LOW_PART
4057                                     || code == ZERO_EXTRACT))
4058                                || code == SET)
4059                               && i == 0), unique_copy);
4060
4061               /* If we found that we will have to reject this combination,
4062                  indicate that by returning the CLOBBER ourselves, rather than
4063                  an expression containing it.  This will speed things up as
4064                  well as prevent accidents where two CLOBBERs are considered
4065                  to be equal, thus producing an incorrect simplification.  */
4066
4067               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4068                 return new;
4069
4070               if (GET_CODE (x) == SUBREG
4071                   && (GET_CODE (new) == CONST_INT
4072                       || GET_CODE (new) == CONST_DOUBLE))
4073                 {
4074                   enum machine_mode mode = GET_MODE (x);
4075
4076                   x = simplify_subreg (GET_MODE (x), new,
4077                                        GET_MODE (SUBREG_REG (x)),
4078                                        SUBREG_BYTE (x));
4079                   if (! x)
4080                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4081                 }
4082               else if (GET_CODE (new) == CONST_INT
4083                        && GET_CODE (x) == ZERO_EXTEND)
4084                 {
4085                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4086                                                 new, GET_MODE (XEXP (x, 0)));
4087                   gcc_assert (x);
4088                 }
4089               else
4090                 SUBST (XEXP (x, i), new);
4091             }
4092         }
4093     }
4094
4095   /* Try to simplify X.  If the simplification changed the code, it is likely
4096      that further simplification will help, so loop, but limit the number
4097      of repetitions that will be performed.  */
4098
4099   for (i = 0; i < 4; i++)
4100     {
4101       /* If X is sufficiently simple, don't bother trying to do anything
4102          with it.  */
4103       if (code != CONST_INT && code != REG && code != CLOBBER)
4104         x = combine_simplify_rtx (x, op0_mode, in_dest);
4105
4106       if (GET_CODE (x) == code)
4107         break;
4108
4109       code = GET_CODE (x);
4110
4111       /* We no longer know the original mode of operand 0 since we
4112          have changed the form of X)  */
4113       op0_mode = VOIDmode;
4114     }
4115
4116   return x;
4117 }
4118 \f
4119 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4120    outer level; call `subst' to simplify recursively.  Return the new
4121    expression.
4122
4123    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4124    if we are inside a SET_DEST.  */
4125
4126 static rtx
4127 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4128 {
4129   enum rtx_code code = GET_CODE (x);
4130   enum machine_mode mode = GET_MODE (x);
4131   rtx temp;
4132   int i;
4133
4134   /* If this is a commutative operation, put a constant last and a complex
4135      expression first.  We don't need to do this for comparisons here.  */
4136   if (COMMUTATIVE_ARITH_P (x)
4137       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4138     {
4139       temp = XEXP (x, 0);
4140       SUBST (XEXP (x, 0), XEXP (x, 1));
4141       SUBST (XEXP (x, 1), temp);
4142     }
4143
4144   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4145      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4146      things.  Check for cases where both arms are testing the same
4147      condition.
4148
4149      Don't do anything if all operands are very simple.  */
4150
4151   if ((BINARY_P (x)
4152        && ((!OBJECT_P (XEXP (x, 0))
4153             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4154                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4155            || (!OBJECT_P (XEXP (x, 1))
4156                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4157                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4158       || (UNARY_P (x)
4159           && (!OBJECT_P (XEXP (x, 0))
4160                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4161                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4162     {
4163       rtx cond, true_rtx, false_rtx;
4164
4165       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4166       if (cond != 0
4167           /* If everything is a comparison, what we have is highly unlikely
4168              to be simpler, so don't use it.  */
4169           && ! (COMPARISON_P (x)
4170                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4171         {
4172           rtx cop1 = const0_rtx;
4173           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4174
4175           if (cond_code == NE && COMPARISON_P (cond))
4176             return x;
4177
4178           /* Simplify the alternative arms; this may collapse the true and
4179              false arms to store-flag values.  Be careful to use copy_rtx
4180              here since true_rtx or false_rtx might share RTL with x as a
4181              result of the if_then_else_cond call above.  */
4182           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4183           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4184
4185           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4186              is unlikely to be simpler.  */
4187           if (general_operand (true_rtx, VOIDmode)
4188               && general_operand (false_rtx, VOIDmode))
4189             {
4190               enum rtx_code reversed;
4191
4192               /* Restarting if we generate a store-flag expression will cause
4193                  us to loop.  Just drop through in this case.  */
4194
4195               /* If the result values are STORE_FLAG_VALUE and zero, we can
4196                  just make the comparison operation.  */
4197               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4198                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4199                                              cond, cop1);
4200               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4201                        && ((reversed = reversed_comparison_code_parts
4202                                         (cond_code, cond, cop1, NULL))
4203                            != UNKNOWN))
4204                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4205                                              cond, cop1);
4206
4207               /* Likewise, we can make the negate of a comparison operation
4208                  if the result values are - STORE_FLAG_VALUE and zero.  */
4209               else if (GET_CODE (true_rtx) == CONST_INT
4210                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4211                        && false_rtx == const0_rtx)
4212                 x = simplify_gen_unary (NEG, mode,
4213                                         simplify_gen_relational (cond_code,
4214                                                                  mode, VOIDmode,
4215                                                                  cond, cop1),
4216                                         mode);
4217               else if (GET_CODE (false_rtx) == CONST_INT
4218                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4219                        && true_rtx == const0_rtx
4220                        && ((reversed = reversed_comparison_code_parts
4221                                         (cond_code, cond, cop1, NULL))
4222                            != UNKNOWN))
4223                 x = simplify_gen_unary (NEG, mode,
4224                                         simplify_gen_relational (reversed,
4225                                                                  mode, VOIDmode,
4226                                                                  cond, cop1),
4227                                         mode);
4228               else
4229                 return gen_rtx_IF_THEN_ELSE (mode,
4230                                              simplify_gen_relational (cond_code,
4231                                                                       mode,
4232                                                                       VOIDmode,
4233                                                                       cond,
4234                                                                       cop1),
4235                                              true_rtx, false_rtx);
4236
4237               code = GET_CODE (x);
4238               op0_mode = VOIDmode;
4239             }
4240         }
4241     }
4242
4243   /* Try to fold this expression in case we have constants that weren't
4244      present before.  */
4245   temp = 0;
4246   switch (GET_RTX_CLASS (code))
4247     {
4248     case RTX_UNARY:
4249       if (op0_mode == VOIDmode)
4250         op0_mode = GET_MODE (XEXP (x, 0));
4251       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4252       break;
4253     case RTX_COMPARE:
4254     case RTX_COMM_COMPARE:
4255       {
4256         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4257         if (cmp_mode == VOIDmode)
4258           {
4259             cmp_mode = GET_MODE (XEXP (x, 1));
4260             if (cmp_mode == VOIDmode)
4261               cmp_mode = op0_mode;
4262           }
4263         temp = simplify_relational_operation (code, mode, cmp_mode,
4264                                               XEXP (x, 0), XEXP (x, 1));
4265       }
4266       break;
4267     case RTX_COMM_ARITH:
4268     case RTX_BIN_ARITH:
4269       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4270       break;
4271     case RTX_BITFIELD_OPS:
4272     case RTX_TERNARY:
4273       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4274                                          XEXP (x, 1), XEXP (x, 2));
4275       break;
4276     default:
4277       break;
4278     }
4279
4280   if (temp)
4281     {
4282       x = temp;
4283       code = GET_CODE (temp);
4284       op0_mode = VOIDmode;
4285       mode = GET_MODE (temp);
4286     }
4287
4288   /* First see if we can apply the inverse distributive law.  */
4289   if (code == PLUS || code == MINUS
4290       || code == AND || code == IOR || code == XOR)
4291     {
4292       x = apply_distributive_law (x);
4293       code = GET_CODE (x);
4294       op0_mode = VOIDmode;
4295     }
4296
4297   /* If CODE is an associative operation not otherwise handled, see if we
4298      can associate some operands.  This can win if they are constants or
4299      if they are logically related (i.e. (a & b) & a).  */
4300   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4301        || code == AND || code == IOR || code == XOR
4302        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4303       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4304           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4305     {
4306       if (GET_CODE (XEXP (x, 0)) == code)
4307         {
4308           rtx other = XEXP (XEXP (x, 0), 0);
4309           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4310           rtx inner_op1 = XEXP (x, 1);
4311           rtx inner;
4312
4313           /* Make sure we pass the constant operand if any as the second
4314              one if this is a commutative operation.  */
4315           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4316             {
4317               rtx tem = inner_op0;
4318               inner_op0 = inner_op1;
4319               inner_op1 = tem;
4320             }
4321           inner = simplify_binary_operation (code == MINUS ? PLUS
4322                                              : code == DIV ? MULT
4323                                              : code,
4324                                              mode, inner_op0, inner_op1);
4325
4326           /* For commutative operations, try the other pair if that one
4327              didn't simplify.  */
4328           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4329             {
4330               other = XEXP (XEXP (x, 0), 1);
4331               inner = simplify_binary_operation (code, mode,
4332                                                  XEXP (XEXP (x, 0), 0),
4333                                                  XEXP (x, 1));
4334             }
4335
4336           if (inner)
4337             return simplify_gen_binary (code, mode, other, inner);
4338         }
4339     }
4340
4341   /* A little bit of algebraic simplification here.  */
4342   switch (code)
4343     {
4344     case MEM:
4345       /* Ensure that our address has any ASHIFTs converted to MULT in case
4346          address-recognizing predicates are called later.  */
4347       temp = make_compound_operation (XEXP (x, 0), MEM);
4348       SUBST (XEXP (x, 0), temp);
4349       break;
4350
4351     case SUBREG:
4352       if (op0_mode == VOIDmode)
4353         op0_mode = GET_MODE (SUBREG_REG (x));
4354
4355       /* See if this can be moved to simplify_subreg.  */
4356       if (CONSTANT_P (SUBREG_REG (x))
4357           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4358              /* Don't call gen_lowpart if the inner mode
4359                 is VOIDmode and we cannot simplify it, as SUBREG without
4360                 inner mode is invalid.  */
4361           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4362               || gen_lowpart_common (mode, SUBREG_REG (x))))
4363         return gen_lowpart (mode, SUBREG_REG (x));
4364
4365       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4366         break;
4367       {
4368         rtx temp;
4369         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4370                                 SUBREG_BYTE (x));
4371         if (temp)
4372           return temp;
4373       }
4374
4375       /* Don't change the mode of the MEM if that would change the meaning
4376          of the address.  */
4377       if (MEM_P (SUBREG_REG (x))
4378           && (MEM_VOLATILE_P (SUBREG_REG (x))
4379               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4380         return gen_rtx_CLOBBER (mode, const0_rtx);
4381
4382       /* Note that we cannot do any narrowing for non-constants since
4383          we might have been counting on using the fact that some bits were
4384          zero.  We now do this in the SET.  */
4385
4386       break;
4387
4388     case NEG:
4389       temp = expand_compound_operation (XEXP (x, 0));
4390
4391       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4392          replaced by (lshiftrt X C).  This will convert
4393          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4394
4395       if (GET_CODE (temp) == ASHIFTRT
4396           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4397           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4398         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4399                                      INTVAL (XEXP (temp, 1)));
4400
4401       /* If X has only a single bit that might be nonzero, say, bit I, convert
4402          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4403          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4404          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4405          or a SUBREG of one since we'd be making the expression more
4406          complex if it was just a register.  */
4407
4408       if (!REG_P (temp)
4409           && ! (GET_CODE (temp) == SUBREG
4410                 && REG_P (SUBREG_REG (temp)))
4411           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4412         {
4413           rtx temp1 = simplify_shift_const
4414             (NULL_RTX, ASHIFTRT, mode,
4415              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4416                                    GET_MODE_BITSIZE (mode) - 1 - i),
4417              GET_MODE_BITSIZE (mode) - 1 - i);
4418
4419           /* If all we did was surround TEMP with the two shifts, we
4420              haven't improved anything, so don't use it.  Otherwise,
4421              we are better off with TEMP1.  */
4422           if (GET_CODE (temp1) != ASHIFTRT
4423               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4424               || XEXP (XEXP (temp1, 0), 0) != temp)
4425             return temp1;
4426         }
4427       break;
4428
4429     case TRUNCATE:
4430       /* We can't handle truncation to a partial integer mode here
4431          because we don't know the real bitsize of the partial
4432          integer mode.  */
4433       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4434         break;
4435
4436       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4437           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4438                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4439         SUBST (XEXP (x, 0),
4440                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4441                               GET_MODE_MASK (mode), 0));
4442
4443       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4444          whose value is a comparison can be replaced with a subreg if
4445          STORE_FLAG_VALUE permits.  */
4446       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4447           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4448           && (temp = get_last_value (XEXP (x, 0)))
4449           && COMPARISON_P (temp))
4450         return gen_lowpart (mode, XEXP (x, 0));
4451       break;
4452
4453 #ifdef HAVE_cc0
4454     case COMPARE:
4455       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4456          using cc0, in which case we want to leave it as a COMPARE
4457          so we can distinguish it from a register-register-copy.  */
4458       if (XEXP (x, 1) == const0_rtx)
4459         return XEXP (x, 0);
4460
4461       /* x - 0 is the same as x unless x's mode has signed zeros and
4462          allows rounding towards -infinity.  Under those conditions,
4463          0 - 0 is -0.  */
4464       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4465             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4466           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4467         return XEXP (x, 0);
4468       break;
4469 #endif
4470
4471     case CONST:
4472       /* (const (const X)) can become (const X).  Do it this way rather than
4473          returning the inner CONST since CONST can be shared with a
4474          REG_EQUAL note.  */
4475       if (GET_CODE (XEXP (x, 0)) == CONST)
4476         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4477       break;
4478
4479 #ifdef HAVE_lo_sum
4480     case LO_SUM:
4481       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4482          can add in an offset.  find_split_point will split this address up
4483          again if it doesn't match.  */
4484       if (GET_CODE (XEXP (x, 0)) == HIGH
4485           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4486         return XEXP (x, 1);
4487       break;
4488 #endif
4489
4490     case PLUS:
4491       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4492          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4493          bit-field and can be replaced by either a sign_extend or a
4494          sign_extract.  The `and' may be a zero_extend and the two
4495          <c>, -<c> constants may be reversed.  */
4496       if (GET_CODE (XEXP (x, 0)) == XOR
4497           && GET_CODE (XEXP (x, 1)) == CONST_INT
4498           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4499           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4500           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4501               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4502           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4503           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4504                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4505                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4506                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4507               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4508                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4509                       == (unsigned int) i + 1))))
4510         return simplify_shift_const
4511           (NULL_RTX, ASHIFTRT, mode,
4512            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4513                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4514                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4515            GET_MODE_BITSIZE (mode) - (i + 1));
4516
4517       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4518          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4519          the bitsize of the mode - 1.  This allows simplification of
4520          "a = (b & 8) == 0;"  */
4521       if (XEXP (x, 1) == constm1_rtx
4522           && !REG_P (XEXP (x, 0))
4523           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4524                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4525           && nonzero_bits (XEXP (x, 0), mode) == 1)
4526         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4527            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4528                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4529                                  GET_MODE_BITSIZE (mode) - 1),
4530            GET_MODE_BITSIZE (mode) - 1);
4531
4532       /* If we are adding two things that have no bits in common, convert
4533          the addition into an IOR.  This will often be further simplified,
4534          for example in cases like ((a & 1) + (a & 2)), which can
4535          become a & 3.  */
4536
4537       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4538           && (nonzero_bits (XEXP (x, 0), mode)
4539               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4540         {
4541           /* Try to simplify the expression further.  */
4542           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4543           temp = combine_simplify_rtx (tor, mode, in_dest);
4544
4545           /* If we could, great.  If not, do not go ahead with the IOR
4546              replacement, since PLUS appears in many special purpose
4547              address arithmetic instructions.  */
4548           if (GET_CODE (temp) != CLOBBER && temp != tor)
4549             return temp;
4550         }
4551       break;
4552
4553     case MINUS:
4554       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4555          (and <foo> (const_int pow2-1))  */
4556       if (GET_CODE (XEXP (x, 1)) == AND
4557           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4558           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4559           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4560         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4561                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4562       break;
4563
4564     case MULT:
4565       /* If we have (mult (plus A B) C), apply the distributive law and then
4566          the inverse distributive law to see if things simplify.  This
4567          occurs mostly in addresses, often when unrolling loops.  */
4568
4569       if (GET_CODE (XEXP (x, 0)) == PLUS)
4570         {
4571           rtx result = distribute_and_simplify_rtx (x, 0);
4572           if (result)
4573             return result;
4574         }
4575
4576       /* Try simplify a*(b/c) as (a*b)/c.  */
4577       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4578           && GET_CODE (XEXP (x, 0)) == DIV)
4579         {
4580           rtx tem = simplify_binary_operation (MULT, mode,
4581                                                XEXP (XEXP (x, 0), 0),
4582                                                XEXP (x, 1));
4583           if (tem)
4584             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4585         }
4586       break;
4587
4588     case UDIV:
4589       /* If this is a divide by a power of two, treat it as a shift if
4590          its first operand is a shift.  */
4591       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4592           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4593           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4594               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4595               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4596               || GET_CODE (XEXP (x, 0)) == ROTATE
4597               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4598         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4599       break;
4600
4601     case EQ:  case NE:
4602     case GT:  case GTU:  case GE:  case GEU:
4603     case LT:  case LTU:  case LE:  case LEU:
4604     case UNEQ:  case LTGT:
4605     case UNGT:  case UNGE:
4606     case UNLT:  case UNLE:
4607     case UNORDERED: case ORDERED:
4608       /* If the first operand is a condition code, we can't do anything
4609          with it.  */
4610       if (GET_CODE (XEXP (x, 0)) == COMPARE
4611           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4612               && ! CC0_P (XEXP (x, 0))))
4613         {
4614           rtx op0 = XEXP (x, 0);
4615           rtx op1 = XEXP (x, 1);
4616           enum rtx_code new_code;
4617
4618           if (GET_CODE (op0) == COMPARE)
4619             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4620
4621           /* Simplify our comparison, if possible.  */
4622           new_code = simplify_comparison (code, &op0, &op1);
4623
4624           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4625              if only the low-order bit is possibly nonzero in X (such as when
4626              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4627              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4628              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4629              (plus X 1).
4630
4631              Remove any ZERO_EXTRACT we made when thinking this was a
4632              comparison.  It may now be simpler to use, e.g., an AND.  If a
4633              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4634              the call to make_compound_operation in the SET case.  */
4635
4636           if (STORE_FLAG_VALUE == 1
4637               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4638               && op1 == const0_rtx
4639               && mode == GET_MODE (op0)
4640               && nonzero_bits (op0, mode) == 1)
4641             return gen_lowpart (mode,
4642                                 expand_compound_operation (op0));
4643
4644           else if (STORE_FLAG_VALUE == 1
4645                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4646                    && op1 == const0_rtx
4647                    && mode == GET_MODE (op0)
4648                    && (num_sign_bit_copies (op0, mode)
4649                        == GET_MODE_BITSIZE (mode)))
4650             {
4651               op0 = expand_compound_operation (op0);
4652               return simplify_gen_unary (NEG, mode,
4653                                          gen_lowpart (mode, op0),
4654                                          mode);
4655             }
4656
4657           else if (STORE_FLAG_VALUE == 1
4658                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4659                    && op1 == const0_rtx
4660                    && mode == GET_MODE (op0)
4661                    && nonzero_bits (op0, mode) == 1)
4662             {
4663               op0 = expand_compound_operation (op0);
4664               return simplify_gen_binary (XOR, mode,
4665                                           gen_lowpart (mode, op0),
4666                                           const1_rtx);
4667             }
4668
4669           else if (STORE_FLAG_VALUE == 1
4670                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4671                    && op1 == const0_rtx
4672                    && mode == GET_MODE (op0)
4673                    && (num_sign_bit_copies (op0, mode)
4674                        == GET_MODE_BITSIZE (mode)))
4675             {
4676               op0 = expand_compound_operation (op0);
4677               return plus_constant (gen_lowpart (mode, op0), 1);
4678             }
4679
4680           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4681              those above.  */
4682           if (STORE_FLAG_VALUE == -1
4683               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4684               && op1 == const0_rtx
4685               && (num_sign_bit_copies (op0, mode)
4686                   == GET_MODE_BITSIZE (mode)))
4687             return gen_lowpart (mode,
4688                                 expand_compound_operation (op0));
4689
4690           else if (STORE_FLAG_VALUE == -1
4691                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4692                    && op1 == const0_rtx
4693                    && mode == GET_MODE (op0)
4694                    && nonzero_bits (op0, mode) == 1)
4695             {
4696               op0 = expand_compound_operation (op0);
4697               return simplify_gen_unary (NEG, mode,
4698                                          gen_lowpart (mode, op0),
4699                                          mode);
4700             }
4701
4702           else if (STORE_FLAG_VALUE == -1
4703                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4704                    && op1 == const0_rtx
4705                    && mode == GET_MODE (op0)
4706                    && (num_sign_bit_copies (op0, mode)
4707                        == GET_MODE_BITSIZE (mode)))
4708             {
4709               op0 = expand_compound_operation (op0);
4710               return simplify_gen_unary (NOT, mode,
4711                                          gen_lowpart (mode, op0),
4712                                          mode);
4713             }
4714
4715           /* If X is 0/1, (eq X 0) is X-1.  */
4716           else if (STORE_FLAG_VALUE == -1
4717                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4718                    && op1 == const0_rtx
4719                    && mode == GET_MODE (op0)
4720                    && nonzero_bits (op0, mode) == 1)
4721             {
4722               op0 = expand_compound_operation (op0);
4723               return plus_constant (gen_lowpart (mode, op0), -1);
4724             }
4725
4726           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4727              one bit that might be nonzero, we can convert (ne x 0) to
4728              (ashift x c) where C puts the bit in the sign bit.  Remove any
4729              AND with STORE_FLAG_VALUE when we are done, since we are only
4730              going to test the sign bit.  */
4731           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4732               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4733               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4734                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4735               && op1 == const0_rtx
4736               && mode == GET_MODE (op0)
4737               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4738             {
4739               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4740                                         expand_compound_operation (op0),
4741                                         GET_MODE_BITSIZE (mode) - 1 - i);
4742               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4743                 return XEXP (x, 0);
4744               else
4745                 return x;
4746             }
4747
4748           /* If the code changed, return a whole new comparison.  */
4749           if (new_code != code)
4750             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4751
4752           /* Otherwise, keep this operation, but maybe change its operands.
4753              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4754           SUBST (XEXP (x, 0), op0);
4755           SUBST (XEXP (x, 1), op1);
4756         }
4757       break;
4758
4759     case IF_THEN_ELSE:
4760       return simplify_if_then_else (x);
4761
4762     case ZERO_EXTRACT:
4763     case SIGN_EXTRACT:
4764     case ZERO_EXTEND:
4765     case SIGN_EXTEND:
4766       /* If we are processing SET_DEST, we are done.  */
4767       if (in_dest)
4768         return x;
4769
4770       return expand_compound_operation (x);
4771
4772     case SET:
4773       return simplify_set (x);
4774
4775     case AND:
4776     case IOR:
4777       return simplify_logical (x);
4778
4779     case ASHIFT:
4780     case LSHIFTRT:
4781     case ASHIFTRT:
4782     case ROTATE:
4783     case ROTATERT:
4784       /* If this is a shift by a constant amount, simplify it.  */
4785       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4786         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4787                                      INTVAL (XEXP (x, 1)));
4788
4789       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4790         SUBST (XEXP (x, 1),
4791                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4792                               ((HOST_WIDE_INT) 1
4793                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4794                               - 1,
4795                               0));
4796       break;
4797
4798     default:
4799       break;
4800     }
4801
4802   return x;
4803 }
4804 \f
4805 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4806
4807 static rtx
4808 simplify_if_then_else (rtx x)
4809 {
4810   enum machine_mode mode = GET_MODE (x);
4811   rtx cond = XEXP (x, 0);
4812   rtx true_rtx = XEXP (x, 1);
4813   rtx false_rtx = XEXP (x, 2);
4814   enum rtx_code true_code = GET_CODE (cond);
4815   int comparison_p = COMPARISON_P (cond);
4816   rtx temp;
4817   int i;
4818   enum rtx_code false_code;
4819   rtx reversed;
4820
4821   /* Simplify storing of the truth value.  */
4822   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4823     return simplify_gen_relational (true_code, mode, VOIDmode,
4824                                     XEXP (cond, 0), XEXP (cond, 1));
4825
4826   /* Also when the truth value has to be reversed.  */
4827   if (comparison_p
4828       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4829       && (reversed = reversed_comparison (cond, mode)))
4830     return reversed;
4831
4832   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4833      in it is being compared against certain values.  Get the true and false
4834      comparisons and see if that says anything about the value of each arm.  */
4835
4836   if (comparison_p
4837       && ((false_code = reversed_comparison_code (cond, NULL))
4838           != UNKNOWN)
4839       && REG_P (XEXP (cond, 0)))
4840     {
4841       HOST_WIDE_INT nzb;
4842       rtx from = XEXP (cond, 0);
4843       rtx true_val = XEXP (cond, 1);
4844       rtx false_val = true_val;
4845       int swapped = 0;
4846
4847       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4848
4849       if (false_code == EQ)
4850         {
4851           swapped = 1, true_code = EQ, false_code = NE;
4852           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4853         }
4854
4855       /* If we are comparing against zero and the expression being tested has
4856          only a single bit that might be nonzero, that is its value when it is
4857          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4858
4859       if (true_code == EQ && true_val == const0_rtx
4860           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4861         false_code = EQ, false_val = GEN_INT (nzb);
4862       else if (true_code == EQ && true_val == const0_rtx
4863                && (num_sign_bit_copies (from, GET_MODE (from))
4864                    == GET_MODE_BITSIZE (GET_MODE (from))))
4865         false_code = EQ, false_val = constm1_rtx;
4866
4867       /* Now simplify an arm if we know the value of the register in the
4868          branch and it is used in the arm.  Be careful due to the potential
4869          of locally-shared RTL.  */
4870
4871       if (reg_mentioned_p (from, true_rtx))
4872         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4873                                       from, true_val),
4874                       pc_rtx, pc_rtx, 0, 0);
4875       if (reg_mentioned_p (from, false_rtx))
4876         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4877                                    from, false_val),
4878                        pc_rtx, pc_rtx, 0, 0);
4879
4880       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4881       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4882
4883       true_rtx = XEXP (x, 1);
4884       false_rtx = XEXP (x, 2);
4885       true_code = GET_CODE (cond);
4886     }
4887
4888   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4889      reversed, do so to avoid needing two sets of patterns for
4890      subtract-and-branch insns.  Similarly if we have a constant in the true
4891      arm, the false arm is the same as the first operand of the comparison, or
4892      the false arm is more complicated than the true arm.  */
4893
4894   if (comparison_p
4895       && reversed_comparison_code (cond, NULL) != UNKNOWN
4896       && (true_rtx == pc_rtx
4897           || (CONSTANT_P (true_rtx)
4898               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4899           || true_rtx == const0_rtx
4900           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4901           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4902               && !OBJECT_P (false_rtx))
4903           || reg_mentioned_p (true_rtx, false_rtx)
4904           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4905     {
4906       true_code = reversed_comparison_code (cond, NULL);
4907       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4908       SUBST (XEXP (x, 1), false_rtx);
4909       SUBST (XEXP (x, 2), true_rtx);
4910
4911       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4912       cond = XEXP (x, 0);
4913
4914       /* It is possible that the conditional has been simplified out.  */
4915       true_code = GET_CODE (cond);
4916       comparison_p = COMPARISON_P (cond);
4917     }
4918
4919   /* If the two arms are identical, we don't need the comparison.  */
4920
4921   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4922     return true_rtx;
4923
4924   /* Convert a == b ? b : a to "a".  */
4925   if (true_code == EQ && ! side_effects_p (cond)
4926       && !HONOR_NANS (mode)
4927       && rtx_equal_p (XEXP (cond, 0), false_rtx)
4928       && rtx_equal_p (XEXP (cond, 1), true_rtx))
4929     return false_rtx;
4930   else if (true_code == NE && ! side_effects_p (cond)
4931            && !HONOR_NANS (mode)
4932            && rtx_equal_p (XEXP (cond, 0), true_rtx)
4933            && rtx_equal_p (XEXP (cond, 1), false_rtx))
4934     return true_rtx;
4935
4936   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4937
4938   if (GET_MODE_CLASS (mode) == MODE_INT
4939       && GET_CODE (false_rtx) == NEG
4940       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4941       && comparison_p
4942       && rtx_equal_p (true_rtx, XEXP (cond, 0))
4943       && ! side_effects_p (true_rtx))
4944     switch (true_code)
4945       {
4946       case GT:
4947       case GE:
4948         return simplify_gen_unary (ABS, mode, true_rtx, mode);
4949       case LT:
4950       case LE:
4951         return
4952           simplify_gen_unary (NEG, mode,
4953                               simplify_gen_unary (ABS, mode, true_rtx, mode),
4954                               mode);
4955       default:
4956         break;
4957       }
4958
4959   /* Look for MIN or MAX.  */
4960
4961   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4962       && comparison_p
4963       && rtx_equal_p (XEXP (cond, 0), true_rtx)
4964       && rtx_equal_p (XEXP (cond, 1), false_rtx)
4965       && ! side_effects_p (cond))
4966     switch (true_code)
4967       {
4968       case GE:
4969       case GT:
4970         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4971       case LE:
4972       case LT:
4973         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4974       case GEU:
4975       case GTU:
4976         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4977       case LEU:
4978       case LTU:
4979         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4980       default:
4981         break;
4982       }
4983
4984   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4985      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4986      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4987      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4988      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4989      neither 1 or -1, but it isn't worth checking for.  */
4990
4991   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4992       && comparison_p
4993       && GET_MODE_CLASS (mode) == MODE_INT
4994       && ! side_effects_p (x))
4995     {
4996       rtx t = make_compound_operation (true_rtx, SET);
4997       rtx f = make_compound_operation (false_rtx, SET);
4998       rtx cond_op0 = XEXP (cond, 0);
4999       rtx cond_op1 = XEXP (cond, 1);
5000       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5001       enum machine_mode m = mode;
5002       rtx z = 0, c1 = NULL_RTX;
5003
5004       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5005            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5006            || GET_CODE (t) == ASHIFT
5007            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5008           && rtx_equal_p (XEXP (t, 0), f))
5009         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5010
5011       /* If an identity-zero op is commutative, check whether there
5012          would be a match if we swapped the operands.  */
5013       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5014                 || GET_CODE (t) == XOR)
5015                && rtx_equal_p (XEXP (t, 1), f))
5016         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5017       else if (GET_CODE (t) == SIGN_EXTEND
5018                && (GET_CODE (XEXP (t, 0)) == PLUS
5019                    || GET_CODE (XEXP (t, 0)) == MINUS
5020                    || GET_CODE (XEXP (t, 0)) == IOR
5021                    || GET_CODE (XEXP (t, 0)) == XOR
5022                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5023                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5024                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5025                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5026                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5027                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5028                && (num_sign_bit_copies (f, GET_MODE (f))
5029                    > (unsigned int)
5030                      (GET_MODE_BITSIZE (mode)
5031                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5032         {
5033           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5034           extend_op = SIGN_EXTEND;
5035           m = GET_MODE (XEXP (t, 0));
5036         }
5037       else if (GET_CODE (t) == SIGN_EXTEND
5038                && (GET_CODE (XEXP (t, 0)) == PLUS
5039                    || GET_CODE (XEXP (t, 0)) == IOR
5040                    || GET_CODE (XEXP (t, 0)) == XOR)
5041                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5042                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5043                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5044                && (num_sign_bit_copies (f, GET_MODE (f))
5045                    > (unsigned int)
5046                      (GET_MODE_BITSIZE (mode)
5047                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5048         {
5049           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5050           extend_op = SIGN_EXTEND;
5051           m = GET_MODE (XEXP (t, 0));
5052         }
5053       else if (GET_CODE (t) == ZERO_EXTEND
5054                && (GET_CODE (XEXP (t, 0)) == PLUS
5055                    || GET_CODE (XEXP (t, 0)) == MINUS
5056                    || GET_CODE (XEXP (t, 0)) == IOR
5057                    || GET_CODE (XEXP (t, 0)) == XOR
5058                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5059                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5060                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5061                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5062                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5063                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5064                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5065                && ((nonzero_bits (f, GET_MODE (f))
5066                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5067                    == 0))
5068         {
5069           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5070           extend_op = ZERO_EXTEND;
5071           m = GET_MODE (XEXP (t, 0));
5072         }
5073       else if (GET_CODE (t) == ZERO_EXTEND
5074                && (GET_CODE (XEXP (t, 0)) == PLUS
5075                    || GET_CODE (XEXP (t, 0)) == IOR
5076                    || GET_CODE (XEXP (t, 0)) == XOR)
5077                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5078                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5079                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5080                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5081                && ((nonzero_bits (f, GET_MODE (f))
5082                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5083                    == 0))
5084         {
5085           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5086           extend_op = ZERO_EXTEND;
5087           m = GET_MODE (XEXP (t, 0));
5088         }
5089
5090       if (z)
5091         {
5092           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5093                                                  cond_op0, cond_op1),
5094                         pc_rtx, pc_rtx, 0, 0);
5095           temp = simplify_gen_binary (MULT, m, temp,
5096                                       simplify_gen_binary (MULT, m, c1,
5097                                                            const_true_rtx));
5098           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5099           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5100
5101           if (extend_op != UNKNOWN)
5102             temp = simplify_gen_unary (extend_op, mode, temp, m);
5103
5104           return temp;
5105         }
5106     }
5107
5108   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5109      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5110      negation of a single bit, we can convert this operation to a shift.  We
5111      can actually do this more generally, but it doesn't seem worth it.  */
5112
5113   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5114       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5115       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5116            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5117           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5118                == GET_MODE_BITSIZE (mode))
5119               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5120     return
5121       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5122                             gen_lowpart (mode, XEXP (cond, 0)), i);
5123
5124   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5125   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5126       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5127       && GET_MODE (XEXP (cond, 0)) == mode
5128       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5129           == nonzero_bits (XEXP (cond, 0), mode)
5130       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5131     return XEXP (cond, 0);
5132
5133   return x;
5134 }
5135 \f
5136 /* Simplify X, a SET expression.  Return the new expression.  */
5137
5138 static rtx
5139 simplify_set (rtx x)
5140 {
5141   rtx src = SET_SRC (x);
5142   rtx dest = SET_DEST (x);
5143   enum machine_mode mode
5144     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5145   rtx other_insn;
5146   rtx *cc_use;
5147
5148   /* (set (pc) (return)) gets written as (return).  */
5149   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5150     return src;
5151
5152   /* Now that we know for sure which bits of SRC we are using, see if we can
5153      simplify the expression for the object knowing that we only need the
5154      low-order bits.  */
5155
5156   if (GET_MODE_CLASS (mode) == MODE_INT
5157       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5158     {
5159       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5160       SUBST (SET_SRC (x), src);
5161     }
5162
5163   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5164      the comparison result and try to simplify it unless we already have used
5165      undobuf.other_insn.  */
5166   if ((GET_MODE_CLASS (mode) == MODE_CC
5167        || GET_CODE (src) == COMPARE
5168        || CC0_P (dest))
5169       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5170       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5171       && COMPARISON_P (*cc_use)
5172       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5173     {
5174       enum rtx_code old_code = GET_CODE (*cc_use);
5175       enum rtx_code new_code;
5176       rtx op0, op1, tmp;
5177       int other_changed = 0;
5178       enum machine_mode compare_mode = GET_MODE (dest);
5179
5180       if (GET_CODE (src) == COMPARE)
5181         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5182       else
5183         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5184
5185       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5186                                            op0, op1);
5187       if (!tmp)
5188         new_code = old_code;
5189       else if (!CONSTANT_P (tmp))
5190         {
5191           new_code = GET_CODE (tmp);
5192           op0 = XEXP (tmp, 0);
5193           op1 = XEXP (tmp, 1);
5194         }
5195       else
5196         {
5197           rtx pat = PATTERN (other_insn);
5198           undobuf.other_insn = other_insn;
5199           SUBST (*cc_use, tmp);
5200
5201           /* Attempt to simplify CC user.  */
5202           if (GET_CODE (pat) == SET)
5203             {
5204               rtx new = simplify_rtx (SET_SRC (pat));
5205               if (new != NULL_RTX)
5206                 SUBST (SET_SRC (pat), new);
5207             }
5208
5209           /* Convert X into a no-op move.  */
5210           SUBST (SET_DEST (x), pc_rtx);
5211           SUBST (SET_SRC (x), pc_rtx);
5212           return x;
5213         }
5214
5215       /* Simplify our comparison, if possible.  */
5216       new_code = simplify_comparison (new_code, &op0, &op1);
5217
5218 #ifdef SELECT_CC_MODE
5219       /* If this machine has CC modes other than CCmode, check to see if we
5220          need to use a different CC mode here.  */
5221       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5222         compare_mode = GET_MODE (op0);
5223       else
5224         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5225
5226 #ifndef HAVE_cc0
5227       /* If the mode changed, we have to change SET_DEST, the mode in the
5228          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5229          a hard register, just build new versions with the proper mode.  If it
5230          is a pseudo, we lose unless it is only time we set the pseudo, in
5231          which case we can safely change its mode.  */
5232       if (compare_mode != GET_MODE (dest))
5233         {
5234           if (can_change_dest_mode (dest, 0, compare_mode))
5235             {
5236               unsigned int regno = REGNO (dest);
5237               rtx new_dest;
5238
5239               if (regno < FIRST_PSEUDO_REGISTER)
5240                 new_dest = gen_rtx_REG (compare_mode, regno);
5241               else
5242                 {
5243                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5244                   new_dest = regno_reg_rtx[regno];
5245                 }
5246
5247               SUBST (SET_DEST (x), new_dest);
5248               SUBST (XEXP (*cc_use, 0), new_dest);
5249               other_changed = 1;
5250
5251               dest = new_dest;
5252             }
5253         }
5254 #endif  /* cc0 */
5255 #endif  /* SELECT_CC_MODE */
5256
5257       /* If the code changed, we have to build a new comparison in
5258          undobuf.other_insn.  */
5259       if (new_code != old_code)
5260         {
5261           int other_changed_previously = other_changed;
5262           unsigned HOST_WIDE_INT mask;
5263
5264           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5265                                           dest, const0_rtx));
5266           other_changed = 1;
5267
5268           /* If the only change we made was to change an EQ into an NE or
5269              vice versa, OP0 has only one bit that might be nonzero, and OP1
5270              is zero, check if changing the user of the condition code will
5271              produce a valid insn.  If it won't, we can keep the original code
5272              in that insn by surrounding our operation with an XOR.  */
5273
5274           if (((old_code == NE && new_code == EQ)
5275                || (old_code == EQ && new_code == NE))
5276               && ! other_changed_previously && op1 == const0_rtx
5277               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5278               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5279             {
5280               rtx pat = PATTERN (other_insn), note = 0;
5281
5282               if ((recog_for_combine (&pat, other_insn, &note) < 0
5283                    && ! check_asm_operands (pat)))
5284                 {
5285                   PUT_CODE (*cc_use, old_code);
5286                   other_changed = 0;
5287
5288                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5289                                              op0, GEN_INT (mask));
5290                 }
5291             }
5292         }
5293
5294       if (other_changed)
5295         undobuf.other_insn = other_insn;
5296
5297 #ifdef HAVE_cc0
5298       /* If we are now comparing against zero, change our source if
5299          needed.  If we do not use cc0, we always have a COMPARE.  */
5300       if (op1 == const0_rtx && dest == cc0_rtx)
5301         {
5302           SUBST (SET_SRC (x), op0);
5303           src = op0;
5304         }
5305       else
5306 #endif
5307
5308       /* Otherwise, if we didn't previously have a COMPARE in the
5309          correct mode, we need one.  */
5310       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5311         {
5312           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5313           src = SET_SRC (x);
5314         }
5315       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5316         {
5317           SUBST(SET_SRC (x), op0);
5318           src = SET_SRC (x);
5319         }
5320       else
5321         {
5322           /* Otherwise, update the COMPARE if needed.  */
5323           SUBST (XEXP (src, 0), op0);
5324           SUBST (XEXP (src, 1), op1);
5325         }
5326     }
5327   else
5328     {
5329       /* Get SET_SRC in a form where we have placed back any
5330          compound expressions.  Then do the checks below.  */
5331       src = make_compound_operation (src, SET);
5332       SUBST (SET_SRC (x), src);
5333     }
5334
5335   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5336      and X being a REG or (subreg (reg)), we may be able to convert this to
5337      (set (subreg:m2 x) (op)).
5338
5339      We can always do this if M1 is narrower than M2 because that means that
5340      we only care about the low bits of the result.
5341
5342      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5343      perform a narrower operation than requested since the high-order bits will
5344      be undefined.  On machine where it is defined, this transformation is safe
5345      as long as M1 and M2 have the same number of words.  */
5346
5347   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5348       && !OBJECT_P (SUBREG_REG (src))
5349       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5350            / UNITS_PER_WORD)
5351           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5352                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5353 #ifndef WORD_REGISTER_OPERATIONS
5354       && (GET_MODE_SIZE (GET_MODE (src))
5355         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5356 #endif
5357 #ifdef CANNOT_CHANGE_MODE_CLASS
5358       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5359             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5360                                          GET_MODE (SUBREG_REG (src)),
5361                                          GET_MODE (src)))
5362 #endif
5363       && (REG_P (dest)
5364           || (GET_CODE (dest) == SUBREG
5365               && REG_P (SUBREG_REG (dest)))))
5366     {
5367       SUBST (SET_DEST (x),
5368              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5369                                       dest));
5370       SUBST (SET_SRC (x), SUBREG_REG (src));
5371
5372       src = SET_SRC (x), dest = SET_DEST (x);
5373     }
5374
5375 #ifdef HAVE_cc0
5376   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5377      in SRC.  */
5378   if (dest == cc0_rtx
5379       && GET_CODE (src) == SUBREG
5380       && subreg_lowpart_p (src)
5381       && (GET_MODE_BITSIZE (GET_MODE (src))
5382           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5383     {
5384       rtx inner = SUBREG_REG (src);
5385       enum machine_mode inner_mode = GET_MODE (inner);
5386
5387       /* Here we make sure that we don't have a sign bit on.  */
5388       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5389           && (nonzero_bits (inner, inner_mode)
5390               < ((unsigned HOST_WIDE_INT) 1
5391                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5392         {
5393           SUBST (SET_SRC (x), inner);
5394           src = SET_SRC (x);
5395         }
5396     }
5397 #endif
5398
5399 #ifdef LOAD_EXTEND_OP
5400   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5401      would require a paradoxical subreg.  Replace the subreg with a
5402      zero_extend to avoid the reload that would otherwise be required.  */
5403
5404   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5405       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5406       && SUBREG_BYTE (src) == 0
5407       && (GET_MODE_SIZE (GET_MODE (src))
5408           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5409       && MEM_P (SUBREG_REG (src)))
5410     {
5411       SUBST (SET_SRC (x),
5412              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5413                             GET_MODE (src), SUBREG_REG (src)));
5414
5415       src = SET_SRC (x);
5416     }
5417 #endif
5418
5419   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5420      are comparing an item known to be 0 or -1 against 0, use a logical
5421      operation instead. Check for one of the arms being an IOR of the other
5422      arm with some value.  We compute three terms to be IOR'ed together.  In
5423      practice, at most two will be nonzero.  Then we do the IOR's.  */
5424
5425   if (GET_CODE (dest) != PC
5426       && GET_CODE (src) == IF_THEN_ELSE
5427       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5428       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5429       && XEXP (XEXP (src, 0), 1) == const0_rtx
5430       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5431 #ifdef HAVE_conditional_move
5432       && ! can_conditionally_move_p (GET_MODE (src))
5433 #endif
5434       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5435                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5436           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5437       && ! side_effects_p (src))
5438     {
5439       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5440                       ? XEXP (src, 1) : XEXP (src, 2));
5441       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5442                    ? XEXP (src, 2) : XEXP (src, 1));
5443       rtx term1 = const0_rtx, term2, term3;
5444
5445       if (GET_CODE (true_rtx) == IOR
5446           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5447         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5448       else if (GET_CODE (true_rtx) == IOR
5449                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5450         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5451       else if (GET_CODE (false_rtx) == IOR
5452                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5453         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5454       else if (GET_CODE (false_rtx) == IOR
5455                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5456         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5457
5458       term2 = simplify_gen_binary (AND, GET_MODE (src),
5459                                    XEXP (XEXP (src, 0), 0), true_rtx);
5460       term3 = simplify_gen_binary (AND, GET_MODE (src),
5461                                    simplify_gen_unary (NOT, GET_MODE (src),
5462                                                        XEXP (XEXP (src, 0), 0),
5463                                                        GET_MODE (src)),
5464                                    false_rtx);
5465
5466       SUBST (SET_SRC (x),
5467              simplify_gen_binary (IOR, GET_MODE (src),
5468                                   simplify_gen_binary (IOR, GET_MODE (src),
5469                                                        term1, term2),
5470                                   term3));
5471
5472       src = SET_SRC (x);
5473     }
5474
5475   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5476      whole thing fail.  */
5477   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5478     return src;
5479   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5480     return dest;
5481   else
5482     /* Convert this into a field assignment operation, if possible.  */
5483     return make_field_assignment (x);
5484 }
5485 \f
5486 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5487    result.  */
5488
5489 static rtx
5490 simplify_logical (rtx x)
5491 {
5492   enum machine_mode mode = GET_MODE (x);
5493   rtx op0 = XEXP (x, 0);
5494   rtx op1 = XEXP (x, 1);
5495
5496   switch (GET_CODE (x))
5497     {
5498     case AND:
5499       /* We can call simplify_and_const_int only if we don't lose
5500          any (sign) bits when converting INTVAL (op1) to
5501          "unsigned HOST_WIDE_INT".  */
5502       if (GET_CODE (op1) == CONST_INT
5503           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5504               || INTVAL (op1) > 0))
5505         {
5506           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5507           if (GET_CODE (x) != AND)
5508             return x;
5509
5510           op0 = XEXP (x, 0);
5511           op1 = XEXP (x, 1);
5512         }
5513
5514       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5515          apply the distributive law and then the inverse distributive
5516          law to see if things simplify.  */
5517       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5518         {
5519           rtx result = distribute_and_simplify_rtx (x, 0);
5520           if (result)
5521             return result;
5522         }
5523       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5524         {
5525           rtx result = distribute_and_simplify_rtx (x, 1);
5526           if (result)
5527             return result;
5528         }
5529       break;
5530
5531     case IOR:
5532       /* If we have (ior (and A B) C), apply the distributive law and then
5533          the inverse distributive law to see if things simplify.  */
5534
5535       if (GET_CODE (op0) == AND)
5536         {
5537           rtx result = distribute_and_simplify_rtx (x, 0);
5538           if (result)
5539             return result;
5540         }
5541
5542       if (GET_CODE (op1) == AND)
5543         {
5544           rtx result = distribute_and_simplify_rtx (x, 1);
5545           if (result)
5546             return result;
5547         }
5548       break;
5549
5550     default:
5551       gcc_unreachable ();
5552     }
5553
5554   return x;
5555 }
5556 \f
5557 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5558    operations" because they can be replaced with two more basic operations.
5559    ZERO_EXTEND is also considered "compound" because it can be replaced with
5560    an AND operation, which is simpler, though only one operation.
5561
5562    The function expand_compound_operation is called with an rtx expression
5563    and will convert it to the appropriate shifts and AND operations,
5564    simplifying at each stage.
5565
5566    The function make_compound_operation is called to convert an expression
5567    consisting of shifts and ANDs into the equivalent compound expression.
5568    It is the inverse of this function, loosely speaking.  */
5569
5570 static rtx
5571 expand_compound_operation (rtx x)
5572 {
5573   unsigned HOST_WIDE_INT pos = 0, len;
5574   int unsignedp = 0;
5575   unsigned int modewidth;
5576   rtx tem;
5577
5578   switch (GET_CODE (x))
5579     {
5580     case ZERO_EXTEND:
5581       unsignedp = 1;
5582     case SIGN_EXTEND:
5583       /* We can't necessarily use a const_int for a multiword mode;
5584          it depends on implicitly extending the value.
5585          Since we don't know the right way to extend it,
5586          we can't tell whether the implicit way is right.
5587
5588          Even for a mode that is no wider than a const_int,
5589          we can't win, because we need to sign extend one of its bits through
5590          the rest of it, and we don't know which bit.  */
5591       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5592         return x;
5593
5594       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5595          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5596          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5597          reloaded. If not for that, MEM's would very rarely be safe.
5598
5599          Reject MODEs bigger than a word, because we might not be able
5600          to reference a two-register group starting with an arbitrary register
5601          (and currently gen_lowpart might crash for a SUBREG).  */
5602
5603       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5604         return x;
5605
5606       /* Reject MODEs that aren't scalar integers because turning vector
5607          or complex modes into shifts causes problems.  */
5608
5609       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5610         return x;
5611
5612       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5613       /* If the inner object has VOIDmode (the only way this can happen
5614          is if it is an ASM_OPERANDS), we can't do anything since we don't
5615          know how much masking to do.  */
5616       if (len == 0)
5617         return x;
5618
5619       break;
5620
5621     case ZERO_EXTRACT:
5622       unsignedp = 1;
5623
5624       /* ... fall through ...  */
5625
5626     case SIGN_EXTRACT:
5627       /* If the operand is a CLOBBER, just return it.  */
5628       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5629         return XEXP (x, 0);
5630
5631       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5632           || GET_CODE (XEXP (x, 2)) != CONST_INT
5633           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5634         return x;
5635
5636       /* Reject MODEs that aren't scalar integers because turning vector
5637          or complex modes into shifts causes problems.  */
5638
5639       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5640         return x;
5641
5642       len = INTVAL (XEXP (x, 1));
5643       pos = INTVAL (XEXP (x, 2));
5644
5645       /* This should stay within the object being extracted, fail otherwise.  */
5646       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5647         return x;
5648
5649       if (BITS_BIG_ENDIAN)
5650         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5651
5652       break;
5653
5654     default:
5655       return x;
5656     }
5657   /* Convert sign extension to zero extension, if we know that the high
5658      bit is not set, as this is easier to optimize.  It will be converted
5659      back to cheaper alternative in make_extraction.  */
5660   if (GET_CODE (x) == SIGN_EXTEND
5661       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5662           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5663                 & ~(((unsigned HOST_WIDE_INT)
5664                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5665                      >> 1))
5666                == 0)))
5667     {
5668       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5669       rtx temp2 = expand_compound_operation (temp);
5670
5671       /* Make sure this is a profitable operation.  */
5672       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5673        return temp2;
5674       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5675        return temp;
5676       else
5677        return x;
5678     }
5679
5680   /* We can optimize some special cases of ZERO_EXTEND.  */
5681   if (GET_CODE (x) == ZERO_EXTEND)
5682     {
5683       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5684          know that the last value didn't have any inappropriate bits
5685          set.  */
5686       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5687           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5688           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5689           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5690               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5691         return XEXP (XEXP (x, 0), 0);
5692
5693       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5694       if (GET_CODE (XEXP (x, 0)) == SUBREG
5695           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5696           && subreg_lowpart_p (XEXP (x, 0))
5697           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5698           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5699               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5700         return SUBREG_REG (XEXP (x, 0));
5701
5702       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5703          is a comparison and STORE_FLAG_VALUE permits.  This is like
5704          the first case, but it works even when GET_MODE (x) is larger
5705          than HOST_WIDE_INT.  */
5706       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5707           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5708           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5709           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5710               <= HOST_BITS_PER_WIDE_INT)
5711           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5712               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5713         return XEXP (XEXP (x, 0), 0);
5714
5715       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5716       if (GET_CODE (XEXP (x, 0)) == SUBREG
5717           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5718           && subreg_lowpart_p (XEXP (x, 0))
5719           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5720           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5721               <= HOST_BITS_PER_WIDE_INT)
5722           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5723               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5724         return SUBREG_REG (XEXP (x, 0));
5725
5726     }
5727
5728   /* If we reach here, we want to return a pair of shifts.  The inner
5729      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5730      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5731      logical depending on the value of UNSIGNEDP.
5732
5733      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5734      converted into an AND of a shift.
5735
5736      We must check for the case where the left shift would have a negative
5737      count.  This can happen in a case like (x >> 31) & 255 on machines
5738      that can't shift by a constant.  On those machines, we would first
5739      combine the shift with the AND to produce a variable-position
5740      extraction.  Then the constant of 31 would be substituted in to produce
5741      a such a position.  */
5742
5743   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5744   if (modewidth + len >= pos)
5745     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5746                                 GET_MODE (x),
5747                                 simplify_shift_const (NULL_RTX, ASHIFT,
5748                                                       GET_MODE (x),
5749                                                       XEXP (x, 0),
5750                                                       modewidth - pos - len),
5751                                 modewidth - len);
5752
5753   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5754     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5755                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5756                                                         GET_MODE (x),
5757                                                         XEXP (x, 0), pos),
5758                                   ((HOST_WIDE_INT) 1 << len) - 1);
5759   else
5760     /* Any other cases we can't handle.  */
5761     return x;
5762
5763   /* If we couldn't do this for some reason, return the original
5764      expression.  */
5765   if (GET_CODE (tem) == CLOBBER)
5766     return x;
5767
5768   return tem;
5769 }
5770 \f
5771 /* X is a SET which contains an assignment of one object into
5772    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5773    or certain SUBREGS). If possible, convert it into a series of
5774    logical operations.
5775
5776    We half-heartedly support variable positions, but do not at all
5777    support variable lengths.  */
5778
5779 static rtx
5780 expand_field_assignment (rtx x)
5781 {
5782   rtx inner;
5783   rtx pos;                      /* Always counts from low bit.  */
5784   int len;
5785   rtx mask, cleared, masked;
5786   enum machine_mode compute_mode;
5787
5788   /* Loop until we find something we can't simplify.  */
5789   while (1)
5790     {
5791       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5792           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5793         {
5794           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5795           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5796           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5797         }
5798       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5799                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5800         {
5801           inner = XEXP (SET_DEST (x), 0);
5802           len = INTVAL (XEXP (SET_DEST (x), 1));
5803           pos = XEXP (SET_DEST (x), 2);
5804
5805           /* A constant position should stay within the width of INNER.  */
5806           if (GET_CODE (pos) == CONST_INT
5807               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5808             break;
5809
5810           if (BITS_BIG_ENDIAN)
5811             {
5812               if (GET_CODE (pos) == CONST_INT)
5813                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5814                                - INTVAL (pos));
5815               else if (GET_CODE (pos) == MINUS
5816                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5817                        && (INTVAL (XEXP (pos, 1))
5818                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5819                 /* If position is ADJUST - X, new position is X.  */
5820                 pos = XEXP (pos, 0);
5821               else
5822                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5823                                            GEN_INT (GET_MODE_BITSIZE (
5824                                                     GET_MODE (inner))
5825                                                     - len),
5826                                            pos);
5827             }
5828         }
5829
5830       /* A SUBREG between two modes that occupy the same numbers of words
5831          can be done by moving the SUBREG to the source.  */
5832       else if (GET_CODE (SET_DEST (x)) == SUBREG
5833                /* We need SUBREGs to compute nonzero_bits properly.  */
5834                && nonzero_sign_valid
5835                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5836                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5837                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5838                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5839         {
5840           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5841                            gen_lowpart
5842                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5843                             SET_SRC (x)));
5844           continue;
5845         }
5846       else
5847         break;
5848
5849       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5850         inner = SUBREG_REG (inner);
5851
5852       compute_mode = GET_MODE (inner);
5853
5854       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
5855       if (! SCALAR_INT_MODE_P (compute_mode))
5856         {
5857           enum machine_mode imode;
5858
5859           /* Don't do anything for vector or complex integral types.  */
5860           if (! FLOAT_MODE_P (compute_mode))
5861             break;
5862
5863           /* Try to find an integral mode to pun with.  */
5864           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5865           if (imode == BLKmode)
5866             break;
5867
5868           compute_mode = imode;
5869           inner = gen_lowpart (imode, inner);
5870         }
5871
5872       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5873       if (len >= HOST_BITS_PER_WIDE_INT)
5874         break;
5875
5876       /* Now compute the equivalent expression.  Make a copy of INNER
5877          for the SET_DEST in case it is a MEM into which we will substitute;
5878          we don't want shared RTL in that case.  */
5879       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5880       cleared = simplify_gen_binary (AND, compute_mode,
5881                                      simplify_gen_unary (NOT, compute_mode,
5882                                        simplify_gen_binary (ASHIFT,
5883                                                             compute_mode,
5884                                                             mask, pos),
5885                                        compute_mode),
5886                                      inner);
5887       masked = simplify_gen_binary (ASHIFT, compute_mode,
5888                                     simplify_gen_binary (
5889                                       AND, compute_mode,
5890                                       gen_lowpart (compute_mode, SET_SRC (x)),
5891                                       mask),
5892                                     pos);
5893
5894       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5895                        simplify_gen_binary (IOR, compute_mode,
5896                                             cleared, masked));
5897     }
5898
5899   return x;
5900 }
5901 \f
5902 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5903    it is an RTX that represents a variable starting position; otherwise,
5904    POS is the (constant) starting bit position (counted from the LSB).
5905
5906    UNSIGNEDP is nonzero for an unsigned reference and zero for a
5907    signed reference.
5908
5909    IN_DEST is nonzero if this is a reference in the destination of a
5910    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
5911    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5912    be used.
5913
5914    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
5915    ZERO_EXTRACT should be built even for bits starting at bit 0.
5916
5917    MODE is the desired mode of the result (if IN_DEST == 0).
5918
5919    The result is an RTX for the extraction or NULL_RTX if the target
5920    can't handle it.  */
5921
5922 static rtx
5923 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5924                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5925                  int in_dest, int in_compare)
5926 {
5927   /* This mode describes the size of the storage area
5928      to fetch the overall value from.  Within that, we
5929      ignore the POS lowest bits, etc.  */
5930   enum machine_mode is_mode = GET_MODE (inner);
5931   enum machine_mode inner_mode;
5932   enum machine_mode wanted_inner_mode;
5933   enum machine_mode wanted_inner_reg_mode = word_mode;
5934   enum machine_mode pos_mode = word_mode;
5935   enum machine_mode extraction_mode = word_mode;
5936   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5937   rtx new = 0;
5938   rtx orig_pos_rtx = pos_rtx;
5939   HOST_WIDE_INT orig_pos;
5940
5941   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5942     {
5943       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5944          consider just the QI as the memory to extract from.
5945          The subreg adds or removes high bits; its mode is
5946          irrelevant to the meaning of this extraction,
5947          since POS and LEN count from the lsb.  */
5948       if (MEM_P (SUBREG_REG (inner)))
5949         is_mode = GET_MODE (SUBREG_REG (inner));
5950       inner = SUBREG_REG (inner);
5951     }
5952   else if (GET_CODE (inner) == ASHIFT
5953            && GET_CODE (XEXP (inner, 1)) == CONST_INT
5954            && pos_rtx == 0 && pos == 0
5955            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5956     {
5957       /* We're extracting the least significant bits of an rtx
5958          (ashift X (const_int C)), where LEN > C.  Extract the
5959          least significant (LEN - C) bits of X, giving an rtx
5960          whose mode is MODE, then shift it left C times.  */
5961       new = make_extraction (mode, XEXP (inner, 0),
5962                              0, 0, len - INTVAL (XEXP (inner, 1)),
5963                              unsignedp, in_dest, in_compare);
5964       if (new != 0)
5965         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5966     }
5967
5968   inner_mode = GET_MODE (inner);
5969
5970   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5971     pos = INTVAL (pos_rtx), pos_rtx = 0;
5972
5973   /* See if this can be done without an extraction.  We never can if the
5974      width of the field is not the same as that of some integer mode. For
5975      registers, we can only avoid the extraction if the position is at the
5976      low-order bit and this is either not in the destination or we have the
5977      appropriate STRICT_LOW_PART operation available.
5978
5979      For MEM, we can avoid an extract if the field starts on an appropriate
5980      boundary and we can change the mode of the memory reference.  */
5981
5982   if (tmode != BLKmode
5983       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5984            && !MEM_P (inner)
5985            && (inner_mode == tmode
5986                || !REG_P (inner)
5987                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
5988                                          GET_MODE_BITSIZE (inner_mode))
5989                || reg_truncated_to_mode (tmode, inner))
5990            && (! in_dest
5991                || (REG_P (inner)
5992                    && have_insn_for (STRICT_LOW_PART, tmode))))
5993           || (MEM_P (inner) && pos_rtx == 0
5994               && (pos
5995                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5996                      : BITS_PER_UNIT)) == 0
5997               /* We can't do this if we are widening INNER_MODE (it
5998                  may not be aligned, for one thing).  */
5999               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6000               && (inner_mode == tmode
6001                   || (! mode_dependent_address_p (XEXP (inner, 0))
6002                       && ! MEM_VOLATILE_P (inner))))))
6003     {
6004       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6005          field.  If the original and current mode are the same, we need not
6006          adjust the offset.  Otherwise, we do if bytes big endian.
6007
6008          If INNER is not a MEM, get a piece consisting of just the field
6009          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6010
6011       if (MEM_P (inner))
6012         {
6013           HOST_WIDE_INT offset;
6014
6015           /* POS counts from lsb, but make OFFSET count in memory order.  */
6016           if (BYTES_BIG_ENDIAN)
6017             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6018           else
6019             offset = pos / BITS_PER_UNIT;
6020
6021           new = adjust_address_nv (inner, tmode, offset);
6022         }
6023       else if (REG_P (inner))
6024         {
6025           if (tmode != inner_mode)
6026             {
6027               /* We can't call gen_lowpart in a DEST since we
6028                  always want a SUBREG (see below) and it would sometimes
6029                  return a new hard register.  */
6030               if (pos || in_dest)
6031                 {
6032                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6033
6034                   if (WORDS_BIG_ENDIAN
6035                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6036                     final_word = ((GET_MODE_SIZE (inner_mode)
6037                                    - GET_MODE_SIZE (tmode))
6038                                   / UNITS_PER_WORD) - final_word;
6039
6040                   final_word *= UNITS_PER_WORD;
6041                   if (BYTES_BIG_ENDIAN &&
6042                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6043                     final_word += (GET_MODE_SIZE (inner_mode)
6044                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6045
6046                   /* Avoid creating invalid subregs, for example when
6047                      simplifying (x>>32)&255.  */
6048                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6049                     return NULL_RTX;
6050
6051                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6052                 }
6053               else
6054                 new = gen_lowpart (tmode, inner);
6055             }
6056           else
6057             new = inner;
6058         }
6059       else
6060         new = force_to_mode (inner, tmode,
6061                              len >= HOST_BITS_PER_WIDE_INT
6062                              ? ~(unsigned HOST_WIDE_INT) 0
6063                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6064                              0);
6065
6066       /* If this extraction is going into the destination of a SET,
6067          make a STRICT_LOW_PART unless we made a MEM.  */
6068
6069       if (in_dest)
6070         return (MEM_P (new) ? new
6071                 : (GET_CODE (new) != SUBREG
6072                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6073                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6074
6075       if (mode == tmode)
6076         return new;
6077
6078       if (GET_CODE (new) == CONST_INT)
6079         return gen_int_mode (INTVAL (new), mode);
6080
6081       /* If we know that no extraneous bits are set, and that the high
6082          bit is not set, convert the extraction to the cheaper of
6083          sign and zero extension, that are equivalent in these cases.  */
6084       if (flag_expensive_optimizations
6085           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6086               && ((nonzero_bits (new, tmode)
6087                    & ~(((unsigned HOST_WIDE_INT)
6088                         GET_MODE_MASK (tmode))
6089                        >> 1))
6090                   == 0)))
6091         {
6092           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6093           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6094
6095           /* Prefer ZERO_EXTENSION, since it gives more information to
6096              backends.  */
6097           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6098             return temp;
6099           return temp1;
6100         }
6101
6102       /* Otherwise, sign- or zero-extend unless we already are in the
6103          proper mode.  */
6104
6105       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6106                              mode, new));
6107     }
6108
6109   /* Unless this is a COMPARE or we have a funny memory reference,
6110      don't do anything with zero-extending field extracts starting at
6111      the low-order bit since they are simple AND operations.  */
6112   if (pos_rtx == 0 && pos == 0 && ! in_dest
6113       && ! in_compare && unsignedp)
6114     return 0;
6115
6116   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6117      if the position is not a constant and the length is not 1.  In all
6118      other cases, we would only be going outside our object in cases when
6119      an original shift would have been undefined.  */
6120   if (MEM_P (inner)
6121       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6122           || (pos_rtx != 0 && len != 1)))
6123     return 0;
6124
6125   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6126      and the mode for the result.  */
6127   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6128     {
6129       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6130       pos_mode = mode_for_extraction (EP_insv, 2);
6131       extraction_mode = mode_for_extraction (EP_insv, 3);
6132     }
6133
6134   if (! in_dest && unsignedp
6135       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6136     {
6137       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6138       pos_mode = mode_for_extraction (EP_extzv, 3);
6139       extraction_mode = mode_for_extraction (EP_extzv, 0);
6140     }
6141
6142   if (! in_dest && ! unsignedp
6143       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6144     {
6145       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6146       pos_mode = mode_for_extraction (EP_extv, 3);
6147       extraction_mode = mode_for_extraction (EP_extv, 0);
6148     }
6149
6150   /* Never narrow an object, since that might not be safe.  */
6151
6152   if (mode != VOIDmode
6153       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6154     extraction_mode = mode;
6155
6156   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6157       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6158     pos_mode = GET_MODE (pos_rtx);
6159
6160   /* If this is not from memory, the desired mode is the preferred mode
6161      for an extraction pattern's first input operand, or word_mode if there
6162      is none.  */
6163   if (!MEM_P (inner))
6164     wanted_inner_mode = wanted_inner_reg_mode;
6165   else
6166     {
6167       /* Be careful not to go beyond the extracted object and maintain the
6168          natural alignment of the memory.  */
6169       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6170       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6171              > GET_MODE_BITSIZE (wanted_inner_mode))
6172         {
6173           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6174           gcc_assert (wanted_inner_mode != VOIDmode);
6175         }
6176
6177       /* If we have to change the mode of memory and cannot, the desired mode
6178          is EXTRACTION_MODE.  */
6179       if (inner_mode != wanted_inner_mode
6180           && (mode_dependent_address_p (XEXP (inner, 0))
6181               || MEM_VOLATILE_P (inner)
6182               || pos_rtx))
6183         wanted_inner_mode = extraction_mode;
6184     }
6185
6186   orig_pos = pos;
6187
6188   if (BITS_BIG_ENDIAN)
6189     {
6190       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6191          BITS_BIG_ENDIAN style.  If position is constant, compute new
6192          position.  Otherwise, build subtraction.
6193          Note that POS is relative to the mode of the original argument.
6194          If it's a MEM we need to recompute POS relative to that.
6195          However, if we're extracting from (or inserting into) a register,
6196          we want to recompute POS relative to wanted_inner_mode.  */
6197       int width = (MEM_P (inner)
6198                    ? GET_MODE_BITSIZE (is_mode)
6199                    : GET_MODE_BITSIZE (wanted_inner_mode));
6200
6201       if (pos_rtx == 0)
6202         pos = width - len - pos;
6203       else
6204         pos_rtx
6205           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6206       /* POS may be less than 0 now, but we check for that below.
6207          Note that it can only be less than 0 if !MEM_P (inner).  */
6208     }
6209
6210   /* If INNER has a wider mode, and this is a constant extraction, try to
6211      make it smaller and adjust the byte to point to the byte containing
6212      the value.  */
6213   if (wanted_inner_mode != VOIDmode
6214       && inner_mode != wanted_inner_mode
6215       && ! pos_rtx
6216       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6217       && MEM_P (inner)
6218       && ! mode_dependent_address_p (XEXP (inner, 0))
6219       && ! MEM_VOLATILE_P (inner))
6220     {
6221       int offset = 0;
6222
6223       /* The computations below will be correct if the machine is big
6224          endian in both bits and bytes or little endian in bits and bytes.
6225          If it is mixed, we must adjust.  */
6226
6227       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6228          adjust OFFSET to compensate.  */
6229       if (BYTES_BIG_ENDIAN
6230           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6231         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6232
6233       /* We can now move to the desired byte.  */
6234       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6235                 * GET_MODE_SIZE (wanted_inner_mode);
6236       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6237
6238       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6239           && is_mode != wanted_inner_mode)
6240         offset = (GET_MODE_SIZE (is_mode)
6241                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6242
6243       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6244     }
6245
6246   /* If INNER is not memory, we can always get it into the proper mode.  If we
6247      are changing its mode, POS must be a constant and smaller than the size
6248      of the new mode.  */
6249   else if (!MEM_P (inner))
6250     {
6251       if (GET_MODE (inner) != wanted_inner_mode
6252           && (pos_rtx != 0
6253               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6254         return 0;
6255
6256       if (orig_pos < 0)
6257         return 0;
6258
6259       inner = force_to_mode (inner, wanted_inner_mode,
6260                              pos_rtx
6261                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6262                              ? ~(unsigned HOST_WIDE_INT) 0
6263                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6264                                 << orig_pos),
6265                              0);
6266     }
6267
6268   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6269      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6270   if (pos_rtx != 0
6271       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6272     {
6273       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6274
6275       /* If we know that no extraneous bits are set, and that the high
6276          bit is not set, convert extraction to cheaper one - either
6277          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6278          cases.  */
6279       if (flag_expensive_optimizations
6280           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6281               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6282                    & ~(((unsigned HOST_WIDE_INT)
6283                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6284                        >> 1))
6285                   == 0)))
6286         {
6287           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6288
6289           /* Prefer ZERO_EXTENSION, since it gives more information to
6290              backends.  */
6291           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6292             temp = temp1;
6293         }
6294       pos_rtx = temp;
6295     }
6296   else if (pos_rtx != 0
6297            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6298     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6299
6300   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6301      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6302      be a CONST_INT.  */
6303   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6304     pos_rtx = orig_pos_rtx;
6305
6306   else if (pos_rtx == 0)
6307     pos_rtx = GEN_INT (pos);
6308
6309   /* Make the required operation.  See if we can use existing rtx.  */
6310   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6311                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6312   if (! in_dest)
6313     new = gen_lowpart (mode, new);
6314
6315   return new;
6316 }
6317 \f
6318 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6319    with any other operations in X.  Return X without that shift if so.  */
6320
6321 static rtx
6322 extract_left_shift (rtx x, int count)
6323 {
6324   enum rtx_code code = GET_CODE (x);
6325   enum machine_mode mode = GET_MODE (x);
6326   rtx tem;
6327
6328   switch (code)
6329     {
6330     case ASHIFT:
6331       /* This is the shift itself.  If it is wide enough, we will return
6332          either the value being shifted if the shift count is equal to
6333          COUNT or a shift for the difference.  */
6334       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6335           && INTVAL (XEXP (x, 1)) >= count)
6336         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6337                                      INTVAL (XEXP (x, 1)) - count);
6338       break;
6339
6340     case NEG:  case NOT:
6341       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6342         return simplify_gen_unary (code, mode, tem, mode);
6343
6344       break;
6345
6346     case PLUS:  case IOR:  case XOR:  case AND:
6347       /* If we can safely shift this constant and we find the inner shift,
6348          make a new operation.  */
6349       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6350           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6351           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6352         return simplify_gen_binary (code, mode, tem,
6353                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6354
6355       break;
6356
6357     default:
6358       break;
6359     }
6360
6361   return 0;
6362 }
6363 \f
6364 /* Look at the expression rooted at X.  Look for expressions
6365    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6366    Form these expressions.
6367
6368    Return the new rtx, usually just X.
6369
6370    Also, for machines like the VAX that don't have logical shift insns,
6371    try to convert logical to arithmetic shift operations in cases where
6372    they are equivalent.  This undoes the canonicalizations to logical
6373    shifts done elsewhere.
6374
6375    We try, as much as possible, to re-use rtl expressions to save memory.
6376
6377    IN_CODE says what kind of expression we are processing.  Normally, it is
6378    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6379    being kludges), it is MEM.  When processing the arguments of a comparison
6380    or a COMPARE against zero, it is COMPARE.  */
6381
6382 static rtx
6383 make_compound_operation (rtx x, enum rtx_code in_code)
6384 {
6385   enum rtx_code code = GET_CODE (x);
6386   enum machine_mode mode = GET_MODE (x);
6387   int mode_width = GET_MODE_BITSIZE (mode);
6388   rtx rhs, lhs;
6389   enum rtx_code next_code;
6390   int i;
6391   rtx new = 0;
6392   rtx tem;
6393   const char *fmt;
6394
6395   /* Select the code to be used in recursive calls.  Once we are inside an
6396      address, we stay there.  If we have a comparison, set to COMPARE,
6397      but once inside, go back to our default of SET.  */
6398
6399   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6400                : ((code == COMPARE || COMPARISON_P (x))
6401                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6402                : in_code == COMPARE ? SET : in_code);
6403
6404   /* Process depending on the code of this operation.  If NEW is set
6405      nonzero, it will be returned.  */
6406
6407   switch (code)
6408     {
6409     case ASHIFT:
6410       /* Convert shifts by constants into multiplications if inside
6411          an address.  */
6412       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6413           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6414           && INTVAL (XEXP (x, 1)) >= 0)
6415         {
6416           new = make_compound_operation (XEXP (x, 0), next_code);
6417           new = gen_rtx_MULT (mode, new,
6418                               GEN_INT ((HOST_WIDE_INT) 1
6419                                        << INTVAL (XEXP (x, 1))));
6420         }
6421       break;
6422
6423     case AND:
6424       /* If the second operand is not a constant, we can't do anything
6425          with it.  */
6426       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6427         break;
6428
6429       /* If the constant is a power of two minus one and the first operand
6430          is a logical right shift, make an extraction.  */
6431       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6432           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6433         {
6434           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6435           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6436                                  0, in_code == COMPARE);
6437         }
6438
6439       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6440       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6441                && subreg_lowpart_p (XEXP (x, 0))
6442                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6443                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6444         {
6445           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6446                                          next_code);
6447           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6448                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6449                                  0, in_code == COMPARE);
6450         }
6451       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6452       else if ((GET_CODE (XEXP (x, 0)) == XOR
6453                 || GET_CODE (XEXP (x, 0)) == IOR)
6454                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6455                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6456                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6457         {
6458           /* Apply the distributive law, and then try to make extractions.  */
6459           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6460                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6461                                              XEXP (x, 1)),
6462                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6463                                              XEXP (x, 1)));
6464           new = make_compound_operation (new, in_code);
6465         }
6466
6467       /* If we are have (and (rotate X C) M) and C is larger than the number
6468          of bits in M, this is an extraction.  */
6469
6470       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6471                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6472                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6473                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6474         {
6475           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6476           new = make_extraction (mode, new,
6477                                  (GET_MODE_BITSIZE (mode)
6478                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6479                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6480         }
6481
6482       /* On machines without logical shifts, if the operand of the AND is
6483          a logical shift and our mask turns off all the propagated sign
6484          bits, we can replace the logical shift with an arithmetic shift.  */
6485       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6486                && !have_insn_for (LSHIFTRT, mode)
6487                && have_insn_for (ASHIFTRT, mode)
6488                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6489                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6490                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6491                && mode_width <= HOST_BITS_PER_WIDE_INT)
6492         {
6493           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6494
6495           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6496           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6497             SUBST (XEXP (x, 0),
6498                    gen_rtx_ASHIFTRT (mode,
6499                                      make_compound_operation
6500                                      (XEXP (XEXP (x, 0), 0), next_code),
6501                                      XEXP (XEXP (x, 0), 1)));
6502         }
6503
6504       /* If the constant is one less than a power of two, this might be
6505          representable by an extraction even if no shift is present.
6506          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6507          we are in a COMPARE.  */
6508       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6509         new = make_extraction (mode,
6510                                make_compound_operation (XEXP (x, 0),
6511                                                         next_code),
6512                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6513
6514       /* If we are in a comparison and this is an AND with a power of two,
6515          convert this into the appropriate bit extract.  */
6516       else if (in_code == COMPARE
6517                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6518         new = make_extraction (mode,
6519                                make_compound_operation (XEXP (x, 0),
6520                                                         next_code),
6521                                i, NULL_RTX, 1, 1, 0, 1);
6522
6523       break;
6524
6525     case LSHIFTRT:
6526       /* If the sign bit is known to be zero, replace this with an
6527          arithmetic shift.  */
6528       if (have_insn_for (ASHIFTRT, mode)
6529           && ! have_insn_for (LSHIFTRT, mode)
6530           && mode_width <= HOST_BITS_PER_WIDE_INT
6531           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6532         {
6533           new = gen_rtx_ASHIFTRT (mode,
6534                                   make_compound_operation (XEXP (x, 0),
6535                                                            next_code),
6536                                   XEXP (x, 1));
6537           break;
6538         }
6539
6540       /* ... fall through ...  */
6541
6542     case ASHIFTRT:
6543       lhs = XEXP (x, 0);
6544       rhs = XEXP (x, 1);
6545
6546       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6547          this is a SIGN_EXTRACT.  */
6548       if (GET_CODE (rhs) == CONST_INT
6549           && GET_CODE (lhs) == ASHIFT
6550           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6551           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6552         {
6553           new = make_compound_operation (XEXP (lhs, 0), next_code);
6554           new = make_extraction (mode, new,
6555                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6556                                  NULL_RTX, mode_width - INTVAL (rhs),
6557                                  code == LSHIFTRT, 0, in_code == COMPARE);
6558           break;
6559         }
6560
6561       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6562          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6563          also do this for some cases of SIGN_EXTRACT, but it doesn't
6564          seem worth the effort; the case checked for occurs on Alpha.  */
6565
6566       if (!OBJECT_P (lhs)
6567           && ! (GET_CODE (lhs) == SUBREG
6568                 && (OBJECT_P (SUBREG_REG (lhs))))
6569           && GET_CODE (rhs) == CONST_INT
6570           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6571           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6572         new = make_extraction (mode, make_compound_operation (new, next_code),
6573                                0, NULL_RTX, mode_width - INTVAL (rhs),
6574                                code == LSHIFTRT, 0, in_code == COMPARE);
6575
6576       break;
6577
6578     case SUBREG:
6579       /* Call ourselves recursively on the inner expression.  If we are
6580          narrowing the object and it has a different RTL code from
6581          what it originally did, do this SUBREG as a force_to_mode.  */
6582
6583       tem = make_compound_operation (SUBREG_REG (x), in_code);
6584
6585       {
6586         rtx simplified;
6587         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6588                                       SUBREG_BYTE (x));
6589
6590         if (simplified)
6591           tem = simplified;
6592
6593         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6594             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6595             && subreg_lowpart_p (x))
6596           {
6597             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6598                                        0);
6599
6600             /* If we have something other than a SUBREG, we might have
6601                done an expansion, so rerun ourselves.  */
6602             if (GET_CODE (newer) != SUBREG)
6603               newer = make_compound_operation (newer, in_code);
6604
6605             return newer;
6606           }
6607
6608         if (simplified)
6609           return tem;
6610       }
6611       break;
6612
6613     default:
6614       break;
6615     }
6616
6617   if (new)
6618     {
6619       x = gen_lowpart (mode, new);
6620       code = GET_CODE (x);
6621     }
6622
6623   /* Now recursively process each operand of this operation.  */
6624   fmt = GET_RTX_FORMAT (code);
6625   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6626     if (fmt[i] == 'e')
6627       {
6628         new = make_compound_operation (XEXP (x, i), next_code);
6629         SUBST (XEXP (x, i), new);
6630       }
6631
6632   /* If this is a commutative operation, the changes to the operands
6633      may have made it noncanonical.  */
6634   if (COMMUTATIVE_ARITH_P (x)
6635       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6636     {
6637       tem = XEXP (x, 0);
6638       SUBST (XEXP (x, 0), XEXP (x, 1));
6639       SUBST (XEXP (x, 1), tem);
6640     }
6641
6642   return x;
6643 }
6644 \f
6645 /* Given M see if it is a value that would select a field of bits
6646    within an item, but not the entire word.  Return -1 if not.
6647    Otherwise, return the starting position of the field, where 0 is the
6648    low-order bit.
6649
6650    *PLEN is set to the length of the field.  */
6651
6652 static int
6653 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6654 {
6655   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6656   int pos = exact_log2 (m & -m);
6657   int len = 0;
6658
6659   if (pos >= 0)
6660     /* Now shift off the low-order zero bits and see if we have a
6661        power of two minus 1.  */
6662     len = exact_log2 ((m >> pos) + 1);
6663
6664   if (len <= 0)
6665     pos = -1;
6666
6667   *plen = len;
6668   return pos;
6669 }
6670 \f
6671 /* If X refers to a register that equals REG in value, replace these
6672    references with REG.  */
6673 static rtx
6674 canon_reg_for_combine (rtx x, rtx reg)
6675 {
6676   rtx op0, op1, op2;
6677   const char *fmt;
6678   int i;
6679   bool copied;
6680
6681   enum rtx_code code = GET_CODE (x);
6682   switch (GET_RTX_CLASS (code))
6683     {
6684     case RTX_UNARY:
6685       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6686       if (op0 != XEXP (x, 0))
6687         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6688                                    GET_MODE (reg));
6689       break;
6690
6691     case RTX_BIN_ARITH:
6692     case RTX_COMM_ARITH:
6693       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6694       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6695       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6696         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6697       break;
6698
6699     case RTX_COMPARE:
6700     case RTX_COMM_COMPARE:
6701       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6702       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6703       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6704         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6705                                         GET_MODE (op0), op0, op1);
6706       break;
6707
6708     case RTX_TERNARY:
6709     case RTX_BITFIELD_OPS:
6710       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6711       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6712       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6713       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6714         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6715                                      GET_MODE (op0), op0, op1, op2);
6716
6717     case RTX_OBJ:
6718       if (REG_P (x))
6719         {
6720           if (rtx_equal_p (get_last_value (reg), x)
6721               || rtx_equal_p (reg, get_last_value (x)))
6722             return reg;
6723           else
6724             break;
6725         }
6726
6727       /* fall through */
6728
6729     default:
6730       fmt = GET_RTX_FORMAT (code);
6731       copied = false;
6732       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6733         if (fmt[i] == 'e')
6734           {
6735             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6736             if (op != XEXP (x, i))
6737               {
6738                 if (!copied)
6739                   {
6740                     copied = true;
6741                     x = copy_rtx (x);
6742                   }
6743                 XEXP (x, i) = op;
6744               }
6745           }
6746         else if (fmt[i] == 'E')
6747           {
6748             int j;
6749             for (j = 0; j < XVECLEN (x, i); j++)
6750               {
6751                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6752                 if (op != XVECEXP (x, i, j))
6753                   {
6754                     if (!copied)
6755                       {
6756                         copied = true;
6757                         x = copy_rtx (x);
6758                       }
6759                     XVECEXP (x, i, j) = op;
6760                   }
6761               }
6762           }
6763
6764       break;
6765     }
6766
6767   return x;
6768 }
6769
6770 /* Return X converted to MODE.  If the value is already truncated to
6771    MODE we can just return a subreg even though in the general case we
6772    would need an explicit truncation.  */
6773
6774 static rtx
6775 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6776 {
6777   if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6778       || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6779                                 GET_MODE_BITSIZE (GET_MODE (x)))
6780       || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6781     return gen_lowpart (mode, x);
6782   else
6783     return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
6784 }
6785
6786 /* See if X can be simplified knowing that we will only refer to it in
6787    MODE and will only refer to those bits that are nonzero in MASK.
6788    If other bits are being computed or if masking operations are done
6789    that select a superset of the bits in MASK, they can sometimes be
6790    ignored.
6791
6792    Return a possibly simplified expression, but always convert X to
6793    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6794
6795    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6796    are all off in X.  This is used when X will be complemented, by either
6797    NOT, NEG, or XOR.  */
6798
6799 static rtx
6800 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6801                int just_select)
6802 {
6803   enum rtx_code code = GET_CODE (x);
6804   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6805   enum machine_mode op_mode;
6806   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6807   rtx op0, op1, temp;
6808
6809   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6810      code below will do the wrong thing since the mode of such an
6811      expression is VOIDmode.
6812
6813      Also do nothing if X is a CLOBBER; this can happen if X was
6814      the return value from a call to gen_lowpart.  */
6815   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6816     return x;
6817
6818   /* We want to perform the operation is its present mode unless we know
6819      that the operation is valid in MODE, in which case we do the operation
6820      in MODE.  */
6821   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6822               && have_insn_for (code, mode))
6823              ? mode : GET_MODE (x));
6824
6825   /* It is not valid to do a right-shift in a narrower mode
6826      than the one it came in with.  */
6827   if ((code == LSHIFTRT || code == ASHIFTRT)
6828       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6829     op_mode = GET_MODE (x);
6830
6831   /* Truncate MASK to fit OP_MODE.  */
6832   if (op_mode)
6833     mask &= GET_MODE_MASK (op_mode);
6834
6835   /* When we have an arithmetic operation, or a shift whose count we
6836      do not know, we need to assume that all bits up to the highest-order
6837      bit in MASK will be needed.  This is how we form such a mask.  */
6838   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6839     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6840   else
6841     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6842                    - 1);
6843
6844   /* Determine what bits of X are guaranteed to be (non)zero.  */
6845   nonzero = nonzero_bits (x, mode);
6846
6847   /* If none of the bits in X are needed, return a zero.  */
6848   if (! just_select && (nonzero & mask) == 0)
6849     x = const0_rtx;
6850
6851   /* If X is a CONST_INT, return a new one.  Do this here since the
6852      test below will fail.  */
6853   if (GET_CODE (x) == CONST_INT)
6854     {
6855       if (SCALAR_INT_MODE_P (mode))
6856         return gen_int_mode (INTVAL (x) & mask, mode);
6857       else
6858         {
6859           x = GEN_INT (INTVAL (x) & mask);
6860           return gen_lowpart_common (mode, x);
6861         }
6862     }
6863
6864   /* If X is narrower than MODE and we want all the bits in X's mode, just
6865      get X in the proper mode.  */
6866   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6867       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6868     return gen_lowpart (mode, x);
6869
6870   switch (code)
6871     {
6872     case CLOBBER:
6873       /* If X is a (clobber (const_int)), return it since we know we are
6874          generating something that won't match.  */
6875       return x;
6876
6877     case SIGN_EXTEND:
6878     case ZERO_EXTEND:
6879     case ZERO_EXTRACT:
6880     case SIGN_EXTRACT:
6881       x = expand_compound_operation (x);
6882       if (GET_CODE (x) != code)
6883         return force_to_mode (x, mode, mask, next_select);
6884       break;
6885
6886     case SUBREG:
6887       if (subreg_lowpart_p (x)
6888           /* We can ignore the effect of this SUBREG if it narrows the mode or
6889              if the constant masks to zero all the bits the mode doesn't
6890              have.  */
6891           && ((GET_MODE_SIZE (GET_MODE (x))
6892                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6893               || (0 == (mask
6894                         & GET_MODE_MASK (GET_MODE (x))
6895                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6896         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6897       break;
6898
6899     case AND:
6900       /* If this is an AND with a constant, convert it into an AND
6901          whose constant is the AND of that constant with MASK.  If it
6902          remains an AND of MASK, delete it since it is redundant.  */
6903
6904       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6905         {
6906           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6907                                       mask & INTVAL (XEXP (x, 1)));
6908
6909           /* If X is still an AND, see if it is an AND with a mask that
6910              is just some low-order bits.  If so, and it is MASK, we don't
6911              need it.  */
6912
6913           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6914               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6915                   == mask))
6916             x = XEXP (x, 0);
6917
6918           /* If it remains an AND, try making another AND with the bits
6919              in the mode mask that aren't in MASK turned on.  If the
6920              constant in the AND is wide enough, this might make a
6921              cheaper constant.  */
6922
6923           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6924               && GET_MODE_MASK (GET_MODE (x)) != mask
6925               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6926             {
6927               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6928                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6929               int width = GET_MODE_BITSIZE (GET_MODE (x));
6930               rtx y;
6931
6932               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6933                  number, sign extend it.  */
6934               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6935                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6936                 cval |= (HOST_WIDE_INT) -1 << width;
6937
6938               y = simplify_gen_binary (AND, GET_MODE (x),
6939                                        XEXP (x, 0), GEN_INT (cval));
6940               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6941                 x = y;
6942             }
6943
6944           break;
6945         }
6946
6947       goto binop;
6948
6949     case PLUS:
6950       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6951          low-order bits (as in an alignment operation) and FOO is already
6952          aligned to that boundary, mask C1 to that boundary as well.
6953          This may eliminate that PLUS and, later, the AND.  */
6954
6955       {
6956         unsigned int width = GET_MODE_BITSIZE (mode);
6957         unsigned HOST_WIDE_INT smask = mask;
6958
6959         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6960            number, sign extend it.  */
6961
6962         if (width < HOST_BITS_PER_WIDE_INT
6963             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6964           smask |= (HOST_WIDE_INT) -1 << width;
6965
6966         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6967             && exact_log2 (- smask) >= 0
6968             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6969             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6970           return force_to_mode (plus_constant (XEXP (x, 0),
6971                                                (INTVAL (XEXP (x, 1)) & smask)),
6972                                 mode, smask, next_select);
6973       }
6974
6975       /* ... fall through ...  */
6976
6977     case MULT:
6978       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6979          most significant bit in MASK since carries from those bits will
6980          affect the bits we are interested in.  */
6981       mask = fuller_mask;
6982       goto binop;
6983
6984     case MINUS:
6985       /* If X is (minus C Y) where C's least set bit is larger than any bit
6986          in the mask, then we may replace with (neg Y).  */
6987       if (GET_CODE (XEXP (x, 0)) == CONST_INT
6988           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6989                                         & -INTVAL (XEXP (x, 0))))
6990               > mask))
6991         {
6992           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6993                                   GET_MODE (x));
6994           return force_to_mode (x, mode, mask, next_select);
6995         }
6996
6997       /* Similarly, if C contains every bit in the fuller_mask, then we may
6998          replace with (not Y).  */
6999       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7000           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7001               == INTVAL (XEXP (x, 0))))
7002         {
7003           x = simplify_gen_unary (NOT, GET_MODE (x),
7004                                   XEXP (x, 1), GET_MODE (x));
7005           return force_to_mode (x, mode, mask, next_select);
7006         }
7007
7008       mask = fuller_mask;
7009       goto binop;
7010
7011     case IOR:
7012     case XOR:
7013       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7014          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7015          operation which may be a bitfield extraction.  Ensure that the
7016          constant we form is not wider than the mode of X.  */
7017
7018       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7019           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7020           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7021           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7022           && GET_CODE (XEXP (x, 1)) == CONST_INT
7023           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7024                + floor_log2 (INTVAL (XEXP (x, 1))))
7025               < GET_MODE_BITSIZE (GET_MODE (x)))
7026           && (INTVAL (XEXP (x, 1))
7027               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7028         {
7029           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7030                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7031           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7032                                       XEXP (XEXP (x, 0), 0), temp);
7033           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7034                                    XEXP (XEXP (x, 0), 1));
7035           return force_to_mode (x, mode, mask, next_select);
7036         }
7037
7038     binop:
7039       /* For most binary operations, just propagate into the operation and
7040          change the mode if we have an operation of that mode.  */
7041
7042       op0 = gen_lowpart_or_truncate (op_mode,
7043                                      force_to_mode (XEXP (x, 0), mode, mask,
7044                                                     next_select));
7045       op1 = gen_lowpart_or_truncate (op_mode,
7046                                      force_to_mode (XEXP (x, 1), mode, mask,
7047                                         next_select));
7048
7049       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7050         x = simplify_gen_binary (code, op_mode, op0, op1);
7051       break;
7052
7053     case ASHIFT:
7054       /* For left shifts, do the same, but just for the first operand.
7055          However, we cannot do anything with shifts where we cannot
7056          guarantee that the counts are smaller than the size of the mode
7057          because such a count will have a different meaning in a
7058          wider mode.  */
7059
7060       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7061              && INTVAL (XEXP (x, 1)) >= 0
7062              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7063           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7064                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7065                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7066         break;
7067
7068       /* If the shift count is a constant and we can do arithmetic in
7069          the mode of the shift, refine which bits we need.  Otherwise, use the
7070          conservative form of the mask.  */
7071       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7072           && INTVAL (XEXP (x, 1)) >= 0
7073           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7074           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7075         mask >>= INTVAL (XEXP (x, 1));
7076       else
7077         mask = fuller_mask;
7078
7079       op0 = gen_lowpart_or_truncate (op_mode,
7080                                      force_to_mode (XEXP (x, 0), op_mode,
7081                                                     mask, next_select));
7082
7083       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7084         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7085       break;
7086
7087     case LSHIFTRT:
7088       /* Here we can only do something if the shift count is a constant,
7089          this shift constant is valid for the host, and we can do arithmetic
7090          in OP_MODE.  */
7091
7092       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7093           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7094           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7095         {
7096           rtx inner = XEXP (x, 0);
7097           unsigned HOST_WIDE_INT inner_mask;
7098
7099           /* Select the mask of the bits we need for the shift operand.  */
7100           inner_mask = mask << INTVAL (XEXP (x, 1));
7101
7102           /* We can only change the mode of the shift if we can do arithmetic
7103              in the mode of the shift and INNER_MASK is no wider than the
7104              width of X's mode.  */
7105           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7106             op_mode = GET_MODE (x);
7107
7108           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7109
7110           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7111             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7112         }
7113
7114       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7115          shift and AND produces only copies of the sign bit (C2 is one less
7116          than a power of two), we can do this with just a shift.  */
7117
7118       if (GET_CODE (x) == LSHIFTRT
7119           && GET_CODE (XEXP (x, 1)) == CONST_INT
7120           /* The shift puts one of the sign bit copies in the least significant
7121              bit.  */
7122           && ((INTVAL (XEXP (x, 1))
7123                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7124               >= GET_MODE_BITSIZE (GET_MODE (x)))
7125           && exact_log2 (mask + 1) >= 0
7126           /* Number of bits left after the shift must be more than the mask
7127              needs.  */
7128           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7129               <= GET_MODE_BITSIZE (GET_MODE (x)))
7130           /* Must be more sign bit copies than the mask needs.  */
7131           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7132               >= exact_log2 (mask + 1)))
7133         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7134                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7135                                           - exact_log2 (mask + 1)));
7136
7137       goto shiftrt;
7138
7139     case ASHIFTRT:
7140       /* If we are just looking for the sign bit, we don't need this shift at
7141          all, even if it has a variable count.  */
7142       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7143           && (mask == ((unsigned HOST_WIDE_INT) 1
7144                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7145         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7146
7147       /* If this is a shift by a constant, get a mask that contains those bits
7148          that are not copies of the sign bit.  We then have two cases:  If
7149          MASK only includes those bits, this can be a logical shift, which may
7150          allow simplifications.  If MASK is a single-bit field not within
7151          those bits, we are requesting a copy of the sign bit and hence can
7152          shift the sign bit to the appropriate location.  */
7153
7154       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7155           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7156         {
7157           int i;
7158
7159           /* If the considered data is wider than HOST_WIDE_INT, we can't
7160              represent a mask for all its bits in a single scalar.
7161              But we only care about the lower bits, so calculate these.  */
7162
7163           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7164             {
7165               nonzero = ~(HOST_WIDE_INT) 0;
7166
7167               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7168                  is the number of bits a full-width mask would have set.
7169                  We need only shift if these are fewer than nonzero can
7170                  hold.  If not, we must keep all bits set in nonzero.  */
7171
7172               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7173                   < HOST_BITS_PER_WIDE_INT)
7174                 nonzero >>= INTVAL (XEXP (x, 1))
7175                             + HOST_BITS_PER_WIDE_INT
7176                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7177             }
7178           else
7179             {
7180               nonzero = GET_MODE_MASK (GET_MODE (x));
7181               nonzero >>= INTVAL (XEXP (x, 1));
7182             }
7183
7184           if ((mask & ~nonzero) == 0)
7185             {
7186               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7187                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7188               if (GET_CODE (x) != ASHIFTRT)
7189                 return force_to_mode (x, mode, mask, next_select);
7190             }
7191
7192           else if ((i = exact_log2 (mask)) >= 0)
7193             {
7194               x = simplify_shift_const
7195                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7196                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7197
7198               if (GET_CODE (x) != ASHIFTRT)
7199                 return force_to_mode (x, mode, mask, next_select);
7200             }
7201         }
7202
7203       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7204          even if the shift count isn't a constant.  */
7205       if (mask == 1)
7206         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7207                                  XEXP (x, 0), XEXP (x, 1));
7208
7209     shiftrt:
7210
7211       /* If this is a zero- or sign-extension operation that just affects bits
7212          we don't care about, remove it.  Be sure the call above returned
7213          something that is still a shift.  */
7214
7215       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7216           && GET_CODE (XEXP (x, 1)) == CONST_INT
7217           && INTVAL (XEXP (x, 1)) >= 0
7218           && (INTVAL (XEXP (x, 1))
7219               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7220           && GET_CODE (XEXP (x, 0)) == ASHIFT
7221           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7222         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7223                               next_select);
7224
7225       break;
7226
7227     case ROTATE:
7228     case ROTATERT:
7229       /* If the shift count is constant and we can do computations
7230          in the mode of X, compute where the bits we care about are.
7231          Otherwise, we can't do anything.  Don't change the mode of
7232          the shift or propagate MODE into the shift, though.  */
7233       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7234           && INTVAL (XEXP (x, 1)) >= 0)
7235         {
7236           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7237                                             GET_MODE (x), GEN_INT (mask),
7238                                             XEXP (x, 1));
7239           if (temp && GET_CODE (temp) == CONST_INT)
7240             SUBST (XEXP (x, 0),
7241                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7242                                   INTVAL (temp), next_select));
7243         }
7244       break;
7245
7246     case NEG:
7247       /* If we just want the low-order bit, the NEG isn't needed since it
7248          won't change the low-order bit.  */
7249       if (mask == 1)
7250         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7251
7252       /* We need any bits less significant than the most significant bit in
7253          MASK since carries from those bits will affect the bits we are
7254          interested in.  */
7255       mask = fuller_mask;
7256       goto unop;
7257
7258     case NOT:
7259       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7260          same as the XOR case above.  Ensure that the constant we form is not
7261          wider than the mode of X.  */
7262
7263       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7264           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7265           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7266           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7267               < GET_MODE_BITSIZE (GET_MODE (x)))
7268           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7269         {
7270           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7271                                GET_MODE (x));
7272           temp = simplify_gen_binary (XOR, GET_MODE (x),
7273                                       XEXP (XEXP (x, 0), 0), temp);
7274           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7275                                    temp, XEXP (XEXP (x, 0), 1));
7276
7277           return force_to_mode (x, mode, mask, next_select);
7278         }
7279
7280       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7281          use the full mask inside the NOT.  */
7282       mask = fuller_mask;
7283
7284     unop:
7285       op0 = gen_lowpart_or_truncate (op_mode,
7286                                      force_to_mode (XEXP (x, 0), mode, mask,
7287                                                     next_select));
7288       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7289         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7290       break;
7291
7292     case NE:
7293       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7294          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7295          which is equal to STORE_FLAG_VALUE.  */
7296       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7297           && GET_MODE (XEXP (x, 0)) == mode
7298           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7299           && (nonzero_bits (XEXP (x, 0), mode)
7300               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7301         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7302
7303       break;
7304
7305     case IF_THEN_ELSE:
7306       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7307          written in a narrower mode.  We play it safe and do not do so.  */
7308
7309       SUBST (XEXP (x, 1),
7310              gen_lowpart_or_truncate (GET_MODE (x),
7311                                       force_to_mode (XEXP (x, 1), mode,
7312                                                      mask, next_select)));
7313       SUBST (XEXP (x, 2),
7314              gen_lowpart_or_truncate (GET_MODE (x),
7315                                       force_to_mode (XEXP (x, 2), mode,
7316                                                      mask, next_select)));
7317       break;
7318
7319     default:
7320       break;
7321     }
7322
7323   /* Ensure we return a value of the proper mode.  */
7324   return gen_lowpart_or_truncate (mode, x);
7325 }
7326 \f
7327 /* Return nonzero if X is an expression that has one of two values depending on
7328    whether some other value is zero or nonzero.  In that case, we return the
7329    value that is being tested, *PTRUE is set to the value if the rtx being
7330    returned has a nonzero value, and *PFALSE is set to the other alternative.
7331
7332    If we return zero, we set *PTRUE and *PFALSE to X.  */
7333
7334 static rtx
7335 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7336 {
7337   enum machine_mode mode = GET_MODE (x);
7338   enum rtx_code code = GET_CODE (x);
7339   rtx cond0, cond1, true0, true1, false0, false1;
7340   unsigned HOST_WIDE_INT nz;
7341
7342   /* If we are comparing a value against zero, we are done.  */
7343   if ((code == NE || code == EQ)
7344       && XEXP (x, 1) == const0_rtx)
7345     {
7346       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7347       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7348       return XEXP (x, 0);
7349     }
7350
7351   /* If this is a unary operation whose operand has one of two values, apply
7352      our opcode to compute those values.  */
7353   else if (UNARY_P (x)
7354            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7355     {
7356       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7357       *pfalse = simplify_gen_unary (code, mode, false0,
7358                                     GET_MODE (XEXP (x, 0)));
7359       return cond0;
7360     }
7361
7362   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7363      make can't possibly match and would suppress other optimizations.  */
7364   else if (code == COMPARE)
7365     ;
7366
7367   /* If this is a binary operation, see if either side has only one of two
7368      values.  If either one does or if both do and they are conditional on
7369      the same value, compute the new true and false values.  */
7370   else if (BINARY_P (x))
7371     {
7372       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7373       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7374
7375       if ((cond0 != 0 || cond1 != 0)
7376           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7377         {
7378           /* If if_then_else_cond returned zero, then true/false are the
7379              same rtl.  We must copy one of them to prevent invalid rtl
7380              sharing.  */
7381           if (cond0 == 0)
7382             true0 = copy_rtx (true0);
7383           else if (cond1 == 0)
7384             true1 = copy_rtx (true1);
7385
7386           if (COMPARISON_P (x))
7387             {
7388               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7389                                                 true0, true1);
7390               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7391                                                  false0, false1);
7392              }
7393           else
7394             {
7395               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7396               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7397             }
7398
7399           return cond0 ? cond0 : cond1;
7400         }
7401
7402       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7403          operands is zero when the other is nonzero, and vice-versa,
7404          and STORE_FLAG_VALUE is 1 or -1.  */
7405
7406       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7407           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7408               || code == UMAX)
7409           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7410         {
7411           rtx op0 = XEXP (XEXP (x, 0), 1);
7412           rtx op1 = XEXP (XEXP (x, 1), 1);
7413
7414           cond0 = XEXP (XEXP (x, 0), 0);
7415           cond1 = XEXP (XEXP (x, 1), 0);
7416
7417           if (COMPARISON_P (cond0)
7418               && COMPARISON_P (cond1)
7419               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7420                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7421                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7422                   || ((swap_condition (GET_CODE (cond0))
7423                        == reversed_comparison_code (cond1, NULL))
7424                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7425                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7426               && ! side_effects_p (x))
7427             {
7428               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7429               *pfalse = simplify_gen_binary (MULT, mode,
7430                                              (code == MINUS
7431                                               ? simplify_gen_unary (NEG, mode,
7432                                                                     op1, mode)
7433                                               : op1),
7434                                               const_true_rtx);
7435               return cond0;
7436             }
7437         }
7438
7439       /* Similarly for MULT, AND and UMIN, except that for these the result
7440          is always zero.  */
7441       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7442           && (code == MULT || code == AND || code == UMIN)
7443           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7444         {
7445           cond0 = XEXP (XEXP (x, 0), 0);
7446           cond1 = XEXP (XEXP (x, 1), 0);
7447
7448           if (COMPARISON_P (cond0)
7449               && COMPARISON_P (cond1)
7450               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7451                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7452                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7453                   || ((swap_condition (GET_CODE (cond0))
7454                        == reversed_comparison_code (cond1, NULL))
7455                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7456                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7457               && ! side_effects_p (x))
7458             {
7459               *ptrue = *pfalse = const0_rtx;
7460               return cond0;
7461             }
7462         }
7463     }
7464
7465   else if (code == IF_THEN_ELSE)
7466     {
7467       /* If we have IF_THEN_ELSE already, extract the condition and
7468          canonicalize it if it is NE or EQ.  */
7469       cond0 = XEXP (x, 0);
7470       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7471       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7472         return XEXP (cond0, 0);
7473       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7474         {
7475           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7476           return XEXP (cond0, 0);
7477         }
7478       else
7479         return cond0;
7480     }
7481
7482   /* If X is a SUBREG, we can narrow both the true and false values
7483      if the inner expression, if there is a condition.  */
7484   else if (code == SUBREG
7485            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7486                                                &true0, &false0)))
7487     {
7488       true0 = simplify_gen_subreg (mode, true0,
7489                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7490       false0 = simplify_gen_subreg (mode, false0,
7491                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7492       if (true0 && false0)
7493         {
7494           *ptrue = true0;
7495           *pfalse = false0;
7496           return cond0;
7497         }
7498     }
7499
7500   /* If X is a constant, this isn't special and will cause confusions
7501      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7502   else if (CONSTANT_P (x)
7503            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7504     ;
7505
7506   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7507      will be least confusing to the rest of the compiler.  */
7508   else if (mode == BImode)
7509     {
7510       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7511       return x;
7512     }
7513
7514   /* If X is known to be either 0 or -1, those are the true and
7515      false values when testing X.  */
7516   else if (x == constm1_rtx || x == const0_rtx
7517            || (mode != VOIDmode
7518                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7519     {
7520       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7521       return x;
7522     }
7523
7524   /* Likewise for 0 or a single bit.  */
7525   else if (SCALAR_INT_MODE_P (mode)
7526            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7527            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7528     {
7529       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7530       return x;
7531     }
7532
7533   /* Otherwise fail; show no condition with true and false values the same.  */
7534   *ptrue = *pfalse = x;
7535   return 0;
7536 }
7537 \f
7538 /* Return the value of expression X given the fact that condition COND
7539    is known to be true when applied to REG as its first operand and VAL
7540    as its second.  X is known to not be shared and so can be modified in
7541    place.
7542
7543    We only handle the simplest cases, and specifically those cases that
7544    arise with IF_THEN_ELSE expressions.  */
7545
7546 static rtx
7547 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7548 {
7549   enum rtx_code code = GET_CODE (x);
7550   rtx temp;
7551   const char *fmt;
7552   int i, j;
7553
7554   if (side_effects_p (x))
7555     return x;
7556
7557   /* If either operand of the condition is a floating point value,
7558      then we have to avoid collapsing an EQ comparison.  */
7559   if (cond == EQ
7560       && rtx_equal_p (x, reg)
7561       && ! FLOAT_MODE_P (GET_MODE (x))
7562       && ! FLOAT_MODE_P (GET_MODE (val)))
7563     return val;
7564
7565   if (cond == UNEQ && rtx_equal_p (x, reg))
7566     return val;
7567
7568   /* If X is (abs REG) and we know something about REG's relationship
7569      with zero, we may be able to simplify this.  */
7570
7571   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7572     switch (cond)
7573       {
7574       case GE:  case GT:  case EQ:
7575         return XEXP (x, 0);
7576       case LT:  case LE:
7577         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7578                                    XEXP (x, 0),
7579                                    GET_MODE (XEXP (x, 0)));
7580       default:
7581         break;
7582       }
7583
7584   /* The only other cases we handle are MIN, MAX, and comparisons if the
7585      operands are the same as REG and VAL.  */
7586
7587   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7588     {
7589       if (rtx_equal_p (XEXP (x, 0), val))
7590         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7591
7592       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7593         {
7594           if (COMPARISON_P (x))
7595             {
7596               if (comparison_dominates_p (cond, code))
7597                 return const_true_rtx;
7598
7599               code = reversed_comparison_code (x, NULL);
7600               if (code != UNKNOWN
7601                   && comparison_dominates_p (cond, code))
7602                 return const0_rtx;
7603               else
7604                 return x;
7605             }
7606           else if (code == SMAX || code == SMIN
7607                    || code == UMIN || code == UMAX)
7608             {
7609               int unsignedp = (code == UMIN || code == UMAX);
7610
7611               /* Do not reverse the condition when it is NE or EQ.
7612                  This is because we cannot conclude anything about
7613                  the value of 'SMAX (x, y)' when x is not equal to y,
7614                  but we can when x equals y.  */
7615               if ((code == SMAX || code == UMAX)
7616                   && ! (cond == EQ || cond == NE))
7617                 cond = reverse_condition (cond);
7618
7619               switch (cond)
7620                 {
7621                 case GE:   case GT:
7622                   return unsignedp ? x : XEXP (x, 1);
7623                 case LE:   case LT:
7624                   return unsignedp ? x : XEXP (x, 0);
7625                 case GEU:  case GTU:
7626                   return unsignedp ? XEXP (x, 1) : x;
7627                 case LEU:  case LTU:
7628                   return unsignedp ? XEXP (x, 0) : x;
7629                 default:
7630                   break;
7631                 }
7632             }
7633         }
7634     }
7635   else if (code == SUBREG)
7636     {
7637       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7638       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7639
7640       if (SUBREG_REG (x) != r)
7641         {
7642           /* We must simplify subreg here, before we lose track of the
7643              original inner_mode.  */
7644           new = simplify_subreg (GET_MODE (x), r,
7645                                  inner_mode, SUBREG_BYTE (x));
7646           if (new)
7647             return new;
7648           else
7649             SUBST (SUBREG_REG (x), r);
7650         }
7651
7652       return x;
7653     }
7654   /* We don't have to handle SIGN_EXTEND here, because even in the
7655      case of replacing something with a modeless CONST_INT, a
7656      CONST_INT is already (supposed to be) a valid sign extension for
7657      its narrower mode, which implies it's already properly
7658      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7659      story is different.  */
7660   else if (code == ZERO_EXTEND)
7661     {
7662       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7663       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7664
7665       if (XEXP (x, 0) != r)
7666         {
7667           /* We must simplify the zero_extend here, before we lose
7668              track of the original inner_mode.  */
7669           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7670                                           r, inner_mode);
7671           if (new)
7672             return new;
7673           else
7674             SUBST (XEXP (x, 0), r);
7675         }
7676
7677       return x;
7678     }
7679
7680   fmt = GET_RTX_FORMAT (code);
7681   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7682     {
7683       if (fmt[i] == 'e')
7684         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7685       else if (fmt[i] == 'E')
7686         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7687           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7688                                                 cond, reg, val));
7689     }
7690
7691   return x;
7692 }
7693 \f
7694 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7695    assignment as a field assignment.  */
7696
7697 static int
7698 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7699 {
7700   if (x == y || rtx_equal_p (x, y))
7701     return 1;
7702
7703   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7704     return 0;
7705
7706   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7707      Note that all SUBREGs of MEM are paradoxical; otherwise they
7708      would have been rewritten.  */
7709   if (MEM_P (x) && GET_CODE (y) == SUBREG
7710       && MEM_P (SUBREG_REG (y))
7711       && rtx_equal_p (SUBREG_REG (y),
7712                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7713     return 1;
7714
7715   if (MEM_P (y) && GET_CODE (x) == SUBREG
7716       && MEM_P (SUBREG_REG (x))
7717       && rtx_equal_p (SUBREG_REG (x),
7718                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7719     return 1;
7720
7721   /* We used to see if get_last_value of X and Y were the same but that's
7722      not correct.  In one direction, we'll cause the assignment to have
7723      the wrong destination and in the case, we'll import a register into this
7724      insn that might have already have been dead.   So fail if none of the
7725      above cases are true.  */
7726   return 0;
7727 }
7728 \f
7729 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7730    Return that assignment if so.
7731
7732    We only handle the most common cases.  */
7733
7734 static rtx
7735 make_field_assignment (rtx x)
7736 {
7737   rtx dest = SET_DEST (x);
7738   rtx src = SET_SRC (x);
7739   rtx assign;
7740   rtx rhs, lhs;
7741   HOST_WIDE_INT c1;
7742   HOST_WIDE_INT pos;
7743   unsigned HOST_WIDE_INT len;
7744   rtx other;
7745   enum machine_mode mode;
7746
7747   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7748      a clear of a one-bit field.  We will have changed it to
7749      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7750      for a SUBREG.  */
7751
7752   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7753       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7754       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7755       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7756     {
7757       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7758                                 1, 1, 1, 0);
7759       if (assign != 0)
7760         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7761       return x;
7762     }
7763
7764   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7765       && subreg_lowpart_p (XEXP (src, 0))
7766       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7767           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7768       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7769       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7770       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7771       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7772     {
7773       assign = make_extraction (VOIDmode, dest, 0,
7774                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7775                                 1, 1, 1, 0);
7776       if (assign != 0)
7777         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7778       return x;
7779     }
7780
7781   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7782      one-bit field.  */
7783   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7784       && XEXP (XEXP (src, 0), 0) == const1_rtx
7785       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7786     {
7787       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7788                                 1, 1, 1, 0);
7789       if (assign != 0)
7790         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7791       return x;
7792     }
7793
7794   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7795      SRC is an AND with all bits of that field set, then we can discard
7796      the AND.  */
7797   if (GET_CODE (dest) == ZERO_EXTRACT
7798       && GET_CODE (XEXP (dest, 1)) == CONST_INT
7799       && GET_CODE (src) == AND
7800       && GET_CODE (XEXP (src, 1)) == CONST_INT)
7801     {
7802       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7803       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7804       unsigned HOST_WIDE_INT ze_mask;
7805
7806       if (width >= HOST_BITS_PER_WIDE_INT)
7807         ze_mask = -1;
7808       else
7809         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7810
7811       /* Complete overlap.  We can remove the source AND.  */
7812       if ((and_mask & ze_mask) == ze_mask)
7813         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7814
7815       /* Partial overlap.  We can reduce the source AND.  */
7816       if ((and_mask & ze_mask) != and_mask)
7817         {
7818           mode = GET_MODE (src);
7819           src = gen_rtx_AND (mode, XEXP (src, 0),
7820                              gen_int_mode (and_mask & ze_mask, mode));
7821           return gen_rtx_SET (VOIDmode, dest, src);
7822         }
7823     }
7824
7825   /* The other case we handle is assignments into a constant-position
7826      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7827      a mask that has all one bits except for a group of zero bits and
7828      OTHER is known to have zeros where C1 has ones, this is such an
7829      assignment.  Compute the position and length from C1.  Shift OTHER
7830      to the appropriate position, force it to the required mode, and
7831      make the extraction.  Check for the AND in both operands.  */
7832
7833   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7834     return x;
7835
7836   rhs = expand_compound_operation (XEXP (src, 0));
7837   lhs = expand_compound_operation (XEXP (src, 1));
7838
7839   if (GET_CODE (rhs) == AND
7840       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7841       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7842     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7843   else if (GET_CODE (lhs) == AND
7844            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7845            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7846     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7847   else
7848     return x;
7849
7850   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7851   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7852       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7853       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7854     return x;
7855
7856   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7857   if (assign == 0)
7858     return x;
7859
7860   /* The mode to use for the source is the mode of the assignment, or of
7861      what is inside a possible STRICT_LOW_PART.  */
7862   mode = (GET_CODE (assign) == STRICT_LOW_PART
7863           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7864
7865   /* Shift OTHER right POS places and make it the source, restricting it
7866      to the proper length and mode.  */
7867
7868   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7869                                                      GET_MODE (src),
7870                                                      other, pos),
7871                                dest);
7872   src = force_to_mode (src, mode,
7873                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7874                        ? ~(unsigned HOST_WIDE_INT) 0
7875                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7876                        0);
7877
7878   /* If SRC is masked by an AND that does not make a difference in
7879      the value being stored, strip it.  */
7880   if (GET_CODE (assign) == ZERO_EXTRACT
7881       && GET_CODE (XEXP (assign, 1)) == CONST_INT
7882       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7883       && GET_CODE (src) == AND
7884       && GET_CODE (XEXP (src, 1)) == CONST_INT
7885       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7886           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7887     src = XEXP (src, 0);
7888
7889   return gen_rtx_SET (VOIDmode, assign, src);
7890 }
7891 \f
7892 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7893    if so.  */
7894
7895 static rtx
7896 apply_distributive_law (rtx x)
7897 {
7898   enum rtx_code code = GET_CODE (x);
7899   enum rtx_code inner_code;
7900   rtx lhs, rhs, other;
7901   rtx tem;
7902
7903   /* Distributivity is not true for floating point as it can change the
7904      value.  So we don't do it unless -funsafe-math-optimizations.  */
7905   if (FLOAT_MODE_P (GET_MODE (x))
7906       && ! flag_unsafe_math_optimizations)
7907     return x;
7908
7909   /* The outer operation can only be one of the following:  */
7910   if (code != IOR && code != AND && code != XOR
7911       && code != PLUS && code != MINUS)
7912     return x;
7913
7914   lhs = XEXP (x, 0);
7915   rhs = XEXP (x, 1);
7916
7917   /* If either operand is a primitive we can't do anything, so get out
7918      fast.  */
7919   if (OBJECT_P (lhs) || OBJECT_P (rhs))
7920     return x;
7921
7922   lhs = expand_compound_operation (lhs);
7923   rhs = expand_compound_operation (rhs);
7924   inner_code = GET_CODE (lhs);
7925   if (inner_code != GET_CODE (rhs))
7926     return x;
7927
7928   /* See if the inner and outer operations distribute.  */
7929   switch (inner_code)
7930     {
7931     case LSHIFTRT:
7932     case ASHIFTRT:
7933     case AND:
7934     case IOR:
7935       /* These all distribute except over PLUS.  */
7936       if (code == PLUS || code == MINUS)
7937         return x;
7938       break;
7939
7940     case MULT:
7941       if (code != PLUS && code != MINUS)
7942         return x;
7943       break;
7944
7945     case ASHIFT:
7946       /* This is also a multiply, so it distributes over everything.  */
7947       break;
7948
7949     case SUBREG:
7950       /* Non-paradoxical SUBREGs distributes over all operations,
7951          provided the inner modes and byte offsets are the same, this
7952          is an extraction of a low-order part, we don't convert an fp
7953          operation to int or vice versa, this is not a vector mode,
7954          and we would not be converting a single-word operation into a
7955          multi-word operation.  The latter test is not required, but
7956          it prevents generating unneeded multi-word operations.  Some
7957          of the previous tests are redundant given the latter test,
7958          but are retained because they are required for correctness.
7959
7960          We produce the result slightly differently in this case.  */
7961
7962       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7963           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7964           || ! subreg_lowpart_p (lhs)
7965           || (GET_MODE_CLASS (GET_MODE (lhs))
7966               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7967           || (GET_MODE_SIZE (GET_MODE (lhs))
7968               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7969           || VECTOR_MODE_P (GET_MODE (lhs))
7970           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7971           /* Result might need to be truncated.  Don't change mode if
7972              explicit truncation is needed.  */
7973           || !TRULY_NOOP_TRUNCATION
7974                (GET_MODE_BITSIZE (GET_MODE (x)),
7975                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7976         return x;
7977
7978       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7979                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
7980       return gen_lowpart (GET_MODE (x), tem);
7981
7982     default:
7983       return x;
7984     }
7985
7986   /* Set LHS and RHS to the inner operands (A and B in the example
7987      above) and set OTHER to the common operand (C in the example).
7988      There is only one way to do this unless the inner operation is
7989      commutative.  */
7990   if (COMMUTATIVE_ARITH_P (lhs)
7991       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7992     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7993   else if (COMMUTATIVE_ARITH_P (lhs)
7994            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7995     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7996   else if (COMMUTATIVE_ARITH_P (lhs)
7997            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7998     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7999   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8000     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8001   else
8002     return x;
8003
8004   /* Form the new inner operation, seeing if it simplifies first.  */
8005   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8006
8007   /* There is one exception to the general way of distributing:
8008      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8009   if (code == XOR && inner_code == IOR)
8010     {
8011       inner_code = AND;
8012       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8013     }
8014
8015   /* We may be able to continuing distributing the result, so call
8016      ourselves recursively on the inner operation before forming the
8017      outer operation, which we return.  */
8018   return simplify_gen_binary (inner_code, GET_MODE (x),
8019                               apply_distributive_law (tem), other);
8020 }
8021
8022 /* See if X is of the form (* (+ A B) C), and if so convert to
8023    (+ (* A C) (* B C)) and try to simplify.
8024
8025    Most of the time, this results in no change.  However, if some of
8026    the operands are the same or inverses of each other, simplifications
8027    will result.
8028
8029    For example, (and (ior A B) (not B)) can occur as the result of
8030    expanding a bit field assignment.  When we apply the distributive
8031    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8032    which then simplifies to (and (A (not B))).
8033
8034    Note that no checks happen on the validity of applying the inverse
8035    distributive law.  This is pointless since we can do it in the
8036    few places where this routine is called.
8037
8038    N is the index of the term that is decomposed (the arithmetic operation,
8039    i.e. (+ A B) in the first example above).  !N is the index of the term that
8040    is distributed, i.e. of C in the first example above.  */
8041 static rtx
8042 distribute_and_simplify_rtx (rtx x, int n)
8043 {
8044   enum machine_mode mode;
8045   enum rtx_code outer_code, inner_code;
8046   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8047
8048   decomposed = XEXP (x, n);
8049   if (!ARITHMETIC_P (decomposed))
8050     return NULL_RTX;
8051
8052   mode = GET_MODE (x);
8053   outer_code = GET_CODE (x);
8054   distributed = XEXP (x, !n);
8055
8056   inner_code = GET_CODE (decomposed);
8057   inner_op0 = XEXP (decomposed, 0);
8058   inner_op1 = XEXP (decomposed, 1);
8059
8060   /* Special case (and (xor B C) (not A)), which is equivalent to
8061      (xor (ior A B) (ior A C))  */
8062   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8063     {
8064       distributed = XEXP (distributed, 0);
8065       outer_code = IOR;
8066     }
8067
8068   if (n == 0)
8069     {
8070       /* Distribute the second term.  */
8071       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8072       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8073     }
8074   else
8075     {
8076       /* Distribute the first term.  */
8077       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8078       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8079     }
8080
8081   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8082                                                      new_op0, new_op1));
8083   if (GET_CODE (tmp) != outer_code
8084       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8085     return tmp;
8086
8087   return NULL_RTX;
8088 }
8089 \f
8090 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8091    in MODE.  Return an equivalent form, if different from (and VAROP
8092    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8093
8094 static rtx
8095 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8096                           unsigned HOST_WIDE_INT constop)
8097 {
8098   unsigned HOST_WIDE_INT nonzero;
8099   unsigned HOST_WIDE_INT orig_constop;
8100   rtx orig_varop;
8101   int i;
8102
8103   orig_varop = varop;
8104   orig_constop = constop;
8105   if (GET_CODE (varop) == CLOBBER)
8106     return NULL_RTX;
8107
8108   /* Simplify VAROP knowing that we will be only looking at some of the
8109      bits in it.
8110
8111      Note by passing in CONSTOP, we guarantee that the bits not set in
8112      CONSTOP are not significant and will never be examined.  We must
8113      ensure that is the case by explicitly masking out those bits
8114      before returning.  */
8115   varop = force_to_mode (varop, mode, constop, 0);
8116
8117   /* If VAROP is a CLOBBER, we will fail so return it.  */
8118   if (GET_CODE (varop) == CLOBBER)
8119     return varop;
8120
8121   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8122      to VAROP and return the new constant.  */
8123   if (GET_CODE (varop) == CONST_INT)
8124     return gen_int_mode (INTVAL (varop) & constop, mode);
8125
8126   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8127      a call to nonzero_bits, here we don't care about bits outside
8128      MODE.  */
8129
8130   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8131
8132   /* Turn off all bits in the constant that are known to already be zero.
8133      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8134      which is tested below.  */
8135
8136   constop &= nonzero;
8137
8138   /* If we don't have any bits left, return zero.  */
8139   if (constop == 0)
8140     return const0_rtx;
8141
8142   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8143      a power of two, we can replace this with an ASHIFT.  */
8144   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8145       && (i = exact_log2 (constop)) >= 0)
8146     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8147
8148   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8149      or XOR, then try to apply the distributive law.  This may eliminate
8150      operations if either branch can be simplified because of the AND.
8151      It may also make some cases more complex, but those cases probably
8152      won't match a pattern either with or without this.  */
8153
8154   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8155     return
8156       gen_lowpart
8157         (mode,
8158          apply_distributive_law
8159          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8160                                simplify_and_const_int (NULL_RTX,
8161                                                        GET_MODE (varop),
8162                                                        XEXP (varop, 0),
8163                                                        constop),
8164                                simplify_and_const_int (NULL_RTX,
8165                                                        GET_MODE (varop),
8166                                                        XEXP (varop, 1),
8167                                                        constop))));
8168
8169   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8170      the AND and see if one of the operands simplifies to zero.  If so, we
8171      may eliminate it.  */
8172
8173   if (GET_CODE (varop) == PLUS
8174       && exact_log2 (constop + 1) >= 0)
8175     {
8176       rtx o0, o1;
8177
8178       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8179       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8180       if (o0 == const0_rtx)
8181         return o1;
8182       if (o1 == const0_rtx)
8183         return o0;
8184     }
8185
8186   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8187   varop = gen_lowpart (mode, varop);
8188   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8189     return NULL_RTX;
8190
8191   /* If we are only masking insignificant bits, return VAROP.  */
8192   if (constop == nonzero)
8193     return varop;
8194
8195   if (varop == orig_varop && constop == orig_constop)
8196     return NULL_RTX;
8197
8198   /* Otherwise, return an AND.  */
8199   constop = trunc_int_for_mode (constop, mode);
8200   return simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8201 }
8202
8203
8204 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8205    in MODE.
8206
8207    Return an equivalent form, if different from X.  Otherwise, return X.  If
8208    X is zero, we are to always construct the equivalent form.  */
8209
8210 static rtx
8211 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8212                         unsigned HOST_WIDE_INT constop)
8213 {
8214   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8215   if (tem)
8216     return tem;
8217
8218   if (!x)
8219     x = simplify_gen_binary (AND, GET_MODE (varop), varop, GEN_INT (constop));
8220   if (GET_MODE (x) != mode)
8221     x = gen_lowpart (mode, x);
8222   return x;
8223 }
8224 \f
8225 /* Given a REG, X, compute which bits in X can be nonzero.
8226    We don't care about bits outside of those defined in MODE.
8227
8228    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8229    a shift, AND, or zero_extract, we can do better.  */
8230
8231 static rtx
8232 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8233                               rtx known_x ATTRIBUTE_UNUSED,
8234                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8235                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8236                               unsigned HOST_WIDE_INT *nonzero)
8237 {
8238   rtx tem;
8239
8240   /* If X is a register whose nonzero bits value is current, use it.
8241      Otherwise, if X is a register whose value we can find, use that
8242      value.  Otherwise, use the previously-computed global nonzero bits
8243      for this register.  */
8244
8245   if (reg_stat[REGNO (x)].last_set_value != 0
8246       && (reg_stat[REGNO (x)].last_set_mode == mode
8247           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8248               && GET_MODE_CLASS (mode) == MODE_INT))
8249       && (reg_stat[REGNO (x)].last_set_label == label_tick
8250           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8251               && REG_N_SETS (REGNO (x)) == 1
8252               && ! REGNO_REG_SET_P
8253                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8254                   REGNO (x))))
8255       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8256     {
8257       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8258       return NULL;
8259     }
8260
8261   tem = get_last_value (x);
8262
8263   if (tem)
8264     {
8265 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8266       /* If X is narrower than MODE and TEM is a non-negative
8267          constant that would appear negative in the mode of X,
8268          sign-extend it for use in reg_nonzero_bits because some
8269          machines (maybe most) will actually do the sign-extension
8270          and this is the conservative approach.
8271
8272          ??? For 2.5, try to tighten up the MD files in this regard
8273          instead of this kludge.  */
8274
8275       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8276           && GET_CODE (tem) == CONST_INT
8277           && INTVAL (tem) > 0
8278           && 0 != (INTVAL (tem)
8279                    & ((HOST_WIDE_INT) 1
8280                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8281         tem = GEN_INT (INTVAL (tem)
8282                        | ((HOST_WIDE_INT) (-1)
8283                           << GET_MODE_BITSIZE (GET_MODE (x))));
8284 #endif
8285       return tem;
8286     }
8287   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8288     {
8289       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8290
8291       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8292         /* We don't know anything about the upper bits.  */
8293         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8294       *nonzero &= mask;
8295     }
8296
8297   return NULL;
8298 }
8299
8300 /* Return the number of bits at the high-order end of X that are known to
8301    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8302    VOIDmode, X will be used in its own mode.  The returned value  will always
8303    be between 1 and the number of bits in MODE.  */
8304
8305 static rtx
8306 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8307                                      rtx known_x ATTRIBUTE_UNUSED,
8308                                      enum machine_mode known_mode
8309                                      ATTRIBUTE_UNUSED,
8310                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8311                                      unsigned int *result)
8312 {
8313   rtx tem;
8314
8315   if (reg_stat[REGNO (x)].last_set_value != 0
8316       && reg_stat[REGNO (x)].last_set_mode == mode
8317       && (reg_stat[REGNO (x)].last_set_label == label_tick
8318           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8319               && REG_N_SETS (REGNO (x)) == 1
8320               && ! REGNO_REG_SET_P
8321                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8322                   REGNO (x))))
8323       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8324     {
8325       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8326       return NULL;
8327     }
8328
8329   tem = get_last_value (x);
8330   if (tem != 0)
8331     return tem;
8332
8333   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8334       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8335     *result = reg_stat[REGNO (x)].sign_bit_copies;
8336
8337   return NULL;
8338 }
8339 \f
8340 /* Return the number of "extended" bits there are in X, when interpreted
8341    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8342    unsigned quantities, this is the number of high-order zero bits.
8343    For signed quantities, this is the number of copies of the sign bit
8344    minus 1.  In both case, this function returns the number of "spare"
8345    bits.  For example, if two quantities for which this function returns
8346    at least 1 are added, the addition is known not to overflow.
8347
8348    This function will always return 0 unless called during combine, which
8349    implies that it must be called from a define_split.  */
8350
8351 unsigned int
8352 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8353 {
8354   if (nonzero_sign_valid == 0)
8355     return 0;
8356
8357   return (unsignedp
8358           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8359              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8360                                - floor_log2 (nonzero_bits (x, mode)))
8361              : 0)
8362           : num_sign_bit_copies (x, mode) - 1);
8363 }
8364 \f
8365 /* This function is called from `simplify_shift_const' to merge two
8366    outer operations.  Specifically, we have already found that we need
8367    to perform operation *POP0 with constant *PCONST0 at the outermost
8368    position.  We would now like to also perform OP1 with constant CONST1
8369    (with *POP0 being done last).
8370
8371    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8372    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8373    complement the innermost operand, otherwise it is unchanged.
8374
8375    MODE is the mode in which the operation will be done.  No bits outside
8376    the width of this mode matter.  It is assumed that the width of this mode
8377    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8378
8379    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8380    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8381    result is simply *PCONST0.
8382
8383    If the resulting operation cannot be expressed as one operation, we
8384    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8385
8386 static int
8387 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8388 {
8389   enum rtx_code op0 = *pop0;
8390   HOST_WIDE_INT const0 = *pconst0;
8391
8392   const0 &= GET_MODE_MASK (mode);
8393   const1 &= GET_MODE_MASK (mode);
8394
8395   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8396   if (op0 == AND)
8397     const1 &= const0;
8398
8399   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8400      if OP0 is SET.  */
8401
8402   if (op1 == UNKNOWN || op0 == SET)
8403     return 1;
8404
8405   else if (op0 == UNKNOWN)
8406     op0 = op1, const0 = const1;
8407
8408   else if (op0 == op1)
8409     {
8410       switch (op0)
8411         {
8412         case AND:
8413           const0 &= const1;
8414           break;
8415         case IOR:
8416           const0 |= const1;
8417           break;
8418         case XOR:
8419           const0 ^= const1;
8420           break;
8421         case PLUS:
8422           const0 += const1;
8423           break;
8424         case NEG:
8425           op0 = UNKNOWN;
8426           break;
8427         default:
8428           break;
8429         }
8430     }
8431
8432   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8433   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8434     return 0;
8435
8436   /* If the two constants aren't the same, we can't do anything.  The
8437      remaining six cases can all be done.  */
8438   else if (const0 != const1)
8439     return 0;
8440
8441   else
8442     switch (op0)
8443       {
8444       case IOR:
8445         if (op1 == AND)
8446           /* (a & b) | b == b */
8447           op0 = SET;
8448         else /* op1 == XOR */
8449           /* (a ^ b) | b == a | b */
8450           {;}
8451         break;
8452
8453       case XOR:
8454         if (op1 == AND)
8455           /* (a & b) ^ b == (~a) & b */
8456           op0 = AND, *pcomp_p = 1;
8457         else /* op1 == IOR */
8458           /* (a | b) ^ b == a & ~b */
8459           op0 = AND, const0 = ~const0;
8460         break;
8461
8462       case AND:
8463         if (op1 == IOR)
8464           /* (a | b) & b == b */
8465         op0 = SET;
8466         else /* op1 == XOR */
8467           /* (a ^ b) & b) == (~a) & b */
8468           *pcomp_p = 1;
8469         break;
8470       default:
8471         break;
8472       }
8473
8474   /* Check for NO-OP cases.  */
8475   const0 &= GET_MODE_MASK (mode);
8476   if (const0 == 0
8477       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8478     op0 = UNKNOWN;
8479   else if (const0 == 0 && op0 == AND)
8480     op0 = SET;
8481   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8482            && op0 == AND)
8483     op0 = UNKNOWN;
8484
8485   /* ??? Slightly redundant with the above mask, but not entirely.
8486      Moving this above means we'd have to sign-extend the mode mask
8487      for the final test.  */
8488   const0 = trunc_int_for_mode (const0, mode);
8489
8490   *pop0 = op0;
8491   *pconst0 = const0;
8492
8493   return 1;
8494 }
8495 \f
8496 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8497    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8498    simplify it.  Otherwise, return a simplified value.
8499
8500    The shift is normally computed in the widest mode we find in VAROP, as
8501    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8502    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8503
8504 static rtx
8505 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8506                         rtx varop, int orig_count)
8507 {
8508   enum rtx_code orig_code = code;
8509   rtx orig_varop = varop;
8510   int count;
8511   enum machine_mode mode = result_mode;
8512   enum machine_mode shift_mode, tmode;
8513   unsigned int mode_words
8514     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8515   /* We form (outer_op (code varop count) (outer_const)).  */
8516   enum rtx_code outer_op = UNKNOWN;
8517   HOST_WIDE_INT outer_const = 0;
8518   int complement_p = 0;
8519   rtx new, x;
8520
8521   /* Make sure and truncate the "natural" shift on the way in.  We don't
8522      want to do this inside the loop as it makes it more difficult to
8523      combine shifts.  */
8524   if (SHIFT_COUNT_TRUNCATED)
8525     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8526
8527   /* If we were given an invalid count, don't do anything except exactly
8528      what was requested.  */
8529
8530   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8531     return NULL_RTX;
8532
8533   count = orig_count;
8534
8535   /* Unless one of the branches of the `if' in this loop does a `continue',
8536      we will `break' the loop after the `if'.  */
8537
8538   while (count != 0)
8539     {
8540       /* If we have an operand of (clobber (const_int 0)), fail.  */
8541       if (GET_CODE (varop) == CLOBBER)
8542         return NULL_RTX;
8543
8544       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8545          here would cause an infinite loop.  */
8546       if (complement_p)
8547         break;
8548
8549       /* Convert ROTATERT to ROTATE.  */
8550       if (code == ROTATERT)
8551         {
8552           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8553           code = ROTATE;
8554           if (VECTOR_MODE_P (result_mode))
8555             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8556           else
8557             count = bitsize - count;
8558         }
8559
8560       /* We need to determine what mode we will do the shift in.  If the
8561          shift is a right shift or a ROTATE, we must always do it in the mode
8562          it was originally done in.  Otherwise, we can do it in MODE, the
8563          widest mode encountered.  */
8564       shift_mode
8565         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8566            ? result_mode : mode);
8567
8568       /* Handle cases where the count is greater than the size of the mode
8569          minus 1.  For ASHIFT, use the size minus one as the count (this can
8570          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8571          take the count modulo the size.  For other shifts, the result is
8572          zero.
8573
8574          Since these shifts are being produced by the compiler by combining
8575          multiple operations, each of which are defined, we know what the
8576          result is supposed to be.  */
8577
8578       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8579         {
8580           if (code == ASHIFTRT)
8581             count = GET_MODE_BITSIZE (shift_mode) - 1;
8582           else if (code == ROTATE || code == ROTATERT)
8583             count %= GET_MODE_BITSIZE (shift_mode);
8584           else
8585             {
8586               /* We can't simply return zero because there may be an
8587                  outer op.  */
8588               varop = const0_rtx;
8589               count = 0;
8590               break;
8591             }
8592         }
8593
8594       /* An arithmetic right shift of a quantity known to be -1 or 0
8595          is a no-op.  */
8596       if (code == ASHIFTRT
8597           && (num_sign_bit_copies (varop, shift_mode)
8598               == GET_MODE_BITSIZE (shift_mode)))
8599         {
8600           count = 0;
8601           break;
8602         }
8603
8604       /* If we are doing an arithmetic right shift and discarding all but
8605          the sign bit copies, this is equivalent to doing a shift by the
8606          bitsize minus one.  Convert it into that shift because it will often
8607          allow other simplifications.  */
8608
8609       if (code == ASHIFTRT
8610           && (count + num_sign_bit_copies (varop, shift_mode)
8611               >= GET_MODE_BITSIZE (shift_mode)))
8612         count = GET_MODE_BITSIZE (shift_mode) - 1;
8613
8614       /* We simplify the tests below and elsewhere by converting
8615          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8616          `make_compound_operation' will convert it to an ASHIFTRT for
8617          those machines (such as VAX) that don't have an LSHIFTRT.  */
8618       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8619           && code == ASHIFTRT
8620           && ((nonzero_bits (varop, shift_mode)
8621                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8622               == 0))
8623         code = LSHIFTRT;
8624
8625       if (code == LSHIFTRT
8626           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8627           && !(nonzero_bits (varop, shift_mode) >> count))
8628         varop = const0_rtx;
8629       if (code == ASHIFT
8630           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8631           && !((nonzero_bits (varop, shift_mode) << count)
8632                & GET_MODE_MASK (shift_mode)))
8633         varop = const0_rtx;
8634
8635       switch (GET_CODE (varop))
8636         {
8637         case SIGN_EXTEND:
8638         case ZERO_EXTEND:
8639         case SIGN_EXTRACT:
8640         case ZERO_EXTRACT:
8641           new = expand_compound_operation (varop);
8642           if (new != varop)
8643             {
8644               varop = new;
8645               continue;
8646             }
8647           break;
8648
8649         case MEM:
8650           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8651              minus the width of a smaller mode, we can do this with a
8652              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8653           if ((code == ASHIFTRT || code == LSHIFTRT)
8654               && ! mode_dependent_address_p (XEXP (varop, 0))
8655               && ! MEM_VOLATILE_P (varop)
8656               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8657                                          MODE_INT, 1)) != BLKmode)
8658             {
8659               new = adjust_address_nv (varop, tmode,
8660                                        BYTES_BIG_ENDIAN ? 0
8661                                        : count / BITS_PER_UNIT);
8662
8663               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8664                                      : ZERO_EXTEND, mode, new);
8665               count = 0;
8666               continue;
8667             }
8668           break;
8669
8670         case SUBREG:
8671           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8672              the same number of words as what we've seen so far.  Then store
8673              the widest mode in MODE.  */
8674           if (subreg_lowpart_p (varop)
8675               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8676                   > GET_MODE_SIZE (GET_MODE (varop)))
8677               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8678                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8679                  == mode_words)
8680             {
8681               varop = SUBREG_REG (varop);
8682               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8683                 mode = GET_MODE (varop);
8684               continue;
8685             }
8686           break;
8687
8688         case MULT:
8689           /* Some machines use MULT instead of ASHIFT because MULT
8690              is cheaper.  But it is still better on those machines to
8691              merge two shifts into one.  */
8692           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8693               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8694             {
8695               varop
8696                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8697                                        XEXP (varop, 0),
8698                                        GEN_INT (exact_log2 (
8699                                                 INTVAL (XEXP (varop, 1)))));
8700               continue;
8701             }
8702           break;
8703
8704         case UDIV:
8705           /* Similar, for when divides are cheaper.  */
8706           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8707               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8708             {
8709               varop
8710                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8711                                        XEXP (varop, 0),
8712                                        GEN_INT (exact_log2 (
8713                                                 INTVAL (XEXP (varop, 1)))));
8714               continue;
8715             }
8716           break;
8717
8718         case ASHIFTRT:
8719           /* If we are extracting just the sign bit of an arithmetic
8720              right shift, that shift is not needed.  However, the sign
8721              bit of a wider mode may be different from what would be
8722              interpreted as the sign bit in a narrower mode, so, if
8723              the result is narrower, don't discard the shift.  */
8724           if (code == LSHIFTRT
8725               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8726               && (GET_MODE_BITSIZE (result_mode)
8727                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8728             {
8729               varop = XEXP (varop, 0);
8730               continue;
8731             }
8732
8733           /* ... fall through ...  */
8734
8735         case LSHIFTRT:
8736         case ASHIFT:
8737         case ROTATE:
8738           /* Here we have two nested shifts.  The result is usually the
8739              AND of a new shift with a mask.  We compute the result below.  */
8740           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8741               && INTVAL (XEXP (varop, 1)) >= 0
8742               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8743               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8744               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8745               && !VECTOR_MODE_P (result_mode))
8746             {
8747               enum rtx_code first_code = GET_CODE (varop);
8748               unsigned int first_count = INTVAL (XEXP (varop, 1));
8749               unsigned HOST_WIDE_INT mask;
8750               rtx mask_rtx;
8751
8752               /* We have one common special case.  We can't do any merging if
8753                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8754                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8755                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8756                  we can convert it to
8757                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8758                  This simplifies certain SIGN_EXTEND operations.  */
8759               if (code == ASHIFT && first_code == ASHIFTRT
8760                   && count == (GET_MODE_BITSIZE (result_mode)
8761                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8762                 {
8763                   /* C3 has the low-order C1 bits zero.  */
8764
8765                   mask = (GET_MODE_MASK (mode)
8766                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8767
8768                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8769                                                   XEXP (varop, 0), mask);
8770                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8771                                                 varop, count);
8772                   count = first_count;
8773                   code = ASHIFTRT;
8774                   continue;
8775                 }
8776
8777               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8778                  than C1 high-order bits equal to the sign bit, we can convert
8779                  this to either an ASHIFT or an ASHIFTRT depending on the
8780                  two counts.
8781
8782                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8783
8784               if (code == ASHIFTRT && first_code == ASHIFT
8785                   && GET_MODE (varop) == shift_mode
8786                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8787                       > first_count))
8788                 {
8789                   varop = XEXP (varop, 0);
8790                   count -= first_count;
8791                   if (count < 0)
8792                     {
8793                       count = -count;
8794                       code = ASHIFT;
8795                     }
8796
8797                   continue;
8798                 }
8799
8800               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8801                  we can only do this if FIRST_CODE is also ASHIFTRT.
8802
8803                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8804                  ASHIFTRT.
8805
8806                  If the mode of this shift is not the mode of the outer shift,
8807                  we can't do this if either shift is a right shift or ROTATE.
8808
8809                  Finally, we can't do any of these if the mode is too wide
8810                  unless the codes are the same.
8811
8812                  Handle the case where the shift codes are the same
8813                  first.  */
8814
8815               if (code == first_code)
8816                 {
8817                   if (GET_MODE (varop) != result_mode
8818                       && (code == ASHIFTRT || code == LSHIFTRT
8819                           || code == ROTATE))
8820                     break;
8821
8822                   count += first_count;
8823                   varop = XEXP (varop, 0);
8824                   continue;
8825                 }
8826
8827               if (code == ASHIFTRT
8828                   || (code == ROTATE && first_code == ASHIFTRT)
8829                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8830                   || (GET_MODE (varop) != result_mode
8831                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8832                           || first_code == ROTATE
8833                           || code == ROTATE)))
8834                 break;
8835
8836               /* To compute the mask to apply after the shift, shift the
8837                  nonzero bits of the inner shift the same way the
8838                  outer shift will.  */
8839
8840               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8841
8842               mask_rtx
8843                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8844                                                    GEN_INT (count));
8845
8846               /* Give up if we can't compute an outer operation to use.  */
8847               if (mask_rtx == 0
8848                   || GET_CODE (mask_rtx) != CONST_INT
8849                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8850                                         INTVAL (mask_rtx),
8851                                         result_mode, &complement_p))
8852                 break;
8853
8854               /* If the shifts are in the same direction, we add the
8855                  counts.  Otherwise, we subtract them.  */
8856               if ((code == ASHIFTRT || code == LSHIFTRT)
8857                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8858                 count += first_count;
8859               else
8860                 count -= first_count;
8861
8862               /* If COUNT is positive, the new shift is usually CODE,
8863                  except for the two exceptions below, in which case it is
8864                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8865                  always be used  */
8866               if (count > 0
8867                   && ((first_code == ROTATE && code == ASHIFT)
8868                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8869                 code = first_code;
8870               else if (count < 0)
8871                 code = first_code, count = -count;
8872
8873               varop = XEXP (varop, 0);
8874               continue;
8875             }
8876
8877           /* If we have (A << B << C) for any shift, we can convert this to
8878              (A << C << B).  This wins if A is a constant.  Only try this if
8879              B is not a constant.  */
8880
8881           else if (GET_CODE (varop) == code
8882                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
8883                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8884             {
8885               rtx new = simplify_const_binary_operation (code, mode,
8886                                                          XEXP (varop, 0),
8887                                                          GEN_INT (count));
8888               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8889               count = 0;
8890               continue;
8891             }
8892           break;
8893
8894         case NOT:
8895           /* Make this fit the case below.  */
8896           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8897                                GEN_INT (GET_MODE_MASK (mode)));
8898           continue;
8899
8900         case IOR:
8901         case AND:
8902         case XOR:
8903           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8904              with C the size of VAROP - 1 and the shift is logical if
8905              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8906              we have an (le X 0) operation.   If we have an arithmetic shift
8907              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8908              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8909
8910           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8911               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8912               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8913               && (code == LSHIFTRT || code == ASHIFTRT)
8914               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8915               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8916             {
8917               count = 0;
8918               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8919                                   const0_rtx);
8920
8921               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8922                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8923
8924               continue;
8925             }
8926
8927           /* If we have (shift (logical)), move the logical to the outside
8928              to allow it to possibly combine with another logical and the
8929              shift to combine with another shift.  This also canonicalizes to
8930              what a ZERO_EXTRACT looks like.  Also, some machines have
8931              (and (shift)) insns.  */
8932
8933           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8934               /* We can't do this if we have (ashiftrt (xor))  and the
8935                  constant has its sign bit set in shift_mode.  */
8936               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8937                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8938                                               shift_mode))
8939               && (new = simplify_const_binary_operation (code, result_mode,
8940                                                          XEXP (varop, 1),
8941                                                          GEN_INT (count))) != 0
8942               && GET_CODE (new) == CONST_INT
8943               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8944                                   INTVAL (new), result_mode, &complement_p))
8945             {
8946               varop = XEXP (varop, 0);
8947               continue;
8948             }
8949
8950           /* If we can't do that, try to simplify the shift in each arm of the
8951              logical expression, make a new logical expression, and apply
8952              the inverse distributive law.  This also can't be done
8953              for some (ashiftrt (xor)).  */
8954           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8955              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8956                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8957                                              shift_mode)))
8958             {
8959               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8960                                               XEXP (varop, 0), count);
8961               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8962                                               XEXP (varop, 1), count);
8963
8964               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8965                                            lhs, rhs);
8966               varop = apply_distributive_law (varop);
8967
8968               count = 0;
8969               continue;
8970             }
8971           break;
8972
8973         case EQ:
8974           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8975              says that the sign bit can be tested, FOO has mode MODE, C is
8976              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8977              that may be nonzero.  */
8978           if (code == LSHIFTRT
8979               && XEXP (varop, 1) == const0_rtx
8980               && GET_MODE (XEXP (varop, 0)) == result_mode
8981               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8982               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8983               && STORE_FLAG_VALUE == -1
8984               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8985               && merge_outer_ops (&outer_op, &outer_const, XOR,
8986                                   (HOST_WIDE_INT) 1, result_mode,
8987                                   &complement_p))
8988             {
8989               varop = XEXP (varop, 0);
8990               count = 0;
8991               continue;
8992             }
8993           break;
8994
8995         case NEG:
8996           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8997              than the number of bits in the mode is equivalent to A.  */
8998           if (code == LSHIFTRT
8999               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9000               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9001             {
9002               varop = XEXP (varop, 0);
9003               count = 0;
9004               continue;
9005             }
9006
9007           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9008              NEG outside to allow shifts to combine.  */
9009           if (code == ASHIFT
9010               && merge_outer_ops (&outer_op, &outer_const, NEG,
9011                                   (HOST_WIDE_INT) 0, result_mode,
9012                                   &complement_p))
9013             {
9014               varop = XEXP (varop, 0);
9015               continue;
9016             }
9017           break;
9018
9019         case PLUS:
9020           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9021              is one less than the number of bits in the mode is
9022              equivalent to (xor A 1).  */
9023           if (code == LSHIFTRT
9024               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9025               && XEXP (varop, 1) == constm1_rtx
9026               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9027               && merge_outer_ops (&outer_op, &outer_const, XOR,
9028                                   (HOST_WIDE_INT) 1, result_mode,
9029                                   &complement_p))
9030             {
9031               count = 0;
9032               varop = XEXP (varop, 0);
9033               continue;
9034             }
9035
9036           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9037              that might be nonzero in BAR are those being shifted out and those
9038              bits are known zero in FOO, we can replace the PLUS with FOO.
9039              Similarly in the other operand order.  This code occurs when
9040              we are computing the size of a variable-size array.  */
9041
9042           if ((code == ASHIFTRT || code == LSHIFTRT)
9043               && count < HOST_BITS_PER_WIDE_INT
9044               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9045               && (nonzero_bits (XEXP (varop, 1), result_mode)
9046                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9047             {
9048               varop = XEXP (varop, 0);
9049               continue;
9050             }
9051           else if ((code == ASHIFTRT || code == LSHIFTRT)
9052                    && count < HOST_BITS_PER_WIDE_INT
9053                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9054                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9055                             >> count)
9056                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9057                             & nonzero_bits (XEXP (varop, 1),
9058                                                  result_mode)))
9059             {
9060               varop = XEXP (varop, 1);
9061               continue;
9062             }
9063
9064           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9065           if (code == ASHIFT
9066               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9067               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9068                                                          XEXP (varop, 1),
9069                                                          GEN_INT (count))) != 0
9070               && GET_CODE (new) == CONST_INT
9071               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9072                                   INTVAL (new), result_mode, &complement_p))
9073             {
9074               varop = XEXP (varop, 0);
9075               continue;
9076             }
9077
9078           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9079              signbit', and attempt to change the PLUS to an XOR and move it to
9080              the outer operation as is done above in the AND/IOR/XOR case
9081              leg for shift(logical). See details in logical handling above
9082              for reasoning in doing so.  */
9083           if (code == LSHIFTRT
9084               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9085               && mode_signbit_p (result_mode, XEXP (varop, 1))
9086               && (new = simplify_const_binary_operation (code, result_mode,
9087                                                          XEXP (varop, 1),
9088                                                          GEN_INT (count))) != 0
9089               && GET_CODE (new) == CONST_INT
9090               && merge_outer_ops (&outer_op, &outer_const, XOR,
9091                                   INTVAL (new), result_mode, &complement_p))
9092             {
9093               varop = XEXP (varop, 0);
9094               continue;
9095             }
9096
9097           break;
9098
9099         case MINUS:
9100           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9101              with C the size of VAROP - 1 and the shift is logical if
9102              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9103              we have a (gt X 0) operation.  If the shift is arithmetic with
9104              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9105              we have a (neg (gt X 0)) operation.  */
9106
9107           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9108               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9109               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9110               && (code == LSHIFTRT || code == ASHIFTRT)
9111               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9112               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9113               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9114             {
9115               count = 0;
9116               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9117                                   const0_rtx);
9118
9119               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9120                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9121
9122               continue;
9123             }
9124           break;
9125
9126         case TRUNCATE:
9127           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9128              if the truncate does not affect the value.  */
9129           if (code == LSHIFTRT
9130               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9131               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9132               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9133                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9134                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9135             {
9136               rtx varop_inner = XEXP (varop, 0);
9137
9138               varop_inner
9139                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9140                                     XEXP (varop_inner, 0),
9141                                     GEN_INT
9142                                     (count + INTVAL (XEXP (varop_inner, 1))));
9143               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9144               count = 0;
9145               continue;
9146             }
9147           break;
9148
9149         default:
9150           break;
9151         }
9152
9153       break;
9154     }
9155
9156   /* We need to determine what mode to do the shift in.  If the shift is
9157      a right shift or ROTATE, we must always do it in the mode it was
9158      originally done in.  Otherwise, we can do it in MODE, the widest mode
9159      encountered.  The code we care about is that of the shift that will
9160      actually be done, not the shift that was originally requested.  */
9161   shift_mode
9162     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9163        ? result_mode : mode);
9164
9165   /* We have now finished analyzing the shift.  The result should be
9166      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9167      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9168      to the result of the shift.  OUTER_CONST is the relevant constant,
9169      but we must turn off all bits turned off in the shift.  */
9170
9171   if (outer_op == UNKNOWN
9172       && orig_code == code && orig_count == count
9173       && varop == orig_varop
9174       && shift_mode == GET_MODE (varop))
9175     return NULL_RTX;
9176
9177   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9178   varop = gen_lowpart (shift_mode, varop);
9179   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9180     return NULL_RTX;
9181
9182   /* If we have an outer operation and we just made a shift, it is
9183      possible that we could have simplified the shift were it not
9184      for the outer operation.  So try to do the simplification
9185      recursively.  */
9186
9187   if (outer_op != UNKNOWN)
9188     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9189   else
9190     x = NULL_RTX;
9191
9192   if (x == NULL_RTX)
9193     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9194
9195   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9196      turn off all the bits that the shift would have turned off.  */
9197   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9198     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9199                                 GET_MODE_MASK (result_mode) >> orig_count);
9200
9201   /* Do the remainder of the processing in RESULT_MODE.  */
9202   x = gen_lowpart_or_truncate (result_mode, x);
9203
9204   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9205      operation.  */
9206   if (complement_p)
9207     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9208
9209   if (outer_op != UNKNOWN)
9210     {
9211       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9212         outer_const = trunc_int_for_mode (outer_const, result_mode);
9213
9214       if (outer_op == AND)
9215         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9216       else if (outer_op == SET)
9217         /* This means that we have determined that the result is
9218            equivalent to a constant.  This should be rare.  */
9219         x = GEN_INT (outer_const);
9220       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9221         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9222       else
9223         x = simplify_gen_binary (outer_op, result_mode, x,
9224                                  GEN_INT (outer_const));
9225     }
9226
9227   return x;
9228 }
9229
9230 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9231    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9232    return X or, if it is NULL, synthesize the expression with
9233    simplify_gen_binary.  Otherwise, return a simplified value.
9234
9235    The shift is normally computed in the widest mode we find in VAROP, as
9236    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9237    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9238
9239 static rtx
9240 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9241                       rtx varop, int count)
9242 {
9243   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9244   if (tem)
9245     return tem;
9246
9247   if (!x)
9248     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9249   if (GET_MODE (x) != result_mode)
9250     x = gen_lowpart (result_mode, x);
9251   return x;
9252 }
9253
9254 \f
9255 /* Like recog, but we receive the address of a pointer to a new pattern.
9256    We try to match the rtx that the pointer points to.
9257    If that fails, we may try to modify or replace the pattern,
9258    storing the replacement into the same pointer object.
9259
9260    Modifications include deletion or addition of CLOBBERs.
9261
9262    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9263    the CLOBBERs are placed.
9264
9265    The value is the final insn code from the pattern ultimately matched,
9266    or -1.  */
9267
9268 static int
9269 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9270 {
9271   rtx pat = *pnewpat;
9272   int insn_code_number;
9273   int num_clobbers_to_add = 0;
9274   int i;
9275   rtx notes = 0;
9276   rtx old_notes, old_pat;
9277
9278   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9279      we use to indicate that something didn't match.  If we find such a
9280      thing, force rejection.  */
9281   if (GET_CODE (pat) == PARALLEL)
9282     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9283       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9284           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9285         return -1;
9286
9287   old_pat = PATTERN (insn);
9288   old_notes = REG_NOTES (insn);
9289   PATTERN (insn) = pat;
9290   REG_NOTES (insn) = 0;
9291
9292   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9293
9294   /* If it isn't, there is the possibility that we previously had an insn
9295      that clobbered some register as a side effect, but the combined
9296      insn doesn't need to do that.  So try once more without the clobbers
9297      unless this represents an ASM insn.  */
9298
9299   if (insn_code_number < 0 && ! check_asm_operands (pat)
9300       && GET_CODE (pat) == PARALLEL)
9301     {
9302       int pos;
9303
9304       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9305         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9306           {
9307             if (i != pos)
9308               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9309             pos++;
9310           }
9311
9312       SUBST_INT (XVECLEN (pat, 0), pos);
9313
9314       if (pos == 1)
9315         pat = XVECEXP (pat, 0, 0);
9316
9317       PATTERN (insn) = pat;
9318       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9319     }
9320   PATTERN (insn) = old_pat;
9321   REG_NOTES (insn) = old_notes;
9322
9323   /* Recognize all noop sets, these will be killed by followup pass.  */
9324   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9325     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9326
9327   /* If we had any clobbers to add, make a new pattern than contains
9328      them.  Then check to make sure that all of them are dead.  */
9329   if (num_clobbers_to_add)
9330     {
9331       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9332                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9333                                                   ? (XVECLEN (pat, 0)
9334                                                      + num_clobbers_to_add)
9335                                                   : num_clobbers_to_add + 1));
9336
9337       if (GET_CODE (pat) == PARALLEL)
9338         for (i = 0; i < XVECLEN (pat, 0); i++)
9339           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9340       else
9341         XVECEXP (newpat, 0, 0) = pat;
9342
9343       add_clobbers (newpat, insn_code_number);
9344
9345       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9346            i < XVECLEN (newpat, 0); i++)
9347         {
9348           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9349               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9350             return -1;
9351           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9352                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9353         }
9354       pat = newpat;
9355     }
9356
9357   *pnewpat = pat;
9358   *pnotes = notes;
9359
9360   return insn_code_number;
9361 }
9362 \f
9363 /* Like gen_lowpart_general but for use by combine.  In combine it
9364    is not possible to create any new pseudoregs.  However, it is
9365    safe to create invalid memory addresses, because combine will
9366    try to recognize them and all they will do is make the combine
9367    attempt fail.
9368
9369    If for some reason this cannot do its job, an rtx
9370    (clobber (const_int 0)) is returned.
9371    An insn containing that will not be recognized.  */
9372
9373 static rtx
9374 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9375 {
9376   enum machine_mode imode = GET_MODE (x);
9377   unsigned int osize = GET_MODE_SIZE (omode);
9378   unsigned int isize = GET_MODE_SIZE (imode);
9379   rtx result;
9380
9381   if (omode == imode)
9382     return x;
9383
9384   /* Return identity if this is a CONST or symbolic reference.  */
9385   if (omode == Pmode
9386       && (GET_CODE (x) == CONST
9387           || GET_CODE (x) == SYMBOL_REF
9388           || GET_CODE (x) == LABEL_REF))
9389     return x;
9390
9391   /* We can only support MODE being wider than a word if X is a
9392      constant integer or has a mode the same size.  */
9393   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9394       && ! ((imode == VOIDmode
9395              && (GET_CODE (x) == CONST_INT
9396                  || GET_CODE (x) == CONST_DOUBLE))
9397             || isize == osize))
9398     goto fail;
9399
9400   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9401      won't know what to do.  So we will strip off the SUBREG here and
9402      process normally.  */
9403   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9404     {
9405       x = SUBREG_REG (x);
9406
9407       /* For use in case we fall down into the address adjustments
9408          further below, we need to adjust the known mode and size of
9409          x; imode and isize, since we just adjusted x.  */
9410       imode = GET_MODE (x);
9411
9412       if (imode == omode)
9413         return x;
9414
9415       isize = GET_MODE_SIZE (imode);
9416     }
9417
9418   result = gen_lowpart_common (omode, x);
9419
9420 #ifdef CANNOT_CHANGE_MODE_CLASS
9421   if (result != 0 && GET_CODE (result) == SUBREG)
9422     record_subregs_of_mode (result);
9423 #endif
9424
9425   if (result)
9426     return result;
9427
9428   if (MEM_P (x))
9429     {
9430       int offset = 0;
9431
9432       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9433          address.  */
9434       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9435         goto fail;
9436
9437       /* If we want to refer to something bigger than the original memref,
9438          generate a paradoxical subreg instead.  That will force a reload
9439          of the original memref X.  */
9440       if (isize < osize)
9441         return gen_rtx_SUBREG (omode, x, 0);
9442
9443       if (WORDS_BIG_ENDIAN)
9444         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9445
9446       /* Adjust the address so that the address-after-the-data is
9447          unchanged.  */
9448       if (BYTES_BIG_ENDIAN)
9449         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9450
9451       return adjust_address_nv (x, omode, offset);
9452     }
9453
9454   /* If X is a comparison operator, rewrite it in a new mode.  This
9455      probably won't match, but may allow further simplifications.  */
9456   else if (COMPARISON_P (x))
9457     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9458
9459   /* If we couldn't simplify X any other way, just enclose it in a
9460      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9461      include an explicit SUBREG or we may simplify it further in combine.  */
9462   else
9463     {
9464       int offset = 0;
9465       rtx res;
9466
9467       offset = subreg_lowpart_offset (omode, imode);
9468       if (imode == VOIDmode)
9469         {
9470           imode = int_mode_for_mode (omode);
9471           x = gen_lowpart_common (imode, x);
9472           if (x == NULL)
9473             goto fail;
9474         }
9475       res = simplify_gen_subreg (omode, x, imode, offset);
9476       if (res)
9477         return res;
9478     }
9479
9480  fail:
9481   return gen_rtx_CLOBBER (imode, const0_rtx);
9482 }
9483 \f
9484 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9485    comparison code that will be tested.
9486
9487    The result is a possibly different comparison code to use.  *POP0 and
9488    *POP1 may be updated.
9489
9490    It is possible that we might detect that a comparison is either always
9491    true or always false.  However, we do not perform general constant
9492    folding in combine, so this knowledge isn't useful.  Such tautologies
9493    should have been detected earlier.  Hence we ignore all such cases.  */
9494
9495 static enum rtx_code
9496 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9497 {
9498   rtx op0 = *pop0;
9499   rtx op1 = *pop1;
9500   rtx tem, tem1;
9501   int i;
9502   enum machine_mode mode, tmode;
9503
9504   /* Try a few ways of applying the same transformation to both operands.  */
9505   while (1)
9506     {
9507 #ifndef WORD_REGISTER_OPERATIONS
9508       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9509          so check specially.  */
9510       if (code != GTU && code != GEU && code != LTU && code != LEU
9511           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9512           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9513           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9514           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9515           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9516           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9517               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9518           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9519           && XEXP (op0, 1) == XEXP (op1, 1)
9520           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9521           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9522           && (INTVAL (XEXP (op0, 1))
9523               == (GET_MODE_BITSIZE (GET_MODE (op0))
9524                   - (GET_MODE_BITSIZE
9525                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9526         {
9527           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9528           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9529         }
9530 #endif
9531
9532       /* If both operands are the same constant shift, see if we can ignore the
9533          shift.  We can if the shift is a rotate or if the bits shifted out of
9534          this shift are known to be zero for both inputs and if the type of
9535          comparison is compatible with the shift.  */
9536       if (GET_CODE (op0) == GET_CODE (op1)
9537           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9538           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9539               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9540                   && (code != GT && code != LT && code != GE && code != LE))
9541               || (GET_CODE (op0) == ASHIFTRT
9542                   && (code != GTU && code != LTU
9543                       && code != GEU && code != LEU)))
9544           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9545           && INTVAL (XEXP (op0, 1)) >= 0
9546           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9547           && XEXP (op0, 1) == XEXP (op1, 1))
9548         {
9549           enum machine_mode mode = GET_MODE (op0);
9550           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9551           int shift_count = INTVAL (XEXP (op0, 1));
9552
9553           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9554             mask &= (mask >> shift_count) << shift_count;
9555           else if (GET_CODE (op0) == ASHIFT)
9556             mask = (mask & (mask << shift_count)) >> shift_count;
9557
9558           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9559               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9560             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9561           else
9562             break;
9563         }
9564
9565       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9566          SUBREGs are of the same mode, and, in both cases, the AND would
9567          be redundant if the comparison was done in the narrower mode,
9568          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9569          and the operand's possibly nonzero bits are 0xffffff01; in that case
9570          if we only care about QImode, we don't need the AND).  This case
9571          occurs if the output mode of an scc insn is not SImode and
9572          STORE_FLAG_VALUE == 1 (e.g., the 386).
9573
9574          Similarly, check for a case where the AND's are ZERO_EXTEND
9575          operations from some narrower mode even though a SUBREG is not
9576          present.  */
9577
9578       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9579                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9580                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9581         {
9582           rtx inner_op0 = XEXP (op0, 0);
9583           rtx inner_op1 = XEXP (op1, 0);
9584           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9585           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9586           int changed = 0;
9587
9588           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9589               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9590                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9591               && (GET_MODE (SUBREG_REG (inner_op0))
9592                   == GET_MODE (SUBREG_REG (inner_op1)))
9593               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9594                   <= HOST_BITS_PER_WIDE_INT)
9595               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9596                                              GET_MODE (SUBREG_REG (inner_op0)))))
9597               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9598                                              GET_MODE (SUBREG_REG (inner_op1))))))
9599             {
9600               op0 = SUBREG_REG (inner_op0);
9601               op1 = SUBREG_REG (inner_op1);
9602
9603               /* The resulting comparison is always unsigned since we masked
9604                  off the original sign bit.  */
9605               code = unsigned_condition (code);
9606
9607               changed = 1;
9608             }
9609
9610           else if (c0 == c1)
9611             for (tmode = GET_CLASS_NARROWEST_MODE
9612                  (GET_MODE_CLASS (GET_MODE (op0)));
9613                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9614               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9615                 {
9616                   op0 = gen_lowpart (tmode, inner_op0);
9617                   op1 = gen_lowpart (tmode, inner_op1);
9618                   code = unsigned_condition (code);
9619                   changed = 1;
9620                   break;
9621                 }
9622
9623           if (! changed)
9624             break;
9625         }
9626
9627       /* If both operands are NOT, we can strip off the outer operation
9628          and adjust the comparison code for swapped operands; similarly for
9629          NEG, except that this must be an equality comparison.  */
9630       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9631                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9632                    && (code == EQ || code == NE)))
9633         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9634
9635       else
9636         break;
9637     }
9638
9639   /* If the first operand is a constant, swap the operands and adjust the
9640      comparison code appropriately, but don't do this if the second operand
9641      is already a constant integer.  */
9642   if (swap_commutative_operands_p (op0, op1))
9643     {
9644       tem = op0, op0 = op1, op1 = tem;
9645       code = swap_condition (code);
9646     }
9647
9648   /* We now enter a loop during which we will try to simplify the comparison.
9649      For the most part, we only are concerned with comparisons with zero,
9650      but some things may really be comparisons with zero but not start
9651      out looking that way.  */
9652
9653   while (GET_CODE (op1) == CONST_INT)
9654     {
9655       enum machine_mode mode = GET_MODE (op0);
9656       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9657       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9658       int equality_comparison_p;
9659       int sign_bit_comparison_p;
9660       int unsigned_comparison_p;
9661       HOST_WIDE_INT const_op;
9662
9663       /* We only want to handle integral modes.  This catches VOIDmode,
9664          CCmode, and the floating-point modes.  An exception is that we
9665          can handle VOIDmode if OP0 is a COMPARE or a comparison
9666          operation.  */
9667
9668       if (GET_MODE_CLASS (mode) != MODE_INT
9669           && ! (mode == VOIDmode
9670                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9671         break;
9672
9673       /* Get the constant we are comparing against and turn off all bits
9674          not on in our mode.  */
9675       const_op = INTVAL (op1);
9676       if (mode != VOIDmode)
9677         const_op = trunc_int_for_mode (const_op, mode);
9678       op1 = GEN_INT (const_op);
9679
9680       /* If we are comparing against a constant power of two and the value
9681          being compared can only have that single bit nonzero (e.g., it was
9682          `and'ed with that bit), we can replace this with a comparison
9683          with zero.  */
9684       if (const_op
9685           && (code == EQ || code == NE || code == GE || code == GEU
9686               || code == LT || code == LTU)
9687           && mode_width <= HOST_BITS_PER_WIDE_INT
9688           && exact_log2 (const_op) >= 0
9689           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9690         {
9691           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9692           op1 = const0_rtx, const_op = 0;
9693         }
9694
9695       /* Similarly, if we are comparing a value known to be either -1 or
9696          0 with -1, change it to the opposite comparison against zero.  */
9697
9698       if (const_op == -1
9699           && (code == EQ || code == NE || code == GT || code == LE
9700               || code == GEU || code == LTU)
9701           && num_sign_bit_copies (op0, mode) == mode_width)
9702         {
9703           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9704           op1 = const0_rtx, const_op = 0;
9705         }
9706
9707       /* Do some canonicalizations based on the comparison code.  We prefer
9708          comparisons against zero and then prefer equality comparisons.
9709          If we can reduce the size of a constant, we will do that too.  */
9710
9711       switch (code)
9712         {
9713         case LT:
9714           /* < C is equivalent to <= (C - 1) */
9715           if (const_op > 0)
9716             {
9717               const_op -= 1;
9718               op1 = GEN_INT (const_op);
9719               code = LE;
9720               /* ... fall through to LE case below.  */
9721             }
9722           else
9723             break;
9724
9725         case LE:
9726           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9727           if (const_op < 0)
9728             {
9729               const_op += 1;
9730               op1 = GEN_INT (const_op);
9731               code = LT;
9732             }
9733
9734           /* If we are doing a <= 0 comparison on a value known to have
9735              a zero sign bit, we can replace this with == 0.  */
9736           else if (const_op == 0
9737                    && mode_width <= HOST_BITS_PER_WIDE_INT
9738                    && (nonzero_bits (op0, mode)
9739                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9740             code = EQ;
9741           break;
9742
9743         case GE:
9744           /* >= C is equivalent to > (C - 1).  */
9745           if (const_op > 0)
9746             {
9747               const_op -= 1;
9748               op1 = GEN_INT (const_op);
9749               code = GT;
9750               /* ... fall through to GT below.  */
9751             }
9752           else
9753             break;
9754
9755         case GT:
9756           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9757           if (const_op < 0)
9758             {
9759               const_op += 1;
9760               op1 = GEN_INT (const_op);
9761               code = GE;
9762             }
9763
9764           /* If we are doing a > 0 comparison on a value known to have
9765              a zero sign bit, we can replace this with != 0.  */
9766           else if (const_op == 0
9767                    && mode_width <= HOST_BITS_PER_WIDE_INT
9768                    && (nonzero_bits (op0, mode)
9769                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9770             code = NE;
9771           break;
9772
9773         case LTU:
9774           /* < C is equivalent to <= (C - 1).  */
9775           if (const_op > 0)
9776             {
9777               const_op -= 1;
9778               op1 = GEN_INT (const_op);
9779               code = LEU;
9780               /* ... fall through ...  */
9781             }
9782
9783           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9784           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9785                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9786             {
9787               const_op = 0, op1 = const0_rtx;
9788               code = GE;
9789               break;
9790             }
9791           else
9792             break;
9793
9794         case LEU:
9795           /* unsigned <= 0 is equivalent to == 0 */
9796           if (const_op == 0)
9797             code = EQ;
9798
9799           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9800           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9801                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9802             {
9803               const_op = 0, op1 = const0_rtx;
9804               code = GE;
9805             }
9806           break;
9807
9808         case GEU:
9809           /* >= C is equivalent to > (C - 1).  */
9810           if (const_op > 1)
9811             {
9812               const_op -= 1;
9813               op1 = GEN_INT (const_op);
9814               code = GTU;
9815               /* ... fall through ...  */
9816             }
9817
9818           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9819           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9820                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9821             {
9822               const_op = 0, op1 = const0_rtx;
9823               code = LT;
9824               break;
9825             }
9826           else
9827             break;
9828
9829         case GTU:
9830           /* unsigned > 0 is equivalent to != 0 */
9831           if (const_op == 0)
9832             code = NE;
9833
9834           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9835           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9836                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9837             {
9838               const_op = 0, op1 = const0_rtx;
9839               code = LT;
9840             }
9841           break;
9842
9843         default:
9844           break;
9845         }
9846
9847       /* Compute some predicates to simplify code below.  */
9848
9849       equality_comparison_p = (code == EQ || code == NE);
9850       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9851       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9852                                || code == GEU);
9853
9854       /* If this is a sign bit comparison and we can do arithmetic in
9855          MODE, say that we will only be needing the sign bit of OP0.  */
9856       if (sign_bit_comparison_p
9857           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9858         op0 = force_to_mode (op0, mode,
9859                              ((HOST_WIDE_INT) 1
9860                               << (GET_MODE_BITSIZE (mode) - 1)),
9861                              0);
9862
9863       /* Now try cases based on the opcode of OP0.  If none of the cases
9864          does a "continue", we exit this loop immediately after the
9865          switch.  */
9866
9867       switch (GET_CODE (op0))
9868         {
9869         case ZERO_EXTRACT:
9870           /* If we are extracting a single bit from a variable position in
9871              a constant that has only a single bit set and are comparing it
9872              with zero, we can convert this into an equality comparison
9873              between the position and the location of the single bit.  */
9874           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9875              have already reduced the shift count modulo the word size.  */
9876           if (!SHIFT_COUNT_TRUNCATED
9877               && GET_CODE (XEXP (op0, 0)) == CONST_INT
9878               && XEXP (op0, 1) == const1_rtx
9879               && equality_comparison_p && const_op == 0
9880               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9881             {
9882               if (BITS_BIG_ENDIAN)
9883                 {
9884                   enum machine_mode new_mode
9885                     = mode_for_extraction (EP_extzv, 1);
9886                   if (new_mode == MAX_MACHINE_MODE)
9887                     i = BITS_PER_WORD - 1 - i;
9888                   else
9889                     {
9890                       mode = new_mode;
9891                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
9892                     }
9893                 }
9894
9895               op0 = XEXP (op0, 2);
9896               op1 = GEN_INT (i);
9897               const_op = i;
9898
9899               /* Result is nonzero iff shift count is equal to I.  */
9900               code = reverse_condition (code);
9901               continue;
9902             }
9903
9904           /* ... fall through ...  */
9905
9906         case SIGN_EXTRACT:
9907           tem = expand_compound_operation (op0);
9908           if (tem != op0)
9909             {
9910               op0 = tem;
9911               continue;
9912             }
9913           break;
9914
9915         case NOT:
9916           /* If testing for equality, we can take the NOT of the constant.  */
9917           if (equality_comparison_p
9918               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9919             {
9920               op0 = XEXP (op0, 0);
9921               op1 = tem;
9922               continue;
9923             }
9924
9925           /* If just looking at the sign bit, reverse the sense of the
9926              comparison.  */
9927           if (sign_bit_comparison_p)
9928             {
9929               op0 = XEXP (op0, 0);
9930               code = (code == GE ? LT : GE);
9931               continue;
9932             }
9933           break;
9934
9935         case NEG:
9936           /* If testing for equality, we can take the NEG of the constant.  */
9937           if (equality_comparison_p
9938               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9939             {
9940               op0 = XEXP (op0, 0);
9941               op1 = tem;
9942               continue;
9943             }
9944
9945           /* The remaining cases only apply to comparisons with zero.  */
9946           if (const_op != 0)
9947             break;
9948
9949           /* When X is ABS or is known positive,
9950              (neg X) is < 0 if and only if X != 0.  */
9951
9952           if (sign_bit_comparison_p
9953               && (GET_CODE (XEXP (op0, 0)) == ABS
9954                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9955                       && (nonzero_bits (XEXP (op0, 0), mode)
9956                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9957             {
9958               op0 = XEXP (op0, 0);
9959               code = (code == LT ? NE : EQ);
9960               continue;
9961             }
9962
9963           /* If we have NEG of something whose two high-order bits are the
9964              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9965           if (num_sign_bit_copies (op0, mode) >= 2)
9966             {
9967               op0 = XEXP (op0, 0);
9968               code = swap_condition (code);
9969               continue;
9970             }
9971           break;
9972
9973         case ROTATE:
9974           /* If we are testing equality and our count is a constant, we
9975              can perform the inverse operation on our RHS.  */
9976           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9977               && (tem = simplify_binary_operation (ROTATERT, mode,
9978                                                    op1, XEXP (op0, 1))) != 0)
9979             {
9980               op0 = XEXP (op0, 0);
9981               op1 = tem;
9982               continue;
9983             }
9984
9985           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9986              a particular bit.  Convert it to an AND of a constant of that
9987              bit.  This will be converted into a ZERO_EXTRACT.  */
9988           if (const_op == 0 && sign_bit_comparison_p
9989               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9990               && mode_width <= HOST_BITS_PER_WIDE_INT)
9991             {
9992               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9993                                             ((HOST_WIDE_INT) 1
9994                                              << (mode_width - 1
9995                                                  - INTVAL (XEXP (op0, 1)))));
9996               code = (code == LT ? NE : EQ);
9997               continue;
9998             }
9999
10000           /* Fall through.  */
10001
10002         case ABS:
10003           /* ABS is ignorable inside an equality comparison with zero.  */
10004           if (const_op == 0 && equality_comparison_p)
10005             {
10006               op0 = XEXP (op0, 0);
10007               continue;
10008             }
10009           break;
10010
10011         case SIGN_EXTEND:
10012           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10013              (compare FOO CONST) if CONST fits in FOO's mode and we
10014              are either testing inequality or have an unsigned
10015              comparison with ZERO_EXTEND or a signed comparison with
10016              SIGN_EXTEND.  But don't do it if we don't have a compare
10017              insn of the given mode, since we'd have to revert it
10018              later on, and then we wouldn't know whether to sign- or
10019              zero-extend.  */
10020           mode = GET_MODE (XEXP (op0, 0));
10021           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10022               && ! unsigned_comparison_p
10023               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10024               && ((unsigned HOST_WIDE_INT) const_op
10025                   < (((unsigned HOST_WIDE_INT) 1
10026                       << (GET_MODE_BITSIZE (mode) - 1))))
10027               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10028             {
10029               op0 = XEXP (op0, 0);
10030               continue;
10031             }
10032           break;
10033
10034         case SUBREG:
10035           /* Check for the case where we are comparing A - C1 with C2, that is
10036
10037                (subreg:MODE (plus (A) (-C1))) op (C2)
10038
10039              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10040              comparison in the wider mode.  One of the following two conditions
10041              must be true in order for this to be valid:
10042
10043                1. The mode extension results in the same bit pattern being added
10044                   on both sides and the comparison is equality or unsigned.  As
10045                   C2 has been truncated to fit in MODE, the pattern can only be
10046                   all 0s or all 1s.
10047
10048                2. The mode extension results in the sign bit being copied on
10049                   each side.
10050
10051              The difficulty here is that we have predicates for A but not for
10052              (A - C1) so we need to check that C1 is within proper bounds so
10053              as to perturbate A as little as possible.  */
10054
10055           if (mode_width <= HOST_BITS_PER_WIDE_INT
10056               && subreg_lowpart_p (op0)
10057               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10058               && GET_CODE (SUBREG_REG (op0)) == PLUS
10059               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10060             {
10061               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10062               rtx a = XEXP (SUBREG_REG (op0), 0);
10063               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10064
10065               if ((c1 > 0
10066                    && (unsigned HOST_WIDE_INT) c1
10067                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10068                    && (equality_comparison_p || unsigned_comparison_p)
10069                    /* (A - C1) zero-extends if it is positive and sign-extends
10070                       if it is negative, C2 both zero- and sign-extends.  */
10071                    && ((0 == (nonzero_bits (a, inner_mode)
10072                               & ~GET_MODE_MASK (mode))
10073                         && const_op >= 0)
10074                        /* (A - C1) sign-extends if it is positive and 1-extends
10075                           if it is negative, C2 both sign- and 1-extends.  */
10076                        || (num_sign_bit_copies (a, inner_mode)
10077                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10078                                              - mode_width)
10079                            && const_op < 0)))
10080                   || ((unsigned HOST_WIDE_INT) c1
10081                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10082                       /* (A - C1) always sign-extends, like C2.  */
10083                       && num_sign_bit_copies (a, inner_mode)
10084                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10085                                            - (mode_width - 1))))
10086                 {
10087                   op0 = SUBREG_REG (op0);
10088                   continue;
10089                 }
10090             }
10091
10092           /* If the inner mode is narrower and we are extracting the low part,
10093              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10094           if (subreg_lowpart_p (op0)
10095               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10096             /* Fall through */ ;
10097           else
10098             break;
10099
10100           /* ... fall through ...  */
10101
10102         case ZERO_EXTEND:
10103           mode = GET_MODE (XEXP (op0, 0));
10104           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10105               && (unsigned_comparison_p || equality_comparison_p)
10106               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10107               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10108               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10109             {
10110               op0 = XEXP (op0, 0);
10111               continue;
10112             }
10113           break;
10114
10115         case PLUS:
10116           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10117              this for equality comparisons due to pathological cases involving
10118              overflows.  */
10119           if (equality_comparison_p
10120               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10121                                                         op1, XEXP (op0, 1))))
10122             {
10123               op0 = XEXP (op0, 0);
10124               op1 = tem;
10125               continue;
10126             }
10127
10128           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10129           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10130               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10131             {
10132               op0 = XEXP (XEXP (op0, 0), 0);
10133               code = (code == LT ? EQ : NE);
10134               continue;
10135             }
10136           break;
10137
10138         case MINUS:
10139           /* We used to optimize signed comparisons against zero, but that
10140              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10141              arrive here as equality comparisons, or (GEU, LTU) are
10142              optimized away.  No need to special-case them.  */
10143
10144           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10145              (eq B (minus A C)), whichever simplifies.  We can only do
10146              this for equality comparisons due to pathological cases involving
10147              overflows.  */
10148           if (equality_comparison_p
10149               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10150                                                         XEXP (op0, 1), op1)))
10151             {
10152               op0 = XEXP (op0, 0);
10153               op1 = tem;
10154               continue;
10155             }
10156
10157           if (equality_comparison_p
10158               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10159                                                         XEXP (op0, 0), op1)))
10160             {
10161               op0 = XEXP (op0, 1);
10162               op1 = tem;
10163               continue;
10164             }
10165
10166           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10167              of bits in X minus 1, is one iff X > 0.  */
10168           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10169               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10170               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10171                  == mode_width - 1
10172               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10173             {
10174               op0 = XEXP (op0, 1);
10175               code = (code == GE ? LE : GT);
10176               continue;
10177             }
10178           break;
10179
10180         case XOR:
10181           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10182              if C is zero or B is a constant.  */
10183           if (equality_comparison_p
10184               && 0 != (tem = simplify_binary_operation (XOR, mode,
10185                                                         XEXP (op0, 1), op1)))
10186             {
10187               op0 = XEXP (op0, 0);
10188               op1 = tem;
10189               continue;
10190             }
10191           break;
10192
10193         case EQ:  case NE:
10194         case UNEQ:  case LTGT:
10195         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10196         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10197         case UNORDERED: case ORDERED:
10198           /* We can't do anything if OP0 is a condition code value, rather
10199              than an actual data value.  */
10200           if (const_op != 0
10201               || CC0_P (XEXP (op0, 0))
10202               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10203             break;
10204
10205           /* Get the two operands being compared.  */
10206           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10207             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10208           else
10209             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10210
10211           /* Check for the cases where we simply want the result of the
10212              earlier test or the opposite of that result.  */
10213           if (code == NE || code == EQ
10214               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10215                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10216                   && (STORE_FLAG_VALUE
10217                       & (((HOST_WIDE_INT) 1
10218                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10219                   && (code == LT || code == GE)))
10220             {
10221               enum rtx_code new_code;
10222               if (code == LT || code == NE)
10223                 new_code = GET_CODE (op0);
10224               else
10225                 new_code = reversed_comparison_code (op0, NULL);
10226
10227               if (new_code != UNKNOWN)
10228                 {
10229                   code = new_code;
10230                   op0 = tem;
10231                   op1 = tem1;
10232                   continue;
10233                 }
10234             }
10235           break;
10236
10237         case IOR:
10238           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10239              iff X <= 0.  */
10240           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10241               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10242               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10243             {
10244               op0 = XEXP (op0, 1);
10245               code = (code == GE ? GT : LE);
10246               continue;
10247             }
10248           break;
10249
10250         case AND:
10251           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10252              will be converted to a ZERO_EXTRACT later.  */
10253           if (const_op == 0 && equality_comparison_p
10254               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10255               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10256             {
10257               op0 = simplify_and_const_int
10258                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10259                                                    XEXP (op0, 1),
10260                                                    XEXP (XEXP (op0, 0), 1)),
10261                  (HOST_WIDE_INT) 1);
10262               continue;
10263             }
10264
10265           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10266              zero and X is a comparison and C1 and C2 describe only bits set
10267              in STORE_FLAG_VALUE, we can compare with X.  */
10268           if (const_op == 0 && equality_comparison_p
10269               && mode_width <= HOST_BITS_PER_WIDE_INT
10270               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10271               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10272               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10273               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10274               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10275             {
10276               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10277                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10278               if ((~STORE_FLAG_VALUE & mask) == 0
10279                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10280                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10281                           && COMPARISON_P (tem))))
10282                 {
10283                   op0 = XEXP (XEXP (op0, 0), 0);
10284                   continue;
10285                 }
10286             }
10287
10288           /* If we are doing an equality comparison of an AND of a bit equal
10289              to the sign bit, replace this with a LT or GE comparison of
10290              the underlying value.  */
10291           if (equality_comparison_p
10292               && const_op == 0
10293               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10294               && mode_width <= HOST_BITS_PER_WIDE_INT
10295               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10296                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10297             {
10298               op0 = XEXP (op0, 0);
10299               code = (code == EQ ? GE : LT);
10300               continue;
10301             }
10302
10303           /* If this AND operation is really a ZERO_EXTEND from a narrower
10304              mode, the constant fits within that mode, and this is either an
10305              equality or unsigned comparison, try to do this comparison in
10306              the narrower mode.
10307
10308              Note that in:
10309
10310              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10311              -> (ne:DI (reg:SI 4) (const_int 0))
10312
10313              unless TRULY_NOOP_TRUNCATION allows it or the register is
10314              known to hold a value of the required mode the
10315              transformation is invalid.  */
10316           if ((equality_comparison_p || unsigned_comparison_p)
10317               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10318               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10319                                    & GET_MODE_MASK (mode))
10320                                   + 1)) >= 0
10321               && const_op >> i == 0
10322               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10323               && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10324                                          GET_MODE_BITSIZE (GET_MODE (op0)))
10325                   || (REG_P (XEXP (op0, 0))
10326                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10327             {
10328               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10329               continue;
10330             }
10331
10332           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10333              fits in both M1 and M2 and the SUBREG is either paradoxical
10334              or represents the low part, permute the SUBREG and the AND
10335              and try again.  */
10336           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10337             {
10338               unsigned HOST_WIDE_INT c1;
10339               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10340               /* Require an integral mode, to avoid creating something like
10341                  (AND:SF ...).  */
10342               if (SCALAR_INT_MODE_P (tmode)
10343                   /* It is unsafe to commute the AND into the SUBREG if the
10344                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10345                      not defined.  As originally written the upper bits
10346                      have a defined value due to the AND operation.
10347                      However, if we commute the AND inside the SUBREG then
10348                      they no longer have defined values and the meaning of
10349                      the code has been changed.  */
10350                   && (0
10351 #ifdef WORD_REGISTER_OPERATIONS
10352                       || (mode_width > GET_MODE_BITSIZE (tmode)
10353                           && mode_width <= BITS_PER_WORD)
10354 #endif
10355                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10356                           && subreg_lowpart_p (XEXP (op0, 0))))
10357                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10358                   && mode_width <= HOST_BITS_PER_WIDE_INT
10359                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10360                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10361                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10362                   && c1 != mask
10363                   && c1 != GET_MODE_MASK (tmode))
10364                 {
10365                   op0 = simplify_gen_binary (AND, tmode,
10366                                              SUBREG_REG (XEXP (op0, 0)),
10367                                              gen_int_mode (c1, tmode));
10368                   op0 = gen_lowpart (mode, op0);
10369                   continue;
10370                 }
10371             }
10372
10373           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10374           if (const_op == 0 && equality_comparison_p
10375               && XEXP (op0, 1) == const1_rtx
10376               && GET_CODE (XEXP (op0, 0)) == NOT)
10377             {
10378               op0 = simplify_and_const_int
10379                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10380               code = (code == NE ? EQ : NE);
10381               continue;
10382             }
10383
10384           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10385              (eq (and (lshiftrt X) 1) 0).
10386              Also handle the case where (not X) is expressed using xor.  */
10387           if (const_op == 0 && equality_comparison_p
10388               && XEXP (op0, 1) == const1_rtx
10389               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10390             {
10391               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10392               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10393
10394               if (GET_CODE (shift_op) == NOT
10395                   || (GET_CODE (shift_op) == XOR
10396                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10397                       && GET_CODE (shift_count) == CONST_INT
10398                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10399                       && (INTVAL (XEXP (shift_op, 1))
10400                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10401                 {
10402                   op0 = simplify_and_const_int
10403                     (NULL_RTX, mode,
10404                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10405                      (HOST_WIDE_INT) 1);
10406                   code = (code == NE ? EQ : NE);
10407                   continue;
10408                 }
10409             }
10410           break;
10411
10412         case ASHIFT:
10413           /* If we have (compare (ashift FOO N) (const_int C)) and
10414              the high order N bits of FOO (N+1 if an inequality comparison)
10415              are known to be zero, we can do this by comparing FOO with C
10416              shifted right N bits so long as the low-order N bits of C are
10417              zero.  */
10418           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10419               && INTVAL (XEXP (op0, 1)) >= 0
10420               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10421                   < HOST_BITS_PER_WIDE_INT)
10422               && ((const_op
10423                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10424               && mode_width <= HOST_BITS_PER_WIDE_INT
10425               && (nonzero_bits (XEXP (op0, 0), mode)
10426                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10427                                + ! equality_comparison_p))) == 0)
10428             {
10429               /* We must perform a logical shift, not an arithmetic one,
10430                  as we want the top N bits of C to be zero.  */
10431               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10432
10433               temp >>= INTVAL (XEXP (op0, 1));
10434               op1 = gen_int_mode (temp, mode);
10435               op0 = XEXP (op0, 0);
10436               continue;
10437             }
10438
10439           /* If we are doing a sign bit comparison, it means we are testing
10440              a particular bit.  Convert it to the appropriate AND.  */
10441           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10442               && mode_width <= HOST_BITS_PER_WIDE_INT)
10443             {
10444               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10445                                             ((HOST_WIDE_INT) 1
10446                                              << (mode_width - 1
10447                                                  - INTVAL (XEXP (op0, 1)))));
10448               code = (code == LT ? NE : EQ);
10449               continue;
10450             }
10451
10452           /* If this an equality comparison with zero and we are shifting
10453              the low bit to the sign bit, we can convert this to an AND of the
10454              low-order bit.  */
10455           if (const_op == 0 && equality_comparison_p
10456               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10457               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10458                  == mode_width - 1)
10459             {
10460               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10461                                             (HOST_WIDE_INT) 1);
10462               continue;
10463             }
10464           break;
10465
10466         case ASHIFTRT:
10467           /* If this is an equality comparison with zero, we can do this
10468              as a logical shift, which might be much simpler.  */
10469           if (equality_comparison_p && const_op == 0
10470               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10471             {
10472               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10473                                           XEXP (op0, 0),
10474                                           INTVAL (XEXP (op0, 1)));
10475               continue;
10476             }
10477
10478           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10479              do the comparison in a narrower mode.  */
10480           if (! unsigned_comparison_p
10481               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10482               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10483               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10484               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10485                                          MODE_INT, 1)) != BLKmode
10486               && (((unsigned HOST_WIDE_INT) const_op
10487                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10488                   <= GET_MODE_MASK (tmode)))
10489             {
10490               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10491               continue;
10492             }
10493
10494           /* Likewise if OP0 is a PLUS of a sign extension with a
10495              constant, which is usually represented with the PLUS
10496              between the shifts.  */
10497           if (! unsigned_comparison_p
10498               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10499               && GET_CODE (XEXP (op0, 0)) == PLUS
10500               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10501               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10502               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10503               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10504                                          MODE_INT, 1)) != BLKmode
10505               && (((unsigned HOST_WIDE_INT) const_op
10506                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10507                   <= GET_MODE_MASK (tmode)))
10508             {
10509               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10510               rtx add_const = XEXP (XEXP (op0, 0), 1);
10511               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10512                                                    add_const, XEXP (op0, 1));
10513
10514               op0 = simplify_gen_binary (PLUS, tmode,
10515                                          gen_lowpart (tmode, inner),
10516                                          new_const);
10517               continue;
10518             }
10519
10520           /* ... fall through ...  */
10521         case LSHIFTRT:
10522           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10523              the low order N bits of FOO are known to be zero, we can do this
10524              by comparing FOO with C shifted left N bits so long as no
10525              overflow occurs.  */
10526           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10527               && INTVAL (XEXP (op0, 1)) >= 0
10528               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10529               && mode_width <= HOST_BITS_PER_WIDE_INT
10530               && (nonzero_bits (XEXP (op0, 0), mode)
10531                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10532               && (((unsigned HOST_WIDE_INT) const_op
10533                    + (GET_CODE (op0) != LSHIFTRT
10534                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10535                          + 1)
10536                       : 0))
10537                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10538             {
10539               /* If the shift was logical, then we must make the condition
10540                  unsigned.  */
10541               if (GET_CODE (op0) == LSHIFTRT)
10542                 code = unsigned_condition (code);
10543
10544               const_op <<= INTVAL (XEXP (op0, 1));
10545               op1 = GEN_INT (const_op);
10546               op0 = XEXP (op0, 0);
10547               continue;
10548             }
10549
10550           /* If we are using this shift to extract just the sign bit, we
10551              can replace this with an LT or GE comparison.  */
10552           if (const_op == 0
10553               && (equality_comparison_p || sign_bit_comparison_p)
10554               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10555               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10556                  == mode_width - 1)
10557             {
10558               op0 = XEXP (op0, 0);
10559               code = (code == NE || code == GT ? LT : GE);
10560               continue;
10561             }
10562           break;
10563
10564         default:
10565           break;
10566         }
10567
10568       break;
10569     }
10570
10571   /* Now make any compound operations involved in this comparison.  Then,
10572      check for an outmost SUBREG on OP0 that is not doing anything or is
10573      paradoxical.  The latter transformation must only be performed when
10574      it is known that the "extra" bits will be the same in op0 and op1 or
10575      that they don't matter.  There are three cases to consider:
10576
10577      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10578      care bits and we can assume they have any convenient value.  So
10579      making the transformation is safe.
10580
10581      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10582      In this case the upper bits of op0 are undefined.  We should not make
10583      the simplification in that case as we do not know the contents of
10584      those bits.
10585
10586      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10587      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10588      also be sure that they are the same as the upper bits of op1.
10589
10590      We can never remove a SUBREG for a non-equality comparison because
10591      the sign bit is in a different place in the underlying object.  */
10592
10593   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10594   op1 = make_compound_operation (op1, SET);
10595
10596   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10597       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10598       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10599       && (code == NE || code == EQ))
10600     {
10601       if (GET_MODE_SIZE (GET_MODE (op0))
10602           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10603         {
10604           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10605              implemented.  */
10606           if (REG_P (SUBREG_REG (op0)))
10607             {
10608               op0 = SUBREG_REG (op0);
10609               op1 = gen_lowpart (GET_MODE (op0), op1);
10610             }
10611         }
10612       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10613                 <= HOST_BITS_PER_WIDE_INT)
10614                && (nonzero_bits (SUBREG_REG (op0),
10615                                  GET_MODE (SUBREG_REG (op0)))
10616                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10617         {
10618           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10619
10620           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10621                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10622             op0 = SUBREG_REG (op0), op1 = tem;
10623         }
10624     }
10625
10626   /* We now do the opposite procedure: Some machines don't have compare
10627      insns in all modes.  If OP0's mode is an integer mode smaller than a
10628      word and we can't do a compare in that mode, see if there is a larger
10629      mode for which we can do the compare.  There are a number of cases in
10630      which we can use the wider mode.  */
10631
10632   mode = GET_MODE (op0);
10633   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10634       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10635       && ! have_insn_for (COMPARE, mode))
10636     for (tmode = GET_MODE_WIDER_MODE (mode);
10637          (tmode != VOIDmode
10638           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10639          tmode = GET_MODE_WIDER_MODE (tmode))
10640       if (have_insn_for (COMPARE, tmode))
10641         {
10642           int zero_extended;
10643
10644           /* If the only nonzero bits in OP0 and OP1 are those in the
10645              narrower mode and this is an equality or unsigned comparison,
10646              we can use the wider mode.  Similarly for sign-extended
10647              values, in which case it is true for all comparisons.  */
10648           zero_extended = ((code == EQ || code == NE
10649                             || code == GEU || code == GTU
10650                             || code == LEU || code == LTU)
10651                            && (nonzero_bits (op0, tmode)
10652                                & ~GET_MODE_MASK (mode)) == 0
10653                            && ((GET_CODE (op1) == CONST_INT
10654                                 || (nonzero_bits (op1, tmode)
10655                                     & ~GET_MODE_MASK (mode)) == 0)));
10656
10657           if (zero_extended
10658               || ((num_sign_bit_copies (op0, tmode)
10659                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10660                                      - GET_MODE_BITSIZE (mode)))
10661                   && (num_sign_bit_copies (op1, tmode)
10662                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10663                                         - GET_MODE_BITSIZE (mode)))))
10664             {
10665               /* If OP0 is an AND and we don't have an AND in MODE either,
10666                  make a new AND in the proper mode.  */
10667               if (GET_CODE (op0) == AND
10668                   && !have_insn_for (AND, mode))
10669                 op0 = simplify_gen_binary (AND, tmode,
10670                                            gen_lowpart (tmode,
10671                                                         XEXP (op0, 0)),
10672                                            gen_lowpart (tmode,
10673                                                         XEXP (op0, 1)));
10674
10675               op0 = gen_lowpart (tmode, op0);
10676               if (zero_extended && GET_CODE (op1) == CONST_INT)
10677                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10678               op1 = gen_lowpart (tmode, op1);
10679               break;
10680             }
10681
10682           /* If this is a test for negative, we can make an explicit
10683              test of the sign bit.  */
10684
10685           if (op1 == const0_rtx && (code == LT || code == GE)
10686               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10687             {
10688               op0 = simplify_gen_binary (AND, tmode,
10689                                          gen_lowpart (tmode, op0),
10690                                          GEN_INT ((HOST_WIDE_INT) 1
10691                                                   << (GET_MODE_BITSIZE (mode)
10692                                                       - 1)));
10693               code = (code == LT) ? NE : EQ;
10694               break;
10695             }
10696         }
10697
10698 #ifdef CANONICALIZE_COMPARISON
10699   /* If this machine only supports a subset of valid comparisons, see if we
10700      can convert an unsupported one into a supported one.  */
10701   CANONICALIZE_COMPARISON (code, op0, op1);
10702 #endif
10703
10704   *pop0 = op0;
10705   *pop1 = op1;
10706
10707   return code;
10708 }
10709 \f
10710 /* Utility function for record_value_for_reg.  Count number of
10711    rtxs in X.  */
10712 static int
10713 count_rtxs (rtx x)
10714 {
10715   enum rtx_code code = GET_CODE (x);
10716   const char *fmt;
10717   int i, ret = 1;
10718
10719   if (GET_RTX_CLASS (code) == '2'
10720       || GET_RTX_CLASS (code) == 'c')
10721     {
10722       rtx x0 = XEXP (x, 0);
10723       rtx x1 = XEXP (x, 1);
10724
10725       if (x0 == x1)
10726         return 1 + 2 * count_rtxs (x0);
10727
10728       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10729            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10730           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10731         return 2 + 2 * count_rtxs (x0)
10732                + count_rtxs (x == XEXP (x1, 0)
10733                              ? XEXP (x1, 1) : XEXP (x1, 0));
10734
10735       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10736            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10737           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10738         return 2 + 2 * count_rtxs (x1)
10739                + count_rtxs (x == XEXP (x0, 0)
10740                              ? XEXP (x0, 1) : XEXP (x0, 0));
10741     }
10742
10743   fmt = GET_RTX_FORMAT (code);
10744   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10745     if (fmt[i] == 'e')
10746       ret += count_rtxs (XEXP (x, i));
10747
10748   return ret;
10749 }
10750 \f
10751 /* Utility function for following routine.  Called when X is part of a value
10752    being stored into last_set_value.  Sets last_set_table_tick
10753    for each register mentioned.  Similar to mention_regs in cse.c  */
10754
10755 static void
10756 update_table_tick (rtx x)
10757 {
10758   enum rtx_code code = GET_CODE (x);
10759   const char *fmt = GET_RTX_FORMAT (code);
10760   int i;
10761
10762   if (code == REG)
10763     {
10764       unsigned int regno = REGNO (x);
10765       unsigned int endregno
10766         = regno + (regno < FIRST_PSEUDO_REGISTER
10767                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10768       unsigned int r;
10769
10770       for (r = regno; r < endregno; r++)
10771         reg_stat[r].last_set_table_tick = label_tick;
10772
10773       return;
10774     }
10775
10776   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10777     /* Note that we can't have an "E" in values stored; see
10778        get_last_value_validate.  */
10779     if (fmt[i] == 'e')
10780       {
10781         /* Check for identical subexpressions.  If x contains
10782            identical subexpression we only have to traverse one of
10783            them.  */
10784         if (i == 0 && ARITHMETIC_P (x))
10785           {
10786             /* Note that at this point x1 has already been
10787                processed.  */
10788             rtx x0 = XEXP (x, 0);
10789             rtx x1 = XEXP (x, 1);
10790
10791             /* If x0 and x1 are identical then there is no need to
10792                process x0.  */
10793             if (x0 == x1)
10794               break;
10795
10796             /* If x0 is identical to a subexpression of x1 then while
10797                processing x1, x0 has already been processed.  Thus we
10798                are done with x.  */
10799             if (ARITHMETIC_P (x1)
10800                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10801               break;
10802
10803             /* If x1 is identical to a subexpression of x0 then we
10804                still have to process the rest of x0.  */
10805             if (ARITHMETIC_P (x0)
10806                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10807               {
10808                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10809                 break;
10810               }
10811           }
10812
10813         update_table_tick (XEXP (x, i));
10814       }
10815 }
10816
10817 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10818    are saying that the register is clobbered and we no longer know its
10819    value.  If INSN is zero, don't update reg_stat[].last_set; this is
10820    only permitted with VALUE also zero and is used to invalidate the
10821    register.  */
10822
10823 static void
10824 record_value_for_reg (rtx reg, rtx insn, rtx value)
10825 {
10826   unsigned int regno = REGNO (reg);
10827   unsigned int endregno
10828     = regno + (regno < FIRST_PSEUDO_REGISTER
10829                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10830   unsigned int i;
10831
10832   /* If VALUE contains REG and we have a previous value for REG, substitute
10833      the previous value.  */
10834   if (value && insn && reg_overlap_mentioned_p (reg, value))
10835     {
10836       rtx tem;
10837
10838       /* Set things up so get_last_value is allowed to see anything set up to
10839          our insn.  */
10840       subst_low_cuid = INSN_CUID (insn);
10841       tem = get_last_value (reg);
10842
10843       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10844          it isn't going to be useful and will take a lot of time to process,
10845          so just use the CLOBBER.  */
10846
10847       if (tem)
10848         {
10849           if (ARITHMETIC_P (tem)
10850               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10851               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10852             tem = XEXP (tem, 0);
10853           else if (count_occurrences (value, reg, 1) >= 2)
10854             {
10855               /* If there are two or more occurrences of REG in VALUE,
10856                  prevent the value from growing too much.  */
10857               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10858                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10859             }
10860
10861           value = replace_rtx (copy_rtx (value), reg, tem);
10862         }
10863     }
10864
10865   /* For each register modified, show we don't know its value, that
10866      we don't know about its bitwise content, that its value has been
10867      updated, and that we don't know the location of the death of the
10868      register.  */
10869   for (i = regno; i < endregno; i++)
10870     {
10871       if (insn)
10872         reg_stat[i].last_set = insn;
10873
10874       reg_stat[i].last_set_value = 0;
10875       reg_stat[i].last_set_mode = 0;
10876       reg_stat[i].last_set_nonzero_bits = 0;
10877       reg_stat[i].last_set_sign_bit_copies = 0;
10878       reg_stat[i].last_death = 0;
10879       reg_stat[i].truncated_to_mode = 0;
10880     }
10881
10882   /* Mark registers that are being referenced in this value.  */
10883   if (value)
10884     update_table_tick (value);
10885
10886   /* Now update the status of each register being set.
10887      If someone is using this register in this block, set this register
10888      to invalid since we will get confused between the two lives in this
10889      basic block.  This makes using this register always invalid.  In cse, we
10890      scan the table to invalidate all entries using this register, but this
10891      is too much work for us.  */
10892
10893   for (i = regno; i < endregno; i++)
10894     {
10895       reg_stat[i].last_set_label = label_tick;
10896       if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10897         reg_stat[i].last_set_invalid = 1;
10898       else
10899         reg_stat[i].last_set_invalid = 0;
10900     }
10901
10902   /* The value being assigned might refer to X (like in "x++;").  In that
10903      case, we must replace it with (clobber (const_int 0)) to prevent
10904      infinite loops.  */
10905   if (value && ! get_last_value_validate (&value, insn,
10906                                           reg_stat[regno].last_set_label, 0))
10907     {
10908       value = copy_rtx (value);
10909       if (! get_last_value_validate (&value, insn,
10910                                      reg_stat[regno].last_set_label, 1))
10911         value = 0;
10912     }
10913
10914   /* For the main register being modified, update the value, the mode, the
10915      nonzero bits, and the number of sign bit copies.  */
10916
10917   reg_stat[regno].last_set_value = value;
10918
10919   if (value)
10920     {
10921       enum machine_mode mode = GET_MODE (reg);
10922       subst_low_cuid = INSN_CUID (insn);
10923       reg_stat[regno].last_set_mode = mode;
10924       if (GET_MODE_CLASS (mode) == MODE_INT
10925           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10926         mode = nonzero_bits_mode;
10927       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10928       reg_stat[regno].last_set_sign_bit_copies
10929         = num_sign_bit_copies (value, GET_MODE (reg));
10930     }
10931 }
10932
10933 /* Called via note_stores from record_dead_and_set_regs to handle one
10934    SET or CLOBBER in an insn.  DATA is the instruction in which the
10935    set is occurring.  */
10936
10937 static void
10938 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10939 {
10940   rtx record_dead_insn = (rtx) data;
10941
10942   if (GET_CODE (dest) == SUBREG)
10943     dest = SUBREG_REG (dest);
10944
10945   if (!record_dead_insn)
10946     {
10947       if (REG_P (dest))
10948         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10949       return;
10950     }
10951
10952   if (REG_P (dest))
10953     {
10954       /* If we are setting the whole register, we know its value.  Otherwise
10955          show that we don't know the value.  We can handle SUBREG in
10956          some cases.  */
10957       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10958         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10959       else if (GET_CODE (setter) == SET
10960                && GET_CODE (SET_DEST (setter)) == SUBREG
10961                && SUBREG_REG (SET_DEST (setter)) == dest
10962                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10963                && subreg_lowpart_p (SET_DEST (setter)))
10964         record_value_for_reg (dest, record_dead_insn,
10965                               gen_lowpart (GET_MODE (dest),
10966                                                        SET_SRC (setter)));
10967       else
10968         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10969     }
10970   else if (MEM_P (dest)
10971            /* Ignore pushes, they clobber nothing.  */
10972            && ! push_operand (dest, GET_MODE (dest)))
10973     mem_last_set = INSN_CUID (record_dead_insn);
10974 }
10975
10976 /* Update the records of when each REG was most recently set or killed
10977    for the things done by INSN.  This is the last thing done in processing
10978    INSN in the combiner loop.
10979
10980    We update reg_stat[], in particular fields last_set, last_set_value,
10981    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10982    last_death, and also the similar information mem_last_set (which insn
10983    most recently modified memory) and last_call_cuid (which insn was the
10984    most recent subroutine call).  */
10985
10986 static void
10987 record_dead_and_set_regs (rtx insn)
10988 {
10989   rtx link;
10990   unsigned int i;
10991
10992   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10993     {
10994       if (REG_NOTE_KIND (link) == REG_DEAD
10995           && REG_P (XEXP (link, 0)))
10996         {
10997           unsigned int regno = REGNO (XEXP (link, 0));
10998           unsigned int endregno
10999             = regno + (regno < FIRST_PSEUDO_REGISTER
11000                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11001                        : 1);
11002
11003           for (i = regno; i < endregno; i++)
11004             reg_stat[i].last_death = insn;
11005         }
11006       else if (REG_NOTE_KIND (link) == REG_INC)
11007         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11008     }
11009
11010   if (CALL_P (insn))
11011     {
11012       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11013         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11014           {
11015             reg_stat[i].last_set_value = 0;
11016             reg_stat[i].last_set_mode = 0;
11017             reg_stat[i].last_set_nonzero_bits = 0;
11018             reg_stat[i].last_set_sign_bit_copies = 0;
11019             reg_stat[i].last_death = 0;
11020             reg_stat[i].truncated_to_mode = 0;
11021           }
11022
11023       last_call_cuid = mem_last_set = INSN_CUID (insn);
11024
11025       /* We can't combine into a call pattern.  Remember, though, that
11026          the return value register is set at this CUID.  We could
11027          still replace a register with the return value from the
11028          wrong subroutine call!  */
11029       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11030     }
11031   else
11032     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11033 }
11034
11035 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11036    register present in the SUBREG, so for each such SUBREG go back and
11037    adjust nonzero and sign bit information of the registers that are
11038    known to have some zero/sign bits set.
11039
11040    This is needed because when combine blows the SUBREGs away, the
11041    information on zero/sign bits is lost and further combines can be
11042    missed because of that.  */
11043
11044 static void
11045 record_promoted_value (rtx insn, rtx subreg)
11046 {
11047   rtx links, set;
11048   unsigned int regno = REGNO (SUBREG_REG (subreg));
11049   enum machine_mode mode = GET_MODE (subreg);
11050
11051   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11052     return;
11053
11054   for (links = LOG_LINKS (insn); links;)
11055     {
11056       insn = XEXP (links, 0);
11057       set = single_set (insn);
11058
11059       if (! set || !REG_P (SET_DEST (set))
11060           || REGNO (SET_DEST (set)) != regno
11061           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11062         {
11063           links = XEXP (links, 1);
11064           continue;
11065         }
11066
11067       if (reg_stat[regno].last_set == insn)
11068         {
11069           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11070             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11071         }
11072
11073       if (REG_P (SET_SRC (set)))
11074         {
11075           regno = REGNO (SET_SRC (set));
11076           links = LOG_LINKS (insn);
11077         }
11078       else
11079         break;
11080     }
11081 }
11082
11083 /* Check if X, a register, is known to contain a value already
11084    truncated to MODE.  In this case we can use a subreg to refer to
11085    the truncated value even though in the generic case we would need
11086    an explicit truncation.  */
11087
11088 static bool
11089 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11090 {
11091   enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11092
11093   if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11094     return false;
11095   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11096     return true;
11097   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11098                              GET_MODE_BITSIZE (truncated)))
11099     return true;
11100   return false;
11101 }
11102
11103 /* X is a REG or a SUBREG.  If X is some sort of a truncation record
11104    it.  For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11105    a truncate into a subreg using this information.  */
11106
11107 static void
11108 record_truncated_value (rtx x)
11109 {
11110   enum machine_mode truncated_mode;
11111
11112   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11113     {
11114       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11115       truncated_mode = GET_MODE (x);
11116
11117       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11118         return;
11119
11120       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11121                                  GET_MODE_BITSIZE (original_mode)))
11122         return;
11123
11124       x = SUBREG_REG (x);
11125     }
11126   /* ??? For hard-regs we now record everything.  We might be able to
11127      optimize this using last_set_mode.  */
11128   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11129     truncated_mode = GET_MODE (x);
11130   else
11131     return;
11132
11133   if (reg_stat[REGNO (x)].truncated_to_mode == 0
11134       || reg_stat[REGNO (x)].truncation_label < label_tick
11135       || (GET_MODE_SIZE (truncated_mode)
11136           < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11137     {
11138       reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11139       reg_stat[REGNO (x)].truncation_label = label_tick;
11140     }
11141 }
11142
11143 /* Scan X for promoted SUBREGs and truncated REGs.  For each one
11144    found, note what it implies to the registers used in it.  */
11145
11146 static void
11147 check_conversions (rtx insn, rtx x)
11148 {
11149   if (GET_CODE (x) == SUBREG || REG_P (x))
11150     {
11151       if (GET_CODE (x) == SUBREG
11152           && SUBREG_PROMOTED_VAR_P (x)
11153           && REG_P (SUBREG_REG (x)))
11154         record_promoted_value (insn, x);
11155
11156       record_truncated_value (x);
11157     }
11158   else
11159     {
11160       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11161       int i, j;
11162
11163       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11164         switch (format[i])
11165           {
11166           case 'e':
11167             check_conversions (insn, XEXP (x, i));
11168             break;
11169           case 'V':
11170           case 'E':
11171             if (XVEC (x, i) != 0)
11172               for (j = 0; j < XVECLEN (x, i); j++)
11173                 check_conversions (insn, XVECEXP (x, i, j));
11174             break;
11175           }
11176     }
11177 }
11178 \f
11179 /* Utility routine for the following function.  Verify that all the registers
11180    mentioned in *LOC are valid when *LOC was part of a value set when
11181    label_tick == TICK.  Return 0 if some are not.
11182
11183    If REPLACE is nonzero, replace the invalid reference with
11184    (clobber (const_int 0)) and return 1.  This replacement is useful because
11185    we often can get useful information about the form of a value (e.g., if
11186    it was produced by a shift that always produces -1 or 0) even though
11187    we don't know exactly what registers it was produced from.  */
11188
11189 static int
11190 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11191 {
11192   rtx x = *loc;
11193   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11194   int len = GET_RTX_LENGTH (GET_CODE (x));
11195   int i;
11196
11197   if (REG_P (x))
11198     {
11199       unsigned int regno = REGNO (x);
11200       unsigned int endregno
11201         = regno + (regno < FIRST_PSEUDO_REGISTER
11202                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11203       unsigned int j;
11204
11205       for (j = regno; j < endregno; j++)
11206         if (reg_stat[j].last_set_invalid
11207             /* If this is a pseudo-register that was only set once and not
11208                live at the beginning of the function, it is always valid.  */
11209             || (! (regno >= FIRST_PSEUDO_REGISTER
11210                    && REG_N_SETS (regno) == 1
11211                    && (! REGNO_REG_SET_P
11212                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11213                         regno)))
11214                 && reg_stat[j].last_set_label > tick))
11215           {
11216             if (replace)
11217               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11218             return replace;
11219           }
11220
11221       return 1;
11222     }
11223   /* If this is a memory reference, make sure that there were
11224      no stores after it that might have clobbered the value.  We don't
11225      have alias info, so we assume any store invalidates it.  */
11226   else if (MEM_P (x) && !MEM_READONLY_P (x)
11227            && INSN_CUID (insn) <= mem_last_set)
11228     {
11229       if (replace)
11230         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11231       return replace;
11232     }
11233
11234   for (i = 0; i < len; i++)
11235     {
11236       if (fmt[i] == 'e')
11237         {
11238           /* Check for identical subexpressions.  If x contains
11239              identical subexpression we only have to traverse one of
11240              them.  */
11241           if (i == 1 && ARITHMETIC_P (x))
11242             {
11243               /* Note that at this point x0 has already been checked
11244                  and found valid.  */
11245               rtx x0 = XEXP (x, 0);
11246               rtx x1 = XEXP (x, 1);
11247
11248               /* If x0 and x1 are identical then x is also valid.  */
11249               if (x0 == x1)
11250                 return 1;
11251
11252               /* If x1 is identical to a subexpression of x0 then
11253                  while checking x0, x1 has already been checked.  Thus
11254                  it is valid and so as x.  */
11255               if (ARITHMETIC_P (x0)
11256                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11257                 return 1;
11258
11259               /* If x0 is identical to a subexpression of x1 then x is
11260                  valid iff the rest of x1 is valid.  */
11261               if (ARITHMETIC_P (x1)
11262                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11263                 return
11264                   get_last_value_validate (&XEXP (x1,
11265                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11266                                            insn, tick, replace);
11267             }
11268
11269           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11270                                        replace) == 0)
11271             return 0;
11272         }
11273       /* Don't bother with these.  They shouldn't occur anyway.  */
11274       else if (fmt[i] == 'E')
11275         return 0;
11276     }
11277
11278   /* If we haven't found a reason for it to be invalid, it is valid.  */
11279   return 1;
11280 }
11281
11282 /* Get the last value assigned to X, if known.  Some registers
11283    in the value may be replaced with (clobber (const_int 0)) if their value
11284    is known longer known reliably.  */
11285
11286 static rtx
11287 get_last_value (rtx x)
11288 {
11289   unsigned int regno;
11290   rtx value;
11291
11292   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11293      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11294      we cannot predict what values the "extra" bits might have.  */
11295   if (GET_CODE (x) == SUBREG
11296       && subreg_lowpart_p (x)
11297       && (GET_MODE_SIZE (GET_MODE (x))
11298           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11299       && (value = get_last_value (SUBREG_REG (x))) != 0)
11300     return gen_lowpart (GET_MODE (x), value);
11301
11302   if (!REG_P (x))
11303     return 0;
11304
11305   regno = REGNO (x);
11306   value = reg_stat[regno].last_set_value;
11307
11308   /* If we don't have a value, or if it isn't for this basic block and
11309      it's either a hard register, set more than once, or it's a live
11310      at the beginning of the function, return 0.
11311
11312      Because if it's not live at the beginning of the function then the reg
11313      is always set before being used (is never used without being set).
11314      And, if it's set only once, and it's always set before use, then all
11315      uses must have the same last value, even if it's not from this basic
11316      block.  */
11317
11318   if (value == 0
11319       || (reg_stat[regno].last_set_label != label_tick
11320           && (regno < FIRST_PSEUDO_REGISTER
11321               || REG_N_SETS (regno) != 1
11322               || (REGNO_REG_SET_P
11323                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11324                    regno)))))
11325     return 0;
11326
11327   /* If the value was set in a later insn than the ones we are processing,
11328      we can't use it even if the register was only set once.  */
11329   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11330     return 0;
11331
11332   /* If the value has all its registers valid, return it.  */
11333   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11334                                reg_stat[regno].last_set_label, 0))
11335     return value;
11336
11337   /* Otherwise, make a copy and replace any invalid register with
11338      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11339
11340   value = copy_rtx (value);
11341   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11342                                reg_stat[regno].last_set_label, 1))
11343     return value;
11344
11345   return 0;
11346 }
11347 \f
11348 /* Return nonzero if expression X refers to a REG or to memory
11349    that is set in an instruction more recent than FROM_CUID.  */
11350
11351 static int
11352 use_crosses_set_p (rtx x, int from_cuid)
11353 {
11354   const char *fmt;
11355   int i;
11356   enum rtx_code code = GET_CODE (x);
11357
11358   if (code == REG)
11359     {
11360       unsigned int regno = REGNO (x);
11361       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11362                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11363
11364 #ifdef PUSH_ROUNDING
11365       /* Don't allow uses of the stack pointer to be moved,
11366          because we don't know whether the move crosses a push insn.  */
11367       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11368         return 1;
11369 #endif
11370       for (; regno < endreg; regno++)
11371         if (reg_stat[regno].last_set
11372             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11373           return 1;
11374       return 0;
11375     }
11376
11377   if (code == MEM && mem_last_set > from_cuid)
11378     return 1;
11379
11380   fmt = GET_RTX_FORMAT (code);
11381
11382   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11383     {
11384       if (fmt[i] == 'E')
11385         {
11386           int j;
11387           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11388             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11389               return 1;
11390         }
11391       else if (fmt[i] == 'e'
11392                && use_crosses_set_p (XEXP (x, i), from_cuid))
11393         return 1;
11394     }
11395   return 0;
11396 }
11397 \f
11398 /* Define three variables used for communication between the following
11399    routines.  */
11400
11401 static unsigned int reg_dead_regno, reg_dead_endregno;
11402 static int reg_dead_flag;
11403
11404 /* Function called via note_stores from reg_dead_at_p.
11405
11406    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11407    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11408
11409 static void
11410 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11411 {
11412   unsigned int regno, endregno;
11413
11414   if (!REG_P (dest))
11415     return;
11416
11417   regno = REGNO (dest);
11418   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11419                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11420
11421   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11422     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11423 }
11424
11425 /* Return nonzero if REG is known to be dead at INSN.
11426
11427    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11428    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11429    live.  Otherwise, see if it is live or dead at the start of the basic
11430    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11431    must be assumed to be always live.  */
11432
11433 static int
11434 reg_dead_at_p (rtx reg, rtx insn)
11435 {
11436   basic_block block;
11437   unsigned int i;
11438
11439   /* Set variables for reg_dead_at_p_1.  */
11440   reg_dead_regno = REGNO (reg);
11441   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11442                                         ? hard_regno_nregs[reg_dead_regno]
11443                                                           [GET_MODE (reg)]
11444                                         : 1);
11445
11446   reg_dead_flag = 0;
11447
11448   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11449      we allow the machine description to decide whether use-and-clobber
11450      patterns are OK.  */
11451   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11452     {
11453       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11454         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11455           return 0;
11456     }
11457
11458   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11459      beginning of function.  */
11460   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11461        insn = prev_nonnote_insn (insn))
11462     {
11463       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11464       if (reg_dead_flag)
11465         return reg_dead_flag == 1 ? 1 : 0;
11466
11467       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11468         return 1;
11469     }
11470
11471   /* Get the basic block that we were in.  */
11472   if (insn == 0)
11473     block = ENTRY_BLOCK_PTR->next_bb;
11474   else
11475     {
11476       FOR_EACH_BB (block)
11477         if (insn == BB_HEAD (block))
11478           break;
11479
11480       if (block == EXIT_BLOCK_PTR)
11481         return 0;
11482     }
11483
11484   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11485     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11486       return 0;
11487
11488   return 1;
11489 }
11490 \f
11491 /* Note hard registers in X that are used.  This code is similar to
11492    that in flow.c, but much simpler since we don't care about pseudos.  */
11493
11494 static void
11495 mark_used_regs_combine (rtx x)
11496 {
11497   RTX_CODE code = GET_CODE (x);
11498   unsigned int regno;
11499   int i;
11500
11501   switch (code)
11502     {
11503     case LABEL_REF:
11504     case SYMBOL_REF:
11505     case CONST_INT:
11506     case CONST:
11507     case CONST_DOUBLE:
11508     case CONST_VECTOR:
11509     case PC:
11510     case ADDR_VEC:
11511     case ADDR_DIFF_VEC:
11512     case ASM_INPUT:
11513 #ifdef HAVE_cc0
11514     /* CC0 must die in the insn after it is set, so we don't need to take
11515        special note of it here.  */
11516     case CC0:
11517 #endif
11518       return;
11519
11520     case CLOBBER:
11521       /* If we are clobbering a MEM, mark any hard registers inside the
11522          address as used.  */
11523       if (MEM_P (XEXP (x, 0)))
11524         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11525       return;
11526
11527     case REG:
11528       regno = REGNO (x);
11529       /* A hard reg in a wide mode may really be multiple registers.
11530          If so, mark all of them just like the first.  */
11531       if (regno < FIRST_PSEUDO_REGISTER)
11532         {
11533           unsigned int endregno, r;
11534
11535           /* None of this applies to the stack, frame or arg pointers.  */
11536           if (regno == STACK_POINTER_REGNUM
11537 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11538               || regno == HARD_FRAME_POINTER_REGNUM
11539 #endif
11540 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11541               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11542 #endif
11543               || regno == FRAME_POINTER_REGNUM)
11544             return;
11545
11546           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11547           for (r = regno; r < endregno; r++)
11548             SET_HARD_REG_BIT (newpat_used_regs, r);
11549         }
11550       return;
11551
11552     case SET:
11553       {
11554         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11555            the address.  */
11556         rtx testreg = SET_DEST (x);
11557
11558         while (GET_CODE (testreg) == SUBREG
11559                || GET_CODE (testreg) == ZERO_EXTRACT
11560                || GET_CODE (testreg) == STRICT_LOW_PART)
11561           testreg = XEXP (testreg, 0);
11562
11563         if (MEM_P (testreg))
11564           mark_used_regs_combine (XEXP (testreg, 0));
11565
11566         mark_used_regs_combine (SET_SRC (x));
11567       }
11568       return;
11569
11570     default:
11571       break;
11572     }
11573
11574   /* Recursively scan the operands of this expression.  */
11575
11576   {
11577     const char *fmt = GET_RTX_FORMAT (code);
11578
11579     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11580       {
11581         if (fmt[i] == 'e')
11582           mark_used_regs_combine (XEXP (x, i));
11583         else if (fmt[i] == 'E')
11584           {
11585             int j;
11586
11587             for (j = 0; j < XVECLEN (x, i); j++)
11588               mark_used_regs_combine (XVECEXP (x, i, j));
11589           }
11590       }
11591   }
11592 }
11593 \f
11594 /* Remove register number REGNO from the dead registers list of INSN.
11595
11596    Return the note used to record the death, if there was one.  */
11597
11598 rtx
11599 remove_death (unsigned int regno, rtx insn)
11600 {
11601   rtx note = find_regno_note (insn, REG_DEAD, regno);
11602
11603   if (note)
11604     {
11605       REG_N_DEATHS (regno)--;
11606       remove_note (insn, note);
11607     }
11608
11609   return note;
11610 }
11611
11612 /* For each register (hardware or pseudo) used within expression X, if its
11613    death is in an instruction with cuid between FROM_CUID (inclusive) and
11614    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11615    list headed by PNOTES.
11616
11617    That said, don't move registers killed by maybe_kill_insn.
11618
11619    This is done when X is being merged by combination into TO_INSN.  These
11620    notes will then be distributed as needed.  */
11621
11622 static void
11623 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11624              rtx *pnotes)
11625 {
11626   const char *fmt;
11627   int len, i;
11628   enum rtx_code code = GET_CODE (x);
11629
11630   if (code == REG)
11631     {
11632       unsigned int regno = REGNO (x);
11633       rtx where_dead = reg_stat[regno].last_death;
11634       rtx before_dead, after_dead;
11635
11636       /* Don't move the register if it gets killed in between from and to.  */
11637       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11638           && ! reg_referenced_p (x, maybe_kill_insn))
11639         return;
11640
11641       /* WHERE_DEAD could be a USE insn made by combine, so first we
11642          make sure that we have insns with valid INSN_CUID values.  */
11643       before_dead = where_dead;
11644       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11645         before_dead = PREV_INSN (before_dead);
11646
11647       after_dead = where_dead;
11648       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11649         after_dead = NEXT_INSN (after_dead);
11650
11651       if (before_dead && after_dead
11652           && INSN_CUID (before_dead) >= from_cuid
11653           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11654               || (where_dead != after_dead
11655                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11656         {
11657           rtx note = remove_death (regno, where_dead);
11658
11659           /* It is possible for the call above to return 0.  This can occur
11660              when last_death points to I2 or I1 that we combined with.
11661              In that case make a new note.
11662
11663              We must also check for the case where X is a hard register
11664              and NOTE is a death note for a range of hard registers
11665              including X.  In that case, we must put REG_DEAD notes for
11666              the remaining registers in place of NOTE.  */
11667
11668           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11669               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11670                   > GET_MODE_SIZE (GET_MODE (x))))
11671             {
11672               unsigned int deadregno = REGNO (XEXP (note, 0));
11673               unsigned int deadend
11674                 = (deadregno + hard_regno_nregs[deadregno]
11675                                                [GET_MODE (XEXP (note, 0))]);
11676               unsigned int ourend
11677                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11678               unsigned int i;
11679
11680               for (i = deadregno; i < deadend; i++)
11681                 if (i < regno || i >= ourend)
11682                   REG_NOTES (where_dead)
11683                     = gen_rtx_EXPR_LIST (REG_DEAD,
11684                                          regno_reg_rtx[i],
11685                                          REG_NOTES (where_dead));
11686             }
11687
11688           /* If we didn't find any note, or if we found a REG_DEAD note that
11689              covers only part of the given reg, and we have a multi-reg hard
11690              register, then to be safe we must check for REG_DEAD notes
11691              for each register other than the first.  They could have
11692              their own REG_DEAD notes lying around.  */
11693           else if ((note == 0
11694                     || (note != 0
11695                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11696                             < GET_MODE_SIZE (GET_MODE (x)))))
11697                    && regno < FIRST_PSEUDO_REGISTER
11698                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11699             {
11700               unsigned int ourend
11701                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11702               unsigned int i, offset;
11703               rtx oldnotes = 0;
11704
11705               if (note)
11706                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11707               else
11708                 offset = 1;
11709
11710               for (i = regno + offset; i < ourend; i++)
11711                 move_deaths (regno_reg_rtx[i],
11712                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11713             }
11714
11715           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11716             {
11717               XEXP (note, 1) = *pnotes;
11718               *pnotes = note;
11719             }
11720           else
11721             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11722
11723           REG_N_DEATHS (regno)++;
11724         }
11725
11726       return;
11727     }
11728
11729   else if (GET_CODE (x) == SET)
11730     {
11731       rtx dest = SET_DEST (x);
11732
11733       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11734
11735       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11736          that accesses one word of a multi-word item, some
11737          piece of everything register in the expression is used by
11738          this insn, so remove any old death.  */
11739       /* ??? So why do we test for equality of the sizes?  */
11740
11741       if (GET_CODE (dest) == ZERO_EXTRACT
11742           || GET_CODE (dest) == STRICT_LOW_PART
11743           || (GET_CODE (dest) == SUBREG
11744               && (((GET_MODE_SIZE (GET_MODE (dest))
11745                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11746                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11747                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11748         {
11749           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11750           return;
11751         }
11752
11753       /* If this is some other SUBREG, we know it replaces the entire
11754          value, so use that as the destination.  */
11755       if (GET_CODE (dest) == SUBREG)
11756         dest = SUBREG_REG (dest);
11757
11758       /* If this is a MEM, adjust deaths of anything used in the address.
11759          For a REG (the only other possibility), the entire value is
11760          being replaced so the old value is not used in this insn.  */
11761
11762       if (MEM_P (dest))
11763         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11764                      to_insn, pnotes);
11765       return;
11766     }
11767
11768   else if (GET_CODE (x) == CLOBBER)
11769     return;
11770
11771   len = GET_RTX_LENGTH (code);
11772   fmt = GET_RTX_FORMAT (code);
11773
11774   for (i = 0; i < len; i++)
11775     {
11776       if (fmt[i] == 'E')
11777         {
11778           int j;
11779           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11780             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11781                          to_insn, pnotes);
11782         }
11783       else if (fmt[i] == 'e')
11784         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11785     }
11786 }
11787 \f
11788 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11789    pattern of an insn.  X must be a REG.  */
11790
11791 static int
11792 reg_bitfield_target_p (rtx x, rtx body)
11793 {
11794   int i;
11795
11796   if (GET_CODE (body) == SET)
11797     {
11798       rtx dest = SET_DEST (body);
11799       rtx target;
11800       unsigned int regno, tregno, endregno, endtregno;
11801
11802       if (GET_CODE (dest) == ZERO_EXTRACT)
11803         target = XEXP (dest, 0);
11804       else if (GET_CODE (dest) == STRICT_LOW_PART)
11805         target = SUBREG_REG (XEXP (dest, 0));
11806       else
11807         return 0;
11808
11809       if (GET_CODE (target) == SUBREG)
11810         target = SUBREG_REG (target);
11811
11812       if (!REG_P (target))
11813         return 0;
11814
11815       tregno = REGNO (target), regno = REGNO (x);
11816       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11817         return target == x;
11818
11819       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11820       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11821
11822       return endregno > tregno && regno < endtregno;
11823     }
11824
11825   else if (GET_CODE (body) == PARALLEL)
11826     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11827       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11828         return 1;
11829
11830   return 0;
11831 }
11832 \f
11833 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11834    as appropriate.  I3 and I2 are the insns resulting from the combination
11835    insns including FROM (I2 may be zero).
11836
11837    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11838    not need REG_DEAD notes because they are being substituted for.  This
11839    saves searching in the most common cases.
11840
11841    Each note in the list is either ignored or placed on some insns, depending
11842    on the type of note.  */
11843
11844 static void
11845 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11846                   rtx elim_i1)
11847 {
11848   rtx note, next_note;
11849   rtx tem;
11850
11851   for (note = notes; note; note = next_note)
11852     {
11853       rtx place = 0, place2 = 0;
11854
11855       next_note = XEXP (note, 1);
11856       switch (REG_NOTE_KIND (note))
11857         {
11858         case REG_BR_PROB:
11859         case REG_BR_PRED:
11860           /* Doesn't matter much where we put this, as long as it's somewhere.
11861              It is preferable to keep these notes on branches, which is most
11862              likely to be i3.  */
11863           place = i3;
11864           break;
11865
11866         case REG_VALUE_PROFILE:
11867           /* Just get rid of this note, as it is unused later anyway.  */
11868           break;
11869
11870         case REG_NON_LOCAL_GOTO:
11871           if (JUMP_P (i3))
11872             place = i3;
11873           else
11874             {
11875               gcc_assert (i2 && JUMP_P (i2));
11876               place = i2;
11877             }
11878           break;
11879
11880         case REG_EH_REGION:
11881           /* These notes must remain with the call or trapping instruction.  */
11882           if (CALL_P (i3))
11883             place = i3;
11884           else if (i2 && CALL_P (i2))
11885             place = i2;
11886           else
11887             {
11888               gcc_assert (flag_non_call_exceptions);
11889               if (may_trap_p (i3))
11890                 place = i3;
11891               else if (i2 && may_trap_p (i2))
11892                 place = i2;
11893               /* ??? Otherwise assume we've combined things such that we
11894                  can now prove that the instructions can't trap.  Drop the
11895                  note in this case.  */
11896             }
11897           break;
11898
11899         case REG_NORETURN:
11900         case REG_SETJMP:
11901           /* These notes must remain with the call.  It should not be
11902              possible for both I2 and I3 to be a call.  */
11903           if (CALL_P (i3))
11904             place = i3;
11905           else
11906             {
11907               gcc_assert (i2 && CALL_P (i2));
11908               place = i2;
11909             }
11910           break;
11911
11912         case REG_UNUSED:
11913           /* Any clobbers for i3 may still exist, and so we must process
11914              REG_UNUSED notes from that insn.
11915
11916              Any clobbers from i2 or i1 can only exist if they were added by
11917              recog_for_combine.  In that case, recog_for_combine created the
11918              necessary REG_UNUSED notes.  Trying to keep any original
11919              REG_UNUSED notes from these insns can cause incorrect output
11920              if it is for the same register as the original i3 dest.
11921              In that case, we will notice that the register is set in i3,
11922              and then add a REG_UNUSED note for the destination of i3, which
11923              is wrong.  However, it is possible to have REG_UNUSED notes from
11924              i2 or i1 for register which were both used and clobbered, so
11925              we keep notes from i2 or i1 if they will turn into REG_DEAD
11926              notes.  */
11927
11928           /* If this register is set or clobbered in I3, put the note there
11929              unless there is one already.  */
11930           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11931             {
11932               if (from_insn != i3)
11933                 break;
11934
11935               if (! (REG_P (XEXP (note, 0))
11936                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11937                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11938                 place = i3;
11939             }
11940           /* Otherwise, if this register is used by I3, then this register
11941              now dies here, so we must put a REG_DEAD note here unless there
11942              is one already.  */
11943           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11944                    && ! (REG_P (XEXP (note, 0))
11945                          ? find_regno_note (i3, REG_DEAD,
11946                                             REGNO (XEXP (note, 0)))
11947                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11948             {
11949               PUT_REG_NOTE_KIND (note, REG_DEAD);
11950               place = i3;
11951             }
11952           break;
11953
11954         case REG_EQUAL:
11955         case REG_EQUIV:
11956         case REG_NOALIAS:
11957           /* These notes say something about results of an insn.  We can
11958              only support them if they used to be on I3 in which case they
11959              remain on I3.  Otherwise they are ignored.
11960
11961              If the note refers to an expression that is not a constant, we
11962              must also ignore the note since we cannot tell whether the
11963              equivalence is still true.  It might be possible to do
11964              slightly better than this (we only have a problem if I2DEST
11965              or I1DEST is present in the expression), but it doesn't
11966              seem worth the trouble.  */
11967
11968           if (from_insn == i3
11969               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11970             place = i3;
11971           break;
11972
11973         case REG_INC:
11974         case REG_NO_CONFLICT:
11975           /* These notes say something about how a register is used.  They must
11976              be present on any use of the register in I2 or I3.  */
11977           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11978             place = i3;
11979
11980           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11981             {
11982               if (place)
11983                 place2 = i2;
11984               else
11985                 place = i2;
11986             }
11987           break;
11988
11989         case REG_LABEL:
11990           /* This can show up in several ways -- either directly in the
11991              pattern, or hidden off in the constant pool with (or without?)
11992              a REG_EQUAL note.  */
11993           /* ??? Ignore the without-reg_equal-note problem for now.  */
11994           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11995               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11996                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11997                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11998             place = i3;
11999
12000           if (i2
12001               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12002                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12003                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12004                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12005             {
12006               if (place)
12007                 place2 = i2;
12008               else
12009                 place = i2;
12010             }
12011
12012           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
12013              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
12014           if (place && JUMP_P (place))
12015             {
12016               rtx label = JUMP_LABEL (place);
12017
12018               if (!label)
12019                 JUMP_LABEL (place) = XEXP (note, 0);
12020               else
12021                 {
12022                   gcc_assert (label == XEXP (note, 0));
12023                   if (LABEL_P (label))
12024                     LABEL_NUSES (label)--;
12025                 }
12026               place = 0;
12027             }
12028           if (place2 && JUMP_P (place2))
12029             {
12030               rtx label = JUMP_LABEL (place2);
12031
12032               if (!label)
12033                 JUMP_LABEL (place2) = XEXP (note, 0);
12034               else
12035                 {
12036                   gcc_assert (label == XEXP (note, 0));
12037                   if (LABEL_P (label))
12038                     LABEL_NUSES (label)--;
12039                 }
12040               place2 = 0;
12041             }
12042           break;
12043
12044         case REG_NONNEG:
12045           /* This note says something about the value of a register prior
12046              to the execution of an insn.  It is too much trouble to see
12047              if the note is still correct in all situations.  It is better
12048              to simply delete it.  */
12049           break;
12050
12051         case REG_RETVAL:
12052           /* If the insn previously containing this note still exists,
12053              put it back where it was.  Otherwise move it to the previous
12054              insn.  Adjust the corresponding REG_LIBCALL note.  */
12055           if (!NOTE_P (from_insn))
12056             place = from_insn;
12057           else
12058             {
12059               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12060               place = prev_real_insn (from_insn);
12061               if (tem && place)
12062                 XEXP (tem, 0) = place;
12063               /* If we're deleting the last remaining instruction of a
12064                  libcall sequence, don't add the notes.  */
12065               else if (XEXP (note, 0) == from_insn)
12066                 tem = place = 0;
12067               /* Don't add the dangling REG_RETVAL note.  */
12068               else if (! tem)
12069                 place = 0;
12070             }
12071           break;
12072
12073         case REG_LIBCALL:
12074           /* This is handled similarly to REG_RETVAL.  */
12075           if (!NOTE_P (from_insn))
12076             place = from_insn;
12077           else
12078             {
12079               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12080               place = next_real_insn (from_insn);
12081               if (tem && place)
12082                 XEXP (tem, 0) = place;
12083               /* If we're deleting the last remaining instruction of a
12084                  libcall sequence, don't add the notes.  */
12085               else if (XEXP (note, 0) == from_insn)
12086                 tem = place = 0;
12087               /* Don't add the dangling REG_LIBCALL note.  */
12088               else if (! tem)
12089                 place = 0;
12090             }
12091           break;
12092
12093         case REG_DEAD:
12094           /* If the register is used as an input in I3, it dies there.
12095              Similarly for I2, if it is nonzero and adjacent to I3.
12096
12097              If the register is not used as an input in either I3 or I2
12098              and it is not one of the registers we were supposed to eliminate,
12099              there are two possibilities.  We might have a non-adjacent I2
12100              or we might have somehow eliminated an additional register
12101              from a computation.  For example, we might have had A & B where
12102              we discover that B will always be zero.  In this case we will
12103              eliminate the reference to A.
12104
12105              In both cases, we must search to see if we can find a previous
12106              use of A and put the death note there.  */
12107
12108           if (from_insn
12109               && CALL_P (from_insn)
12110               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12111             place = from_insn;
12112           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12113             place = i3;
12114           else if (i2 != 0 && next_nonnote_insn (i2) == i3
12115                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12116             place = i2;
12117
12118           if (place == 0
12119               && (rtx_equal_p (XEXP (note, 0), elim_i2)
12120                   || rtx_equal_p (XEXP (note, 0), elim_i1)))
12121             break;
12122
12123           if (place == 0)
12124             {
12125               basic_block bb = this_basic_block;
12126
12127               /* You might think you could search back from FROM_INSN
12128                  rather than from I3, but combine tries to split invalid
12129                  combined instructions.  This can result in the old I2
12130                  or I1 moving later in the insn sequence.  */
12131               for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12132                 {
12133                   if (! INSN_P (tem))
12134                     {
12135                       if (tem == BB_HEAD (bb))
12136                         break;
12137                       continue;
12138                     }
12139
12140                   /* If the register is being set at TEM, see if that is all
12141                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12142                      into a REG_UNUSED note instead. Don't delete sets to
12143                      global register vars.  */
12144                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12145                        || !global_regs[REGNO (XEXP (note, 0))])
12146                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12147                     {
12148                       rtx set = single_set (tem);
12149                       rtx inner_dest = 0;
12150 #ifdef HAVE_cc0
12151                       rtx cc0_setter = NULL_RTX;
12152 #endif
12153
12154                       if (set != 0)
12155                         for (inner_dest = SET_DEST (set);
12156                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12157                               || GET_CODE (inner_dest) == SUBREG
12158                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12159                              inner_dest = XEXP (inner_dest, 0))
12160                           ;
12161
12162                       /* Verify that it was the set, and not a clobber that
12163                          modified the register.
12164
12165                          CC0 targets must be careful to maintain setter/user
12166                          pairs.  If we cannot delete the setter due to side
12167                          effects, mark the user with an UNUSED note instead
12168                          of deleting it.  */
12169
12170                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12171                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12172 #ifdef HAVE_cc0
12173                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12174                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12175                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12176 #endif
12177                           )
12178                         {
12179                           /* Move the notes and links of TEM elsewhere.
12180                              This might delete other dead insns recursively.
12181                              First set the pattern to something that won't use
12182                              any register.  */
12183                           rtx old_notes = REG_NOTES (tem);
12184
12185                           PATTERN (tem) = pc_rtx;
12186                           REG_NOTES (tem) = NULL;
12187
12188                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12189                                             NULL_RTX, NULL_RTX);
12190                           distribute_links (LOG_LINKS (tem));
12191
12192                           SET_INSN_DELETED (tem);
12193
12194 #ifdef HAVE_cc0
12195                           /* Delete the setter too.  */
12196                           if (cc0_setter)
12197                             {
12198                               PATTERN (cc0_setter) = pc_rtx;
12199                               old_notes = REG_NOTES (cc0_setter);
12200                               REG_NOTES (cc0_setter) = NULL;
12201
12202                               distribute_notes (old_notes, cc0_setter,
12203                                                 cc0_setter, NULL_RTX,
12204                                                 NULL_RTX, NULL_RTX);
12205                               distribute_links (LOG_LINKS (cc0_setter));
12206
12207                               SET_INSN_DELETED (cc0_setter);
12208                             }
12209 #endif
12210                         }
12211                       else
12212                         {
12213                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12214
12215                           /*  If there isn't already a REG_UNUSED note, put one
12216                               here.  Do not place a REG_DEAD note, even if
12217                               the register is also used here; that would not
12218                               match the algorithm used in lifetime analysis
12219                               and can cause the consistency check in the
12220                               scheduler to fail.  */
12221                           if (! find_regno_note (tem, REG_UNUSED,
12222                                                  REGNO (XEXP (note, 0))))
12223                             place = tem;
12224                           break;
12225                         }
12226                     }
12227                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12228                            || (CALL_P (tem)
12229                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12230                     {
12231                       /* This may not be the correct place for the death
12232                          note if FROM_INSN is before TEM, and the reg is
12233                          set between FROM_INSN and TEM.  The reg might
12234                          die two or more times.  An existing death note
12235                          means we are looking at the wrong live range.  */
12236                       if (from_insn
12237                           && INSN_CUID (from_insn) < INSN_CUID (tem)
12238                           && find_regno_note (tem, REG_DEAD,
12239                                               REGNO (XEXP (note, 0))))
12240                         {
12241                           tem = from_insn;
12242                           if (tem == BB_HEAD (bb))
12243                             break;
12244                           continue;
12245                         }
12246
12247                       place = tem;
12248
12249                       /* If we are doing a 3->2 combination, and we have a
12250                          register which formerly died in i3 and was not used
12251                          by i2, which now no longer dies in i3 and is used in
12252                          i2 but does not die in i2, and place is between i2
12253                          and i3, then we may need to move a link from place to
12254                          i2.  */
12255                       if (i2 && INSN_UID (place) <= max_uid_cuid
12256                           && INSN_CUID (place) > INSN_CUID (i2)
12257                           && from_insn
12258                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12259                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12260                         {
12261                           rtx links = LOG_LINKS (place);
12262                           LOG_LINKS (place) = 0;
12263                           distribute_links (links);
12264                         }
12265                       break;
12266                     }
12267
12268                   if (tem == BB_HEAD (bb))
12269                     break;
12270                 }
12271
12272               /* We haven't found an insn for the death note and it
12273                  is still a REG_DEAD note, but we have hit the beginning
12274                  of the block.  If the existing life info says the reg
12275                  was dead, there's nothing left to do.  Otherwise, we'll
12276                  need to do a global life update after combine.  */
12277               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12278                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12279                                       REGNO (XEXP (note, 0))))
12280                 SET_BIT (refresh_blocks, this_basic_block->index);
12281             }
12282
12283           /* If the register is set or already dead at PLACE, we needn't do
12284              anything with this note if it is still a REG_DEAD note.
12285              We check here if it is set at all, not if is it totally replaced,
12286              which is what `dead_or_set_p' checks, so also check for it being
12287              set partially.  */
12288
12289           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12290             {
12291               unsigned int regno = REGNO (XEXP (note, 0));
12292
12293               /* Similarly, if the instruction on which we want to place
12294                  the note is a noop, we'll need do a global live update
12295                  after we remove them in delete_noop_moves.  */
12296               if (noop_move_p (place))
12297                 SET_BIT (refresh_blocks, this_basic_block->index);
12298
12299               if (dead_or_set_p (place, XEXP (note, 0))
12300                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12301                 {
12302                   /* Unless the register previously died in PLACE, clear
12303                      last_death.  [I no longer understand why this is
12304                      being done.] */
12305                   if (reg_stat[regno].last_death != place)
12306                     reg_stat[regno].last_death = 0;
12307                   place = 0;
12308                 }
12309               else
12310                 reg_stat[regno].last_death = place;
12311
12312               /* If this is a death note for a hard reg that is occupying
12313                  multiple registers, ensure that we are still using all
12314                  parts of the object.  If we find a piece of the object
12315                  that is unused, we must arrange for an appropriate REG_DEAD
12316                  note to be added for it.  However, we can't just emit a USE
12317                  and tag the note to it, since the register might actually
12318                  be dead; so we recourse, and the recursive call then finds
12319                  the previous insn that used this register.  */
12320
12321               if (place && regno < FIRST_PSEUDO_REGISTER
12322                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12323                 {
12324                   unsigned int endregno
12325                     = regno + hard_regno_nregs[regno]
12326                                               [GET_MODE (XEXP (note, 0))];
12327                   int all_used = 1;
12328                   unsigned int i;
12329
12330                   for (i = regno; i < endregno; i++)
12331                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12332                          && ! find_regno_fusage (place, USE, i))
12333                         || dead_or_set_regno_p (place, i))
12334                       all_used = 0;
12335
12336                   if (! all_used)
12337                     {
12338                       /* Put only REG_DEAD notes for pieces that are
12339                          not already dead or set.  */
12340
12341                       for (i = regno; i < endregno;
12342                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12343                         {
12344                           rtx piece = regno_reg_rtx[i];
12345                           basic_block bb = this_basic_block;
12346
12347                           if (! dead_or_set_p (place, piece)
12348                               && ! reg_bitfield_target_p (piece,
12349                                                           PATTERN (place)))
12350                             {
12351                               rtx new_note
12352                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12353
12354                               distribute_notes (new_note, place, place,
12355                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12356                             }
12357                           else if (! refers_to_regno_p (i, i + 1,
12358                                                         PATTERN (place), 0)
12359                                    && ! find_regno_fusage (place, USE, i))
12360                             for (tem = PREV_INSN (place); ;
12361                                  tem = PREV_INSN (tem))
12362                               {
12363                                 if (! INSN_P (tem))
12364                                   {
12365                                     if (tem == BB_HEAD (bb))
12366                                       {
12367                                         SET_BIT (refresh_blocks,
12368                                                  this_basic_block->index);
12369                                         break;
12370                                       }
12371                                     continue;
12372                                   }
12373                                 if (dead_or_set_p (tem, piece)
12374                                     || reg_bitfield_target_p (piece,
12375                                                               PATTERN (tem)))
12376                                   {
12377                                     REG_NOTES (tem)
12378                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12379                                                            REG_NOTES (tem));
12380                                     break;
12381                                   }
12382                               }
12383
12384                         }
12385
12386                       place = 0;
12387                     }
12388                 }
12389             }
12390           break;
12391
12392         default:
12393           /* Any other notes should not be present at this point in the
12394              compilation.  */
12395           gcc_unreachable ();
12396         }
12397
12398       if (place)
12399         {
12400           XEXP (note, 1) = REG_NOTES (place);
12401           REG_NOTES (place) = note;
12402         }
12403       else if ((REG_NOTE_KIND (note) == REG_DEAD
12404                 || REG_NOTE_KIND (note) == REG_UNUSED)
12405                && REG_P (XEXP (note, 0)))
12406         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12407
12408       if (place2)
12409         {
12410           if ((REG_NOTE_KIND (note) == REG_DEAD
12411                || REG_NOTE_KIND (note) == REG_UNUSED)
12412               && REG_P (XEXP (note, 0)))
12413             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12414
12415           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12416                                                REG_NOTE_KIND (note),
12417                                                XEXP (note, 0),
12418                                                REG_NOTES (place2));
12419         }
12420     }
12421 }
12422 \f
12423 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12424    I3, I2, and I1 to new locations.  This is also called to add a link
12425    pointing at I3 when I3's destination is changed.  */
12426
12427 static void
12428 distribute_links (rtx links)
12429 {
12430   rtx link, next_link;
12431
12432   for (link = links; link; link = next_link)
12433     {
12434       rtx place = 0;
12435       rtx insn;
12436       rtx set, reg;
12437
12438       next_link = XEXP (link, 1);
12439
12440       /* If the insn that this link points to is a NOTE or isn't a single
12441          set, ignore it.  In the latter case, it isn't clear what we
12442          can do other than ignore the link, since we can't tell which
12443          register it was for.  Such links wouldn't be used by combine
12444          anyway.
12445
12446          It is not possible for the destination of the target of the link to
12447          have been changed by combine.  The only potential of this is if we
12448          replace I3, I2, and I1 by I3 and I2.  But in that case the
12449          destination of I2 also remains unchanged.  */
12450
12451       if (NOTE_P (XEXP (link, 0))
12452           || (set = single_set (XEXP (link, 0))) == 0)
12453         continue;
12454
12455       reg = SET_DEST (set);
12456       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12457              || GET_CODE (reg) == STRICT_LOW_PART)
12458         reg = XEXP (reg, 0);
12459
12460       /* A LOG_LINK is defined as being placed on the first insn that uses
12461          a register and points to the insn that sets the register.  Start
12462          searching at the next insn after the target of the link and stop
12463          when we reach a set of the register or the end of the basic block.
12464
12465          Note that this correctly handles the link that used to point from
12466          I3 to I2.  Also note that not much searching is typically done here
12467          since most links don't point very far away.  */
12468
12469       for (insn = NEXT_INSN (XEXP (link, 0));
12470            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12471                      || BB_HEAD (this_basic_block->next_bb) != insn));
12472            insn = NEXT_INSN (insn))
12473         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12474           {
12475             if (reg_referenced_p (reg, PATTERN (insn)))
12476               place = insn;
12477             break;
12478           }
12479         else if (CALL_P (insn)
12480                  && find_reg_fusage (insn, USE, reg))
12481           {
12482             place = insn;
12483             break;
12484           }
12485         else if (INSN_P (insn) && reg_set_p (reg, insn))
12486           break;
12487
12488       /* If we found a place to put the link, place it there unless there
12489          is already a link to the same insn as LINK at that point.  */
12490
12491       if (place)
12492         {
12493           rtx link2;
12494
12495           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12496             if (XEXP (link2, 0) == XEXP (link, 0))
12497               break;
12498
12499           if (link2 == 0)
12500             {
12501               XEXP (link, 1) = LOG_LINKS (place);
12502               LOG_LINKS (place) = link;
12503
12504               /* Set added_links_insn to the earliest insn we added a
12505                  link to.  */
12506               if (added_links_insn == 0
12507                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12508                 added_links_insn = place;
12509             }
12510         }
12511     }
12512 }
12513 \f
12514 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12515    Check whether the expression pointer to by LOC is a register or
12516    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12517    Otherwise return zero.  */
12518
12519 static int
12520 unmentioned_reg_p_1 (rtx *loc, void *expr)
12521 {
12522   rtx x = *loc;
12523
12524   if (x != NULL_RTX
12525       && (REG_P (x) || MEM_P (x))
12526       && ! reg_mentioned_p (x, (rtx) expr))
12527     return 1;
12528   return 0;
12529 }
12530
12531 /* Check for any register or memory mentioned in EQUIV that is not
12532    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12533    of EXPR where some registers may have been replaced by constants.  */
12534
12535 static bool
12536 unmentioned_reg_p (rtx equiv, rtx expr)
12537 {
12538   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12539 }
12540 \f
12541 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12542
12543 static int
12544 insn_cuid (rtx insn)
12545 {
12546   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12547          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12548     insn = NEXT_INSN (insn);
12549
12550   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12551
12552   return INSN_CUID (insn);
12553 }
12554 \f
12555 void
12556 dump_combine_stats (FILE *file)
12557 {
12558   fprintf
12559     (file,
12560      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12561      combine_attempts, combine_merges, combine_extras, combine_successes);
12562 }
12563
12564 void
12565 dump_combine_total_stats (FILE *file)
12566 {
12567   fprintf
12568     (file,
12569      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12570      total_attempts, total_merges, total_extras, total_successes);
12571 }
12572 \f
12573
12574 static bool
12575 gate_handle_combine (void)
12576 {
12577   return (optimize > 0);
12578 }
12579
12580 /* Try combining insns through substitution.  */
12581 static unsigned int
12582 rest_of_handle_combine (void)
12583 {
12584   int rebuild_jump_labels_after_combine
12585     = combine_instructions (get_insns (), max_reg_num ());
12586
12587   /* Combining insns may have turned an indirect jump into a
12588      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12589      instructions.  */
12590   if (rebuild_jump_labels_after_combine)
12591     {
12592       timevar_push (TV_JUMP);
12593       rebuild_jump_labels (get_insns ());
12594       timevar_pop (TV_JUMP);
12595
12596       delete_dead_jumptables ();
12597       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12598     }
12599   return 0;
12600 }
12601
12602 struct tree_opt_pass pass_combine =
12603 {
12604   "combine",                            /* name */
12605   gate_handle_combine,                  /* gate */
12606   rest_of_handle_combine,               /* execute */
12607   NULL,                                 /* sub */
12608   NULL,                                 /* next */
12609   0,                                    /* static_pass_number */
12610   TV_COMBINE,                           /* tv_id */
12611   0,                                    /* properties_required */
12612   0,                                    /* properties_provided */
12613   0,                                    /* properties_destroyed */
12614   0,                                    /* todo_flags_start */
12615   TODO_dump_func |
12616   TODO_ggc_collect,                     /* todo_flags_finish */
12617   'c'                                   /* letter */
12618 };
12619