1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
29 #include "coretypes.h"
31 #include "hard-reg-set.h"
36 #include "basic-block.h"
38 #include "addresses.h"
40 #include "insn-config.h"
51 static void init_reg_sets_1 (void);
52 static void init_reg_autoinc (void);
54 /* If we have auto-increment or auto-decrement and we can have secondary
55 reloads, we are not allowed to use classes requiring secondary
56 reloads for pseudos auto-incremented since reload can't handle it. */
57 /* We leave it to target hooks to decide if we have secondary reloads, so
58 assume that we might have them. */
59 #if defined(AUTO_INC_DEC) /* */
60 #define FORBIDDEN_INC_DEC_CLASSES
63 /* Register tables used by many passes. */
65 /* Indexed by hard register number, contains 1 for registers
66 that are fixed use (stack pointer, pc, frame pointer, etc.).
67 These are the registers that cannot be used to allocate
68 a pseudo reg for general use. */
70 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
72 /* Same info as a HARD_REG_SET. */
74 HARD_REG_SET fixed_reg_set
;
76 /* Data for initializing the above. */
78 static const char initial_fixed_regs
[] = FIXED_REGISTERS
;
80 /* Indexed by hard register number, contains 1 for registers
81 that are fixed use or are clobbered by function calls.
82 These are the registers that cannot be used to allocate
83 a pseudo reg whose life crosses calls unless we are able
84 to save/restore them across the calls. */
86 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
88 /* Same info as a HARD_REG_SET. */
90 HARD_REG_SET call_used_reg_set
;
92 /* HARD_REG_SET of registers we want to avoid caller saving. */
93 HARD_REG_SET losing_caller_save_reg_set
;
95 /* Data for initializing the above. */
97 static const char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
99 /* This is much like call_used_regs, except it doesn't have to
100 be a superset of FIXED_REGISTERS. This vector indicates
101 what is really call clobbered, and is used when defining
102 regs_invalidated_by_call. */
104 #ifdef CALL_REALLY_USED_REGISTERS
105 char call_really_used_regs
[] = CALL_REALLY_USED_REGISTERS
;
108 #ifdef CALL_REALLY_USED_REGISTERS
109 #define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X]
111 #define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X]
115 /* Indexed by hard register number, contains 1 for registers that are
116 fixed use or call used registers that cannot hold quantities across
117 calls even if we are willing to save and restore them. call fixed
118 registers are a subset of call used registers. */
120 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
122 /* The same info as a HARD_REG_SET. */
124 HARD_REG_SET call_fixed_reg_set
;
126 /* Indexed by hard register number, contains 1 for registers
127 that are being used for global register decls.
128 These must be exempt from ordinary flow analysis
129 and are also considered fixed. */
131 char global_regs
[FIRST_PSEUDO_REGISTER
];
133 /* Contains 1 for registers that are set or clobbered by calls. */
134 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
135 for someone's bright idea to have call_used_regs strictly include
136 fixed_regs. Which leaves us guessing as to the set of fixed_regs
137 that are actually preserved. We know for sure that those associated
138 with the local stack frame are safe, but scant others. */
140 HARD_REG_SET regs_invalidated_by_call
;
142 /* Table of register numbers in the order in which to try to use them. */
143 #ifdef REG_ALLOC_ORDER
144 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
146 /* The inverse of reg_alloc_order. */
147 int inv_reg_alloc_order
[FIRST_PSEUDO_REGISTER
];
150 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
152 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
154 /* The same information, but as an array of unsigned ints. We copy from
155 these unsigned ints to the table above. We do this so the tm.h files
156 do not have to be aware of the wordsize for machines with <= 64 regs.
157 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
160 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
162 static const unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
163 = REG_CLASS_CONTENTS
;
165 /* For each reg class, number of regs it contains. */
167 unsigned int reg_class_size
[N_REG_CLASSES
];
169 /* For each reg class, table listing all the containing classes. */
171 static enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
173 /* For each reg class, table listing all the classes contained in it. */
175 static enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
177 /* For each pair of reg classes,
178 a largest reg class contained in their union. */
180 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
182 /* For each pair of reg classes,
183 the smallest reg class containing their union. */
185 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
187 /* Array containing all of the register names. */
189 const char * reg_names
[] = REGISTER_NAMES
;
191 /* Array containing all of the register class names. */
193 const char * reg_class_names
[] = REG_CLASS_NAMES
;
195 /* For each hard register, the widest mode object that it can contain.
196 This will be a MODE_INT mode if the register can hold integers. Otherwise
197 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
200 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
202 /* 1 if there is a register of given mode. */
204 bool have_regs_of_mode
[MAX_MACHINE_MODE
];
206 /* 1 if class does contain register of given mode. */
208 static char contains_reg_of_mode
[N_REG_CLASSES
] [MAX_MACHINE_MODE
];
210 /* Maximum cost of moving from a register in one class to a register in
211 another class. Based on REGISTER_MOVE_COST. */
213 static int move_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
215 /* Similar, but here we don't have to move if the first index is a subset
216 of the second so in that case the cost is zero. */
218 static int may_move_in_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
220 /* Similar, but here we don't have to move if the first index is a superset
221 of the second so in that case the cost is zero. */
223 static int may_move_out_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
225 #ifdef FORBIDDEN_INC_DEC_CLASSES
227 /* These are the classes that regs which are auto-incremented or decremented
230 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
232 /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec
235 static char *in_inc_dec
;
237 #endif /* FORBIDDEN_INC_DEC_CLASSES */
239 /* Sample MEM values for use by memory_move_secondary_cost. */
241 static GTY(()) rtx top_of_stack
[MAX_MACHINE_MODE
];
243 /* Linked list of reg_info structures allocated for reg_n_info array.
244 Grouping all of the allocated structures together in one lump
245 means only one call to bzero to clear them, rather than n smaller
247 struct reg_info_data
{
248 struct reg_info_data
*next
; /* next set of reg_info structures */
249 size_t min_index
; /* minimum index # */
250 size_t max_index
; /* maximum index # */
251 char used_p
; /* nonzero if this has been used previously */
252 reg_info data
[1]; /* beginning of the reg_info data */
255 static struct reg_info_data
*reg_info_head
;
257 /* No more global register variables may be declared; true once
258 regclass has been initialized. */
260 static int no_global_reg_vars
= 0;
262 /* Specify number of hard registers given machine mode occupy. */
263 unsigned char hard_regno_nregs
[FIRST_PSEUDO_REGISTER
][MAX_MACHINE_MODE
];
265 /* Function called only once to initialize the above data on reg usage.
266 Once this is done, various switches may override. */
273 /* First copy the register information from the initial int form into
276 for (i
= 0; i
< N_REG_CLASSES
; i
++)
278 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
280 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
281 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
282 if (int_reg_class_contents
[i
][j
/ 32]
283 & ((unsigned) 1 << (j
% 32)))
284 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
287 /* Sanity check: make sure the target macros FIXED_REGISTERS and
288 CALL_USED_REGISTERS had the right number of initializers. */
289 gcc_assert (sizeof fixed_regs
== sizeof initial_fixed_regs
);
290 gcc_assert (sizeof call_used_regs
== sizeof initial_call_used_regs
);
292 memcpy (fixed_regs
, initial_fixed_regs
, sizeof fixed_regs
);
293 memcpy (call_used_regs
, initial_call_used_regs
, sizeof call_used_regs
);
294 memset (global_regs
, 0, sizeof global_regs
);
296 #ifdef REG_ALLOC_ORDER
297 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
298 inv_reg_alloc_order
[reg_alloc_order
[i
]] = i
;
302 /* After switches have been processed, which perhaps alter
303 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
306 init_reg_sets_1 (void)
309 unsigned int /* enum machine_mode */ m
;
311 /* This macro allows the fixed or call-used registers
312 and the register classes to depend on target flags. */
314 #ifdef CONDITIONAL_REGISTER_USAGE
315 CONDITIONAL_REGISTER_USAGE
;
318 /* Compute number of hard regs in each class. */
320 memset (reg_class_size
, 0, sizeof reg_class_size
);
321 for (i
= 0; i
< N_REG_CLASSES
; i
++)
322 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
323 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
326 /* Initialize the table of subunions.
327 reg_class_subunion[I][J] gets the largest-numbered reg-class
328 that is contained in the union of classes I and J. */
330 for (i
= 0; i
< N_REG_CLASSES
; i
++)
332 for (j
= 0; j
< N_REG_CLASSES
; j
++)
337 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
338 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
339 for (k
= 0; k
< N_REG_CLASSES
; k
++)
341 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
346 /* Keep the largest subclass. */ /* SPEE 900308 */
347 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
348 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
350 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
357 /* Initialize the table of superunions.
358 reg_class_superunion[I][J] gets the smallest-numbered reg-class
359 containing the union of classes I and J. */
361 for (i
= 0; i
< N_REG_CLASSES
; i
++)
363 for (j
= 0; j
< N_REG_CLASSES
; j
++)
368 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
369 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
370 for (k
= 0; k
< N_REG_CLASSES
; k
++)
371 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
374 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
378 /* Initialize the tables of subclasses and superclasses of each reg class.
379 First clear the whole table, then add the elements as they are found. */
381 for (i
= 0; i
< N_REG_CLASSES
; i
++)
383 for (j
= 0; j
< N_REG_CLASSES
; j
++)
385 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
386 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
390 for (i
= 0; i
< N_REG_CLASSES
; i
++)
392 if (i
== (int) NO_REGS
)
395 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
399 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
403 /* Reg class I is a subclass of J.
404 Add J to the table of superclasses of I. */
405 p
= ®_class_superclasses
[i
][0];
406 while (*p
!= LIM_REG_CLASSES
) p
++;
407 *p
= (enum reg_class
) j
;
408 /* Add I to the table of superclasses of J. */
409 p
= ®_class_subclasses
[j
][0];
410 while (*p
!= LIM_REG_CLASSES
) p
++;
411 *p
= (enum reg_class
) i
;
415 /* Initialize "constant" tables. */
417 CLEAR_HARD_REG_SET (fixed_reg_set
);
418 CLEAR_HARD_REG_SET (call_used_reg_set
);
419 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
420 CLEAR_HARD_REG_SET (regs_invalidated_by_call
);
422 memcpy (call_fixed_regs
, fixed_regs
, sizeof call_fixed_regs
);
424 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
426 /* call_used_regs must include fixed_regs. */
427 gcc_assert (!fixed_regs
[i
] || call_used_regs
[i
]);
428 #ifdef CALL_REALLY_USED_REGISTERS
429 /* call_used_regs must include call_really_used_regs. */
430 gcc_assert (!call_really_used_regs
[i
] || call_used_regs
[i
]);
434 SET_HARD_REG_BIT (fixed_reg_set
, i
);
436 if (call_used_regs
[i
])
437 SET_HARD_REG_BIT (call_used_reg_set
, i
);
438 if (call_fixed_regs
[i
])
439 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
440 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
441 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
443 /* There are a couple of fixed registers that we know are safe to
444 exclude from being clobbered by calls:
446 The frame pointer is always preserved across calls. The arg pointer
447 is if it is fixed. The stack pointer usually is, unless
448 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
449 If we are generating PIC code, the PIC offset table register is
450 preserved across calls, though the target can override that. */
452 if (i
== STACK_POINTER_REGNUM
)
454 else if (global_regs
[i
])
455 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
456 else if (i
== FRAME_POINTER_REGNUM
)
458 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
459 else if (i
== HARD_FRAME_POINTER_REGNUM
)
462 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
463 else if (i
== ARG_POINTER_REGNUM
&& fixed_regs
[i
])
466 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
467 else if (i
== (unsigned) PIC_OFFSET_TABLE_REGNUM
&& fixed_regs
[i
])
470 else if (CALL_REALLY_USED_REGNO_P (i
))
471 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
474 memset (have_regs_of_mode
, 0, sizeof (have_regs_of_mode
));
475 memset (contains_reg_of_mode
, 0, sizeof (contains_reg_of_mode
));
476 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
477 for (i
= 0; i
< N_REG_CLASSES
; i
++)
478 if ((unsigned) CLASS_MAX_NREGS (i
, m
) <= reg_class_size
[i
])
479 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
480 if (!fixed_regs
[j
] && TEST_HARD_REG_BIT (reg_class_contents
[i
], j
)
481 && HARD_REGNO_MODE_OK (j
, m
))
483 contains_reg_of_mode
[i
][m
] = 1;
484 have_regs_of_mode
[m
] = 1;
488 /* Initialize the move cost table. Find every subset of each class
489 and take the maximum cost of moving any subset to any other. */
491 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
492 if (have_regs_of_mode
[m
])
494 for (i
= 0; i
< N_REG_CLASSES
; i
++)
495 if (contains_reg_of_mode
[i
][m
])
496 for (j
= 0; j
< N_REG_CLASSES
; j
++)
499 enum reg_class
*p1
, *p2
;
501 if (!contains_reg_of_mode
[j
][m
])
503 move_cost
[m
][i
][j
] = 65536;
504 may_move_in_cost
[m
][i
][j
] = 65536;
505 may_move_out_cost
[m
][i
][j
] = 65536;
509 cost
= REGISTER_MOVE_COST (m
, i
, j
);
511 for (p2
= ®_class_subclasses
[j
][0];
512 *p2
!= LIM_REG_CLASSES
;
514 if (*p2
!= i
&& contains_reg_of_mode
[*p2
][m
])
515 cost
= MAX (cost
, move_cost
[m
][i
][*p2
]);
517 for (p1
= ®_class_subclasses
[i
][0];
518 *p1
!= LIM_REG_CLASSES
;
520 if (*p1
!= j
&& contains_reg_of_mode
[*p1
][m
])
521 cost
= MAX (cost
, move_cost
[m
][*p1
][j
]);
523 move_cost
[m
][i
][j
] = cost
;
525 if (reg_class_subset_p (i
, j
))
526 may_move_in_cost
[m
][i
][j
] = 0;
528 may_move_in_cost
[m
][i
][j
] = cost
;
530 if (reg_class_subset_p (j
, i
))
531 may_move_out_cost
[m
][i
][j
] = 0;
533 may_move_out_cost
[m
][i
][j
] = cost
;
537 for (j
= 0; j
< N_REG_CLASSES
; j
++)
539 move_cost
[m
][i
][j
] = 65536;
540 may_move_in_cost
[m
][i
][j
] = 65536;
541 may_move_out_cost
[m
][i
][j
] = 65536;
546 /* Compute the table of register modes.
547 These values are used to record death information for individual registers
548 (as opposed to a multi-register mode). */
551 init_reg_modes_once (void)
555 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
556 for (j
= 0; j
< MAX_MACHINE_MODE
; j
++)
557 hard_regno_nregs
[i
][j
] = HARD_REGNO_NREGS(i
, (enum machine_mode
)j
);
559 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
561 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1, false);
563 /* If we couldn't find a valid mode, just use the previous mode.
564 ??? One situation in which we need to do this is on the mips where
565 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
566 to use DF mode for the even registers and VOIDmode for the odd
567 (for the cpu models where the odd ones are inaccessible). */
568 if (reg_raw_mode
[i
] == VOIDmode
)
569 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
573 /* Finish initializing the register sets and
574 initialize the register modes. */
579 /* This finishes what was started by init_reg_sets, but couldn't be done
580 until after register usage was specified. */
586 /* Initialize some fake stack-frame MEM references for use in
587 memory_move_secondary_cost. */
590 init_fake_stack_mems (void)
595 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
596 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
601 /* Compute extra cost of moving registers to/from memory due to reloads.
602 Only needed if secondary reloads are required for memory moves. */
605 memory_move_secondary_cost (enum machine_mode mode
, enum reg_class
class, int in
)
607 enum reg_class altclass
;
608 int partial_cost
= 0;
609 /* We need a memory reference to feed to SECONDARY... macros. */
610 /* mem may be unused even if the SECONDARY_ macros are defined. */
611 rtx mem ATTRIBUTE_UNUSED
= top_of_stack
[(int) mode
];
614 altclass
= secondary_reload_class (in
? 1 : 0, class, mode
, mem
);
616 if (altclass
== NO_REGS
)
620 partial_cost
= REGISTER_MOVE_COST (mode
, altclass
, class);
622 partial_cost
= REGISTER_MOVE_COST (mode
, class, altclass
);
624 if (class == altclass
)
625 /* This isn't simply a copy-to-temporary situation. Can't guess
626 what it is, so MEMORY_MOVE_COST really ought not to be calling
629 I'm tempted to put in an assert here, but returning this will
630 probably only give poor estimates, which is what we would've
631 had before this code anyways. */
634 /* Check if the secondary reload register will also need a
636 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
639 /* Return a machine mode that is legitimate for hard reg REGNO and large
640 enough to save nregs. If we can't find one, return VOIDmode.
641 If CALL_SAVED is true, only consider modes that are call saved. */
644 choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED
,
645 unsigned int nregs
, bool call_saved
)
647 unsigned int /* enum machine_mode */ m
;
648 enum machine_mode found_mode
= VOIDmode
, mode
;
650 /* We first look for the largest integer mode that can be validly
651 held in REGNO. If none, we look for the largest floating-point mode.
652 If we still didn't find a valid mode, try CCmode. */
654 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
656 mode
= GET_MODE_WIDER_MODE (mode
))
657 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
658 && HARD_REGNO_MODE_OK (regno
, mode
)
659 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
662 if (found_mode
!= VOIDmode
)
665 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
667 mode
= GET_MODE_WIDER_MODE (mode
))
668 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
669 && HARD_REGNO_MODE_OK (regno
, mode
)
670 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
673 if (found_mode
!= VOIDmode
)
676 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT
);
678 mode
= GET_MODE_WIDER_MODE (mode
))
679 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
680 && HARD_REGNO_MODE_OK (regno
, mode
)
681 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
684 if (found_mode
!= VOIDmode
)
687 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT
);
689 mode
= GET_MODE_WIDER_MODE (mode
))
690 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
691 && HARD_REGNO_MODE_OK (regno
, mode
)
692 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
695 if (found_mode
!= VOIDmode
)
698 /* Iterate over all of the CCmodes. */
699 for (m
= (unsigned int) CCmode
; m
< (unsigned int) NUM_MACHINE_MODES
; ++m
)
701 mode
= (enum machine_mode
) m
;
702 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
703 && HARD_REGNO_MODE_OK (regno
, mode
)
704 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
708 /* We can't find a mode valid for this register. */
712 /* Specify the usage characteristics of the register named NAME.
713 It should be a fixed register if FIXED and a
714 call-used register if CALL_USED. */
717 fix_register (const char *name
, int fixed
, int call_used
)
721 /* Decode the name and update the primary form of
722 the register info. */
724 if ((i
= decode_reg_name (name
)) >= 0)
726 if ((i
== STACK_POINTER_REGNUM
727 #ifdef HARD_FRAME_POINTER_REGNUM
728 || i
== HARD_FRAME_POINTER_REGNUM
730 || i
== FRAME_POINTER_REGNUM
733 && (fixed
== 0 || call_used
== 0))
735 static const char * const what_option
[2][2] = {
736 { "call-saved", "call-used" },
737 { "no-such-option", "fixed" }};
739 error ("can't use '%s' as a %s register", name
,
740 what_option
[fixed
][call_used
]);
744 fixed_regs
[i
] = fixed
;
745 call_used_regs
[i
] = call_used
;
746 #ifdef CALL_REALLY_USED_REGISTERS
748 call_really_used_regs
[i
] = call_used
;
754 warning (0, "unknown register name: %s", name
);
758 /* Mark register number I as global. */
761 globalize_reg (int i
)
763 if (fixed_regs
[i
] == 0 && no_global_reg_vars
)
764 error ("global register variable follows a function definition");
768 warning (0, "register used for two global register variables");
772 if (call_used_regs
[i
] && ! fixed_regs
[i
])
773 warning (0, "call-clobbered register used for global register variable");
777 /* If we're globalizing the frame pointer, we need to set the
778 appropriate regs_invalidated_by_call bit, even if it's already
779 set in fixed_regs. */
780 if (i
!= STACK_POINTER_REGNUM
)
781 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
783 /* If already fixed, nothing else to do. */
787 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
788 #ifdef CALL_REALLY_USED_REGISTERS
789 call_really_used_regs
[i
] = 1;
792 SET_HARD_REG_BIT (fixed_reg_set
, i
);
793 SET_HARD_REG_BIT (call_used_reg_set
, i
);
794 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
797 /* Now the data and code for the `regclass' pass, which happens
798 just before local-alloc. */
800 /* The `costs' struct records the cost of using a hard register of each class
801 and of using memory for each pseudo. We use this data to set up
802 register class preferences. */
806 int cost
[N_REG_CLASSES
];
810 /* Structure used to record preferences of given pseudo. */
813 /* (enum reg_class) prefclass is the preferred class. May be
814 NO_REGS if no class is better than memory. */
817 /* altclass is a register class that we should use for allocating
818 pseudo if no register in the preferred class is available.
819 If no register in this class is available, memory is preferred.
821 It might appear to be more general to have a bitmask of classes here,
822 but since it is recommended that there be a class corresponding to the
823 union of most major pair of classes, that generality is not required. */
827 /* Record the cost of each class for each pseudo. */
829 static struct costs
*costs
;
831 /* Initialized once, and used to initialize cost values for each insn. */
833 static struct costs init_cost
;
835 /* Record preferences of each pseudo.
836 This is available after `regclass' is run. */
838 static struct reg_pref
*reg_pref
;
840 /* Allocated buffers for reg_pref. */
842 static struct reg_pref
*reg_pref_buffer
;
844 /* Frequency of executions of current insn. */
846 static int frequency
;
848 static rtx
scan_one_insn (rtx
, int);
849 static void record_operand_costs (rtx
, struct costs
*, struct reg_pref
*);
850 static void dump_regclass (FILE *);
851 static void record_reg_classes (int, int, rtx
*, enum machine_mode
*,
852 const char **, rtx
, struct costs
*,
854 static int copy_cost (rtx
, enum machine_mode
, enum reg_class
, int,
855 secondary_reload_info
*);
856 static void record_address_regs (enum machine_mode
, rtx
, int, enum rtx_code
,
858 #ifdef FORBIDDEN_INC_DEC_CLASSES
859 static int auto_inc_dec_reg_p (rtx
, enum machine_mode
);
861 static void reg_scan_mark_refs (rtx
, rtx
, int);
863 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
866 ok_for_index_p_nonstrict (rtx reg
)
868 unsigned regno
= REGNO (reg
);
869 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
872 /* A version of regno_ok_for_base_p for use during regclass, when all pseudos
873 should count as OK. Arguments as for regno_ok_for_base_p. */
876 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
,
877 enum rtx_code outer_code
, enum rtx_code index_code
)
879 unsigned regno
= REGNO (reg
);
880 if (regno
>= FIRST_PSEUDO_REGISTER
)
883 return ok_for_base_p_1 (regno
, mode
, outer_code
, index_code
);
886 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
887 This function is sometimes called before the info has been computed.
888 When that happens, just return GENERAL_REGS, which is innocuous. */
891 reg_preferred_class (int regno
)
895 return (enum reg_class
) reg_pref
[regno
].prefclass
;
899 reg_alternate_class (int regno
)
904 return (enum reg_class
) reg_pref
[regno
].altclass
;
907 /* Initialize some global data for this pass. */
914 init_cost
.mem_cost
= 10000;
915 for (i
= 0; i
< N_REG_CLASSES
; i
++)
916 init_cost
.cost
[i
] = 10000;
918 /* This prevents dump_flow_info from losing if called
919 before regclass is run. */
922 /* No more global register variables may be declared. */
923 no_global_reg_vars
= 1;
926 /* Dump register costs. */
928 dump_regclass (FILE *dump
)
931 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
933 int /* enum reg_class */ class;
936 fprintf (dump
, " Register %i costs:", i
);
937 for (class = 0; class < (int) N_REG_CLASSES
; class++)
938 if (contains_reg_of_mode
[(enum reg_class
) class][PSEUDO_REGNO_MODE (i
)]
939 #ifdef FORBIDDEN_INC_DEC_CLASSES
941 || !forbidden_inc_dec_class
[(enum reg_class
) class])
943 #ifdef CANNOT_CHANGE_MODE_CLASS
944 && ! invalid_mode_change_p (i
, (enum reg_class
) class,
945 PSEUDO_REGNO_MODE (i
))
948 fprintf (dump
, " %s:%i", reg_class_names
[class],
949 costs
[i
].cost
[(enum reg_class
) class]);
950 fprintf (dump
, " MEM:%i\n", costs
[i
].mem_cost
);
956 /* Calculate the costs of insn operands. */
959 record_operand_costs (rtx insn
, struct costs
*op_costs
,
960 struct reg_pref
*reg_pref
)
962 const char *constraints
[MAX_RECOG_OPERANDS
];
963 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
966 for (i
= 0; i
< recog_data
.n_operands
; i
++)
968 constraints
[i
] = recog_data
.constraints
[i
];
969 modes
[i
] = recog_data
.operand_mode
[i
];
972 /* If we get here, we are set up to record the costs of all the
973 operands for this insn. Start by initializing the costs.
974 Then handle any address registers. Finally record the desired
975 classes for any pseudos, doing it twice if some pair of
976 operands are commutative. */
978 for (i
= 0; i
< recog_data
.n_operands
; i
++)
980 op_costs
[i
] = init_cost
;
982 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
983 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
985 if (MEM_P (recog_data
.operand
[i
]))
986 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
987 XEXP (recog_data
.operand
[i
], 0),
988 0, MEM
, SCRATCH
, frequency
* 2);
989 else if (constraints
[i
][0] == 'p'
990 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0], constraints
[i
]))
991 record_address_regs (VOIDmode
, recog_data
.operand
[i
], 0, ADDRESS
,
992 SCRATCH
, frequency
* 2);
995 /* Check for commutative in a separate loop so everything will
996 have been initialized. We must do this even if one operand
997 is a constant--see addsi3 in m68k.md. */
999 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
1000 if (constraints
[i
][0] == '%')
1002 const char *xconstraints
[MAX_RECOG_OPERANDS
];
1005 /* Handle commutative operands by swapping the constraints.
1006 We assume the modes are the same. */
1008 for (j
= 0; j
< recog_data
.n_operands
; j
++)
1009 xconstraints
[j
] = constraints
[j
];
1011 xconstraints
[i
] = constraints
[i
+1];
1012 xconstraints
[i
+1] = constraints
[i
];
1013 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1014 recog_data
.operand
, modes
,
1015 xconstraints
, insn
, op_costs
, reg_pref
);
1018 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1019 recog_data
.operand
, modes
,
1020 constraints
, insn
, op_costs
, reg_pref
);
1023 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1024 time it would save code to put a certain register in a certain class.
1025 PASS, when nonzero, inhibits some optimizations which need only be done
1027 Return the last insn processed, so that the scan can be continued from
1031 scan_one_insn (rtx insn
, int pass
)
1033 enum rtx_code pat_code
;
1036 struct costs op_costs
[MAX_RECOG_OPERANDS
];
1041 pat_code
= GET_CODE (PATTERN (insn
));
1043 || pat_code
== CLOBBER
1044 || pat_code
== ASM_INPUT
1045 || pat_code
== ADDR_VEC
1046 || pat_code
== ADDR_DIFF_VEC
)
1049 set
= single_set (insn
);
1050 extract_insn (insn
);
1052 /* If this insn loads a parameter from its stack slot, then
1053 it represents a savings, rather than a cost, if the
1054 parameter is stored in memory. Record this fact. */
1056 if (set
!= 0 && REG_P (SET_DEST (set
))
1057 && MEM_P (SET_SRC (set
))
1058 && (note
= find_reg_note (insn
, REG_EQUIV
,
1060 && MEM_P (XEXP (note
, 0)))
1062 costs
[REGNO (SET_DEST (set
))].mem_cost
1063 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
1066 record_address_regs (GET_MODE (SET_SRC (set
)), XEXP (SET_SRC (set
), 0),
1067 0, MEM
, SCRATCH
, frequency
* 2);
1071 /* Improve handling of two-address insns such as
1072 (set X (ashift CONST Y)) where CONST must be made to
1073 match X. Change it into two insns: (set X CONST)
1074 (set X (ashift X Y)). If we left this for reloading, it
1075 would probably get three insns because X and Y might go
1076 in the same place. This prevents X and Y from receiving
1079 We can only do this if the modes of operands 0 and 1
1080 (which might not be the same) are tieable and we only need
1081 do this during our first pass. */
1083 if (pass
== 0 && optimize
1084 && recog_data
.n_operands
>= 3
1085 && recog_data
.constraints
[1][0] == '0'
1086 && recog_data
.constraints
[1][1] == 0
1087 && CONSTANT_P (recog_data
.operand
[1])
1088 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[1])
1089 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[2])
1090 && REG_P (recog_data
.operand
[0])
1091 && MODES_TIEABLE_P (GET_MODE (recog_data
.operand
[0]),
1092 recog_data
.operand_mode
[1]))
1094 rtx previnsn
= prev_real_insn (insn
);
1096 = gen_lowpart (recog_data
.operand_mode
[1],
1097 recog_data
.operand
[0]);
1099 = emit_insn_before (gen_move_insn (dest
, recog_data
.operand
[1]), insn
);
1101 /* If this insn was the start of a basic block,
1102 include the new insn in that block.
1103 We need not check for code_label here;
1104 while a basic block can start with a code_label,
1105 INSN could not be at the beginning of that block. */
1106 if (previnsn
== 0 || JUMP_P (previnsn
))
1110 if (insn
== BB_HEAD (b
))
1111 BB_HEAD (b
) = newinsn
;
1114 /* This makes one more setting of new insns's dest. */
1115 REG_N_SETS (REGNO (recog_data
.operand
[0]))++;
1116 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1117 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1119 *recog_data
.operand_loc
[1] = recog_data
.operand
[0];
1120 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1121 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1122 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
1123 if (recog_data
.dup_num
[i
] == 1)
1125 *recog_data
.dup_loc
[i
] = recog_data
.operand
[0];
1126 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1127 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1130 return PREV_INSN (newinsn
);
1133 record_operand_costs (insn
, op_costs
, reg_pref
);
1135 /* Now add the cost for each operand to the total costs for
1138 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1139 if (REG_P (recog_data
.operand
[i
])
1140 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1142 int regno
= REGNO (recog_data
.operand
[i
]);
1143 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
1145 p
->mem_cost
+= q
->mem_cost
* frequency
;
1146 for (j
= 0; j
< N_REG_CLASSES
; j
++)
1147 p
->cost
[j
] += q
->cost
[j
] * frequency
;
1153 /* Initialize information about which register classes can be used for
1154 pseudos that are auto-incremented or auto-decremented. */
1157 init_reg_autoinc (void)
1159 #ifdef FORBIDDEN_INC_DEC_CLASSES
1162 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1164 rtx r
= gen_rtx_raw_REG (VOIDmode
, 0);
1165 enum machine_mode m
;
1168 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1169 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
1173 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
1174 m
= (enum machine_mode
) ((int) m
+ 1))
1175 if (HARD_REGNO_MODE_OK (j
, m
))
1177 /* ??? There are two assumptions here; that the base class does not
1178 depend on the exact outer code (POST_INC vs. PRE_INC etc.), and
1179 that it does not depend on the machine mode of the memory
1181 enum reg_class base_class
1182 = base_reg_class (VOIDmode
, POST_INC
, SCRATCH
);
1186 /* If a register is not directly suitable for an
1187 auto-increment or decrement addressing mode and
1188 requires secondary reloads, disallow its class from
1189 being used in such addresses. */
1191 if ((secondary_reload_class (1, base_class
, m
, r
)
1192 || secondary_reload_class (1, base_class
, m
, r
))
1193 && ! auto_inc_dec_reg_p (r
, m
))
1194 forbidden_inc_dec_class
[i
] = 1;
1198 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1201 /* This is a pass of the compiler that scans all instructions
1202 and calculates the preferred class for each pseudo-register.
1203 This information can be accessed later by calling `reg_preferred_class'.
1204 This pass comes just before local register allocation. */
1207 regclass (rtx f
, int nregs
)
1215 costs
= XNEWVEC (struct costs
, nregs
);
1217 #ifdef FORBIDDEN_INC_DEC_CLASSES
1219 in_inc_dec
= XNEWVEC (char, nregs
);
1221 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1223 /* Normally we scan the insns once and determine the best class to use for
1224 each register. However, if -fexpensive_optimizations are on, we do so
1225 twice, the second time using the tentative best classes to guide the
1228 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1233 fprintf (dump_file
, "\n\nPass %i\n\n",pass
);
1234 /* Zero out our accumulation of the cost of each class for each reg. */
1236 memset (costs
, 0, nregs
* sizeof (struct costs
));
1238 #ifdef FORBIDDEN_INC_DEC_CLASSES
1239 memset (in_inc_dec
, 0, nregs
);
1242 /* Scan the instructions and record each time it would
1243 save code to put a certain register in a certain class. */
1247 frequency
= REG_FREQ_MAX
;
1248 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1249 insn
= scan_one_insn (insn
, pass
);
1254 /* Show that an insn inside a loop is likely to be executed three
1255 times more than insns outside a loop. This is much more
1256 aggressive than the assumptions made elsewhere and is being
1257 tried as an experiment. */
1258 frequency
= REG_FREQ_FROM_BB (bb
);
1259 for (insn
= BB_HEAD (bb
); ; insn
= NEXT_INSN (insn
))
1261 insn
= scan_one_insn (insn
, pass
);
1262 if (insn
== BB_END (bb
))
1267 /* Now for each register look at how desirable each class is
1268 and find which class is preferred. Store that in
1269 `prefclass'. Record in `altclass' the largest register
1270 class any of whose registers is better than memory. */
1273 reg_pref
= reg_pref_buffer
;
1277 dump_regclass (dump_file
);
1278 fprintf (dump_file
,"\n");
1280 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1282 int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1283 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1284 /* This is an enum reg_class, but we call it an int
1285 to save lots of casts. */
1287 struct costs
*p
= &costs
[i
];
1289 /* In non-optimizing compilation REG_N_REFS is not initialized
1291 if (optimize
&& !REG_N_REFS (i
) && !REG_N_SETS (i
))
1294 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1296 /* Ignore classes that are too small for this operand or
1297 invalid for an operand that was auto-incremented. */
1298 if (!contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1299 #ifdef FORBIDDEN_INC_DEC_CLASSES
1300 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1302 #ifdef CANNOT_CHANGE_MODE_CLASS
1303 || invalid_mode_change_p (i
, (enum reg_class
) class,
1304 PSEUDO_REGNO_MODE (i
))
1308 else if (p
->cost
[class] < best_cost
)
1310 best_cost
= p
->cost
[class];
1311 best
= (enum reg_class
) class;
1313 else if (p
->cost
[class] == best_cost
)
1314 best
= reg_class_subunion
[(int) best
][class];
1317 /* If no register class is better than memory, use memory. */
1318 if (p
->mem_cost
< best_cost
)
1321 /* Record the alternate register class; i.e., a class for which
1322 every register in it is better than using memory. If adding a
1323 class would make a smaller class (i.e., no union of just those
1324 classes exists), skip that class. The major unions of classes
1325 should be provided as a register class. Don't do this if we
1326 will be doing it again later. */
1328 if ((pass
== 1 || dump_file
) || ! flag_expensive_optimizations
)
1329 for (class = 0; class < N_REG_CLASSES
; class++)
1330 if (p
->cost
[class] < p
->mem_cost
1331 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1332 > reg_class_size
[(int) alt
])
1333 #ifdef FORBIDDEN_INC_DEC_CLASSES
1334 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1336 #ifdef CANNOT_CHANGE_MODE_CLASS
1337 && ! invalid_mode_change_p (i
, (enum reg_class
) class,
1338 PSEUDO_REGNO_MODE (i
))
1341 alt
= reg_class_subunion
[(int) alt
][class];
1343 /* If we don't add any classes, nothing to try. */
1348 && (reg_pref
[i
].prefclass
!= (int) best
1349 || reg_pref
[i
].altclass
!= (int) alt
))
1351 fprintf (dump_file
, " Register %i", i
);
1352 if (alt
== ALL_REGS
|| best
== ALL_REGS
)
1353 fprintf (dump_file
, " pref %s\n", reg_class_names
[(int) best
]);
1354 else if (alt
== NO_REGS
)
1355 fprintf (dump_file
, " pref %s or none\n", reg_class_names
[(int) best
]);
1357 fprintf (dump_file
, " pref %s, else %s\n",
1358 reg_class_names
[(int) best
],
1359 reg_class_names
[(int) alt
]);
1362 /* We cast to (int) because (char) hits bugs in some compilers. */
1363 reg_pref
[i
].prefclass
= (int) best
;
1364 reg_pref
[i
].altclass
= (int) alt
;
1368 #ifdef FORBIDDEN_INC_DEC_CLASSES
1374 /* Record the cost of using memory or registers of various classes for
1375 the operands in INSN.
1377 N_ALTS is the number of alternatives.
1379 N_OPS is the number of operands.
1381 OPS is an array of the operands.
1383 MODES are the modes of the operands, in case any are VOIDmode.
1385 CONSTRAINTS are the constraints to use for the operands. This array
1386 is modified by this procedure.
1388 This procedure works alternative by alternative. For each alternative
1389 we assume that we will be able to allocate all pseudos to their ideal
1390 register class and calculate the cost of using that alternative. Then
1391 we compute for each operand that is a pseudo-register, the cost of
1392 having the pseudo allocated to each register class and using it in that
1393 alternative. To this cost is added the cost of the alternative.
1395 The cost of each class for this insn is its lowest cost among all the
1399 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
1400 enum machine_mode
*modes
, const char **constraints
,
1401 rtx insn
, struct costs
*op_costs
,
1402 struct reg_pref
*reg_pref
)
1408 /* Process each alternative, each time minimizing an operand's cost with
1409 the cost for each operand in that alternative. */
1411 for (alt
= 0; alt
< n_alts
; alt
++)
1413 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1416 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1417 int allows_mem
[MAX_RECOG_OPERANDS
];
1420 for (i
= 0; i
< n_ops
; i
++)
1422 const char *p
= constraints
[i
];
1424 enum machine_mode mode
= modes
[i
];
1425 int allows_addr
= 0;
1429 /* Initially show we know nothing about the register class. */
1430 classes
[i
] = NO_REGS
;
1433 /* If this operand has no constraints at all, we can conclude
1434 nothing about it since anything is valid. */
1438 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1439 memset (&this_op_costs
[i
], 0, sizeof this_op_costs
[i
]);
1444 /* If this alternative is only relevant when this operand
1445 matches a previous operand, we do different things depending
1446 on whether this operand is a pseudo-reg or not. We must process
1447 any modifiers for the operand before we can make this test. */
1449 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1452 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1454 /* Copy class and whether memory is allowed from the matching
1455 alternative. Then perform any needed cost computations
1456 and/or adjustments. */
1458 classes
[i
] = classes
[j
];
1459 allows_mem
[i
] = allows_mem
[j
];
1461 if (!REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1463 /* If this matches the other operand, we have no added
1465 if (rtx_equal_p (ops
[j
], op
))
1468 /* If we can put the other operand into a register, add to
1469 the cost of this alternative the cost to copy this
1470 operand to the register used for the other operand. */
1472 else if (classes
[j
] != NO_REGS
)
1474 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
1478 else if (!REG_P (ops
[j
])
1479 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1481 /* This op is a pseudo but the one it matches is not. */
1483 /* If we can't put the other operand into a register, this
1484 alternative can't be used. */
1486 if (classes
[j
] == NO_REGS
)
1489 /* Otherwise, add to the cost of this alternative the cost
1490 to copy the other operand to the register used for this
1494 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
1498 /* The costs of this operand are not the same as the other
1499 operand since move costs are not symmetric. Moreover,
1500 if we cannot tie them, this alternative needs to do a
1501 copy, which is one instruction. */
1503 struct costs
*pp
= &this_op_costs
[i
];
1505 for (class = 0; class < N_REG_CLASSES
; class++)
1507 = ((recog_data
.operand_type
[i
] != OP_OUT
1508 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1510 + (recog_data
.operand_type
[i
] != OP_IN
1511 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1514 /* If the alternative actually allows memory, make things
1515 a bit cheaper since we won't need an extra insn to
1519 = ((recog_data
.operand_type
[i
] != OP_IN
1520 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1522 + (recog_data
.operand_type
[i
] != OP_OUT
1523 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1524 : 0) - allows_mem
[i
]);
1526 /* If we have assigned a class to this register in our
1527 first pass, add a cost to this alternative corresponding
1528 to what we would add if this register were not in the
1529 appropriate class. */
1531 if (reg_pref
&& reg_pref
[REGNO (op
)].prefclass
!= NO_REGS
)
1533 += (may_move_in_cost
[mode
]
1534 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1535 [(int) classes
[i
]]);
1537 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1538 && ! find_reg_note (insn
, REG_DEAD
, op
))
1541 /* This is in place of ordinary cost computation
1542 for this operand, so skip to the end of the
1543 alternative (should be just one character). */
1544 while (*p
&& *p
++ != ',')
1552 /* Scan all the constraint letters. See if the operand matches
1553 any of the constraints. Collect the valid register classes
1554 and see if this operand accepts memory. */
1563 /* Ignore the next letter for this pass. */
1569 case '!': case '#': case '&':
1570 case '0': case '1': case '2': case '3': case '4':
1571 case '5': case '6': case '7': case '8': case '9':
1576 win
= address_operand (op
, GET_MODE (op
));
1577 /* We know this operand is an address, so we want it to be
1578 allocated to a register that can be the base of an
1579 address, i.e. BASE_REG_CLASS. */
1581 = reg_class_subunion
[(int) classes
[i
]]
1582 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1585 case 'm': case 'o': case 'V':
1586 /* It doesn't seem worth distinguishing between offsettable
1587 and non-offsettable addresses here. */
1595 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1596 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1602 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1603 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1609 if (GET_CODE (op
) == CONST_DOUBLE
1610 || (GET_CODE (op
) == CONST_VECTOR
1611 && (GET_MODE_CLASS (GET_MODE (op
))
1612 == MODE_VECTOR_FLOAT
)))
1618 if (GET_CODE (op
) == CONST_DOUBLE
1619 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1624 if (GET_CODE (op
) == CONST_INT
1625 || (GET_CODE (op
) == CONST_DOUBLE
1626 && GET_MODE (op
) == VOIDmode
))
1630 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1635 if (GET_CODE (op
) == CONST_INT
1636 || (GET_CODE (op
) == CONST_DOUBLE
1637 && GET_MODE (op
) == VOIDmode
))
1649 if (GET_CODE (op
) == CONST_INT
1650 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1661 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
1666 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1670 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) != NO_REGS
)
1672 = reg_class_subunion
[(int) classes
[i
]]
1673 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1674 #ifdef EXTRA_CONSTRAINT_STR
1675 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1678 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1680 /* Every MEM can be reloaded to fit. */
1685 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1687 /* Every address can be reloaded to fit. */
1689 if (address_operand (op
, GET_MODE (op
)))
1691 /* We know this operand is an address, so we want it to
1692 be allocated to a register that can be the base of an
1693 address, i.e. BASE_REG_CLASS. */
1695 = reg_class_subunion
[(int) classes
[i
]]
1696 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1701 p
+= CONSTRAINT_LEN (c
, p
);
1708 /* How we account for this operand now depends on whether it is a
1709 pseudo register or not. If it is, we first check if any
1710 register classes are valid. If not, we ignore this alternative,
1711 since we want to assume that all pseudos get allocated for
1712 register preferencing. If some register class is valid, compute
1713 the costs of moving the pseudo into that class. */
1715 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1717 if (classes
[i
] == NO_REGS
)
1719 /* We must always fail if the operand is a REG, but
1720 we did not find a suitable class.
1722 Otherwise we may perform an uninitialized read
1723 from this_op_costs after the `continue' statement
1729 struct costs
*pp
= &this_op_costs
[i
];
1731 for (class = 0; class < N_REG_CLASSES
; class++)
1733 = ((recog_data
.operand_type
[i
] != OP_OUT
1734 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1736 + (recog_data
.operand_type
[i
] != OP_IN
1737 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1740 /* If the alternative actually allows memory, make things
1741 a bit cheaper since we won't need an extra insn to
1745 = ((recog_data
.operand_type
[i
] != OP_IN
1746 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1748 + (recog_data
.operand_type
[i
] != OP_OUT
1749 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1750 : 0) - allows_mem
[i
]);
1752 /* If we have assigned a class to this register in our
1753 first pass, add a cost to this alternative corresponding
1754 to what we would add if this register were not in the
1755 appropriate class. */
1757 if (reg_pref
&& reg_pref
[REGNO (op
)].prefclass
!= NO_REGS
)
1759 += (may_move_in_cost
[mode
]
1760 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1761 [(int) classes
[i
]]);
1765 /* Otherwise, if this alternative wins, either because we
1766 have already determined that or if we have a hard register of
1767 the proper class, there is no cost for this alternative. */
1771 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1774 /* If registers are valid, the cost of this alternative includes
1775 copying the object to and/or from a register. */
1777 else if (classes
[i
] != NO_REGS
)
1779 if (recog_data
.operand_type
[i
] != OP_OUT
)
1780 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
1782 if (recog_data
.operand_type
[i
] != OP_IN
)
1783 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
1786 /* The only other way this alternative can be used is if this is a
1787 constant that could be placed into memory. */
1789 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1790 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1798 /* Finally, update the costs with the information we've calculated
1799 about this alternative. */
1801 for (i
= 0; i
< n_ops
; i
++)
1803 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1805 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1806 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1808 pp
->mem_cost
= MIN (pp
->mem_cost
,
1809 (qq
->mem_cost
+ alt_cost
) * scale
);
1811 for (class = 0; class < N_REG_CLASSES
; class++)
1812 pp
->cost
[class] = MIN (pp
->cost
[class],
1813 (qq
->cost
[class] + alt_cost
) * scale
);
1817 /* If this insn is a single set copying operand 1 to operand 0
1818 and one operand is a pseudo with the other a hard reg or a pseudo
1819 that prefers a register that is in its own register class then
1820 we may want to adjust the cost of that register class to -1.
1822 Avoid the adjustment if the source does not die to avoid stressing of
1823 register allocator by preferrencing two colliding registers into single
1826 Also avoid the adjustment if a copy between registers of the class
1827 is expensive (ten times the cost of a default copy is considered
1828 arbitrarily expensive). This avoids losing when the preferred class
1829 is very expensive as the source of a copy instruction. */
1831 if ((set
= single_set (insn
)) != 0
1832 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1833 && REG_P (ops
[0]) && REG_P (ops
[1])
1834 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
1835 for (i
= 0; i
<= 1; i
++)
1836 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1838 unsigned int regno
= REGNO (ops
[!i
]);
1839 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1843 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_pref
!= 0
1844 && reg_pref
[regno
].prefclass
!= NO_REGS
)
1846 enum reg_class pref
= reg_pref
[regno
].prefclass
;
1848 if ((reg_class_size
[(unsigned char) pref
]
1849 == (unsigned) CLASS_MAX_NREGS (pref
, mode
))
1850 && REGISTER_MOVE_COST (mode
, pref
, pref
) < 10 * 2)
1851 op_costs
[i
].cost
[(unsigned char) pref
] = -1;
1853 else if (regno
< FIRST_PSEUDO_REGISTER
)
1854 for (class = 0; class < N_REG_CLASSES
; class++)
1855 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1856 && reg_class_size
[class] == (unsigned) CLASS_MAX_NREGS (class, mode
))
1858 if (reg_class_size
[class] == 1)
1859 op_costs
[i
].cost
[class] = -1;
1862 for (nr
= 0; nr
< (unsigned) hard_regno_nregs
[regno
][mode
]; nr
++)
1864 if (! TEST_HARD_REG_BIT (reg_class_contents
[class],
1869 if (nr
== (unsigned) hard_regno_nregs
[regno
][mode
])
1870 op_costs
[i
].cost
[class] = -1;
1876 /* Compute the cost of loading X into (if TO_P is nonzero) or from (if
1877 TO_P is zero) a register of class CLASS in mode MODE.
1879 X must not be a pseudo. */
1882 copy_cost (rtx x
, enum machine_mode mode
, enum reg_class
class, int to_p
,
1883 secondary_reload_info
*prev_sri
)
1885 enum reg_class secondary_class
= NO_REGS
;
1886 secondary_reload_info sri
;
1888 /* If X is a SCRATCH, there is actually nothing to move since we are
1889 assuming optimal allocation. */
1891 if (GET_CODE (x
) == SCRATCH
)
1894 /* Get the class we will actually use for a reload. */
1895 class = PREFERRED_RELOAD_CLASS (x
, class);
1897 /* If we need a secondary reload for an intermediate, the
1898 cost is that to load the input into the intermediate register, then
1901 sri
.prev_sri
= prev_sri
;
1903 secondary_class
= targetm
.secondary_reload (to_p
, x
, class, mode
, &sri
);
1905 if (secondary_class
!= NO_REGS
)
1906 return (move_cost
[mode
][(int) secondary_class
][(int) class]
1908 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
1910 /* For memory, use the memory move cost, for (hard) registers, use the
1911 cost to move between the register classes, and use 2 for everything
1912 else (constants). */
1914 if (MEM_P (x
) || class == NO_REGS
)
1915 return sri
.extra_cost
+ MEMORY_MOVE_COST (mode
, class, to_p
);
1918 return (sri
.extra_cost
1919 + move_cost
[mode
][(int) REGNO_REG_CLASS (REGNO (x
))][(int) class]);
1922 /* If this is a constant, we may eventually want to call rtx_cost here. */
1923 return sri
.extra_cost
+ COSTS_N_INSNS (1);
1926 /* Record the pseudo registers we must reload into hard registers
1927 in a subexpression of a memory address, X.
1929 If CONTEXT is 0, we are looking at the base part of an address, otherwise we
1930 are looking at the index part.
1932 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
1933 give the context that the rtx appears in. These three arguments are
1934 passed down to base_reg_class.
1936 SCALE is twice the amount to multiply the cost by (it is twice so we
1937 can represent half-cost adjustments). */
1940 record_address_regs (enum machine_mode mode
, rtx x
, int context
,
1941 enum rtx_code outer_code
, enum rtx_code index_code
,
1944 enum rtx_code code
= GET_CODE (x
);
1945 enum reg_class
class;
1948 class = INDEX_REG_CLASS
;
1950 class = base_reg_class (mode
, outer_code
, index_code
);
1963 /* When we have an address that is a sum,
1964 we must determine whether registers are "base" or "index" regs.
1965 If there is a sum of two registers, we must choose one to be
1966 the "base". Luckily, we can use the REG_POINTER to make a good
1967 choice most of the time. We only need to do this on machines
1968 that can have two registers in an address and where the base
1969 and index register classes are different.
1971 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1972 that seems bogus since it should only be set when we are sure
1973 the register is being used as a pointer. */
1976 rtx arg0
= XEXP (x
, 0);
1977 rtx arg1
= XEXP (x
, 1);
1978 enum rtx_code code0
= GET_CODE (arg0
);
1979 enum rtx_code code1
= GET_CODE (arg1
);
1981 /* Look inside subregs. */
1982 if (code0
== SUBREG
)
1983 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1984 if (code1
== SUBREG
)
1985 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1987 /* If this machine only allows one register per address, it must
1988 be in the first operand. */
1990 if (MAX_REGS_PER_ADDRESS
== 1)
1991 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
1993 /* If index and base registers are the same on this machine, just
1994 record registers in any non-constant operands. We assume here,
1995 as well as in the tests below, that all addresses are in
1998 else if (INDEX_REG_CLASS
== base_reg_class (VOIDmode
, PLUS
, SCRATCH
))
2000 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
2001 if (! CONSTANT_P (arg1
))
2002 record_address_regs (mode
, arg1
, context
, PLUS
, code0
, scale
);
2005 /* If the second operand is a constant integer, it doesn't change
2006 what class the first operand must be. */
2008 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
2009 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
2011 /* If the second operand is a symbolic constant, the first operand
2012 must be an index register. */
2014 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
2015 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
2017 /* If both operands are registers but one is already a hard register
2018 of index or reg-base class, give the other the class that the
2019 hard register is not. */
2021 else if (code0
== REG
&& code1
== REG
2022 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
2023 && (ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
2024 || ok_for_index_p_nonstrict (arg0
)))
2025 record_address_regs (mode
, arg1
,
2026 ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
2029 else if (code0
== REG
&& code1
== REG
2030 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
2031 && (ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
2032 || ok_for_index_p_nonstrict (arg1
)))
2033 record_address_regs (mode
, arg0
,
2034 ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
2038 /* If one operand is known to be a pointer, it must be the base
2039 with the other operand the index. Likewise if the other operand
2042 else if ((code0
== REG
&& REG_POINTER (arg0
))
2045 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
2046 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
);
2048 else if ((code1
== REG
&& REG_POINTER (arg1
))
2051 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
2052 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
);
2055 /* Otherwise, count equal chances that each might be a base
2056 or index register. This case should be rare. */
2060 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
/ 2);
2061 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
/ 2);
2062 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
/ 2);
2063 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
/ 2);
2068 /* Double the importance of a pseudo register that is incremented
2069 or decremented, since it would take two extra insns
2070 if it ends up in the wrong place. */
2073 record_address_regs (mode
, XEXP (x
, 0), 0, code
,
2074 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
2075 if (REG_P (XEXP (XEXP (x
, 1), 1)))
2076 record_address_regs (mode
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
2084 /* Double the importance of a pseudo register that is incremented
2085 or decremented, since it would take two extra insns
2086 if it ends up in the wrong place. If the operand is a pseudo,
2087 show it is being used in an INC_DEC context. */
2089 #ifdef FORBIDDEN_INC_DEC_CLASSES
2090 if (REG_P (XEXP (x
, 0))
2091 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
2092 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
2095 record_address_regs (mode
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
2100 struct costs
*pp
= &costs
[REGNO (x
)];
2103 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
2105 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2106 pp
->cost
[i
] += (may_move_in_cost
[Pmode
][i
][(int) class] * scale
) / 2;
2112 const char *fmt
= GET_RTX_FORMAT (code
);
2114 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2116 record_address_regs (mode
, XEXP (x
, i
), context
, code
, SCRATCH
,
2122 #ifdef FORBIDDEN_INC_DEC_CLASSES
2124 /* Return 1 if REG is valid as an auto-increment memory reference
2125 to an object of MODE. */
2128 auto_inc_dec_reg_p (rtx reg
, enum machine_mode mode
)
2130 if (HAVE_POST_INCREMENT
2131 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
2134 if (HAVE_POST_DECREMENT
2135 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
2138 if (HAVE_PRE_INCREMENT
2139 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
2142 if (HAVE_PRE_DECREMENT
2143 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
2150 static short *renumber
;
2151 static size_t regno_allocated
;
2152 static unsigned int reg_n_max
;
2154 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2155 reg_scan and flow_analysis that are indexed by the register number. If
2156 NEW_P is nonzero, initialize all of the registers, otherwise only
2157 initialize the new registers allocated. The same table is kept from
2158 function to function, only reallocating it when we need more room. If
2159 RENUMBER_P is nonzero, allocate the reg_renumber array also. */
2162 allocate_reg_info (size_t num_regs
, int new_p
, int renumber_p
)
2165 size_t size_renumber
;
2166 size_t min
= (new_p
) ? 0 : reg_n_max
;
2167 struct reg_info_data
*reg_data
;
2169 if (num_regs
> regno_allocated
)
2171 size_t old_allocated
= regno_allocated
;
2173 regno_allocated
= num_regs
+ (num_regs
/ 20); /* Add some slop space. */
2174 size_renumber
= regno_allocated
* sizeof (short);
2178 reg_n_info
= VEC_alloc (reg_info_p
, heap
, regno_allocated
);
2179 VEC_safe_grow (reg_info_p
, heap
, reg_n_info
, regno_allocated
);
2180 memset (VEC_address (reg_info_p
, reg_n_info
), 0,
2181 sizeof (reg_info_p
) * regno_allocated
);
2182 renumber
= xmalloc (size_renumber
);
2183 reg_pref_buffer
= XNEWVEC (struct reg_pref
, regno_allocated
);
2187 size_t old_length
= VEC_length (reg_info_p
, reg_n_info
);
2188 if (old_length
< regno_allocated
)
2191 VEC_safe_grow (reg_info_p
, heap
, reg_n_info
, regno_allocated
);
2192 addr
= VEC_address (reg_info_p
, reg_n_info
);
2193 memset (&addr
[old_length
], 0,
2194 sizeof (reg_info_p
) * (regno_allocated
- old_length
));
2196 else if (regno_allocated
< old_length
)
2198 VEC_truncate (reg_info_p
, reg_n_info
, regno_allocated
);
2201 if (new_p
) /* If we're zapping everything, no need to realloc. */
2203 free ((char *) renumber
);
2204 free ((char *) reg_pref
);
2205 renumber
= xmalloc (size_renumber
);
2206 reg_pref_buffer
= XNEWVEC (struct reg_pref
, regno_allocated
);
2211 renumber
= xrealloc (renumber
, size_renumber
);
2212 reg_pref_buffer
= (struct reg_pref
*) xrealloc (reg_pref_buffer
,
2214 * sizeof (struct reg_pref
));
2218 size_info
= (regno_allocated
- old_allocated
) * sizeof (reg_info
)
2219 + sizeof (struct reg_info_data
) - sizeof (reg_info
);
2220 reg_data
= xcalloc (size_info
, 1);
2221 reg_data
->min_index
= old_allocated
;
2222 reg_data
->max_index
= regno_allocated
- 1;
2223 reg_data
->next
= reg_info_head
;
2224 reg_info_head
= reg_data
;
2227 reg_n_max
= num_regs
;
2230 /* Loop through each of the segments allocated for the actual
2231 reg_info pages, and set up the pointers, zero the pages, etc. */
2232 for (reg_data
= reg_info_head
;
2233 reg_data
&& reg_data
->max_index
>= min
;
2234 reg_data
= reg_data
->next
)
2236 size_t min_index
= reg_data
->min_index
;
2237 size_t max_index
= reg_data
->max_index
;
2238 size_t max
= MIN (max_index
, num_regs
);
2239 size_t local_min
= min
- min_index
;
2242 if (reg_data
->min_index
> num_regs
)
2245 if (min
< min_index
)
2247 if (!reg_data
->used_p
) /* page just allocated with calloc */
2248 reg_data
->used_p
= 1; /* no need to zero */
2250 memset (®_data
->data
[local_min
], 0,
2251 sizeof (reg_info
) * (max
- min_index
- local_min
+ 1));
2253 for (i
= min_index
+local_min
; i
<= max
; i
++)
2255 VEC_replace (reg_info_p
, reg_n_info
, i
,
2256 ®_data
->data
[i
-min_index
]);
2257 REG_BASIC_BLOCK (i
) = REG_BLOCK_UNKNOWN
;
2259 reg_pref_buffer
[i
].prefclass
= (char) NO_REGS
;
2260 reg_pref_buffer
[i
].altclass
= (char) NO_REGS
;
2265 /* If {pref,alt}class have already been allocated, update the pointers to
2266 the newly realloced ones. */
2268 reg_pref
= reg_pref_buffer
;
2271 reg_renumber
= renumber
;
2274 /* Free up the space allocated by allocate_reg_info. */
2276 free_reg_info (void)
2280 struct reg_info_data
*reg_data
;
2281 struct reg_info_data
*reg_next
;
2283 VEC_free (reg_info_p
, heap
, reg_n_info
);
2284 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
2286 reg_next
= reg_data
->next
;
2287 free ((char *) reg_data
);
2290 free (reg_pref_buffer
);
2291 reg_pref_buffer
= (struct reg_pref
*) 0;
2292 reg_info_head
= (struct reg_info_data
*) 0;
2293 renumber
= (short *) 0;
2295 regno_allocated
= 0;
2299 /* This is the `regscan' pass of the compiler, run just before cse
2300 and again just before loop.
2302 It finds the first and last use of each pseudo-register
2303 and records them in the vectors regno_first_uid, regno_last_uid
2304 and counts the number of sets in the vector reg_n_sets.
2306 REPEAT is nonzero the second time this is called. */
2308 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2309 Always at least 3, since the combiner could put that many together
2310 and we want this to remain correct for all the remaining passes.
2311 This corresponds to the maximum number of times note_stores will call
2312 a function for any insn. */
2316 /* Used as a temporary to record the largest number of registers in
2317 PARALLEL in a SET_DEST. This is added to max_parallel. */
2319 static int max_set_parallel
;
2322 reg_scan (rtx f
, unsigned int nregs
)
2326 timevar_push (TV_REG_SCAN
);
2328 allocate_reg_info (nregs
, TRUE
, FALSE
);
2330 max_set_parallel
= 0;
2332 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
2335 rtx pat
= PATTERN (insn
);
2336 if (GET_CODE (pat
) == PARALLEL
2337 && XVECLEN (pat
, 0) > max_parallel
)
2338 max_parallel
= XVECLEN (pat
, 0);
2339 reg_scan_mark_refs (pat
, insn
, 0);
2341 if (REG_NOTES (insn
))
2342 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1);
2345 max_parallel
+= max_set_parallel
;
2347 timevar_pop (TV_REG_SCAN
);
2350 /* X is the expression to scan. INSN is the insn it appears in.
2351 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */
2354 reg_scan_mark_refs (rtx x
, rtx insn
, int note_flag
)
2362 code
= GET_CODE (x
);
2379 unsigned int regno
= REGNO (x
);
2382 REGNO_LAST_UID (regno
) = INSN_UID (insn
);
2383 if (REGNO_FIRST_UID (regno
) == 0)
2384 REGNO_FIRST_UID (regno
) = INSN_UID (insn
);
2390 reg_scan_mark_refs (XEXP (x
, 0), insn
, note_flag
);
2392 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
);
2397 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
);
2402 rtx reg
= XEXP (x
, 0);
2405 REG_N_SETS (REGNO (reg
))++;
2406 REG_N_REFS (REGNO (reg
))++;
2408 else if (MEM_P (reg
))
2409 reg_scan_mark_refs (XEXP (reg
, 0), insn
, note_flag
);
2414 /* Count a set of the destination if it is a register. */
2415 for (dest
= SET_DEST (x
);
2416 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2417 || GET_CODE (dest
) == ZERO_EXTEND
;
2418 dest
= XEXP (dest
, 0))
2421 /* For a PARALLEL, record the number of things (less the usual one for a
2422 SET) that are set. */
2423 if (GET_CODE (dest
) == PARALLEL
)
2424 max_set_parallel
= MAX (max_set_parallel
, XVECLEN (dest
, 0) - 1);
2428 REG_N_SETS (REGNO (dest
))++;
2429 REG_N_REFS (REGNO (dest
))++;
2432 /* If this is setting a pseudo from another pseudo or the sum of a
2433 pseudo and a constant integer and the other pseudo is known to be
2434 a pointer, set the destination to be a pointer as well.
2436 Likewise if it is setting the destination from an address or from a
2437 value equivalent to an address or to the sum of an address and
2440 But don't do any of this if the pseudo corresponds to a user
2441 variable since it should have already been set as a pointer based
2444 if (REG_P (SET_DEST (x
))
2445 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2446 /* If the destination pseudo is set more than once, then other
2447 sets might not be to a pointer value (consider access to a
2448 union in two threads of control in the presence of global
2449 optimizations). So only set REG_POINTER on the destination
2450 pseudo if this is the only set of that pseudo. */
2451 && REG_N_SETS (REGNO (SET_DEST (x
))) == 1
2452 && ! REG_USERVAR_P (SET_DEST (x
))
2453 && ! REG_POINTER (SET_DEST (x
))
2454 && ((REG_P (SET_SRC (x
))
2455 && REG_POINTER (SET_SRC (x
)))
2456 || ((GET_CODE (SET_SRC (x
)) == PLUS
2457 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2458 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2459 && REG_P (XEXP (SET_SRC (x
), 0))
2460 && REG_POINTER (XEXP (SET_SRC (x
), 0)))
2461 || GET_CODE (SET_SRC (x
)) == CONST
2462 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2463 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2464 || (GET_CODE (SET_SRC (x
)) == HIGH
2465 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2466 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2467 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2468 || ((GET_CODE (SET_SRC (x
)) == PLUS
2469 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2470 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2471 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2472 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2473 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2474 && (GET_CODE (XEXP (note
, 0)) == CONST
2475 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2476 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2477 REG_POINTER (SET_DEST (x
)) = 1;
2479 /* If this is setting a register from a register or from a simple
2480 conversion of a register, propagate REG_EXPR. */
2483 rtx src
= SET_SRC (x
);
2485 while (GET_CODE (src
) == SIGN_EXTEND
2486 || GET_CODE (src
) == ZERO_EXTEND
2487 || GET_CODE (src
) == TRUNCATE
2488 || (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)))
2489 src
= XEXP (src
, 0);
2491 if (!REG_ATTRS (dest
) && REG_P (src
))
2492 REG_ATTRS (dest
) = REG_ATTRS (src
);
2493 if (!REG_ATTRS (dest
) && MEM_P (src
))
2494 set_reg_attrs_from_mem (dest
, src
);
2497 /* ... fall through ... */
2501 const char *fmt
= GET_RTX_FORMAT (code
);
2503 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2506 reg_scan_mark_refs (XEXP (x
, i
), insn
, note_flag
);
2507 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2510 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2511 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
, note_flag
);
2518 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2522 reg_class_subset_p (enum reg_class c1
, enum reg_class c2
)
2524 if (c1
== c2
) return 1;
2529 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) c1
],
2530 reg_class_contents
[(int) c2
],
2535 /* Return nonzero if there is a register that is in both C1 and C2. */
2538 reg_classes_intersect_p (enum reg_class c1
, enum reg_class c2
)
2542 if (c1
== c2
) return 1;
2544 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
2547 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
2548 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
2550 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);
2557 #ifdef CANNOT_CHANGE_MODE_CLASS
2559 struct subregs_of_mode_node
2562 unsigned char modes
[MAX_MACHINE_MODE
];
2565 static htab_t subregs_of_mode
;
2568 som_hash (const void *x
)
2570 const struct subregs_of_mode_node
*a
= x
;
2575 som_eq (const void *x
, const void *y
)
2577 const struct subregs_of_mode_node
*a
= x
;
2578 const struct subregs_of_mode_node
*b
= y
;
2579 return a
->block
== b
->block
;
2583 init_subregs_of_mode (void)
2585 if (subregs_of_mode
)
2586 htab_empty (subregs_of_mode
);
2588 subregs_of_mode
= htab_create (100, som_hash
, som_eq
, free
);
2592 record_subregs_of_mode (rtx subreg
)
2594 struct subregs_of_mode_node dummy
, *node
;
2595 enum machine_mode mode
;
2599 if (!REG_P (SUBREG_REG (subreg
)))
2602 regno
= REGNO (SUBREG_REG (subreg
));
2603 mode
= GET_MODE (subreg
);
2605 if (regno
< FIRST_PSEUDO_REGISTER
)
2608 dummy
.block
= regno
& -8;
2609 slot
= htab_find_slot_with_hash (subregs_of_mode
, &dummy
,
2610 dummy
.block
, INSERT
);
2614 node
= XCNEW (struct subregs_of_mode_node
);
2615 node
->block
= regno
& -8;
2619 node
->modes
[mode
] |= 1 << (regno
& 7);
2622 /* Set bits in *USED which correspond to registers which can't change
2623 their mode from FROM to any mode in which REGNO was encountered. */
2626 cannot_change_mode_set_regs (HARD_REG_SET
*used
, enum machine_mode from
,
2629 struct subregs_of_mode_node dummy
, *node
;
2630 enum machine_mode to
;
2634 dummy
.block
= regno
& -8;
2635 node
= htab_find_with_hash (subregs_of_mode
, &dummy
, dummy
.block
);
2639 mask
= 1 << (regno
& 7);
2640 for (to
= VOIDmode
; to
< NUM_MACHINE_MODES
; to
++)
2641 if (node
->modes
[to
] & mask
)
2642 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2643 if (!TEST_HARD_REG_BIT (*used
, i
)
2644 && REG_CANNOT_CHANGE_MODE_P (i
, from
, to
))
2645 SET_HARD_REG_BIT (*used
, i
);
2648 /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM
2652 invalid_mode_change_p (unsigned int regno
, enum reg_class
class,
2653 enum machine_mode from
)
2655 struct subregs_of_mode_node dummy
, *node
;
2656 enum machine_mode to
;
2659 dummy
.block
= regno
& -8;
2660 node
= htab_find_with_hash (subregs_of_mode
, &dummy
, dummy
.block
);
2664 mask
= 1 << (regno
& 7);
2665 for (to
= VOIDmode
; to
< NUM_MACHINE_MODES
; to
++)
2666 if (node
->modes
[to
] & mask
)
2667 if (CANNOT_CHANGE_MODE_CLASS (from
, to
, class))
2672 #endif /* CANNOT_CHANGE_MODE_CLASS */
2674 #include "gt-regclass.h"