gomp-20050608-branch/gcc/testsuite/gcc.target/powerpc/altivec-consts.c

   1 /* { dg-do run { target powerpc*-*-* } } */
   2 /* { dg-xfail-if "" { "powerpc-*-eabispe*" "powerpc-ibm-aix*" } { "*" } { "" } } */
   3 /* { dg-options "-maltivec -mabi=altivec -O2" } */
   4
   5 /* Check that "easy" AltiVec constants are correctly synthesized.  */
   6
   7 #include "altivec_check.h"
   8
   9 extern void abort (void);
  10
  11 typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
  12 typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
  13 typedef __attribute__ ((vector_size (16))) unsigned int v4si;
  14
  15 char w[16] __attribute__((aligned(16)));
  16
  17 \f
  18 /* Emulate the vspltis? instructions on a 16-byte array of chars.  */
  19
  20 void vspltisb (char *v, int val)
  21 {
  22   int i;
  23   for (i = 0; i < 16; i++)
  24     v[i] = val;
  25 }
  26
  27 void vspltish (char *v, int val)
  28 {
  29   int i;
  30   for (i = 0; i < 16; i += 2)
  31     v[i] = val >> 7, v[i + 1] = val;
  32 }
  33
  34 void vspltisw (char *v, int val)
  35 {
  36   int i;
  37   for (i = 0; i < 16; i += 4)
  38     v[i] = v[i + 1] = v[i + 2] = val >> 7, v[i + 3] = val;
  39 }
  40
  41 \f
  42 /* Use three different check functions for each mode-instruction pair.
  43    The callers have no typecasting and no addressable vectors, to make
  44    the test more robust.  */
  45
  46 void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2)
  47 {
  48   if (memcmp (&v1, v2, 16))
  49     abort ();
  50 }
  51
  52 void __attribute__ ((noinline)) check_v8hi (v8hi v1, char *v2)
  53 {
  54   if (memcmp (&v1, v2, 16))
  55     abort ();
  56 }
  57
  58 void __attribute__ ((noinline)) check_v4si (v4si v1, char *v2)
  59 {
  60   if (memcmp (&v1, v2, 16))
  61     abort ();
  62 }
  63
  64 \f
  65 /* V16QI tests.  */
  66
  67 void v16qi_vspltisb ()
  68 {
  69   v16qi v = { 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15 };
  70   vspltisb (w, 15);
  71   check_v16qi (v, w);
  72 }
  73
  74 void v16qi_vspltisb_neg ()
  75 {
  76   v16qi v = { -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5 };
  77   vspltisb (w, -5);
  78   check_v16qi (v, w);
  79 }
  80
  81 void v16qi_vspltisb_addself ()
  82 {
  83   v16qi v = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30 };
  84   vspltisb (w, 30);
  85   check_v16qi (v, w);
  86 }
  87
  88 void v16qi_vspltisb_neg_addself ()
  89 {
  90   v16qi v = { -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24 };
  91   vspltisb (w, -24);
  92   check_v16qi (v, w);
  93 }
  94
  95 void v16qi_vspltish ()
  96 {
  97   v16qi v = { 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15 };
  98   vspltish (w, 15);
  99   check_v16qi (v, w);
 100 }
 101
 102 void v16qi_vspltish_addself ()
 103 {
 104   v16qi v = { 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30 };
 105   vspltish (w, 30);
 106   check_v16qi (v, w);
 107 }
 108
 109 void v16qi_vspltish_neg ()
 110 {
 111   v16qi v = { -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5 };
 112   vspltish (w, -5);
 113   check_v16qi (v, w);
 114 }
 115
 116 void v16qi_vspltisw ()
 117 {
 118   v16qi v = { 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15 };
 119   vspltisw (w, 15);
 120   check_v16qi (v, w);
 121 }
 122
 123 void v16qi_vspltisw_addself ()
 124 {
 125   v16qi v = { 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30 };
 126   vspltisw (w, 30);
 127   check_v16qi (v, w);
 128 }
 129
 130 void v16qi_vspltisw_neg ()
 131 {
 132   v16qi v = { -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5 };
 133   vspltisw (w, -5);
 134   check_v16qi (v, w);
 135 }
 136
 137 \f
 138 /* V8HI tests. */
 139
 140 void v8hi_vspltisb ()
 141 {
 142   v8hi v = { 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F };
 143   vspltisb (w, 15);
 144   check_v8hi (v, w);
 145 }
 146
 147 void v8hi_vspltisb_addself ()
 148 {
 149   v8hi v = { 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E };
 150   vspltisb (w, 30);
 151   check_v8hi (v, w);
 152 }
 153
 154 void v8hi_vspltisb_neg ()
 155 {
 156   v8hi v = { 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB };
 157   vspltisb (w, -5);
 158   check_v8hi (v, w);
 159 }
 160
 161 void v8hi_vspltish ()
 162 {
 163   v8hi v = { 15, 15, 15, 15, 15, 15, 15, 15 };
 164   vspltish (w, 15);
 165   check_v8hi (v, w);
 166 }
 167
 168 void v8hi_vspltish_neg ()
 169 {
 170   v8hi v = { -5, -5, -5, -5, -5, -5, -5, -5 };
 171   vspltish (w, -5);
 172   check_v8hi (v, w);
 173 }
 174
 175 void v8hi_vspltish_addself ()
 176 {
 177   v8hi v = { 30, 30, 30, 30, 30, 30, 30, 30 };
 178   vspltish (w, 30);
 179   check_v8hi (v, w);
 180 }
 181
 182 void v8hi_vspltish_neg_addself ()
 183 {
 184   v8hi v = { -24, -24, -24, -24, -24, -24, -24, -24 };
 185   vspltish (w, -24);
 186   check_v8hi (v, w);
 187 }
 188
 189 void v8hi_vspltisw ()
 190 {
 191   v8hi v = { 0, 15, 0, 15, 0, 15, 0, 15 };
 192   vspltisw (w, 15);
 193   check_v8hi (v, w);
 194 }
 195
 196 void v8hi_vspltisw_addself ()
 197 {
 198   v8hi v = { 0, 30, 0, 30, 0, 30, 0, 30 };
 199   vspltisw (w, 30);
 200   check_v8hi (v, w);
 201 }
 202
 203 void v8hi_vspltisw_neg ()
 204 {
 205   v8hi v = { -1, -5, -1, -5, -1, -5, -1, -5 };
 206   vspltisw (w, -5);
 207   check_v8hi (v, w);
 208 }
 209
 210 /* V4SI tests. */
 211
 212 void v4si_vspltisb ()
 213 {
 214   v4si v = { 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F };
 215   vspltisb (w, 15);
 216   check_v4si (v, w);
 217 }
 218
 219 void v4si_vspltisb_addself ()
 220 {
 221   v4si v = { 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E };
 222   vspltisb (w, 30);
 223   check_v4si (v, w);
 224 }
 225
 226 void v4si_vspltisb_neg ()
 227 {
 228   v4si v = { 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB };
 229   vspltisb (w, -5);
 230   check_v4si (v, w);
 231 }
 232
 233 void v4si_vspltish ()
 234 {
 235   v4si v = { 0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F };
 236   vspltish (w, 15);
 237   check_v4si (v, w);
 238 }
 239
 240 void v4si_vspltish_addself ()
 241 {
 242   v4si v = { 0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E };
 243   vspltish (w, 30);
 244   check_v4si (v, w);
 245 }
 246
 247 void v4si_vspltish_neg ()
 248 {
 249   v4si v = { 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB };
 250   vspltish (w, -5);
 251   check_v4si (v, w);
 252 }
 253
 254 void v4si_vspltisw ()
 255 {
 256   v4si v = { 15, 15, 15, 15 };
 257   vspltisw (w, 15);
 258   check_v4si (v, w);
 259 }
 260
 261 void v4si_vspltisw_neg ()
 262 {
 263   v4si v = { -5, -5, -5, -5 };
 264   vspltisw (w, -5);
 265   check_v4si (v, w);
 266 }
 267
 268 void v4si_vspltisw_addself ()
 269 {
 270   v4si v = { 30, 30, 30, 30 };
 271   vspltisw (w, 30);
 272   check_v4si (v, w);
 273 }
 274
 275 void v4si_vspltisw_neg_addself ()
 276 {
 277   v4si v = { -24, -24, -24, -24 };
 278   vspltisw (w, -24);
 279   check_v4si (v, w);
 280 }
 281
 282 \f
 283
 284 int main ()
 285 {
 286   altivec_check ();   /* Exit if hardware doesn't support AltiVec.  */
 287
 288   v16qi_vspltisb ();
 289   v16qi_vspltisb_neg ();
 290   v16qi_vspltisb_addself ();
 291   v16qi_vspltisb_neg_addself ();
 292   v16qi_vspltish ();
 293   v16qi_vspltish_addself ();
 294   v16qi_vspltish_neg ();
 295   v16qi_vspltisw ();
 296   v16qi_vspltisw_addself ();
 297   v16qi_vspltisw_neg ();
 298
 299   v8hi_vspltisb ();
 300   v8hi_vspltisb_addself ();
 301   v8hi_vspltisb_neg ();
 302   v8hi_vspltish ();
 303   v8hi_vspltish_neg ();
 304   v8hi_vspltish_addself ();
 305   v8hi_vspltish_neg_addself ();
 306   v8hi_vspltisw ();
 307   v8hi_vspltisw_addself ();
 308   v8hi_vspltisw_neg ();
 309
 310   v4si_vspltisb ();
 311   v4si_vspltisb_addself ();
 312   v4si_vspltisb_neg ();
 313   v4si_vspltish ();
 314   v4si_vspltish_addself ();
 315   v4si_vspltish_neg ();
 316   v4si_vspltisw ();
 317   v4si_vspltisw_neg ();
 318   v4si_vspltisw_addself ();
 319   v4si_vspltisw_neg_addself ();
 320   return 0;
 321 }