| blob | 0f3e562be20a09cb45cd204947857e45d93e9533 |
1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
12 ;; version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ;; for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 ;; 02110-1301, USA.
24 ;;
25 ;; Special constraints for s/390 machine description:
26 ;;
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
45 ;;
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; O -- Multiple letter constraint followed by 1 parameter.
51 ;; s: Signed extended immediate value (-2G .. 2G-1).
52 ;; p: Positive extended immediate value (0 .. 4G-1).
53 ;; n: Negative extended immediate value (-4G .. -1).
54 ;; These constraints do not accept any operand if the machine does
55 ;; not provide the extended-immediate facility.
56 ;; P -- Any integer constant that can be loaded without literal pool.
57 ;; Q -- Memory reference without index register and with short displacement.
58 ;; R -- Memory reference with index register and short displacement.
59 ;; S -- Memory reference without index register but with long displacement.
60 ;; T -- Memory reference with index register and long displacement.
61 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
62 ;; Offsettable memory reference of type specified by second letter.
63 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
64 ;; Memory reference of the type specified by second letter that
65 ;; does *not* refer to a literal pool entry.
66 ;; U -- Pointer with short displacement.
67 ;; W -- Pointer with long displacement.
68 ;; Y -- Shift count operand.
69 ;;
70 ;; Special formats used for outputting 390 instructions.
71 ;;
72 ;; %C: print opcode suffix for branch condition.
73 ;; %D: print opcode suffix for inverse branch condition.
74 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
75 ;; %G: print the size of the operand in bytes.
76 ;; %O: print only the displacement of a memory reference.
77 ;; %R: print only the base register of a memory reference.
78 ;; %S: print S-type memory reference (base+displacement).
79 ;; %N: print the second word of a DImode operand.
80 ;; %M: print the second word of a TImode operand.
81 ;; %Y: print shift count operand.
82 ;;
83 ;; %b: print integer X as if it's an unsigned byte.
84 ;; %x: print integer X as if it's an unsigned halfword.
85 ;; %h: print integer X as if it's a signed halfword.
86 ;; %i: print the first nonzero HImode part of X.
87 ;; %j: print the first HImode part unequal to -1 of X.
88 ;; %k: print the first nonzero SImode part of X.
89 ;; %m: print the first SImode part unequal to -1 of X.
90 ;; %o: print integer X as if it's an unsigned 32bit word.
91 ;;
92 ;; We have a special constraint for pattern matching.
93 ;;
94 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
95 ;;
97 ;;
98 ;; UNSPEC usage
99 ;;
101 (define_constants
102 [; Miscellaneous
103 (UNSPEC_ROUND 1)
104 (UNSPEC_CMPINT 2)
105 (UNSPEC_ICM 10)
107 ; GOT/PLT and lt-relative accesses
108 (UNSPEC_LTREL_OFFSET 100)
109 (UNSPEC_LTREL_BASE 101)
110 (UNSPEC_GOTENT 110)
111 (UNSPEC_GOT 111)
112 (UNSPEC_GOTOFF 112)
113 (UNSPEC_PLT 113)
114 (UNSPEC_PLTOFF 114)
116 ; Literal pool
117 (UNSPEC_RELOAD_BASE 210)
118 (UNSPEC_MAIN_BASE 211)
119 (UNSPEC_LTREF 212)
120 (UNSPEC_INSN 213)
121 (UNSPEC_EXECUTE 214)
123 ; TLS relocation specifiers
124 (UNSPEC_TLSGD 500)
125 (UNSPEC_TLSLDM 501)
126 (UNSPEC_NTPOFF 502)
127 (UNSPEC_DTPOFF 503)
128 (UNSPEC_GOTNTPOFF 504)
129 (UNSPEC_INDNTPOFF 505)
131 ; TLS support
132 (UNSPEC_TLSLDM_NTPOFF 511)
133 (UNSPEC_TLS_LOAD 512)
135 ; String Functions
136 (UNSPEC_SRST 600)
137 (UNSPEC_MVST 601)
139 ; Stack Smashing Protector
140 (UNSPEC_SP_SET 700)
141 (UNSPEC_SP_TEST 701)
142 ])
144 ;;
145 ;; UNSPEC_VOLATILE usage
146 ;;
148 (define_constants
149 [; Blockage
150 (UNSPECV_BLOCKAGE 0)
152 ; TPF Support
153 (UNSPECV_TPF_PROLOGUE 20)
154 (UNSPECV_TPF_EPILOGUE 21)
156 ; Literal pool
157 (UNSPECV_POOL 200)
158 (UNSPECV_POOL_SECTION 201)
159 (UNSPECV_POOL_ALIGN 202)
160 (UNSPECV_POOL_ENTRY 203)
161 (UNSPECV_MAIN_POOL 300)
163 ; TLS support
164 (UNSPECV_SET_TP 500)
166 ; Atomic Support
167 (UNSPECV_MB 700)
168 (UNSPECV_CAS 701)
169 ])
171 ;;
172 ;; Registers
173 ;;
175 (define_constants
176 [
177 ; Sibling call register.
178 (SIBCALL_REGNUM 1)
179 ; Literal pool base register.
180 (BASE_REGNUM 13)
181 ; Return address register.
182 (RETURN_REGNUM 14)
183 ; Condition code register.
184 (CC_REGNUM 33)
185 ; Thread local storage pointer register.
186 (TP_REGNUM 36)
187 ])
190 ;; Instruction operand type as used in the Principles of Operation.
191 ;; Used to determine defaults for length and other attribute values.
193 (define_attr "op_type"
194 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
195 (const_string "NN"))
197 ;; Instruction type attribute used for scheduling.
199 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
200 cs,vs,store,sem,idiv,
201 imulhi,imulsi,imuldi,
202 branch,jsr,fsimptf,fsimpdf,fsimpsf,
203 floadtf,floaddf,floadsf,fstoredf,fstoresf,
204 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
205 ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf,
206 ftrunctf,ftruncdf,other"
207 (cond [(eq_attr "op_type" "NN") (const_string "other")
208 (eq_attr "op_type" "SS") (const_string "cs")]
209 (const_string "integer")))
211 ;; Another attribute used for scheduling purposes:
212 ;; agen: Instruction uses the address generation unit
213 ;; reg: Instruction does not use the agen unit
215 (define_attr "atype" "agen,reg"
216 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
217 (const_string "reg")
218 (const_string "agen")))
220 ;; Length in bytes.
222 (define_attr "length" ""
223 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
224 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)]
225 (const_int 6)))
228 ;; Processor type. This attribute must exactly match the processor_type
229 ;; enumeration in s390.h. The current machine description does not
230 ;; distinguish between g5 and g6, but there are differences between the two
231 ;; CPUs could in theory be modeled.
233 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
234 (const (symbol_ref "s390_tune")))
236 ;; Pipeline description for z900. For lack of anything better,
237 ;; this description is also used for the g5 and g6.
238 (include "2064.md")
240 ;; Pipeline description for z990.
241 (include "2084.md")
243 ;; Predicates
244 (include "predicates.md")
246 ;; Other includes
247 (include "tpf.md")
249 ;; Macros
251 ;; This mode macro allows floating point patterns to be generated from the
252 ;; same template.
253 (define_mode_macro FPR [TF DF SF])
254 (define_mode_macro DSF [DF SF])
256 ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
257 ;; from the same template.
258 (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
260 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
261 ;; from the same template.
262 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
263 (define_mode_macro DSI [DI SI])
265 ;; This mode macro allows :P to be used for patterns that operate on
266 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
267 (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
268 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
270 ;; This mode macro allows the QI and HI patterns to be defined from
271 ;; the same template.
272 (define_mode_macro HQI [HI QI])
274 ;; This mode macro allows the integer patterns to be defined from the
275 ;; same template.
276 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
278 ;; This macro allows to unify all 'bCOND' expander patterns.
279 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
280 ordered uneq unlt ungt unle unge ltgt])
282 ;; This macro allows to unify all 'sCOND' patterns.
283 (define_code_macro SCOND [ltu gtu leu geu])
285 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
286 ;; the same template.
287 (define_code_macro SHIFT [ashift lshiftrt])
289 ;; These macros allow to combine most atomic operations.
290 (define_code_macro ATOMIC [and ior xor plus minus mult])
291 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
292 (plus "add") (minus "sub") (mult "nand")])
295 ;; In FPR templates, a string like "lt<de>br" will expand to "ltxbr" in TFmode,
296 ;; "ltdbr" in DFmode, and "ltebr" in SFmode.
297 (define_mode_attr xde [(TF "x") (DF "d") (SF "e")])
299 ;; In FPR templates, a string like "m<dee>br" will expand to "mxbr" in TFmode,
300 ;; "mdbr" in DFmode, and "meebr" in SFmode.
301 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee")])
303 ;; In FPR templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
304 ;; Likewise for "<RXe>".
305 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
306 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
308 ;; In FPR templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
309 ;; This is used to disable the memory alternative in TFmode patterns.
310 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R")])
312 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
313 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
314 ;; version only operates on one register.
315 (define_mode_attr d0 [(DI "d") (SI "0")])
317 ;; In combination with d0 this allows to combine instructions of which the 31bit
318 ;; version only operates on one register. The DImode version needs an additional
319 ;; register for the assembler output.
320 (define_mode_attr 1 [(DI "%1,") (SI "")])
322 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
323 ;; 'ashift' and "srdl" in 'lshiftrt'.
324 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
326 ;; In SHIFT templates, this attribute holds the correct standard name for the
327 ;; pattern itself and the corresponding function calls.
328 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
330 ;; This attribute handles differences in the instruction 'type' and will result
331 ;; in "RRE" for DImode and "RR" for SImode.
332 (define_mode_attr E [(DI "E") (SI "")])
334 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
335 ;; to result in "RXY" for DImode and "RX" for SImode.
336 (define_mode_attr Y [(DI "Y") (SI "")])
338 ;; This attribute handles differences in the instruction 'type' and will result
339 ;; in "RSE" for TImode and "RS" for DImode.
340 (define_mode_attr TE [(TI "E") (DI "")])
342 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
343 ;; and "lcr" in SImode.
344 (define_mode_attr g [(DI "g") (SI "")])
346 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
347 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
348 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
349 ;; variant for long displacements.
350 (define_mode_attr y [(DI "g") (SI "y")])
352 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
353 ;; and "cds" in DImode.
354 (define_mode_attr tg [(TI "g") (DI "")])
356 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
357 ;; and "cfdbr" in SImode.
358 (define_mode_attr gf [(DI "g") (SI "f")])
360 ;; ICM mask required to load MODE value into the lowest subreg
361 ;; of a SImode register.
362 (define_mode_attr icm_lo [(HI "3") (QI "1")])
364 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
365 ;; HImode and "llgc" in QImode.
366 (define_mode_attr hc [(HI "h") (QI "c")])
368 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
369 ;; in SImode.
370 (define_mode_attr DBL [(DI "TI") (SI "DI")])
372 ;; Maximum unsigned integer that fits in MODE.
373 (define_mode_attr max_uint [(HI "65535") (QI "255")])
376 ;;
377 ;;- Compare instructions.
378 ;;
380 (define_expand "cmp<mode>"
381 [(set (reg:CC CC_REGNUM)
382 (compare:CC (match_operand:GPR 0 "register_operand" "")
383 (match_operand:GPR 1 "general_operand" "")))]
384 ""
385 {
386 s390_compare_op0 = operands[0];
387 s390_compare_op1 = operands[1];
388 DONE;
389 })
391 (define_expand "cmp<mode>"
392 [(set (reg:CC CC_REGNUM)
393 (compare:CC (match_operand:FPR 0 "register_operand" "")
394 (match_operand:FPR 1 "general_operand" "")))]
395 "TARGET_HARD_FLOAT"
396 {
397 s390_compare_op0 = operands[0];
398 s390_compare_op1 = operands[1];
399 DONE;
400 })
403 ; Test-under-Mask instructions
405 (define_insn "*tmqi_mem"
406 [(set (reg CC_REGNUM)
407 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
408 (match_operand:QI 1 "immediate_operand" "n,n"))
409 (match_operand:QI 2 "immediate_operand" "n,n")))]
410 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
411 "@
412 tm\t%S0,%b1
413 tmy\t%S0,%b1"
414 [(set_attr "op_type" "SI,SIY")])
416 (define_insn "*tmdi_reg"
417 [(set (reg CC_REGNUM)
418 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
419 (match_operand:DI 1 "immediate_operand"
420 "N0HD0,N1HD0,N2HD0,N3HD0"))
421 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
422 "TARGET_64BIT
423 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
424 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
425 "@
426 tmhh\t%0,%i1
427 tmhl\t%0,%i1
428 tmlh\t%0,%i1
429 tmll\t%0,%i1"
430 [(set_attr "op_type" "RI")])
432 (define_insn "*tmsi_reg"
433 [(set (reg CC_REGNUM)
434 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
435 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
436 (match_operand:SI 2 "immediate_operand" "n,n")))]
437 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
438 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
439 "@
440 tmh\t%0,%i1
441 tml\t%0,%i1"
442 [(set_attr "op_type" "RI")])
444 (define_insn "*tm<mode>_full"
445 [(set (reg CC_REGNUM)
446 (compare (match_operand:HQI 0 "register_operand" "d")
447 (match_operand:HQI 1 "immediate_operand" "n")))]
448 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
449 "tml\t%0,<max_uint>"
450 [(set_attr "op_type" "RI")])
453 ;
454 ; Load-and-Test instructions
455 ;
457 ; tst(di|si) intruction pattern(s).
459 (define_insn "*tstdi_sign"
460 [(set (reg CC_REGNUM)
461 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
462 (const_int 32)) (const_int 32))
463 (match_operand:DI 1 "const0_operand" "")))
464 (set (match_operand:DI 2 "register_operand" "=d")
465 (sign_extend:DI (match_dup 0)))]
466 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
467 "ltgfr\t%2,%0"
468 [(set_attr "op_type" "RRE")])
470 (define_insn "*tst<mode>_extimm"
471 [(set (reg CC_REGNUM)
472 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
473 (match_operand:GPR 1 "const0_operand" "")))
474 (set (match_operand:GPR 2 "register_operand" "=d,d")
475 (match_dup 0))]
476 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
477 "@
478 lt<g>r\t%2,%0
479 lt<g>\t%2,%0"
480 [(set_attr "op_type" "RR<E>,RXY")])
482 (define_insn "*tst<mode>_cconly_extimm"
483 [(set (reg CC_REGNUM)
484 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
485 (match_operand:GPR 1 "const0_operand" "")))
486 (clobber (match_scratch:GPR 2 "=X,d"))]
487 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
488 "@
489 lt<g>r\t%0,%0
490 lt<g>\t%2,%0"
491 [(set_attr "op_type" "RR<E>,RXY")])
493 (define_insn "*tstdi"
494 [(set (reg CC_REGNUM)
495 (compare (match_operand:DI 0 "register_operand" "d")
496 (match_operand:DI 1 "const0_operand" "")))
497 (set (match_operand:DI 2 "register_operand" "=d")
498 (match_dup 0))]
499 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
500 "ltgr\t%2,%0"
501 [(set_attr "op_type" "RRE")])
503 (define_insn "*tstsi"
504 [(set (reg CC_REGNUM)
505 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
506 (match_operand:SI 1 "const0_operand" "")))
507 (set (match_operand:SI 2 "register_operand" "=d,d,d")
508 (match_dup 0))]
509 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
510 "@
511 ltr\t%2,%0
512 icm\t%2,15,%S0
513 icmy\t%2,15,%S0"
514 [(set_attr "op_type" "RR,RS,RSY")])
516 (define_insn "*tstsi_cconly"
517 [(set (reg CC_REGNUM)
518 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
519 (match_operand:SI 1 "const0_operand" "")))
520 (clobber (match_scratch:SI 2 "=X,d,d"))]
521 "s390_match_ccmode(insn, CCSmode)"
522 "@
523 ltr\t%0,%0
524 icm\t%2,15,%S0
525 icmy\t%2,15,%S0"
526 [(set_attr "op_type" "RR,RS,RSY")])
528 (define_insn "*tstdi_cconly_31"
529 [(set (reg CC_REGNUM)
530 (compare (match_operand:DI 0 "register_operand" "d")
531 (match_operand:DI 1 "const0_operand" "")))]
532 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
533 "srda\t%0,0"
534 [(set_attr "op_type" "RS")
535 (set_attr "atype" "reg")])
537 (define_insn "*tst<mode>_cconly2"
538 [(set (reg CC_REGNUM)
539 (compare (match_operand:GPR 0 "register_operand" "d")
540 (match_operand:GPR 1 "const0_operand" "")))]
541 "s390_match_ccmode(insn, CCSmode)"
542 "lt<g>r\t%0,%0"
543 [(set_attr "op_type" "RR<E>")])
545 ; tst(hi|qi) intruction pattern(s).
547 (define_insn "*tst<mode>CCT"
548 [(set (reg CC_REGNUM)
549 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
550 (match_operand:HQI 1 "const0_operand" "")))
551 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
552 (match_dup 0))]
553 "s390_match_ccmode(insn, CCTmode)"
554 "@
555 icm\t%2,<icm_lo>,%S0
556 icmy\t%2,<icm_lo>,%S0
557 tml\t%0,<max_uint>"
558 [(set_attr "op_type" "RS,RSY,RI")])
560 (define_insn "*tsthiCCT_cconly"
561 [(set (reg CC_REGNUM)
562 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
563 (match_operand:HI 1 "const0_operand" "")))
564 (clobber (match_scratch:HI 2 "=d,d,X"))]
565 "s390_match_ccmode(insn, CCTmode)"
566 "@
567 icm\t%2,3,%S0
568 icmy\t%2,3,%S0
569 tml\t%0,65535"
570 [(set_attr "op_type" "RS,RSY,RI")])
572 (define_insn "*tstqiCCT_cconly"
573 [(set (reg CC_REGNUM)
574 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
575 (match_operand:QI 1 "const0_operand" "")))]
576 "s390_match_ccmode(insn, CCTmode)"
577 "@
578 cli\t%S0,0
579 cliy\t%S0,0
580 tml\t%0,255"
581 [(set_attr "op_type" "SI,SIY,RI")])
583 (define_insn "*tst<mode>"
584 [(set (reg CC_REGNUM)
585 (compare (match_operand:HQI 0 "s_operand" "Q,S")
586 (match_operand:HQI 1 "const0_operand" "")))
587 (set (match_operand:HQI 2 "register_operand" "=d,d")
588 (match_dup 0))]
589 "s390_match_ccmode(insn, CCSmode)"
590 "@
591 icm\t%2,<icm_lo>,%S0
592 icmy\t%2,<icm_lo>,%S0"
593 [(set_attr "op_type" "RS,RSY")])
595 (define_insn "*tst<mode>_cconly"
596 [(set (reg CC_REGNUM)
597 (compare (match_operand:HQI 0 "s_operand" "Q,S")
598 (match_operand:HQI 1 "const0_operand" "")))
599 (clobber (match_scratch:HQI 2 "=d,d"))]
600 "s390_match_ccmode(insn, CCSmode)"
601 "@
602 icm\t%2,<icm_lo>,%S0
603 icmy\t%2,<icm_lo>,%S0"
604 [(set_attr "op_type" "RS,RSY")])
607 ; Compare (equality) instructions
609 (define_insn "*cmpdi_cct"
610 [(set (reg CC_REGNUM)
611 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
612 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
613 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
614 "@
615 cgr\t%0,%1
616 cghi\t%0,%h1
617 cgfi\t%0,%1
618 cg\t%0,%1
619 #"
620 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
622 (define_insn "*cmpsi_cct"
623 [(set (reg CC_REGNUM)
624 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
625 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
626 "s390_match_ccmode (insn, CCTmode)"
627 "@
628 cr\t%0,%1
629 chi\t%0,%h1
630 cfi\t%0,%1
631 c\t%0,%1
632 cy\t%0,%1
633 #"
634 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
637 ; Compare (signed) instructions
639 (define_insn "*cmpdi_ccs_sign"
640 [(set (reg CC_REGNUM)
641 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
642 (match_operand:DI 0 "register_operand" "d,d")))]
643 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
644 "@
645 cgfr\t%0,%1
646 cgf\t%0,%1"
647 [(set_attr "op_type" "RRE,RXY")])
649 (define_insn "*cmpsi_ccs_sign"
650 [(set (reg CC_REGNUM)
651 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
652 (match_operand:SI 0 "register_operand" "d,d")))]
653 "s390_match_ccmode(insn, CCSRmode)"
654 "@
655 ch\t%0,%1
656 chy\t%0,%1"
657 [(set_attr "op_type" "RX,RXY")])
659 (define_insn "*cmp<mode>_ccs"
660 [(set (reg CC_REGNUM)
661 (compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d")
662 (match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))]
663 "s390_match_ccmode(insn, CCSmode)"
664 "@
665 c<g>r\t%0,%1
666 c<g>hi\t%0,%h1
667 c<g>fi\t%0,%1
668 c<g>\t%0,%1
669 c<y>\t%0,%1"
670 [(set_attr "op_type" "RR<E>,RI,RIL,RX<Y>,RXY")])
673 ; Compare (unsigned) instructions
675 (define_insn "*cmpdi_ccu_zero"
676 [(set (reg CC_REGNUM)
677 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
678 (match_operand:DI 0 "register_operand" "d,d")))]
679 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
680 "@
681 clgfr\t%0,%1
682 clgf\t%0,%1"
683 [(set_attr "op_type" "RRE,RXY")])
685 (define_insn "*cmpdi_ccu"
686 [(set (reg CC_REGNUM)
687 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
688 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
689 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
690 "@
691 clgr\t%0,%1
692 clgfi\t%0,%1
693 clg\t%0,%1
694 #
695 #"
696 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
698 (define_insn "*cmpsi_ccu"
699 [(set (reg CC_REGNUM)
700 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
701 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
702 "s390_match_ccmode (insn, CCUmode)"
703 "@
704 clr\t%0,%1
705 clfi\t%0,%o1
706 cl\t%0,%1
707 cly\t%0,%1
708 #
709 #"
710 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
712 (define_insn "*cmphi_ccu"
713 [(set (reg CC_REGNUM)
714 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
715 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
716 "s390_match_ccmode (insn, CCUmode)
717 && !register_operand (operands[1], HImode)"
718 "@
719 clm\t%0,3,%S1
720 clmy\t%0,3,%S1
721 #
722 #"
723 [(set_attr "op_type" "RS,RSY,SS,SS")])
725 (define_insn "*cmpqi_ccu"
726 [(set (reg CC_REGNUM)
727 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
728 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
729 "s390_match_ccmode (insn, CCUmode)
730 && !register_operand (operands[1], QImode)"
731 "@
732 clm\t%0,1,%S1
733 clmy\t%0,1,%S1
734 cli\t%S0,%b1
735 cliy\t%S0,%b1
736 #
737 #"
738 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
741 ; Block compare (CLC) instruction patterns.
743 (define_insn "*clc"
744 [(set (reg CC_REGNUM)
745 (compare (match_operand:BLK 0 "memory_operand" "Q")
746 (match_operand:BLK 1 "memory_operand" "Q")))
747 (use (match_operand 2 "const_int_operand" "n"))]
748 "s390_match_ccmode (insn, CCUmode)
749 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
750 "clc\t%O0(%2,%R0),%S1"
751 [(set_attr "op_type" "SS")])
753 (define_split
754 [(set (reg CC_REGNUM)
755 (compare (match_operand 0 "memory_operand" "")
756 (match_operand 1 "memory_operand" "")))]
757 "reload_completed
758 && s390_match_ccmode (insn, CCUmode)
759 && GET_MODE (operands[0]) == GET_MODE (operands[1])
760 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
761 [(parallel
762 [(set (match_dup 0) (match_dup 1))
763 (use (match_dup 2))])]
764 {
765 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
766 operands[0] = adjust_address (operands[0], BLKmode, 0);
767 operands[1] = adjust_address (operands[1], BLKmode, 0);
769 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
770 operands[0], operands[1]);
771 operands[0] = SET_DEST (PATTERN (curr_insn));
772 })
775 ; (DF|SF) instructions
777 (define_insn "*cmp<mode>_ccs_0"
778 [(set (reg CC_REGNUM)
779 (compare (match_operand:FPR 0 "register_operand" "f")
780 (match_operand:FPR 1 "const0_operand" "")))]
781 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
782 "lt<xde>br\t%0,%0"
783 [(set_attr "op_type" "RRE")
784 (set_attr "type" "fsimp<mode>")])
786 (define_insn "*cmp<mode>_ccs_0_ibm"
787 [(set (reg CC_REGNUM)
788 (compare (match_operand:FPR 0 "register_operand" "f")
789 (match_operand:FPR 1 "const0_operand" "")))]
790 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
791 "lt<xde>r\t%0,%0"
792 [(set_attr "op_type" "<RRe>")
793 (set_attr "type" "fsimp<mode>")])
795 (define_insn "*cmp<mode>_ccs"
796 [(set (reg CC_REGNUM)
797 (compare (match_operand:FPR 0 "register_operand" "f,f")
798 (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
799 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
800 "@
801 c<xde>br\t%0,%1
802 c<xde>b\t%0,%1"
803 [(set_attr "op_type" "RRE,RXE")
804 (set_attr "type" "fsimp<mode>")])
806 (define_insn "*cmp<mode>_ccs_ibm"
807 [(set (reg CC_REGNUM)
808 (compare (match_operand:FPR 0 "register_operand" "f,f")
809 (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
810 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
811 "@
812 c<xde>r\t%0,%1
813 c<xde>\t%0,%1"
814 [(set_attr "op_type" "<RRe>,<RXe>")
815 (set_attr "type" "fsimp<mode>")])
818 ;;
819 ;;- Move instructions.
820 ;;
822 ;
823 ; movti instruction pattern(s).
824 ;
826 (define_insn "movti"
827 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
828 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
829 "TARGET_64BIT"
830 "@
831 lmg\t%0,%N0,%S1
832 stmg\t%1,%N1,%S0
833 #
834 #
835 #"
836 [(set_attr "op_type" "RSY,RSY,*,*,SS")
837 (set_attr "type" "lm,stm,*,*,*")])
839 (define_split
840 [(set (match_operand:TI 0 "nonimmediate_operand" "")
841 (match_operand:TI 1 "general_operand" ""))]
842 "TARGET_64BIT && reload_completed
843 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
844 [(set (match_dup 2) (match_dup 4))
845 (set (match_dup 3) (match_dup 5))]
846 {
847 operands[2] = operand_subword (operands[0], 0, 0, TImode);
848 operands[3] = operand_subword (operands[0], 1, 0, TImode);
849 operands[4] = operand_subword (operands[1], 0, 0, TImode);
850 operands[5] = operand_subword (operands[1], 1, 0, TImode);
851 })
853 (define_split
854 [(set (match_operand:TI 0 "nonimmediate_operand" "")
855 (match_operand:TI 1 "general_operand" ""))]
856 "TARGET_64BIT && reload_completed
857 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
858 [(set (match_dup 2) (match_dup 4))
859 (set (match_dup 3) (match_dup 5))]
860 {
861 operands[2] = operand_subword (operands[0], 1, 0, TImode);
862 operands[3] = operand_subword (operands[0], 0, 0, TImode);
863 operands[4] = operand_subword (operands[1], 1, 0, TImode);
864 operands[5] = operand_subword (operands[1], 0, 0, TImode);
865 })
867 (define_split
868 [(set (match_operand:TI 0 "register_operand" "")
869 (match_operand:TI 1 "memory_operand" ""))]
870 "TARGET_64BIT && reload_completed
871 && !s_operand (operands[1], VOIDmode)"
872 [(set (match_dup 0) (match_dup 1))]
873 {
874 rtx addr = operand_subword (operands[0], 1, 0, TImode);
875 s390_load_address (addr, XEXP (operands[1], 0));
876 operands[1] = replace_equiv_address (operands[1], addr);
877 })
879 (define_expand "reload_outti"
880 [(parallel [(match_operand:TI 0 "" "")
881 (match_operand:TI 1 "register_operand" "d")
882 (match_operand:DI 2 "register_operand" "=&a")])]
883 "TARGET_64BIT"
884 {
885 gcc_assert (MEM_P (operands[0]));
886 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
887 operands[0] = replace_equiv_address (operands[0], operands[2]);
888 emit_move_insn (operands[0], operands[1]);
889 DONE;
890 })
892 ;
893 ; movdi instruction pattern(s).
894 ;
896 (define_expand "movdi"
897 [(set (match_operand:DI 0 "general_operand" "")
898 (match_operand:DI 1 "general_operand" ""))]
899 ""
900 {
901 /* Handle symbolic constants. */
902 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
903 emit_symbolic_move (operands);
904 })
906 (define_insn "*movdi_larl"
907 [(set (match_operand:DI 0 "register_operand" "=d")
908 (match_operand:DI 1 "larl_operand" "X"))]
909 "TARGET_64BIT
910 && !FP_REG_P (operands[0])"
911 "larl\t%0,%1"
912 [(set_attr "op_type" "RIL")
913 (set_attr "type" "larl")])
915 (define_insn "*movdi_64extimm"
916 [(set (match_operand:DI 0 "nonimmediate_operand"
917 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
918 (match_operand:DI 1 "general_operand"
919 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
920 "TARGET_64BIT && TARGET_EXTIMM"
921 "@
922 lghi\t%0,%h1
923 llihh\t%0,%i1
924 llihl\t%0,%i1
925 llilh\t%0,%i1
926 llill\t%0,%i1
927 lgfi\t%0,%1
928 llihf\t%0,%k1
929 llilf\t%0,%k1
930 lay\t%0,%a1
931 lgr\t%0,%1
932 lg\t%0,%1
933 stg\t%1,%0
934 ldr\t%0,%1
935 ld\t%0,%1
936 ldy\t%0,%1
937 std\t%1,%0
938 stdy\t%1,%0
939 #
940 #
941 stam\t%1,%N1,%S0
942 lam\t%0,%N0,%S1
943 #"
944 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
945 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
946 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
947 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
949 (define_insn "*movdi_64"
950 [(set (match_operand:DI 0 "nonimmediate_operand"
951 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
952 (match_operand:DI 1 "general_operand"
953 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
954 "TARGET_64BIT && !TARGET_EXTIMM"
955 "@
956 lghi\t%0,%h1
957 llihh\t%0,%i1
958 llihl\t%0,%i1
959 llilh\t%0,%i1
960 llill\t%0,%i1
961 lay\t%0,%a1
962 lgr\t%0,%1
963 lg\t%0,%1
964 stg\t%1,%0
965 ldr\t%0,%1
966 ld\t%0,%1
967 ldy\t%0,%1
968 std\t%1,%0
969 stdy\t%1,%0
970 #
971 #
972 stam\t%1,%N1,%S0
973 lam\t%0,%N0,%S1
974 #"
975 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
976 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
977 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
978 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
980 (define_split
981 [(set (match_operand:DI 0 "register_operand" "")
982 (match_operand:DI 1 "register_operand" ""))]
983 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
984 [(set (match_dup 2) (match_dup 3))
985 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
986 (set (strict_low_part (match_dup 2)) (match_dup 4))]
987 "operands[2] = gen_lowpart (SImode, operands[0]);
988 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
990 (define_split
991 [(set (match_operand:DI 0 "register_operand" "")
992 (match_operand:DI 1 "register_operand" ""))]
993 "TARGET_64BIT && ACCESS_REG_P (operands[0])
994 && dead_or_set_p (insn, operands[1])"
995 [(set (match_dup 3) (match_dup 2))
996 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
997 (set (match_dup 4) (match_dup 2))]
998 "operands[2] = gen_lowpart (SImode, operands[1]);
999 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1001 (define_split
1002 [(set (match_operand:DI 0 "register_operand" "")
1003 (match_operand:DI 1 "register_operand" ""))]
1004 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1005 && !dead_or_set_p (insn, operands[1])"
1006 [(set (match_dup 3) (match_dup 2))
1007 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1008 (set (match_dup 4) (match_dup 2))
1009 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1010 "operands[2] = gen_lowpart (SImode, operands[1]);
1011 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1013 (define_insn "*movdi_31"
1014 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1015 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1016 "!TARGET_64BIT"
1017 "@
1018 lm\t%0,%N0,%S1
1019 lmy\t%0,%N0,%S1
1020 stm\t%1,%N1,%S0
1021 stmy\t%1,%N1,%S0
1022 #
1023 #
1024 ldr\t%0,%1
1025 ld\t%0,%1
1026 ldy\t%0,%1
1027 std\t%1,%0
1028 stdy\t%1,%0
1029 #"
1030 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1031 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1033 (define_split
1034 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1035 (match_operand:DI 1 "general_operand" ""))]
1036 "!TARGET_64BIT && reload_completed
1037 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1038 [(set (match_dup 2) (match_dup 4))
1039 (set (match_dup 3) (match_dup 5))]
1040 {
1041 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1042 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1043 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1044 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1045 })
1047 (define_split
1048 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1049 (match_operand:DI 1 "general_operand" ""))]
1050 "!TARGET_64BIT && reload_completed
1051 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1052 [(set (match_dup 2) (match_dup 4))
1053 (set (match_dup 3) (match_dup 5))]
1054 {
1055 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1056 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1057 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1058 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1059 })
1061 (define_split
1062 [(set (match_operand:DI 0 "register_operand" "")
1063 (match_operand:DI 1 "memory_operand" ""))]
1064 "!TARGET_64BIT && reload_completed
1065 && !FP_REG_P (operands[0])
1066 && !s_operand (operands[1], VOIDmode)"
1067 [(set (match_dup 0) (match_dup 1))]
1068 {
1069 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1070 s390_load_address (addr, XEXP (operands[1], 0));
1071 operands[1] = replace_equiv_address (operands[1], addr);
1072 })
1074 (define_expand "reload_outdi"
1075 [(parallel [(match_operand:DI 0 "" "")
1076 (match_operand:DI 1 "register_operand" "d")
1077 (match_operand:SI 2 "register_operand" "=&a")])]
1078 "!TARGET_64BIT"
1079 {
1080 gcc_assert (MEM_P (operands[0]));
1081 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1082 operands[0] = replace_equiv_address (operands[0], operands[2]);
1083 emit_move_insn (operands[0], operands[1]);
1084 DONE;
1085 })
1087 (define_peephole2
1088 [(set (match_operand:DI 0 "register_operand" "")
1089 (mem:DI (match_operand 1 "address_operand" "")))]
1090 "TARGET_64BIT
1091 && !FP_REG_P (operands[0])
1092 && GET_CODE (operands[1]) == SYMBOL_REF
1093 && CONSTANT_POOL_ADDRESS_P (operands[1])
1094 && get_pool_mode (operands[1]) == DImode
1095 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1096 [(set (match_dup 0) (match_dup 2))]
1097 "operands[2] = get_pool_constant (operands[1]);")
1099 (define_insn "*la_64"
1100 [(set (match_operand:DI 0 "register_operand" "=d,d")
1101 (match_operand:QI 1 "address_operand" "U,W"))]
1102 "TARGET_64BIT"
1103 "@
1104 la\t%0,%a1
1105 lay\t%0,%a1"
1106 [(set_attr "op_type" "RX,RXY")
1107 (set_attr "type" "la")])
1109 (define_peephole2
1110 [(parallel
1111 [(set (match_operand:DI 0 "register_operand" "")
1112 (match_operand:QI 1 "address_operand" ""))
1113 (clobber (reg:CC CC_REGNUM))])]
1114 "TARGET_64BIT
1115 && preferred_la_operand_p (operands[1], const0_rtx)"
1116 [(set (match_dup 0) (match_dup 1))]
1117 "")
1119 (define_peephole2
1120 [(set (match_operand:DI 0 "register_operand" "")
1121 (match_operand:DI 1 "register_operand" ""))
1122 (parallel
1123 [(set (match_dup 0)
1124 (plus:DI (match_dup 0)
1125 (match_operand:DI 2 "nonmemory_operand" "")))
1126 (clobber (reg:CC CC_REGNUM))])]
1127 "TARGET_64BIT
1128 && !reg_overlap_mentioned_p (operands[0], operands[2])
1129 && preferred_la_operand_p (operands[1], operands[2])"
1130 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1131 "")
1133 (define_expand "reload_indi"
1134 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1135 (match_operand:DI 1 "s390_plus_operand" "")
1136 (match_operand:DI 2 "register_operand" "=&a")])]
1137 "TARGET_64BIT"
1138 {
1139 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1140 DONE;
1141 })
1143 ;
1144 ; movsi instruction pattern(s).
1145 ;
1147 (define_expand "movsi"
1148 [(set (match_operand:SI 0 "general_operand" "")
1149 (match_operand:SI 1 "general_operand" ""))]
1150 ""
1151 {
1152 /* Handle symbolic constants. */
1153 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1154 emit_symbolic_move (operands);
1155 })
1157 (define_insn "*movsi_larl"
1158 [(set (match_operand:SI 0 "register_operand" "=d")
1159 (match_operand:SI 1 "larl_operand" "X"))]
1160 "!TARGET_64BIT && TARGET_CPU_ZARCH
1161 && !FP_REG_P (operands[0])"
1162 "larl\t%0,%1"
1163 [(set_attr "op_type" "RIL")
1164 (set_attr "type" "larl")])
1166 (define_insn "*movsi_zarch"
1167 [(set (match_operand:SI 0 "nonimmediate_operand"
1168 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1169 (match_operand:SI 1 "general_operand"
1170 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1171 "TARGET_ZARCH"
1172 "@
1173 lhi\t%0,%h1
1174 llilh\t%0,%i1
1175 llill\t%0,%i1
1176 iilf\t%0,%o1
1177 lay\t%0,%a1
1178 lr\t%0,%1
1179 l\t%0,%1
1180 ly\t%0,%1
1181 st\t%1,%0
1182 sty\t%1,%0
1183 ler\t%0,%1
1184 le\t%0,%1
1185 ley\t%0,%1
1186 ste\t%1,%0
1187 stey\t%1,%0
1188 ear\t%0,%1
1189 sar\t%0,%1
1190 stam\t%1,%1,%S0
1191 lam\t%0,%0,%S1
1192 #"
1193 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1194 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1195 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1196 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1198 (define_insn "*movsi_esa"
1199 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1200 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1201 "!TARGET_ZARCH"
1202 "@
1203 lhi\t%0,%h1
1204 lr\t%0,%1
1205 l\t%0,%1
1206 st\t%1,%0
1207 ler\t%0,%1
1208 le\t%0,%1
1209 ste\t%1,%0
1210 ear\t%0,%1
1211 sar\t%0,%1
1212 stam\t%1,%1,%S0
1213 lam\t%0,%0,%S1
1214 #"
1215 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1216 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1218 (define_peephole2
1219 [(set (match_operand:SI 0 "register_operand" "")
1220 (mem:SI (match_operand 1 "address_operand" "")))]
1221 "!FP_REG_P (operands[0])
1222 && GET_CODE (operands[1]) == SYMBOL_REF
1223 && CONSTANT_POOL_ADDRESS_P (operands[1])
1224 && get_pool_mode (operands[1]) == SImode
1225 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1226 [(set (match_dup 0) (match_dup 2))]
1227 "operands[2] = get_pool_constant (operands[1]);")
1229 (define_insn "*la_31"
1230 [(set (match_operand:SI 0 "register_operand" "=d,d")
1231 (match_operand:QI 1 "address_operand" "U,W"))]
1232 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1233 "@
1234 la\t%0,%a1
1235 lay\t%0,%a1"
1236 [(set_attr "op_type" "RX,RXY")
1237 (set_attr "type" "la")])
1239 (define_peephole2
1240 [(parallel
1241 [(set (match_operand:SI 0 "register_operand" "")
1242 (match_operand:QI 1 "address_operand" ""))
1243 (clobber (reg:CC CC_REGNUM))])]
1244 "!TARGET_64BIT
1245 && preferred_la_operand_p (operands[1], const0_rtx)"
1246 [(set (match_dup 0) (match_dup 1))]
1247 "")
1249 (define_peephole2
1250 [(set (match_operand:SI 0 "register_operand" "")
1251 (match_operand:SI 1 "register_operand" ""))
1252 (parallel
1253 [(set (match_dup 0)
1254 (plus:SI (match_dup 0)
1255 (match_operand:SI 2 "nonmemory_operand" "")))
1256 (clobber (reg:CC CC_REGNUM))])]
1257 "!TARGET_64BIT
1258 && !reg_overlap_mentioned_p (operands[0], operands[2])
1259 && preferred_la_operand_p (operands[1], operands[2])"
1260 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1261 "")
1263 (define_insn "*la_31_and"
1264 [(set (match_operand:SI 0 "register_operand" "=d,d")
1265 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1266 (const_int 2147483647)))]
1267 "!TARGET_64BIT"
1268 "@
1269 la\t%0,%a1
1270 lay\t%0,%a1"
1271 [(set_attr "op_type" "RX,RXY")
1272 (set_attr "type" "la")])
1274 (define_insn_and_split "*la_31_and_cc"
1275 [(set (match_operand:SI 0 "register_operand" "=d")
1276 (and:SI (match_operand:QI 1 "address_operand" "p")
1277 (const_int 2147483647)))
1278 (clobber (reg:CC CC_REGNUM))]
1279 "!TARGET_64BIT"
1280 "#"
1281 "&& reload_completed"
1282 [(set (match_dup 0)
1283 (and:SI (match_dup 1) (const_int 2147483647)))]
1284 ""
1285 [(set_attr "op_type" "RX")
1286 (set_attr "type" "la")])
1288 (define_insn "force_la_31"
1289 [(set (match_operand:SI 0 "register_operand" "=d,d")
1290 (match_operand:QI 1 "address_operand" "U,W"))
1291 (use (const_int 0))]
1292 "!TARGET_64BIT"
1293 "@
1294 la\t%0,%a1
1295 lay\t%0,%a1"
1296 [(set_attr "op_type" "RX")
1297 (set_attr "type" "la")])
1299 (define_expand "reload_insi"
1300 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1301 (match_operand:SI 1 "s390_plus_operand" "")
1302 (match_operand:SI 2 "register_operand" "=&a")])]
1303 "!TARGET_64BIT"
1304 {
1305 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1306 DONE;
1307 })
1309 ;
1310 ; movhi instruction pattern(s).
1311 ;
1313 (define_expand "movhi"
1314 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1315 (match_operand:HI 1 "general_operand" ""))]
1316 ""
1317 {
1318 /* Make it explicit that loading a register from memory
1319 always sign-extends (at least) to SImode. */
1320 if (optimize && !no_new_pseudos
1321 && register_operand (operands[0], VOIDmode)
1322 && GET_CODE (operands[1]) == MEM)
1323 {
1324 rtx tmp = gen_reg_rtx (SImode);
1325 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1326 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1327 operands[1] = gen_lowpart (HImode, tmp);
1328 }
1329 })
1331 (define_insn "*movhi"
1332 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1333 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1334 ""
1335 "@
1336 lr\t%0,%1
1337 lhi\t%0,%h1
1338 lh\t%0,%1
1339 lhy\t%0,%1
1340 sth\t%1,%0
1341 sthy\t%1,%0
1342 #"
1343 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1344 (set_attr "type" "lr,*,*,*,store,store,*")])
1346 (define_peephole2
1347 [(set (match_operand:HI 0 "register_operand" "")
1348 (mem:HI (match_operand 1 "address_operand" "")))]
1349 "GET_CODE (operands[1]) == SYMBOL_REF
1350 && CONSTANT_POOL_ADDRESS_P (operands[1])
1351 && get_pool_mode (operands[1]) == HImode
1352 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1353 [(set (match_dup 0) (match_dup 2))]
1354 "operands[2] = get_pool_constant (operands[1]);")
1356 ;
1357 ; movqi instruction pattern(s).
1358 ;
1360 (define_expand "movqi"
1361 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1362 (match_operand:QI 1 "general_operand" ""))]
1363 ""
1364 {
1365 /* On z/Architecture, zero-extending from memory to register
1366 is just as fast as a QImode load. */
1367 if (TARGET_ZARCH && optimize && !no_new_pseudos
1368 && register_operand (operands[0], VOIDmode)
1369 && GET_CODE (operands[1]) == MEM)
1370 {
1371 rtx tmp = gen_reg_rtx (word_mode);
1372 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1373 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1374 operands[1] = gen_lowpart (QImode, tmp);
1375 }
1376 })
1378 (define_insn "*movqi"
1379 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1380 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1381 ""
1382 "@
1383 lr\t%0,%1
1384 lhi\t%0,%b1
1385 ic\t%0,%1
1386 icy\t%0,%1
1387 stc\t%1,%0
1388 stcy\t%1,%0
1389 mvi\t%S0,%b1
1390 mviy\t%S0,%b1
1391 #"
1392 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1393 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1395 (define_peephole2
1396 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1397 (mem:QI (match_operand 1 "address_operand" "")))]
1398 "GET_CODE (operands[1]) == SYMBOL_REF
1399 && CONSTANT_POOL_ADDRESS_P (operands[1])
1400 && get_pool_mode (operands[1]) == QImode
1401 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1402 [(set (match_dup 0) (match_dup 2))]
1403 "operands[2] = get_pool_constant (operands[1]);")
1405 ;
1406 ; movstrictqi instruction pattern(s).
1407 ;
1409 (define_insn "*movstrictqi"
1410 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1411 (match_operand:QI 1 "memory_operand" "R,T"))]
1412 ""
1413 "@
1414 ic\t%0,%1
1415 icy\t%0,%1"
1416 [(set_attr "op_type" "RX,RXY")])
1418 ;
1419 ; movstricthi instruction pattern(s).
1420 ;
1422 (define_insn "*movstricthi"
1423 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1424 (match_operand:HI 1 "memory_operand" "Q,S"))
1425 (clobber (reg:CC CC_REGNUM))]
1426 ""
1427 "@
1428 icm\t%0,3,%S1
1429 icmy\t%0,3,%S1"
1430 [(set_attr "op_type" "RS,RSY")])
1432 ;
1433 ; movstrictsi instruction pattern(s).
1434 ;
1436 (define_insn "movstrictsi"
1437 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1438 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1439 "TARGET_64BIT"
1440 "@
1441 lr\t%0,%1
1442 l\t%0,%1
1443 ly\t%0,%1
1444 ear\t%0,%1"
1445 [(set_attr "op_type" "RR,RX,RXY,RRE")
1446 (set_attr "type" "lr,load,load,*")])
1448 ;
1449 ; movtf instruction pattern(s).
1450 ;
1452 (define_expand "movtf"
1453 [(set (match_operand:TF 0 "nonimmediate_operand" "")
1454 (match_operand:TF 1 "general_operand" ""))]
1455 ""
1456 "")
1458 (define_insn "*movtf_64"
1459 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,d,QS,d,o,Q")
1460 (match_operand:TF 1 "general_operand" "G,f,o,f,QS,d,dm,d,Q"))]
1461 "TARGET_64BIT"
1462 "@
1463 lzxr\t%0
1464 lxr\t%0,%1
1465 #
1466 #
1467 lmg\t%0,%N0,%S1
1468 stmg\t%1,%N1,%S0
1469 #
1470 #
1471 #"
1472 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*")
1473 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*,*")])
1475 (define_insn "*movtf_31"
1476 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,Q")
1477 (match_operand:TF 1 "general_operand" "G,f,o,f,Q"))]
1478 "!TARGET_64BIT"
1479 "@
1480 lzxr\t%0
1481 lxr\t%0,%1
1482 #
1483 #
1484 #"
1485 [(set_attr "op_type" "RRE,RRE,*,*,*")
1486 (set_attr "type" "fsimptf,fsimptf,*,*,*")])
1488 ; TFmode in GPRs splitters
1490 (define_split
1491 [(set (match_operand:TF 0 "nonimmediate_operand" "")
1492 (match_operand:TF 1 "general_operand" ""))]
1493 "TARGET_64BIT && reload_completed
1494 && s390_split_ok_p (operands[0], operands[1], TFmode, 0)"
1495 [(set (match_dup 2) (match_dup 4))
1496 (set (match_dup 3) (match_dup 5))]
1497 {
1498 operands[2] = operand_subword (operands[0], 0, 0, TFmode);
1499 operands[3] = operand_subword (operands[0], 1, 0, TFmode);
1500 operands[4] = operand_subword (operands[1], 0, 0, TFmode);
1501 operands[5] = operand_subword (operands[1], 1, 0, TFmode);
1502 })
1504 (define_split
1505 [(set (match_operand:TF 0 "nonimmediate_operand" "")
1506 (match_operand:TF 1 "general_operand" ""))]
1507 "TARGET_64BIT && reload_completed
1508 && s390_split_ok_p (operands[0], operands[1], TFmode, 1)"
1509 [(set (match_dup 2) (match_dup 4))
1510 (set (match_dup 3) (match_dup 5))]
1511 {
1512 operands[2] = operand_subword (operands[0], 1, 0, TFmode);
1513 operands[3] = operand_subword (operands[0], 0, 0, TFmode);
1514 operands[4] = operand_subword (operands[1], 1, 0, TFmode);
1515 operands[5] = operand_subword (operands[1], 0, 0, TFmode);
1516 })
1518 (define_split
1519 [(set (match_operand:TF 0 "register_operand" "")
1520 (match_operand:TF 1 "memory_operand" ""))]
1521 "TARGET_64BIT && reload_completed
1522 && !FP_REG_P (operands[0])
1523 && !s_operand (operands[1], VOIDmode)"
1524 [(set (match_dup 0) (match_dup 1))]
1525 {
1526 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1527 s390_load_address (addr, XEXP (operands[1], 0));
1528 operands[1] = replace_equiv_address (operands[1], addr);
1529 })
1531 ; TFmode in FPRs splitters
1533 (define_split
1534 [(set (match_operand:TF 0 "register_operand" "")
1535 (match_operand:TF 1 "memory_operand" ""))]
1536 "reload_completed && offsettable_memref_p (operands[1])
1537 && FP_REG_P (operands[0])"
1538 [(set (match_dup 2) (match_dup 4))
1539 (set (match_dup 3) (match_dup 5))]
1540 {
1541 operands[2] = simplify_gen_subreg (DFmode, operands[0], TFmode, 0);
1542 operands[3] = simplify_gen_subreg (DFmode, operands[0], TFmode, 8);
1543 operands[4] = adjust_address_nv (operands[1], DFmode, 0);
1544 operands[5] = adjust_address_nv (operands[1], DFmode, 8);
1545 })
1547 (define_split
1548 [(set (match_operand:TF 0 "memory_operand" "")
1549 (match_operand:TF 1 "register_operand" ""))]
1550 "reload_completed && offsettable_memref_p (operands[0])
1551 && FP_REG_P (operands[1])"
1552 [(set (match_dup 2) (match_dup 4))
1553 (set (match_dup 3) (match_dup 5))]
1554 {
1555 operands[2] = adjust_address_nv (operands[0], DFmode, 0);
1556 operands[3] = adjust_address_nv (operands[0], DFmode, 8);
1557 operands[4] = simplify_gen_subreg (DFmode, operands[1], TFmode, 0);
1558 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, 8);
1559 })
1561 (define_expand "reload_outtf"
1562 [(parallel [(match_operand:TF 0 "" "")
1563 (match_operand:TF 1 "register_operand" "f")
1564 (match_operand:SI 2 "register_operand" "=&a")])]
1565 ""
1566 {
1567 rtx addr = gen_lowpart (Pmode, operands[2]);
1569 gcc_assert (MEM_P (operands[0]));
1570 s390_load_address (addr, find_replacement (&XEXP (operands[0], 0)));
1571 operands[0] = replace_equiv_address (operands[0], addr);
1572 emit_move_insn (operands[0], operands[1]);
1573 DONE;
1574 })
1576 (define_expand "reload_intf"
1577 [(parallel [(match_operand:TF 0 "register_operand" "=f")
1578 (match_operand:TF 1 "" "")
1579 (match_operand:SI 2 "register_operand" "=&a")])]
1580 ""
1581 {
1582 rtx addr = gen_lowpart (Pmode, operands[2]);
1584 gcc_assert (MEM_P (operands[1]));
1585 s390_load_address (addr, find_replacement (&XEXP (operands[1], 0)));
1586 operands[1] = replace_equiv_address (operands[1], addr);
1587 emit_move_insn (operands[0], operands[1]);
1588 DONE;
1589 })
1591 ;
1592 ; movdf instruction pattern(s).
1593 ;
1595 (define_expand "movdf"
1596 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1597 (match_operand:DF 1 "general_operand" ""))]
1598 ""
1599 "")
1601 (define_insn "*movdf_64"
1602 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1603 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1604 "TARGET_64BIT"
1605 "@
1606 lzdr\t%0
1607 ldr\t%0,%1
1608 ld\t%0,%1
1609 ldy\t%0,%1
1610 std\t%1,%0
1611 stdy\t%1,%0
1612 lgr\t%0,%1
1613 lg\t%0,%1
1614 stg\t%1,%0
1615 #"
1616 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1617 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1619 (define_insn "*movdf_31"
1620 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1621 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1622 "!TARGET_64BIT"
1623 "@
1624 lzdr\t%0
1625 ldr\t%0,%1
1626 ld\t%0,%1
1627 ldy\t%0,%1
1628 std\t%1,%0
1629 stdy\t%1,%0
1630 lm\t%0,%N0,%S1
1631 lmy\t%0,%N0,%S1
1632 stm\t%1,%N1,%S0
1633 stmy\t%1,%N1,%S0
1634 #
1635 #
1636 #"
1637 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1638 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1639 lm,lm,stm,stm,*,*,*")])
1641 (define_split
1642 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1643 (match_operand:DF 1 "general_operand" ""))]
1644 "!TARGET_64BIT && reload_completed
1645 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1646 [(set (match_dup 2) (match_dup 4))
1647 (set (match_dup 3) (match_dup 5))]
1648 {
1649 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1650 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1651 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1652 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1653 })
1655 (define_split
1656 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1657 (match_operand:DF 1 "general_operand" ""))]
1658 "!TARGET_64BIT && reload_completed
1659 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1660 [(set (match_dup 2) (match_dup 4))
1661 (set (match_dup 3) (match_dup 5))]
1662 {
1663 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1664 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1665 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1666 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1667 })
1669 (define_split
1670 [(set (match_operand:DF 0 "register_operand" "")
1671 (match_operand:DF 1 "memory_operand" ""))]
1672 "!TARGET_64BIT && reload_completed
1673 && !FP_REG_P (operands[0])
1674 && !s_operand (operands[1], VOIDmode)"
1675 [(set (match_dup 0) (match_dup 1))]
1676 {
1677 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1678 s390_load_address (addr, XEXP (operands[1], 0));
1679 operands[1] = replace_equiv_address (operands[1], addr);
1680 })
1682 (define_expand "reload_outdf"
1683 [(parallel [(match_operand:DF 0 "" "")
1684 (match_operand:DF 1 "register_operand" "d")
1685 (match_operand:SI 2 "register_operand" "=&a")])]
1686 "!TARGET_64BIT"
1687 {
1688 gcc_assert (MEM_P (operands[0]));
1689 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1690 operands[0] = replace_equiv_address (operands[0], operands[2]);
1691 emit_move_insn (operands[0], operands[1]);
1692 DONE;
1693 })
1695 ;
1696 ; movsf instruction pattern(s).
1697 ;
1699 (define_insn "movsf"
1700 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1701 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1702 ""
1703 "@
1704 lzer\t%0
1705 ler\t%0,%1
1706 le\t%0,%1
1707 ley\t%0,%1
1708 ste\t%1,%0
1709 stey\t%1,%0
1710 lr\t%0,%1
1711 l\t%0,%1
1712 ly\t%0,%1
1713 st\t%1,%0
1714 sty\t%1,%0
1715 #"
1716 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1717 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1718 lr,load,load,store,store,*")])
1720 ;
1721 ; movcc instruction pattern
1722 ;
1724 (define_insn "movcc"
1725 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1726 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1727 ""
1728 "@
1729 lr\t%0,%1
1730 tmh\t%1,12288
1731 ipm\t%0
1732 st\t%0,%1
1733 sty\t%0,%1
1734 l\t%1,%0
1735 ly\t%1,%0"
1736 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1737 (set_attr "type" "lr,*,*,store,store,load,load")])
1739 ;
1740 ; Block move (MVC) patterns.
1741 ;
1743 (define_insn "*mvc"
1744 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1745 (match_operand:BLK 1 "memory_operand" "Q"))
1746 (use (match_operand 2 "const_int_operand" "n"))]
1747 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1748 "mvc\t%O0(%2,%R0),%S1"
1749 [(set_attr "op_type" "SS")])
1751 (define_split
1752 [(set (match_operand 0 "memory_operand" "")
1753 (match_operand 1 "memory_operand" ""))]
1754 "reload_completed
1755 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1756 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1757 [(parallel
1758 [(set (match_dup 0) (match_dup 1))
1759 (use (match_dup 2))])]
1760 {
1761 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1762 operands[0] = adjust_address (operands[0], BLKmode, 0);
1763 operands[1] = adjust_address (operands[1], BLKmode, 0);
1764 })
1766 (define_peephole2
1767 [(parallel
1768 [(set (match_operand:BLK 0 "memory_operand" "")
1769 (match_operand:BLK 1 "memory_operand" ""))
1770 (use (match_operand 2 "const_int_operand" ""))])
1771 (parallel
1772 [(set (match_operand:BLK 3 "memory_operand" "")
1773 (match_operand:BLK 4 "memory_operand" ""))
1774 (use (match_operand 5 "const_int_operand" ""))])]
1775 "s390_offset_p (operands[0], operands[3], operands[2])
1776 && s390_offset_p (operands[1], operands[4], operands[2])
1777 && !s390_overlap_p (operands[0], operands[1],
1778 INTVAL (operands[2]) + INTVAL (operands[5]))
1779 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1780 [(parallel
1781 [(set (match_dup 6) (match_dup 7))
1782 (use (match_dup 8))])]
1783 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1784 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1785 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1788 ;
1789 ; load_multiple pattern(s).
1790 ;
1791 ; ??? Due to reload problems with replacing registers inside match_parallel
1792 ; we currently support load_multiple/store_multiple only after reload.
1793 ;
1795 (define_expand "load_multiple"
1796 [(match_par_dup 3 [(set (match_operand 0 "" "")
1797 (match_operand 1 "" ""))
1798 (use (match_operand 2 "" ""))])]
1799 "reload_completed"
1800 {
1801 enum machine_mode mode;
1802 int regno;
1803 int count;
1804 rtx from;
1805 int i, off;
1807 /* Support only loading a constant number of fixed-point registers from
1808 memory and only bother with this if more than two */
1809 if (GET_CODE (operands[2]) != CONST_INT
1810 || INTVAL (operands[2]) < 2
1811 || INTVAL (operands[2]) > 16
1812 || GET_CODE (operands[1]) != MEM
1813 || GET_CODE (operands[0]) != REG
1814 || REGNO (operands[0]) >= 16)
1815 FAIL;
1817 count = INTVAL (operands[2]);
1818 regno = REGNO (operands[0]);
1819 mode = GET_MODE (operands[0]);
1820 if (mode != SImode && mode != word_mode)
1821 FAIL;
1823 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1824 if (no_new_pseudos)
1825 {
1826 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1827 {
1828 from = XEXP (operands[1], 0);
1829 off = 0;
1830 }
1831 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1832 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1833 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1834 {
1835 from = XEXP (XEXP (operands[1], 0), 0);
1836 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1837 }
1838 else
1839 FAIL;
1840 }
1841 else
1842 {
1843 from = force_reg (Pmode, XEXP (operands[1], 0));
1844 off = 0;
1845 }
1847 for (i = 0; i < count; i++)
1848 XVECEXP (operands[3], 0, i)
1849 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1850 change_address (operands[1], mode,
1851 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1852 })
1854 (define_insn "*load_multiple_di"
1855 [(match_parallel 0 "load_multiple_operation"
1856 [(set (match_operand:DI 1 "register_operand" "=r")
1857 (match_operand:DI 2 "s_operand" "QS"))])]
1858 "reload_completed && word_mode == DImode"
1859 {
1860 int words = XVECLEN (operands[0], 0);
1861 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1862 return "lmg\t%1,%0,%S2";
1863 }
1864 [(set_attr "op_type" "RSY")
1865 (set_attr "type" "lm")])
1867 (define_insn "*load_multiple_si"
1868 [(match_parallel 0 "load_multiple_operation"
1869 [(set (match_operand:SI 1 "register_operand" "=r,r")
1870 (match_operand:SI 2 "s_operand" "Q,S"))])]
1871 "reload_completed"
1872 {
1873 int words = XVECLEN (operands[0], 0);
1874 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1875 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1876 }
1877 [(set_attr "op_type" "RS,RSY")
1878 (set_attr "type" "lm")])
1880 ;
1881 ; store multiple pattern(s).
1882 ;
1884 (define_expand "store_multiple"
1885 [(match_par_dup 3 [(set (match_operand 0 "" "")
1886 (match_operand 1 "" ""))
1887 (use (match_operand 2 "" ""))])]
1888 "reload_completed"
1889 {
1890 enum machine_mode mode;
1891 int regno;
1892 int count;
1893 rtx to;
1894 int i, off;
1896 /* Support only storing a constant number of fixed-point registers to
1897 memory and only bother with this if more than two. */
1898 if (GET_CODE (operands[2]) != CONST_INT
1899 || INTVAL (operands[2]) < 2
1900 || INTVAL (operands[2]) > 16
1901 || GET_CODE (operands[0]) != MEM
1902 || GET_CODE (operands[1]) != REG
1903 || REGNO (operands[1]) >= 16)
1904 FAIL;
1906 count = INTVAL (operands[2]);
1907 regno = REGNO (operands[1]);
1908 mode = GET_MODE (operands[1]);
1909 if (mode != SImode && mode != word_mode)
1910 FAIL;
1912 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1914 if (no_new_pseudos)
1915 {
1916 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1917 {
1918 to = XEXP (operands[0], 0);
1919 off = 0;
1920 }
1921 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1922 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1923 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1924 {
1925 to = XEXP (XEXP (operands[0], 0), 0);
1926 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1927 }
1928 else
1929 FAIL;
1930 }
1931 else
1932 {
1933 to = force_reg (Pmode, XEXP (operands[0], 0));
1934 off = 0;
1935 }
1937 for (i = 0; i < count; i++)
1938 XVECEXP (operands[3], 0, i)
1939 = gen_rtx_SET (VOIDmode,
1940 change_address (operands[0], mode,
1941 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1942 gen_rtx_REG (mode, regno + i));
1943 })
1945 (define_insn "*store_multiple_di"
1946 [(match_parallel 0 "store_multiple_operation"
1947 [(set (match_operand:DI 1 "s_operand" "=QS")
1948 (match_operand:DI 2 "register_operand" "r"))])]
1949 "reload_completed && word_mode == DImode"
1950 {
1951 int words = XVECLEN (operands[0], 0);
1952 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1953 return "stmg\t%2,%0,%S1";
1954 }
1955 [(set_attr "op_type" "RSY")
1956 (set_attr "type" "stm")])
1959 (define_insn "*store_multiple_si"
1960 [(match_parallel 0 "store_multiple_operation"
1961 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1962 (match_operand:SI 2 "register_operand" "r,r"))])]
1963 "reload_completed"
1964 {
1965 int words = XVECLEN (operands[0], 0);
1966 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1967 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1968 }
1969 [(set_attr "op_type" "RS,RSY")
1970 (set_attr "type" "stm")])
1972 ;;
1973 ;; String instructions.
1974 ;;
1976 (define_insn "*execute"
1977 [(match_parallel 0 ""
1978 [(unspec [(match_operand 1 "register_operand" "a")
1979 (match_operand:BLK 2 "memory_operand" "R")
1980 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1981 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1982 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1983 "ex\t%1,%2"
1984 [(set_attr "op_type" "RX")
1985 (set_attr "type" "cs")])
1988 ;
1989 ; strlenM instruction pattern(s).
1990 ;
1992 (define_expand "strlen<mode>"
1993 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1994 (parallel
1995 [(set (match_dup 4)
1996 (unspec:P [(const_int 0)
1997 (match_operand:BLK 1 "memory_operand" "")
1998 (reg:SI 0)
1999 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2000 (clobber (scratch:P))
2001 (clobber (reg:CC CC_REGNUM))])
2002 (parallel
2003 [(set (match_operand:P 0 "register_operand" "")
2004 (minus:P (match_dup 4) (match_dup 5)))
2005 (clobber (reg:CC CC_REGNUM))])]
2006 ""
2007 {
2008 operands[4] = gen_reg_rtx (Pmode);
2009 operands[5] = gen_reg_rtx (Pmode);
2010 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2011 operands[1] = replace_equiv_address (operands[1], operands[5]);
2012 })
2014 (define_insn "*strlen<mode>"
2015 [(set (match_operand:P 0 "register_operand" "=a")
2016 (unspec:P [(match_operand:P 2 "general_operand" "0")
2017 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2018 (reg:SI 0)
2019 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2020 (clobber (match_scratch:P 1 "=a"))
2021 (clobber (reg:CC CC_REGNUM))]
2022 ""
2023 "srst\t%0,%1\;jo\t.-4"
2024 [(set_attr "length" "8")
2025 (set_attr "type" "vs")])
2027 ;
2028 ; cmpstrM instruction pattern(s).
2029 ;
2031 (define_expand "cmpstrsi"
2032 [(set (reg:SI 0) (const_int 0))
2033 (parallel
2034 [(clobber (match_operand 3 "" ""))
2035 (clobber (match_dup 4))
2036 (set (reg:CCU CC_REGNUM)
2037 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2038 (match_operand:BLK 2 "memory_operand" "")))
2039 (use (reg:SI 0))])
2040 (parallel
2041 [(set (match_operand:SI 0 "register_operand" "=d")
2042 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
2043 (clobber (reg:CC CC_REGNUM))])]
2044 ""
2045 {
2046 /* As the result of CMPINT is inverted compared to what we need,
2047 we have to swap the operands. */
2048 rtx op1 = operands[2];
2049 rtx op2 = operands[1];
2050 rtx addr1 = gen_reg_rtx (Pmode);
2051 rtx addr2 = gen_reg_rtx (Pmode);
2053 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2054 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2055 operands[1] = replace_equiv_address_nv (op1, addr1);
2056 operands[2] = replace_equiv_address_nv (op2, addr2);
2057 operands[3] = addr1;
2058 operands[4] = addr2;
2059 })
2061 (define_insn "*cmpstr<mode>"
2062 [(clobber (match_operand:P 0 "register_operand" "=d"))
2063 (clobber (match_operand:P 1 "register_operand" "=d"))
2064 (set (reg:CCU CC_REGNUM)
2065 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2066 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2067 (use (reg:SI 0))]
2068 ""
2069 "clst\t%0,%1\;jo\t.-4"
2070 [(set_attr "length" "8")
2071 (set_attr "type" "vs")])
2073 ;
2074 ; movstr instruction pattern.
2075 ;
2077 (define_expand "movstr"
2078 [(set (reg:SI 0) (const_int 0))
2079 (parallel
2080 [(clobber (match_dup 3))
2081 (set (match_operand:BLK 1 "memory_operand" "")
2082 (match_operand:BLK 2 "memory_operand" ""))
2083 (set (match_operand 0 "register_operand" "")
2084 (unspec [(match_dup 1)
2085 (match_dup 2)
2086 (reg:SI 0)] UNSPEC_MVST))
2087 (clobber (reg:CC CC_REGNUM))])]
2088 ""
2089 {
2090 rtx addr1 = gen_reg_rtx (Pmode);
2091 rtx addr2 = gen_reg_rtx (Pmode);
2093 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2094 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2095 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2096 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2097 operands[3] = addr2;
2098 })
2100 (define_insn "*movstr"
2101 [(clobber (match_operand:P 2 "register_operand" "=d"))
2102 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2103 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2104 (set (match_operand:P 0 "register_operand" "=d")
2105 (unspec [(mem:BLK (match_dup 1))
2106 (mem:BLK (match_dup 3))
2107 (reg:SI 0)] UNSPEC_MVST))
2108 (clobber (reg:CC CC_REGNUM))]
2109 ""
2110 "mvst\t%1,%2\;jo\t.-4"
2111 [(set_attr "length" "8")
2112 (set_attr "type" "vs")])
2115 ;
2116 ; movmemM instruction pattern(s).
2117 ;
2119 (define_expand "movmem<mode>"
2120 [(set (match_operand:BLK 0 "memory_operand" "")
2121 (match_operand:BLK 1 "memory_operand" ""))
2122 (use (match_operand:GPR 2 "general_operand" ""))
2123 (match_operand 3 "" "")]
2124 ""
2125 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2127 ; Move a block that is up to 256 bytes in length.
2128 ; The block length is taken as (operands[2] % 256) + 1.
2130 (define_expand "movmem_short"
2131 [(parallel
2132 [(set (match_operand:BLK 0 "memory_operand" "")
2133 (match_operand:BLK 1 "memory_operand" ""))
2134 (use (match_operand 2 "nonmemory_operand" ""))
2135 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2136 (clobber (match_dup 3))])]
2137 ""
2138 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2140 (define_insn "*movmem_short"
2141 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2142 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
2143 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2144 (use (match_operand 3 "immediate_operand" "X,R,X"))
2145 (clobber (match_scratch 4 "=X,X,&a"))]
2146 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2147 && GET_MODE (operands[4]) == Pmode"
2148 "#"
2149 [(set_attr "type" "cs")])
2151 (define_split
2152 [(set (match_operand:BLK 0 "memory_operand" "")
2153 (match_operand:BLK 1 "memory_operand" ""))
2154 (use (match_operand 2 "const_int_operand" ""))
2155 (use (match_operand 3 "immediate_operand" ""))
2156 (clobber (scratch))]
2157 "reload_completed"
2158 [(parallel
2159 [(set (match_dup 0) (match_dup 1))
2160 (use (match_dup 2))])]
2161 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2163 (define_split
2164 [(set (match_operand:BLK 0 "memory_operand" "")
2165 (match_operand:BLK 1 "memory_operand" ""))
2166 (use (match_operand 2 "register_operand" ""))
2167 (use (match_operand 3 "memory_operand" ""))
2168 (clobber (scratch))]
2169 "reload_completed"
2170 [(parallel
2171 [(unspec [(match_dup 2) (match_dup 3)
2172 (const_int 0)] UNSPEC_EXECUTE)
2173 (set (match_dup 0) (match_dup 1))
2174 (use (const_int 1))])]
2175 "")
2177 (define_split
2178 [(set (match_operand:BLK 0 "memory_operand" "")
2179 (match_operand:BLK 1 "memory_operand" ""))
2180 (use (match_operand 2 "register_operand" ""))
2181 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2182 (clobber (match_operand 3 "register_operand" ""))]
2183 "reload_completed && TARGET_CPU_ZARCH"
2184 [(set (match_dup 3) (label_ref (match_dup 4)))
2185 (parallel
2186 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2187 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2188 (set (match_dup 0) (match_dup 1))
2189 (use (const_int 1))])]
2190 "operands[4] = gen_label_rtx ();")
2192 ; Move a block of arbitrary length.
2194 (define_expand "movmem_long"
2195 [(parallel
2196 [(clobber (match_dup 2))
2197 (clobber (match_dup 3))
2198 (set (match_operand:BLK 0 "memory_operand" "")
2199 (match_operand:BLK 1 "memory_operand" ""))
2200 (use (match_operand 2 "general_operand" ""))
2201 (use (match_dup 3))
2202 (clobber (reg:CC CC_REGNUM))])]
2203 ""
2204 {
2205 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2206 rtx reg0 = gen_reg_rtx (dword_mode);
2207 rtx reg1 = gen_reg_rtx (dword_mode);
2208 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2209 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2210 rtx len0 = gen_lowpart (Pmode, reg0);
2211 rtx len1 = gen_lowpart (Pmode, reg1);
2213 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2214 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2215 emit_move_insn (len0, operands[2]);
2217 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2218 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2219 emit_move_insn (len1, operands[2]);
2221 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2222 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2223 operands[2] = reg0;
2224 operands[3] = reg1;
2225 })
2227 (define_insn "*movmem_long"
2228 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2229 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2230 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2231 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2232 (use (match_dup 2))
2233 (use (match_dup 3))
2234 (clobber (reg:CC CC_REGNUM))]
2235 ""
2236 "mvcle\t%0,%1,0\;jo\t.-4"
2237 [(set_attr "length" "8")
2238 (set_attr "type" "vs")])
2240 ;
2241 ; setmemM instruction pattern(s).
2242 ;
2244 (define_expand "setmem<mode>"
2245 [(set (match_operand:BLK 0 "memory_operand" "")
2246 (match_operand:QI 2 "general_operand" ""))
2247 (use (match_operand:GPR 1 "general_operand" ""))
2248 (match_operand 3 "" "")]
2249 ""
2250 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2252 ; Clear a block that is up to 256 bytes in length.
2253 ; The block length is taken as (operands[1] % 256) + 1.
2255 (define_expand "clrmem_short"
2256 [(parallel
2257 [(set (match_operand:BLK 0 "memory_operand" "")
2258 (const_int 0))
2259 (use (match_operand 1 "nonmemory_operand" ""))
2260 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2261 (clobber (match_dup 2))
2262 (clobber (reg:CC CC_REGNUM))])]
2263 ""
2264 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2266 (define_insn "*clrmem_short"
2267 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2268 (const_int 0))
2269 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2270 (use (match_operand 2 "immediate_operand" "X,R,X"))
2271 (clobber (match_scratch 3 "=X,X,&a"))
2272 (clobber (reg:CC CC_REGNUM))]
2273 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2274 && GET_MODE (operands[3]) == Pmode"
2275 "#"
2276 [(set_attr "type" "cs")])
2278 (define_split
2279 [(set (match_operand:BLK 0 "memory_operand" "")
2280 (const_int 0))
2281 (use (match_operand 1 "const_int_operand" ""))
2282 (use (match_operand 2 "immediate_operand" ""))
2283 (clobber (scratch))
2284 (clobber (reg:CC CC_REGNUM))]
2285 "reload_completed"
2286 [(parallel
2287 [(set (match_dup 0) (const_int 0))
2288 (use (match_dup 1))
2289 (clobber (reg:CC CC_REGNUM))])]
2290 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2292 (define_split
2293 [(set (match_operand:BLK 0 "memory_operand" "")
2294 (const_int 0))
2295 (use (match_operand 1 "register_operand" ""))
2296 (use (match_operand 2 "memory_operand" ""))
2297 (clobber (scratch))
2298 (clobber (reg:CC CC_REGNUM))]
2299 "reload_completed"
2300 [(parallel
2301 [(unspec [(match_dup 1) (match_dup 2)
2302 (const_int 0)] UNSPEC_EXECUTE)
2303 (set (match_dup 0) (const_int 0))
2304 (use (const_int 1))
2305 (clobber (reg:CC CC_REGNUM))])]
2306 "")
2308 (define_split
2309 [(set (match_operand:BLK 0 "memory_operand" "")
2310 (const_int 0))
2311 (use (match_operand 1 "register_operand" ""))
2312 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2313 (clobber (match_operand 2 "register_operand" ""))
2314 (clobber (reg:CC CC_REGNUM))]
2315 "reload_completed && TARGET_CPU_ZARCH"
2316 [(set (match_dup 2) (label_ref (match_dup 3)))
2317 (parallel
2318 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2319 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2320 (set (match_dup 0) (const_int 0))
2321 (use (const_int 1))
2322 (clobber (reg:CC CC_REGNUM))])]
2323 "operands[3] = gen_label_rtx ();")
2325 ; Initialize a block of arbitrary length with (operands[2] % 256).
2327 (define_expand "setmem_long"
2328 [(parallel
2329 [(clobber (match_dup 1))
2330 (set (match_operand:BLK 0 "memory_operand" "")
2331 (match_operand 2 "shift_count_or_setmem_operand" ""))
2332 (use (match_operand 1 "general_operand" ""))
2333 (use (match_dup 3))
2334 (clobber (reg:CC CC_REGNUM))])]
2335 ""
2336 {
2337 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2338 rtx reg0 = gen_reg_rtx (dword_mode);
2339 rtx reg1 = gen_reg_rtx (dword_mode);
2340 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2341 rtx len0 = gen_lowpart (Pmode, reg0);
2343 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2344 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2345 emit_move_insn (len0, operands[1]);
2347 emit_move_insn (reg1, const0_rtx);
2349 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2350 operands[1] = reg0;
2351 operands[3] = reg1;
2352 })
2354 (define_insn "*setmem_long"
2355 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2356 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2357 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2358 (use (match_dup 3))
2359 (use (match_operand:<DBL> 1 "register_operand" "d"))
2360 (clobber (reg:CC CC_REGNUM))]
2361 ""
2362 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2363 [(set_attr "length" "8")
2364 (set_attr "type" "vs")])
2366 (define_insn "*setmem_long_and"
2367 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2368 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2369 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2370 (match_operand 4 "const_int_operand" "n")))
2371 (use (match_dup 3))
2372 (use (match_operand:<DBL> 1 "register_operand" "d"))
2373 (clobber (reg:CC CC_REGNUM))]
2374 "(INTVAL (operands[4]) & 255) == 255"
2375 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2376 [(set_attr "length" "8")
2377 (set_attr "type" "vs")])
2378 ;
2379 ; cmpmemM instruction pattern(s).
2380 ;
2382 (define_expand "cmpmemsi"
2383 [(set (match_operand:SI 0 "register_operand" "")
2384 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2385 (match_operand:BLK 2 "memory_operand" "") ) )
2386 (use (match_operand:SI 3 "general_operand" ""))
2387 (use (match_operand:SI 4 "" ""))]
2388 ""
2389 "s390_expand_cmpmem (operands[0], operands[1],
2390 operands[2], operands[3]); DONE;")
2392 ; Compare a block that is up to 256 bytes in length.
2393 ; The block length is taken as (operands[2] % 256) + 1.
2395 (define_expand "cmpmem_short"
2396 [(parallel
2397 [(set (reg:CCU CC_REGNUM)
2398 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2399 (match_operand:BLK 1 "memory_operand" "")))
2400 (use (match_operand 2 "nonmemory_operand" ""))
2401 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2402 (clobber (match_dup 3))])]
2403 ""
2404 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2406 (define_insn "*cmpmem_short"
2407 [(set (reg:CCU CC_REGNUM)
2408 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2409 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2410 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2411 (use (match_operand 3 "immediate_operand" "X,R,X"))
2412 (clobber (match_scratch 4 "=X,X,&a"))]
2413 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2414 && GET_MODE (operands[4]) == Pmode"
2415 "#"
2416 [(set_attr "type" "cs")])
2418 (define_split
2419 [(set (reg:CCU CC_REGNUM)
2420 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2421 (match_operand:BLK 1 "memory_operand" "")))
2422 (use (match_operand 2 "const_int_operand" ""))
2423 (use (match_operand 3 "immediate_operand" ""))
2424 (clobber (scratch))]
2425 "reload_completed"
2426 [(parallel
2427 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2428 (use (match_dup 2))])]
2429 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2431 (define_split
2432 [(set (reg:CCU CC_REGNUM)
2433 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2434 (match_operand:BLK 1 "memory_operand" "")))
2435 (use (match_operand 2 "register_operand" ""))
2436 (use (match_operand 3 "memory_operand" ""))
2437 (clobber (scratch))]
2438 "reload_completed"
2439 [(parallel
2440 [(unspec [(match_dup 2) (match_dup 3)
2441 (const_int 0)] UNSPEC_EXECUTE)
2442 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2443 (use (const_int 1))])]
2444 "")
2446 (define_split
2447 [(set (reg:CCU CC_REGNUM)
2448 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2449 (match_operand:BLK 1 "memory_operand" "")))
2450 (use (match_operand 2 "register_operand" ""))
2451 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2452 (clobber (match_operand 3 "register_operand" ""))]
2453 "reload_completed && TARGET_CPU_ZARCH"
2454 [(set (match_dup 3) (label_ref (match_dup 4)))
2455 (parallel
2456 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2457 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2458 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2459 (use (const_int 1))])]
2460 "operands[4] = gen_label_rtx ();")
2462 ; Compare a block of arbitrary length.
2464 (define_expand "cmpmem_long"
2465 [(parallel
2466 [(clobber (match_dup 2))
2467 (clobber (match_dup 3))
2468 (set (reg:CCU CC_REGNUM)
2469 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2470 (match_operand:BLK 1 "memory_operand" "")))
2471 (use (match_operand 2 "general_operand" ""))
2472 (use (match_dup 3))])]
2473 ""
2474 {
2475 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2476 rtx reg0 = gen_reg_rtx (dword_mode);
2477 rtx reg1 = gen_reg_rtx (dword_mode);
2478 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2479 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2480 rtx len0 = gen_lowpart (Pmode, reg0);
2481 rtx len1 = gen_lowpart (Pmode, reg1);
2483 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2484 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2485 emit_move_insn (len0, operands[2]);
2487 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2488 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2489 emit_move_insn (len1, operands[2]);
2491 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2492 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2493 operands[2] = reg0;
2494 operands[3] = reg1;
2495 })
2497 (define_insn "*cmpmem_long"
2498 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2499 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2500 (set (reg:CCU CC_REGNUM)
2501 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2502 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2503 (use (match_dup 2))
2504 (use (match_dup 3))]
2505 ""
2506 "clcle\t%0,%1,0\;jo\t.-4"
2507 [(set_attr "length" "8")
2508 (set_attr "type" "vs")])
2510 ; Convert CCUmode condition code to integer.
2511 ; Result is zero if EQ, positive if LTU, negative if GTU.
2513 (define_insn_and_split "cmpint"
2514 [(set (match_operand:SI 0 "register_operand" "=d")
2515 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2516 UNSPEC_CMPINT))
2517 (clobber (reg:CC CC_REGNUM))]
2518 ""
2519 "#"
2520 "reload_completed"
2521 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2522 (parallel
2523 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2524 (clobber (reg:CC CC_REGNUM))])])
2526 (define_insn_and_split "*cmpint_cc"
2527 [(set (reg CC_REGNUM)
2528 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2529 UNSPEC_CMPINT)
2530 (const_int 0)))
2531 (set (match_operand:SI 0 "register_operand" "=d")
2532 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2533 "s390_match_ccmode (insn, CCSmode)"
2534 "#"
2535 "&& reload_completed"
2536 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2537 (parallel
2538 [(set (match_dup 2) (match_dup 3))
2539 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2540 {
2541 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2542 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2543 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2544 })
2546 (define_insn_and_split "*cmpint_sign"
2547 [(set (match_operand:DI 0 "register_operand" "=d")
2548 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2549 UNSPEC_CMPINT)))
2550 (clobber (reg:CC CC_REGNUM))]
2551 "TARGET_64BIT"
2552 "#"
2553 "&& reload_completed"
2554 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2555 (parallel
2556 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2557 (clobber (reg:CC CC_REGNUM))])])
2559 (define_insn_and_split "*cmpint_sign_cc"
2560 [(set (reg CC_REGNUM)
2561 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2562 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2563 UNSPEC_CMPINT) 0)
2564 (const_int 32)) (const_int 32))
2565 (const_int 0)))
2566 (set (match_operand:DI 0 "register_operand" "=d")
2567 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2568 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2569 "#"
2570 "&& reload_completed"
2571 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2572 (parallel
2573 [(set (match_dup 2) (match_dup 3))
2574 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2575 {
2576 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2577 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2578 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2579 })
2582 ;;
2583 ;;- Conversion instructions.
2584 ;;
2586 (define_insn "*sethighpartsi"
2587 [(set (match_operand:SI 0 "register_operand" "=d,d")
2588 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
2589 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2590 (clobber (reg:CC CC_REGNUM))]
2591 ""
2592 "@
2593 icm\t%0,%2,%S1
2594 icmy\t%0,%2,%S1"
2595 [(set_attr "op_type" "RS,RSY")])
2597 (define_insn "*sethighpartdi_64"
2598 [(set (match_operand:DI 0 "register_operand" "=d")
2599 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
2600 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
2601 (clobber (reg:CC CC_REGNUM))]
2602 "TARGET_64BIT"
2603 "icmh\t%0,%2,%S1"
2604 [(set_attr "op_type" "RSY")])
2606 (define_insn "*sethighpartdi_31"
2607 [(set (match_operand:DI 0 "register_operand" "=d,d")
2608 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
2609 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2610 (clobber (reg:CC CC_REGNUM))]
2611 "!TARGET_64BIT"
2612 "@
2613 icm\t%0,%2,%S1
2614 icmy\t%0,%2,%S1"
2615 [(set_attr "op_type" "RS,RSY")])
2617 (define_insn_and_split "*extzv<mode>"
2618 [(set (match_operand:GPR 0 "register_operand" "=d")
2619 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2620 (match_operand 2 "const_int_operand" "n")
2621 (const_int 0)))
2622 (clobber (reg:CC CC_REGNUM))]
2623 "INTVAL (operands[2]) > 0
2624 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2625 "#"
2626 "&& reload_completed"
2627 [(parallel
2628 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2629 (clobber (reg:CC CC_REGNUM))])
2630 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
2631 {
2632 int bitsize = INTVAL (operands[2]);
2633 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2634 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2636 operands[1] = adjust_address (operands[1], BLKmode, 0);
2637 set_mem_size (operands[1], GEN_INT (size));
2638 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2639 operands[3] = GEN_INT (mask);
2640 })
2642 (define_insn_and_split "*extv<mode>"
2643 [(set (match_operand:GPR 0 "register_operand" "=d")
2644 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2645 (match_operand 2 "const_int_operand" "n")
2646 (const_int 0)))
2647 (clobber (reg:CC CC_REGNUM))]
2648 "INTVAL (operands[2]) > 0
2649 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2650 "#"
2651 "&& reload_completed"
2652 [(parallel
2653 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2654 (clobber (reg:CC CC_REGNUM))])
2655 (parallel
2656 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2657 (clobber (reg:CC CC_REGNUM))])]
2658 {
2659 int bitsize = INTVAL (operands[2]);
2660 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2661 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2663 operands[1] = adjust_address (operands[1], BLKmode, 0);
2664 set_mem_size (operands[1], GEN_INT (size));
2665 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2666 operands[3] = GEN_INT (mask);
2667 })
2669 ;
2670 ; insv instruction patterns
2671 ;
2673 (define_expand "insv"
2674 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2675 (match_operand 1 "const_int_operand" "")
2676 (match_operand 2 "const_int_operand" ""))
2677 (match_operand 3 "general_operand" ""))]
2678 ""
2679 {
2680 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
2681 DONE;
2682 FAIL;
2683 })
2685 (define_insn "*insv<mode>_mem_reg"
2686 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
2687 (match_operand 1 "const_int_operand" "n,n")
2688 (const_int 0))
2689 (match_operand:P 2 "register_operand" "d,d"))]
2690 "INTVAL (operands[1]) > 0
2691 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2692 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2693 {
2694 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2696 operands[1] = GEN_INT ((1ul << size) - 1);
2697 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
2698 : "stcmy\t%2,%1,%S0";
2699 }
2700 [(set_attr "op_type" "RS,RSY")])
2702 (define_insn "*insvdi_mem_reghigh"
2703 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
2704 (match_operand 1 "const_int_operand" "n")
2705 (const_int 0))
2706 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
2707 (const_int 32)))]
2708 "TARGET_64BIT
2709 && INTVAL (operands[1]) > 0
2710 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2711 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2712 {
2713 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2715 operands[1] = GEN_INT ((1ul << size) - 1);
2716 return "stcmh\t%2,%1,%S0";
2717 }
2718 [(set_attr "op_type" "RSY")])
2720 (define_insn "*insv<mode>_reg_imm"
2721 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2722 (const_int 16)
2723 (match_operand 1 "const_int_operand" "n"))
2724 (match_operand:P 2 "const_int_operand" "n"))]
2725 "TARGET_ZARCH
2726 && INTVAL (operands[1]) >= 0
2727 && INTVAL (operands[1]) < BITS_PER_WORD
2728 && INTVAL (operands[1]) % 16 == 0"
2729 {
2730 switch (BITS_PER_WORD - INTVAL (operands[1]))
2731 {
2732 case 64: return "iihh\t%0,%x2"; break;
2733 case 48: return "iihl\t%0,%x2"; break;
2734 case 32: return "iilh\t%0,%x2"; break;
2735 case 16: return "iill\t%0,%x2"; break;
2736 default: gcc_unreachable();
2737 }
2738 }
2739 [(set_attr "op_type" "RI")])
2741 (define_insn "*insv<mode>_reg_extimm"
2742 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2743 (const_int 32)
2744 (match_operand 1 "const_int_operand" "n"))
2745 (match_operand:P 2 "const_int_operand" "n"))]
2746 "TARGET_EXTIMM
2747 && INTVAL (operands[1]) >= 0
2748 && INTVAL (operands[1]) < BITS_PER_WORD
2749 && INTVAL (operands[1]) % 32 == 0"
2750 {
2751 switch (BITS_PER_WORD - INTVAL (operands[1]))
2752 {
2753 case 64: return "iihf\t%0,%o2"; break;
2754 case 32: return "iilf\t%0,%o2"; break;
2755 default: gcc_unreachable();
2756 }
2757 }
2758 [(set_attr "op_type" "RIL")])
2760 ;
2761 ; extendsidi2 instruction pattern(s).
2762 ;
2764 (define_expand "extendsidi2"
2765 [(set (match_operand:DI 0 "register_operand" "")
2766 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2767 ""
2768 {
2769 if (!TARGET_64BIT)
2770 {
2771 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2772 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2773 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2774 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2775 DONE;
2776 }
2777 })
2779 (define_insn "*extendsidi2"
2780 [(set (match_operand:DI 0 "register_operand" "=d,d")
2781 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2782 "TARGET_64BIT"
2783 "@
2784 lgfr\t%0,%1
2785 lgf\t%0,%1"
2786 [(set_attr "op_type" "RRE,RXY")])
2788 ;
2789 ; extend(hi|qi)(si|di)2 instruction pattern(s).
2790 ;
2792 (define_expand "extend<HQI:mode><DSI:mode>2"
2793 [(set (match_operand:DSI 0 "register_operand" "")
2794 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2795 ""
2796 {
2797 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
2798 {
2799 rtx tmp = gen_reg_rtx (SImode);
2800 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
2801 emit_insn (gen_extendsidi2 (operands[0], tmp));
2802 DONE;
2803 }
2804 else if (!TARGET_EXTIMM)
2805 {
2806 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
2807 GET_MODE_BITSIZE (<HQI:MODE>mode));
2809 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
2810 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
2811 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
2812 DONE;
2813 }
2814 })
2816 ;
2817 ; extendhidi2 instruction pattern(s).
2818 ;
2820 (define_insn "*extendhidi2_extimm"
2821 [(set (match_operand:DI 0 "register_operand" "=d,d")
2822 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2823 "TARGET_64BIT && TARGET_EXTIMM"
2824 "@
2825 lghr\t%0,%1
2826 lgh\t%0,%1"
2827 [(set_attr "op_type" "RRE,RXY")])
2829 (define_insn "*extendhidi2"
2830 [(set (match_operand:DI 0 "register_operand" "=d")
2831 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2832 "TARGET_64BIT"
2833 "lgh\t%0,%1"
2834 [(set_attr "op_type" "RXY")])
2836 ;
2837 ; extendhisi2 instruction pattern(s).
2838 ;
2840 (define_insn "*extendhisi2_extimm"
2841 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2842 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2843 "TARGET_EXTIMM"
2844 "@
2845 lhr\t%0,%1
2846 lh\t%0,%1
2847 lhy\t%0,%1"
2848 [(set_attr "op_type" "RRE,RX,RXY")])
2850 (define_insn "*extendhisi2"
2851 [(set (match_operand:SI 0 "register_operand" "=d,d")
2852 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2853 "!TARGET_EXTIMM"
2854 "@
2855 lh\t%0,%1
2856 lhy\t%0,%1"
2857 [(set_attr "op_type" "RX,RXY")])
2859 ;
2860 ; extendqi(si|di)2 instruction pattern(s).
2861 ;
2863 (define_insn "*extendqi<mode>2_extimm"
2864 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2865 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2866 "TARGET_EXTIMM"
2867 "@
2868 l<g>br\t%0,%1
2869 l<g>b\t%0,%1"
2870 [(set_attr "op_type" "RRE,RXY")])
2872 (define_insn "*extendqi<mode>2"
2873 [(set (match_operand:GPR 0 "register_operand" "=d")
2874 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
2875 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
2876 "l<g>b\t%0,%1"
2877 [(set_attr "op_type" "RXY")])
2879 (define_insn_and_split "*extendqi<mode>2_short_displ"
2880 [(set (match_operand:GPR 0 "register_operand" "=d")
2881 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
2882 (clobber (reg:CC CC_REGNUM))]
2883 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
2884 "#"
2885 "&& reload_completed"
2886 [(parallel
2887 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2888 (clobber (reg:CC CC_REGNUM))])
2889 (parallel
2890 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2891 (clobber (reg:CC CC_REGNUM))])]
2892 {
2893 operands[1] = adjust_address (operands[1], BLKmode, 0);
2894 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
2895 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
2896 - GET_MODE_BITSIZE (QImode));
2897 })
2899 ;
2900 ; zero_extendsidi2 instruction pattern(s).
2901 ;
2903 (define_expand "zero_extendsidi2"
2904 [(set (match_operand:DI 0 "register_operand" "")
2905 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2906 ""
2907 {
2908 if (!TARGET_64BIT)
2909 {
2910 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2911 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2912 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2913 DONE;
2914 }
2915 })
2917 (define_insn "*zero_extendsidi2"
2918 [(set (match_operand:DI 0 "register_operand" "=d,d")
2919 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2920 "TARGET_64BIT"
2921 "@
2922 llgfr\t%0,%1
2923 llgf\t%0,%1"
2924 [(set_attr "op_type" "RRE,RXY")])
2926 ;
2927 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2928 ;
2930 (define_insn "*llgt_sidi"
2931 [(set (match_operand:DI 0 "register_operand" "=d")
2932 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2933 (const_int 2147483647)))]
2934 "TARGET_64BIT"
2935 "llgt\t%0,%1"
2936 [(set_attr "op_type" "RXE")])
2938 (define_insn_and_split "*llgt_sidi_split"
2939 [(set (match_operand:DI 0 "register_operand" "=d")
2940 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2941 (const_int 2147483647)))
2942 (clobber (reg:CC CC_REGNUM))]
2943 "TARGET_64BIT"
2944 "#"
2945 "&& reload_completed"
2946 [(set (match_dup 0)
2947 (and:DI (subreg:DI (match_dup 1) 0)
2948 (const_int 2147483647)))]
2949 "")
2951 (define_insn "*llgt_sisi"
2952 [(set (match_operand:SI 0 "register_operand" "=d,d")
2953 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2954 (const_int 2147483647)))]
2955 "TARGET_ZARCH"
2956 "@
2957 llgtr\t%0,%1
2958 llgt\t%0,%1"
2959 [(set_attr "op_type" "RRE,RXE")])
2961 (define_insn "*llgt_didi"
2962 [(set (match_operand:DI 0 "register_operand" "=d,d")
2963 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2964 (const_int 2147483647)))]
2965 "TARGET_64BIT"
2966 "@
2967 llgtr\t%0,%1
2968 llgt\t%0,%N1"
2969 [(set_attr "op_type" "RRE,RXE")])
2971 (define_split
2972 [(set (match_operand:GPR 0 "register_operand" "")
2973 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2974 (const_int 2147483647)))
2975 (clobber (reg:CC CC_REGNUM))]
2976 "TARGET_ZARCH && reload_completed"
2977 [(set (match_dup 0)
2978 (and:GPR (match_dup 1)
2979 (const_int 2147483647)))]
2980 "")
2982 ;
2983 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
2984 ;
2986 (define_expand "zero_extend<mode>di2"
2987 [(set (match_operand:DI 0 "register_operand" "")
2988 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2989 ""
2990 {
2991 if (!TARGET_64BIT)
2992 {
2993 rtx tmp = gen_reg_rtx (SImode);
2994 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2995 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2996 DONE;
2997 }
2998 else if (!TARGET_EXTIMM)
2999 {
3000 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3001 GET_MODE_BITSIZE(<MODE>mode));
3002 operands[1] = gen_lowpart (DImode, operands[1]);
3003 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3004 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3005 DONE;
3006 }
3007 })
3009 (define_expand "zero_extend<mode>si2"
3010 [(set (match_operand:SI 0 "register_operand" "")
3011 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3012 ""
3013 {
3014 if (!TARGET_EXTIMM)
3015 {
3016 operands[1] = gen_lowpart (SImode, operands[1]);
3017 emit_insn (gen_andsi3 (operands[0], operands[1],
3018 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3019 DONE;
3020 }
3021 })
3023 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3024 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3025 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
3026 "TARGET_EXTIMM"
3027 "@
3028 ll<g><hc>r\t%0,%1
3029 ll<g><hc>\t%0,%1"
3030 [(set_attr "op_type" "RRE,RXY")])
3032 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3033 [(set (match_operand:GPR 0 "register_operand" "=d")
3034 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
3035 "TARGET_ZARCH && !TARGET_EXTIMM"
3036 "llg<hc>\t%0,%1"
3037 [(set_attr "op_type" "RXY")])
3039 (define_insn_and_split "*zero_extendhisi2_31"
3040 [(set (match_operand:SI 0 "register_operand" "=&d")
3041 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3042 (clobber (reg:CC CC_REGNUM))]
3043 "!TARGET_ZARCH"
3044 "#"
3045 "&& reload_completed"
3046 [(set (match_dup 0) (const_int 0))
3047 (parallel
3048 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3049 (clobber (reg:CC CC_REGNUM))])]
3050 "operands[2] = gen_lowpart (HImode, operands[0]);")
3052 (define_insn_and_split "*zero_extendqisi2_31"
3053 [(set (match_operand:SI 0 "register_operand" "=&d")
3054 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3055 "!TARGET_ZARCH"
3056 "#"
3057 "&& reload_completed"
3058 [(set (match_dup 0) (const_int 0))
3059 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3060 "operands[2] = gen_lowpart (QImode, operands[0]);")
3062 ;
3063 ; zero_extendqihi2 instruction pattern(s).
3064 ;
3066 (define_expand "zero_extendqihi2"
3067 [(set (match_operand:HI 0 "register_operand" "")
3068 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3069 "TARGET_ZARCH && !TARGET_EXTIMM"
3070 {
3071 operands[1] = gen_lowpart (HImode, operands[1]);
3072 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3073 DONE;
3074 })
3076 (define_insn "*zero_extendqihi2_64"
3077 [(set (match_operand:HI 0 "register_operand" "=d")
3078 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3079 "TARGET_ZARCH && !TARGET_EXTIMM"
3080 "llgc\t%0,%1"
3081 [(set_attr "op_type" "RXY")])
3083 (define_insn_and_split "*zero_extendqihi2_31"
3084 [(set (match_operand:HI 0 "register_operand" "=&d")
3085 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3086 "!TARGET_ZARCH"
3087 "#"
3088 "&& reload_completed"
3089 [(set (match_dup 0) (const_int 0))
3090 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3091 "operands[2] = gen_lowpart (QImode, operands[0]);")
3094 ;
3095 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
3096 ;
3098 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
3099 [(set (match_operand:GPR 0 "register_operand" "")
3100 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
3101 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3102 {
3103 rtx label1 = gen_label_rtx ();
3104 rtx label2 = gen_label_rtx ();
3105 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
3106 REAL_VALUE_TYPE cmp, sub;
3108 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
3109 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
3110 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
3112 emit_insn (gen_cmp<FPR:mode> (operands[1],
3113 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
3114 emit_jump_insn (gen_blt (label1));
3115 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
3116 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
3117 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
3118 GEN_INT(7)));
3119 emit_jump (label2);
3121 emit_label (label1);
3122 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
3123 operands[1], GEN_INT(5)));
3124 emit_label (label2);
3125 DONE;
3126 })
3128 (define_expand "fix_trunc<mode>di2"
3129 [(set (match_operand:DI 0 "register_operand" "")
3130 (fix:DI (match_operand:DSF 1 "nonimmediate_operand" "")))]
3131 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3132 {
3133 operands[1] = force_reg (<MODE>mode, operands[1]);
3134 emit_insn (gen_fix_trunc<mode>di2_ieee (operands[0], operands[1],
3135 GEN_INT(5)));
3136 DONE;
3137 })
3139 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
3140 [(set (match_operand:GPR 0 "register_operand" "=d")
3141 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
3142 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3143 (clobber (reg:CC CC_REGNUM))]
3144 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3145 "c<GPR:gf><FPR:xde>br\t%0,%h2,%1"
3146 [(set_attr "op_type" "RRE")
3147 (set_attr "type" "ftoi")])
3149 ;
3150 ; fix_trunctf(si|di)2 instruction pattern(s).
3151 ;
3153 (define_expand "fix_trunctf<mode>2"
3154 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3155 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3156 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3157 (clobber (reg:CC CC_REGNUM))])]
3158 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3159 "")
3161 ;
3162 ; fix_truncdfsi2 instruction pattern(s).
3163 ;
3165 (define_expand "fix_truncdfsi2"
3166 [(set (match_operand:SI 0 "register_operand" "")
3167 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
3168 "TARGET_HARD_FLOAT"
3169 {
3170 if (TARGET_IBM_FLOAT)
3171 {
3172 /* This is the algorithm from POP chapter A.5.7.2. */
3174 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3175 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
3176 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
3178 operands[1] = force_reg (DFmode, operands[1]);
3179 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
3180 two31r, two32, temp));
3181 }
3182 else
3183 {
3184 operands[1] = force_reg (DFmode, operands[1]);
3185 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3186 }
3188 DONE;
3189 })
3191 (define_insn "fix_truncdfsi2_ibm"
3192 [(set (match_operand:SI 0 "register_operand" "=d")
3193 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
3194 (use (match_operand:DI 2 "immediate_operand" "m"))
3195 (use (match_operand:DI 3 "immediate_operand" "m"))
3196 (use (match_operand:BLK 4 "memory_operand" "m"))
3197 (clobber (reg:CC CC_REGNUM))]
3198 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3199 {
3200 output_asm_insn ("sd\t%1,%2", operands);
3201 output_asm_insn ("aw\t%1,%3", operands);
3202 output_asm_insn ("std\t%1,%4", operands);
3203 output_asm_insn ("xi\t%N4,128", operands);
3204 return "l\t%0,%N4";
3205 }
3206 [(set_attr "length" "20")])
3208 ;
3209 ; fix_truncsfsi2 instruction pattern(s).
3210 ;
3212 (define_expand "fix_truncsfsi2"
3213 [(set (match_operand:SI 0 "register_operand" "")
3214 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3215 "TARGET_HARD_FLOAT"
3216 {
3217 if (TARGET_IBM_FLOAT)
3218 {
3219 /* Convert to DFmode and then use the POP algorithm. */
3220 rtx temp = gen_reg_rtx (DFmode);
3221 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3222 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3223 }
3224 else
3225 {
3226 operands[1] = force_reg (SFmode, operands[1]);
3227 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3228 }
3230 DONE;
3231 })
3233 ;
3234 ; float(si|di)(tf|df|sf)2 instruction pattern(s).
3235 ;
3237 (define_insn "floatdi<mode>2"
3238 [(set (match_operand:FPR 0 "register_operand" "=f")
3239 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
3240 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3241 "c<xde>gbr\t%0,%1"
3242 [(set_attr "op_type" "RRE")
3243 (set_attr "type" "itof" )])
3245 (define_insn "floatsi<mode>2_ieee"
3246 [(set (match_operand:FPR 0 "register_operand" "=f")
3247 (float:FPR (match_operand:SI 1 "register_operand" "d")))]
3248 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3249 "c<xde>fbr\t%0,%1"
3250 [(set_attr "op_type" "RRE")
3251 (set_attr "type" "itof" )])
3254 ;
3255 ; floatsi(tf|df)2 instruction pattern(s).
3256 ;
3258 (define_expand "floatsitf2"
3259 [(set (match_operand:TF 0 "register_operand" "")
3260 (float:TF (match_operand:SI 1 "register_operand" "")))]
3261 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3262 "")
3264 (define_expand "floatsidf2"
3265 [(set (match_operand:DF 0 "register_operand" "")
3266 (float:DF (match_operand:SI 1 "register_operand" "")))]
3267 "TARGET_HARD_FLOAT"
3268 {
3269 if (TARGET_IBM_FLOAT)
3270 {
3271 /* This is the algorithm from POP chapter A.5.7.1. */
3273 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3274 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3276 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3277 DONE;
3278 }
3279 })
3281 (define_insn "floatsidf2_ibm"
3282 [(set (match_operand:DF 0 "register_operand" "=f")
3283 (float:DF (match_operand:SI 1 "register_operand" "d")))
3284 (use (match_operand:DI 2 "immediate_operand" "m"))
3285 (use (match_operand:BLK 3 "memory_operand" "m"))
3286 (clobber (reg:CC CC_REGNUM))]
3287 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3288 {
3289 output_asm_insn ("st\t%1,%N3", operands);
3290 output_asm_insn ("xi\t%N3,128", operands);
3291 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3292 output_asm_insn ("ld\t%0,%3", operands);
3293 return "sd\t%0,%2";
3294 }
3295 [(set_attr "length" "20")])
3297 ;
3298 ; floatsisf2 instruction pattern(s).
3299 ;
3301 (define_expand "floatsisf2"
3302 [(set (match_operand:SF 0 "register_operand" "")
3303 (float:SF (match_operand:SI 1 "register_operand" "")))]
3304 "TARGET_HARD_FLOAT"
3305 {
3306 if (TARGET_IBM_FLOAT)
3307 {
3308 /* Use the POP algorithm to convert to DFmode and then truncate. */
3309 rtx temp = gen_reg_rtx (DFmode);
3310 emit_insn (gen_floatsidf2 (temp, operands[1]));
3311 emit_insn (gen_truncdfsf2 (operands[0], temp));
3312 DONE;
3313 }
3314 })
3316 ;
3317 ; truncdfsf2 instruction pattern(s).
3318 ;
3320 (define_expand "truncdfsf2"
3321 [(set (match_operand:SF 0 "register_operand" "")
3322 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3323 "TARGET_HARD_FLOAT"
3324 "")
3326 (define_insn "truncdfsf2_ieee"
3327 [(set (match_operand:SF 0 "register_operand" "=f")
3328 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3329 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3330 "ledbr\t%0,%1"
3331 [(set_attr "op_type" "RRE")
3332 (set_attr "type" "ftruncdf")])
3334 (define_insn "truncdfsf2_ibm"
3335 [(set (match_operand:SF 0 "register_operand" "=f,f")
3336 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3337 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3338 "@
3339 ler\t%0,%1
3340 le\t%0,%1"
3341 [(set_attr "op_type" "RR,RX")
3342 (set_attr "type" "floadsf")])
3344 ;
3345 ; trunctfdf2 instruction pattern(s).
3346 ;
3348 (define_expand "trunctfdf2"
3349 [(parallel
3350 [(set (match_operand:DF 0 "register_operand" "")
3351 (float_truncate:DF (match_operand:TF 1 "register_operand" "")))
3352 (clobber (match_scratch:TF 2 "=f"))])]
3353 "TARGET_HARD_FLOAT"
3354 "")
3356 (define_insn "*trunctfdf2_ieee"
3357 [(set (match_operand:DF 0 "register_operand" "=f")
3358 (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
3359 (clobber (match_scratch:TF 2 "=f"))]
3360 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3361 "ldxbr\t%2,%1\;ldr\t%0,%2"
3362 [(set_attr "length" "6")
3363 (set_attr "type" "ftrunctf")])
3365 (define_insn "*trunctfdf2_ibm"
3366 [(set (match_operand:DF 0 "register_operand" "=f")
3367 (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
3368 (clobber (match_scratch:TF 2 "=f"))]
3369 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3370 "ldxr\t%2,%1\;ldr\t%0,%2"
3371 [(set_attr "length" "4")
3372 (set_attr "type" "ftrunctf")])
3374 ;
3375 ; trunctfsf2 instruction pattern(s).
3376 ;
3378 (define_expand "trunctfsf2"
3379 [(parallel
3380 [(set (match_operand:SF 0 "register_operand" "=f")
3381 (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3382 (clobber (match_scratch:TF 2 "=f"))])]
3383 "TARGET_HARD_FLOAT"
3384 "")
3386 (define_insn "*trunctfsf2_ieee"
3387 [(set (match_operand:SF 0 "register_operand" "=f")
3388 (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3389 (clobber (match_scratch:TF 2 "=f"))]
3390 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3391 "lexbr\t%2,%1\;ler\t%0,%2"
3392 [(set_attr "length" "6")
3393 (set_attr "type" "ftrunctf")])
3395 (define_insn "*trunctfsf2_ibm"
3396 [(set (match_operand:SF 0 "register_operand" "=f")
3397 (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3398 (clobber (match_scratch:TF 2 "=f"))]
3399 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3400 "lexr\t%2,%1\;ler\t%0,%2"
3401 [(set_attr "length" "6")
3402 (set_attr "type" "ftrunctf")])
3404 ;
3405 ; extendsfdf2 instruction pattern(s).
3406 ;
3408 (define_expand "extendsfdf2"
3409 [(set (match_operand:DF 0 "register_operand" "")
3410 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3411 "TARGET_HARD_FLOAT"
3412 {
3413 if (TARGET_IBM_FLOAT)
3414 {
3415 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3416 DONE;
3417 }
3418 })
3420 (define_insn "extendsfdf2_ieee"
3421 [(set (match_operand:DF 0 "register_operand" "=f,f")
3422 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3423 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3424 "@
3425 ldebr\t%0,%1
3426 ldeb\t%0,%1"
3427 [(set_attr "op_type" "RRE,RXE")
3428 (set_attr "type" "fsimpsf, floadsf")])
3430 (define_insn "extendsfdf2_ibm"
3431 [(set (match_operand:DF 0 "register_operand" "=f,f")
3432 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3433 (clobber (reg:CC CC_REGNUM))]
3434 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3435 "@
3436 sdr\t%0,%0\;ler\t%0,%1
3437 sdr\t%0,%0\;le\t%0,%1"
3438 [(set_attr "length" "4,6")
3439 (set_attr "type" "floadsf")])
3441 ;
3442 ; extenddftf2 instruction pattern(s).
3443 ;
3445 (define_expand "extenddftf2"
3446 [(set (match_operand:TF 0 "register_operand" "")
3447 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
3448 "TARGET_HARD_FLOAT"
3449 "")
3451 (define_insn "*extenddftf2_ieee"
3452 [(set (match_operand:TF 0 "register_operand" "=f,f")
3453 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3454 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3455 "@
3456 lxdbr\t%0,%1
3457 lxdb\t%0,%1"
3458 [(set_attr "op_type" "RRE,RXE")
3459 (set_attr "type" "fsimptf, floadtf")])
3461 (define_insn "*extenddftf2_ibm"
3462 [(set (match_operand:TF 0 "register_operand" "=f,f")
3463 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3464 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3465 "@
3466 lxdr\t%0,%1
3467 lxd\t%0,%1"
3468 [(set_attr "op_type" "RRE,RXE")
3469 (set_attr "type" "fsimptf, floadtf")])
3471 ;
3472 ; extendsftf2 instruction pattern(s).
3473 ;
3475 (define_expand "extendsftf2"
3476 [(set (match_operand:TF 0 "register_operand" "")
3477 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
3478 "TARGET_HARD_FLOAT"
3479 "")
3481 (define_insn "*extendsftf2_ieee"
3482 [(set (match_operand:TF 0 "register_operand" "=f,f")
3483 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3484 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3485 "@
3486 lxebr\t%0,%1
3487 lxeb\t%0,%1"
3488 [(set_attr "op_type" "RRE,RXE")
3489 (set_attr "type" "fsimptf, floadtf")])
3491 (define_insn "*extendsftf2_ibm"
3492 [(set (match_operand:TF 0 "register_operand" "=f,f")
3493 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3494 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3495 "@
3496 lxer\t%0,%1
3497 lxe\t%0,%1"
3498 [(set_attr "op_type" "RRE,RXE")
3499 (set_attr "type" "fsimptf, floadtf")])
3502 ;;
3503 ;; ARITHMETIC OPERATIONS
3504 ;;
3505 ; arithmetic operations set the ConditionCode,
3506 ; because of unpredictable Bits in Register for Halfword and Byte
3507 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3509 ;;
3510 ;;- Add instructions.
3511 ;;
3513 ;
3514 ; addti3 instruction pattern(s).
3515 ;
3517 (define_insn_and_split "addti3"
3518 [(set (match_operand:TI 0 "register_operand" "=&d")
3519 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3520 (match_operand:TI 2 "general_operand" "do") ) )
3521 (clobber (reg:CC CC_REGNUM))]
3522 "TARGET_64BIT"
3523 "#"
3524 "&& reload_completed"
3525 [(parallel
3526 [(set (reg:CCL1 CC_REGNUM)
3527 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3528 (match_dup 7)))
3529 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3530 (parallel
3531 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3532 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3533 (clobber (reg:CC CC_REGNUM))])]
3534 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3535 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3536 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3537 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3538 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3539 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3541 ;
3542 ; adddi3 instruction pattern(s).
3543 ;
3545 (define_expand "adddi3"
3546 [(parallel
3547 [(set (match_operand:DI 0 "register_operand" "")
3548 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3549 (match_operand:DI 2 "general_operand" "")))
3550 (clobber (reg:CC CC_REGNUM))])]
3551 ""
3552 "")
3554 (define_insn "*adddi3_sign"
3555 [(set (match_operand:DI 0 "register_operand" "=d,d")
3556 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3557 (match_operand:DI 1 "register_operand" "0,0")))
3558 (clobber (reg:CC CC_REGNUM))]
3559 "TARGET_64BIT"
3560 "@
3561 agfr\t%0,%2
3562 agf\t%0,%2"
3563 [(set_attr "op_type" "RRE,RXY")])
3565 (define_insn "*adddi3_zero_cc"
3566 [(set (reg CC_REGNUM)
3567 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3568 (match_operand:DI 1 "register_operand" "0,0"))
3569 (const_int 0)))
3570 (set (match_operand:DI 0 "register_operand" "=d,d")
3571 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3572 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3573 "@
3574 algfr\t%0,%2
3575 algf\t%0,%2"
3576 [(set_attr "op_type" "RRE,RXY")])
3578 (define_insn "*adddi3_zero_cconly"
3579 [(set (reg CC_REGNUM)
3580 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3581 (match_operand:DI 1 "register_operand" "0,0"))
3582 (const_int 0)))
3583 (clobber (match_scratch:DI 0 "=d,d"))]
3584 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3585 "@
3586 algfr\t%0,%2
3587 algf\t%0,%2"
3588 [(set_attr "op_type" "RRE,RXY")])
3590 (define_insn "*adddi3_zero"
3591 [(set (match_operand:DI 0 "register_operand" "=d,d")
3592 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3593 (match_operand:DI 1 "register_operand" "0,0")))
3594 (clobber (reg:CC CC_REGNUM))]
3595 "TARGET_64BIT"
3596 "@
3597 algfr\t%0,%2
3598 algf\t%0,%2"
3599 [(set_attr "op_type" "RRE,RXY")])
3601 (define_insn_and_split "*adddi3_31z"
3602 [(set (match_operand:DI 0 "register_operand" "=&d")
3603 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3604 (match_operand:DI 2 "general_operand" "do") ) )
3605 (clobber (reg:CC CC_REGNUM))]
3606 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3607 "#"
3608 "&& reload_completed"
3609 [(parallel
3610 [(set (reg:CCL1 CC_REGNUM)
3611 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3612 (match_dup 7)))
3613 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3614 (parallel
3615 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3616 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3617 (clobber (reg:CC CC_REGNUM))])]
3618 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3619 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3620 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3621 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3622 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3623 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3625 (define_insn_and_split "*adddi3_31"
3626 [(set (match_operand:DI 0 "register_operand" "=&d")
3627 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3628 (match_operand:DI 2 "general_operand" "do") ) )
3629 (clobber (reg:CC CC_REGNUM))]
3630 "!TARGET_CPU_ZARCH"
3631 "#"
3632 "&& reload_completed"
3633 [(parallel
3634 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3635 (clobber (reg:CC CC_REGNUM))])
3636 (parallel
3637 [(set (reg:CCL1 CC_REGNUM)
3638 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3639 (match_dup 7)))
3640 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3641 (set (pc)
3642 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3643 (pc)
3644 (label_ref (match_dup 9))))
3645 (parallel
3646 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3647 (clobber (reg:CC CC_REGNUM))])
3648 (match_dup 9)]
3649 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3650 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3651 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3652 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3653 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3654 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3655 operands[9] = gen_label_rtx ();")
3657 ;
3658 ; addsi3 instruction pattern(s).
3659 ;
3661 (define_expand "addsi3"
3662 [(parallel
3663 [(set (match_operand:SI 0 "register_operand" "")
3664 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
3665 (match_operand:SI 2 "general_operand" "")))
3666 (clobber (reg:CC CC_REGNUM))])]
3667 ""
3668 "")
3670 (define_insn "*addsi3_sign"
3671 [(set (match_operand:SI 0 "register_operand" "=d,d")
3672 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3673 (match_operand:SI 1 "register_operand" "0,0")))
3674 (clobber (reg:CC CC_REGNUM))]
3675 ""
3676 "@
3677 ah\t%0,%2
3678 ahy\t%0,%2"
3679 [(set_attr "op_type" "RX,RXY")])
3681 ;
3682 ; add(di|si)3 instruction pattern(s).
3683 ;
3685 (define_insn "*add<mode>3"
3686 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d")
3687 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
3688 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T") ) )
3689 (clobber (reg:CC CC_REGNUM))]
3690 ""
3691 "@
3692 a<g>r\t%0,%2
3693 a<g>hi\t%0,%h2
3694 al<g>fi\t%0,%2
3695 sl<g>fi\t%0,%n2
3696 a<g>\t%0,%2
3697 a<y>\t%0,%2"
3698 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY")])
3700 (define_insn "*add<mode>3_carry1_cc"
3701 [(set (reg CC_REGNUM)
3702 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3703 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3704 (match_dup 1)))
3705 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3706 (plus:GPR (match_dup 1) (match_dup 2)))]
3707 "s390_match_ccmode (insn, CCL1mode)"
3708 "@
3709 al<g>r\t%0,%2
3710 al<g>fi\t%0,%2
3711 sl<g>fi\t%0,%n2
3712 al<g>\t%0,%2
3713 al<y>\t%0,%2"
3714 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3716 (define_insn "*add<mode>3_carry1_cconly"
3717 [(set (reg CC_REGNUM)
3718 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3719 (match_operand:GPR 2 "general_operand" "d,R,T"))
3720 (match_dup 1)))
3721 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3722 "s390_match_ccmode (insn, CCL1mode)"
3723 "@
3724 al<g>r\t%0,%2
3725 al<g>\t%0,%2
3726 al<y>\t%0,%2"
3727 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3729 (define_insn "*add<mode>3_carry2_cc"
3730 [(set (reg CC_REGNUM)
3731 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3732 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3733 (match_dup 2)))
3734 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3735 (plus:GPR (match_dup 1) (match_dup 2)))]
3736 "s390_match_ccmode (insn, CCL1mode)"
3737 "@
3738 al<g>r\t%0,%2
3739 al<g>fi\t%0,%2
3740 sl<g>fi\t%0,%n2
3741 al<g>\t%0,%2
3742 al<y>\t%0,%2"
3743 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3745 (define_insn "*add<mode>3_carry2_cconly"
3746 [(set (reg CC_REGNUM)
3747 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3748 (match_operand:GPR 2 "general_operand" "d,R,T"))
3749 (match_dup 2)))
3750 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3751 "s390_match_ccmode (insn, CCL1mode)"
3752 "@
3753 al<g>r\t%0,%2
3754 al<g>\t%0,%2
3755 al<y>\t%0,%2"
3756 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3758 (define_insn "*add<mode>3_cc"
3759 [(set (reg CC_REGNUM)
3760 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3761 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3762 (const_int 0)))
3763 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3764 (plus:GPR (match_dup 1) (match_dup 2)))]
3765 "s390_match_ccmode (insn, CCLmode)"
3766 "@
3767 al<g>r\t%0,%2
3768 al<g>fi\t%0,%2
3769 sl<g>fi\t%0,%n2
3770 al<g>\t%0,%2
3771 al<y>\t%0,%2"
3772 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3774 (define_insn "*add<mode>3_cconly"
3775 [(set (reg CC_REGNUM)
3776 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3777 (match_operand:GPR 2 "general_operand" "d,R,T"))
3778 (const_int 0)))
3779 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3780 "s390_match_ccmode (insn, CCLmode)"
3781 "@
3782 al<g>r\t%0,%2
3783 al<g>\t%0,%2
3784 al<y>\t%0,%2"
3785 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3787 (define_insn "*add<mode>3_cconly2"
3788 [(set (reg CC_REGNUM)
3789 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3790 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
3791 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3792 "s390_match_ccmode(insn, CCLmode)"
3793 "@
3794 al<g>r\t%0,%2
3795 al<g>\t%0,%2
3796 al<y>\t%0,%2"
3797 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3799 (define_insn "*add<mode>3_imm_cc"
3800 [(set (reg CC_REGNUM)
3801 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3802 (match_operand:GPR 2 "const_int_operand" "K,Os"))
3803 (const_int 0)))
3804 (set (match_operand:GPR 0 "register_operand" "=d,d")
3805 (plus:GPR (match_dup 1) (match_dup 2)))]
3806 "s390_match_ccmode (insn, CCAmode)
3807 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3808 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3809 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
3810 "@
3811 a<g>hi\t%0,%h2
3812 a<g>fi\t%0,%2"
3813 [(set_attr "op_type" "RI,RIL")])
3815 ;
3816 ; add(df|sf)3 instruction pattern(s).
3817 ;
3819 (define_expand "add<mode>3"
3820 [(parallel
3821 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3822 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3823 (match_operand:FPR 2 "general_operand" "f,<Rf>")))
3824 (clobber (reg:CC CC_REGNUM))])]
3825 "TARGET_HARD_FLOAT"
3826 "")
3828 (define_insn "*add<mode>3"
3829 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3830 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3831 (match_operand:FPR 2 "general_operand" "f,<Rf>")))
3832 (clobber (reg:CC CC_REGNUM))]
3833 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3834 "@
3835 a<xde>br\t%0,%2
3836 a<xde>b\t%0,%2"
3837 [(set_attr "op_type" "RRE,RXE")
3838 (set_attr "type" "fsimp<mode>")])
3840 (define_insn "*add<mode>3_cc"
3841 [(set (reg CC_REGNUM)
3842 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3843 (match_operand:FPR 2 "general_operand" "f,<Rf>"))
3844 (match_operand:FPR 3 "const0_operand" "")))
3845 (set (match_operand:FPR 0 "register_operand" "=f,f")
3846 (plus:FPR (match_dup 1) (match_dup 2)))]
3847 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3848 "@
3849 a<xde>br\t%0,%2
3850 a<xde>b\t%0,%2"
3851 [(set_attr "op_type" "RRE,RXE")
3852 (set_attr "type" "fsimp<mode>")])
3854 (define_insn "*add<mode>3_cconly"
3855 [(set (reg CC_REGNUM)
3856 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3857 (match_operand:FPR 2 "general_operand" "f,<Rf>"))
3858 (match_operand:FPR 3 "const0_operand" "")))
3859 (clobber (match_scratch:FPR 0 "=f,f"))]
3860 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3861 "@
3862 a<xde>br\t%0,%2
3863 a<xde>b\t%0,%2"
3864 [(set_attr "op_type" "RRE,RXE")
3865 (set_attr "type" "fsimp<mode>")])
3867 (define_insn "*add<mode>3_ibm"
3868 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3869 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3870 (match_operand:FPR 2 "general_operand" "f,<Rf>")))
3871 (clobber (reg:CC CC_REGNUM))]
3872 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3873 "@
3874 a<xde>r\t%0,%2
3875 a<xde>\t%0,%2"
3876 [(set_attr "op_type" "<RRe>,<RXe>")
3877 (set_attr "type" "fsimp<mode>")])
3880 ;;
3881 ;;- Subtract instructions.
3882 ;;
3884 ;
3885 ; subti3 instruction pattern(s).
3886 ;
3888 (define_insn_and_split "subti3"
3889 [(set (match_operand:TI 0 "register_operand" "=&d")
3890 (minus:TI (match_operand:TI 1 "register_operand" "0")
3891 (match_operand:TI 2 "general_operand" "do") ) )
3892 (clobber (reg:CC CC_REGNUM))]
3893 "TARGET_64BIT"
3894 "#"
3895 "&& reload_completed"
3896 [(parallel
3897 [(set (reg:CCL2 CC_REGNUM)
3898 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3899 (match_dup 7)))
3900 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3901 (parallel
3902 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3903 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3904 (clobber (reg:CC CC_REGNUM))])]
3905 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3906 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3907 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3908 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3909 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3910 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3912 ;
3913 ; subdi3 instruction pattern(s).
3914 ;
3916 (define_expand "subdi3"
3917 [(parallel
3918 [(set (match_operand:DI 0 "register_operand" "")
3919 (minus:DI (match_operand:DI 1 "register_operand" "")
3920 (match_operand:DI 2 "general_operand" "")))
3921 (clobber (reg:CC CC_REGNUM))])]
3922 ""
3923 "")
3925 (define_insn "*subdi3_sign"
3926 [(set (match_operand:DI 0 "register_operand" "=d,d")
3927 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3928 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3929 (clobber (reg:CC CC_REGNUM))]
3930 "TARGET_64BIT"
3931 "@
3932 sgfr\t%0,%2
3933 sgf\t%0,%2"
3934 [(set_attr "op_type" "RRE,RXY")])
3936 (define_insn "*subdi3_zero_cc"
3937 [(set (reg CC_REGNUM)
3938 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3939 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3940 (const_int 0)))
3941 (set (match_operand:DI 0 "register_operand" "=d,d")
3942 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3943 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3944 "@
3945 slgfr\t%0,%2
3946 slgf\t%0,%2"
3947 [(set_attr "op_type" "RRE,RXY")])
3949 (define_insn "*subdi3_zero_cconly"
3950 [(set (reg CC_REGNUM)
3951 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3952 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3953 (const_int 0)))
3954 (clobber (match_scratch:DI 0 "=d,d"))]
3955 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3956 "@
3957 slgfr\t%0,%2
3958 slgf\t%0,%2"
3959 [(set_attr "op_type" "RRE,RXY")])
3961 (define_insn "*subdi3_zero"
3962 [(set (match_operand:DI 0 "register_operand" "=d,d")
3963 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3964 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3965 (clobber (reg:CC CC_REGNUM))]
3966 "TARGET_64BIT"
3967 "@
3968 slgfr\t%0,%2
3969 slgf\t%0,%2"
3970 [(set_attr "op_type" "RRE,RXY")])
3972 (define_insn_and_split "*subdi3_31z"
3973 [(set (match_operand:DI 0 "register_operand" "=&d")
3974 (minus:DI (match_operand:DI 1 "register_operand" "0")
3975 (match_operand:DI 2 "general_operand" "do") ) )
3976 (clobber (reg:CC CC_REGNUM))]
3977 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3978 "#"
3979 "&& reload_completed"
3980 [(parallel
3981 [(set (reg:CCL2 CC_REGNUM)
3982 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3983 (match_dup 7)))
3984 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3985 (parallel
3986 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3987 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3988 (clobber (reg:CC CC_REGNUM))])]
3989 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3990 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3991 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3992 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3993 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3994 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3996 (define_insn_and_split "*subdi3_31"
3997 [(set (match_operand:DI 0 "register_operand" "=&d")
3998 (minus:DI (match_operand:DI 1 "register_operand" "0")
3999 (match_operand:DI 2 "general_operand" "do") ) )
4000 (clobber (reg:CC CC_REGNUM))]
4001 "!TARGET_CPU_ZARCH"
4002 "#"
4003 "&& reload_completed"
4004 [(parallel
4005 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4006 (clobber (reg:CC CC_REGNUM))])
4007 (parallel
4008 [(set (reg:CCL2 CC_REGNUM)
4009 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4010 (match_dup 7)))
4011 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4012 (set (pc)
4013 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4014 (pc)
4015 (label_ref (match_dup 9))))
4016 (parallel
4017 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4018 (clobber (reg:CC CC_REGNUM))])
4019 (match_dup 9)]
4020 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4021 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4022 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4023 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4024 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4025 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4026 operands[9] = gen_label_rtx ();")
4028 ;
4029 ; subsi3 instruction pattern(s).
4030 ;
4032 (define_expand "subsi3"
4033 [(parallel
4034 [(set (match_operand:SI 0 "register_operand" "")
4035 (minus:SI (match_operand:SI 1 "register_operand" "")
4036 (match_operand:SI 2 "general_operand" "")))
4037 (clobber (reg:CC CC_REGNUM))])]
4038 ""
4039 "")
4041 (define_insn "*subsi3_sign"
4042 [(set (match_operand:SI 0 "register_operand" "=d,d")
4043 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4044 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4045 (clobber (reg:CC CC_REGNUM))]
4046 ""
4047 "@
4048 sh\t%0,%2
4049 shy\t%0,%2"
4050 [(set_attr "op_type" "RX,RXY")])
4052 ;
4053 ; sub(di|si)3 instruction pattern(s).
4054 ;
4056 (define_insn "*sub<mode>3"
4057 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4058 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4059 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4060 (clobber (reg:CC CC_REGNUM))]
4061 ""
4062 "@
4063 s<g>r\t%0,%2
4064 s<g>\t%0,%2
4065 s<y>\t%0,%2"
4066 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4068 (define_insn "*sub<mode>3_borrow_cc"
4069 [(set (reg CC_REGNUM)
4070 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4071 (match_operand:GPR 2 "general_operand" "d,R,T"))
4072 (match_dup 1)))
4073 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4074 (minus:GPR (match_dup 1) (match_dup 2)))]
4075 "s390_match_ccmode (insn, CCL2mode)"
4076 "@
4077 sl<g>r\t%0,%2
4078 sl<g>\t%0,%2
4079 sl<y>\t%0,%2"
4080 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4082 (define_insn "*sub<mode>3_borrow_cconly"
4083 [(set (reg CC_REGNUM)
4084 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4085 (match_operand:GPR 2 "general_operand" "d,R,T"))
4086 (match_dup 1)))
4087 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4088 "s390_match_ccmode (insn, CCL2mode)"
4089 "@
4090 sl<g>r\t%0,%2
4091 sl<g>\t%0,%2
4092 sl<y>\t%0,%2"
4093 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4095 (define_insn "*sub<mode>3_cc"
4096 [(set (reg CC_REGNUM)
4097 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4098 (match_operand:GPR 2 "general_operand" "d,R,T"))
4099 (const_int 0)))
4100 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4101 (minus:GPR (match_dup 1) (match_dup 2)))]
4102 "s390_match_ccmode (insn, CCLmode)"
4103 "@
4104 sl<g>r\t%0,%2
4105 sl<g>\t%0,%2
4106 sl<y>\t%0,%2"
4107 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4109 (define_insn "*sub<mode>3_cc2"
4110 [(set (reg CC_REGNUM)
4111 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4112 (match_operand:GPR 2 "general_operand" "d,R,T")))
4113 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4114 (minus:GPR (match_dup 1) (match_dup 2)))]
4115 "s390_match_ccmode (insn, CCL3mode)"
4116 "@
4117 sl<g>r\t%0,%2
4118 sl<g>\t%0,%2
4119 sl<y>\t%0,%2"
4120 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4122 (define_insn "*sub<mode>3_cconly"
4123 [(set (reg CC_REGNUM)
4124 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4125 (match_operand:GPR 2 "general_operand" "d,R,T"))
4126 (const_int 0)))
4127 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4128 "s390_match_ccmode (insn, CCLmode)"
4129 "@
4130 sl<g>r\t%0,%2
4131 sl<g>\t%0,%2
4132 sl<y>\t%0,%2"
4133 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4135 (define_insn "*sub<mode>3_cconly2"
4136 [(set (reg CC_REGNUM)
4137 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4138 (match_operand:GPR 2 "general_operand" "d,R,T")))
4139 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4140 "s390_match_ccmode (insn, CCL3mode)"
4141 "@
4142 sl<g>r\t%0,%2
4143 sl<g>\t%0,%2
4144 sl<y>\t%0,%2"
4145 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4147 ;
4148 ; sub(df|sf)3 instruction pattern(s).
4149 ;
4151 (define_expand "sub<mode>3"
4152 [(parallel
4153 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4154 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4155 (match_operand:FPR 2 "general_operand" "f,R")))
4156 (clobber (reg:CC CC_REGNUM))])]
4157 "TARGET_HARD_FLOAT"
4158 "")
4160 (define_insn "*sub<mode>3"
4161 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4162 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4163 (match_operand:FPR 2 "general_operand" "f,<Rf>")))
4164 (clobber (reg:CC CC_REGNUM))]
4165 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4166 "@
4167 s<xde>br\t%0,%2
4168 s<xde>b\t%0,%2"
4169 [(set_attr "op_type" "RRE,RXE")
4170 (set_attr "type" "fsimp<mode>")])
4172 (define_insn "*sub<mode>3_cc"
4173 [(set (reg CC_REGNUM)
4174 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4175 (match_operand:FPR 2 "general_operand" "f,<Rf>"))
4176 (match_operand:FPR 3 "const0_operand" "")))
4177 (set (match_operand:FPR 0 "register_operand" "=f,f")
4178 (minus:FPR (match_dup 1) (match_dup 2)))]
4179 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4180 "@
4181 s<xde>br\t%0,%2
4182 s<xde>b\t%0,%2"
4183 [(set_attr "op_type" "RRE,RXE")
4184 (set_attr "type" "fsimp<mode>")])
4186 (define_insn "*sub<mode>3_cconly"
4187 [(set (reg CC_REGNUM)
4188 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4189 (match_operand:FPR 2 "general_operand" "f,<Rf>"))
4190 (match_operand:FPR 3 "const0_operand" "")))
4191 (clobber (match_scratch:FPR 0 "=f,f"))]
4192 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4193 "@
4194 s<xde>br\t%0,%2
4195 s<xde>b\t%0,%2"
4196 [(set_attr "op_type" "RRE,RXE")
4197 (set_attr "type" "fsimp<mode>")])
4199 (define_insn "*sub<mode>3_ibm"
4200 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4201 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4202 (match_operand:FPR 2 "general_operand" "f,<Rf>")))
4203 (clobber (reg:CC CC_REGNUM))]
4204 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4205 "@
4206 s<xde>r\t%0,%2
4207 s<xde>\t%0,%2"
4208 [(set_attr "op_type" "<RRe>,<RXe>")
4209 (set_attr "type" "fsimp<mode>")])
4212 ;;
4213 ;;- Conditional add/subtract instructions.
4214 ;;
4216 ;
4217 ; add(di|si)cc instruction pattern(s).
4218 ;
4220 (define_insn "*add<mode>3_alc_cc"
4221 [(set (reg CC_REGNUM)
4222 (compare
4223 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4224 (match_operand:GPR 2 "general_operand" "d,m"))
4225 (match_operand:GPR 3 "s390_alc_comparison" ""))
4226 (const_int 0)))
4227 (set (match_operand:GPR 0 "register_operand" "=d,d")
4228 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4229 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4230 "@
4231 alc<g>r\t%0,%2
4232 alc<g>\t%0,%2"
4233 [(set_attr "op_type" "RRE,RXY")])
4235 (define_insn "*add<mode>3_alc"
4236 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4237 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4238 (match_operand:GPR 2 "general_operand" "d,m"))
4239 (match_operand:GPR 3 "s390_alc_comparison" "")))
4240 (clobber (reg:CC CC_REGNUM))]
4241 "TARGET_CPU_ZARCH"
4242 "@
4243 alc<g>r\t%0,%2
4244 alc<g>\t%0,%2"
4245 [(set_attr "op_type" "RRE,RXY")])
4247 (define_insn "*sub<mode>3_slb_cc"
4248 [(set (reg CC_REGNUM)
4249 (compare
4250 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4251 (match_operand:GPR 2 "general_operand" "d,m"))
4252 (match_operand:GPR 3 "s390_slb_comparison" ""))
4253 (const_int 0)))
4254 (set (match_operand:GPR 0 "register_operand" "=d,d")
4255 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4256 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4257 "@
4258 slb<g>r\t%0,%2
4259 slb<g>\t%0,%2"
4260 [(set_attr "op_type" "RRE,RXY")])
4262 (define_insn "*sub<mode>3_slb"
4263 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4264 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4265 (match_operand:GPR 2 "general_operand" "d,m"))
4266 (match_operand:GPR 3 "s390_slb_comparison" "")))
4267 (clobber (reg:CC CC_REGNUM))]
4268 "TARGET_CPU_ZARCH"
4269 "@
4270 slb<g>r\t%0,%2
4271 slb<g>\t%0,%2"
4272 [(set_attr "op_type" "RRE,RXY")])
4274 (define_expand "add<mode>cc"
4275 [(match_operand:GPR 0 "register_operand" "")
4276 (match_operand 1 "comparison_operator" "")
4277 (match_operand:GPR 2 "register_operand" "")
4278 (match_operand:GPR 3 "const_int_operand" "")]
4279 "TARGET_CPU_ZARCH"
4280 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4281 s390_compare_op0, s390_compare_op1,
4282 operands[0], operands[2],
4283 operands[3])) FAIL; DONE;")
4285 ;
4286 ; scond instruction pattern(s).
4287 ;
4289 (define_insn_and_split "*scond<mode>"
4290 [(set (match_operand:GPR 0 "register_operand" "=&d")
4291 (match_operand:GPR 1 "s390_alc_comparison" ""))
4292 (clobber (reg:CC CC_REGNUM))]
4293 "TARGET_CPU_ZARCH"
4294 "#"
4295 "&& reload_completed"
4296 [(set (match_dup 0) (const_int 0))
4297 (parallel
4298 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4299 (match_dup 1)))
4300 (clobber (reg:CC CC_REGNUM))])]
4301 "")
4303 (define_insn_and_split "*scond<mode>_neg"
4304 [(set (match_operand:GPR 0 "register_operand" "=&d")
4305 (match_operand:GPR 1 "s390_slb_comparison" ""))
4306 (clobber (reg:CC CC_REGNUM))]
4307 "TARGET_CPU_ZARCH"
4308 "#"
4309 "&& reload_completed"
4310 [(set (match_dup 0) (const_int 0))
4311 (parallel
4312 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4313 (match_dup 1)))
4314 (clobber (reg:CC CC_REGNUM))])
4315 (parallel
4316 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4317 (clobber (reg:CC CC_REGNUM))])]
4318 "")
4321 (define_expand "s<code>"
4322 [(set (match_operand:SI 0 "register_operand" "")
4323 (SCOND (match_dup 0)
4324 (match_dup 0)))]
4325 "TARGET_CPU_ZARCH"
4326 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4327 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4329 (define_expand "seq"
4330 [(parallel
4331 [(set (match_operand:SI 0 "register_operand" "=d")
4332 (match_dup 1))
4333 (clobber (reg:CC CC_REGNUM))])
4334 (parallel
4335 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4336 (clobber (reg:CC CC_REGNUM))])]
4337 ""
4338 {
4339 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4340 FAIL;
4341 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4342 PUT_MODE (operands[1], SImode);
4343 })
4345 (define_insn_and_split "*sne"
4346 [(set (match_operand:SI 0 "register_operand" "=d")
4347 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4348 (const_int 0)))
4349 (clobber (reg:CC CC_REGNUM))]
4350 ""
4351 "#"
4352 "reload_completed"
4353 [(parallel
4354 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4355 (clobber (reg:CC CC_REGNUM))])])
4358 ;;
4359 ;;- Multiply instructions.
4360 ;;
4362 ;
4363 ; muldi3 instruction pattern(s).
4364 ;
4366 (define_insn "*muldi3_sign"
4367 [(set (match_operand:DI 0 "register_operand" "=d,d")
4368 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4369 (match_operand:DI 1 "register_operand" "0,0")))]
4370 "TARGET_64BIT"
4371 "@
4372 msgfr\t%0,%2
4373 msgf\t%0,%2"
4374 [(set_attr "op_type" "RRE,RXY")
4375 (set_attr "type" "imuldi")])
4377 (define_insn "muldi3"
4378 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4379 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4380 (match_operand:DI 2 "general_operand" "d,K,m")))]
4381 "TARGET_64BIT"
4382 "@
4383 msgr\t%0,%2
4384 mghi\t%0,%h2
4385 msg\t%0,%2"
4386 [(set_attr "op_type" "RRE,RI,RXY")
4387 (set_attr "type" "imuldi")])
4389 ;
4390 ; mulsi3 instruction pattern(s).
4391 ;
4393 (define_insn "*mulsi3_sign"
4394 [(set (match_operand:SI 0 "register_operand" "=d")
4395 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4396 (match_operand:SI 1 "register_operand" "0")))]
4397 ""
4398 "mh\t%0,%2"
4399 [(set_attr "op_type" "RX")
4400 (set_attr "type" "imulhi")])
4402 (define_insn "mulsi3"
4403 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4404 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4405 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4406 ""
4407 "@
4408 msr\t%0,%2
4409 mhi\t%0,%h2
4410 ms\t%0,%2
4411 msy\t%0,%2"
4412 [(set_attr "op_type" "RRE,RI,RX,RXY")
4413 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4415 ;
4416 ; mulsidi3 instruction pattern(s).
4417 ;
4419 (define_insn "mulsidi3"
4420 [(set (match_operand:DI 0 "register_operand" "=d,d")
4421 (mult:DI (sign_extend:DI
4422 (match_operand:SI 1 "register_operand" "%0,0"))
4423 (sign_extend:DI
4424 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4425 "!TARGET_64BIT"
4426 "@
4427 mr\t%0,%2
4428 m\t%0,%2"
4429 [(set_attr "op_type" "RR,RX")
4430 (set_attr "type" "imulsi")])
4432 ;
4433 ; umulsidi3 instruction pattern(s).
4434 ;
4436 (define_insn "umulsidi3"
4437 [(set (match_operand:DI 0 "register_operand" "=d,d")
4438 (mult:DI (zero_extend:DI
4439 (match_operand:SI 1 "register_operand" "%0,0"))
4440 (zero_extend:DI
4441 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4442 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4443 "@
4444 mlr\t%0,%2
4445 ml\t%0,%2"
4446 [(set_attr "op_type" "RRE,RXY")
4447 (set_attr "type" "imulsi")])
4449 ;
4450 ; mul(df|sf)3 instruction pattern(s).
4451 ;
4453 (define_expand "mul<mode>3"
4454 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4455 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4456 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4457 "TARGET_HARD_FLOAT"
4458 "")
4460 (define_insn "*mul<mode>3"
4461 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4462 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4463 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4464 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4465 "@
4466 m<xdee>br\t%0,%2
4467 m<xdee>b\t%0,%2"
4468 [(set_attr "op_type" "RRE,RXE")
4469 (set_attr "type" "fmul<mode>")])
4471 (define_insn "*mul<mode>3_ibm"
4472 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4473 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4474 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4475 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4476 "@
4477 m<xde>r\t%0,%2
4478 m<xde>\t%0,%2"
4479 [(set_attr "op_type" "<RRe>,<RXe>")
4480 (set_attr "type" "fmul<mode>")])
4482 (define_insn "*fmadd<mode>"
4483 [(set (match_operand:DSF 0 "register_operand" "=f,f")
4484 (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
4485 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
4486 (match_operand:DSF 3 "register_operand" "0,0")))]
4487 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4488 "@
4489 ma<xde>br\t%0,%1,%2
4490 ma<xde>b\t%0,%1,%2"
4491 [(set_attr "op_type" "RRE,RXE")
4492 (set_attr "type" "fmul<mode>")])
4494 (define_insn "*fmsub<mode>"
4495 [(set (match_operand:DSF 0 "register_operand" "=f,f")
4496 (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
4497 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
4498 (match_operand:DSF 3 "register_operand" "0,0")))]
4499 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4500 "@
4501 ms<xde>br\t%0,%1,%2
4502 ms<xde>b\t%0,%1,%2"
4503 [(set_attr "op_type" "RRE,RXE")
4504 (set_attr "type" "fmul<mode>")])
4506 ;;
4507 ;;- Divide and modulo instructions.
4508 ;;
4510 ;
4511 ; divmoddi4 instruction pattern(s).
4512 ;
4514 (define_expand "divmoddi4"
4515 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4516 (div:DI (match_operand:DI 1 "register_operand" "")
4517 (match_operand:DI 2 "general_operand" "")))
4518 (set (match_operand:DI 3 "general_operand" "")
4519 (mod:DI (match_dup 1) (match_dup 2)))])
4520 (clobber (match_dup 4))]
4521 "TARGET_64BIT"
4522 {
4523 rtx insn, div_equal, mod_equal;
4525 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4526 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4528 operands[4] = gen_reg_rtx(TImode);
4529 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4531 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4532 REG_NOTES (insn) =
4533 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4535 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4536 REG_NOTES (insn) =
4537 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4539 DONE;
4540 })
4542 (define_insn "divmodtidi3"
4543 [(set (match_operand:TI 0 "register_operand" "=d,d")
4544 (ior:TI
4545 (ashift:TI
4546 (zero_extend:TI
4547 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4548 (match_operand:DI 2 "general_operand" "d,m")))
4549 (const_int 64))
4550 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4551 "TARGET_64BIT"
4552 "@
4553 dsgr\t%0,%2
4554 dsg\t%0,%2"
4555 [(set_attr "op_type" "RRE,RXY")
4556 (set_attr "type" "idiv")])
4558 (define_insn "divmodtisi3"
4559 [(set (match_operand:TI 0 "register_operand" "=d,d")
4560 (ior:TI
4561 (ashift:TI
4562 (zero_extend:TI
4563 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4564 (sign_extend:DI
4565 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4566 (const_int 64))
4567 (zero_extend:TI
4568 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4569 "TARGET_64BIT"
4570 "@
4571 dsgfr\t%0,%2
4572 dsgf\t%0,%2"
4573 [(set_attr "op_type" "RRE,RXY")
4574 (set_attr "type" "idiv")])
4576 ;
4577 ; udivmoddi4 instruction pattern(s).
4578 ;
4580 (define_expand "udivmoddi4"
4581 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4582 (udiv:DI (match_operand:DI 1 "general_operand" "")
4583 (match_operand:DI 2 "nonimmediate_operand" "")))
4584 (set (match_operand:DI 3 "general_operand" "")
4585 (umod:DI (match_dup 1) (match_dup 2)))])
4586 (clobber (match_dup 4))]
4587 "TARGET_64BIT"
4588 {
4589 rtx insn, div_equal, mod_equal, equal;
4591 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4592 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4593 equal = gen_rtx_IOR (TImode,
4594 gen_rtx_ASHIFT (TImode,
4595 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4596 GEN_INT (64)),
4597 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4599 operands[4] = gen_reg_rtx(TImode);
4600 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4601 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4602 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4603 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4604 REG_NOTES (insn) =
4605 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4607 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4608 REG_NOTES (insn) =
4609 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4611 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4612 REG_NOTES (insn) =
4613 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4615 DONE;
4616 })
4618 (define_insn "udivmodtidi3"
4619 [(set (match_operand:TI 0 "register_operand" "=d,d")
4620 (ior:TI
4621 (ashift:TI
4622 (zero_extend:TI
4623 (truncate:DI
4624 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4625 (zero_extend:TI
4626 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4627 (const_int 64))
4628 (zero_extend:TI
4629 (truncate:DI
4630 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4631 "TARGET_64BIT"
4632 "@
4633 dlgr\t%0,%2
4634 dlg\t%0,%2"
4635 [(set_attr "op_type" "RRE,RXY")
4636 (set_attr "type" "idiv")])
4638 ;
4639 ; divmodsi4 instruction pattern(s).
4640 ;
4642 (define_expand "divmodsi4"
4643 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4644 (div:SI (match_operand:SI 1 "general_operand" "")
4645 (match_operand:SI 2 "nonimmediate_operand" "")))
4646 (set (match_operand:SI 3 "general_operand" "")
4647 (mod:SI (match_dup 1) (match_dup 2)))])
4648 (clobber (match_dup 4))]
4649 "!TARGET_64BIT"
4650 {
4651 rtx insn, div_equal, mod_equal, equal;
4653 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4654 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4655 equal = gen_rtx_IOR (DImode,
4656 gen_rtx_ASHIFT (DImode,
4657 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4658 GEN_INT (32)),
4659 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4661 operands[4] = gen_reg_rtx(DImode);
4662 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4663 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4664 REG_NOTES (insn) =
4665 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4667 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4668 REG_NOTES (insn) =
4669 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4671 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4672 REG_NOTES (insn) =
4673 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4675 DONE;
4676 })
4678 (define_insn "divmoddisi3"
4679 [(set (match_operand:DI 0 "register_operand" "=d,d")
4680 (ior:DI
4681 (ashift:DI
4682 (zero_extend:DI
4683 (truncate:SI
4684 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4685 (sign_extend:DI
4686 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4687 (const_int 32))
4688 (zero_extend:DI
4689 (truncate:SI
4690 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4691 "!TARGET_64BIT"
4692 "@
4693 dr\t%0,%2
4694 d\t%0,%2"
4695 [(set_attr "op_type" "RR,RX")
4696 (set_attr "type" "idiv")])
4698 ;
4699 ; udivsi3 and umodsi3 instruction pattern(s).
4700 ;
4702 (define_expand "udivmodsi4"
4703 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4704 (udiv:SI (match_operand:SI 1 "general_operand" "")
4705 (match_operand:SI 2 "nonimmediate_operand" "")))
4706 (set (match_operand:SI 3 "general_operand" "")
4707 (umod:SI (match_dup 1) (match_dup 2)))])
4708 (clobber (match_dup 4))]
4709 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4710 {
4711 rtx insn, div_equal, mod_equal, equal;
4713 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4714 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4715 equal = gen_rtx_IOR (DImode,
4716 gen_rtx_ASHIFT (DImode,
4717 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4718 GEN_INT (32)),
4719 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4721 operands[4] = gen_reg_rtx(DImode);
4722 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4723 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4724 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4725 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4726 REG_NOTES (insn) =
4727 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4729 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4730 REG_NOTES (insn) =
4731 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4733 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4734 REG_NOTES (insn) =
4735 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4737 DONE;
4738 })
4740 (define_insn "udivmoddisi3"
4741 [(set (match_operand:DI 0 "register_operand" "=d,d")
4742 (ior:DI
4743 (ashift:DI
4744 (zero_extend:DI
4745 (truncate:SI
4746 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4747 (zero_extend:DI
4748 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4749 (const_int 32))
4750 (zero_extend:DI
4751 (truncate:SI
4752 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4753 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4754 "@
4755 dlr\t%0,%2
4756 dl\t%0,%2"
4757 [(set_attr "op_type" "RRE,RXY")
4758 (set_attr "type" "idiv")])
4760 (define_expand "udivsi3"
4761 [(set (match_operand:SI 0 "register_operand" "=d")
4762 (udiv:SI (match_operand:SI 1 "general_operand" "")
4763 (match_operand:SI 2 "general_operand" "")))
4764 (clobber (match_dup 3))]
4765 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4766 {
4767 rtx insn, udiv_equal, umod_equal, equal;
4769 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4770 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4771 equal = gen_rtx_IOR (DImode,
4772 gen_rtx_ASHIFT (DImode,
4773 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4774 GEN_INT (32)),
4775 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4777 operands[3] = gen_reg_rtx (DImode);
4779 if (CONSTANT_P (operands[2]))
4780 {
4781 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4782 {
4783 rtx label1 = gen_label_rtx ();
4785 operands[1] = make_safe_from (operands[1], operands[0]);
4786 emit_move_insn (operands[0], const0_rtx);
4787 emit_insn (gen_cmpsi (operands[1], operands[2]));
4788 emit_jump_insn (gen_bltu (label1));
4789 emit_move_insn (operands[0], const1_rtx);
4790 emit_label (label1);
4791 }
4792 else
4793 {
4794 operands[2] = force_reg (SImode, operands[2]);
4795 operands[2] = make_safe_from (operands[2], operands[0]);
4797 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4798 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4799 operands[2]));
4800 REG_NOTES (insn) =
4801 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4803 insn = emit_move_insn (operands[0],
4804 gen_lowpart (SImode, operands[3]));
4805 REG_NOTES (insn) =
4806 gen_rtx_EXPR_LIST (REG_EQUAL,
4807 udiv_equal, REG_NOTES (insn));
4808 }
4809 }
4810 else
4811 {
4812 rtx label1 = gen_label_rtx ();
4813 rtx label2 = gen_label_rtx ();
4814 rtx label3 = gen_label_rtx ();
4816 operands[1] = force_reg (SImode, operands[1]);
4817 operands[1] = make_safe_from (operands[1], operands[0]);
4818 operands[2] = force_reg (SImode, operands[2]);
4819 operands[2] = make_safe_from (operands[2], operands[0]);
4821 emit_move_insn (operands[0], const0_rtx);
4822 emit_insn (gen_cmpsi (operands[2], operands[1]));
4823 emit_jump_insn (gen_bgtu (label3));
4824 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4825 emit_jump_insn (gen_blt (label2));
4826 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4827 emit_jump_insn (gen_beq (label1));
4828 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4829 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4830 operands[2]));
4831 REG_NOTES (insn) =
4832 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4834 insn = emit_move_insn (operands[0],
4835 gen_lowpart (SImode, operands[3]));
4836 REG_NOTES (insn) =
4837 gen_rtx_EXPR_LIST (REG_EQUAL,
4838 udiv_equal, REG_NOTES (insn));
4839 emit_jump (label3);
4840 emit_label (label1);
4841 emit_move_insn (operands[0], operands[1]);
4842 emit_jump (label3);
4843 emit_label (label2);
4844 emit_move_insn (operands[0], const1_rtx);
4845 emit_label (label3);
4846 }
4847 emit_move_insn (operands[0], operands[0]);
4848 DONE;
4849 })
4851 (define_expand "umodsi3"
4852 [(set (match_operand:SI 0 "register_operand" "=d")
4853 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4854 (match_operand:SI 2 "nonimmediate_operand" "")))
4855 (clobber (match_dup 3))]
4856 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4857 {
4858 rtx insn, udiv_equal, umod_equal, equal;
4860 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4861 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4862 equal = gen_rtx_IOR (DImode,
4863 gen_rtx_ASHIFT (DImode,
4864 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4865 GEN_INT (32)),
4866 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4868 operands[3] = gen_reg_rtx (DImode);
4870 if (CONSTANT_P (operands[2]))
4871 {
4872 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4873 {
4874 rtx label1 = gen_label_rtx ();
4876 operands[1] = make_safe_from (operands[1], operands[0]);
4877 emit_move_insn (operands[0], operands[1]);
4878 emit_insn (gen_cmpsi (operands[0], operands[2]));
4879 emit_jump_insn (gen_bltu (label1));
4880 emit_insn (gen_abssi2 (operands[0], operands[2]));
4881 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4882 emit_label (label1);
4883 }
4884 else
4885 {
4886 operands[2] = force_reg (SImode, operands[2]);
4887 operands[2] = make_safe_from (operands[2], operands[0]);
4889 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4890 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4891 operands[2]));
4892 REG_NOTES (insn) =
4893 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4895 insn = emit_move_insn (operands[0],
4896 gen_highpart (SImode, operands[3]));
4897 REG_NOTES (insn) =
4898 gen_rtx_EXPR_LIST (REG_EQUAL,
4899 umod_equal, REG_NOTES (insn));
4900 }
4901 }
4902 else
4903 {
4904 rtx label1 = gen_label_rtx ();
4905 rtx label2 = gen_label_rtx ();
4906 rtx label3 = gen_label_rtx ();
4908 operands[1] = force_reg (SImode, operands[1]);
4909 operands[1] = make_safe_from (operands[1], operands[0]);
4910 operands[2] = force_reg (SImode, operands[2]);
4911 operands[2] = make_safe_from (operands[2], operands[0]);
4913 emit_move_insn(operands[0], operands[1]);
4914 emit_insn (gen_cmpsi (operands[2], operands[1]));
4915 emit_jump_insn (gen_bgtu (label3));
4916 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4917 emit_jump_insn (gen_blt (label2));
4918 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4919 emit_jump_insn (gen_beq (label1));
4920 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4921 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4922 operands[2]));
4923 REG_NOTES (insn) =
4924 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4926 insn = emit_move_insn (operands[0],
4927 gen_highpart (SImode, operands[3]));
4928 REG_NOTES (insn) =
4929 gen_rtx_EXPR_LIST (REG_EQUAL,
4930 umod_equal, REG_NOTES (insn));
4931 emit_jump (label3);
4932 emit_label (label1);
4933 emit_move_insn (operands[0], const0_rtx);
4934 emit_jump (label3);
4935 emit_label (label2);
4936 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4937 emit_label (label3);
4938 }
4939 DONE;
4940 })
4942 ;
4943 ; div(df|sf)3 instruction pattern(s).
4944 ;
4946 (define_expand "div<mode>3"
4947 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4948 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4949 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4950 "TARGET_HARD_FLOAT"
4951 "")
4953 (define_insn "*div<mode>3"
4954 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4955 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4956 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4957 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4958 "@
4959 d<xde>br\t%0,%2
4960 d<xde>b\t%0,%2"
4961 [(set_attr "op_type" "RRE,RXE")
4962 (set_attr "type" "fdiv<mode>")])
4964 (define_insn "*div<mode>3_ibm"
4965 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4966 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4967 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4968 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4969 "@
4970 d<xde>r\t%0,%2
4971 d<xde>\t%0,%2"
4972 [(set_attr "op_type" "<RRe>,<RXe>")
4973 (set_attr "type" "fdiv<mode>")])
4976 ;;
4977 ;;- And instructions.
4978 ;;
4980 (define_expand "and<mode>3"
4981 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4982 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4983 (match_operand:INT 2 "general_operand" "")))
4984 (clobber (reg:CC CC_REGNUM))]
4985 ""
4986 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4988 ;
4989 ; anddi3 instruction pattern(s).
4990 ;
4992 (define_insn "*anddi3_cc"
4993 [(set (reg CC_REGNUM)
4994 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4995 (match_operand:DI 2 "general_operand" "d,m"))
4996 (const_int 0)))
4997 (set (match_operand:DI 0 "register_operand" "=d,d")
4998 (and:DI (match_dup 1) (match_dup 2)))]
4999 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5000 "@
5001 ngr\t%0,%2
5002 ng\t%0,%2"
5003 [(set_attr "op_type" "RRE,RXY")])
5005 (define_insn "*anddi3_cconly"
5006 [(set (reg CC_REGNUM)
5007 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5008 (match_operand:DI 2 "general_operand" "d,m"))
5009 (const_int 0)))
5010 (clobber (match_scratch:DI 0 "=d,d"))]
5011 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5012 /* Do not steal TM patterns. */
5013 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5014 "@
5015 ngr\t%0,%2
5016 ng\t%0,%2"
5017 [(set_attr "op_type" "RRE,RXY")])
5019 (define_insn "*anddi3_extimm"
5020 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5021 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5022 "%d,o,0,0,0,0,0,0,0,0,0,0")
5023 (match_operand:DI 2 "general_operand"
5024 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
5025 (clobber (reg:CC CC_REGNUM))]
5026 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5027 "@
5028 #
5029 #
5030 nihh\t%0,%j2
5031 nihl\t%0,%j2
5032 nilh\t%0,%j2
5033 nill\t%0,%j2
5034 nihf\t%0,%m2
5035 nilf\t%0,%m2
5036 ngr\t%0,%2
5037 ng\t%0,%2
5038 #
5039 #"
5040 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5042 (define_insn "*anddi3"
5043 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5044 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5045 "%d,o,0,0,0,0,0,0,0,0")
5046 (match_operand:DI 2 "general_operand"
5047 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5048 (clobber (reg:CC CC_REGNUM))]
5049 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5050 "@
5051 #
5052 #
5053 nihh\t%0,%j2
5054 nihl\t%0,%j2
5055 nilh\t%0,%j2
5056 nill\t%0,%j2
5057 ngr\t%0,%2
5058 ng\t%0,%2
5059 #
5060 #"
5061 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5063 (define_split
5064 [(set (match_operand:DI 0 "s_operand" "")
5065 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5066 (clobber (reg:CC CC_REGNUM))]
5067 "reload_completed"
5068 [(parallel
5069 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5070 (clobber (reg:CC CC_REGNUM))])]
5071 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5074 ;
5075 ; andsi3 instruction pattern(s).
5076 ;
5078 (define_insn "*andsi3_cc"
5079 [(set (reg CC_REGNUM)
5080 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5081 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5082 (const_int 0)))
5083 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5084 (and:SI (match_dup 1) (match_dup 2)))]
5085 "s390_match_ccmode(insn, CCTmode)"
5086 "@
5087 nilf\t%0,%o2
5088 nr\t%0,%2
5089 n\t%0,%2
5090 ny\t%0,%2"
5091 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5093 (define_insn "*andsi3_cconly"
5094 [(set (reg CC_REGNUM)
5095 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5096 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5097 (const_int 0)))
5098 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5099 "s390_match_ccmode(insn, CCTmode)
5100 /* Do not steal TM patterns. */
5101 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5102 "@
5103 nilf\t%0,%o2
5104 nr\t%0,%2
5105 n\t%0,%2
5106 ny\t%0,%2"
5107 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5109 (define_insn "*andsi3_zarch"
5110 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5111 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5112 "%d,o,0,0,0,0,0,0,0,0")
5113 (match_operand:SI 2 "general_operand"
5114 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5115 (clobber (reg:CC CC_REGNUM))]
5116 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5117 "@
5118 #
5119 #
5120 nilh\t%0,%j2
5121 nill\t%0,%j2
5122 nilf\t%0,%o2
5123 nr\t%0,%2
5124 n\t%0,%2
5125 ny\t%0,%2
5126 #
5127 #"
5128 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
5130 (define_insn "*andsi3_esa"
5131 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5132 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5133 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5134 (clobber (reg:CC CC_REGNUM))]
5135 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5136 "@
5137 nr\t%0,%2
5138 n\t%0,%2
5139 #
5140 #"
5141 [(set_attr "op_type" "RR,RX,SI,SS")])
5143 (define_split
5144 [(set (match_operand:SI 0 "s_operand" "")
5145 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5146 (clobber (reg:CC CC_REGNUM))]
5147 "reload_completed"
5148 [(parallel
5149 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5150 (clobber (reg:CC CC_REGNUM))])]
5151 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5153 ;
5154 ; andhi3 instruction pattern(s).
5155 ;
5157 (define_insn "*andhi3_zarch"
5158 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5159 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5160 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5161 (clobber (reg:CC CC_REGNUM))]
5162 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5163 "@
5164 nr\t%0,%2
5165 nill\t%0,%x2
5166 #
5167 #"
5168 [(set_attr "op_type" "RR,RI,SI,SS")])
5170 (define_insn "*andhi3_esa"
5171 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5172 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5173 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5174 (clobber (reg:CC CC_REGNUM))]
5175 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5176 "@
5177 nr\t%0,%2
5178 #
5179 #"
5180 [(set_attr "op_type" "RR,SI,SS")])
5182 (define_split
5183 [(set (match_operand:HI 0 "s_operand" "")
5184 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5185 (clobber (reg:CC CC_REGNUM))]
5186 "reload_completed"
5187 [(parallel
5188 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5189 (clobber (reg:CC CC_REGNUM))])]
5190 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5192 ;
5193 ; andqi3 instruction pattern(s).
5194 ;
5196 (define_insn "*andqi3_zarch"
5197 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5198 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5199 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5200 (clobber (reg:CC CC_REGNUM))]
5201 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5202 "@
5203 nr\t%0,%2
5204 nill\t%0,%b2
5205 ni\t%S0,%b2
5206 niy\t%S0,%b2
5207 #"
5208 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5210 (define_insn "*andqi3_esa"
5211 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5212 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5213 (match_operand:QI 2 "general_operand" "d,n,Q")))
5214 (clobber (reg:CC CC_REGNUM))]
5215 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5216 "@
5217 nr\t%0,%2
5218 ni\t%S0,%b2
5219 #"
5220 [(set_attr "op_type" "RR,SI,SS")])
5222 ;
5223 ; Block and (NC) patterns.
5224 ;
5226 (define_insn "*nc"
5227 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5228 (and:BLK (match_dup 0)
5229 (match_operand:BLK 1 "memory_operand" "Q")))
5230 (use (match_operand 2 "const_int_operand" "n"))
5231 (clobber (reg:CC CC_REGNUM))]
5232 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5233 "nc\t%O0(%2,%R0),%S1"
5234 [(set_attr "op_type" "SS")])
5236 (define_split
5237 [(set (match_operand 0 "memory_operand" "")
5238 (and (match_dup 0)
5239 (match_operand 1 "memory_operand" "")))
5240 (clobber (reg:CC CC_REGNUM))]
5241 "reload_completed
5242 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5243 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5244 [(parallel
5245 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5246 (use (match_dup 2))
5247 (clobber (reg:CC CC_REGNUM))])]
5248 {
5249 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5250 operands[0] = adjust_address (operands[0], BLKmode, 0);
5251 operands[1] = adjust_address (operands[1], BLKmode, 0);
5252 })
5254 (define_peephole2
5255 [(parallel
5256 [(set (match_operand:BLK 0 "memory_operand" "")
5257 (and:BLK (match_dup 0)
5258 (match_operand:BLK 1 "memory_operand" "")))
5259 (use (match_operand 2 "const_int_operand" ""))
5260 (clobber (reg:CC CC_REGNUM))])
5261 (parallel
5262 [(set (match_operand:BLK 3 "memory_operand" "")
5263 (and:BLK (match_dup 3)
5264 (match_operand:BLK 4 "memory_operand" "")))
5265 (use (match_operand 5 "const_int_operand" ""))
5266 (clobber (reg:CC CC_REGNUM))])]
5267 "s390_offset_p (operands[0], operands[3], operands[2])
5268 && s390_offset_p (operands[1], operands[4], operands[2])
5269 && !s390_overlap_p (operands[0], operands[1],
5270 INTVAL (operands[2]) + INTVAL (operands[5]))
5271 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5272 [(parallel
5273 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5274 (use (match_dup 8))
5275 (clobber (reg:CC CC_REGNUM))])]
5276 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5277 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5278 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5281 ;;
5282 ;;- Bit set (inclusive or) instructions.
5283 ;;
5285 (define_expand "ior<mode>3"
5286 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5287 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5288 (match_operand:INT 2 "general_operand" "")))
5289 (clobber (reg:CC CC_REGNUM))]
5290 ""
5291 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5293 ;
5294 ; iordi3 instruction pattern(s).
5295 ;
5297 (define_insn "*iordi3_cc"
5298 [(set (reg CC_REGNUM)
5299 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5300 (match_operand:DI 2 "general_operand" "d,m"))
5301 (const_int 0)))
5302 (set (match_operand:DI 0 "register_operand" "=d,d")
5303 (ior:DI (match_dup 1) (match_dup 2)))]
5304 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5305 "@
5306 ogr\t%0,%2
5307 og\t%0,%2"
5308 [(set_attr "op_type" "RRE,RXY")])
5310 (define_insn "*iordi3_cconly"
5311 [(set (reg CC_REGNUM)
5312 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5313 (match_operand:DI 2 "general_operand" "d,m"))
5314 (const_int 0)))
5315 (clobber (match_scratch:DI 0 "=d,d"))]
5316 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5317 "@
5318 ogr\t%0,%2
5319 og\t%0,%2"
5320 [(set_attr "op_type" "RRE,RXY")])
5322 (define_insn "*iordi3_extimm"
5323 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5324 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5325 (match_operand:DI 2 "general_operand"
5326 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5327 (clobber (reg:CC CC_REGNUM))]
5328 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5329 "@
5330 oihh\t%0,%i2
5331 oihl\t%0,%i2
5332 oilh\t%0,%i2
5333 oill\t%0,%i2
5334 oihf\t%0,%k2
5335 oilf\t%0,%k2
5336 ogr\t%0,%2
5337 og\t%0,%2
5338 #
5339 #"
5340 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5342 (define_insn "*iordi3"
5343 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5344 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5345 (match_operand:DI 2 "general_operand"
5346 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5347 (clobber (reg:CC CC_REGNUM))]
5348 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5349 "@
5350 oihh\t%0,%i2
5351 oihl\t%0,%i2
5352 oilh\t%0,%i2
5353 oill\t%0,%i2
5354 ogr\t%0,%2
5355 og\t%0,%2
5356 #
5357 #"
5358 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5360 (define_split
5361 [(set (match_operand:DI 0 "s_operand" "")
5362 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5363 (clobber (reg:CC CC_REGNUM))]
5364 "reload_completed"
5365 [(parallel
5366 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5367 (clobber (reg:CC CC_REGNUM))])]
5368 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5370 ;
5371 ; iorsi3 instruction pattern(s).
5372 ;
5374 (define_insn "*iorsi3_cc"
5375 [(set (reg CC_REGNUM)
5376 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5377 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5378 (const_int 0)))
5379 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5380 (ior:SI (match_dup 1) (match_dup 2)))]
5381 "s390_match_ccmode(insn, CCTmode)"
5382 "@
5383 oilf\t%0,%o2
5384 or\t%0,%2
5385 o\t%0,%2
5386 oy\t%0,%2"
5387 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5389 (define_insn "*iorsi3_cconly"
5390 [(set (reg CC_REGNUM)
5391 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5392 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5393 (const_int 0)))
5394 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5395 "s390_match_ccmode(insn, CCTmode)"
5396 "@
5397 oilf\t%0,%o2
5398 or\t%0,%2
5399 o\t%0,%2
5400 oy\t%0,%2"
5401 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5403 (define_insn "*iorsi3_zarch"
5404 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5405 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5406 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5407 (clobber (reg:CC CC_REGNUM))]
5408 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5409 "@
5410 oilh\t%0,%i2
5411 oill\t%0,%i2
5412 oilf\t%0,%o2
5413 or\t%0,%2
5414 o\t%0,%2
5415 oy\t%0,%2
5416 #
5417 #"
5418 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5420 (define_insn "*iorsi3_esa"
5421 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5422 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5423 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5424 (clobber (reg:CC CC_REGNUM))]
5425 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5426 "@
5427 or\t%0,%2
5428 o\t%0,%2
5429 #
5430 #"
5431 [(set_attr "op_type" "RR,RX,SI,SS")])
5433 (define_split
5434 [(set (match_operand:SI 0 "s_operand" "")
5435 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5436 (clobber (reg:CC CC_REGNUM))]
5437 "reload_completed"
5438 [(parallel
5439 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5440 (clobber (reg:CC CC_REGNUM))])]
5441 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5443 ;
5444 ; iorhi3 instruction pattern(s).
5445 ;
5447 (define_insn "*iorhi3_zarch"
5448 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5449 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5450 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5451 (clobber (reg:CC CC_REGNUM))]
5452 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5453 "@
5454 or\t%0,%2
5455 oill\t%0,%x2
5456 #
5457 #"
5458 [(set_attr "op_type" "RR,RI,SI,SS")])
5460 (define_insn "*iorhi3_esa"
5461 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5462 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5463 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5464 (clobber (reg:CC CC_REGNUM))]
5465 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5466 "@
5467 or\t%0,%2
5468 #
5469 #"
5470 [(set_attr "op_type" "RR,SI,SS")])
5472 (define_split
5473 [(set (match_operand:HI 0 "s_operand" "")
5474 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5475 (clobber (reg:CC CC_REGNUM))]
5476 "reload_completed"
5477 [(parallel
5478 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5479 (clobber (reg:CC CC_REGNUM))])]
5480 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5482 ;
5483 ; iorqi3 instruction pattern(s).
5484 ;
5486 (define_insn "*iorqi3_zarch"
5487 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5488 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5489 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5490 (clobber (reg:CC CC_REGNUM))]
5491 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5492 "@
5493 or\t%0,%2
5494 oill\t%0,%b2
5495 oi\t%S0,%b2
5496 oiy\t%S0,%b2
5497 #"
5498 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5500 (define_insn "*iorqi3_esa"
5501 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5502 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5503 (match_operand:QI 2 "general_operand" "d,n,Q")))
5504 (clobber (reg:CC CC_REGNUM))]
5505 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5506 "@
5507 or\t%0,%2
5508 oi\t%S0,%b2
5509 #"
5510 [(set_attr "op_type" "RR,SI,SS")])
5512 ;
5513 ; Block inclusive or (OC) patterns.
5514 ;
5516 (define_insn "*oc"
5517 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5518 (ior:BLK (match_dup 0)
5519 (match_operand:BLK 1 "memory_operand" "Q")))
5520 (use (match_operand 2 "const_int_operand" "n"))
5521 (clobber (reg:CC CC_REGNUM))]
5522 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5523 "oc\t%O0(%2,%R0),%S1"
5524 [(set_attr "op_type" "SS")])
5526 (define_split
5527 [(set (match_operand 0 "memory_operand" "")
5528 (ior (match_dup 0)
5529 (match_operand 1 "memory_operand" "")))
5530 (clobber (reg:CC CC_REGNUM))]
5531 "reload_completed
5532 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5533 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5534 [(parallel
5535 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5536 (use (match_dup 2))
5537 (clobber (reg:CC CC_REGNUM))])]
5538 {
5539 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5540 operands[0] = adjust_address (operands[0], BLKmode, 0);
5541 operands[1] = adjust_address (operands[1], BLKmode, 0);
5542 })
5544 (define_peephole2
5545 [(parallel
5546 [(set (match_operand:BLK 0 "memory_operand" "")
5547 (ior:BLK (match_dup 0)
5548 (match_operand:BLK 1 "memory_operand" "")))
5549 (use (match_operand 2 "const_int_operand" ""))
5550 (clobber (reg:CC CC_REGNUM))])
5551 (parallel
5552 [(set (match_operand:BLK 3 "memory_operand" "")
5553 (ior:BLK (match_dup 3)
5554 (match_operand:BLK 4 "memory_operand" "")))
5555 (use (match_operand 5 "const_int_operand" ""))
5556 (clobber (reg:CC CC_REGNUM))])]
5557 "s390_offset_p (operands[0], operands[3], operands[2])
5558 && s390_offset_p (operands[1], operands[4], operands[2])
5559 && !s390_overlap_p (operands[0], operands[1],
5560 INTVAL (operands[2]) + INTVAL (operands[5]))
5561 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5562 [(parallel
5563 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5564 (use (match_dup 8))
5565 (clobber (reg:CC CC_REGNUM))])]
5566 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5567 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5568 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5571 ;;
5572 ;;- Xor instructions.
5573 ;;
5575 (define_expand "xor<mode>3"
5576 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5577 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5578 (match_operand:INT 2 "general_operand" "")))
5579 (clobber (reg:CC CC_REGNUM))]
5580 ""
5581 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5583 ;
5584 ; xordi3 instruction pattern(s).
5585 ;
5587 (define_insn "*xordi3_cc"
5588 [(set (reg CC_REGNUM)
5589 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5590 (match_operand:DI 2 "general_operand" "d,m"))
5591 (const_int 0)))
5592 (set (match_operand:DI 0 "register_operand" "=d,d")
5593 (xor:DI (match_dup 1) (match_dup 2)))]
5594 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5595 "@
5596 xgr\t%0,%2
5597 xg\t%0,%2"
5598 [(set_attr "op_type" "RRE,RXY")])
5600 (define_insn "*xordi3_cconly"
5601 [(set (reg CC_REGNUM)
5602 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5603 (match_operand:DI 2 "general_operand" "d,m"))
5604 (const_int 0)))
5605 (clobber (match_scratch:DI 0 "=d,d"))]
5606 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5607 "@
5608 xgr\t%0,%2
5609 xr\t%0,%2"
5610 [(set_attr "op_type" "RRE,RXY")])
5612 (define_insn "*xordi3_extimm"
5613 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5614 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5615 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5616 (clobber (reg:CC CC_REGNUM))]
5617 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5618 "@
5619 xihf\t%0,%k2
5620 xilf\t%0,%k2
5621 xgr\t%0,%2
5622 xg\t%0,%2
5623 #
5624 #"
5625 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5627 (define_insn "*xordi3"
5628 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5629 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5630 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5631 (clobber (reg:CC CC_REGNUM))]
5632 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5633 "@
5634 xgr\t%0,%2
5635 xg\t%0,%2
5636 #
5637 #"
5638 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5640 (define_split
5641 [(set (match_operand:DI 0 "s_operand" "")
5642 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5643 (clobber (reg:CC CC_REGNUM))]
5644 "reload_completed"
5645 [(parallel
5646 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5647 (clobber (reg:CC CC_REGNUM))])]
5648 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5650 ;
5651 ; xorsi3 instruction pattern(s).
5652 ;
5654 (define_insn "*xorsi3_cc"
5655 [(set (reg CC_REGNUM)
5656 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5657 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5658 (const_int 0)))
5659 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5660 (xor:SI (match_dup 1) (match_dup 2)))]
5661 "s390_match_ccmode(insn, CCTmode)"
5662 "@
5663 xilf\t%0,%o2
5664 xr\t%0,%2
5665 x\t%0,%2
5666 xy\t%0,%2"
5667 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5669 (define_insn "*xorsi3_cconly"
5670 [(set (reg CC_REGNUM)
5671 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5672 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5673 (const_int 0)))
5674 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5675 "s390_match_ccmode(insn, CCTmode)"
5676 "@
5677 xilf\t%0,%o2
5678 xr\t%0,%2
5679 x\t%0,%2
5680 xy\t%0,%2"
5681 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5683 (define_insn "*xorsi3"
5684 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5685 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5686 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5687 (clobber (reg:CC CC_REGNUM))]
5688 "s390_logical_operator_ok_p (operands)"
5689 "@
5690 xilf\t%0,%o2
5691 xr\t%0,%2
5692 x\t%0,%2
5693 xy\t%0,%2
5694 #
5695 #"
5696 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5698 (define_split
5699 [(set (match_operand:SI 0 "s_operand" "")
5700 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5701 (clobber (reg:CC CC_REGNUM))]
5702 "reload_completed"
5703 [(parallel
5704 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5705 (clobber (reg:CC CC_REGNUM))])]
5706 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5708 ;
5709 ; xorhi3 instruction pattern(s).
5710 ;
5712 (define_insn "*xorhi3"
5713 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5714 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5715 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5716 (clobber (reg:CC CC_REGNUM))]
5717 "s390_logical_operator_ok_p (operands)"
5718 "@
5719 xilf\t%0,%x2
5720 xr\t%0,%2
5721 #
5722 #"
5723 [(set_attr "op_type" "RIL,RR,SI,SS")])
5725 (define_split
5726 [(set (match_operand:HI 0 "s_operand" "")
5727 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5728 (clobber (reg:CC CC_REGNUM))]
5729 "reload_completed"
5730 [(parallel
5731 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5732 (clobber (reg:CC CC_REGNUM))])]
5733 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5735 ;
5736 ; xorqi3 instruction pattern(s).
5737 ;
5739 (define_insn "*xorqi3"
5740 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5741 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5742 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5743 (clobber (reg:CC CC_REGNUM))]
5744 "s390_logical_operator_ok_p (operands)"
5745 "@
5746 xilf\t%0,%b2
5747 xr\t%0,%2
5748 xi\t%S0,%b2
5749 xiy\t%S0,%b2
5750 #"
5751 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5753 ;
5754 ; Block exclusive or (XC) patterns.
5755 ;
5757 (define_insn "*xc"
5758 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5759 (xor:BLK (match_dup 0)
5760 (match_operand:BLK 1 "memory_operand" "Q")))
5761 (use (match_operand 2 "const_int_operand" "n"))
5762 (clobber (reg:CC CC_REGNUM))]
5763 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5764 "xc\t%O0(%2,%R0),%S1"
5765 [(set_attr "op_type" "SS")])
5767 (define_split
5768 [(set (match_operand 0 "memory_operand" "")
5769 (xor (match_dup 0)
5770 (match_operand 1 "memory_operand" "")))
5771 (clobber (reg:CC CC_REGNUM))]
5772 "reload_completed
5773 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5774 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5775 [(parallel
5776 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5777 (use (match_dup 2))
5778 (clobber (reg:CC CC_REGNUM))])]
5779 {
5780 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5781 operands[0] = adjust_address (operands[0], BLKmode, 0);
5782 operands[1] = adjust_address (operands[1], BLKmode, 0);
5783 })
5785 (define_peephole2
5786 [(parallel
5787 [(set (match_operand:BLK 0 "memory_operand" "")
5788 (xor:BLK (match_dup 0)
5789 (match_operand:BLK 1 "memory_operand" "")))
5790 (use (match_operand 2 "const_int_operand" ""))
5791 (clobber (reg:CC CC_REGNUM))])
5792 (parallel
5793 [(set (match_operand:BLK 3 "memory_operand" "")
5794 (xor:BLK (match_dup 3)
5795 (match_operand:BLK 4 "memory_operand" "")))
5796 (use (match_operand 5 "const_int_operand" ""))
5797 (clobber (reg:CC CC_REGNUM))])]
5798 "s390_offset_p (operands[0], operands[3], operands[2])
5799 && s390_offset_p (operands[1], operands[4], operands[2])
5800 && !s390_overlap_p (operands[0], operands[1],
5801 INTVAL (operands[2]) + INTVAL (operands[5]))
5802 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5803 [(parallel
5804 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5805 (use (match_dup 8))
5806 (clobber (reg:CC CC_REGNUM))])]
5807 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5808 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5809 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5811 ;
5812 ; Block xor (XC) patterns with src == dest.
5813 ;
5815 (define_insn "*xc_zero"
5816 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5817 (const_int 0))
5818 (use (match_operand 1 "const_int_operand" "n"))
5819 (clobber (reg:CC CC_REGNUM))]
5820 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5821 "xc\t%O0(%1,%R0),%S0"
5822 [(set_attr "op_type" "SS")])
5824 (define_peephole2
5825 [(parallel
5826 [(set (match_operand:BLK 0 "memory_operand" "")
5827 (const_int 0))
5828 (use (match_operand 1 "const_int_operand" ""))
5829 (clobber (reg:CC CC_REGNUM))])
5830 (parallel
5831 [(set (match_operand:BLK 2 "memory_operand" "")
5832 (const_int 0))
5833 (use (match_operand 3 "const_int_operand" ""))
5834 (clobber (reg:CC CC_REGNUM))])]
5835 "s390_offset_p (operands[0], operands[2], operands[1])
5836 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5837 [(parallel
5838 [(set (match_dup 4) (const_int 0))
5839 (use (match_dup 5))
5840 (clobber (reg:CC CC_REGNUM))])]
5841 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5842 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5845 ;;
5846 ;;- Negate instructions.
5847 ;;
5849 ;
5850 ; neg(di|si)2 instruction pattern(s).
5851 ;
5853 (define_expand "neg<mode>2"
5854 [(parallel
5855 [(set (match_operand:DSI 0 "register_operand" "=d")
5856 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5857 (clobber (reg:CC CC_REGNUM))])]
5858 ""
5859 "")
5861 (define_insn "*negdi2_sign_cc"
5862 [(set (reg CC_REGNUM)
5863 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5864 (match_operand:SI 1 "register_operand" "d") 0)
5865 (const_int 32)) (const_int 32)))
5866 (const_int 0)))
5867 (set (match_operand:DI 0 "register_operand" "=d")
5868 (neg:DI (sign_extend:DI (match_dup 1))))]
5869 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5870 "lcgfr\t%0,%1"
5871 [(set_attr "op_type" "RRE")])
5873 (define_insn "*negdi2_sign"
5874 [(set (match_operand:DI 0 "register_operand" "=d")
5875 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5876 (clobber (reg:CC CC_REGNUM))]
5877 "TARGET_64BIT"
5878 "lcgfr\t%0,%1"
5879 [(set_attr "op_type" "RRE")])
5881 (define_insn "*neg<mode>2_cc"
5882 [(set (reg CC_REGNUM)
5883 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5884 (const_int 0)))
5885 (set (match_operand:GPR 0 "register_operand" "=d")
5886 (neg:GPR (match_dup 1)))]
5887 "s390_match_ccmode (insn, CCAmode)"
5888 "lc<g>r\t%0,%1"
5889 [(set_attr "op_type" "RR<E>")])
5891 (define_insn "*neg<mode>2_cconly"
5892 [(set (reg CC_REGNUM)
5893 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5894 (const_int 0)))
5895 (clobber (match_scratch:GPR 0 "=d"))]
5896 "s390_match_ccmode (insn, CCAmode)"
5897 "lc<g>r\t%0,%1"
5898 [(set_attr "op_type" "RR<E>")])
5900 (define_insn "*neg<mode>2"
5901 [(set (match_operand:GPR 0 "register_operand" "=d")
5902 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5903 (clobber (reg:CC CC_REGNUM))]
5904 ""
5905 "lc<g>r\t%0,%1"
5906 [(set_attr "op_type" "RR<E>")])
5908 (define_insn_and_split "*negdi2_31"
5909 [(set (match_operand:DI 0 "register_operand" "=d")
5910 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5911 (clobber (reg:CC CC_REGNUM))]
5912 "!TARGET_64BIT"
5913 "#"
5914 "&& reload_completed"
5915 [(parallel
5916 [(set (match_dup 2) (neg:SI (match_dup 3)))
5917 (clobber (reg:CC CC_REGNUM))])
5918 (parallel
5919 [(set (reg:CCAP CC_REGNUM)
5920 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5921 (set (match_dup 4) (neg:SI (match_dup 5)))])
5922 (set (pc)
5923 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5924 (pc)
5925 (label_ref (match_dup 6))))
5926 (parallel
5927 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5928 (clobber (reg:CC CC_REGNUM))])
5929 (match_dup 6)]
5930 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5931 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5932 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5933 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5934 operands[6] = gen_label_rtx ();")
5936 ;
5937 ; neg(df|sf)2 instruction pattern(s).
5938 ;
5940 (define_expand "neg<mode>2"
5941 [(parallel
5942 [(set (match_operand:FPR 0 "register_operand" "=f")
5943 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5944 (clobber (reg:CC CC_REGNUM))])]
5945 "TARGET_HARD_FLOAT"
5946 "")
5948 (define_insn "*neg<mode>2_cc"
5949 [(set (reg CC_REGNUM)
5950 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5951 (match_operand:FPR 2 "const0_operand" "")))
5952 (set (match_operand:FPR 0 "register_operand" "=f")
5953 (neg:FPR (match_dup 1)))]
5954 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5955 "lc<xde>br\t%0,%1"
5956 [(set_attr "op_type" "RRE")
5957 (set_attr "type" "fsimp<mode>")])
5959 (define_insn "*neg<mode>2_cconly"
5960 [(set (reg CC_REGNUM)
5961 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5962 (match_operand:FPR 2 "const0_operand" "")))
5963 (clobber (match_scratch:FPR 0 "=f"))]
5964 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5965 "lc<xde>br\t%0,%1"
5966 [(set_attr "op_type" "RRE")
5967 (set_attr "type" "fsimp<mode>")])
5969 (define_insn "*neg<mode>2"
5970 [(set (match_operand:FPR 0 "register_operand" "=f")
5971 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5972 (clobber (reg:CC CC_REGNUM))]
5973 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5974 "lc<xde>br\t%0,%1"
5975 [(set_attr "op_type" "RRE")
5976 (set_attr "type" "fsimp<mode>")])
5978 (define_insn "*neg<mode>2_ibm"
5979 [(set (match_operand:FPR 0 "register_operand" "=f")
5980 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5981 (clobber (reg:CC CC_REGNUM))]
5982 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5983 "lc<xde>r\t%0,%1"
5984 [(set_attr "op_type" "<RRe>")
5985 (set_attr "type" "fsimp<mode>")])
5988 ;;
5989 ;;- Absolute value instructions.
5990 ;;
5992 ;
5993 ; abs(di|si)2 instruction pattern(s).
5994 ;
5996 (define_insn "*absdi2_sign_cc"
5997 [(set (reg CC_REGNUM)
5998 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5999 (match_operand:SI 1 "register_operand" "d") 0)
6000 (const_int 32)) (const_int 32)))
6001 (const_int 0)))
6002 (set (match_operand:DI 0 "register_operand" "=d")
6003 (abs:DI (sign_extend:DI (match_dup 1))))]
6004 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6005 "lpgfr\t%0,%1"
6006 [(set_attr "op_type" "RRE")])
6008 (define_insn "*absdi2_sign"
6009 [(set (match_operand:DI 0 "register_operand" "=d")
6010 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6011 (clobber (reg:CC CC_REGNUM))]
6012 "TARGET_64BIT"
6013 "lpgfr\t%0,%1"
6014 [(set_attr "op_type" "RRE")])
6016 (define_insn "*abs<mode>2_cc"
6017 [(set (reg CC_REGNUM)
6018 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6019 (const_int 0)))
6020 (set (match_operand:GPR 0 "register_operand" "=d")
6021 (abs:GPR (match_dup 1)))]
6022 "s390_match_ccmode (insn, CCAmode)"
6023 "lp<g>r\t%0,%1"
6024 [(set_attr "op_type" "RR<E>")])
6026 (define_insn "*abs<mode>2_cconly"
6027 [(set (reg CC_REGNUM)
6028 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6029 (const_int 0)))
6030 (clobber (match_scratch:GPR 0 "=d"))]
6031 "s390_match_ccmode (insn, CCAmode)"
6032 "lp<g>r\t%0,%1"
6033 [(set_attr "op_type" "RR<E>")])
6035 (define_insn "abs<mode>2"
6036 [(set (match_operand:GPR 0 "register_operand" "=d")
6037 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6038 (clobber (reg:CC CC_REGNUM))]
6039 ""
6040 "lp<g>r\t%0,%1"
6041 [(set_attr "op_type" "RR<E>")])
6043 ;
6044 ; abs(df|sf)2 instruction pattern(s).
6045 ;
6047 (define_expand "abs<mode>2"
6048 [(parallel
6049 [(set (match_operand:FPR 0 "register_operand" "=f")
6050 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6051 (clobber (reg:CC CC_REGNUM))])]
6052 "TARGET_HARD_FLOAT"
6053 "")
6055 (define_insn "*abs<mode>2_cc"
6056 [(set (reg CC_REGNUM)
6057 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
6058 (match_operand:FPR 2 "const0_operand" "")))
6059 (set (match_operand:FPR 0 "register_operand" "=f")
6060 (abs:FPR (match_dup 1)))]
6061 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6062 "lp<xde>br\t%0,%1"
6063 [(set_attr "op_type" "RRE")
6064 (set_attr "type" "fsimp<mode>")])
6066 (define_insn "*abs<mode>2_cconly"
6067 [(set (reg CC_REGNUM)
6068 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
6069 (match_operand:FPR 2 "const0_operand" "")))
6070 (clobber (match_scratch:FPR 0 "=f"))]
6071 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6072 "lp<xde>br\t%0,%1"
6073 [(set_attr "op_type" "RRE")
6074 (set_attr "type" "fsimp<mode>")])
6076 (define_insn "*abs<mode>2"
6077 [(set (match_operand:FPR 0 "register_operand" "=f")
6078 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6079 (clobber (reg:CC CC_REGNUM))]
6080 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6081 "lp<xde>br\t%0,%1"
6082 [(set_attr "op_type" "RRE")
6083 (set_attr "type" "fsimp<mode>")])
6085 (define_insn "*abs<mode>2_ibm"
6086 [(set (match_operand:FPR 0 "register_operand" "=f")
6087 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6088 (clobber (reg:CC CC_REGNUM))]
6089 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6090 "lp<xde>r\t%0,%1"
6091 [(set_attr "op_type" "<RRe>")
6092 (set_attr "type" "fsimp<mode>")])
6094 ;;
6095 ;;- Negated absolute value instructions
6096 ;;
6098 ;
6099 ; Integer
6100 ;
6102 (define_insn "*negabsdi2_sign_cc"
6103 [(set (reg CC_REGNUM)
6104 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6105 (match_operand:SI 1 "register_operand" "d") 0)
6106 (const_int 32)) (const_int 32))))
6107 (const_int 0)))
6108 (set (match_operand:DI 0 "register_operand" "=d")
6109 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6110 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6111 "lngfr\t%0,%1"
6112 [(set_attr "op_type" "RRE")])
6114 (define_insn "*negabsdi2_sign"
6115 [(set (match_operand:DI 0 "register_operand" "=d")
6116 (neg:DI (abs:DI (sign_extend:DI
6117 (match_operand:SI 1 "register_operand" "d")))))
6118 (clobber (reg:CC CC_REGNUM))]
6119 "TARGET_64BIT"
6120 "lngfr\t%0,%1"
6121 [(set_attr "op_type" "RRE")])
6123 (define_insn "*negabs<mode>2_cc"
6124 [(set (reg CC_REGNUM)
6125 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6126 (const_int 0)))
6127 (set (match_operand:GPR 0 "register_operand" "=d")
6128 (neg:GPR (abs:GPR (match_dup 1))))]
6129 "s390_match_ccmode (insn, CCAmode)"
6130 "ln<g>r\t%0,%1"
6131 [(set_attr "op_type" "RR<E>")])
6133 (define_insn "*negabs<mode>2_cconly"
6134 [(set (reg CC_REGNUM)
6135 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6136 (const_int 0)))
6137 (clobber (match_scratch:GPR 0 "=d"))]
6138 "s390_match_ccmode (insn, CCAmode)"
6139 "ln<g>r\t%0,%1"
6140 [(set_attr "op_type" "RR<E>")])
6142 (define_insn "*negabs<mode>2"
6143 [(set (match_operand:GPR 0 "register_operand" "=d")
6144 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6145 (clobber (reg:CC CC_REGNUM))]
6146 ""
6147 "ln<g>r\t%0,%1"
6148 [(set_attr "op_type" "RR<E>")])
6150 ;
6151 ; Floating point
6152 ;
6154 (define_insn "*negabs<mode>2_cc"
6155 [(set (reg CC_REGNUM)
6156 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6157 (match_operand:FPR 2 "const0_operand" "")))
6158 (set (match_operand:FPR 0 "register_operand" "=f")
6159 (neg:FPR (abs:FPR (match_dup 1))))]
6160 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6161 "ln<xde>br\t%0,%1"
6162 [(set_attr "op_type" "RRE")
6163 (set_attr "type" "fsimp<mode>")])
6165 (define_insn "*negabs<mode>2_cconly"
6166 [(set (reg CC_REGNUM)
6167 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6168 (match_operand:FPR 2 "const0_operand" "")))
6169 (clobber (match_scratch:FPR 0 "=f"))]
6170 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6171 "ln<xde>br\t%0,%1"
6172 [(set_attr "op_type" "RRE")
6173 (set_attr "type" "fsimp<mode>")])
6175 (define_insn "*negabs<mode>2"
6176 [(set (match_operand:FPR 0 "register_operand" "=f")
6177 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
6178 (clobber (reg:CC CC_REGNUM))]
6179 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6180 "ln<xde>br\t%0,%1"
6181 [(set_attr "op_type" "RRE")
6182 (set_attr "type" "fsimp<mode>")])
6184 ;;
6185 ;;- Square root instructions.
6186 ;;
6188 ;
6189 ; sqrt(df|sf)2 instruction pattern(s).
6190 ;
6192 (define_insn "sqrt<mode>2"
6193 [(set (match_operand:FPR 0 "register_operand" "=f,f")
6194 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
6195 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6196 "@
6197 sq<xde>br\t%0,%1
6198 sq<xde>b\t%0,%1"
6199 [(set_attr "op_type" "RRE,RXE")
6200 (set_attr "type" "fsqrt<mode>")])
6203 ;;
6204 ;;- One complement instructions.
6205 ;;
6207 ;
6208 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6209 ;
6211 (define_expand "one_cmpl<mode>2"
6212 [(parallel
6213 [(set (match_operand:INT 0 "register_operand" "")
6214 (xor:INT (match_operand:INT 1 "register_operand" "")
6215 (const_int -1)))
6216 (clobber (reg:CC CC_REGNUM))])]
6217 ""
6218 "")
6221 ;;
6222 ;; Find leftmost bit instructions.
6223 ;;
6225 (define_expand "clzdi2"
6226 [(set (match_operand:DI 0 "register_operand" "=d")
6227 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6228 "TARGET_EXTIMM && TARGET_64BIT"
6229 {
6230 rtx insn, clz_equal;
6231 rtx wide_reg = gen_reg_rtx (TImode);
6232 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6234 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6236 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6238 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6239 REG_NOTES (insn) =
6240 gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
6242 DONE;
6243 })
6245 (define_insn "clztidi2"
6246 [(set (match_operand:TI 0 "register_operand" "=d")
6247 (ior:TI
6248 (ashift:TI
6249 (zero_extend:TI
6250 (xor:DI (match_operand:DI 1 "register_operand" "d")
6251 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6252 (subreg:SI (clz:DI (match_dup 1)) 4))))
6254 (const_int 64))
6255 (zero_extend:TI (clz:DI (match_dup 1)))))
6256 (clobber (reg:CC CC_REGNUM))]
6257 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6258 == (unsigned HOST_WIDE_INT) 1 << 63
6259 && TARGET_EXTIMM && TARGET_64BIT"
6260 "flogr\t%0,%1"
6261 [(set_attr "op_type" "RRE")])
6264 ;;
6265 ;;- Rotate instructions.
6266 ;;
6268 ;
6269 ; rotl(di|si)3 instruction pattern(s).
6270 ;
6272 (define_insn "rotl<mode>3"
6273 [(set (match_operand:GPR 0 "register_operand" "=d")
6274 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6275 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6276 "TARGET_CPU_ZARCH"
6277 "rll<g>\t%0,%1,%Y2"
6278 [(set_attr "op_type" "RSE")
6279 (set_attr "atype" "reg")])
6281 (define_insn "*rotl<mode>3_and"
6282 [(set (match_operand:GPR 0 "register_operand" "=d")
6283 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6284 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6285 (match_operand:SI 3 "const_int_operand" "n"))))]
6286 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
6287 "rll<g>\t%0,%1,%Y2"
6288 [(set_attr "op_type" "RSE")
6289 (set_attr "atype" "reg")])
6292 ;;
6293 ;;- Shift instructions.
6294 ;;
6296 ;
6297 ; (ashl|lshr)(di|si)3 instruction pattern(s).
6298 ;
6300 (define_expand "<shift><mode>3"
6301 [(set (match_operand:DSI 0 "register_operand" "")
6302 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
6303 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
6304 ""
6305 "")
6307 (define_insn "*<shift>di3_31"
6308 [(set (match_operand:DI 0 "register_operand" "=d")
6309 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6310 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6311 "!TARGET_64BIT"
6312 "s<lr>dl\t%0,%Y2"
6313 [(set_attr "op_type" "RS")
6314 (set_attr "atype" "reg")])
6316 (define_insn "*<shift><mode>3"
6317 [(set (match_operand:GPR 0 "register_operand" "=d")
6318 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6319 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6320 ""
6321 "s<lr>l<g>\t%0,<1>%Y2"
6322 [(set_attr "op_type" "RS<E>")
6323 (set_attr "atype" "reg")])
6325 (define_insn "*<shift>di3_31_and"
6326 [(set (match_operand:DI 0 "register_operand" "=d")
6327 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6328 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6329 (match_operand:SI 3 "const_int_operand" "n"))))]
6330 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6331 "s<lr>dl\t%0,%Y2"
6332 [(set_attr "op_type" "RS")
6333 (set_attr "atype" "reg")])
6335 (define_insn "*<shift><mode>3_and"
6336 [(set (match_operand:GPR 0 "register_operand" "=d")
6337 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6338 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6339 (match_operand:SI 3 "const_int_operand" "n"))))]
6340 "(INTVAL (operands[3]) & 63) == 63"
6341 "s<lr>l<g>\t%0,<1>%Y2"
6342 [(set_attr "op_type" "RS<E>")
6343 (set_attr "atype" "reg")])
6345 ;
6346 ; ashr(di|si)3 instruction pattern(s).
6347 ;
6349 (define_expand "ashr<mode>3"
6350 [(parallel
6351 [(set (match_operand:DSI 0 "register_operand" "")
6352 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
6353 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
6354 (clobber (reg:CC CC_REGNUM))])]
6355 ""
6356 "")
6358 (define_insn "*ashrdi3_cc_31"
6359 [(set (reg CC_REGNUM)
6360 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6361 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6362 (const_int 0)))
6363 (set (match_operand:DI 0 "register_operand" "=d")
6364 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6365 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6366 "srda\t%0,%Y2"
6367 [(set_attr "op_type" "RS")
6368 (set_attr "atype" "reg")])
6370 (define_insn "*ashrdi3_cconly_31"
6371 [(set (reg CC_REGNUM)
6372 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6373 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6374 (const_int 0)))
6375 (clobber (match_scratch:DI 0 "=d"))]
6376 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6377 "srda\t%0,%Y2"
6378 [(set_attr "op_type" "RS")
6379 (set_attr "atype" "reg")])
6381 (define_insn "*ashrdi3_31"
6382 [(set (match_operand:DI 0 "register_operand" "=d")
6383 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6384 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6385 (clobber (reg:CC CC_REGNUM))]
6386 "!TARGET_64BIT"
6387 "srda\t%0,%Y2"
6388 [(set_attr "op_type" "RS")
6389 (set_attr "atype" "reg")])
6391 (define_insn "*ashr<mode>3_cc"
6392 [(set (reg CC_REGNUM)
6393 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6394 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6395 (const_int 0)))
6396 (set (match_operand:GPR 0 "register_operand" "=d")
6397 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
6398 "s390_match_ccmode(insn, CCSmode)"
6399 "sra<g>\t%0,<1>%Y2"
6400 [(set_attr "op_type" "RS<E>")
6401 (set_attr "atype" "reg")])
6403 (define_insn "*ashr<mode>3_cconly"
6404 [(set (reg CC_REGNUM)
6405 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6406 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6407 (const_int 0)))
6408 (clobber (match_scratch:GPR 0 "=d"))]
6409 "s390_match_ccmode(insn, CCSmode)"
6410 "sra<g>\t%0,<1>%Y2"
6411 [(set_attr "op_type" "RS<E>")
6412 (set_attr "atype" "reg")])
6414 (define_insn "*ashr<mode>3"
6415 [(set (match_operand:GPR 0 "register_operand" "=d")
6416 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6417 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6418 (clobber (reg:CC CC_REGNUM))]
6419 ""
6420 "sra<g>\t%0,<1>%Y2"
6421 [(set_attr "op_type" "RS<E>")
6422 (set_attr "atype" "reg")])
6425 ; shift pattern with implicit ANDs
6427 (define_insn "*ashrdi3_cc_31_and"
6428 [(set (reg CC_REGNUM)
6429 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6430 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6431 (match_operand:SI 3 "const_int_operand" "n")))
6432 (const_int 0)))
6433 (set (match_operand:DI 0 "register_operand" "=d")
6434 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6435 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6436 && (INTVAL (operands[3]) & 63) == 63"
6437 "srda\t%0,%Y2"
6438 [(set_attr "op_type" "RS")
6439 (set_attr "atype" "reg")])
6441 (define_insn "*ashrdi3_cconly_31_and"
6442 [(set (reg CC_REGNUM)
6443 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6444 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6445 (match_operand:SI 3 "const_int_operand" "n")))
6446 (const_int 0)))
6447 (clobber (match_scratch:DI 0 "=d"))]
6448 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6449 && (INTVAL (operands[3]) & 63) == 63"
6450 "srda\t%0,%Y2"
6451 [(set_attr "op_type" "RS")
6452 (set_attr "atype" "reg")])
6454 (define_insn "*ashrdi3_31_and"
6455 [(set (match_operand:DI 0 "register_operand" "=d")
6456 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6457 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6458 (match_operand:SI 3 "const_int_operand" "n"))))
6459 (clobber (reg:CC CC_REGNUM))]
6460 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6461 "srda\t%0,%Y2"
6462 [(set_attr "op_type" "RS")
6463 (set_attr "atype" "reg")])
6465 (define_insn "*ashr<mode>3_cc_and"
6466 [(set (reg CC_REGNUM)
6467 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6468 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6469 (match_operand:SI 3 "const_int_operand" "n")))
6470 (const_int 0)))
6471 (set (match_operand:GPR 0 "register_operand" "=d")
6472 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6473 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6474 "sra<g>\t%0,<1>%Y2"
6475 [(set_attr "op_type" "RS<E>")
6476 (set_attr "atype" "reg")])
6478 (define_insn "*ashr<mode>3_cconly_and"
6479 [(set (reg CC_REGNUM)
6480 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6481 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6482 (match_operand:SI 3 "const_int_operand" "n")))
6483 (const_int 0)))
6484 (clobber (match_scratch:GPR 0 "=d"))]
6485 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6486 "sra<g>\t%0,<1>%Y2"
6487 [(set_attr "op_type" "RS<E>")
6488 (set_attr "atype" "reg")])
6490 (define_insn "*ashr<mode>3_and"
6491 [(set (match_operand:GPR 0 "register_operand" "=d")
6492 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6493 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6494 (match_operand:SI 3 "const_int_operand" "n"))))
6495 (clobber (reg:CC CC_REGNUM))]
6496 "(INTVAL (operands[3]) & 63) == 63"
6497 "sra<g>\t%0,<1>%Y2"
6498 [(set_attr "op_type" "RS<E>")
6499 (set_attr "atype" "reg")])
6502 ;;
6503 ;; Branch instruction patterns.
6504 ;;
6506 (define_expand "b<code>"
6507 [(set (pc)
6508 (if_then_else (COMPARE (match_operand 0 "" "")
6509 (const_int 0))
6510 (match_dup 0)
6511 (pc)))]
6512 ""
6513 "s390_emit_jump (operands[0],
6514 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6517 ;;
6518 ;;- Conditional jump instructions.
6519 ;;
6521 (define_insn "*cjump_64"
6522 [(set (pc)
6523 (if_then_else
6524 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6525 (label_ref (match_operand 0 "" ""))
6526 (pc)))]
6527 "TARGET_CPU_ZARCH"
6528 {
6529 if (get_attr_length (insn) == 4)
6530 return "j%C1\t%l0";
6531 else
6532 return "jg%C1\t%l0";
6533 }
6534 [(set_attr "op_type" "RI")
6535 (set_attr "type" "branch")
6536 (set (attr "length")
6537 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6538 (const_int 4) (const_int 6)))])
6540 (define_insn "*cjump_31"
6541 [(set (pc)
6542 (if_then_else
6543 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6544 (label_ref (match_operand 0 "" ""))
6545 (pc)))]
6546 "!TARGET_CPU_ZARCH"
6547 {
6548 gcc_assert (get_attr_length (insn) == 4);
6549 return "j%C1\t%l0";
6550 }
6551 [(set_attr "op_type" "RI")
6552 (set_attr "type" "branch")
6553 (set (attr "length")
6554 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6555 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6556 (const_int 4) (const_int 6))
6557 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6558 (const_int 4) (const_int 8))))])
6560 (define_insn "*cjump_long"
6561 [(set (pc)
6562 (if_then_else
6563 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6564 (match_operand 0 "address_operand" "U")
6565 (pc)))]
6566 ""
6567 {
6568 if (get_attr_op_type (insn) == OP_TYPE_RR)
6569 return "b%C1r\t%0";
6570 else
6571 return "b%C1\t%a0";
6572 }
6573 [(set (attr "op_type")
6574 (if_then_else (match_operand 0 "register_operand" "")
6575 (const_string "RR") (const_string "RX")))
6576 (set_attr "type" "branch")
6577 (set_attr "atype" "agen")])
6580 ;;
6581 ;;- Negated conditional jump instructions.
6582 ;;
6584 (define_insn "*icjump_64"
6585 [(set (pc)
6586 (if_then_else
6587 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6588 (pc)
6589 (label_ref (match_operand 0 "" ""))))]
6590 "TARGET_CPU_ZARCH"
6591 {
6592 if (get_attr_length (insn) == 4)
6593 return "j%D1\t%l0";
6594 else
6595 return "jg%D1\t%l0";
6596 }
6597 [(set_attr "op_type" "RI")
6598 (set_attr "type" "branch")
6599 (set (attr "length")
6600 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6601 (const_int 4) (const_int 6)))])
6603 (define_insn "*icjump_31"
6604 [(set (pc)
6605 (if_then_else
6606 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6607 (pc)
6608 (label_ref (match_operand 0 "" ""))))]
6609 "!TARGET_CPU_ZARCH"
6610 {
6611 gcc_assert (get_attr_length (insn) == 4);
6612 return "j%D1\t%l0";
6613 }
6614 [(set_attr "op_type" "RI")
6615 (set_attr "type" "branch")
6616 (set (attr "length")
6617 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6618 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6619 (const_int 4) (const_int 6))
6620 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6621 (const_int 4) (const_int 8))))])
6623 (define_insn "*icjump_long"
6624 [(set (pc)
6625 (if_then_else
6626 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6627 (pc)
6628 (match_operand 0 "address_operand" "U")))]
6629 ""
6630 {
6631 if (get_attr_op_type (insn) == OP_TYPE_RR)
6632 return "b%D1r\t%0";
6633 else
6634 return "b%D1\t%a0";
6635 }
6636 [(set (attr "op_type")
6637 (if_then_else (match_operand 0 "register_operand" "")
6638 (const_string "RR") (const_string "RX")))
6639 (set_attr "type" "branch")
6640 (set_attr "atype" "agen")])
6642 ;;
6643 ;;- Trap instructions.
6644 ;;
6646 (define_insn "trap"
6647 [(trap_if (const_int 1) (const_int 0))]
6648 ""
6649 "j\t.+2"
6650 [(set_attr "op_type" "RI")
6651 (set_attr "type" "branch")])
6653 (define_expand "conditional_trap"
6654 [(trap_if (match_operand 0 "comparison_operator" "")
6655 (match_operand 1 "general_operand" ""))]
6656 ""
6657 {
6658 if (operands[1] != const0_rtx) FAIL;
6659 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6660 s390_compare_op0, s390_compare_op1);
6661 })
6663 (define_insn "*trap"
6664 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6665 (const_int 0))]
6666 ""
6667 "j%C0\t.+2";
6668 [(set_attr "op_type" "RI")
6669 (set_attr "type" "branch")])
6671 ;;
6672 ;;- Loop instructions.
6673 ;;
6674 ;; This is all complicated by the fact that since this is a jump insn
6675 ;; we must handle our own output reloads.
6677 (define_expand "doloop_end"
6678 [(use (match_operand 0 "" "")) ; loop pseudo
6679 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6680 (use (match_operand 2 "" "")) ; max iterations
6681 (use (match_operand 3 "" "")) ; loop level
6682 (use (match_operand 4 "" ""))] ; label
6683 ""
6684 {
6685 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6686 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6687 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6688 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6689 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6690 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6691 else
6692 FAIL;
6694 DONE;
6695 })
6697 (define_insn_and_split "doloop_si64"
6698 [(set (pc)
6699 (if_then_else
6700 (ne (match_operand:SI 1 "register_operand" "d,d")
6701 (const_int 1))
6702 (label_ref (match_operand 0 "" ""))
6703 (pc)))
6704 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6705 (plus:SI (match_dup 1) (const_int -1)))
6706 (clobber (match_scratch:SI 3 "=X,&1"))
6707 (clobber (reg:CC CC_REGNUM))]
6708 "TARGET_CPU_ZARCH"
6709 {
6710 if (which_alternative != 0)
6711 return "#";
6712 else if (get_attr_length (insn) == 4)
6713 return "brct\t%1,%l0";
6714 else
6715 return "ahi\t%1,-1\;jgne\t%l0";
6716 }
6717 "&& reload_completed
6718 && (! REG_P (operands[2])
6719 || ! rtx_equal_p (operands[1], operands[2]))"
6720 [(parallel [(set (reg:CCAN CC_REGNUM)
6721 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6722 (const_int 0)))
6723 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6724 (set (match_dup 2) (match_dup 3))
6725 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6726 (label_ref (match_dup 0))
6727 (pc)))]
6728 ""
6729 [(set_attr "op_type" "RI")
6730 (set_attr "type" "branch")
6731 (set (attr "length")
6732 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6733 (const_int 4) (const_int 10)))])
6735 (define_insn_and_split "doloop_si31"
6736 [(set (pc)
6737 (if_then_else
6738 (ne (match_operand:SI 1 "register_operand" "d,d")
6739 (const_int 1))
6740 (label_ref (match_operand 0 "" ""))
6741 (pc)))
6742 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6743 (plus:SI (match_dup 1) (const_int -1)))
6744 (clobber (match_scratch:SI 3 "=X,&1"))
6745 (clobber (reg:CC CC_REGNUM))]
6746 "!TARGET_CPU_ZARCH"
6747 {
6748 if (which_alternative != 0)
6749 return "#";
6750 else if (get_attr_length (insn) == 4)
6751 return "brct\t%1,%l0";
6752 else
6753 gcc_unreachable ();
6754 }
6755 "&& reload_completed
6756 && (! REG_P (operands[2])
6757 || ! rtx_equal_p (operands[1], operands[2]))"
6758 [(parallel [(set (reg:CCAN CC_REGNUM)
6759 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6760 (const_int 0)))
6761 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6762 (set (match_dup 2) (match_dup 3))
6763 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6764 (label_ref (match_dup 0))
6765 (pc)))]
6766 ""
6767 [(set_attr "op_type" "RI")
6768 (set_attr "type" "branch")
6769 (set (attr "length")
6770 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6771 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6772 (const_int 4) (const_int 6))
6773 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6774 (const_int 4) (const_int 8))))])
6776 (define_insn "*doloop_si_long"
6777 [(set (pc)
6778 (if_then_else
6779 (ne (match_operand:SI 1 "register_operand" "d,d")
6780 (const_int 1))
6781 (match_operand 0 "address_operand" "U,U")
6782 (pc)))
6783 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6784 (plus:SI (match_dup 1) (const_int -1)))
6785 (clobber (match_scratch:SI 3 "=X,&1"))
6786 (clobber (reg:CC CC_REGNUM))]
6787 "!TARGET_CPU_ZARCH"
6788 {
6789 if (get_attr_op_type (insn) == OP_TYPE_RR)
6790 return "bctr\t%1,%0";
6791 else
6792 return "bct\t%1,%a0";
6793 }
6794 [(set (attr "op_type")
6795 (if_then_else (match_operand 0 "register_operand" "")
6796 (const_string "RR") (const_string "RX")))
6797 (set_attr "type" "branch")
6798 (set_attr "atype" "agen")])
6800 (define_insn_and_split "doloop_di"
6801 [(set (pc)
6802 (if_then_else
6803 (ne (match_operand:DI 1 "register_operand" "d,d")
6804 (const_int 1))
6805 (label_ref (match_operand 0 "" ""))
6806 (pc)))
6807 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6808 (plus:DI (match_dup 1) (const_int -1)))
6809 (clobber (match_scratch:DI 3 "=X,&1"))
6810 (clobber (reg:CC CC_REGNUM))]
6811 "TARGET_64BIT"
6812 {
6813 if (which_alternative != 0)
6814 return "#";
6815 else if (get_attr_length (insn) == 4)
6816 return "brctg\t%1,%l0";
6817 else
6818 return "aghi\t%1,-1\;jgne\t%l0";
6819 }
6820 "&& reload_completed
6821 && (! REG_P (operands[2])
6822 || ! rtx_equal_p (operands[1], operands[2]))"
6823 [(parallel [(set (reg:CCAN CC_REGNUM)
6824 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6825 (const_int 0)))
6826 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6827 (set (match_dup 2) (match_dup 3))
6828 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6829 (label_ref (match_dup 0))
6830 (pc)))]
6831 ""
6832 [(set_attr "op_type" "RI")
6833 (set_attr "type" "branch")
6834 (set (attr "length")
6835 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6836 (const_int 4) (const_int 10)))])
6838 ;;
6839 ;;- Unconditional jump instructions.
6840 ;;
6842 ;
6843 ; jump instruction pattern(s).
6844 ;
6846 (define_expand "jump"
6847 [(match_operand 0 "" "")]
6848 ""
6849 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6851 (define_insn "*jump64"
6852 [(set (pc) (label_ref (match_operand 0 "" "")))]
6853 "TARGET_CPU_ZARCH"
6854 {
6855 if (get_attr_length (insn) == 4)
6856 return "j\t%l0";
6857 else
6858 return "jg\t%l0";
6859 }
6860 [(set_attr "op_type" "RI")
6861 (set_attr "type" "branch")
6862 (set (attr "length")
6863 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6864 (const_int 4) (const_int 6)))])
6866 (define_insn "*jump31"
6867 [(set (pc) (label_ref (match_operand 0 "" "")))]
6868 "!TARGET_CPU_ZARCH"
6869 {
6870 gcc_assert (get_attr_length (insn) == 4);
6871 return "j\t%l0";
6872 }
6873 [(set_attr "op_type" "RI")
6874 (set_attr "type" "branch")
6875 (set (attr "length")
6876 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6877 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6878 (const_int 4) (const_int 6))
6879 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6880 (const_int 4) (const_int 8))))])
6882 ;
6883 ; indirect-jump instruction pattern(s).
6884 ;
6886 (define_insn "indirect_jump"
6887 [(set (pc) (match_operand 0 "address_operand" "U"))]
6888 ""
6889 {
6890 if (get_attr_op_type (insn) == OP_TYPE_RR)
6891 return "br\t%0";
6892 else
6893 return "b\t%a0";
6894 }
6895 [(set (attr "op_type")
6896 (if_then_else (match_operand 0 "register_operand" "")
6897 (const_string "RR") (const_string "RX")))
6898 (set_attr "type" "branch")
6899 (set_attr "atype" "agen")])
6901 ;
6902 ; casesi instruction pattern(s).
6903 ;
6905 (define_insn "casesi_jump"
6906 [(set (pc) (match_operand 0 "address_operand" "U"))
6907 (use (label_ref (match_operand 1 "" "")))]
6908 ""
6909 {
6910 if (get_attr_op_type (insn) == OP_TYPE_RR)
6911 return "br\t%0";
6912 else
6913 return "b\t%a0";
6914 }
6915 [(set (attr "op_type")
6916 (if_then_else (match_operand 0 "register_operand" "")
6917 (const_string "RR") (const_string "RX")))
6918 (set_attr "type" "branch")
6919 (set_attr "atype" "agen")])
6921 (define_expand "casesi"
6922 [(match_operand:SI 0 "general_operand" "")
6923 (match_operand:SI 1 "general_operand" "")
6924 (match_operand:SI 2 "general_operand" "")
6925 (label_ref (match_operand 3 "" ""))
6926 (label_ref (match_operand 4 "" ""))]
6927 ""
6928 {
6929 rtx index = gen_reg_rtx (SImode);
6930 rtx base = gen_reg_rtx (Pmode);
6931 rtx target = gen_reg_rtx (Pmode);
6933 emit_move_insn (index, operands[0]);
6934 emit_insn (gen_subsi3 (index, index, operands[1]));
6935 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6936 operands[4]);
6938 if (Pmode != SImode)
6939 index = convert_to_mode (Pmode, index, 1);
6940 if (GET_CODE (index) != REG)
6941 index = copy_to_mode_reg (Pmode, index);
6943 if (TARGET_64BIT)
6944 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6945 else
6946 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6948 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6950 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6951 emit_move_insn (target, index);
6953 if (flag_pic)
6954 target = gen_rtx_PLUS (Pmode, base, target);
6955 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6957 DONE;
6958 })
6961 ;;
6962 ;;- Jump to subroutine.
6963 ;;
6964 ;;
6966 ;
6967 ; untyped call instruction pattern(s).
6968 ;
6970 ;; Call subroutine returning any type.
6971 (define_expand "untyped_call"
6972 [(parallel [(call (match_operand 0 "" "")
6973 (const_int 0))
6974 (match_operand 1 "" "")
6975 (match_operand 2 "" "")])]
6976 ""
6977 {
6978 int i;
6980 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6982 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6983 {
6984 rtx set = XVECEXP (operands[2], 0, i);
6985 emit_move_insn (SET_DEST (set), SET_SRC (set));
6986 }
6988 /* The optimizer does not know that the call sets the function value
6989 registers we stored in the result block. We avoid problems by
6990 claiming that all hard registers are used and clobbered at this
6991 point. */
6992 emit_insn (gen_blockage ());
6994 DONE;
6995 })
6997 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6998 ;; all of memory. This blocks insns from being moved across this point.
7000 (define_insn "blockage"
7001 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7002 ""
7003 ""
7004 [(set_attr "type" "none")
7005 (set_attr "length" "0")])
7007 ;
7008 ; sibcall patterns
7009 ;
7011 (define_expand "sibcall"
7012 [(call (match_operand 0 "" "")
7013 (match_operand 1 "" ""))]
7014 ""
7015 {
7016 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7017 DONE;
7018 })
7020 (define_insn "*sibcall_br"
7021 [(call (mem:QI (reg SIBCALL_REGNUM))
7022 (match_operand 0 "const_int_operand" "n"))]
7023 "SIBLING_CALL_P (insn)
7024 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7025 "br\t%%r1"
7026 [(set_attr "op_type" "RR")
7027 (set_attr "type" "branch")
7028 (set_attr "atype" "agen")])
7030 (define_insn "*sibcall_brc"
7031 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7032 (match_operand 1 "const_int_operand" "n"))]
7033 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7034 "j\t%0"
7035 [(set_attr "op_type" "RI")
7036 (set_attr "type" "branch")])
7038 (define_insn "*sibcall_brcl"
7039 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7040 (match_operand 1 "const_int_operand" "n"))]
7041 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7042 "jg\t%0"
7043 [(set_attr "op_type" "RIL")
7044 (set_attr "type" "branch")])
7046 ;
7047 ; sibcall_value patterns
7048 ;
7050 (define_expand "sibcall_value"
7051 [(set (match_operand 0 "" "")
7052 (call (match_operand 1 "" "")
7053 (match_operand 2 "" "")))]
7054 ""
7055 {
7056 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7057 DONE;
7058 })
7060 (define_insn "*sibcall_value_br"
7061 [(set (match_operand 0 "" "")
7062 (call (mem:QI (reg SIBCALL_REGNUM))
7063 (match_operand 1 "const_int_operand" "n")))]
7064 "SIBLING_CALL_P (insn)
7065 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7066 "br\t%%r1"
7067 [(set_attr "op_type" "RR")
7068 (set_attr "type" "branch")
7069 (set_attr "atype" "agen")])
7071 (define_insn "*sibcall_value_brc"
7072 [(set (match_operand 0 "" "")
7073 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7074 (match_operand 2 "const_int_operand" "n")))]
7075 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7076 "j\t%1"
7077 [(set_attr "op_type" "RI")
7078 (set_attr "type" "branch")])
7080 (define_insn "*sibcall_value_brcl"
7081 [(set (match_operand 0 "" "")
7082 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7083 (match_operand 2 "const_int_operand" "n")))]
7084 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7085 "jg\t%1"
7086 [(set_attr "op_type" "RIL")
7087 (set_attr "type" "branch")])
7090 ;
7091 ; call instruction pattern(s).
7092 ;
7094 (define_expand "call"
7095 [(call (match_operand 0 "" "")
7096 (match_operand 1 "" ""))
7097 (use (match_operand 2 "" ""))]
7098 ""
7099 {
7100 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7101 gen_rtx_REG (Pmode, RETURN_REGNUM));
7102 DONE;
7103 })
7105 (define_insn "*bras"
7106 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7107 (match_operand 1 "const_int_operand" "n"))
7108 (clobber (match_operand 2 "register_operand" "=r"))]
7109 "!SIBLING_CALL_P (insn)
7110 && TARGET_SMALL_EXEC
7111 && GET_MODE (operands[2]) == Pmode"
7112 "bras\t%2,%0"
7113 [(set_attr "op_type" "RI")
7114 (set_attr "type" "jsr")])
7116 (define_insn "*brasl"
7117 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7118 (match_operand 1 "const_int_operand" "n"))
7119 (clobber (match_operand 2 "register_operand" "=r"))]
7120 "!SIBLING_CALL_P (insn)
7121 && TARGET_CPU_ZARCH
7122 && GET_MODE (operands[2]) == Pmode"
7123 "brasl\t%2,%0"
7124 [(set_attr "op_type" "RIL")
7125 (set_attr "type" "jsr")])
7127 (define_insn "*basr"
7128 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7129 (match_operand 1 "const_int_operand" "n"))
7130 (clobber (match_operand 2 "register_operand" "=r"))]
7131 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7132 {
7133 if (get_attr_op_type (insn) == OP_TYPE_RR)
7134 return "basr\t%2,%0";
7135 else
7136 return "bas\t%2,%a0";
7137 }
7138 [(set (attr "op_type")
7139 (if_then_else (match_operand 0 "register_operand" "")
7140 (const_string "RR") (const_string "RX")))
7141 (set_attr "type" "jsr")
7142 (set_attr "atype" "agen")])
7144 ;
7145 ; call_value instruction pattern(s).
7146 ;
7148 (define_expand "call_value"
7149 [(set (match_operand 0 "" "")
7150 (call (match_operand 1 "" "")
7151 (match_operand 2 "" "")))
7152 (use (match_operand 3 "" ""))]
7153 ""
7154 {
7155 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7156 gen_rtx_REG (Pmode, RETURN_REGNUM));
7157 DONE;
7158 })
7160 (define_insn "*bras_r"
7161 [(set (match_operand 0 "" "")
7162 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7163 (match_operand:SI 2 "const_int_operand" "n")))
7164 (clobber (match_operand 3 "register_operand" "=r"))]
7165 "!SIBLING_CALL_P (insn)
7166 && TARGET_SMALL_EXEC
7167 && GET_MODE (operands[3]) == Pmode"
7168 "bras\t%3,%1"
7169 [(set_attr "op_type" "RI")
7170 (set_attr "type" "jsr")])
7172 (define_insn "*brasl_r"
7173 [(set (match_operand 0 "" "")
7174 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7175 (match_operand 2 "const_int_operand" "n")))
7176 (clobber (match_operand 3 "register_operand" "=r"))]
7177 "!SIBLING_CALL_P (insn)
7178 && TARGET_CPU_ZARCH
7179 && GET_MODE (operands[3]) == Pmode"
7180 "brasl\t%3,%1"
7181 [(set_attr "op_type" "RIL")
7182 (set_attr "type" "jsr")])
7184 (define_insn "*basr_r"
7185 [(set (match_operand 0 "" "")
7186 (call (mem:QI (match_operand 1 "address_operand" "U"))
7187 (match_operand 2 "const_int_operand" "n")))
7188 (clobber (match_operand 3 "register_operand" "=r"))]
7189 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7190 {
7191 if (get_attr_op_type (insn) == OP_TYPE_RR)
7192 return "basr\t%3,%1";
7193 else
7194 return "bas\t%3,%a1";
7195 }
7196 [(set (attr "op_type")
7197 (if_then_else (match_operand 1 "register_operand" "")
7198 (const_string "RR") (const_string "RX")))
7199 (set_attr "type" "jsr")
7200 (set_attr "atype" "agen")])
7202 ;;
7203 ;;- Thread-local storage support.
7204 ;;
7206 (define_expand "get_tp_64"
7207 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
7208 "TARGET_64BIT"
7209 "")
7211 (define_expand "get_tp_31"
7212 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
7213 "!TARGET_64BIT"
7214 "")
7216 (define_expand "set_tp_64"
7217 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
7218 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
7219 "TARGET_64BIT"
7220 "")
7222 (define_expand "set_tp_31"
7223 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
7224 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
7225 "!TARGET_64BIT"
7226 "")
7228 (define_insn "*set_tp"
7229 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
7230 ""
7231 ""
7232 [(set_attr "type" "none")
7233 (set_attr "length" "0")])
7235 (define_insn "*tls_load_64"
7236 [(set (match_operand:DI 0 "register_operand" "=d")
7237 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7238 (match_operand:DI 2 "" "")]
7239 UNSPEC_TLS_LOAD))]
7240 "TARGET_64BIT"
7241 "lg\t%0,%1%J2"
7242 [(set_attr "op_type" "RXE")])
7244 (define_insn "*tls_load_31"
7245 [(set (match_operand:SI 0 "register_operand" "=d,d")
7246 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7247 (match_operand:SI 2 "" "")]
7248 UNSPEC_TLS_LOAD))]
7249 "!TARGET_64BIT"
7250 "@
7251 l\t%0,%1%J2
7252 ly\t%0,%1%J2"
7253 [(set_attr "op_type" "RX,RXY")])
7255 (define_insn "*bras_tls"
7256 [(set (match_operand 0 "" "")
7257 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7258 (match_operand 2 "const_int_operand" "n")))
7259 (clobber (match_operand 3 "register_operand" "=r"))
7260 (use (match_operand 4 "" ""))]
7261 "!SIBLING_CALL_P (insn)
7262 && TARGET_SMALL_EXEC
7263 && GET_MODE (operands[3]) == Pmode"
7264 "bras\t%3,%1%J4"
7265 [(set_attr "op_type" "RI")
7266 (set_attr "type" "jsr")])
7268 (define_insn "*brasl_tls"
7269 [(set (match_operand 0 "" "")
7270 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7271 (match_operand 2 "const_int_operand" "n")))
7272 (clobber (match_operand 3 "register_operand" "=r"))
7273 (use (match_operand 4 "" ""))]
7274 "!SIBLING_CALL_P (insn)
7275 && TARGET_CPU_ZARCH
7276 && GET_MODE (operands[3]) == Pmode"
7277 "brasl\t%3,%1%J4"
7278 [(set_attr "op_type" "RIL")
7279 (set_attr "type" "jsr")])
7281 (define_insn "*basr_tls"
7282 [(set (match_operand 0 "" "")
7283 (call (mem:QI (match_operand 1 "address_operand" "U"))
7284 (match_operand 2 "const_int_operand" "n")))
7285 (clobber (match_operand 3 "register_operand" "=r"))
7286 (use (match_operand 4 "" ""))]
7287 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7288 {
7289 if (get_attr_op_type (insn) == OP_TYPE_RR)
7290 return "basr\t%3,%1%J4";
7291 else
7292 return "bas\t%3,%a1%J4";
7293 }
7294 [(set (attr "op_type")
7295 (if_then_else (match_operand 1 "register_operand" "")
7296 (const_string "RR") (const_string "RX")))
7297 (set_attr "type" "jsr")
7298 (set_attr "atype" "agen")])
7300 ;;
7301 ;;- Atomic operations
7302 ;;
7304 ;
7305 ; memory barrier pattern.
7306 ;
7308 (define_expand "memory_barrier"
7309 [(set (mem:BLK (match_dup 0))
7310 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7311 ""
7312 {
7313 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7314 MEM_VOLATILE_P (operands[0]) = 1;
7315 })
7317 (define_insn "*memory_barrier"
7318 [(set (match_operand:BLK 0 "" "")
7319 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7320 ""
7321 "bcr\t15,0"
7322 [(set_attr "op_type" "RR")])
7324 ;
7325 ; compare and swap patterns.
7326 ;
7328 (define_expand "sync_compare_and_swap<mode>"
7329 [(parallel
7330 [(set (match_operand:TDSI 0 "register_operand" "")
7331 (match_operand:TDSI 1 "memory_operand" ""))
7332 (set (match_dup 1)
7333 (unspec_volatile:TDSI
7334 [(match_dup 1)
7335 (match_operand:TDSI 2 "register_operand" "")
7336 (match_operand:TDSI 3 "register_operand" "")]
7337 UNSPECV_CAS))
7338 (set (reg:CCZ1 CC_REGNUM)
7339 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7340 "")
7342 (define_expand "sync_compare_and_swap<mode>"
7343 [(parallel
7344 [(set (match_operand:HQI 0 "register_operand" "")
7345 (match_operand:HQI 1 "memory_operand" ""))
7346 (set (match_dup 1)
7347 (unspec_volatile:HQI
7348 [(match_dup 1)
7349 (match_operand:HQI 2 "general_operand" "")
7350 (match_operand:HQI 3 "general_operand" "")]
7351 UNSPECV_CAS))
7352 (set (reg:CCZ1 CC_REGNUM)
7353 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7354 ""
7355 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
7356 operands[2], operands[3]); DONE;")
7358 (define_expand "sync_compare_and_swap_cc<mode>"
7359 [(parallel
7360 [(set (match_operand:TDSI 0 "register_operand" "")
7361 (match_operand:TDSI 1 "memory_operand" ""))
7362 (set (match_dup 1)
7363 (unspec_volatile:TDSI
7364 [(match_dup 1)
7365 (match_operand:TDSI 2 "register_operand" "")
7366 (match_operand:TDSI 3 "register_operand" "")]
7367 UNSPECV_CAS))
7368 (set (match_dup 4)
7369 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7370 ""
7371 {
7372 /* Emulate compare. */
7373 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7374 s390_compare_op0 = operands[1];
7375 s390_compare_op1 = operands[2];
7376 s390_compare_emitted = operands[4];
7377 })
7379 (define_insn "*sync_compare_and_swap<mode>"
7380 [(set (match_operand:DP 0 "register_operand" "=r")
7381 (match_operand:DP 1 "memory_operand" "+Q"))
7382 (set (match_dup 1)
7383 (unspec_volatile:DP
7384 [(match_dup 1)
7385 (match_operand:DP 2 "register_operand" "0")
7386 (match_operand:DP 3 "register_operand" "r")]
7387 UNSPECV_CAS))
7388 (set (reg:CCZ1 CC_REGNUM)
7389 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7390 ""
7391 "cds<tg>\t%0,%3,%S1"
7392 [(set_attr "op_type" "RS<TE>")
7393 (set_attr "type" "sem")])
7395 (define_insn "*sync_compare_and_swap<mode>"
7396 [(set (match_operand:GPR 0 "register_operand" "=r")
7397 (match_operand:GPR 1 "memory_operand" "+Q"))
7398 (set (match_dup 1)
7399 (unspec_volatile:GPR
7400 [(match_dup 1)
7401 (match_operand:GPR 2 "register_operand" "0")
7402 (match_operand:GPR 3 "register_operand" "r")]
7403 UNSPECV_CAS))
7404 (set (reg:CCZ1 CC_REGNUM)
7405 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7406 ""
7407 "cs<g>\t%0,%3,%S1"
7408 [(set_attr "op_type" "RS<E>")
7409 (set_attr "type" "sem")])
7412 ;
7413 ; Other atomic instruction patterns.
7414 ;
7416 (define_expand "sync_lock_test_and_set<mode>"
7417 [(match_operand:HQI 0 "register_operand")
7418 (match_operand:HQI 1 "memory_operand")
7419 (match_operand:HQI 2 "general_operand")]
7420 ""
7421 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
7422 operands[2], false); DONE;")
7424 (define_expand "sync_<atomic><mode>"
7425 [(set (match_operand:HQI 0 "memory_operand")
7426 (ATOMIC:HQI (match_dup 0)
7427 (match_operand:HQI 1 "general_operand")))]
7428 ""
7429 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
7430 operands[1], false); DONE;")
7432 (define_expand "sync_old_<atomic><mode>"
7433 [(set (match_operand:HQI 0 "register_operand")
7434 (match_operand:HQI 1 "memory_operand"))
7435 (set (match_dup 1)
7436 (ATOMIC:HQI (match_dup 1)
7437 (match_operand:HQI 2 "general_operand")))]
7438 ""
7439 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7440 operands[2], false); DONE;")
7442 (define_expand "sync_new_<atomic><mode>"
7443 [(set (match_operand:HQI 0 "register_operand")
7444 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
7445 (match_operand:HQI 2 "general_operand")))
7446 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
7447 ""
7448 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7449 operands[2], true); DONE;")
7451 ;;
7452 ;;- Miscellaneous instructions.
7453 ;;
7455 ;
7456 ; allocate stack instruction pattern(s).
7457 ;
7459 (define_expand "allocate_stack"
7460 [(match_operand 0 "general_operand" "")
7461 (match_operand 1 "general_operand" "")]
7462 "TARGET_BACKCHAIN"
7463 {
7464 rtx temp = gen_reg_rtx (Pmode);
7466 emit_move_insn (temp, s390_back_chain_rtx ());
7467 anti_adjust_stack (operands[1]);
7468 emit_move_insn (s390_back_chain_rtx (), temp);
7470 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7471 DONE;
7472 })
7475 ;
7476 ; setjmp instruction pattern.
7477 ;
7479 (define_expand "builtin_setjmp_receiver"
7480 [(match_operand 0 "" "")]
7481 "flag_pic"
7482 {
7483 emit_insn (s390_load_got ());
7484 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7485 DONE;
7486 })
7488 ;; These patterns say how to save and restore the stack pointer. We need not
7489 ;; save the stack pointer at function level since we are careful to
7490 ;; preserve the backchain. At block level, we have to restore the backchain
7491 ;; when we restore the stack pointer.
7492 ;;
7493 ;; For nonlocal gotos, we must save both the stack pointer and its
7494 ;; backchain and restore both. Note that in the nonlocal case, the
7495 ;; save area is a memory location.
7497 (define_expand "save_stack_function"
7498 [(match_operand 0 "general_operand" "")
7499 (match_operand 1 "general_operand" "")]
7500 ""
7501 "DONE;")
7503 (define_expand "restore_stack_function"
7504 [(match_operand 0 "general_operand" "")
7505 (match_operand 1 "general_operand" "")]
7506 ""
7507 "DONE;")
7509 (define_expand "restore_stack_block"
7510 [(match_operand 0 "register_operand" "")
7511 (match_operand 1 "register_operand" "")]
7512 "TARGET_BACKCHAIN"
7513 {
7514 rtx temp = gen_reg_rtx (Pmode);
7516 emit_move_insn (temp, s390_back_chain_rtx ());
7517 emit_move_insn (operands[0], operands[1]);
7518 emit_move_insn (s390_back_chain_rtx (), temp);
7520 DONE;
7521 })
7523 (define_expand "save_stack_nonlocal"
7524 [(match_operand 0 "memory_operand" "")
7525 (match_operand 1 "register_operand" "")]
7526 ""
7527 {
7528 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7529 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7531 /* Copy the backchain to the first word, sp to the second and the
7532 literal pool base to the third. */
7534 if (TARGET_BACKCHAIN)
7535 {
7536 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7537 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7538 }
7540 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7541 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7543 DONE;
7544 })
7546 (define_expand "restore_stack_nonlocal"
7547 [(match_operand 0 "register_operand" "")
7548 (match_operand 1 "memory_operand" "")]
7549 ""
7550 {
7551 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7552 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7553 rtx temp = NULL_RTX;
7555 /* Restore the backchain from the first word, sp from the second and the
7556 literal pool base from the third. */
7558 if (TARGET_BACKCHAIN)
7559 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7561 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7562 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7564 if (temp)
7565 emit_move_insn (s390_back_chain_rtx (), temp);
7567 emit_insn (gen_rtx_USE (VOIDmode, base));
7568 DONE;
7569 })
7571 (define_expand "exception_receiver"
7572 [(const_int 0)]
7573 ""
7574 {
7575 s390_set_has_landing_pad_p (true);
7576 DONE;
7577 })
7579 ;
7580 ; nop instruction pattern(s).
7581 ;
7583 (define_insn "nop"
7584 [(const_int 0)]
7585 ""
7586 "lr\t0,0"
7587 [(set_attr "op_type" "RR")])
7590 ;
7591 ; Special literal pool access instruction pattern(s).
7592 ;
7594 (define_insn "*pool_entry"
7595 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7596 UNSPECV_POOL_ENTRY)]
7597 ""
7598 {
7599 enum machine_mode mode = GET_MODE (PATTERN (insn));
7600 unsigned int align = GET_MODE_BITSIZE (mode);
7601 s390_output_pool_entry (operands[0], mode, align);
7602 return "";
7603 }
7604 [(set (attr "length")
7605 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7607 (define_insn "pool_align"
7608 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7609 UNSPECV_POOL_ALIGN)]
7610 ""
7611 ".align\t%0"
7612 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7614 (define_insn "pool_section_start"
7615 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7616 ""
7617 ".section\t.rodata"
7618 [(set_attr "length" "0")])
7620 (define_insn "pool_section_end"
7621 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7622 ""
7623 ".previous"
7624 [(set_attr "length" "0")])
7626 (define_insn "main_base_31_small"
7627 [(set (match_operand 0 "register_operand" "=a")
7628 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7629 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7630 "basr\t%0,0"
7631 [(set_attr "op_type" "RR")
7632 (set_attr "type" "la")])
7634 (define_insn "main_base_31_large"
7635 [(set (match_operand 0 "register_operand" "=a")
7636 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7637 (set (pc) (label_ref (match_operand 2 "" "")))]
7638 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7639 "bras\t%0,%2"
7640 [(set_attr "op_type" "RI")])
7642 (define_insn "main_base_64"
7643 [(set (match_operand 0 "register_operand" "=a")
7644 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7645 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7646 "larl\t%0,%1"
7647 [(set_attr "op_type" "RIL")
7648 (set_attr "type" "larl")])
7650 (define_insn "main_pool"
7651 [(set (match_operand 0 "register_operand" "=a")
7652 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7653 "GET_MODE (operands[0]) == Pmode"
7654 {
7655 gcc_unreachable ();
7656 }
7657 [(set (attr "type")
7658 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7659 (const_string "larl") (const_string "la")))])
7661 (define_insn "reload_base_31"
7662 [(set (match_operand 0 "register_operand" "=a")
7663 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7664 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7665 "basr\t%0,0\;la\t%0,%1-.(%0)"
7666 [(set_attr "length" "6")
7667 (set_attr "type" "la")])
7669 (define_insn "reload_base_64"
7670 [(set (match_operand 0 "register_operand" "=a")
7671 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7672 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7673 "larl\t%0,%1"
7674 [(set_attr "op_type" "RIL")
7675 (set_attr "type" "larl")])
7677 (define_insn "pool"
7678 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7679 ""
7680 {
7681 gcc_unreachable ();
7682 }
7683 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7685 ;;
7686 ;; Insns related to generating the function prologue and epilogue.
7687 ;;
7690 (define_expand "prologue"
7691 [(use (const_int 0))]
7692 ""
7693 "s390_emit_prologue (); DONE;")
7695 (define_expand "epilogue"
7696 [(use (const_int 1))]
7697 ""
7698 "s390_emit_epilogue (false); DONE;")
7700 (define_expand "sibcall_epilogue"
7701 [(use (const_int 0))]
7702 ""
7703 "s390_emit_epilogue (true); DONE;")
7705 (define_insn "*return"
7706 [(return)
7707 (use (match_operand 0 "register_operand" "a"))]
7708 "GET_MODE (operands[0]) == Pmode"
7709 "br\t%0"
7710 [(set_attr "op_type" "RR")
7711 (set_attr "type" "jsr")
7712 (set_attr "atype" "agen")])
7715 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7716 ;; pointer. This is used for compatibility.
7718 (define_expand "ptr_extend"
7719 [(set (match_operand:DI 0 "register_operand" "=r")
7720 (match_operand:SI 1 "register_operand" "r"))]
7721 "TARGET_64BIT"
7722 {
7723 emit_insn (gen_anddi3 (operands[0],
7724 gen_lowpart (DImode, operands[1]),
7725 GEN_INT (0x7fffffff)));
7726 DONE;
7727 })
7729 ;; Instruction definition to expand eh_return macro to support
7730 ;; swapping in special linkage return addresses.
7732 (define_expand "eh_return"
7733 [(use (match_operand 0 "register_operand" ""))]
7734 "TARGET_TPF"
7735 {
7736 s390_emit_tpf_eh_return (operands[0]);
7737 DONE;
7738 })
7740 ;
7741 ; Stack Protector Patterns
7742 ;
7744 (define_expand "stack_protect_set"
7745 [(set (match_operand 0 "memory_operand" "")
7746 (match_operand 1 "memory_operand" ""))]
7747 ""
7748 {
7749 #ifdef TARGET_THREAD_SSP_OFFSET
7750 operands[1]
7751 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7752 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7753 #endif
7754 if (TARGET_64BIT)
7755 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7756 else
7757 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7759 DONE;
7760 })
7762 (define_insn "stack_protect_set<mode>"
7763 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7764 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7765 ""
7766 "mvc\t%O0(%G0,%R0),%S1"
7767 [(set_attr "op_type" "SS")])
7769 (define_expand "stack_protect_test"
7770 [(set (reg:CC CC_REGNUM)
7771 (compare (match_operand 0 "memory_operand" "")
7772 (match_operand 1 "memory_operand" "")))
7773 (match_operand 2 "" "")]
7774 ""
7775 {
7776 #ifdef TARGET_THREAD_SSP_OFFSET
7777 operands[1]
7778 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7779 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7780 #endif
7781 s390_compare_op0 = operands[0];
7782 s390_compare_op1 = operands[1];
7783 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7785 if (TARGET_64BIT)
7786 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7787 else
7788 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7790 emit_jump_insn (gen_beq (operands[2]));
7792 DONE;
7793 })
7795 (define_insn "stack_protect_test<mode>"
7796 [(set (reg:CCZ CC_REGNUM)
7797 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7798 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7799 ""
7800 "clc\t%O0(%G0,%R0),%S1"
7801 [(set_attr "op_type" "SS")])