1 ;; Machine Descriptions for R8C/M16C/M32C
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the Free
20 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
23 ;; move, push, extend, etc.
25 ;; Be careful to never create an alternative that has memory as both
26 ;; src and dest, as that makes gcc think that mem-mem moves in general
27 ;; are supported. While the chip does support this, it only has two
28 ;; address registers and sometimes gcc requires more than that. One
29 ;; example is code like this: a = *b where both a and b are spilled to
32 ;; Match push/pop before mov.b for passing char as arg,
33 ;; e.g. stdlib/efgcvt.c.
34 (define_insn "movqi_op"
35 [(set (match_operand:QI 0 "mra_qi_operand"
36 "=Rqi*Rmm, <, RqiSd*Rmm, SdSs, Rqi*Rmm, Sd")
37 (match_operand:QI 1 "mrai_qi_operand"
38 "iRqi*Rmm, iRqiSd*Rmm, >, Rqi*Rmm, SdSs, i"))]
39 "m32c_mov_ok (operands, QImode)"
47 [(set_attr "flags" "sz,*,*,sz,sz,sz")]
50 (define_expand "movqi"
51 [(set (match_operand:QI 0 "mra_qi_operand" "=RqiSd*Rmm")
52 (match_operand:QI 1 "mrai_qi_operand" "iRqiSd*Rmm"))]
54 "if (m32c_prepare_move (operands, QImode)) DONE;"
58 (define_insn "movhi_op"
59 [(set (match_operand:HI 0 "nonimmediate_operand"
60 "=Rhi*Rmm, Sd, SdSs, *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
61 (match_operand:HI 1 "general_operand"
62 "iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
63 "m32c_mov_ok (operands, HImode)"
74 [(set_attr "flags" "sz,sz,sz,*,*,*,*,*,*")]
77 (define_expand "movhi"
78 [(set (match_operand:HI 0 "nonimmediate_operand" "=RhiSd*Rmm")
79 (match_operand:HI 1 "general_operand" "iRhiSd*Rmm"))]
81 "if (m32c_prepare_move (operands, HImode)) DONE;"
85 (define_insn "movpsi_op"
86 [(set (match_operand:PSI 0 "nonimmediate_operand"
87 "=Raa, SdRmmRpi, Rcl, RpiSd*Rmm, <, <, Rcl, Rsi*Rmm")
88 (match_operand:PSI 1 "general_operand"
89 "sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rsi*Rmm, Rcl, >, >"))]
90 "TARGET_A24 && m32c_mov_ok (operands, PSImode)"
100 [(set_attr "flags" "sz,sz,*,*,*,*,*,*")]
104 ;; The intention here is to combine the add with the move to create an
105 ;; indexed move. GCC doesn't always figure this out itself.
107 (define_mode_macro QHSI [QI HI SI])
108 (define_mode_macro HPSI [(HI "TARGET_A16") (PSI "TARGET_A24")])
111 [(set (match_operand:HPSI 0 "register_operand" "")
112 (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
113 (match_operand:HPSI 2 "immediate_operand" "")))
114 (set (match_operand:QHSI 3 "nonimmediate_operand" "")
115 (mem:QHSI (match_operand:HPSI 4 "register_operand" "")))]
116 "REGNO (operands[0]) == REGNO (operands[1])
117 && REGNO (operands[0]) == REGNO (operands[4])
118 && (rtx_equal_p (operands[0], operands[3])
119 || (dead_or_set_p (peep2_next_insn (1), operands[4])
120 && ! reg_mentioned_p (operands[0], operands[3])))"
122 (mem:QHSI (plus:HPSI (match_dup 1)
127 [(set (match_operand:HPSI 0 "register_operand" "")
128 (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
129 (match_operand:HPSI 2 "immediate_operand" "")))
130 (set (mem:QHSI (match_operand:HPSI 4 "register_operand" ""))
131 (match_operand:QHSI 3 "general_operand" ""))]
132 "REGNO (operands[0]) == REGNO (operands[1])
133 && REGNO (operands[0]) == REGNO (operands[4])
134 && dead_or_set_p (peep2_next_insn (1), operands[4])
135 && ! reg_mentioned_p (operands[0], operands[3])"
136 [(set (mem:QHSI (plus:HPSI (match_dup 1)
142 ; Some PSI moves must be split.
144 [(set (match_operand:PSI 0 "nonimmediate_operand" "")
145 (match_operand:PSI 1 "general_operand" ""))]
146 "reload_completed && m32c_split_psi_p (operands)"
151 "m32c_split_move (operands, PSImode, 3);"
154 (define_expand "movpsi"
155 [(set (match_operand:PSI 0 "mras_operand" "")
156 (match_operand:PSI 1 "mrasi_operand" ""))]
158 "if (m32c_prepare_move (operands, PSImode)) DONE;"
163 (define_expand "movsi"
164 [(set (match_operand:SI 0 "mras_operand" "=RsiSd*Rmm")
165 (match_operand:SI 1 "mrasi_operand" "iRsiSd*Rmm"))]
167 "if (m32c_split_move (operands, SImode, 0)) DONE;"
170 ; All SI moves are split if TARGET_A16
171 (define_insn_and_split "movsi_splittable"
172 [(set (match_operand:SI 0 "mras_operand" "=Rsi<*Rmm,RsiSd*Rmm,Ss")
173 (match_operand:SI 1 "mrasi_operand" "iRsiSd*Rmm,iRsi>*Rmm,Rsi*Rmm"))]
176 "TARGET_A16 && reload_completed"
178 "m32c_split_move (operands, SImode, 1); DONE;"
181 ; The movsi pattern doesn't always match because sometimes the modes
183 (define_insn "push_a01_l"
184 [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
185 (match_operand 0 "a_operand" ""))]
190 (define_insn "movsi_24"
191 [(set (match_operand:SI 0 "mras_operand" "=Rsi*Rmm, Sd, RsiSd*Rmm, <")
192 (match_operand:SI 1 "mrasi_operand" "iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm"))]
201 (define_expand "movdi"
202 [(set (match_operand:DI 0 "mras_operand" "=RdiSd*Rmm")
203 (match_operand:DI 1 "mrasi_operand" "iRdiSd*Rmm"))]
205 "if (m32c_split_move (operands, DImode, 0)) DONE;"
208 (define_insn_and_split "movdi_splittable"
209 [(set (match_operand:DI 0 "mras_operand" "=Rdi<*Rmm,RdiSd*Rmm")
210 (match_operand:DI 1 "mrasi_operand" "iRdiSd*Rmm,iRdi>*Rmm"))]
215 "m32c_split_move (operands, DImode, 1); DONE;"
221 (define_insn "pushqi"
222 [(set (mem:QI (pre_dec:PSI (reg:PSI SP_REGNO)))
223 (match_operand:QI 0 "mrai_operand" "iRqiSd*Rmm"))]
228 (define_expand "pushhi"
229 [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
230 (match_operand:HI 0 "" ""))]
233 gen_pushhi_16 (operands[0]);
235 gen_pushhi_24 (operands[0]);
239 (define_insn "pushhi_16"
240 [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
241 (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm,Rcr"))]
248 (define_insn "pushhi_24"
249 [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
250 (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm"))]
255 ;(define_insn "pushpi"
256 ; [(set (mem:PSI (pre_dec:PSI (reg:PSI SP_REGNO)))
257 ; (match_operand:PI 0 "mrai_operand" "iRaa,Rcr"))]
264 (define_insn "pushsi"
265 [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
266 (match_operand:SI 0 "mrai_operand" "iRsiSd*Rmm"))]
271 (define_expand "pophi"
272 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
273 (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
276 gen_pophi_16 (operands[0]);
278 gen_pophi_24 (operands[0]);
282 (define_insn "pophi_16"
283 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
284 (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
291 (define_insn "pophi_24"
292 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm")
293 (mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))]
298 (define_insn "poppsi"
299 [(set (match_operand:PSI 0 "cr_operand" "=Rcl")
300 (mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))]
306 ;; Rhl used here as an HI-mode Rxl
307 (define_insn "extendqihi2"
308 [(set (match_operand:HI 0 "mra_operand" "=RhlSd*Rmm")
309 (sign_extend:HI (match_operand:QI 1 "mra_operand" "0")))]
312 [(set_attr "flags" "sz")]
315 (define_insn "extendhisi2"
316 [(set (match_operand:SI 0 "r0123_operand" "=R03")
317 (sign_extend:SI (match_operand:HI 1 "r0123_operand" "0")))]
320 if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
321 else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
322 [(set_attr "flags" "sz")]
325 (define_insn "extendpsisi2"
326 [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
327 (sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
329 "; expand psi %1 to si %0"
332 (define_insn "zero_extendpsisi2"
333 [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
334 (zero_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
336 "; expand psi %1 to si %0"
339 (define_insn "zero_extendhipsi2"
340 [(set (match_operand:PSI 0 "nonimmediate_operand" "=Raa")
341 (truncate:PSI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "Rhi"))))]
346 (define_insn "zero_extendhisi2"
347 [(set (match_operand:SI 0 "nonimmediate_operand" "=RsiSd")
348 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))]
353 (define_insn "zero_extendqihi2"
354 [(set (match_operand:HI 0 "nonimmediate_operand" "=RsiRaaSd*Rmm")
355 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
360 (define_insn "truncsipsi2_16"
361 [(set (match_operand:PSI 0 "nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
362 (truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
365 ; no-op trunc si %1 to psi %0
371 (define_insn "trunchiqi2"
372 [(set (match_operand:QI 0 "mra_qi_operand" "=RqiRmmSd")
373 (truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))]
375 "; no-op trunc hi %1 to qi %0"
378 (define_insn "truncsipsi2_24"
379 [(set (match_operand:PSI 0 "nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm")
380 (truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))]
383 ; no-op trunc si %1 to psi %0
389 (define_expand "truncsipsi2"
390 [(set (match_operand:PSI 0 "nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
391 (truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
396 (define_expand "reload_inqi"
397 [(set (match_operand:QI 2 "" "=&Rqi")
398 (match_operand:QI 1 "" ""))
399 (set (match_operand:QI 0 "" "")
405 (define_expand "reload_outqi"
406 [(set (match_operand:QI 2 "" "=&Rqi")
407 (match_operand:QI 1 "" ""))
408 (set (match_operand:QI 0 "" "")
414 (define_expand "reload_inhi"
415 [(set (match_operand:HI 2 "" "=&Rhi")
416 (match_operand:HI 1 "" ""))
417 (set (match_operand:HI 0 "" "")
423 (define_expand "reload_outhi"
424 [(set (match_operand:HI 2 "" "=&Rhi")
425 (match_operand:HI 1 "" ""))
426 (set (match_operand:HI 0 "" "")