1 ;; IA-64 Machine description template
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
5 ;; David Mosberger <davidm@hpl.hp.com>.
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 ;; Boston, MA 02110-1301, USA.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
27 ;; reload. This will be fixed once scheduling support is turned on.
29 ;; ??? Optimize for post-increment addressing modes.
31 ;; ??? fselect is not supported, because there is no integer register
34 ;; ??? fp abs/min/max instructions may also work for integer values.
36 ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
37 ;; it assumes the operand is a register and takes REGNO of it without checking.
39 ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
40 ;; it assumes the operand is a register and takes REGNO of it without checking.
42 ;; ??? Go through list of documented named patterns and look for more to
45 ;; ??? Go through instruction manual and look for more instructions that
48 ;; ??? Add function unit scheduling info for Itanium (TM) processor.
50 ;; ??? Need a better way to describe alternate fp status registers.
54 (UNSPEC_LTOFF_DTPMOD 0)
55 (UNSPEC_LTOFF_DTPREL 1)
57 (UNSPEC_LTOFF_TPREL 3)
63 (UNSPEC_GR_RESTORE 11)
65 (UNSPEC_FR_RESTORE 13)
66 (UNSPEC_FR_RECIP_APPROX 14)
67 (UNSPEC_PRED_REL_MUTEX 15)
71 (UNSPEC_CMPXCHG_ACQ 19)
72 (UNSPEC_FETCHADD_ACQ 20)
75 (UNSPEC_BUNDLE_SELECTOR 23)
77 (UNSPEC_PROLOGUE_USE 25)
80 (UNSPEC_FR_SQRT_RECIP_APPROX 28)
89 (UNSPECV_INSN_GROUP_BARRIER 2)
92 (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls
93 (UNSPECV_PSAC_NORMAL 6)
94 (UNSPECV_SETJMP_RECEIVER 7)
97 (include "predicates.md")
99 ;; ::::::::::::::::::::
103 ;; ::::::::::::::::::::
105 ;; Processor type. This attribute must exactly match the processor_type
106 ;; enumeration in ia64.h.
107 (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune")))
109 ;; Instruction type. This primarily determines how instructions can be
110 ;; packed in bundles, and secondarily affects scheduling to function units.
112 ;; A alu, can go in I or M syllable of a bundle
117 ;; L long immediate, takes two syllables
120 ;; ??? Should not have any pattern with type unknown. Perhaps add code to
121 ;; check this in md_reorg? Currently use unknown for patterns which emit
122 ;; multiple instructions, patterns which emit 0 instructions, and patterns
123 ;; which emit instruction that can go in any slot (e.g. nop).
125 (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
126 fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,
127 ld,chk_s,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,
128 st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,
129 nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle"
130 (const_string "unknown"))
132 ;; chk_s has an I and an M form; use type A for convenience.
133 (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
134 (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M")
135 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
136 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
137 (eq_attr "itanium_class" "lfetch") (const_string "M")
138 (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog,mmalua")
140 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
141 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
142 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
143 (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
144 (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I")
145 (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B")
146 (eq_attr "itanium_class" "stop_bit") (const_string "S")
147 (eq_attr "itanium_class" "nop_x") (const_string "X")
148 (eq_attr "itanium_class" "long_i") (const_string "L")]
149 (const_string "unknown")))
151 (define_attr "itanium_requires_unit0" "no,yes"
152 (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes")
153 (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes")
154 (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes")
155 (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes")
156 (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes")
157 (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")]
158 (const_string "no")))
160 ;; Predication. True iff this instruction can be predicated.
162 (define_attr "predicable" "no,yes" (const_string "yes"))
164 ;; Empty. True iff this insn does not generate any code.
166 (define_attr "empty" "no,yes" (const_string "no"))
168 ;; True iff this insn must be the first insn of an instruction group.
169 ;; This is true for the alloc instruction, and will also be true of others
170 ;; when we have full intrinsics support.
172 (define_attr "first_insn" "no,yes" (const_string "no"))
174 ;; DFA descriptions of ia64 processors used for insn scheduling and
177 (automata_option "ndfa")
179 ;; Uncomment the following line to output automata for debugging.
180 ;; (automata_option "v")
182 (automata_option "w")
184 (include "itanium1.md")
185 (include "itanium2.md")
188 ;; ::::::::::::::::::::
192 ;; ::::::::::::::::::::
194 ;; Set of a single predicate register. This is only used to implement
195 ;; pr-to-pr move and complement.
197 (define_insn "*movcci"
198 [(set (match_operand:CCI 0 "register_operand" "=c,c,c")
199 (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))]
202 cmp.ne %0, p0 = r0, r0
203 cmp.eq %0, p0 = r0, r0
204 (%1) cmp.eq.unc %0, p0 = r0, r0"
205 [(set_attr "itanium_class" "icmp")
206 (set_attr "predicable" "no")])
209 [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
210 (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
213 cmp.ne %0, %I0 = r0, r0
214 cmp.eq %0, %I0 = r0, r0
217 tbit.nz %0, %I0 = %1, 0
222 [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
225 [(set (match_operand:BI 0 "register_operand" "")
226 (match_operand:BI 1 "register_operand" ""))]
228 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
229 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
230 [(cond_exec (ne (match_dup 1) (const_int 0))
231 (set (match_dup 0) (const_int 1)))
232 (cond_exec (eq (match_dup 1) (const_int 0))
233 (set (match_dup 0) (const_int 0)))]
237 [(set (match_operand:BI 0 "register_operand" "")
238 (match_operand:BI 1 "register_operand" ""))]
240 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
241 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
242 [(set (match_dup 2) (match_dup 4))
243 (set (match_dup 3) (match_dup 5))
244 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
245 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
246 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
247 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
248 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
250 (define_expand "movqi"
251 [(set (match_operand:QI 0 "general_operand" "")
252 (match_operand:QI 1 "general_operand" ""))]
255 rtx op1 = ia64_expand_move (operands[0], operands[1]);
261 (define_insn "*movqi_internal"
262 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
263 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
264 "ia64_move_ok (operands[0], operands[1])"
273 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
275 (define_expand "movhi"
276 [(set (match_operand:HI 0 "general_operand" "")
277 (match_operand:HI 1 "general_operand" ""))]
280 rtx op1 = ia64_expand_move (operands[0], operands[1]);
286 (define_insn "*movhi_internal"
287 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
288 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
289 "ia64_move_ok (operands[0], operands[1])"
298 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
300 (define_expand "movsi"
301 [(set (match_operand:SI 0 "general_operand" "")
302 (match_operand:SI 1 "general_operand" ""))]
305 rtx op1 = ia64_expand_move (operands[0], operands[1]);
311 (define_insn "*movsi_internal"
312 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
313 (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
314 "ia64_move_ok (operands[0], operands[1])"
326 ;; frar_m, toar_m ??? why not frar_i and toar_i
327 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
329 (define_expand "movdi"
330 [(set (match_operand:DI 0 "general_operand" "")
331 (match_operand:DI 1 "general_operand" ""))]
334 rtx op1 = ia64_expand_move (operands[0], operands[1]);
340 (define_insn "*movdi_internal"
341 [(set (match_operand:DI 0 "destination_operand"
342 "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
343 (match_operand:DI 1 "move_operand"
344 "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
345 "ia64_move_ok (operands[0], operands[1])"
347 static const char * const alt[] = {
349 "%,addl %0 = %1, r0",
351 "%,ld8%O1 %0 = %1%P1",
352 "%,st8%Q0 %0 = %r1%P0",
353 "%,getf.sig %0 = %1",
354 "%,setf.sig %0 = %r1",
368 gcc_assert (which_alternative != 2 || TARGET_NO_PIC
369 || !symbolic_operand (operands[1], VOIDmode));
371 return alt[which_alternative];
373 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
376 [(set (match_operand 0 "register_operand" "")
377 (match_operand 1 "symbolic_operand" ""))]
381 if (ia64_expand_load_address (operands[0], operands[1]))
387 (define_expand "load_fptr"
388 [(set (match_operand:DI 0 "register_operand" "")
389 (plus:DI (match_dup 2) (match_operand 1 "function_operand" "")))
390 (set (match_dup 0) (match_dup 3))]
393 operands[2] = pic_offset_table_rtx;
394 operands[3] = gen_const_mem (DImode, operands[0]);
397 (define_insn "*load_fptr_internal1"
398 [(set (match_operand:DI 0 "register_operand" "=r")
399 (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))]
401 "addl %0 = @ltoff(@fptr(%1)), gp"
402 [(set_attr "itanium_class" "ialu")])
404 (define_insn "load_gprel"
405 [(set (match_operand:DI 0 "register_operand" "=r")
406 (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))]
408 "addl %0 = @gprel(%1), gp"
409 [(set_attr "itanium_class" "ialu")])
411 (define_insn "*gprel64_offset"
412 [(set (match_operand:DI 0 "register_operand" "=r")
413 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
415 "movl %0 = @gprel(%1)"
416 [(set_attr "itanium_class" "long_i")])
418 (define_expand "load_gprel64"
419 [(set (match_operand:DI 0 "register_operand" "")
420 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2)))
422 (plus:DI (match_dup 2) (match_dup 0)))]
425 operands[2] = pic_offset_table_rtx;
428 ;; This is used as a placeholder for the return address during early
429 ;; compilation. We won't know where we've placed this until during
430 ;; reload, at which point it can wind up in b0, a general register,
431 ;; or memory. The only safe destination under these conditions is a
434 (define_insn_and_split "*movdi_ret_addr"
435 [(set (match_operand:DI 0 "register_operand" "=r")
436 (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))]
442 ia64_split_return_addr_rtx (operands[0]);
445 [(set_attr "itanium_class" "ialu")])
447 (define_insn "*load_symptr_high"
448 [(set (match_operand:DI 0 "register_operand" "=r")
449 (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s"))
450 (match_operand:DI 2 "register_operand" "a")))]
453 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
454 return "%,addl %0 = @ltoffx(%1), %2";
456 return "%,addl %0 = @ltoff(%1), %2";
458 [(set_attr "itanium_class" "ialu")])
460 (define_insn "*load_symptr_low"
461 [(set (match_operand:DI 0 "register_operand" "=r")
462 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
463 (match_operand 2 "got_symbolic_operand" "s")))]
466 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
467 return "%,ld8.mov %0 = [%1], %2";
469 return "%,ld8 %0 = [%1]";
471 [(set_attr "itanium_class" "ld")])
473 (define_insn_and_split "load_dtpmod"
474 [(set (match_operand:DI 0 "register_operand" "=r")
475 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
481 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD)
483 (set (match_dup 0) (match_dup 3))]
485 operands[2] = pic_offset_table_rtx;
486 operands[3] = gen_const_mem (DImode, operands[0]);
489 (define_insn "*load_ltoff_dtpmod"
490 [(set (match_operand:DI 0 "register_operand" "=r")
491 (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
493 (match_operand:DI 2 "register_operand" "a")))]
495 "addl %0 = @ltoff(@dtpmod(%1)), %2"
496 [(set_attr "itanium_class" "ialu")])
498 (define_expand "load_dtprel"
499 [(set (match_operand:DI 0 "register_operand" "")
500 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
505 (define_insn "*load_dtprel64"
506 [(set (match_operand:DI 0 "register_operand" "=r")
507 (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
510 "movl %0 = @dtprel(%1)"
511 [(set_attr "itanium_class" "long_i")])
513 (define_insn "*load_dtprel22"
514 [(set (match_operand:DI 0 "register_operand" "=r")
515 (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
518 "addl %0 = @dtprel(%1), r0"
519 [(set_attr "itanium_class" "ialu")])
521 (define_insn_and_split "*load_dtprel_gd"
522 [(set (match_operand:DI 0 "register_operand" "=r")
523 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
529 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL)
531 (set (match_dup 0) (match_dup 3))]
533 operands[2] = pic_offset_table_rtx;
534 operands[3] = gen_const_mem (DImode, operands[0]);
537 (define_insn "*load_ltoff_dtprel"
538 [(set (match_operand:DI 0 "register_operand" "=r")
539 (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
541 (match_operand:DI 2 "register_operand" "a")))]
543 "addl %0 = @ltoff(@dtprel(%1)), %2"
544 [(set_attr "itanium_class" "ialu")])
546 (define_expand "add_dtprel"
547 [(set (match_operand:DI 0 "register_operand" "")
548 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
550 (match_operand:DI 2 "register_operand" "")))]
554 (define_insn "*add_dtprel14"
555 [(set (match_operand:DI 0 "register_operand" "=r")
556 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
558 (match_operand:DI 2 "register_operand" "r")))]
560 "adds %0 = @dtprel(%1), %2"
561 [(set_attr "itanium_class" "ialu")])
563 (define_insn "*add_dtprel22"
564 [(set (match_operand:DI 0 "register_operand" "=r")
565 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
567 (match_operand:DI 2 "register_operand" "a")))]
569 "addl %0 = @dtprel(%1), %2"
570 [(set_attr "itanium_class" "ialu")])
572 (define_expand "load_tprel"
573 [(set (match_operand:DI 0 "register_operand" "")
574 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
579 (define_insn "*load_tprel64"
580 [(set (match_operand:DI 0 "register_operand" "=r")
581 (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
584 "movl %0 = @tprel(%1)"
585 [(set_attr "itanium_class" "long_i")])
587 (define_insn "*load_tprel22"
588 [(set (match_operand:DI 0 "register_operand" "=r")
589 (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
592 "addl %0 = @tprel(%1), r0"
593 [(set_attr "itanium_class" "ialu")])
595 (define_insn_and_split "*load_tprel_ie"
596 [(set (match_operand:DI 0 "register_operand" "=r")
597 (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
603 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL)
605 (set (match_dup 0) (match_dup 3))]
607 operands[2] = pic_offset_table_rtx;
608 operands[3] = gen_const_mem (DImode, operands[0]);
611 (define_insn "*load_ltoff_tprel"
612 [(set (match_operand:DI 0 "register_operand" "=r")
613 (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
615 (match_operand:DI 2 "register_operand" "a")))]
617 "addl %0 = @ltoff(@tprel(%1)), %2"
618 [(set_attr "itanium_class" "ialu")])
620 (define_expand "add_tprel"
621 [(set (match_operand:DI 0 "register_operand" "")
622 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
624 (match_operand:DI 2 "register_operand" "")))]
628 (define_insn "*add_tprel14"
629 [(set (match_operand:DI 0 "register_operand" "=r")
630 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
632 (match_operand:DI 2 "register_operand" "r")))]
634 "adds %0 = @tprel(%1), %2"
635 [(set_attr "itanium_class" "ialu")])
637 (define_insn "*add_tprel22"
638 [(set (match_operand:DI 0 "register_operand" "=r")
639 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
641 (match_operand:DI 2 "register_operand" "a")))]
643 "addl %0 = @tprel(%1), %2"
644 [(set_attr "itanium_class" "ialu")])
646 ;; With no offsettable memory references, we've got to have a scratch
647 ;; around to play with the second word. However, in order to avoid a
648 ;; reload nightmare we lie, claim we don't need one, and fix it up
649 ;; in ia64_split_tmode_move.
650 (define_expand "movti"
651 [(set (match_operand:TI 0 "general_operand" "")
652 (match_operand:TI 1 "general_operand" ""))]
655 rtx op1 = ia64_expand_move (operands[0], operands[1]);
661 (define_insn_and_split "*movti_internal"
662 [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q")
663 (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))]
664 "ia64_move_ok (operands[0], operands[1])"
671 "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])"
674 ia64_split_tmode_move (operands);
677 [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")])
679 ;; Floating Point Moves
681 ;; Note - Patterns for SF mode moves are compulsory, but
682 ;; patterns for DF are optional, as GCC can synthesize them.
684 (define_expand "movsf"
685 [(set (match_operand:SF 0 "general_operand" "")
686 (match_operand:SF 1 "general_operand" ""))]
689 rtx op1 = ia64_expand_move (operands[0], operands[1]);
695 (define_insn "*movsf_internal"
696 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
697 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
698 "ia64_move_ok (operands[0], operands[1])"
708 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
710 (define_expand "movdf"
711 [(set (match_operand:DF 0 "general_operand" "")
712 (match_operand:DF 1 "general_operand" ""))]
715 rtx op1 = ia64_expand_move (operands[0], operands[1]);
721 (define_insn "*movdf_internal"
722 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
723 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
724 "ia64_move_ok (operands[0], operands[1])"
734 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
736 ;; With no offsettable memory references, we've got to have a scratch
737 ;; around to play with the second word if the variable winds up in GRs.
738 (define_expand "movxf"
739 [(set (match_operand:XF 0 "general_operand" "")
740 (match_operand:XF 1 "general_operand" ""))]
743 if (ia64_expand_movxf_movrf (XFmode, operands))
747 ;; ??? There's no easy way to mind volatile acquire/release semantics.
749 (define_insn "*movxf_internal"
750 [(set (match_operand:XF 0 "destination_operand" "=f,f, m")
751 (match_operand:XF 1 "general_operand" "fG,m,fG"))]
752 "ia64_move_ok (operands[0], operands[1])"
757 [(set_attr "itanium_class" "fmisc,fld,stf")])
759 ;; Same as for movxf, but for RFmode.
760 (define_expand "movrf"
761 [(set (match_operand:RF 0 "general_operand" "")
762 (match_operand:RF 1 "general_operand" ""))]
765 if (ia64_expand_movxf_movrf (RFmode, operands))
769 (define_insn "*movrf_internal"
770 [(set (match_operand:RF 0 "destination_operand" "=f,f, m")
771 (match_operand:RF 1 "general_operand" "fG,m,fG"))]
772 "ia64_move_ok (operands[0], operands[1])"
776 stf.spill %0 = %F1%P0"
777 [(set_attr "itanium_class" "fmisc,fld,stf")])
779 ;; Better code generation via insns that deal with TFmode register pairs
780 ;; directly. Same concerns apply as for TImode.
781 (define_expand "movtf"
782 [(set (match_operand:TF 0 "general_operand" "")
783 (match_operand:TF 1 "general_operand" ""))]
786 rtx op1 = ia64_expand_move (operands[0], operands[1]);
792 (define_insn_and_split "*movtf_internal"
793 [(set (match_operand:TF 0 "destination_operand" "=r,r,m")
794 (match_operand:TF 1 "general_operand" "ri,m,r"))]
795 "ia64_move_ok (operands[0], operands[1])"
800 ia64_split_tmode_move (operands);
803 [(set_attr "itanium_class" "unknown")
804 (set_attr "predicable" "no")])
807 ;; ::::::::::::::::::::
811 ;; ::::::::::::::::::::
813 ;; Signed conversions from a smaller integer to a larger integer
815 (define_insn "extendqidi2"
816 [(set (match_operand:DI 0 "gr_register_operand" "=r")
817 (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
820 [(set_attr "itanium_class" "xtd")])
822 (define_insn "extendhidi2"
823 [(set (match_operand:DI 0 "gr_register_operand" "=r")
824 (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
827 [(set_attr "itanium_class" "xtd")])
829 (define_insn "extendsidi2"
830 [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
831 (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))]
836 [(set_attr "itanium_class" "xtd,fmisc")])
838 ;; Unsigned conversions from a smaller integer to a larger integer
840 (define_insn "zero_extendqidi2"
841 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
842 (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))]
847 [(set_attr "itanium_class" "xtd,ld")])
849 (define_insn "zero_extendhidi2"
850 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
851 (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))]
856 [(set_attr "itanium_class" "xtd,ld")])
858 (define_insn "zero_extendsidi2"
859 [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
861 (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
867 [(set_attr "itanium_class" "ialu,ld,fmisc")])
869 ;; Convert between floating point types of different sizes.
871 ;; At first glance, it would appear that emitting fnorm for an extending
872 ;; conversion is unnecessary. However, the stf and getf instructions work
873 ;; correctly only if the input is properly rounded for its type. In
874 ;; particular, we get the wrong result for getf.d/stfd if the input is a
875 ;; denorm single. Since we don't know what the next instruction will be, we
876 ;; have to emit an fnorm.
878 ;; ??? Optimization opportunity here. Get rid of the insn altogether
879 ;; when we can. Should probably use a scheme like has been proposed
880 ;; for ia32 in dealing with operands that match unary operators. This
881 ;; would let combine merge the thing into adjacent insns. See also how the
882 ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via
883 ;; se_register_operand.
885 (define_insn "extendsfdf2"
886 [(set (match_operand:DF 0 "fr_register_operand" "=f")
887 (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))]
890 [(set_attr "itanium_class" "fmac")])
892 (define_insn "extendsfxf2"
893 [(set (match_operand:XF 0 "fr_register_operand" "=f")
894 (float_extend:XF (match_operand:SF 1 "fr_register_operand" "f")))]
897 [(set_attr "itanium_class" "fmac")])
899 (define_insn "extenddfxf2"
900 [(set (match_operand:XF 0 "fr_register_operand" "=f")
901 (float_extend:XF (match_operand:DF 1 "fr_register_operand" "f")))]
904 [(set_attr "itanium_class" "fmac")])
906 (define_insn "truncdfsf2"
907 [(set (match_operand:SF 0 "fr_register_operand" "=f")
908 (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))]
911 [(set_attr "itanium_class" "fmac")])
913 (define_insn "truncxfsf2"
914 [(set (match_operand:SF 0 "fr_register_operand" "=f")
915 (float_truncate:SF (match_operand:XF 1 "fr_register_operand" "f")))]
918 [(set_attr "itanium_class" "fmac")])
920 (define_insn "truncxfdf2"
921 [(set (match_operand:DF 0 "fr_register_operand" "=f")
922 (float_truncate:DF (match_operand:XF 1 "fr_register_operand" "f")))]
925 [(set_attr "itanium_class" "fmac")])
927 ;; Convert between signed integer types and floating point.
929 (define_insn "floatdixf2"
930 [(set (match_operand:XF 0 "fr_register_operand" "=f")
931 (float:XF (match_operand:DI 1 "fr_register_operand" "f")))]
934 [(set_attr "itanium_class" "fcvtfx")])
936 (define_insn "fix_truncsfdi2"
937 [(set (match_operand:DI 0 "fr_register_operand" "=f")
938 (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
940 "fcvt.fx.trunc %0 = %1"
941 [(set_attr "itanium_class" "fcvtfx")])
943 (define_insn "fix_truncdfdi2"
944 [(set (match_operand:DI 0 "fr_register_operand" "=f")
945 (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
947 "fcvt.fx.trunc %0 = %1"
948 [(set_attr "itanium_class" "fcvtfx")])
950 (define_insn "fix_truncxfdi2"
951 [(set (match_operand:DI 0 "fr_register_operand" "=f")
952 (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))]
954 "fcvt.fx.trunc %0 = %1"
955 [(set_attr "itanium_class" "fcvtfx")])
957 (define_insn "fix_truncxfdi2_alts"
958 [(set (match_operand:DI 0 "fr_register_operand" "=f")
959 (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))
960 (use (match_operand:SI 2 "const_int_operand" ""))]
962 "fcvt.fx.trunc.s%2 %0 = %1"
963 [(set_attr "itanium_class" "fcvtfx")])
965 ;; Convert between unsigned integer types and floating point.
967 (define_insn "floatunsdisf2"
968 [(set (match_operand:SF 0 "fr_register_operand" "=f")
969 (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))]
972 [(set_attr "itanium_class" "fcvtfx")])
974 (define_insn "floatunsdidf2"
975 [(set (match_operand:DF 0 "fr_register_operand" "=f")
976 (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))]
979 [(set_attr "itanium_class" "fcvtfx")])
981 (define_insn "floatunsdixf2"
982 [(set (match_operand:XF 0 "fr_register_operand" "=f")
983 (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "f")))]
986 [(set_attr "itanium_class" "fcvtfx")])
988 (define_insn "fixuns_truncsfdi2"
989 [(set (match_operand:DI 0 "fr_register_operand" "=f")
990 (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
992 "fcvt.fxu.trunc %0 = %1"
993 [(set_attr "itanium_class" "fcvtfx")])
995 (define_insn "fixuns_truncdfdi2"
996 [(set (match_operand:DI 0 "fr_register_operand" "=f")
997 (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
999 "fcvt.fxu.trunc %0 = %1"
1000 [(set_attr "itanium_class" "fcvtfx")])
1002 (define_insn "fixuns_truncxfdi2"
1003 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1004 (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))]
1006 "fcvt.fxu.trunc %0 = %1"
1007 [(set_attr "itanium_class" "fcvtfx")])
1009 (define_insn "fixuns_truncxfdi2_alts"
1010 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1011 (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))
1012 (use (match_operand:SI 2 "const_int_operand" ""))]
1014 "fcvt.fxu.trunc.s%2 %0 = %1"
1015 [(set_attr "itanium_class" "fcvtfx")])
1017 ;; ::::::::::::::::::::
1019 ;; :: Bit field extraction
1021 ;; ::::::::::::::::::::
1024 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1025 (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1026 (match_operand:DI 2 "extr_len_operand" "n")
1027 (match_operand:DI 3 "shift_count_operand" "M")))]
1029 "extr %0 = %1, %3, %2"
1030 [(set_attr "itanium_class" "ishf")])
1032 (define_insn "extzv"
1033 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1034 (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1035 (match_operand:DI 2 "extr_len_operand" "n")
1036 (match_operand:DI 3 "shift_count_operand" "M")))]
1038 "extr.u %0 = %1, %3, %2"
1039 [(set_attr "itanium_class" "ishf")])
1041 ;; Insert a bit field.
1042 ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
1043 ;; Source1 can be 0 or -1.
1044 ;; Source2 can be 0.
1046 ;; ??? Actual dep instruction is more powerful than what these insv
1047 ;; patterns support. Unfortunately, combine is unable to create patterns
1048 ;; where source2 != dest.
1050 (define_expand "insv"
1051 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "")
1052 (match_operand:DI 1 "const_int_operand" "")
1053 (match_operand:DI 2 "const_int_operand" ""))
1054 (match_operand:DI 3 "nonmemory_operand" ""))]
1057 int width = INTVAL (operands[1]);
1058 int shift = INTVAL (operands[2]);
1060 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
1062 if (! register_operand (operands[3], DImode)
1063 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
1064 operands[3] = force_reg (DImode, operands[3]);
1066 /* If this is a single dep instruction, we have nothing to do. */
1067 if (! ((register_operand (operands[3], DImode) && width <= 16)
1068 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
1070 /* Check for cases that can be implemented with a mix instruction. */
1071 if (width == 32 && shift == 0)
1073 /* Directly generating the mix4left instruction confuses
1074 optimize_bit_field in function.c. Since this is performing
1075 a useful optimization, we defer generation of the complicated
1076 mix4left RTL to the first splitting phase. */
1077 rtx tmp = gen_reg_rtx (DImode);
1078 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
1081 else if (width == 32 && shift == 32)
1083 emit_insn (gen_mix4right (operands[0], operands[3]));
1087 /* We could handle remaining cases by emitting multiple dep
1090 If we need more than two dep instructions then we lose. A 6
1091 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1092 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
1093 the latter is 6 cycles on an Itanium (TM) processor, because there is
1094 only one function unit that can execute dep and shr immed.
1096 If we only need two dep instruction, then we still lose.
1097 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
1098 the unnecessary mov, this is still undesirable because it will be
1099 hard to optimize, and it creates unnecessary pressure on the I0
1105 /* This code may be useful for other IA-64 processors, so we leave it in
1111 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
1115 tmp = gen_reg_rtx (DImode);
1116 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
1119 operands[1] = GEN_INT (width);
1120 operands[2] = GEN_INT (shift);
1125 (define_insn "*insv_internal"
1126 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1127 (match_operand:DI 1 "const_int_operand" "n")
1128 (match_operand:DI 2 "const_int_operand" "n"))
1129 (match_operand:DI 3 "nonmemory_operand" "rP"))]
1130 "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
1131 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
1132 "dep %0 = %3, %0, %2, %1"
1133 [(set_attr "itanium_class" "ishf")])
1135 ;; Combine doesn't like to create bit-field insertions into zero.
1136 (define_insn "*shladdp4_internal"
1137 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1138 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1139 (match_operand:DI 2 "shladd_log2_operand" "n"))
1140 (match_operand:DI 3 "const_int_operand" "n")))]
1141 "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32"
1142 "shladdp4 %0 = %1, %2, r0"
1143 [(set_attr "itanium_class" "ialu")])
1145 (define_insn "*depz_internal"
1146 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1147 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1148 (match_operand:DI 2 "const_int_operand" "n"))
1149 (match_operand:DI 3 "const_int_operand" "n")))]
1150 "CONST_OK_FOR_M (INTVAL (operands[2]))
1151 && ia64_depz_field_mask (operands[3], operands[2]) > 0"
1153 operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
1154 return "%,dep.z %0 = %1, %2, %3";
1156 [(set_attr "itanium_class" "ishf")])
1158 (define_insn "shift_mix4left"
1159 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1160 (const_int 32) (const_int 0))
1161 (match_operand:DI 1 "gr_register_operand" "r"))
1162 (clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
1165 [(set_attr "itanium_class" "unknown")])
1168 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1169 (const_int 32) (const_int 0))
1170 (match_operand:DI 1 "register_operand" ""))
1171 (clobber (match_operand:DI 2 "register_operand" ""))]
1173 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1174 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1175 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1176 "operands[3] = operands[2];")
1178 (define_insn "*mix4left"
1179 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1180 (const_int 32) (const_int 0))
1181 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
1184 "mix4.l %0 = %0, %r1"
1185 [(set_attr "itanium_class" "mmshf")])
1187 (define_insn "mix4right"
1188 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1189 (const_int 32) (const_int 32))
1190 (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
1192 "mix4.r %0 = %r1, %0"
1193 [(set_attr "itanium_class" "mmshf")])
1195 ;; This is used by the rotrsi3 pattern.
1197 (define_insn "*mix4right_3op"
1198 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1199 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r"))
1200 (ashift:DI (zero_extend:DI
1201 (match_operand:SI 2 "gr_register_operand" "r"))
1204 "mix4.r %0 = %2, %1"
1205 [(set_attr "itanium_class" "mmshf")])
1208 ;; ::::::::::::::::::::
1210 ;; :: 1 bit Integer arithmetic
1212 ;; ::::::::::::::::::::
1214 (define_insn_and_split "andbi3"
1215 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1216 (and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1217 (match_operand:BI 2 "register_operand" "c,r,r")))]
1221 tbit.nz.and.orcm %0, %I0 = %2, 0
1224 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1225 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1226 [(cond_exec (eq (match_dup 2) (const_int 0))
1227 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1230 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1232 (define_insn_and_split "*andcmbi3"
1233 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1234 (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
1235 (match_operand:BI 2 "register_operand" "0,0,r")))]
1239 tbit.z.and.orcm %0, %I0 = %1, 0
1242 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1243 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1244 [(cond_exec (ne (match_dup 1) (const_int 0))
1245 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1248 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1250 (define_insn_and_split "iorbi3"
1251 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1252 (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1253 (match_operand:BI 2 "register_operand" "c,r,r")))]
1257 tbit.nz.or.andcm %0, %I0 = %2, 0
1260 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1261 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1262 [(cond_exec (ne (match_dup 2) (const_int 0))
1263 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1266 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1268 (define_insn_and_split "*iorcmbi3"
1269 [(set (match_operand:BI 0 "register_operand" "=c,c")
1270 (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
1271 (match_operand:BI 2 "register_operand" "0,0")))]
1275 tbit.z.or.andcm %0, %I0 = %1, 0"
1277 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1278 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1279 [(cond_exec (eq (match_dup 1) (const_int 0))
1280 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1283 [(set_attr "itanium_class" "unknown,tbit")])
1285 (define_insn "one_cmplbi2"
1286 [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
1287 (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
1288 (clobber (match_scratch:BI 2 "=X,X,c,X"))]
1291 tbit.z %0, %I0 = %1, 0
1295 [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
1298 [(set (match_operand:BI 0 "register_operand" "")
1299 (not:BI (match_operand:BI 1 "register_operand" "")))
1300 (clobber (match_scratch:BI 2 ""))]
1302 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1303 && rtx_equal_p (operands[0], operands[1])"
1304 [(set (match_dup 4) (match_dup 3))
1305 (set (match_dup 0) (const_int 1))
1306 (cond_exec (ne (match_dup 2) (const_int 0))
1307 (set (match_dup 0) (const_int 0)))
1308 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1309 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1310 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
1313 [(set (match_operand:BI 0 "register_operand" "")
1314 (not:BI (match_operand:BI 1 "register_operand" "")))
1315 (clobber (match_scratch:BI 2 ""))]
1317 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1318 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1319 && ! rtx_equal_p (operands[0], operands[1])"
1320 [(cond_exec (ne (match_dup 1) (const_int 0))
1321 (set (match_dup 0) (const_int 0)))
1322 (cond_exec (eq (match_dup 1) (const_int 0))
1323 (set (match_dup 0) (const_int 1)))
1324 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1327 (define_insn "*cmpsi_and_0"
1328 [(set (match_operand:BI 0 "register_operand" "=c")
1329 (and:BI (match_operator:BI 4 "predicate_operator"
1330 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1331 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1332 (match_operand:BI 1 "register_operand" "0")))]
1334 "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
1335 [(set_attr "itanium_class" "icmp")])
1337 (define_insn "*cmpsi_and_1"
1338 [(set (match_operand:BI 0 "register_operand" "=c")
1339 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1340 [(match_operand:SI 2 "gr_register_operand" "r")
1342 (match_operand:BI 1 "register_operand" "0")))]
1344 "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
1345 [(set_attr "itanium_class" "icmp")])
1347 (define_insn "*cmpsi_andnot_0"
1348 [(set (match_operand:BI 0 "register_operand" "=c")
1349 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1350 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1351 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1352 (match_operand:BI 1 "register_operand" "0")))]
1354 "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
1355 [(set_attr "itanium_class" "icmp")])
1357 (define_insn "*cmpsi_andnot_1"
1358 [(set (match_operand:BI 0 "register_operand" "=c")
1359 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1360 [(match_operand:SI 2 "gr_register_operand" "r")
1362 (match_operand:BI 1 "register_operand" "0")))]
1364 "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
1365 [(set_attr "itanium_class" "icmp")])
1367 (define_insn "*cmpdi_and_0"
1368 [(set (match_operand:BI 0 "register_operand" "=c")
1369 (and:BI (match_operator:BI 4 "predicate_operator"
1370 [(match_operand:DI 2 "gr_register_operand" "r")
1371 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1372 (match_operand:BI 1 "register_operand" "0")))]
1374 "cmp.%C4.and.orcm %0, %I0 = %3, %2"
1375 [(set_attr "itanium_class" "icmp")])
1377 (define_insn "*cmpdi_and_1"
1378 [(set (match_operand:BI 0 "register_operand" "=c")
1379 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1380 [(match_operand:DI 2 "gr_register_operand" "r")
1382 (match_operand:BI 1 "register_operand" "0")))]
1384 "cmp.%C3.and.orcm %0, %I0 = r0, %2"
1385 [(set_attr "itanium_class" "icmp")])
1387 (define_insn "*cmpdi_andnot_0"
1388 [(set (match_operand:BI 0 "register_operand" "=c")
1389 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1390 [(match_operand:DI 2 "gr_register_operand" "r")
1391 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1392 (match_operand:BI 1 "register_operand" "0")))]
1394 "cmp.%C4.or.andcm %I0, %0 = %3, %2"
1395 [(set_attr "itanium_class" "icmp")])
1397 (define_insn "*cmpdi_andnot_1"
1398 [(set (match_operand:BI 0 "register_operand" "=c")
1399 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1400 [(match_operand:DI 2 "gr_register_operand" "r")
1402 (match_operand:BI 1 "register_operand" "0")))]
1404 "cmp.%C3.or.andcm %I0, %0 = r0, %2"
1405 [(set_attr "itanium_class" "icmp")])
1407 (define_insn "*tbit_and_0"
1408 [(set (match_operand:BI 0 "register_operand" "=c")
1409 (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1412 (match_operand:BI 2 "register_operand" "0")))]
1414 "tbit.nz.and.orcm %0, %I0 = %1, 0"
1415 [(set_attr "itanium_class" "tbit")])
1417 (define_insn "*tbit_and_1"
1418 [(set (match_operand:BI 0 "register_operand" "=c")
1419 (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1422 (match_operand:BI 2 "register_operand" "0")))]
1424 "tbit.z.and.orcm %0, %I0 = %1, 0"
1425 [(set_attr "itanium_class" "tbit")])
1427 (define_insn "*tbit_and_2"
1428 [(set (match_operand:BI 0 "register_operand" "=c")
1429 (and:BI (ne:BI (zero_extract:DI
1430 (match_operand:DI 1 "gr_register_operand" "r")
1432 (match_operand:DI 2 "shift_count_operand" "M"))
1434 (match_operand:BI 3 "register_operand" "0")))]
1436 "tbit.nz.and.orcm %0, %I0 = %1, %2"
1437 [(set_attr "itanium_class" "tbit")])
1439 (define_insn "*tbit_and_3"
1440 [(set (match_operand:BI 0 "register_operand" "=c")
1441 (and:BI (eq:BI (zero_extract:DI
1442 (match_operand:DI 1 "gr_register_operand" "r")
1444 (match_operand:DI 2 "shift_count_operand" "M"))
1446 (match_operand:BI 3 "register_operand" "0")))]
1448 "tbit.z.and.orcm %0, %I0 = %1, %2"
1449 [(set_attr "itanium_class" "tbit")])
1451 (define_insn "*cmpsi_or_0"
1452 [(set (match_operand:BI 0 "register_operand" "=c")
1453 (ior:BI (match_operator:BI 4 "predicate_operator"
1454 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1455 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1456 (match_operand:BI 1 "register_operand" "0")))]
1458 "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
1459 [(set_attr "itanium_class" "icmp")])
1461 (define_insn "*cmpsi_or_1"
1462 [(set (match_operand:BI 0 "register_operand" "=c")
1463 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1464 [(match_operand:SI 2 "gr_register_operand" "r")
1466 (match_operand:BI 1 "register_operand" "0")))]
1468 "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
1469 [(set_attr "itanium_class" "icmp")])
1471 (define_insn "*cmpsi_orcm_0"
1472 [(set (match_operand:BI 0 "register_operand" "=c")
1473 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1474 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1475 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1476 (match_operand:BI 1 "register_operand" "0")))]
1478 "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
1479 [(set_attr "itanium_class" "icmp")])
1481 (define_insn "*cmpsi_orcm_1"
1482 [(set (match_operand:BI 0 "register_operand" "=c")
1483 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1484 [(match_operand:SI 2 "gr_register_operand" "r")
1486 (match_operand:BI 1 "register_operand" "0")))]
1488 "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
1489 [(set_attr "itanium_class" "icmp")])
1491 (define_insn "*cmpdi_or_0"
1492 [(set (match_operand:BI 0 "register_operand" "=c")
1493 (ior:BI (match_operator:BI 4 "predicate_operator"
1494 [(match_operand:DI 2 "gr_register_operand" "r")
1495 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1496 (match_operand:BI 1 "register_operand" "0")))]
1498 "cmp.%C4.or.andcm %0, %I0 = %3, %2"
1499 [(set_attr "itanium_class" "icmp")])
1501 (define_insn "*cmpdi_or_1"
1502 [(set (match_operand:BI 0 "register_operand" "=c")
1503 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1504 [(match_operand:DI 2 "gr_register_operand" "r")
1506 (match_operand:BI 1 "register_operand" "0")))]
1508 "cmp.%C3.or.andcm %0, %I0 = r0, %2"
1509 [(set_attr "itanium_class" "icmp")])
1511 (define_insn "*cmpdi_orcm_0"
1512 [(set (match_operand:BI 0 "register_operand" "=c")
1513 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1514 [(match_operand:DI 2 "gr_register_operand" "r")
1515 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1516 (match_operand:BI 1 "register_operand" "0")))]
1518 "cmp.%C4.and.orcm %I0, %0 = %3, %2"
1519 [(set_attr "itanium_class" "icmp")])
1521 (define_insn "*cmpdi_orcm_1"
1522 [(set (match_operand:BI 0 "register_operand" "=c")
1523 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1524 [(match_operand:DI 2 "gr_register_operand" "r")
1526 (match_operand:BI 1 "register_operand" "0")))]
1528 "cmp.%C3.and.orcm %I0, %0 = r0, %2"
1529 [(set_attr "itanium_class" "icmp")])
1531 (define_insn "*tbit_or_0"
1532 [(set (match_operand:BI 0 "register_operand" "=c")
1533 (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1536 (match_operand:BI 2 "register_operand" "0")))]
1538 "tbit.nz.or.andcm %0, %I0 = %1, 0"
1539 [(set_attr "itanium_class" "tbit")])
1541 (define_insn "*tbit_or_1"
1542 [(set (match_operand:BI 0 "register_operand" "=c")
1543 (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1546 (match_operand:BI 2 "register_operand" "0")))]
1548 "tbit.z.or.andcm %0, %I0 = %1, 0"
1549 [(set_attr "itanium_class" "tbit")])
1551 (define_insn "*tbit_or_2"
1552 [(set (match_operand:BI 0 "register_operand" "=c")
1553 (ior:BI (ne:BI (zero_extract:DI
1554 (match_operand:DI 1 "gr_register_operand" "r")
1556 (match_operand:DI 2 "shift_count_operand" "M"))
1558 (match_operand:BI 3 "register_operand" "0")))]
1560 "tbit.nz.or.andcm %0, %I0 = %1, %2"
1561 [(set_attr "itanium_class" "tbit")])
1563 (define_insn "*tbit_or_3"
1564 [(set (match_operand:BI 0 "register_operand" "=c")
1565 (ior:BI (eq:BI (zero_extract:DI
1566 (match_operand:DI 1 "gr_register_operand" "r")
1568 (match_operand:DI 2 "shift_count_operand" "M"))
1570 (match_operand:BI 3 "register_operand" "0")))]
1572 "tbit.z.or.andcm %0, %I0 = %1, %2"
1573 [(set_attr "itanium_class" "tbit")])
1575 ;; Transform test of and/or of setcc into parallel comparisons.
1578 [(set (match_operand:BI 0 "register_operand" "")
1579 (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1581 (match_operand:DI 3 "register_operand" ""))
1585 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1590 [(set (match_operand:BI 0 "register_operand" "")
1591 (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1593 (match_operand:DI 3 "register_operand" ""))
1597 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1599 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1600 (clobber (scratch))])]
1604 [(set (match_operand:BI 0 "register_operand" "")
1605 (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1607 (match_operand:DI 3 "register_operand" ""))
1611 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1616 [(set (match_operand:BI 0 "register_operand" "")
1617 (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1619 (match_operand:DI 3 "register_operand" ""))
1623 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1625 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1626 (clobber (scratch))])]
1629 ;; ??? Incredibly hackish. Either need four proper patterns with all
1630 ;; the alternatives, or rely on sched1 to split the insn and hope that
1631 ;; nothing bad happens to the comparisons in the meantime.
1633 ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
1634 ;; that we're doing height reduction.
1636 ;(define_insn_and_split ""
1637 ; [(set (match_operand:BI 0 "register_operand" "=c")
1638 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1639 ; [(match_operand 2 "" "")
1640 ; (match_operand 3 "" "")])
1641 ; (match_operator:BI 4 "comparison_operator"
1642 ; [(match_operand 5 "" "")
1643 ; (match_operand 6 "" "")]))
1645 ; "flag_schedule_insns"
1648 ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
1649 ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
1652 ;(define_insn_and_split ""
1653 ; [(set (match_operand:BI 0 "register_operand" "=c")
1654 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1655 ; [(match_operand 2 "" "")
1656 ; (match_operand 3 "" "")])
1657 ; (match_operator:BI 4 "comparison_operator"
1658 ; [(match_operand 5 "" "")
1659 ; (match_operand 6 "" "")]))
1661 ; "flag_schedule_insns"
1664 ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
1665 ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
1669 ; [(set (match_operand:BI 0 "register_operand" "")
1670 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1671 ; [(match_operand 2 "" "")
1672 ; (match_operand 3 "" "")])
1673 ; (match_operand:BI 7 "register_operand" ""))
1674 ; (and:BI (match_operator:BI 4 "comparison_operator"
1675 ; [(match_operand 5 "" "")
1676 ; (match_operand 6 "" "")])
1677 ; (match_operand:BI 8 "register_operand" ""))))]
1679 ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
1680 ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
1685 ; [(set (match_operand:BI 0 "register_operand" "")
1686 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1687 ; [(match_operand 2 "" "")
1688 ; (match_operand 3 "" "")])
1689 ; (match_operand:BI 7 "register_operand" ""))
1690 ; (ior:BI (match_operator:BI 4 "comparison_operator"
1691 ; [(match_operand 5 "" "")
1692 ; (match_operand 6 "" "")])
1693 ; (match_operand:BI 8 "register_operand" ""))))]
1695 ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
1696 ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
1700 ;; Try harder to avoid predicate copies by duplicating compares.
1701 ;; Note that we'll have already split the predicate copy, which
1702 ;; is kind of a pain, but oh well.
1705 [(set (match_operand:BI 0 "register_operand" "")
1706 (match_operand:BI 1 "comparison_operator" ""))
1707 (set (match_operand:CCI 2 "register_operand" "")
1708 (match_operand:CCI 3 "register_operand" ""))
1709 (set (match_operand:CCI 4 "register_operand" "")
1710 (match_operand:CCI 5 "register_operand" ""))
1711 (set (match_operand:BI 6 "register_operand" "")
1712 (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))]
1713 "REGNO (operands[3]) == REGNO (operands[0])
1714 && REGNO (operands[4]) == REGNO (operands[0]) + 1
1715 && REGNO (operands[4]) == REGNO (operands[2]) + 1
1716 && REGNO (operands[6]) == REGNO (operands[2])"
1717 [(set (match_dup 0) (match_dup 1))
1718 (set (match_dup 6) (match_dup 7))]
1719 "operands[7] = copy_rtx (operands[1]);")
1721 ;; ::::::::::::::::::::
1723 ;; :: 16 bit Integer arithmetic
1725 ;; ::::::::::::::::::::
1727 (define_insn "mulhi3"
1728 [(set (match_operand:HI 0 "gr_register_operand" "=r")
1729 (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
1730 (match_operand:HI 2 "gr_register_operand" "r")))]
1732 "pmpy2.r %0 = %1, %2"
1733 [(set_attr "itanium_class" "mmmul")])
1736 ;; ::::::::::::::::::::
1738 ;; :: 32 bit Integer arithmetic
1740 ;; ::::::::::::::::::::
1742 (define_insn "addsi3"
1743 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
1744 (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a")
1745 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
1751 [(set_attr "itanium_class" "ialu")])
1753 (define_insn "*addsi3_plus1"
1754 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1755 (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r")
1756 (match_operand:SI 2 "gr_register_operand" "r"))
1759 "add %0 = %1, %2, 1"
1760 [(set_attr "itanium_class" "ialu")])
1762 (define_insn "*addsi3_plus1_alt"
1763 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1764 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
1768 "add %0 = %1, %1, 1"
1769 [(set_attr "itanium_class" "ialu")])
1771 (define_insn "*addsi3_shladd"
1772 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1773 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
1774 (match_operand:SI 2 "shladd_operand" "n"))
1775 (match_operand:SI 3 "gr_register_operand" "r")))]
1777 "shladd %0 = %1, %S2, %3"
1778 [(set_attr "itanium_class" "ialu")])
1780 (define_insn "subsi3"
1781 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1782 (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK")
1783 (match_operand:SI 2 "gr_register_operand" "r")))]
1786 [(set_attr "itanium_class" "ialu")])
1788 (define_insn "*subsi3_minus1"
1789 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1790 (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r"))
1791 (match_operand:SI 2 "gr_register_operand" "r")))]
1793 "sub %0 = %2, %1, 1"
1794 [(set_attr "itanium_class" "ialu")])
1796 ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
1798 (define_insn "mulsi3"
1799 [(set (match_operand:SI 0 "fr_register_operand" "=f")
1800 (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
1801 (match_operand:SI 2 "grfr_register_operand" "f")))]
1803 "xmpy.l %0 = %1, %2"
1804 [(set_attr "itanium_class" "xmpy")])
1806 (define_insn "maddsi4"
1807 [(set (match_operand:SI 0 "fr_register_operand" "=f")
1808 (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
1809 (match_operand:SI 2 "grfr_register_operand" "f"))
1810 (match_operand:SI 3 "grfr_register_operand" "f")))]
1812 "xma.l %0 = %1, %2, %3"
1813 [(set_attr "itanium_class" "xmpy")])
1815 (define_insn "negsi2"
1816 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1817 (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
1820 [(set_attr "itanium_class" "ialu")])
1822 (define_expand "abssi2"
1824 (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
1825 (set (match_operand:SI 0 "gr_register_operand" "")
1826 (if_then_else:SI (eq (match_dup 2) (const_int 0))
1827 (neg:SI (match_dup 1))
1830 { operands[2] = gen_reg_rtx (BImode); })
1832 (define_expand "sminsi3"
1834 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
1835 (match_operand:SI 2 "gr_register_operand" "")))
1836 (set (match_operand:SI 0 "gr_register_operand" "")
1837 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1838 (match_dup 2) (match_dup 1)))]
1840 { operands[3] = gen_reg_rtx (BImode); })
1842 (define_expand "smaxsi3"
1844 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
1845 (match_operand:SI 2 "gr_register_operand" "")))
1846 (set (match_operand:SI 0 "gr_register_operand" "")
1847 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1848 (match_dup 1) (match_dup 2)))]
1850 { operands[3] = gen_reg_rtx (BImode); })
1852 (define_expand "uminsi3"
1854 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
1855 (match_operand:SI 2 "gr_register_operand" "")))
1856 (set (match_operand:SI 0 "gr_register_operand" "")
1857 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1858 (match_dup 2) (match_dup 1)))]
1860 { operands[3] = gen_reg_rtx (BImode); })
1862 (define_expand "umaxsi3"
1864 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
1865 (match_operand:SI 2 "gr_register_operand" "")))
1866 (set (match_operand:SI 0 "gr_register_operand" "")
1867 (if_then_else:SI (ne (match_dup 3) (const_int 0))
1868 (match_dup 1) (match_dup 2)))]
1870 { operands[3] = gen_reg_rtx (BImode); })
1872 (define_expand "divsi3"
1873 [(set (match_operand:SI 0 "register_operand" "")
1874 (div:SI (match_operand:SI 1 "general_operand" "")
1875 (match_operand:SI 2 "general_operand" "")))]
1876 "TARGET_INLINE_INT_DIV"
1878 rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp;
1880 op0_xf = gen_reg_rtx (XFmode);
1881 op0_di = gen_reg_rtx (DImode);
1883 if (CONSTANT_P (operands[1]))
1884 operands[1] = force_reg (SImode, operands[1]);
1885 op1_xf = gen_reg_rtx (XFmode);
1886 expand_float (op1_xf, operands[1], 0);
1888 if (CONSTANT_P (operands[2]))
1889 operands[2] = force_reg (SImode, operands[2]);
1890 op2_xf = gen_reg_rtx (XFmode);
1891 expand_float (op2_xf, operands[2], 0);
1894 twon34_exp = gen_reg_rtx (DImode);
1895 emit_move_insn (twon34_exp, GEN_INT (65501));
1896 twon34 = gen_reg_rtx (XFmode);
1897 emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
1899 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode),
1900 CONST1_RTX (SImode)));
1902 emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
1904 emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
1905 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
1909 (define_expand "modsi3"
1910 [(set (match_operand:SI 0 "register_operand" "")
1911 (mod:SI (match_operand:SI 1 "general_operand" "")
1912 (match_operand:SI 2 "general_operand" "")))]
1913 "TARGET_INLINE_INT_DIV"
1915 rtx op2_neg, op1_di, div;
1917 div = gen_reg_rtx (SImode);
1918 emit_insn (gen_divsi3 (div, operands[1], operands[2]));
1920 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
1922 /* This is a trick to get us to reuse the value that we're sure to
1923 have already copied to the FP regs. */
1924 op1_di = gen_reg_rtx (DImode);
1925 convert_move (op1_di, operands[1], 0);
1927 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
1928 gen_lowpart (SImode, op1_di)));
1932 (define_expand "udivsi3"
1933 [(set (match_operand:SI 0 "register_operand" "")
1934 (udiv:SI (match_operand:SI 1 "general_operand" "")
1935 (match_operand:SI 2 "general_operand" "")))]
1936 "TARGET_INLINE_INT_DIV"
1938 rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp;
1940 op0_xf = gen_reg_rtx (XFmode);
1941 op0_di = gen_reg_rtx (DImode);
1943 if (CONSTANT_P (operands[1]))
1944 operands[1] = force_reg (SImode, operands[1]);
1945 op1_xf = gen_reg_rtx (XFmode);
1946 expand_float (op1_xf, operands[1], 1);
1948 if (CONSTANT_P (operands[2]))
1949 operands[2] = force_reg (SImode, operands[2]);
1950 op2_xf = gen_reg_rtx (XFmode);
1951 expand_float (op2_xf, operands[2], 1);
1954 twon34_exp = gen_reg_rtx (DImode);
1955 emit_move_insn (twon34_exp, GEN_INT (65501));
1956 twon34 = gen_reg_rtx (XFmode);
1957 emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
1959 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode),
1960 CONST1_RTX (SImode)));
1962 emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
1964 emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
1965 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
1969 (define_expand "umodsi3"
1970 [(set (match_operand:SI 0 "register_operand" "")
1971 (umod:SI (match_operand:SI 1 "general_operand" "")
1972 (match_operand:SI 2 "general_operand" "")))]
1973 "TARGET_INLINE_INT_DIV"
1975 rtx op2_neg, op1_di, div;
1977 div = gen_reg_rtx (SImode);
1978 emit_insn (gen_udivsi3 (div, operands[1], operands[2]));
1980 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
1982 /* This is a trick to get us to reuse the value that we're sure to
1983 have already copied to the FP regs. */
1984 op1_di = gen_reg_rtx (DImode);
1985 convert_move (op1_di, operands[1], 1);
1987 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
1988 gen_lowpart (SImode, op1_di)));
1992 (define_insn_and_split "divsi3_internal"
1993 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
1994 (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
1995 (match_operand:XF 2 "fr_register_operand" "f"))))
1996 (clobber (match_scratch:XF 4 "=&f"))
1997 (clobber (match_scratch:XF 5 "=&f"))
1998 (clobber (match_scratch:BI 6 "=c"))
1999 (use (match_operand:XF 3 "fr_register_operand" "f"))]
2000 "TARGET_INLINE_INT_DIV"
2002 "&& reload_completed"
2003 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
2004 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
2005 UNSPEC_FR_RECIP_APPROX))
2006 (use (const_int 1))])
2007 (cond_exec (ne (match_dup 6) (const_int 0))
2008 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
2009 (use (const_int 1))]))
2010 (cond_exec (ne (match_dup 6) (const_int 0))
2011 (parallel [(set (match_dup 5)
2012 (minus:XF (match_dup 7)
2013 (mult:XF (match_dup 2) (match_dup 0))))
2014 (use (const_int 1))]))
2015 (cond_exec (ne (match_dup 6) (const_int 0))
2016 (parallel [(set (match_dup 4)
2017 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
2019 (use (const_int 1))]))
2020 (cond_exec (ne (match_dup 6) (const_int 0))
2021 (parallel [(set (match_dup 5)
2022 (plus:XF (mult:XF (match_dup 5) (match_dup 5))
2024 (use (const_int 1))]))
2025 (cond_exec (ne (match_dup 6) (const_int 0))
2026 (parallel [(set (match_dup 0)
2027 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
2029 (use (const_int 1))]))
2031 "operands[7] = CONST1_RTX (XFmode);"
2032 [(set_attr "predicable" "no")])
2034 ;; ::::::::::::::::::::
2036 ;; :: 64 bit Integer arithmetic
2038 ;; ::::::::::::::::::::
2040 (define_insn "adddi3"
2041 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
2042 (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a")
2043 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2049 [(set_attr "itanium_class" "ialu")])
2051 (define_insn "*adddi3_plus1"
2052 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2053 (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r")
2054 (match_operand:DI 2 "gr_register_operand" "r"))
2057 "add %0 = %1, %2, 1"
2058 [(set_attr "itanium_class" "ialu")])
2060 ;; This has some of the same problems as shladd. We let the shladd
2061 ;; eliminator hack handle it, which results in the 1 being forced into
2062 ;; a register, but not more ugliness here.
2063 (define_insn "*adddi3_plus1_alt"
2064 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2065 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
2069 "add %0 = %1, %1, 1"
2070 [(set_attr "itanium_class" "ialu")])
2072 (define_insn "subdi3"
2073 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2074 (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK")
2075 (match_operand:DI 2 "gr_register_operand" "r")))]
2078 [(set_attr "itanium_class" "ialu")])
2080 (define_insn "*subdi3_minus1"
2081 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2082 (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r"))
2083 (match_operand:DI 2 "gr_register_operand" "r")))]
2085 "sub %0 = %2, %1, 1"
2086 [(set_attr "itanium_class" "ialu")])
2088 ;; ??? Use grfr instead of fr because of virtual register elimination
2089 ;; and silly test cases multiplying by the frame pointer.
2090 (define_insn "muldi3"
2091 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2092 (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2093 (match_operand:DI 2 "grfr_register_operand" "f")))]
2095 "xmpy.l %0 = %1, %2"
2096 [(set_attr "itanium_class" "xmpy")])
2098 ;; ??? If operand 3 is an eliminable reg, then register elimination causes the
2099 ;; same problem that we have with shladd below. Unfortunately, this case is
2100 ;; much harder to fix because the multiply puts the result in an FP register,
2101 ;; but the add needs inputs from a general register. We add a spurious clobber
2102 ;; here so that it will be present just in case register elimination gives us
2103 ;; the funny result.
2105 ;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2107 ;; ??? Maybe we should change how adds are canonicalized.
2109 (define_insn "madddi4"
2110 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2111 (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2112 (match_operand:DI 2 "grfr_register_operand" "f"))
2113 (match_operand:DI 3 "grfr_register_operand" "f")))
2114 (clobber (match_scratch:DI 4 "=X"))]
2116 "xma.l %0 = %1, %2, %3"
2117 [(set_attr "itanium_class" "xmpy")])
2119 ;; This can be created by register elimination if operand3 of shladd is an
2120 ;; eliminable register or has reg_equiv_constant set.
2122 ;; We have to use nonmemory_operand for operand 4, to ensure that the
2123 ;; validate_changes call inside eliminate_regs will always succeed. If it
2124 ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
2127 (define_insn "*madddi4_elim"
2128 [(set (match_operand:DI 0 "register_operand" "=&r")
2129 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
2130 (match_operand:DI 2 "register_operand" "f"))
2131 (match_operand:DI 3 "register_operand" "f"))
2132 (match_operand:DI 4 "nonmemory_operand" "rI")))
2133 (clobber (match_scratch:DI 5 "=f"))]
2134 "reload_in_progress"
2136 [(set_attr "itanium_class" "unknown")])
2139 [(set (match_operand:DI 0 "register_operand" "")
2140 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2141 (match_operand:DI 2 "register_operand" ""))
2142 (match_operand:DI 3 "register_operand" ""))
2143 (match_operand:DI 4 "gr_reg_or_14bit_operand" "")))
2144 (clobber (match_scratch:DI 5 ""))]
2146 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
2148 (clobber (match_dup 0))])
2149 (set (match_dup 0) (match_dup 5))
2150 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
2153 (define_insn "smuldi3_highpart"
2154 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2157 (mult:TI (sign_extend:TI
2158 (match_operand:DI 1 "fr_register_operand" "f"))
2160 (match_operand:DI 2 "fr_register_operand" "f")))
2163 "xmpy.h %0 = %1, %2"
2164 [(set_attr "itanium_class" "xmpy")])
2166 (define_insn "umuldi3_highpart"
2167 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2170 (mult:TI (zero_extend:TI
2171 (match_operand:DI 1 "fr_register_operand" "f"))
2173 (match_operand:DI 2 "fr_register_operand" "f")))
2176 "xmpy.hu %0 = %1, %2"
2177 [(set_attr "itanium_class" "xmpy")])
2179 (define_insn "negdi2"
2180 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2181 (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2184 [(set_attr "itanium_class" "ialu")])
2186 (define_expand "absdi2"
2188 (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2189 (set (match_operand:DI 0 "gr_register_operand" "")
2190 (if_then_else:DI (eq (match_dup 2) (const_int 0))
2191 (neg:DI (match_dup 1))
2194 { operands[2] = gen_reg_rtx (BImode); })
2196 (define_expand "smindi3"
2198 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2199 (match_operand:DI 2 "gr_register_operand" "")))
2200 (set (match_operand:DI 0 "gr_register_operand" "")
2201 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2202 (match_dup 2) (match_dup 1)))]
2204 { operands[3] = gen_reg_rtx (BImode); })
2206 (define_expand "smaxdi3"
2208 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2209 (match_operand:DI 2 "gr_register_operand" "")))
2210 (set (match_operand:DI 0 "gr_register_operand" "")
2211 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2212 (match_dup 1) (match_dup 2)))]
2214 { operands[3] = gen_reg_rtx (BImode); })
2216 (define_expand "umindi3"
2218 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2219 (match_operand:DI 2 "gr_register_operand" "")))
2220 (set (match_operand:DI 0 "gr_register_operand" "")
2221 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2222 (match_dup 2) (match_dup 1)))]
2224 { operands[3] = gen_reg_rtx (BImode); })
2226 (define_expand "umaxdi3"
2228 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2229 (match_operand:DI 2 "gr_register_operand" "")))
2230 (set (match_operand:DI 0 "gr_register_operand" "")
2231 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2232 (match_dup 1) (match_dup 2)))]
2234 { operands[3] = gen_reg_rtx (BImode); })
2236 (define_expand "ffsdi2"
2238 (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2239 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
2240 (set (match_dup 5) (const_int 0))
2241 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
2242 (set (match_dup 4) (popcount:DI (match_dup 3)))
2243 (set (match_operand:DI 0 "gr_register_operand" "")
2244 (if_then_else:DI (ne (match_dup 6) (const_int 0))
2245 (match_dup 5) (match_dup 4)))]
2248 operands[2] = gen_reg_rtx (DImode);
2249 operands[3] = gen_reg_rtx (DImode);
2250 operands[4] = gen_reg_rtx (DImode);
2251 operands[5] = gen_reg_rtx (DImode);
2252 operands[6] = gen_reg_rtx (BImode);
2255 (define_expand "ctzdi2"
2256 [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "")
2258 (set (match_dup 3) (not:DI (match_dup 1)))
2259 (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3)))
2260 (set (match_operand:DI 0 "gr_register_operand" "")
2261 (popcount:DI (match_dup 4)))]
2264 operands[2] = gen_reg_rtx (DImode);
2265 operands[3] = gen_reg_rtx (DImode);
2266 operands[4] = gen_reg_rtx (DImode);
2269 ;; Note the computation here is op0 = 63 - (exp - 0xffff).
2270 (define_expand "clzdi2"
2272 (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "")))
2274 (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP))
2275 (set (match_dup 4) (const_int 65598))
2276 (set (match_operand:DI 0 "gr_register_operand" "")
2277 (minus:DI (match_dup 4) (match_dup 3)))]
2280 operands[2] = gen_reg_rtx (XFmode);
2281 operands[3] = gen_reg_rtx (DImode);
2282 operands[4] = gen_reg_rtx (DImode);
2285 (define_insn "popcountdi2"
2286 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2287 (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2290 [(set_attr "itanium_class" "mmmul")])
2292 (define_insn "*getf_exp_xf"
2293 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2294 (unspec:DI [(match_operand:XF 1 "fr_register_operand" "f")]
2298 [(set_attr "itanium_class" "frfr")])
2300 (define_expand "divdi3"
2301 [(set (match_operand:DI 0 "register_operand" "")
2302 (div:DI (match_operand:DI 1 "general_operand" "")
2303 (match_operand:DI 2 "general_operand" "")))]
2304 "TARGET_INLINE_INT_DIV"
2306 rtx op1_xf, op2_xf, op0_xf;
2308 op0_xf = gen_reg_rtx (XFmode);
2310 if (CONSTANT_P (operands[1]))
2311 operands[1] = force_reg (DImode, operands[1]);
2312 op1_xf = gen_reg_rtx (XFmode);
2313 expand_float (op1_xf, operands[1], 0);
2315 if (CONSTANT_P (operands[2]))
2316 operands[2] = force_reg (DImode, operands[2]);
2317 op2_xf = gen_reg_rtx (XFmode);
2318 expand_float (op2_xf, operands[2], 0);
2320 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode),
2321 CONST1_RTX (DImode)));
2323 if (TARGET_INLINE_INT_DIV == INL_MIN_LAT)
2324 emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
2326 emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
2328 emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx));
2332 (define_expand "moddi3"
2333 [(set (match_operand:DI 0 "register_operand" "")
2334 (mod:SI (match_operand:DI 1 "general_operand" "")
2335 (match_operand:DI 2 "general_operand" "")))]
2336 "TARGET_INLINE_INT_DIV"
2340 div = gen_reg_rtx (DImode);
2341 emit_insn (gen_divdi3 (div, operands[1], operands[2]));
2343 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2345 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2349 (define_expand "udivdi3"
2350 [(set (match_operand:DI 0 "register_operand" "")
2351 (udiv:DI (match_operand:DI 1 "general_operand" "")
2352 (match_operand:DI 2 "general_operand" "")))]
2353 "TARGET_INLINE_INT_DIV"
2355 rtx op1_xf, op2_xf, op0_xf;
2357 op0_xf = gen_reg_rtx (XFmode);
2359 if (CONSTANT_P (operands[1]))
2360 operands[1] = force_reg (DImode, operands[1]);
2361 op1_xf = gen_reg_rtx (XFmode);
2362 expand_float (op1_xf, operands[1], 1);
2364 if (CONSTANT_P (operands[2]))
2365 operands[2] = force_reg (DImode, operands[2]);
2366 op2_xf = gen_reg_rtx (XFmode);
2367 expand_float (op2_xf, operands[2], 1);
2369 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode),
2370 CONST1_RTX (DImode)));
2372 if (TARGET_INLINE_INT_DIV == INL_MIN_LAT)
2373 emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
2375 emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
2377 emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx));
2381 (define_expand "umoddi3"
2382 [(set (match_operand:DI 0 "register_operand" "")
2383 (umod:DI (match_operand:DI 1 "general_operand" "")
2384 (match_operand:DI 2 "general_operand" "")))]
2385 "TARGET_INLINE_INT_DIV"
2389 div = gen_reg_rtx (DImode);
2390 emit_insn (gen_udivdi3 (div, operands[1], operands[2]));
2392 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2394 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2398 (define_insn_and_split "divdi3_internal_lat"
2399 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
2400 (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
2401 (match_operand:XF 2 "fr_register_operand" "f"))))
2402 (clobber (match_scratch:XF 3 "=&f"))
2403 (clobber (match_scratch:XF 4 "=&f"))
2404 (clobber (match_scratch:XF 5 "=&f"))
2405 (clobber (match_scratch:BI 6 "=c"))]
2406 "TARGET_INLINE_INT_DIV == INL_MIN_LAT"
2408 "&& reload_completed"
2409 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
2410 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
2411 UNSPEC_FR_RECIP_APPROX))
2412 (use (const_int 1))])
2413 (cond_exec (ne (match_dup 6) (const_int 0))
2414 (parallel [(set (match_dup 3)
2415 (minus:XF (match_dup 7)
2416 (mult:XF (match_dup 2) (match_dup 0))))
2417 (use (const_int 1))]))
2418 (cond_exec (ne (match_dup 6) (const_int 0))
2419 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
2420 (use (const_int 1))]))
2421 (cond_exec (ne (match_dup 6) (const_int 0))
2422 (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3)))
2423 (use (const_int 1))]))
2424 (cond_exec (ne (match_dup 6) (const_int 0))
2425 (parallel [(set (match_dup 4)
2426 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
2428 (use (const_int 1))]))
2429 (cond_exec (ne (match_dup 6) (const_int 0))
2430 (parallel [(set (match_dup 0)
2431 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
2433 (use (const_int 1))]))
2434 (cond_exec (ne (match_dup 6) (const_int 0))
2435 (parallel [(set (match_dup 3)
2436 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
2438 (use (const_int 1))]))
2439 (cond_exec (ne (match_dup 6) (const_int 0))
2440 (parallel [(set (match_dup 0)
2441 (plus:XF (mult:XF (match_dup 5) (match_dup 0))
2443 (use (const_int 1))]))
2444 (cond_exec (ne (match_dup 6) (const_int 0))
2445 (parallel [(set (match_dup 4)
2446 (minus:XF (match_dup 1)
2447 (mult:XF (match_dup 2) (match_dup 3))))
2448 (use (const_int 1))]))
2449 (cond_exec (ne (match_dup 6) (const_int 0))
2450 (parallel [(set (match_dup 0)
2451 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
2453 (use (const_int 1))]))
2455 "operands[7] = CONST1_RTX (XFmode);"
2456 [(set_attr "predicable" "no")])
2458 (define_insn_and_split "divdi3_internal_thr"
2459 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
2460 (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
2461 (match_operand:XF 2 "fr_register_operand" "f"))))
2462 (clobber (match_scratch:XF 3 "=&f"))
2463 (clobber (match_scratch:XF 4 "=f"))
2464 (clobber (match_scratch:BI 5 "=c"))]
2465 "TARGET_INLINE_INT_DIV == INL_MAX_THR"
2467 "&& reload_completed"
2468 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
2469 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
2470 UNSPEC_FR_RECIP_APPROX))
2471 (use (const_int 1))])
2472 (cond_exec (ne (match_dup 5) (const_int 0))
2473 (parallel [(set (match_dup 3)
2474 (minus:XF (match_dup 6)
2475 (mult:XF (match_dup 2) (match_dup 0))))
2476 (use (const_int 1))]))
2477 (cond_exec (ne (match_dup 5) (const_int 0))
2478 (parallel [(set (match_dup 0)
2479 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
2481 (use (const_int 1))]))
2482 (cond_exec (ne (match_dup 5) (const_int 0))
2483 (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3)))
2484 (use (const_int 1))]))
2485 (cond_exec (ne (match_dup 5) (const_int 0))
2486 (parallel [(set (match_dup 0)
2487 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
2489 (use (const_int 1))]))
2490 (cond_exec (ne (match_dup 5) (const_int 0))
2491 (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1)))
2492 (use (const_int 1))]))
2493 (cond_exec (ne (match_dup 5) (const_int 0))
2494 (parallel [(set (match_dup 4)
2495 (minus:XF (match_dup 1)
2496 (mult:XF (match_dup 2) (match_dup 3))))
2497 (use (const_int 1))]))
2498 (cond_exec (ne (match_dup 5) (const_int 0))
2499 (parallel [(set (match_dup 0)
2500 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
2502 (use (const_int 1))]))
2504 "operands[6] = CONST1_RTX (XFmode);"
2505 [(set_attr "predicable" "no")])
2507 ;; ::::::::::::::::::::
2509 ;; :: 128 bit Integer arithmetic
2511 ;; ::::::::::::::::::::
2513 (define_insn "addti3"
2514 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2515 (plus:TI (match_operand:TI 1 "gr_register_operand" "%r")
2516 (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI")))
2517 (clobber (match_scratch:BI 3 "=&c"))]
2520 [(set_attr "itanium_class" "unknown")])
2523 [(set (match_operand:TI 0 "register_operand" "")
2524 (plus:TI (match_operand:TI 1 "register_operand" "")
2525 (match_operand:TI 2 "register_operand" "")))
2526 (clobber (match_scratch:BI 3 ""))]
2528 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
2529 (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
2530 (cond_exec (eq (match_dup 3) (const_int 0))
2531 (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6))))
2532 (cond_exec (ne (match_dup 3) (const_int 0))
2534 (plus:DI (plus:DI (match_dup 5) (match_dup 6))
2537 operands[4] = gen_highpart (DImode, operands[0]);
2538 operands[0] = gen_lowpart (DImode, operands[0]);
2539 operands[5] = gen_highpart (DImode, operands[1]);
2540 operands[1] = gen_lowpart (DImode, operands[1]);
2541 operands[6] = gen_highpart (DImode, operands[2]);
2542 operands[2] = gen_lowpart (DImode, operands[2]);
2546 [(set (match_operand:TI 0 "register_operand" "")
2547 (plus:TI (match_operand:TI 1 "register_operand" "")
2548 (match_operand:TI 2 "immediate_operand" "")))
2549 (clobber (match_scratch:BI 3 ""))]
2551 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
2552 (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
2553 (cond_exec (eq (match_dup 3) (const_int 0))
2555 (plus:DI (match_dup 5) (match_dup 6))))
2556 (cond_exec (ne (match_dup 3) (const_int 0))
2558 (plus:DI (match_dup 5) (match_dup 7))))]
2560 operands[4] = gen_highpart (DImode, operands[0]);
2561 operands[0] = gen_lowpart (DImode, operands[0]);
2562 operands[5] = gen_highpart (DImode, operands[1]);
2563 operands[1] = gen_lowpart (DImode, operands[1]);
2564 operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2565 operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx;
2568 (define_insn "subti3"
2569 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2570 (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK")
2571 (match_operand:TI 2 "gr_register_operand" "r")))
2572 (clobber (match_scratch:BI 3 "=&c"))]
2575 [(set_attr "itanium_class" "unknown")])
2578 [(set (match_operand:TI 0 "register_operand" "")
2579 (minus:TI (match_operand:TI 1 "register_operand" "")
2580 (match_operand:TI 2 "register_operand" "")))
2581 (clobber (match_scratch:BI 3 "=&c"))]
2583 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
2584 (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0)))
2585 (cond_exec (eq (match_dup 3) (const_int 0))
2586 (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6))))
2587 (cond_exec (ne (match_dup 3) (const_int 0))
2589 (plus:DI (not:DI (match_dup 6)) (match_dup 5))))]
2591 operands[4] = gen_highpart (DImode, operands[0]);
2592 operands[0] = gen_lowpart (DImode, operands[0]);
2593 operands[5] = gen_highpart (DImode, operands[1]);
2594 operands[1] = gen_lowpart (DImode, operands[1]);
2595 operands[6] = gen_highpart (DImode, operands[2]);
2596 operands[2] = gen_lowpart (DImode, operands[2]);
2600 [(set (match_operand:TI 0 "register_operand" "")
2601 (minus:TI (match_operand:TI 1 "immediate_operand" "")
2602 (match_operand:TI 2 "register_operand" "")))
2603 (clobber (match_scratch:BI 3 "=&c"))]
2604 "reload_completed && CONST_OK_FOR_K (INTVAL (operands[1]))"
2605 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
2606 (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1)))
2607 (cond_exec (ne (match_dup 3) (const_int 0))
2608 (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5))))
2609 (cond_exec (eq (match_dup 3) (const_int 0))
2610 (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))]
2612 operands[4] = gen_highpart (DImode, operands[0]);
2613 operands[0] = gen_lowpart (DImode, operands[0]);
2614 operands[5] = gen_highpart (DImode, operands[2]);
2615 operands[2] = gen_lowpart (DImode, operands[2]);
2616 operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx;
2617 operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
2620 (define_expand "mulditi3"
2621 [(set (match_operand:TI 0 "fr_register_operand" "")
2622 (mult:TI (sign_extend:TI
2623 (match_operand:DI 1 "fr_register_operand" ""))
2625 (match_operand:DI 2 "fr_register_operand" ""))))]
2629 (define_insn_and_split "*mulditi3_internal"
2630 [(set (match_operand:TI 0 "fr_register_operand" "=&f")
2631 (mult:TI (sign_extend:TI
2632 (match_operand:DI 1 "fr_register_operand" "%f"))
2634 (match_operand:DI 2 "fr_register_operand" "f"))))]
2638 [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
2639 (set (match_dup 3) (truncate:DI
2641 (mult:TI (sign_extend:TI (match_dup 1))
2642 (sign_extend:TI (match_dup 2)))
2645 operands[3] = gen_highpart (DImode, operands[0]);
2646 operands[0] = gen_lowpart (DImode, operands[0]);
2648 [(set_attr "itanium_class" "unknown")])
2650 (define_expand "umulditi3"
2651 [(set (match_operand:TI 0 "fr_register_operand" "")
2652 (mult:TI (zero_extend:TI
2653 (match_operand:DI 1 "fr_register_operand" ""))
2655 (match_operand:DI 2 "fr_register_operand" ""))))]
2659 (define_insn_and_split "*umulditi3_internal"
2660 [(set (match_operand:TI 0 "fr_register_operand" "=&f")
2661 (mult:TI (zero_extend:TI
2662 (match_operand:DI 1 "fr_register_operand" "%f"))
2664 (match_operand:DI 2 "fr_register_operand" "f"))))]
2668 [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
2669 (set (match_dup 3) (truncate:DI
2671 (mult:TI (zero_extend:TI (match_dup 1))
2672 (zero_extend:TI (match_dup 2)))
2675 operands[3] = gen_highpart (DImode, operands[0]);
2676 operands[0] = gen_lowpart (DImode, operands[0]);
2678 [(set_attr "itanium_class" "unknown")])
2680 (define_insn_and_split "negti2"
2681 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2682 (neg:TI (match_operand:TI 1 "gr_register_operand" "r")))
2683 (clobber (match_scratch:BI 2 "=&c"))]
2687 [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0)))
2688 (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1)))
2689 (cond_exec (eq (match_dup 2) (const_int 0))
2690 (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4))))
2691 (cond_exec (ne (match_dup 2) (const_int 0))
2692 (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))]
2694 operands[3] = gen_highpart (DImode, operands[0]);
2695 operands[0] = gen_lowpart (DImode, operands[0]);
2696 operands[4] = gen_highpart (DImode, operands[1]);
2697 operands[1] = gen_lowpart (DImode, operands[1]);
2699 [(set_attr "itanium_class" "unknown")])
2701 ;; ::::::::::::::::::::
2703 ;; :: 32 bit floating point arithmetic
2705 ;; ::::::::::::::::::::
2707 (define_insn "addsf3"
2708 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2709 (plus:SF (match_operand:SF 1 "fr_register_operand" "%f")
2710 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2712 "fadd.s %0 = %1, %F2"
2713 [(set_attr "itanium_class" "fmac")])
2715 (define_insn "subsf3"
2716 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2717 (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2718 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2720 "fsub.s %0 = %F1, %F2"
2721 [(set_attr "itanium_class" "fmac")])
2723 (define_insn "mulsf3"
2724 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2725 (mult:SF (match_operand:SF 1 "fr_register_operand" "%f")
2726 (match_operand:SF 2 "fr_register_operand" "f")))]
2728 "fmpy.s %0 = %1, %2"
2729 [(set_attr "itanium_class" "fmac")])
2731 (define_insn "abssf2"
2732 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2733 (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2736 [(set_attr "itanium_class" "fmisc")])
2738 (define_insn "negsf2"
2739 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2740 (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2743 [(set_attr "itanium_class" "fmisc")])
2745 (define_insn "*nabssf2"
2746 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2747 (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))]
2750 [(set_attr "itanium_class" "fmisc")])
2752 (define_insn "copysignsf3"
2753 [(set (match_operand:SF 0 "register_operand" "=f")
2754 (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2755 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
2758 "fmerge.s %0 = %F2, %F1"
2759 [(set_attr "itanium_class" "fmisc")])
2761 (define_insn "*ncopysignsf3"
2762 [(set (match_operand:SF 0 "register_operand" "=f")
2763 (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2764 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
2767 "fmerge.ns %0 = %F2, %F1"
2768 [(set_attr "itanium_class" "fmisc")])
2770 (define_insn "sminsf3"
2771 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2772 (smin:SF (match_operand:SF 1 "fr_register_operand" "f")
2773 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2776 [(set_attr "itanium_class" "fmisc")])
2778 (define_insn "smaxsf3"
2779 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2780 (smax:SF (match_operand:SF 1 "fr_register_operand" "f")
2781 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2784 [(set_attr "itanium_class" "fmisc")])
2786 (define_insn "*maddsf4"
2787 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2788 (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2789 (match_operand:SF 2 "fr_register_operand" "f"))
2790 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2792 "fma.s %0 = %1, %2, %F3"
2793 [(set_attr "itanium_class" "fmac")])
2795 (define_insn "*msubsf4"
2796 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2797 (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2798 (match_operand:SF 2 "fr_register_operand" "f"))
2799 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2801 "fms.s %0 = %1, %2, %F3"
2802 [(set_attr "itanium_class" "fmac")])
2804 (define_insn "*nmulsf3"
2805 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2806 (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2807 (match_operand:SF 2 "fr_register_operand" "f"))))]
2809 "fnmpy.s %0 = %1, %2"
2810 [(set_attr "itanium_class" "fmac")])
2812 (define_insn "*nmaddsf4"
2813 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2814 (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")
2815 (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2816 (match_operand:SF 2 "fr_register_operand" "f"))))]
2818 "fnma.s %0 = %1, %2, %F3"
2819 [(set_attr "itanium_class" "fmac")])
2821 (define_insn "*nmaddsf4_alts"
2822 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2823 (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")
2824 (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2825 (match_operand:SF 2 "fr_register_operand" "f"))))
2826 (use (match_operand:SI 4 "const_int_operand" ""))]
2828 "fnma.s.s%4 %0 = %1, %2, %F3"
2829 [(set_attr "itanium_class" "fmac")])
2831 (define_expand "divsf3"
2832 [(set (match_operand:SF 0 "fr_register_operand" "")
2833 (div:SF (match_operand:SF 1 "fr_register_operand" "")
2834 (match_operand:SF 2 "fr_register_operand" "")))]
2835 "TARGET_INLINE_FLOAT_DIV"
2838 if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT)
2839 insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
2841 insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
2846 (define_insn_and_split "divsf3_internal_lat"
2847 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2848 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2849 (match_operand:SF 2 "fr_register_operand" "f")))
2850 (clobber (match_scratch:XF 3 "=&f"))
2851 (clobber (match_scratch:XF 4 "=f"))
2852 (clobber (match_scratch:BI 5 "=c"))]
2853 "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT"
2855 "&& reload_completed"
2856 [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
2857 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
2858 UNSPEC_FR_RECIP_APPROX))
2859 (use (const_int 0))])
2860 (cond_exec (ne (match_dup 5) (const_int 0))
2861 (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6)))
2862 (use (const_int 1))]))
2863 (cond_exec (ne (match_dup 5) (const_int 0))
2864 (parallel [(set (match_dup 4)
2865 (minus:XF (match_dup 10)
2866 (mult:XF (match_dup 8) (match_dup 6))))
2867 (use (const_int 1))]))
2868 (cond_exec (ne (match_dup 5) (const_int 0))
2869 (parallel [(set (match_dup 3)
2870 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
2872 (use (const_int 1))]))
2873 (cond_exec (ne (match_dup 5) (const_int 0))
2874 (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4)))
2875 (use (const_int 1))]))
2876 (cond_exec (ne (match_dup 5) (const_int 0))
2877 (parallel [(set (match_dup 3)
2878 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
2880 (use (const_int 1))]))
2881 (cond_exec (ne (match_dup 5) (const_int 0))
2882 (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4)))
2883 (use (const_int 1))]))
2884 (cond_exec (ne (match_dup 5) (const_int 0))
2885 (parallel [(set (match_dup 9)
2887 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
2889 (use (const_int 1))]))
2890 (cond_exec (ne (match_dup 5) (const_int 0))
2892 (float_truncate:SF (match_dup 6))))
2895 operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
2896 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
2897 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
2898 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
2899 operands[10] = CONST1_RTX (XFmode);
2901 [(set_attr "predicable" "no")])
2903 (define_insn_and_split "divsf3_internal_thr"
2904 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2905 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2906 (match_operand:SF 2 "fr_register_operand" "f")))
2907 (clobber (match_scratch:XF 3 "=&f"))
2908 (clobber (match_scratch:XF 4 "=f"))
2909 (clobber (match_scratch:BI 5 "=c"))]
2910 "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
2912 "&& reload_completed"
2913 [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
2914 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
2915 UNSPEC_FR_RECIP_APPROX))
2916 (use (const_int 0))])
2917 (cond_exec (ne (match_dup 5) (const_int 0))
2918 (parallel [(set (match_dup 3)
2919 (minus:XF (match_dup 10)
2920 (mult:XF (match_dup 8) (match_dup 6))))
2921 (use (const_int 1))]))
2922 (cond_exec (ne (match_dup 5) (const_int 0))
2923 (parallel [(set (match_dup 3)
2924 (plus:XF (mult:XF (match_dup 3) (match_dup 3))
2926 (use (const_int 1))]))
2927 (cond_exec (ne (match_dup 5) (const_int 0))
2928 (parallel [(set (match_dup 6)
2929 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
2931 (use (const_int 1))]))
2932 (cond_exec (ne (match_dup 5) (const_int 0))
2933 (parallel [(set (match_dup 9)
2935 (mult:XF (match_dup 7) (match_dup 6))))
2936 (use (const_int 1))]))
2937 (cond_exec (ne (match_dup 5) (const_int 0))
2938 (parallel [(set (match_dup 4)
2939 (minus:XF (match_dup 7)
2940 (mult:XF (match_dup 8) (match_dup 3))))
2941 (use (const_int 1))]))
2942 (cond_exec (ne (match_dup 5) (const_int 0))
2945 (plus:XF (mult:XF (match_dup 4) (match_dup 6))
2949 operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
2950 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
2951 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
2952 operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
2953 operands[10] = CONST1_RTX (XFmode);
2955 [(set_attr "predicable" "no")])
2957 ;; Inline square root.
2959 (define_insn "*sqrt_approx"
2960 [(set (match_operand:XF 0 "fr_register_operand" "=f")
2961 (div:XF (const_int 1)
2962 (sqrt:XF (match_operand:XF 2 "fr_register_operand" "f"))))
2963 (set (match_operand:BI 1 "register_operand" "=c")
2964 (unspec:BI [(match_dup 2)] UNSPEC_FR_SQRT_RECIP_APPROX))
2965 (use (match_operand:SI 3 "const_int_operand" "")) ]
2967 "frsqrta.s%3 %0, %1 = %2"
2968 [(set_attr "itanium_class" "fmisc")
2969 (set_attr "predicable" "no")])
2971 (define_insn "setf_exp_xf"
2972 [(set (match_operand:XF 0 "fr_register_operand" "=f")
2973 (unspec:XF [(match_operand:DI 1 "register_operand" "r")]
2977 [(set_attr "itanium_class" "frfr")])
2979 (define_expand "sqrtsf2"
2980 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2981 (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2982 "TARGET_INLINE_SQRT"
2986 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
2987 insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]);
2990 gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT);
2992 insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]);
2997 ;; Latency-optimized square root.
2998 ;; FIXME: Implement.
3000 ;; Throughput-optimized square root.
3002 (define_insn_and_split "sqrtsf2_internal_thr"
3003 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
3004 (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))
3005 ;; Register r2 in optimization guide.
3006 (clobber (match_scratch:DI 2 "=r"))
3007 ;; Register f8 in optimization guide
3008 (clobber (match_scratch:XF 3 "=&f"))
3009 ;; Register f9 in optimization guide
3010 (clobber (match_scratch:XF 4 "=&f"))
3011 ;; Register f10 in optimization guide
3012 (clobber (match_scratch:XF 5 "=&f"))
3013 ;; Register p6 in optimization guide.
3014 (clobber (match_scratch:BI 6 "=c"))]
3015 "TARGET_INLINE_SQRT == INL_MAX_THR"
3017 "&& reload_completed"
3018 [ ;; exponent of +1/2 in r2
3019 (set (match_dup 2) (const_int 65534))
3022 (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP))
3024 ;; y0 = 1/sqrt(a) in f7
3025 (parallel [(set (match_dup 7)
3026 (div:XF (const_int 1)
3027 (sqrt:XF (match_dup 8))))
3029 (unspec:BI [(match_dup 8)]
3030 UNSPEC_FR_SQRT_RECIP_APPROX))
3031 (use (const_int 0))])
3033 ;; H0 = 1/2 * y0 in f9
3034 (cond_exec (ne (match_dup 6) (const_int 0))
3035 (parallel [(set (match_dup 4)
3036 (plus:XF (mult:XF (match_dup 3) (match_dup 7))
3038 (use (const_int 1))]))
3040 ;; S0 = a * y0 in f7
3041 (cond_exec (ne (match_dup 6) (const_int 0))
3042 (parallel [(set (match_dup 7)
3043 (plus:XF (mult:XF (match_dup 8) (match_dup 7))
3045 (use (const_int 1))]))
3047 ;; d = 1/2 - S0 * H0 in f10
3048 (cond_exec (ne (match_dup 6) (const_int 0))
3049 (parallel [(set (match_dup 5)
3050 (minus:XF (match_dup 3)
3051 (mult:XF (match_dup 7) (match_dup 4))))
3052 (use (const_int 1))]))
3054 ;; d' = d + 1/2 * d in f8
3055 (cond_exec (ne (match_dup 6) (const_int 0))
3056 (parallel [(set (match_dup 3)
3057 (plus:XF (mult:XF (match_dup 3) (match_dup 5))
3059 (use (const_int 1))]))
3061 ;; e = d + d * d' in f8
3062 (cond_exec (ne (match_dup 6) (const_int 0))
3063 (parallel [(set (match_dup 3)
3064 (plus:XF (mult:XF (match_dup 5) (match_dup 3))
3066 (use (const_int 1))]))
3068 ;; S1 = S0 + e * S0 in f7
3069 (cond_exec (ne (match_dup 6) (const_int 0))
3070 (parallel [(set (match_dup 0)
3072 (plus:XF (mult:XF (match_dup 3) (match_dup 7))
3074 (use (const_int 1))]))
3076 ;; H1 = H0 + e * H0 in f8
3077 (cond_exec (ne (match_dup 6) (const_int 0))
3078 (parallel [(set (match_dup 3)
3079 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
3081 (use (const_int 1))]))
3083 ;; d1 = a - S1 * S1 in f9
3084 (cond_exec (ne (match_dup 6) (const_int 0))
3085 (parallel [(set (match_dup 4)
3086 (minus:XF (match_dup 8)
3087 (mult:XF (match_dup 7) (match_dup 7))))
3088 (use (const_int 1))]))
3090 ;; S = S1 + d1 * H1 in f7
3091 (cond_exec (ne (match_dup 6) (const_int 0))
3092 (parallel [(set (match_dup 0)
3094 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3096 (use (const_int 0))]))]
3098 /* Generate 82-bit versions of the input and output operands. */
3099 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3100 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3101 /* Generate required floating-point constants. */
3102 operands[9] = CONST0_RTX (XFmode);
3104 [(set_attr "predicable" "no")])
3106 ;; ::::::::::::::::::::
3108 ;; :: 64 bit floating point arithmetic
3110 ;; ::::::::::::::::::::
3112 (define_insn "adddf3"
3113 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3114 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
3115 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3117 "fadd.d %0 = %1, %F2"
3118 [(set_attr "itanium_class" "fmac")])
3120 (define_insn "*adddf3_trunc"
3121 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3123 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
3124 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
3126 "fadd.s %0 = %1, %F2"
3127 [(set_attr "itanium_class" "fmac")])
3129 (define_insn "subdf3"
3130 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3131 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3132 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3134 "fsub.d %0 = %F1, %F2"
3135 [(set_attr "itanium_class" "fmac")])
3137 (define_insn "*subdf3_trunc"
3138 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3140 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3141 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
3143 "fsub.s %0 = %F1, %F2"
3144 [(set_attr "itanium_class" "fmac")])
3146 (define_insn "muldf3"
3147 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3148 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3149 (match_operand:DF 2 "fr_register_operand" "f")))]
3151 "fmpy.d %0 = %1, %2"
3152 [(set_attr "itanium_class" "fmac")])
3154 (define_insn "*muldf3_trunc"
3155 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3157 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3158 (match_operand:DF 2 "fr_register_operand" "f"))))]
3160 "fmpy.s %0 = %1, %2"
3161 [(set_attr "itanium_class" "fmac")])
3163 (define_insn "absdf2"
3164 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3165 (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3168 [(set_attr "itanium_class" "fmisc")])
3170 (define_insn "negdf2"
3171 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3172 (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3175 [(set_attr "itanium_class" "fmisc")])
3177 (define_insn "*nabsdf2"
3178 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3179 (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))]
3182 [(set_attr "itanium_class" "fmisc")])
3184 (define_insn "copysigndf3"
3185 [(set (match_operand:DF 0 "register_operand" "=f")
3186 (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3187 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
3190 "fmerge.s %0 = %F2, %F1"
3191 [(set_attr "itanium_class" "fmisc")])
3193 (define_insn "*ncopysigndf3"
3194 [(set (match_operand:DF 0 "register_operand" "=f")
3195 (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3196 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
3199 "fmerge.ns %0 = %F2, %F1"
3200 [(set_attr "itanium_class" "fmisc")])
3202 (define_insn "smindf3"
3203 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3204 (smin:DF (match_operand:DF 1 "fr_register_operand" "f")
3205 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3208 [(set_attr "itanium_class" "fmisc")])
3210 (define_insn "smaxdf3"
3211 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3212 (smax:DF (match_operand:DF 1 "fr_register_operand" "f")
3213 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3216 [(set_attr "itanium_class" "fmisc")])
3218 (define_insn "*madddf4"
3219 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3220 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3221 (match_operand:DF 2 "fr_register_operand" "f"))
3222 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3224 "fma.d %0 = %1, %2, %F3"
3225 [(set_attr "itanium_class" "fmac")])
3227 (define_insn "*madddf4_trunc"
3228 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3230 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3231 (match_operand:DF 2 "fr_register_operand" "f"))
3232 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3234 "fma.s %0 = %1, %2, %F3"
3235 [(set_attr "itanium_class" "fmac")])
3237 (define_insn "*msubdf4"
3238 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3239 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3240 (match_operand:DF 2 "fr_register_operand" "f"))
3241 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3243 "fms.d %0 = %1, %2, %F3"
3244 [(set_attr "itanium_class" "fmac")])
3246 (define_insn "*msubdf4_trunc"
3247 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3249 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3250 (match_operand:DF 2 "fr_register_operand" "f"))
3251 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3253 "fms.s %0 = %1, %2, %F3"
3254 [(set_attr "itanium_class" "fmac")])
3256 (define_insn "*nmuldf3"
3257 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3258 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3259 (match_operand:DF 2 "fr_register_operand" "f"))))]
3261 "fnmpy.d %0 = %1, %2"
3262 [(set_attr "itanium_class" "fmac")])
3264 (define_insn "*nmuldf3_trunc"
3265 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3267 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3268 (match_operand:DF 2 "fr_register_operand" "f")))))]
3270 "fnmpy.s %0 = %1, %2"
3271 [(set_attr "itanium_class" "fmac")])
3273 (define_insn "*nmadddf4"
3274 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3275 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3276 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3277 (match_operand:DF 2 "fr_register_operand" "f"))))]
3279 "fnma.d %0 = %1, %2, %F3"
3280 [(set_attr "itanium_class" "fmac")])
3282 (define_insn "*nmadddf4_alts"
3283 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3284 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3285 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3286 (match_operand:DF 2 "fr_register_operand" "f"))))
3287 (use (match_operand:SI 4 "const_int_operand" ""))]
3289 "fnma.d.s%4 %0 = %1, %2, %F3"
3290 [(set_attr "itanium_class" "fmac")])
3292 (define_insn "*nmadddf4_truncsf"
3293 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3295 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3296 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3297 (match_operand:DF 2 "fr_register_operand" "f")))))]
3299 "fnma.s %0 = %1, %2, %F3"
3300 [(set_attr "itanium_class" "fmac")])
3302 (define_insn "*nmadddf4_truncsf_alts"
3303 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3305 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3306 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3307 (match_operand:DF 2 "fr_register_operand" "f")))))
3308 (use (match_operand:SI 4 "const_int_operand" ""))]
3310 "fnma.s.s%4 %0 = %1, %2, %F3"
3311 [(set_attr "itanium_class" "fmac")])
3313 (define_expand "divdf3"
3314 [(set (match_operand:DF 0 "fr_register_operand" "")
3315 (div:DF (match_operand:DF 1 "fr_register_operand" "")
3316 (match_operand:DF 2 "fr_register_operand" "")))]
3317 "TARGET_INLINE_FLOAT_DIV"
3320 if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT)
3321 insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
3323 insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
3328 (define_insn_and_split "divdf3_internal_lat"
3329 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3330 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3331 (match_operand:DF 2 "fr_register_operand" "f")))
3332 (clobber (match_scratch:XF 3 "=&f"))
3333 (clobber (match_scratch:XF 4 "=&f"))
3334 (clobber (match_scratch:XF 5 "=&f"))
3335 (clobber (match_scratch:BI 6 "=c"))]
3336 "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT"
3338 "&& reload_completed"
3339 [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9)))
3340 (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
3341 UNSPEC_FR_RECIP_APPROX))
3342 (use (const_int 0))])
3343 (cond_exec (ne (match_dup 6) (const_int 0))
3344 (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7)))
3345 (use (const_int 1))]))
3346 (cond_exec (ne (match_dup 6) (const_int 0))
3347 (parallel [(set (match_dup 4)
3348 (minus:XF (match_dup 12)
3349 (mult:XF (match_dup 9) (match_dup 7))))
3350 (use (const_int 1))]))
3351 (cond_exec (ne (match_dup 6) (const_int 0))
3352 (parallel [(set (match_dup 3)
3353 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3355 (use (const_int 1))]))
3356 (cond_exec (ne (match_dup 6) (const_int 0))
3357 (parallel [(set (match_dup 5) (mult:XF (match_dup 4) (match_dup 4)))
3358 (use (const_int 1))]))
3359 (cond_exec (ne (match_dup 6) (const_int 0))
3360 (parallel [(set (match_dup 7)
3361 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3363 (use (const_int 1))]))
3364 (cond_exec (ne (match_dup 6) (const_int 0))
3365 (parallel [(set (match_dup 3)
3366 (plus:XF (mult:XF (match_dup 5) (match_dup 3))
3368 (use (const_int 1))]))
3369 (cond_exec (ne (match_dup 6) (const_int 0))
3370 (parallel [(set (match_dup 4) (mult:XF (match_dup 5) (match_dup 5)))
3371 (use (const_int 1))]))
3372 (cond_exec (ne (match_dup 6) (const_int 0))
3373 (parallel [(set (match_dup 7)
3374 (plus:XF (mult:XF (match_dup 5) (match_dup 7))
3376 (use (const_int 1))]))
3377 (cond_exec (ne (match_dup 6) (const_int 0))
3378 (parallel [(set (match_dup 10)
3380 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3382 (use (const_int 1))]))
3383 (cond_exec (ne (match_dup 6) (const_int 0))
3384 (parallel [(set (match_dup 7)
3385 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3387 (use (const_int 1))]))
3388 (cond_exec (ne (match_dup 6) (const_int 0))
3389 (parallel [(set (match_dup 11)
3391 (minus:XF (match_dup 8)
3392 (mult:XF (match_dup 9) (match_dup 3)))))
3393 (use (const_int 1))]))
3394 (cond_exec (ne (match_dup 6) (const_int 0))
3396 (float_truncate:DF (plus:XF (mult:XF (match_dup 5) (match_dup 7))
3400 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3401 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3402 operands[9] = gen_rtx_REG (XFmode, REGNO (operands[2]));
3403 operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3404 operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
3405 operands[12] = CONST1_RTX (XFmode);
3407 [(set_attr "predicable" "no")])
3409 (define_insn_and_split "divdf3_internal_thr"
3410 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3411 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3412 (match_operand:DF 2 "fr_register_operand" "f")))
3413 (clobber (match_scratch:XF 3 "=&f"))
3414 (clobber (match_scratch:DF 4 "=f"))
3415 (clobber (match_scratch:BI 5 "=c"))]
3416 "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
3418 "&& reload_completed"
3419 [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
3420 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
3421 UNSPEC_FR_RECIP_APPROX))
3422 (use (const_int 0))])
3423 (cond_exec (ne (match_dup 5) (const_int 0))
3424 (parallel [(set (match_dup 3)
3425 (minus:XF (match_dup 10)
3426 (mult:XF (match_dup 8) (match_dup 6))))
3427 (use (const_int 1))]))
3428 (cond_exec (ne (match_dup 5) (const_int 0))
3429 (parallel [(set (match_dup 6)
3430 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
3432 (use (const_int 1))]))
3433 (cond_exec (ne (match_dup 5) (const_int 0))
3434 (parallel [(set (match_dup 3)
3435 (mult:XF (match_dup 3) (match_dup 3)))
3436 (use (const_int 1))]))
3437 (cond_exec (ne (match_dup 5) (const_int 0))
3438 (parallel [(set (match_dup 6)
3439 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
3441 (use (const_int 1))]))
3442 (cond_exec (ne (match_dup 5) (const_int 0))
3443 (parallel [(set (match_dup 3)
3444 (mult:XF (match_dup 3) (match_dup 3)))
3445 (use (const_int 1))]))
3446 (cond_exec (ne (match_dup 5) (const_int 0))
3447 (parallel [(set (match_dup 6)
3448 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
3450 (use (const_int 1))]))
3451 (cond_exec (ne (match_dup 5) (const_int 0))
3452 (parallel [(set (match_dup 9)
3454 (mult:XF (match_dup 7) (match_dup 6))))
3455 (use (const_int 1))]))
3456 (cond_exec (ne (match_dup 5) (const_int 0))
3457 (parallel [(set (match_dup 4)
3458 (minus:DF (match_dup 1)
3459 (mult:DF (match_dup 2) (match_dup 9))))
3460 (use (const_int 1))]))
3461 (cond_exec (ne (match_dup 5) (const_int 0))
3463 (plus:DF (mult:DF (match_dup 4) (match_dup 0))
3467 operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3468 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3469 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
3470 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3471 operands[10] = CONST1_RTX (XFmode);
3473 [(set_attr "predicable" "no")])
3475 ;; Inline square root.
3477 (define_expand "sqrtdf2"
3478 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3479 (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3480 "TARGET_INLINE_SQRT"
3484 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
3485 insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]);
3488 gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT);
3490 insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]);
3495 ;; Latency-optimized square root.
3496 ;; FIXME: Implement.
3498 ;; Throughput-optimized square root.
3500 (define_insn_and_split "sqrtdf2_internal_thr"
3501 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3502 (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))
3503 ;; Register r2 in optimization guide.
3504 (clobber (match_scratch:DI 2 "=r"))
3505 ;; Register f8 in optimization guide
3506 (clobber (match_scratch:XF 3 "=&f"))
3507 ;; Register f9 in optimization guide
3508 (clobber (match_scratch:XF 4 "=&f"))
3509 ;; Register f10 in optimization guide
3510 (clobber (match_scratch:XF 5 "=&f"))
3511 ;; Register p6 in optimization guide.
3512 (clobber (match_scratch:BI 6 "=c"))]
3513 "TARGET_INLINE_SQRT == INL_MAX_THR"
3515 "&& reload_completed"
3516 [ ;; exponent of +1/2 in r2
3517 (set (match_dup 2) (const_int 65534))
3520 (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP))
3522 ;; y0 = 1/sqrt(a) in f7
3523 (parallel [(set (match_dup 7)
3524 (div:XF (const_int 1)
3525 (sqrt:XF (match_dup 8))))
3527 (unspec:BI [(match_dup 8)]
3528 UNSPEC_FR_SQRT_RECIP_APPROX))
3529 (use (const_int 0))])
3531 ;; H0 = 1/2 * y0 in f8
3532 (cond_exec (ne (match_dup 6) (const_int 0))
3533 (parallel [(set (match_dup 3)
3534 (plus:XF (mult:XF (match_dup 5) (match_dup 7))
3536 (use (const_int 1))]))
3538 ;; G0 = a * y0 in f7
3539 (cond_exec (ne (match_dup 6) (const_int 0))
3540 (parallel [(set (match_dup 7)
3541 (plus:XF (mult:XF (match_dup 8) (match_dup 7))
3543 (use (const_int 1))]))
3545 ;; r0 = 1/2 - G0 * H0 in f9
3546 (cond_exec (ne (match_dup 6) (const_int 0))
3547 (parallel [(set (match_dup 4)
3548 (minus:XF (match_dup 5)
3549 (mult:XF (match_dup 7) (match_dup 3))))
3550 (use (const_int 1))]))
3552 ;; H1 = H0 + r0 * H0 in f8
3553 (cond_exec (ne (match_dup 6) (const_int 0))
3554 (parallel [(set (match_dup 3)
3555 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3557 (use (const_int 1))]))
3559 ;; G1 = G0 + r0 * G0 in f7
3560 (cond_exec (ne (match_dup 6) (const_int 0))
3561 (parallel [(set (match_dup 7)
3562 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3564 (use (const_int 1))]))
3566 ;; r1 = 1/2 - G1 * H1 in f9
3567 (cond_exec (ne (match_dup 6) (const_int 0))
3568 (parallel [(set (match_dup 4)
3569 (minus:XF (match_dup 5)
3570 (mult:XF (match_dup 7) (match_dup 3))))
3571 (use (const_int 1))]))
3573 ;; H2 = H1 + r1 * H1 in f8
3574 (cond_exec (ne (match_dup 6) (const_int 0))
3575 (parallel [(set (match_dup 3)
3576 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3578 (use (const_int 1))]))
3580 ;; G2 = G1 + r1 * G1 in f7
3581 (cond_exec (ne (match_dup 6) (const_int 0))
3582 (parallel [(set (match_dup 7)
3583 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3585 (use (const_int 1))]))
3587 ;; d2 = a - G2 * G2 in f9
3588 (cond_exec (ne (match_dup 6) (const_int 0))
3589 (parallel [(set (match_dup 4)
3590 (minus:XF (match_dup 8)
3591 (mult:XF (match_dup 7) (match_dup 7))))
3592 (use (const_int 1))]))
3594 ;; G3 = G2 + d2 * H2 in f7
3595 (cond_exec (ne (match_dup 6) (const_int 0))
3596 (parallel [(set (match_dup 7)
3597 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3599 (use (const_int 1))]))
3601 ;; d3 = a - G3 * G3 in f9
3602 (cond_exec (ne (match_dup 6) (const_int 0))
3603 (parallel [(set (match_dup 4)
3604 (minus:XF (match_dup 8)
3605 (mult:XF (match_dup 7) (match_dup 7))))
3606 (use (const_int 1))]))
3608 ;; S = G3 + d3 * H2 in f7
3609 (cond_exec (ne (match_dup 6) (const_int 0))
3610 (parallel [(set (match_dup 0)
3612 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3614 (use (const_int 0))]))]
3616 /* Generate 82-bit versions of the input and output operands. */
3617 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3618 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3619 /* Generate required floating-point constants. */
3620 operands[9] = CONST0_RTX (XFmode);
3622 [(set_attr "predicable" "no")])
3624 ;; ::::::::::::::::::::
3626 ;; :: 80 bit floating point arithmetic
3628 ;; ::::::::::::::::::::
3630 (define_insn "addxf3"
3631 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3632 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3633 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3635 "fadd %0 = %F1, %F2"
3636 [(set_attr "itanium_class" "fmac")])
3638 (define_insn "*addxf3_truncsf"
3639 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3641 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3642 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3644 "fadd.s %0 = %F1, %F2"
3645 [(set_attr "itanium_class" "fmac")])
3647 (define_insn "*addxf3_truncdf"
3648 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3650 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3651 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3653 "fadd.d %0 = %F1, %F2"
3654 [(set_attr "itanium_class" "fmac")])
3656 (define_insn "subxf3"
3657 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3658 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3659 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3661 "fsub %0 = %F1, %F2"
3662 [(set_attr "itanium_class" "fmac")])
3664 (define_insn "*subxf3_truncsf"
3665 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3667 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3668 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3670 "fsub.s %0 = %F1, %F2"
3671 [(set_attr "itanium_class" "fmac")])
3673 (define_insn "*subxf3_truncdf"
3674 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3676 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3677 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3679 "fsub.d %0 = %F1, %F2"
3680 [(set_attr "itanium_class" "fmac")])
3682 (define_insn "mulxf3"
3683 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3684 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3685 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3687 "fmpy %0 = %F1, %F2"
3688 [(set_attr "itanium_class" "fmac")])
3690 (define_insn "*mulxf3_truncsf"
3691 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3693 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3694 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3696 "fmpy.s %0 = %F1, %F2"
3697 [(set_attr "itanium_class" "fmac")])
3699 (define_insn "*mulxf3_truncdf"
3700 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3702 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3703 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3705 "fmpy.d %0 = %F1, %F2"
3706 [(set_attr "itanium_class" "fmac")])
3708 (define_insn "*mulxf3_alts"
3709 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3710 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3711 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))
3712 (use (match_operand:SI 3 "const_int_operand" ""))]
3714 "fmpy.s%3 %0 = %F1, %F2"
3715 [(set_attr "itanium_class" "fmac")])
3717 (define_insn "*mulxf3_truncsf_alts"
3718 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3720 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3721 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))
3722 (use (match_operand:SI 3 "const_int_operand" ""))]
3724 "fmpy.s.s%3 %0 = %F1, %F2"
3725 [(set_attr "itanium_class" "fmac")])
3727 (define_insn "*mulxf3_truncdf_alts"
3728 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3730 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3731 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))
3732 (use (match_operand:SI 3 "const_int_operand" ""))]
3734 "fmpy.d.s%3 %0 = %F1, %F2"
3735 [(set_attr "itanium_class" "fmac")])
3737 (define_insn "absxf2"
3738 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3739 (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3742 [(set_attr "itanium_class" "fmisc")])
3744 (define_insn "negxf2"
3745 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3746 (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3749 [(set_attr "itanium_class" "fmisc")])
3751 (define_insn "*nabsxf2"
3752 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3753 (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))]
3756 [(set_attr "itanium_class" "fmisc")])
3758 (define_insn "copysignxf3"
3759 [(set (match_operand:XF 0 "register_operand" "=f")
3760 (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3761 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
3764 "fmerge.s %0 = %F2, %F1"
3765 [(set_attr "itanium_class" "fmisc")])
3767 (define_insn "*ncopysignxf3"
3768 [(set (match_operand:XF 0 "register_operand" "=f")
3769 (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3770 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
3773 "fmerge.ns %0 = %F2, %F1"
3774 [(set_attr "itanium_class" "fmisc")])
3776 (define_insn "sminxf3"
3777 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3778 (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3779 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3781 "fmin %0 = %F1, %F2"
3782 [(set_attr "itanium_class" "fmisc")])
3784 (define_insn "smaxxf3"
3785 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3786 (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3787 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3789 "fmax %0 = %F1, %F2"
3790 [(set_attr "itanium_class" "fmisc")])
3792 (define_insn "*maddxf4"
3793 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3794 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3795 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3796 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
3798 "fma %0 = %F1, %F2, %F3"
3799 [(set_attr "itanium_class" "fmac")])
3801 (define_insn "*maddxf4_truncsf"
3802 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3804 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3805 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3806 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3808 "fma.s %0 = %F1, %F2, %F3"
3809 [(set_attr "itanium_class" "fmac")])
3811 (define_insn "*maddxf4_truncdf"
3812 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3814 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3815 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3816 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3818 "fma.d %0 = %F1, %F2, %F3"
3819 [(set_attr "itanium_class" "fmac")])
3821 (define_insn "*maddxf4_alts"
3822 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3823 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3824 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3825 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))
3826 (use (match_operand:SI 4 "const_int_operand" ""))]
3828 "fma.s%4 %0 = %F1, %F2, %F3"
3829 [(set_attr "itanium_class" "fmac")])
3831 (define_insn "*maddxf4_alts_truncsf"
3832 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3834 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3835 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3836 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))
3837 (use (match_operand:SI 4 "const_int_operand" ""))]
3839 "fma.s.s%4 %0 = %F1, %F2, %F3"
3840 [(set_attr "itanium_class" "fmac")])
3842 (define_insn "*maddxf4_alts_truncdf"
3843 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3845 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3846 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3847 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))
3848 (use (match_operand:SI 4 "const_int_operand" ""))]
3850 "fma.d.s%4 %0 = %F1, %F2, %F3"
3851 [(set_attr "itanium_class" "fmac")])
3853 (define_insn "*msubxf4"
3854 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3855 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3856 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3857 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
3859 "fms %0 = %F1, %F2, %F3"
3860 [(set_attr "itanium_class" "fmac")])
3862 (define_insn "*msubxf4_truncsf"
3863 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3865 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3866 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3867 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3869 "fms.s %0 = %F1, %F2, %F3"
3870 [(set_attr "itanium_class" "fmac")])
3872 (define_insn "*msubxf4_truncdf"
3873 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3875 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3876 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3877 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3879 "fms.d %0 = %F1, %F2, %F3"
3880 [(set_attr "itanium_class" "fmac")])
3882 (define_insn "*nmulxf3"
3883 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3884 (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3885 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3887 "fnmpy %0 = %F1, %F2"
3888 [(set_attr "itanium_class" "fmac")])
3890 (define_insn "*nmulxf3_truncsf"
3891 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3894 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3895 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
3897 "fnmpy.s %0 = %F1, %F2"
3898 [(set_attr "itanium_class" "fmac")])
3900 (define_insn "*nmulxf3_truncdf"
3901 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3904 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3905 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
3907 "fnmpy.d %0 = %F1, %F2"
3908 [(set_attr "itanium_class" "fmac")])
3910 (define_insn "*nmaddxf4"
3911 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3912 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
3913 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3914 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3917 "fnma %0 = %F1, %F2, %F3"
3918 [(set_attr "itanium_class" "fmac")])
3920 (define_insn "*nmaddxf4_truncsf"
3921 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3923 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
3924 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3925 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3928 "fnma.s %0 = %F1, %F2, %F3"
3929 [(set_attr "itanium_class" "fmac")])
3931 (define_insn "*nmaddxf4_truncdf"
3932 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3934 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
3935 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3936 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3939 "fnma.d %0 = %F1, %F2, %F3"
3940 [(set_attr "itanium_class" "fmac")])
3942 (define_insn "*nmaddxf4_alts"
3943 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3944 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
3945 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3946 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3948 (use (match_operand:SI 4 "const_int_operand" ""))]
3950 "fnma.s%4 %0 = %F1, %F2, %F3"
3951 [(set_attr "itanium_class" "fmac")])
3953 (define_insn "*nmaddxf4_truncsf_alts"
3954 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3956 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
3957 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3958 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3960 (use (match_operand:SI 4 "const_int_operand" ""))]
3962 "fnma.s.s%4 %0 = %F1, %F2, %F3"
3963 [(set_attr "itanium_class" "fmac")])
3965 (define_insn "*nmaddxf4_truncdf_alts"
3966 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3968 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
3969 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3970 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3972 (use (match_operand:SI 4 "const_int_operand" ""))]
3974 "fnma.d.s%4 %0 = %F1, %F2, %F3"
3975 [(set_attr "itanium_class" "fmac")])
3977 (define_expand "divxf3"
3978 [(set (match_operand:XF 0 "fr_register_operand" "")
3979 (div:XF (match_operand:XF 1 "fr_register_operand" "")
3980 (match_operand:XF 2 "fr_register_operand" "")))]
3981 "TARGET_INLINE_FLOAT_DIV"
3984 if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT)
3985 insn = gen_divxf3_internal_lat (operands[0], operands[1], operands[2]);
3987 insn = gen_divxf3_internal_thr (operands[0], operands[1], operands[2]);
3992 (define_insn_and_split "divxf3_internal_lat"
3993 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
3994 (div:XF (match_operand:XF 1 "fr_register_operand" "f")
3995 (match_operand:XF 2 "fr_register_operand" "f")))
3996 (clobber (match_scratch:XF 3 "=&f"))
3997 (clobber (match_scratch:XF 4 "=&f"))
3998 (clobber (match_scratch:XF 5 "=&f"))
3999 (clobber (match_scratch:XF 6 "=&f"))
4000 (clobber (match_scratch:BI 7 "=c"))]
4001 "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT"
4003 "&& reload_completed"
4004 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
4005 (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
4006 UNSPEC_FR_RECIP_APPROX))
4007 (use (const_int 0))])
4008 (cond_exec (ne (match_dup 7) (const_int 0))
4009 (parallel [(set (match_dup 3)
4010 (minus:XF (match_dup 8)
4011 (mult:XF (match_dup 2) (match_dup 0))))
4012 (use (const_int 1))]))
4013 (cond_exec (ne (match_dup 7) (const_int 0))
4014 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
4015 (use (const_int 1))]))
4016 (cond_exec (ne (match_dup 7) (const_int 0))
4017 (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3)))
4018 (use (const_int 1))]))
4019 (cond_exec (ne (match_dup 7) (const_int 0))
4020 (parallel [(set (match_dup 6)
4021 (plus:XF (mult:XF (match_dup 3) (match_dup 3))
4023 (use (const_int 1))]))
4024 (cond_exec (ne (match_dup 7) (const_int 0))
4025 (parallel [(set (match_dup 3)
4026 (plus:XF (mult:XF (match_dup 5) (match_dup 5))
4028 (use (const_int 1))]))
4029 (cond_exec (ne (match_dup 7) (const_int 0))
4030 (parallel [(set (match_dup 5)
4031 (plus:XF (mult:XF (match_dup 6) (match_dup 0))
4033 (use (const_int 1))]))
4034 (cond_exec (ne (match_dup 7) (const_int 0))
4035 (parallel [(set (match_dup 0)
4036 (plus:XF (mult:XF (match_dup 5) (match_dup 3))
4038 (use (const_int 1))]))
4039 (cond_exec (ne (match_dup 7) (const_int 0))
4040 (parallel [(set (match_dup 4)
4041 (minus:XF (match_dup 1)
4042 (mult:XF (match_dup 2) (match_dup 4))))
4043 (use (const_int 1))]))
4044 (cond_exec (ne (match_dup 7) (const_int 0))
4045 (parallel [(set (match_dup 3)
4046 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
4048 (use (const_int 1))]))
4049 (cond_exec (ne (match_dup 7) (const_int 0))
4050 (parallel [(set (match_dup 5)
4051 (minus:XF (match_dup 8)
4052 (mult:XF (match_dup 2) (match_dup 0))))
4053 (use (const_int 1))]))
4054 (cond_exec (ne (match_dup 7) (const_int 0))
4055 (parallel [(set (match_dup 0)
4056 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4058 (use (const_int 1))]))
4059 (cond_exec (ne (match_dup 7) (const_int 0))
4060 (parallel [(set (match_dup 4)
4061 (minus:XF (match_dup 1)
4062 (mult:XF (match_dup 2) (match_dup 3))))
4063 (use (const_int 1))]))
4064 (cond_exec (ne (match_dup 7) (const_int 0))
4066 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4069 "operands[8] = CONST1_RTX (XFmode);"
4070 [(set_attr "predicable" "no")])
4072 (define_insn_and_split "divxf3_internal_thr"
4073 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
4074 (div:XF (match_operand:XF 1 "fr_register_operand" "f")
4075 (match_operand:XF 2 "fr_register_operand" "f")))
4076 (clobber (match_scratch:XF 3 "=&f"))
4077 (clobber (match_scratch:XF 4 "=&f"))
4078 (clobber (match_scratch:BI 5 "=c"))]
4079 "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
4081 "&& reload_completed"
4082 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
4083 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
4084 UNSPEC_FR_RECIP_APPROX))
4085 (use (const_int 0))])
4086 (cond_exec (ne (match_dup 5) (const_int 0))
4087 (parallel [(set (match_dup 3)
4088 (minus:XF (match_dup 6)
4089 (mult:XF (match_dup 2) (match_dup 0))))
4090 (use (const_int 1))]))
4091 (cond_exec (ne (match_dup 5) (const_int 0))
4092 (parallel [(set (match_dup 4)
4093 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
4095 (use (const_int 1))]))
4096 (cond_exec (ne (match_dup 5) (const_int 0))
4097 (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3)))
4098 (use (const_int 1))]))
4099 (cond_exec (ne (match_dup 5) (const_int 0))
4100 (parallel [(set (match_dup 3)
4101 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
4103 (use (const_int 1))]))
4104 (cond_exec (ne (match_dup 5) (const_int 0))
4105 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
4106 (use (const_int 1))]))
4107 (cond_exec (ne (match_dup 5) (const_int 0))
4108 (parallel [(set (match_dup 0)
4109 (minus:XF (match_dup 6)
4110 (mult:XF (match_dup 2) (match_dup 3))))
4111 (use (const_int 1))]))
4112 (cond_exec (ne (match_dup 5) (const_int 0))
4113 (parallel [(set (match_dup 0)
4114 (plus:XF (mult:XF (match_dup 0) (match_dup 3))
4116 (use (const_int 1))]))
4117 (cond_exec (ne (match_dup 5) (const_int 0))
4118 (parallel [(set (match_dup 3)
4119 (minus:XF (match_dup 1)
4120 (mult:XF (match_dup 2) (match_dup 4))))
4121 (use (const_int 1))]))
4122 (cond_exec (ne (match_dup 5) (const_int 0))
4123 (parallel [(set (match_dup 3)
4124 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
4126 (use (const_int 1))]))
4127 (cond_exec (ne (match_dup 5) (const_int 0))
4128 (parallel [(set (match_dup 4)
4129 (minus:XF (match_dup 6)
4130 (mult:XF (match_dup 2) (match_dup 0))))
4131 (use (const_int 1))]))
4132 (cond_exec (ne (match_dup 5) (const_int 0))
4133 (parallel [(set (match_dup 0)
4134 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4136 (use (const_int 1))]))
4137 (cond_exec (ne (match_dup 5) (const_int 0))
4138 (parallel [(set (match_dup 4)
4139 (minus:XF (match_dup 1)
4140 (mult:XF (match_dup 2) (match_dup 3))))
4141 (use (const_int 1))]))
4142 (cond_exec (ne (match_dup 5) (const_int 0))
4144 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4147 "operands[6] = CONST1_RTX (XFmode);"
4148 [(set_attr "predicable" "no")])
4150 ;; Inline square root.
4152 (define_expand "sqrtxf2"
4153 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
4154 (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))]
4155 "TARGET_INLINE_SQRT"
4159 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
4160 insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]);
4163 gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT);
4165 insn = gen_sqrtxf2_internal_thr (operands[0], operands[1]);
4170 ;; Latency-optimized square root.
4171 ;; FIXME: Implement.
4173 ;; Throughput-optimized square root.
4175 (define_insn_and_split "sqrtxf2_internal_thr"
4176 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
4177 (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))
4178 ;; Register r2 in optimization guide.
4179 (clobber (match_scratch:DI 2 "=r"))
4180 ;; Register f8 in optimization guide
4181 (clobber (match_scratch:XF 3 "=&f"))
4182 ;; Register f9 in optimization guide
4183 (clobber (match_scratch:XF 4 "=&f"))
4184 ;; Register f10 in optimization guide
4185 (clobber (match_scratch:XF 5 "=&f"))
4186 ;; Register f11 in optimization guide
4187 (clobber (match_scratch:XF 6 "=&f"))
4188 ;; Register p6 in optimization guide.
4189 (clobber (match_scratch:BI 7 "=c"))]
4190 "TARGET_INLINE_SQRT == INL_MAX_THR"
4192 "&& reload_completed"
4193 [ ;; exponent of +1/2 in r2
4194 (set (match_dup 2) (const_int 65534))
4195 ;; +1/2 in f8. The Intel manual mistakenly specifies f10.
4197 (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP))
4199 ;; y0 = 1/sqrt(a) in f7
4200 (parallel [(set (match_dup 8)
4201 (div:XF (const_int 1)
4202 (sqrt:XF (match_dup 9))))
4204 (unspec:BI [(match_dup 9)]
4205 UNSPEC_FR_SQRT_RECIP_APPROX))
4206 (use (const_int 0))])
4208 ;; H0 = 1/2 * y0 in f9
4209 (cond_exec (ne (match_dup 7) (const_int 0))
4210 (parallel [(set (match_dup 4)
4211 (plus:XF (mult:XF (match_dup 3) (match_dup 8))
4213 (use (const_int 1))]))
4215 ;; S0 = a * y0 in f7
4216 (cond_exec (ne (match_dup 7) (const_int 0))
4217 (parallel [(set (match_dup 8)
4218 (plus:XF (mult:XF (match_dup 9) (match_dup 8))
4220 (use (const_int 1))]))
4222 ;; d0 = 1/2 - S0 * H0 in f10
4223 (cond_exec (ne (match_dup 7) (const_int 0))
4224 (parallel [(set (match_dup 5)
4225 (minus:XF (match_dup 3)
4226 (mult:XF (match_dup 8) (match_dup 4))))
4227 (use (const_int 1))]))
4229 ;; H1 = H0 + d0 * H0 in f9
4230 (cond_exec (ne (match_dup 7) (const_int 0))
4231 (parallel [(set (match_dup 4)
4232 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
4234 (use (const_int 1))]))
4236 ;; S1 = S0 + d0 * S0 in f7
4237 (cond_exec (ne (match_dup 7) (const_int 0))
4238 (parallel [(set (match_dup 8)
4239 (plus:XF (mult:XF (match_dup 5) (match_dup 8))
4241 (use (const_int 1))]))
4243 ;; d1 = 1/2 - S1 * H1 in f10
4244 (cond_exec (ne (match_dup 7) (const_int 0))
4245 (parallel [(set (match_dup 5)
4246 (minus:XF (match_dup 3)
4247 (mult:XF (match_dup 8) (match_dup 4))))
4248 (use (const_int 1))]))
4250 ;; H2 = H1 + d1 * H1 in f9
4251 (cond_exec (ne (match_dup 7) (const_int 0))
4252 (parallel [(set (match_dup 4)
4253 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
4255 (use (const_int 1))]))
4257 ;; S2 = S1 + d1 * S1 in f7
4258 (cond_exec (ne (match_dup 7) (const_int 0))
4259 (parallel [(set (match_dup 8)
4260 (plus:XF (mult:XF (match_dup 5) (match_dup 8))
4262 (use (const_int 1))]))
4264 ;; d2 = 1/2 - S2 * H2 in f10
4265 (cond_exec (ne (match_dup 7) (const_int 0))
4266 (parallel [(set (match_dup 5)
4267 (minus:XF (match_dup 3)
4268 (mult:XF (match_dup 8) (match_dup 4))))
4269 (use (const_int 1))]))
4271 ;; e2 = a - S2 * S2 in f8
4272 (cond_exec (ne (match_dup 7) (const_int 0))
4273 (parallel [(set (match_dup 3)
4274 (minus:XF (match_dup 9)
4275 (mult:XF (match_dup 8) (match_dup 8))))
4276 (use (const_int 1))]))
4278 ;; S3 = S2 + e2 * H2 in f7
4279 (cond_exec (ne (match_dup 7) (const_int 0))
4280 (parallel [(set (match_dup 8)
4281 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
4283 (use (const_int 1))]))
4285 ;; H3 = H2 + d2 * H2 in f9
4286 (cond_exec (ne (match_dup 7) (const_int 0))
4287 (parallel [(set (match_dup 4)
4288 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
4290 (use (const_int 1))]))
4292 ;; e3 = a - S3 * S3 in f8
4293 (cond_exec (ne (match_dup 7) (const_int 0))
4294 (parallel [(set (match_dup 3)
4295 (minus:XF (match_dup 9)
4296 (mult:XF (match_dup 8) (match_dup 8))))
4297 (use (const_int 1))]))
4299 ;; S = S3 + e3 * H3 in f7
4300 (cond_exec (ne (match_dup 7) (const_int 0))
4301 (parallel [(set (match_dup 0)
4302 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
4304 (use (const_int 0))]))]
4306 /* Generate 82-bit versions of the input and output operands. */
4307 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[0]));
4308 operands[9] = gen_rtx_REG (XFmode, REGNO (operands[1]));
4309 /* Generate required floating-point constants. */
4310 operands[10] = CONST0_RTX (XFmode);
4312 [(set_attr "predicable" "no")])
4314 ;; ??? frcpa works like cmp.foo.unc.
4316 (define_insn "*recip_approx"
4317 [(set (match_operand:XF 0 "fr_register_operand" "=f")
4318 (div:XF (const_int 1)
4319 (match_operand:XF 3 "fr_register_operand" "f")))
4320 (set (match_operand:BI 1 "register_operand" "=c")
4321 (unspec:BI [(match_operand:XF 2 "fr_register_operand" "f")
4322 (match_dup 3)] UNSPEC_FR_RECIP_APPROX))
4323 (use (match_operand:SI 4 "const_int_operand" ""))]
4325 "frcpa.s%4 %0, %1 = %2, %3"
4326 [(set_attr "itanium_class" "fmisc")
4327 (set_attr "predicable" "no")])
4329 ;; ::::::::::::::::::::
4331 ;; :: 32 bit Integer Shifts and Rotates
4333 ;; ::::::::::::::::::::
4335 (define_expand "ashlsi3"
4336 [(set (match_operand:SI 0 "gr_register_operand" "")
4337 (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
4338 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4341 if (GET_CODE (operands[2]) != CONST_INT)
4343 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
4344 we've got to get rid of stray bits outside the SImode register. */
4345 rtx subshift = gen_reg_rtx (DImode);
4346 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
4347 operands[2] = subshift;
4351 (define_insn "*ashlsi3_internal"
4352 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
4353 (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r")
4354 (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))]
4357 shladd %0 = %1, %2, r0
4358 dep.z %0 = %1, %2, %E2
4360 [(set_attr "itanium_class" "ialu,ishf,mmshf")])
4362 (define_expand "ashrsi3"
4363 [(set (match_operand:SI 0 "gr_register_operand" "")
4364 (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
4365 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4368 rtx subtarget = gen_reg_rtx (DImode);
4369 if (GET_CODE (operands[2]) == CONST_INT)
4370 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
4371 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
4374 rtx subshift = gen_reg_rtx (DImode);
4375 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
4376 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
4377 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
4379 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
4383 (define_expand "lshrsi3"
4384 [(set (match_operand:SI 0 "gr_register_operand" "")
4385 (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
4386 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4389 rtx subtarget = gen_reg_rtx (DImode);
4390 if (GET_CODE (operands[2]) == CONST_INT)
4391 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
4392 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
4395 rtx subshift = gen_reg_rtx (DImode);
4396 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
4397 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
4398 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
4400 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
4404 ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
4405 ;; here, instead of 64 like the patterns above. Keep the pattern together
4406 ;; until after combine; otherwise it won't get matched often.
4408 (define_expand "rotrsi3"
4409 [(set (match_operand:SI 0 "gr_register_operand" "")
4410 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
4411 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4414 if (GET_MODE (operands[2]) != VOIDmode)
4416 rtx tmp = gen_reg_rtx (DImode);
4417 emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
4422 (define_insn_and_split "*rotrsi3_internal"
4423 [(set (match_operand:SI 0 "gr_register_operand" "=&r")
4424 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r")
4425 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))]
4430 (ior:DI (zero_extend:DI (match_dup 1))
4431 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
4433 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
4434 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
4436 (define_expand "rotlsi3"
4437 [(set (match_operand:SI 0 "gr_register_operand" "")
4438 (rotate:SI (match_operand:SI 1 "gr_register_operand" "")
4439 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4442 if (! shift_32bit_count_operand (operands[2], SImode))
4444 rtx tmp = gen_reg_rtx (SImode);
4445 emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2]));
4446 emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
4451 (define_insn_and_split "*rotlsi3_internal"
4452 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4453 (rotate:SI (match_operand:SI 1 "gr_register_operand" "r")
4454 (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
4456 "mux2 %0 = %1, 0xe1"
4457 "reload_completed && INTVAL (operands[2]) != 16"
4459 (ior:DI (zero_extend:DI (match_dup 1))
4460 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
4462 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
4464 operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
4465 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
4467 [(set_attr "itanium_class" "mmshf")])
4469 ;; ::::::::::::::::::::
4471 ;; :: 64 bit Integer Shifts and Rotates
4473 ;; ::::::::::::::::::::
4475 (define_insn "ashldi3"
4476 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
4477 (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r")
4478 (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))]
4481 shladd %0 = %1, %2, r0
4484 [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
4486 ;; ??? Maybe combine this with the multiply and add instruction?
4488 (define_insn "*shladd"
4489 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4490 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
4491 (match_operand:DI 2 "shladd_operand" "n"))
4492 (match_operand:DI 3 "gr_register_operand" "r")))]
4494 "shladd %0 = %1, %S2, %3"
4495 [(set_attr "itanium_class" "ialu")])
4497 ;; This can be created by register elimination if operand3 of shladd is an
4498 ;; eliminable register or has reg_equiv_constant set.
4500 ;; We have to use nonmemory_operand for operand 4, to ensure that the
4501 ;; validate_changes call inside eliminate_regs will always succeed. If it
4502 ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
4505 (define_insn_and_split "*shladd_elim"
4506 [(set (match_operand:DI 0 "gr_register_operand" "=&r")
4507 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
4508 (match_operand:DI 2 "shladd_operand" "n"))
4509 (match_operand:DI 3 "nonmemory_operand" "r"))
4510 (match_operand:DI 4 "nonmemory_operand" "rI")))]
4511 "reload_in_progress"
4512 "* gcc_unreachable ();"
4514 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
4516 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
4518 [(set_attr "itanium_class" "unknown")])
4520 (define_insn "ashrdi3"
4521 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4522 (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
4523 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
4528 [(set_attr "itanium_class" "mmshf,mmshfi")])
4530 (define_insn "lshrdi3"
4531 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4532 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
4533 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
4538 [(set_attr "itanium_class" "mmshf,mmshfi")])
4540 ;; Using a predicate that accepts only constants doesn't work, because optabs
4541 ;; will load the operand into a register and call the pattern if the predicate
4542 ;; did not accept it on the first try. So we use nonmemory_operand and then
4543 ;; verify that we have an appropriate constant in the expander.
4545 (define_expand "rotrdi3"
4546 [(set (match_operand:DI 0 "gr_register_operand" "")
4547 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
4548 (match_operand:DI 2 "nonmemory_operand" "")))]
4551 if (! shift_count_operand (operands[2], DImode))
4555 (define_insn "*rotrdi3_internal"
4556 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4557 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r")
4558 (match_operand:DI 2 "shift_count_operand" "M")))]
4560 "shrp %0 = %1, %1, %2"
4561 [(set_attr "itanium_class" "ishf")])
4563 (define_expand "rotldi3"
4564 [(set (match_operand:DI 0 "gr_register_operand" "")
4565 (rotate:DI (match_operand:DI 1 "gr_register_operand" "")
4566 (match_operand:DI 2 "nonmemory_operand" "")))]
4569 if (! shift_count_operand (operands[2], DImode))
4573 (define_insn "*rotldi3_internal"
4574 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4575 (rotate:DI (match_operand:DI 1 "gr_register_operand" "r")
4576 (match_operand:DI 2 "shift_count_operand" "M")))]
4578 "shrp %0 = %1, %1, %e2"
4579 [(set_attr "itanium_class" "ishf")])
4581 ;; ::::::::::::::::::::
4583 ;; :: 128 bit Integer Shifts and Rotates
4585 ;; ::::::::::::::::::::
4587 (define_expand "ashlti3"
4588 [(set (match_operand:TI 0 "gr_register_operand" "")
4589 (ashift:TI (match_operand:TI 1 "gr_register_operand" "")
4590 (match_operand:DI 2 "nonmemory_operand" "")))]
4593 if (!dshift_count_operand (operands[2], DImode))
4597 (define_insn_and_split "*ashlti3_internal"
4598 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
4599 (ashift:TI (match_operand:TI 1 "gr_register_operand" "r")
4600 (match_operand:DI 2 "dshift_count_operand" "n")))]
4606 HOST_WIDE_INT shift = INTVAL (operands[2]);
4607 rtx rl = gen_lowpart (DImode, operands[0]);
4608 rtx rh = gen_highpart (DImode, operands[0]);
4609 rtx lo = gen_lowpart (DImode, operands[1]);
4610 rtx shiftlo = GEN_INT (shift & 63);
4614 emit_move_insn (rl, const0_rtx);
4616 emit_insn (gen_ashldi3 (rh, lo, shiftlo));
4618 emit_move_insn (rh, lo);
4622 rtx hi = gen_highpart (DImode, operands[1]);
4624 emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63)));
4625 emit_insn (gen_ashldi3 (rl, lo, shiftlo));
4630 (define_expand "ashrti3"
4631 [(set (match_operand:TI 0 "gr_register_operand" "")
4632 (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
4633 (match_operand:DI 2 "nonmemory_operand" "")))]
4636 if (!dshift_count_operand (operands[2], DImode))
4640 (define_insn_and_split "*ashrti3_internal"
4641 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
4642 (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
4643 (match_operand:DI 2 "dshift_count_operand" "n")))]
4649 HOST_WIDE_INT shift = INTVAL (operands[2]);
4650 rtx rl = gen_lowpart (DImode, operands[0]);
4651 rtx rh = gen_highpart (DImode, operands[0]);
4652 rtx hi = gen_highpart (DImode, operands[1]);
4653 rtx shiftlo = GEN_INT (shift & 63);
4658 emit_insn (gen_ashrdi3 (rl, hi, shiftlo));
4660 emit_move_insn (rl, hi);
4661 emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63)));
4665 rtx lo = gen_lowpart (DImode, operands[1]);
4667 emit_insn (gen_shrp (rl, hi, lo, shiftlo));
4668 emit_insn (gen_ashrdi3 (rh, hi, shiftlo));
4673 (define_expand "lshrti3"
4674 [(set (match_operand:TI 0 "gr_register_operand" "")
4675 (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
4676 (match_operand:DI 2 "nonmemory_operand" "")))]
4679 if (!dshift_count_operand (operands[2], DImode))
4683 (define_insn_and_split "*lshrti3_internal"
4684 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
4685 (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
4686 (match_operand:DI 2 "dshift_count_operand" "n")))]
4692 HOST_WIDE_INT shift = INTVAL (operands[2]);
4693 rtx rl = gen_lowpart (DImode, operands[0]);
4694 rtx rh = gen_highpart (DImode, operands[0]);
4695 rtx hi = gen_highpart (DImode, operands[1]);
4696 rtx shiftlo = GEN_INT (shift & 63);
4701 emit_insn (gen_lshrdi3 (rl, hi, shiftlo));
4703 emit_move_insn (rl, hi);
4704 emit_move_insn (rh, const0_rtx);
4708 rtx lo = gen_lowpart (DImode, operands[1]);
4710 emit_insn (gen_shrp (rl, hi, lo, shiftlo));
4711 emit_insn (gen_lshrdi3 (rh, hi, shiftlo));
4716 (define_expand "rotlti3"
4717 [(set (match_operand:TI 0 "gr_register_operand" "")
4718 (rotate:TI (match_operand:TI 1 "gr_register_operand" "")
4719 (match_operand:DI 2 "nonmemory_operand" "")))]
4722 if (! dshift_count_operand (operands[2], DImode))
4726 (define_insn_and_split "*rotlti3_internal"
4727 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
4728 (rotate:TI (match_operand:TI 1 "gr_register_operand" "r")
4729 (match_operand:DI 2 "dshift_count_operand" "n")))]
4735 HOST_WIDE_INT count = INTVAL (operands[2]);
4736 rtx rl = gen_lowpart (DImode, operands[0]);
4737 rtx rh = gen_highpart (DImode, operands[0]);
4738 rtx lo = gen_lowpart (DImode, operands[1]);
4739 rtx hi = gen_highpart (DImode, operands[1]);
4740 rtx countlo = GEN_INT (-count & 63);
4746 emit_insn (gen_shrp (rl, hi, lo, countlo));
4747 emit_insn (gen_shrp (rh, lo, hi, countlo));
4751 emit_move_insn (rl, hi);
4752 emit_move_insn (rh, lo);
4757 emit_insn (gen_shrp (rl, lo, hi, countlo));
4758 emit_insn (gen_shrp (rh, hi, lo, countlo));
4762 [(set_attr "itanium_class" "unknown")])
4765 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4766 (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")
4767 (match_operand:DI 2 "gr_register_operand" "r")
4768 (match_operand:DI 3 "shift_count_operand" "M")]
4771 "shrp %0 = %1, %2, %3"
4772 [(set_attr "itanium_class" "ishf")])
4774 ;; ::::::::::::::::::::
4776 ;; :: 32 bit Integer Logical operations
4778 ;; ::::::::::::::::::::
4780 ;; We don't seem to need any other 32-bit logical operations, because gcc
4781 ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
4782 ;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
4783 ;; This doesn't work for unary logical operations, because we don't call
4784 ;; apply_distributive_law for them.
4786 ;; ??? Likewise, this doesn't work for andnot, which isn't handled by
4787 ;; apply_distributive_law. We get inefficient code for
4788 ;; int sub4 (int i, int j) { return i & ~j; }
4789 ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
4790 ;; (zero_extend (and (not A) B)) in combine.
4791 ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
4792 ;; one_cmplsi2 pattern.
4794 (define_insn "one_cmplsi2"
4795 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4796 (not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
4799 [(set_attr "itanium_class" "ilog")])
4801 ;; ::::::::::::::::::::
4803 ;; :: 64 bit Integer Logical operations
4805 ;; ::::::::::::::::::::
4807 (define_insn "anddi3"
4808 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4809 (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4810 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4815 [(set_attr "itanium_class" "ilog,fmisc")])
4817 (define_insn "*andnot"
4818 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4819 (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f"))
4820 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4825 [(set_attr "itanium_class" "ilog,fmisc")])
4827 (define_insn "iordi3"
4828 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4829 (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4830 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4835 [(set_attr "itanium_class" "ilog,fmisc")])
4837 (define_insn "xordi3"
4838 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4839 (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4840 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4845 [(set_attr "itanium_class" "ilog,fmisc")])
4847 (define_insn "one_cmpldi2"
4848 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4849 (not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
4852 [(set_attr "itanium_class" "ilog")])
4854 ;; ::::::::::::::::::::
4858 ;; ::::::::::::::::::::
4860 (define_expand "cmpbi"
4862 (compare (match_operand:BI 0 "register_operand" "")
4863 (match_operand:BI 1 "const_int_operand" "")))]
4866 ia64_compare_op0 = operands[0];
4867 ia64_compare_op1 = operands[1];
4871 (define_expand "cmpsi"
4873 (compare (match_operand:SI 0 "gr_register_operand" "")
4874 (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
4877 ia64_compare_op0 = operands[0];
4878 ia64_compare_op1 = operands[1];
4882 (define_expand "cmpdi"
4884 (compare (match_operand:DI 0 "gr_register_operand" "")
4885 (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
4888 ia64_compare_op0 = operands[0];
4889 ia64_compare_op1 = operands[1];
4893 (define_expand "cmpsf"
4895 (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
4896 (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
4899 ia64_compare_op0 = operands[0];
4900 ia64_compare_op1 = operands[1];
4904 (define_expand "cmpdf"
4906 (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
4907 (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
4910 ia64_compare_op0 = operands[0];
4911 ia64_compare_op1 = operands[1];
4915 (define_expand "cmpxf"
4917 (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "")
4918 (match_operand:XF 1 "xfreg_or_fp01_operand" "")))]
4921 ia64_compare_op0 = operands[0];
4922 ia64_compare_op1 = operands[1];
4926 (define_expand "cmptf"
4928 (compare (match_operand:TF 0 "gr_register_operand" "")
4929 (match_operand:TF 1 "gr_register_operand" "")))]
4932 ia64_compare_op0 = operands[0];
4933 ia64_compare_op1 = operands[1];
4937 (define_insn "*cmpsi_normal"
4938 [(set (match_operand:BI 0 "register_operand" "=c")
4939 (match_operator:BI 1 "normal_comparison_operator"
4940 [(match_operand:SI 2 "gr_register_operand" "r")
4941 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
4943 "cmp4.%C1 %0, %I0 = %3, %2"
4944 [(set_attr "itanium_class" "icmp")])
4946 ;; We use %r3 because it is possible for us to match a 0, and two of the
4947 ;; unsigned comparisons don't accept immediate operands of zero.
4949 (define_insn "*cmpsi_adjusted"
4950 [(set (match_operand:BI 0 "register_operand" "=c")
4951 (match_operator:BI 1 "adjusted_comparison_operator"
4952 [(match_operand:SI 2 "gr_register_operand" "r")
4953 (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4955 "cmp4.%C1 %0, %I0 = %r3, %2"
4956 [(set_attr "itanium_class" "icmp")])
4958 (define_insn "*cmpdi_normal"
4959 [(set (match_operand:BI 0 "register_operand" "=c")
4960 (match_operator:BI 1 "normal_comparison_operator"
4961 [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
4962 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
4964 "cmp.%C1 %0, %I0 = %3, %r2"
4965 [(set_attr "itanium_class" "icmp")])
4967 ;; We use %r3 because it is possible for us to match a 0, and two of the
4968 ;; unsigned comparisons don't accept immediate operands of zero.
4970 (define_insn "*cmpdi_adjusted"
4971 [(set (match_operand:BI 0 "register_operand" "=c")
4972 (match_operator:BI 1 "adjusted_comparison_operator"
4973 [(match_operand:DI 2 "gr_register_operand" "r")
4974 (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4976 "cmp.%C1 %0, %I0 = %r3, %2"
4977 [(set_attr "itanium_class" "icmp")])
4979 (define_insn "*cmpsf_internal"
4980 [(set (match_operand:BI 0 "register_operand" "=c")
4981 (match_operator:BI 1 "comparison_operator"
4982 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
4983 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
4985 "fcmp.%D1 %0, %I0 = %F2, %F3"
4986 [(set_attr "itanium_class" "fcmp")])
4988 (define_insn "*cmpdf_internal"
4989 [(set (match_operand:BI 0 "register_operand" "=c")
4990 (match_operator:BI 1 "comparison_operator"
4991 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
4992 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
4994 "fcmp.%D1 %0, %I0 = %F2, %F3"
4995 [(set_attr "itanium_class" "fcmp")])
4997 (define_insn "*cmpxf_internal"
4998 [(set (match_operand:BI 0 "register_operand" "=c")
4999 (match_operator:BI 1 "comparison_operator"
5000 [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
5001 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))]
5003 "fcmp.%D1 %0, %I0 = %F2, %F3"
5004 [(set_attr "itanium_class" "fcmp")])
5006 ;; ??? Can this pattern be generated?
5008 (define_insn "*bit_zero"
5009 [(set (match_operand:BI 0 "register_operand" "=c")
5010 (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
5012 (match_operand:DI 2 "shift_count_operand" "M"))
5015 "tbit.z %0, %I0 = %1, %2"
5016 [(set_attr "itanium_class" "tbit")])
5018 (define_insn "*bit_one"
5019 [(set (match_operand:BI 0 "register_operand" "=c")
5020 (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
5022 (match_operand:DI 2 "shift_count_operand" "M"))
5025 "tbit.nz %0, %I0 = %1, %2"
5026 [(set_attr "itanium_class" "tbit")])
5028 ;; ::::::::::::::::::::
5032 ;; ::::::::::::::::::::
5034 (define_expand "beq"
5036 (if_then_else (match_dup 1)
5037 (label_ref (match_operand 0 "" ""))
5040 "operands[1] = ia64_expand_compare (EQ, VOIDmode);")
5042 (define_expand "bne"
5044 (if_then_else (match_dup 1)
5045 (label_ref (match_operand 0 "" ""))
5048 "operands[1] = ia64_expand_compare (NE, VOIDmode);")
5050 (define_expand "blt"
5052 (if_then_else (match_dup 1)
5053 (label_ref (match_operand 0 "" ""))
5056 "operands[1] = ia64_expand_compare (LT, VOIDmode);")
5058 (define_expand "ble"
5060 (if_then_else (match_dup 1)
5061 (label_ref (match_operand 0 "" ""))
5064 "operands[1] = ia64_expand_compare (LE, VOIDmode);")
5066 (define_expand "bgt"
5068 (if_then_else (match_dup 1)
5069 (label_ref (match_operand 0 "" ""))
5072 "operands[1] = ia64_expand_compare (GT, VOIDmode);")
5074 (define_expand "bge"
5076 (if_then_else (match_dup 1)
5077 (label_ref (match_operand 0 "" ""))
5080 "operands[1] = ia64_expand_compare (GE, VOIDmode);")
5082 (define_expand "bltu"
5084 (if_then_else (match_dup 1)
5085 (label_ref (match_operand 0 "" ""))
5088 "operands[1] = ia64_expand_compare (LTU, VOIDmode);")
5090 (define_expand "bleu"
5092 (if_then_else (match_dup 1)
5093 (label_ref (match_operand 0 "" ""))
5096 "operands[1] = ia64_expand_compare (LEU, VOIDmode);")
5098 (define_expand "bgtu"
5100 (if_then_else (match_dup 1)
5101 (label_ref (match_operand 0 "" ""))
5104 "operands[1] = ia64_expand_compare (GTU, VOIDmode);")
5106 (define_expand "bgeu"
5108 (if_then_else (match_dup 1)
5109 (label_ref (match_operand 0 "" ""))
5112 "operands[1] = ia64_expand_compare (GEU, VOIDmode);")
5114 (define_expand "bunordered"
5116 (if_then_else (match_dup 1)
5117 (label_ref (match_operand 0 "" ""))
5120 "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);")
5122 (define_expand "bordered"
5124 (if_then_else (match_dup 1)
5125 (label_ref (match_operand 0 "" ""))
5128 "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);")
5130 (define_insn "*br_true"
5132 (if_then_else (match_operator 0 "predicate_operator"
5133 [(match_operand:BI 1 "register_operand" "c")
5135 (label_ref (match_operand 2 "" ""))
5138 "(%J0) br.cond%+ %l2"
5139 [(set_attr "itanium_class" "br")
5140 (set_attr "predicable" "no")])
5142 (define_insn "*br_false"
5144 (if_then_else (match_operator 0 "predicate_operator"
5145 [(match_operand:BI 1 "register_operand" "c")
5148 (label_ref (match_operand 2 "" ""))))]
5150 "(%j0) br.cond%+ %l2"
5151 [(set_attr "itanium_class" "br")
5152 (set_attr "predicable" "no")])
5154 ;; ::::::::::::::::::::
5156 ;; :: Counted loop operations
5158 ;; ::::::::::::::::::::
5160 (define_expand "doloop_end"
5161 [(use (match_operand 0 "" "")) ; loop pseudo
5162 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5163 (use (match_operand 2 "" "")) ; max iterations
5164 (use (match_operand 3 "" "")) ; loop level
5165 (use (match_operand 4 "" ""))] ; label
5168 /* Only use cloop on innermost loops. */
5169 if (INTVAL (operands[3]) > 1)
5171 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
5176 (define_insn "doloop_end_internal"
5177 [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
5179 (label_ref (match_operand 1 "" ""))
5181 (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
5182 (plus:DI (match_dup 0) (const_int -1))
5185 "br.cloop.sptk.few %l1"
5186 [(set_attr "itanium_class" "br")
5187 (set_attr "predicable" "no")])
5189 ;; ::::::::::::::::::::
5191 ;; :: Set flag operations
5193 ;; ::::::::::::::::::::
5195 (define_expand "seq"
5196 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5198 "operands[1] = ia64_expand_compare (EQ, DImode);")
5200 (define_expand "sne"
5201 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5203 "operands[1] = ia64_expand_compare (NE, DImode);")
5205 (define_expand "slt"
5206 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5208 "operands[1] = ia64_expand_compare (LT, DImode);")
5210 (define_expand "sle"
5211 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5213 "operands[1] = ia64_expand_compare (LE, DImode);")
5215 (define_expand "sgt"
5216 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5218 "operands[1] = ia64_expand_compare (GT, DImode);")
5220 (define_expand "sge"
5221 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5223 "operands[1] = ia64_expand_compare (GE, DImode);")
5225 (define_expand "sltu"
5226 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5228 "operands[1] = ia64_expand_compare (LTU, DImode);")
5230 (define_expand "sleu"
5231 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5233 "operands[1] = ia64_expand_compare (LEU, DImode);")
5235 (define_expand "sgtu"
5236 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5238 "operands[1] = ia64_expand_compare (GTU, DImode);")
5240 (define_expand "sgeu"
5241 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5243 "operands[1] = ia64_expand_compare (GEU, DImode);")
5245 (define_expand "sunordered"
5246 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5248 "operands[1] = ia64_expand_compare (UNORDERED, DImode);")
5250 (define_expand "sordered"
5251 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5253 "operands[1] = ia64_expand_compare (ORDERED, DImode);")
5255 ;; Don't allow memory as destination here, because cmov/cmov/st is more
5256 ;; efficient than mov/mov/cst/cst.
5258 (define_insn_and_split "*sne_internal"
5259 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5260 (ne:DI (match_operand:BI 1 "register_operand" "c")
5265 [(cond_exec (ne (match_dup 1) (const_int 0))
5266 (set (match_dup 0) (const_int 1)))
5267 (cond_exec (eq (match_dup 1) (const_int 0))
5268 (set (match_dup 0) (const_int 0)))]
5270 [(set_attr "itanium_class" "unknown")])
5272 (define_insn_and_split "*seq_internal"
5273 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5274 (eq:DI (match_operand:BI 1 "register_operand" "c")
5279 [(cond_exec (ne (match_dup 1) (const_int 0))
5280 (set (match_dup 0) (const_int 0)))
5281 (cond_exec (eq (match_dup 1) (const_int 0))
5282 (set (match_dup 0) (const_int 1)))]
5284 [(set_attr "itanium_class" "unknown")])
5286 ;; ::::::::::::::::::::
5288 ;; :: Conditional move instructions.
5290 ;; ::::::::::::::::::::
5292 ;; ??? Add movXXcc patterns?
5295 ;; DImode if_then_else patterns.
5298 (define_insn "*cmovdi_internal"
5299 [(set (match_operand:DI 0 "destination_operand"
5300 "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
5302 (match_operator 4 "predicate_operator"
5303 [(match_operand:BI 1 "register_operand"
5304 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
5306 (match_operand:DI 2 "move_operand"
5307 "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
5308 (match_operand:DI 3 "move_operand"
5309 "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
5310 "ia64_move_ok (operands[0], operands[2])
5311 && ia64_move_ok (operands[0], operands[3])"
5312 { gcc_unreachable (); }
5313 [(set_attr "predicable" "no")])
5316 [(set (match_operand 0 "destination_operand" "")
5318 (match_operator 4 "predicate_operator"
5319 [(match_operand:BI 1 "register_operand" "")
5321 (match_operand 2 "move_operand" "")
5322 (match_operand 3 "move_operand" "")))]
5326 bool emitted_something = false;
5327 rtx dest = operands[0];
5328 rtx srct = operands[2];
5329 rtx srcf = operands[3];
5330 rtx cond = operands[4];
5332 if (! rtx_equal_p (dest, srct))
5334 ia64_emit_cond_move (dest, srct, cond);
5335 emitted_something = true;
5337 if (! rtx_equal_p (dest, srcf))
5339 cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE,
5340 VOIDmode, operands[1], const0_rtx);
5341 ia64_emit_cond_move (dest, srcf, cond);
5342 emitted_something = true;
5344 if (! emitted_something)
5345 emit_note (NOTE_INSN_DELETED);
5349 ;; Absolute value pattern.
5351 (define_insn "*absdi2_internal"
5352 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
5354 (match_operator 4 "predicate_operator"
5355 [(match_operand:BI 1 "register_operand" "c,c")
5357 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
5358 (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
5361 [(set_attr "itanium_class" "ialu,unknown")
5362 (set_attr "predicable" "no")])
5365 [(set (match_operand:DI 0 "register_operand" "")
5367 (match_operator 4 "predicate_operator"
5368 [(match_operand:BI 1 "register_operand" "c,c")
5370 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
5371 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
5372 "reload_completed && rtx_equal_p (operands[0], operands[3])"
5376 (neg:DI (match_dup 2))))]
5380 [(set (match_operand:DI 0 "register_operand" "")
5382 (match_operator 4 "predicate_operator"
5383 [(match_operand:BI 1 "register_operand" "c,c")
5385 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
5386 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
5390 (set (match_dup 0) (neg:DI (match_dup 2))))
5393 (set (match_dup 0) (match_dup 3)))]
5395 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
5396 VOIDmode, operands[1], const0_rtx);
5400 ;; SImode if_then_else patterns.
5403 (define_insn "*cmovsi_internal"
5404 [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f")
5406 (match_operator 4 "predicate_operator"
5407 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
5409 (match_operand:SI 2 "move_operand"
5410 "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
5411 (match_operand:SI 3 "move_operand"
5412 "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
5413 "ia64_move_ok (operands[0], operands[2])
5414 && ia64_move_ok (operands[0], operands[3])"
5415 { gcc_unreachable (); }
5416 [(set_attr "predicable" "no")])
5418 (define_insn "*abssi2_internal"
5419 [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
5421 (match_operator 4 "predicate_operator"
5422 [(match_operand:BI 1 "register_operand" "c,c")
5424 (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
5425 (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
5428 [(set_attr "itanium_class" "ialu,unknown")
5429 (set_attr "predicable" "no")])
5432 [(set (match_operand:SI 0 "register_operand" "")
5434 (match_operator 4 "predicate_operator"
5435 [(match_operand:BI 1 "register_operand" "c,c")
5437 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
5438 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
5439 "reload_completed && rtx_equal_p (operands[0], operands[3])"
5443 (neg:SI (match_dup 2))))]
5447 [(set (match_operand:SI 0 "register_operand" "")
5449 (match_operator 4 "predicate_operator"
5450 [(match_operand:BI 1 "register_operand" "c,c")
5452 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
5453 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
5457 (set (match_dup 0) (neg:SI (match_dup 2))))
5460 (set (match_dup 0) (match_dup 3)))]
5462 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
5463 VOIDmode, operands[1], const0_rtx);
5466 (define_insn_and_split "*cond_opsi2_internal"
5467 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5468 (match_operator:SI 5 "condop_operator"
5470 (match_operator 6 "predicate_operator"
5471 [(match_operand:BI 1 "register_operand" "c")
5473 (match_operand:SI 2 "gr_register_operand" "r")
5474 (match_operand:SI 3 "gr_register_operand" "r"))
5475 (match_operand:SI 4 "gr_register_operand" "r")]))]
5481 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)])))
5484 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
5486 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
5487 VOIDmode, operands[1], const0_rtx);
5489 [(set_attr "itanium_class" "ialu")
5490 (set_attr "predicable" "no")])
5493 (define_insn_and_split "*cond_opsi2_internal_b"
5494 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5495 (match_operator:SI 5 "condop_operator"
5496 [(match_operand:SI 4 "gr_register_operand" "r")
5498 (match_operator 6 "predicate_operator"
5499 [(match_operand:BI 1 "register_operand" "c")
5501 (match_operand:SI 2 "gr_register_operand" "r")
5502 (match_operand:SI 3 "gr_register_operand" "r"))]))]
5508 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)])))
5511 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
5513 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
5514 VOIDmode, operands[1], const0_rtx);
5516 [(set_attr "itanium_class" "ialu")
5517 (set_attr "predicable" "no")])
5520 ;; ::::::::::::::::::::
5522 ;; :: Call and branch instructions
5524 ;; ::::::::::::::::::::
5526 ;; Subroutine call instruction returning no value. Operand 0 is the function
5527 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
5528 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
5529 ;; registers used as operands.
5531 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
5532 ;; is supplied for the sake of some RISC machines which need to put this
5533 ;; information into the assembler code; they can put it in the RTL instead of
5536 (define_expand "call"
5537 [(use (match_operand:DI 0 "" ""))
5538 (use (match_operand 1 "" ""))
5539 (use (match_operand 2 "" ""))
5540 (use (match_operand 3 "" ""))]
5543 ia64_expand_call (NULL_RTX, operands[0], operands[2], false);
5547 (define_expand "sibcall"
5548 [(use (match_operand:DI 0 "" ""))
5549 (use (match_operand 1 "" ""))
5550 (use (match_operand 2 "" ""))
5551 (use (match_operand 3 "" ""))]
5554 ia64_expand_call (NULL_RTX, operands[0], operands[2], true);
5558 ;; Subroutine call instruction returning a value. Operand 0 is the hard
5559 ;; register in which the value is returned. There are three more operands,
5560 ;; the same as the three operands of the `call' instruction (but with numbers
5561 ;; increased by one).
5563 ;; Subroutines that return `BLKmode' objects use the `call' insn.
5565 (define_expand "call_value"
5566 [(use (match_operand 0 "" ""))
5567 (use (match_operand:DI 1 "" ""))
5568 (use (match_operand 2 "" ""))
5569 (use (match_operand 3 "" ""))
5570 (use (match_operand 4 "" ""))]
5573 ia64_expand_call (operands[0], operands[1], operands[3], false);
5577 (define_expand "sibcall_value"
5578 [(use (match_operand 0 "" ""))
5579 (use (match_operand:DI 1 "" ""))
5580 (use (match_operand 2 "" ""))
5581 (use (match_operand 3 "" ""))
5582 (use (match_operand 4 "" ""))]
5585 ia64_expand_call (operands[0], operands[1], operands[3], true);
5589 ;; Call subroutine returning any type.
5591 (define_expand "untyped_call"
5592 [(parallel [(call (match_operand 0 "" "")
5594 (match_operand 1 "" "")
5595 (match_operand 2 "" "")])]
5600 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
5602 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5604 rtx set = XVECEXP (operands[2], 0, i);
5605 emit_move_insn (SET_DEST (set), SET_SRC (set));
5608 /* The optimizer does not know that the call sets the function value
5609 registers we stored in the result block. We avoid problems by
5610 claiming that all hard registers are used and clobbered at this
5612 emit_insn (gen_blockage ());
5617 (define_insn "call_nogp"
5618 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
5620 (clobber (match_operand:DI 1 "register_operand" "=b,b"))]
5622 "br.call%+.many %1 = %0"
5623 [(set_attr "itanium_class" "br,scall")])
5625 (define_insn "call_value_nogp"
5626 [(set (match_operand 0 "" "=X,X")
5627 (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i"))
5629 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
5631 "br.call%+.many %2 = %1"
5632 [(set_attr "itanium_class" "br,scall")])
5634 (define_insn "sibcall_nogp"
5635 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
5639 [(set_attr "itanium_class" "br,scall")])
5641 (define_insn "call_gp"
5642 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
5644 (clobber (match_operand:DI 1 "register_operand" "=b,b"))
5645 (clobber (match_scratch:DI 2 "=&r,X"))
5646 (clobber (match_scratch:DI 3 "=b,X"))]
5649 [(set_attr "itanium_class" "br,scall")])
5651 ;; Irritatingly, we don't have access to INSN within the split body.
5652 ;; See commentary in ia64_split_call as to why these aren't peep2.
5654 [(call (mem (match_operand 0 "call_operand" ""))
5656 (clobber (match_operand:DI 1 "register_operand" ""))
5657 (clobber (match_scratch:DI 2 ""))
5658 (clobber (match_scratch:DI 3 ""))]
5659 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
5662 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
5663 operands[3], true, false);
5668 [(call (mem (match_operand 0 "call_operand" ""))
5670 (clobber (match_operand:DI 1 "register_operand" ""))
5671 (clobber (match_scratch:DI 2 ""))
5672 (clobber (match_scratch:DI 3 ""))]
5676 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
5677 operands[3], false, false);
5681 (define_insn "call_value_gp"
5682 [(set (match_operand 0 "" "=X,X")
5683 (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i"))
5685 (clobber (match_operand:DI 2 "register_operand" "=b,b"))
5686 (clobber (match_scratch:DI 3 "=&r,X"))
5687 (clobber (match_scratch:DI 4 "=b,X"))]
5690 [(set_attr "itanium_class" "br,scall")])
5693 [(set (match_operand 0 "" "")
5694 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
5696 (clobber (match_operand:DI 2 "register_operand" ""))
5697 (clobber (match_scratch:DI 3 ""))
5698 (clobber (match_scratch:DI 4 ""))]
5699 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
5702 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
5703 operands[4], true, false);
5708 [(set (match_operand 0 "" "")
5709 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
5711 (clobber (match_operand:DI 2 "register_operand" ""))
5712 (clobber (match_scratch:DI 3 ""))
5713 (clobber (match_scratch:DI 4 ""))]
5717 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
5718 operands[4], false, false);
5722 (define_insn_and_split "sibcall_gp"
5723 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
5725 (clobber (match_scratch:DI 1 "=&r,X"))
5726 (clobber (match_scratch:DI 2 "=b,X"))]
5732 ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1],
5733 operands[2], true, true);
5736 [(set_attr "itanium_class" "br")])
5738 (define_insn "return_internal"
5740 (use (match_operand:DI 0 "register_operand" "b"))]
5742 "br.ret.sptk.many %0"
5743 [(set_attr "itanium_class" "br")])
5745 (define_insn "return"
5747 "ia64_direct_return ()"
5748 "br.ret.sptk.many rp"
5749 [(set_attr "itanium_class" "br")])
5751 (define_insn "*return_true"
5753 (if_then_else (match_operator 0 "predicate_operator"
5754 [(match_operand:BI 1 "register_operand" "c")
5758 "ia64_direct_return ()"
5759 "(%J0) br.ret%+.many rp"
5760 [(set_attr "itanium_class" "br")
5761 (set_attr "predicable" "no")])
5763 (define_insn "*return_false"
5765 (if_then_else (match_operator 0 "predicate_operator"
5766 [(match_operand:BI 1 "register_operand" "c")
5770 "ia64_direct_return ()"
5771 "(%j0) br.ret%+.many rp"
5772 [(set_attr "itanium_class" "br")
5773 (set_attr "predicable" "no")])
5776 [(set (pc) (label_ref (match_operand 0 "" "")))]
5779 [(set_attr "itanium_class" "br")])
5781 (define_insn "indirect_jump"
5782 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
5785 [(set_attr "itanium_class" "br")])
5787 (define_expand "tablejump"
5788 [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" ""))
5789 (use (label_ref (match_operand 1 "" "")))])]
5792 rtx op0 = operands[0];
5795 /* ??? Bother -- do_tablejump is "helpful" and pulls the table
5796 element into a register without bothering to see whether that
5797 is necessary given the operand predicate. Check for MEM just
5798 in case someone fixes this. */
5799 if (GET_CODE (op0) == MEM)
5800 addr = XEXP (op0, 0);
5803 /* Otherwise, cheat and guess that the previous insn in the
5804 stream was the memory load. Grab the address from that.
5805 Note we have to momentarily pop out of the sequence started
5806 by the insn-emit wrapper in order to grab the last insn. */
5810 last = get_last_insn ();
5812 set = single_set (last);
5814 gcc_assert (rtx_equal_p (SET_DEST (set), op0)
5815 && GET_CODE (SET_SRC (set)) == MEM);
5816 addr = XEXP (SET_SRC (set), 0);
5817 gcc_assert (!rtx_equal_p (addr, op0));
5820 /* Jump table elements are stored pc-relative. That is, a displacement
5821 from the entry to the label. Thus to convert to an absolute address
5822 we add the address of the memory from which the value is loaded. */
5823 operands[0] = expand_simple_binop (DImode, PLUS, op0, addr,
5824 NULL_RTX, 1, OPTAB_DIRECT);
5827 (define_insn "*tablejump_internal"
5828 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
5829 (use (label_ref (match_operand 1 "" "")))]
5832 [(set_attr "itanium_class" "br")])
5835 ;; ::::::::::::::::::::
5837 ;; :: Prologue and Epilogue instructions
5839 ;; ::::::::::::::::::::
5841 (define_expand "prologue"
5845 ia64_expand_prologue ();
5849 (define_expand "epilogue"
5853 ia64_expand_epilogue (0);
5857 (define_expand "sibcall_epilogue"
5861 ia64_expand_epilogue (1);
5865 ;; This prevents the scheduler from moving the SP decrement past FP-relative
5866 ;; stack accesses. This is the same as adddi3 plus the extra set.
5868 (define_insn "prologue_allocate_stack"
5869 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
5870 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
5871 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))
5872 (set (match_operand:DI 3 "register_operand" "+r,r,r")
5879 [(set_attr "itanium_class" "ialu")])
5881 ;; This prevents the scheduler from moving the SP restore past FP-relative
5882 ;; stack accesses. This is similar to movdi plus the extra set.
5884 (define_insn "epilogue_deallocate_stack"
5885 [(set (match_operand:DI 0 "register_operand" "=r")
5886 (match_operand:DI 1 "register_operand" "+r"))
5887 (set (match_dup 1) (match_dup 1))]
5890 [(set_attr "itanium_class" "ialu")])
5892 ;; As USE insns aren't meaningful after reload, this is used instead
5893 ;; to prevent deleting instructions setting registers for EH handling
5894 (define_insn "prologue_use"
5895 [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
5896 UNSPEC_PROLOGUE_USE)]
5899 [(set_attr "itanium_class" "ignore")
5900 (set_attr "predicable" "no")
5901 (set_attr "empty" "yes")])
5903 ;; Allocate a new register frame.
5905 (define_insn "alloc"
5906 [(set (match_operand:DI 0 "register_operand" "=r")
5907 (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
5908 (use (match_operand:DI 1 "const_int_operand" "i"))
5909 (use (match_operand:DI 2 "const_int_operand" "i"))
5910 (use (match_operand:DI 3 "const_int_operand" "i"))
5911 (use (match_operand:DI 4 "const_int_operand" "i"))]
5913 "alloc %0 = ar.pfs, %1, %2, %3, %4"
5914 [(set_attr "itanium_class" "syst_m0")
5915 (set_attr "predicable" "no")
5916 (set_attr "first_insn" "yes")])
5919 (define_expand "gr_spill"
5920 [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
5921 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5922 (match_operand:DI 2 "const_int_operand" "")]
5924 (clobber (match_dup 3))])]
5926 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5928 (define_insn "gr_spill_internal"
5929 [(set (match_operand:DI 0 "destination_operand" "=m")
5930 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5931 (match_operand:DI 2 "const_int_operand" "")]
5933 (clobber (match_operand:DI 3 "register_operand" ""))]
5936 /* Note that we use a C output pattern here to avoid the predicate
5937 being automatically added before the .mem.offset directive. */
5938 return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
5940 [(set_attr "itanium_class" "st")])
5943 (define_expand "gr_restore"
5944 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
5945 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
5946 (match_operand:DI 2 "const_int_operand" "")]
5948 (use (match_dup 3))])]
5950 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5952 (define_insn "gr_restore_internal"
5953 [(set (match_operand:DI 0 "register_operand" "=r")
5954 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
5955 (match_operand:DI 2 "const_int_operand" "")]
5957 (use (match_operand:DI 3 "register_operand" ""))]
5959 { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
5960 [(set_attr "itanium_class" "ld")])
5962 (define_insn "fr_spill"
5963 [(set (match_operand:XF 0 "destination_operand" "=m")
5964 (unspec:XF [(match_operand:XF 1 "register_operand" "f")]
5967 "stf.spill %0 = %1%P0"
5968 [(set_attr "itanium_class" "stf")])
5970 (define_insn "fr_restore"
5971 [(set (match_operand:XF 0 "register_operand" "=f")
5972 (unspec:XF [(match_operand:XF 1 "memory_operand" "m")]
5973 UNSPEC_FR_RESTORE))]
5975 "ldf.fill %0 = %1%P1"
5976 [(set_attr "itanium_class" "fld")])
5978 ;; ??? The explicit stop is not ideal. It would be better if
5979 ;; rtx_needs_barrier took care of this, but this is something that can be
5980 ;; fixed later. This avoids an RSE DV.
5982 (define_insn "bsp_value"
5983 [(set (match_operand:DI 0 "register_operand" "=r")
5984 (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
5988 return \";;\;%,mov %0 = ar.bsp\";
5990 [(set_attr "itanium_class" "frar_i")])
5992 (define_insn "set_bsp"
5993 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
6011 [(set_attr "itanium_class" "unknown")
6012 (set_attr "predicable" "no")])
6014 ;; ??? The explicit stops are not ideal. It would be better if
6015 ;; rtx_needs_barrier took care of this, but this is something that can be
6016 ;; fixed later. This avoids an RSE DV.
6018 (define_insn "flushrs"
6019 [(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
6022 [(set_attr "itanium_class" "rse_m")
6023 (set_attr "predicable" "no")])
6025 ;; ::::::::::::::::::::
6027 ;; :: Miscellaneous instructions
6029 ;; ::::::::::::::::::::
6031 ;; ??? Emitting a NOP instruction isn't very useful. This should probably
6032 ;; be emitting ";;" to force a break in the instruction packing.
6034 ;; No operation, needed in case the user uses -g but not -O.
6039 [(set_attr "itanium_class" "nop")])
6041 (define_insn "nop_m"
6045 [(set_attr "itanium_class" "nop_m")])
6047 (define_insn "nop_i"
6051 [(set_attr "itanium_class" "nop_i")])
6053 (define_insn "nop_f"
6057 [(set_attr "itanium_class" "nop_f")])
6059 (define_insn "nop_b"
6063 [(set_attr "itanium_class" "nop_b")])
6065 (define_insn "nop_x"
6069 [(set_attr "itanium_class" "nop_x")
6070 (set_attr "empty" "yes")])
6072 ;; The following insn will be never generated. It is used only by
6073 ;; insn scheduler to change state before advancing cycle.
6074 (define_insn "pre_cycle"
6078 [(set_attr "itanium_class" "pre_cycle")])
6080 (define_insn "bundle_selector"
6081 [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
6083 { return get_bundle_name (INTVAL (operands[0])); }
6084 [(set_attr "itanium_class" "ignore")
6085 (set_attr "predicable" "no")])
6087 ;; Pseudo instruction that prevents the scheduler from moving code above this
6089 (define_insn "blockage"
6090 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6093 [(set_attr "itanium_class" "ignore")
6094 (set_attr "predicable" "no")])
6096 (define_insn "insn_group_barrier"
6097 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
6098 UNSPECV_INSN_GROUP_BARRIER)]
6101 [(set_attr "itanium_class" "stop_bit")
6102 (set_attr "predicable" "no")
6103 (set_attr "empty" "yes")])
6105 (define_expand "trap"
6106 [(trap_if (const_int 1) (const_int 0))]
6110 ;; ??? We don't have a match-any slot type. Setting the type to unknown
6111 ;; produces worse code that setting the slot type to A.
6113 (define_insn "*trap"
6114 [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))]
6117 [(set_attr "itanium_class" "chk_s")])
6119 (define_expand "conditional_trap"
6120 [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))]
6123 operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode);
6126 (define_insn "*conditional_trap"
6127 [(trap_if (match_operator 0 "predicate_operator"
6128 [(match_operand:BI 1 "register_operand" "c")
6130 (match_operand 2 "const_int_operand" ""))]
6133 [(set_attr "itanium_class" "chk_s")
6134 (set_attr "predicable" "no")])
6136 (define_insn "break_f"
6137 [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
6140 [(set_attr "itanium_class" "nop_f")])
6142 (define_insn "prefetch"
6143 [(prefetch (match_operand:DI 0 "address_operand" "p")
6144 (match_operand:DI 1 "const_int_operand" "n")
6145 (match_operand:DI 2 "const_int_operand" "n"))]
6148 static const char * const alt[2][4] = {
6150 "%,lfetch.nta [%0]",
6151 "%,lfetch.nt1 [%0]",
6152 "%,lfetch.nt2 [%0]",
6156 "%,lfetch.excl.nta [%0]",
6157 "%,lfetch.excl.nt1 [%0]",
6158 "%,lfetch.excl.nt2 [%0]",
6159 "%,lfetch.excl [%0]"
6162 int i = (INTVAL (operands[1]));
6163 int j = (INTVAL (operands[2]));
6165 gcc_assert (i == 0 || i == 1);
6166 gcc_assert (j >= 0 && j <= 3);
6169 [(set_attr "itanium_class" "lfetch")])
6171 ;; Non-local goto support.
6173 (define_expand "save_stack_nonlocal"
6174 [(use (match_operand:OI 0 "memory_operand" ""))
6175 (use (match_operand:DI 1 "register_operand" ""))]
6178 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
6179 \"__ia64_save_stack_nonlocal\"),
6180 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
6181 operands[1], Pmode);
6185 (define_expand "nonlocal_goto"
6186 [(use (match_operand 0 "general_operand" ""))
6187 (use (match_operand 1 "general_operand" ""))
6188 (use (match_operand 2 "general_operand" ""))
6189 (use (match_operand 3 "general_operand" ""))]
6192 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
6193 LCT_NORETURN, VOIDmode, 3,
6195 copy_to_reg (XEXP (operands[2], 0)), Pmode,
6196 operands[3], Pmode);
6201 (define_insn_and_split "builtin_setjmp_receiver"
6202 [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)]
6212 (define_expand "eh_epilogue"
6213 [(use (match_operand:DI 0 "register_operand" "r"))
6214 (use (match_operand:DI 1 "register_operand" "r"))
6215 (use (match_operand:DI 2 "register_operand" "r"))]
6218 rtx bsp = gen_rtx_REG (Pmode, 10);
6219 rtx sp = gen_rtx_REG (Pmode, 9);
6221 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
6223 emit_move_insn (bsp, operands[0]);
6226 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
6228 emit_move_insn (sp, operands[2]);
6231 emit_insn (gen_rtx_USE (VOIDmode, sp));
6232 emit_insn (gen_rtx_USE (VOIDmode, bsp));
6234 cfun->machine->ia64_eh_epilogue_sp = sp;
6235 cfun->machine->ia64_eh_epilogue_bsp = bsp;
6238 ;; Builtin apply support.
6240 (define_expand "restore_stack_nonlocal"
6241 [(use (match_operand:DI 0 "register_operand" ""))
6242 (use (match_operand:OI 1 "memory_operand" ""))]
6245 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
6246 "__ia64_restore_stack_nonlocal"),
6248 copy_to_reg (XEXP (operands[1], 0)), Pmode);
6256 [(match_operator 0 "predicate_operator"
6257 [(match_operand:BI 1 "register_operand" "c")
6262 (define_insn "pred_rel_mutex"
6263 [(set (match_operand:BI 0 "register_operand" "+c")
6264 (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
6266 ".pred.rel.mutex %0, %I0"
6267 [(set_attr "itanium_class" "ignore")
6268 (set_attr "predicable" "no")])
6270 (define_insn "safe_across_calls_all"
6271 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
6273 ".pred.safe_across_calls p1-p63"
6274 [(set_attr "itanium_class" "ignore")
6275 (set_attr "predicable" "no")])
6277 (define_insn "safe_across_calls_normal"
6278 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
6281 emit_safe_across_calls ();
6284 [(set_attr "itanium_class" "ignore")
6285 (set_attr "predicable" "no")])
6287 ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit
6288 ;; pointer. This is used by the HP-UX 32 bit mode.
6290 (define_insn "ptr_extend"
6291 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6292 (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
6296 [(set_attr "itanium_class" "ialu")])
6299 ;; Optimizations for ptr_extend
6301 (define_insn "ptr_extend_plus_imm"
6302 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6304 [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
6305 (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
6307 "addp4_optimize_ok (operands[1], operands[2])"
6309 [(set_attr "itanium_class" "ialu")])
6311 (define_insn "*ptr_extend_plus_2"
6312 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6314 [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
6315 (match_operand:SI 2 "basereg_operand" "r"))]
6317 "addp4_optimize_ok (operands[1], operands[2])"
6319 [(set_attr "itanium_class" "ialu")])
6322 ;; Get instruction pointer
6324 (define_insn "ip_value"
6325 [(set (match_operand:DI 0 "register_operand" "=r")
6329 [(set_attr "itanium_class" "ialu")])
6331 ;; Vector operations
6333 ;; Atomic operations