1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "rtl-error.h"
29 #include "insn-config.h"
30 #include "insn-attr.h"
31 #include "hard-reg-set.h"
34 #include "addresses.h"
38 #include "basic-block.h"
42 #include "tree-pass.h"
45 #ifndef STACK_PUSH_CODE
46 #ifdef STACK_GROWS_DOWNWARD
47 #define STACK_PUSH_CODE PRE_DEC
49 #define STACK_PUSH_CODE PRE_INC
53 #ifndef STACK_POP_CODE
54 #ifdef STACK_GROWS_DOWNWARD
55 #define STACK_POP_CODE POST_INC
57 #define STACK_POP_CODE POST_DEC
61 #ifndef HAVE_ATTR_enabled
63 get_attr_enabled (rtx insn ATTRIBUTE_UNUSED
)
69 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx
, bool);
70 static void validate_replace_src_1 (rtx
*, void *);
71 static rtx
split_insn (rtx
);
73 /* Nonzero means allow operands to be volatile.
74 This should be 0 if you are generating rtl, such as if you are calling
75 the functions in optabs.c and expmed.c (most of the time).
76 This should be 1 if all valid insns need to be recognized,
77 such as in reginfo.c and final.c and reload.c.
79 init_recog and init_recog_no_volatile are responsible for setting this. */
83 struct recog_data recog_data
;
85 /* Contains a vector of operand_alternative structures for every operand.
86 Set up by preprocess_constraints. */
87 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
89 /* On return from `constrain_operands', indicate which alternative
92 int which_alternative
;
94 /* Nonzero after end of reload pass.
95 Set to 1 or 0 by toplev.c.
96 Controls the significance of (SUBREG (MEM)). */
100 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
101 int epilogue_completed
;
103 /* Initialize data used by the function `recog'.
104 This must be called once in the compilation of a function
105 before any insn recognition may be done in the function. */
108 init_recog_no_volatile (void)
120 /* Return true if labels in asm operands BODY are LABEL_REFs. */
123 asm_labels_ok (rtx body
)
128 asmop
= extract_asm_operands (body
);
129 if (asmop
== NULL_RTX
)
132 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
133 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
139 /* Check that X is an insn-body for an `asm' with operands
140 and that the operands mentioned in it are legitimate. */
143 check_asm_operands (rtx x
)
147 const char **constraints
;
150 if (!asm_labels_ok (x
))
153 /* Post-reload, be more strict with things. */
154 if (reload_completed
)
156 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
157 extract_insn (make_insn_raw (x
));
158 constrain_operands (1);
159 return which_alternative
>= 0;
162 noperands
= asm_noperands (x
);
168 operands
= XALLOCAVEC (rtx
, noperands
);
169 constraints
= XALLOCAVEC (const char *, noperands
);
171 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
173 for (i
= 0; i
< noperands
; i
++)
175 const char *c
= constraints
[i
];
178 if (! asm_operand_ok (operands
[i
], c
, constraints
))
185 /* Static data for the next two routines. */
187 typedef struct change_t
196 static change_t
*changes
;
197 static int changes_allocated
;
199 static int num_changes
= 0;
201 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
202 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
203 the change is simply made.
205 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
206 will be called with the address and mode as parameters. If OBJECT is
207 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
210 IN_GROUP is nonzero if this is part of a group of changes that must be
211 performed as a group. In that case, the changes will be stored. The
212 function `apply_change_group' will validate and apply the changes.
214 If IN_GROUP is zero, this is a single change. Try to recognize the insn
215 or validate the memory reference with the change applied. If the result
216 is not valid for the machine, suppress the change and return zero.
217 Otherwise, perform the change and return 1. */
220 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
224 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
227 gcc_assert (in_group
!= 0 || num_changes
== 0);
231 /* Save the information describing this change. */
232 if (num_changes
>= changes_allocated
)
234 if (changes_allocated
== 0)
235 /* This value allows for repeated substitutions inside complex
236 indexed addresses, or changes in up to 5 insns. */
237 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
239 changes_allocated
*= 2;
241 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
244 changes
[num_changes
].object
= object
;
245 changes
[num_changes
].loc
= loc
;
246 changes
[num_changes
].old
= old
;
247 changes
[num_changes
].unshare
= unshare
;
249 if (object
&& !MEM_P (object
))
251 /* Set INSN_CODE to force rerecognition of insn. Save old code in
253 changes
[num_changes
].old_code
= INSN_CODE (object
);
254 INSN_CODE (object
) = -1;
259 /* If we are making a group of changes, return 1. Otherwise, validate the
260 change group we made. */
265 return apply_change_group ();
268 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
272 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
274 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
277 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
281 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
283 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
287 /* Keep X canonicalized if some changes have made it non-canonical; only
288 modifies the operands of X, not (for example) its code. Simplifications
289 are not the job of this routine.
291 Return true if anything was changed. */
293 canonicalize_change_group (rtx insn
, rtx x
)
295 if (COMMUTATIVE_P (x
)
296 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
298 /* Oops, the caller has made X no longer canonical.
299 Let's redo the changes in the correct order. */
300 rtx tem
= XEXP (x
, 0);
301 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
302 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
310 /* This subroutine of apply_change_group verifies whether the changes to INSN
311 were valid; i.e. whether INSN can still be recognized.
313 If IN_GROUP is true clobbers which have to be added in order to
314 match the instructions will be added to the current change group.
315 Otherwise the changes will take effect immediately. */
318 insn_invalid_p (rtx insn
, bool in_group
)
320 rtx pat
= PATTERN (insn
);
321 int num_clobbers
= 0;
322 /* If we are before reload and the pattern is a SET, see if we can add
324 int icode
= recog (pat
, insn
,
325 (GET_CODE (pat
) == SET
326 && ! reload_completed
&& ! reload_in_progress
)
327 ? &num_clobbers
: 0);
328 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
331 /* If this is an asm and the operand aren't legal, then fail. Likewise if
332 this is not an asm and the insn wasn't recognized. */
333 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
334 || (!is_asm
&& icode
< 0))
337 /* If we have to add CLOBBERs, fail if we have to add ones that reference
338 hard registers since our callers can't know if they are live or not.
339 Otherwise, add them. */
340 if (num_clobbers
> 0)
344 if (added_clobbers_hard_reg_p (icode
))
347 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
348 XVECEXP (newpat
, 0, 0) = pat
;
349 add_clobbers (newpat
, icode
);
351 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
353 PATTERN (insn
) = pat
= newpat
;
356 /* After reload, verify that all constraints are satisfied. */
357 if (reload_completed
)
361 if (! constrain_operands (1))
365 INSN_CODE (insn
) = icode
;
369 /* Return number of changes made and not validated yet. */
371 num_changes_pending (void)
376 /* Tentatively apply the changes numbered NUM and up.
377 Return 1 if all changes are valid, zero otherwise. */
380 verify_changes (int num
)
383 rtx last_validated
= NULL_RTX
;
385 /* The changes have been applied and all INSN_CODEs have been reset to force
388 The changes are valid if we aren't given an object, or if we are
389 given a MEM and it still is a valid address, or if this is in insn
390 and it is recognized. In the latter case, if reload has completed,
391 we also require that the operands meet the constraints for
394 for (i
= num
; i
< num_changes
; i
++)
396 rtx object
= changes
[i
].object
;
398 /* If there is no object to test or if it is the same as the one we
399 already tested, ignore it. */
400 if (object
== 0 || object
== last_validated
)
405 if (! memory_address_addr_space_p (GET_MODE (object
),
407 MEM_ADDR_SPACE (object
)))
410 else if (REG_P (changes
[i
].old
)
411 && asm_noperands (PATTERN (object
)) > 0
412 && REG_EXPR (changes
[i
].old
) != NULL_TREE
413 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
414 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
416 /* Don't allow changes of hard register operands to inline
417 assemblies if they have been defined as register asm ("x"). */
420 else if (DEBUG_INSN_P (object
))
422 else if (insn_invalid_p (object
, true))
424 rtx pat
= PATTERN (object
);
426 /* Perhaps we couldn't recognize the insn because there were
427 extra CLOBBERs at the end. If so, try to re-recognize
428 without the last CLOBBER (later iterations will cause each of
429 them to be eliminated, in turn). But don't do this if we
430 have an ASM_OPERAND. */
431 if (GET_CODE (pat
) == PARALLEL
432 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
433 && asm_noperands (PATTERN (object
)) < 0)
437 if (XVECLEN (pat
, 0) == 2)
438 newpat
= XVECEXP (pat
, 0, 0);
444 = gen_rtx_PARALLEL (VOIDmode
,
445 rtvec_alloc (XVECLEN (pat
, 0) - 1));
446 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
447 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
450 /* Add a new change to this group to replace the pattern
451 with this new pattern. Then consider this change
452 as having succeeded. The change we added will
453 cause the entire call to fail if things remain invalid.
455 Note that this can lose if a later change than the one
456 we are processing specified &XVECEXP (PATTERN (object), 0, X)
457 but this shouldn't occur. */
459 validate_change (object
, &PATTERN (object
), newpat
, 1);
462 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
463 || GET_CODE (pat
) == VAR_LOCATION
)
464 /* If this insn is a CLOBBER or USE, it is always valid, but is
470 last_validated
= object
;
473 return (i
== num_changes
);
476 /* A group of changes has previously been issued with validate_change
477 and verified with verify_changes. Call df_insn_rescan for each of
478 the insn changed and clear num_changes. */
481 confirm_change_group (void)
484 rtx last_object
= NULL
;
486 for (i
= 0; i
< num_changes
; i
++)
488 rtx object
= changes
[i
].object
;
490 if (changes
[i
].unshare
)
491 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
493 /* Avoid unnecessary rescanning when multiple changes to same instruction
497 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
498 df_insn_rescan (last_object
);
499 last_object
= object
;
503 if (last_object
&& INSN_P (last_object
))
504 df_insn_rescan (last_object
);
508 /* Apply a group of changes previously issued with `validate_change'.
509 If all changes are valid, call confirm_change_group and return 1,
510 otherwise, call cancel_changes and return 0. */
513 apply_change_group (void)
515 if (verify_changes (0))
517 confirm_change_group ();
528 /* Return the number of changes so far in the current group. */
531 num_validated_changes (void)
536 /* Retract the changes numbered NUM and up. */
539 cancel_changes (int num
)
543 /* Back out all the changes. Do this in the opposite order in which
545 for (i
= num_changes
- 1; i
>= num
; i
--)
547 *changes
[i
].loc
= changes
[i
].old
;
548 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
549 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
554 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
558 simplify_while_replacing (rtx
*loc
, rtx to
, rtx object
,
559 enum machine_mode op0_mode
)
562 enum rtx_code code
= GET_CODE (x
);
565 if (SWAPPABLE_OPERANDS_P (x
)
566 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
568 validate_unshare_change (object
, loc
,
569 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
570 : swap_condition (code
),
571 GET_MODE (x
), XEXP (x
, 1),
580 /* If we have a PLUS whose second operand is now a CONST_INT, use
581 simplify_gen_binary to try to simplify it.
582 ??? We may want later to remove this, once simplification is
583 separated from this function. */
584 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
585 validate_change (object
, loc
,
587 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
590 if (CONST_INT_P (XEXP (x
, 1))
591 || GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
)
592 validate_change (object
, loc
,
594 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
595 simplify_gen_unary (NEG
,
596 GET_MODE (x
), XEXP (x
, 1),
601 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
603 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
605 /* If any of the above failed, substitute in something that
606 we know won't be recognized. */
608 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
609 validate_change (object
, loc
, new_rtx
, 1);
613 /* All subregs possible to simplify should be simplified. */
614 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
617 /* Subregs of VOIDmode operands are incorrect. */
618 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
619 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
621 validate_change (object
, loc
, new_rtx
, 1);
625 /* If we are replacing a register with memory, try to change the memory
626 to be the mode required for memory in extract operations (this isn't
627 likely to be an insertion operation; if it was, nothing bad will
628 happen, we might just fail in some cases). */
630 if (MEM_P (XEXP (x
, 0))
631 && CONST_INT_P (XEXP (x
, 1))
632 && CONST_INT_P (XEXP (x
, 2))
633 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0))
634 && !MEM_VOLATILE_P (XEXP (x
, 0)))
636 enum machine_mode wanted_mode
= VOIDmode
;
637 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
638 int pos
= INTVAL (XEXP (x
, 2));
640 if (GET_CODE (x
) == ZERO_EXTRACT
)
642 enum machine_mode new_mode
643 = mode_for_extraction (EP_extzv
, 1);
644 if (new_mode
!= MAX_MACHINE_MODE
)
645 wanted_mode
= new_mode
;
647 else if (GET_CODE (x
) == SIGN_EXTRACT
)
649 enum machine_mode new_mode
650 = mode_for_extraction (EP_extv
, 1);
651 if (new_mode
!= MAX_MACHINE_MODE
)
652 wanted_mode
= new_mode
;
655 /* If we have a narrower mode, we can do something. */
656 if (wanted_mode
!= VOIDmode
657 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
659 int offset
= pos
/ BITS_PER_UNIT
;
662 /* If the bytes and bits are counted differently, we
663 must adjust the offset. */
664 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
666 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
669 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
670 == GET_MODE_BITSIZE (wanted_mode
));
671 pos
%= GET_MODE_BITSIZE (wanted_mode
);
673 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
675 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
676 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
687 /* Replace every occurrence of FROM in X with TO. Mark each change with
688 validate_change passing OBJECT. */
691 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx object
,
698 enum machine_mode op0_mode
= VOIDmode
;
699 int prev_changes
= num_changes
;
705 fmt
= GET_RTX_FORMAT (code
);
707 op0_mode
= GET_MODE (XEXP (x
, 0));
709 /* X matches FROM if it is the same rtx or they are both referring to the
710 same register in the same mode. Avoid calling rtx_equal_p unless the
711 operands look similar. */
714 || (REG_P (x
) && REG_P (from
)
715 && GET_MODE (x
) == GET_MODE (from
)
716 && REGNO (x
) == REGNO (from
))
717 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
718 && rtx_equal_p (x
, from
)))
720 validate_unshare_change (object
, loc
, to
, 1);
724 /* Call ourself recursively to perform the replacements.
725 We must not replace inside already replaced expression, otherwise we
726 get infinite recursion for replacements like (reg X)->(subreg (reg X))
727 done by regmove, so we must special case shared ASM_OPERANDS. */
729 if (GET_CODE (x
) == PARALLEL
)
731 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
733 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
734 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
736 /* Verify that operands are really shared. */
737 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
738 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
740 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
741 from
, to
, object
, simplify
);
744 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
749 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
752 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
753 else if (fmt
[i
] == 'E')
754 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
755 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
759 /* If we didn't substitute, there is nothing more to do. */
760 if (num_changes
== prev_changes
)
763 /* Allow substituted expression to have different mode. This is used by
764 regmove to change mode of pseudo register. */
765 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
766 op0_mode
= GET_MODE (XEXP (x
, 0));
768 /* Do changes needed to keep rtx consistent. Don't do any other
769 simplifications, as it is not our job. */
771 simplify_while_replacing (loc
, to
, object
, op0_mode
);
774 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
775 with TO. After all changes have been made, validate by seeing
776 if INSN is still valid. */
779 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx insn
, rtx
*loc
)
781 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
782 return apply_change_group ();
785 /* Try replacing every occurrence of FROM in INSN with TO. After all
786 changes have been made, validate by seeing if INSN is still valid. */
789 validate_replace_rtx (rtx from
, rtx to
, rtx insn
)
791 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
792 return apply_change_group ();
795 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
796 is a part of INSN. After all changes have been made, validate by seeing if
798 validate_replace_rtx (from, to, insn) is equivalent to
799 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
802 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx insn
)
804 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
805 return apply_change_group ();
808 /* Same as above, but do not simplify rtx afterwards. */
810 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
813 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
814 return apply_change_group ();
818 /* Try replacing every occurrence of FROM in INSN with TO. This also
819 will replace in REG_EQUAL and REG_EQUIV notes. */
822 validate_replace_rtx_group (rtx from
, rtx to
, rtx insn
)
825 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
826 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
827 if (REG_NOTE_KIND (note
) == REG_EQUAL
828 || REG_NOTE_KIND (note
) == REG_EQUIV
)
829 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
832 /* Function called by note_uses to replace used subexpressions. */
833 struct validate_replace_src_data
835 rtx from
; /* Old RTX */
836 rtx to
; /* New RTX */
837 rtx insn
; /* Insn in which substitution is occurring. */
841 validate_replace_src_1 (rtx
*x
, void *data
)
843 struct validate_replace_src_data
*d
844 = (struct validate_replace_src_data
*) data
;
846 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
849 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
853 validate_replace_src_group (rtx from
, rtx to
, rtx insn
)
855 struct validate_replace_src_data d
;
860 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
863 /* Try simplify INSN.
864 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
865 pattern and return true if something was simplified. */
868 validate_simplify_insn (rtx insn
)
874 pat
= PATTERN (insn
);
876 if (GET_CODE (pat
) == SET
)
878 newpat
= simplify_rtx (SET_SRC (pat
));
879 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
880 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
881 newpat
= simplify_rtx (SET_DEST (pat
));
882 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
883 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
885 else if (GET_CODE (pat
) == PARALLEL
)
886 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
888 rtx s
= XVECEXP (pat
, 0, i
);
890 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
892 newpat
= simplify_rtx (SET_SRC (s
));
893 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
894 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
895 newpat
= simplify_rtx (SET_DEST (s
));
896 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
897 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
900 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
904 /* Return 1 if the insn using CC0 set by INSN does not contain
905 any ordered tests applied to the condition codes.
906 EQ and NE tests do not count. */
909 next_insn_tests_no_inequality (rtx insn
)
911 rtx next
= next_cc0_user (insn
);
913 /* If there is no next insn, we have to take the conservative choice. */
917 return (INSN_P (next
)
918 && ! inequality_comparisons_p (PATTERN (next
)));
922 /* Return 1 if OP is a valid general operand for machine mode MODE.
923 This is either a register reference, a memory reference,
924 or a constant. In the case of a memory reference, the address
925 is checked for general validity for the target machine.
927 Register and memory references must have mode MODE in order to be valid,
928 but some constants have no machine mode and are valid for any mode.
930 If MODE is VOIDmode, OP is checked for validity for whatever mode
933 The main use of this function is as a predicate in match_operand
934 expressions in the machine description. */
937 general_operand (rtx op
, enum machine_mode mode
)
939 enum rtx_code code
= GET_CODE (op
);
941 if (mode
== VOIDmode
)
942 mode
= GET_MODE (op
);
944 /* Don't accept CONST_INT or anything similar
945 if the caller wants something floating. */
946 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
947 && GET_MODE_CLASS (mode
) != MODE_INT
948 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
953 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
957 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
959 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
960 && targetm
.legitimate_constant_p (mode
== VOIDmode
964 /* Except for certain constants with VOIDmode, already checked for,
965 OP's mode must match MODE if MODE specifies a mode. */
967 if (GET_MODE (op
) != mode
)
972 rtx sub
= SUBREG_REG (op
);
974 #ifdef INSN_SCHEDULING
975 /* On machines that have insn scheduling, we want all memory
976 reference to be explicit, so outlaw paradoxical SUBREGs.
977 However, we must allow them after reload so that they can
978 get cleaned up by cleanup_subreg_operands. */
979 if (!reload_completed
&& MEM_P (sub
)
980 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
983 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
984 may result in incorrect reference. We should simplify all valid
985 subregs of MEM anyway. But allow this after reload because we
986 might be called from cleanup_subreg_operands.
988 ??? This is a kludge. */
989 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
993 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
994 create such rtl, and we must reject it. */
995 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
996 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1000 code
= GET_CODE (op
);
1004 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1005 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1009 rtx y
= XEXP (op
, 0);
1011 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1014 /* Use the mem's mode, since it will be reloaded thus. */
1015 if (memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1022 /* Return 1 if OP is a valid memory address for a memory reference
1025 The main use of this function is as a predicate in match_operand
1026 expressions in the machine description. */
1029 address_operand (rtx op
, enum machine_mode mode
)
1031 return memory_address_p (mode
, op
);
1034 /* Return 1 if OP is a register reference of mode MODE.
1035 If MODE is VOIDmode, accept a register in any mode.
1037 The main use of this function is as a predicate in match_operand
1038 expressions in the machine description. */
1041 register_operand (rtx op
, enum machine_mode mode
)
1043 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1046 if (GET_CODE (op
) == SUBREG
)
1048 rtx sub
= SUBREG_REG (op
);
1050 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1051 because it is guaranteed to be reloaded into one.
1052 Just make sure the MEM is valid in itself.
1053 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1054 but currently it does result from (SUBREG (REG)...) where the
1055 reg went on the stack.) */
1056 if (! reload_completed
&& MEM_P (sub
))
1057 return general_operand (op
, mode
);
1059 #ifdef CANNOT_CHANGE_MODE_CLASS
1061 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1062 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1063 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1064 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
)
1068 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1069 create such rtl, and we must reject it. */
1070 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1071 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1078 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1079 || in_hard_reg_set_p (operand_reg_set
,
1080 GET_MODE (op
), REGNO (op
))));
1083 /* Return 1 for a register in Pmode; ignore the tested mode. */
1086 pmode_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1088 return register_operand (op
, Pmode
);
1091 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1092 or a hard register. */
1095 scratch_operand (rtx op
, enum machine_mode mode
)
1097 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1100 return (GET_CODE (op
) == SCRATCH
1102 && REGNO (op
) < FIRST_PSEUDO_REGISTER
));
1105 /* Return 1 if OP is a valid immediate operand for mode MODE.
1107 The main use of this function is as a predicate in match_operand
1108 expressions in the machine description. */
1111 immediate_operand (rtx op
, enum machine_mode mode
)
1113 /* Don't accept CONST_INT or anything similar
1114 if the caller wants something floating. */
1115 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1116 && GET_MODE_CLASS (mode
) != MODE_INT
1117 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1120 if (CONST_INT_P (op
)
1122 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1125 return (CONSTANT_P (op
)
1126 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1127 || GET_MODE (op
) == VOIDmode
)
1128 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1129 && targetm
.legitimate_constant_p (mode
== VOIDmode
1134 /* Returns 1 if OP is an operand that is a CONST_INT. */
1137 const_int_operand (rtx op
, enum machine_mode mode
)
1139 if (!CONST_INT_P (op
))
1142 if (mode
!= VOIDmode
1143 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1149 /* Returns 1 if OP is an operand that is a constant integer or constant
1150 floating-point number. */
1153 const_double_operand (rtx op
, enum machine_mode mode
)
1155 /* Don't accept CONST_INT or anything similar
1156 if the caller wants something floating. */
1157 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1158 && GET_MODE_CLASS (mode
) != MODE_INT
1159 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1162 return ((GET_CODE (op
) == CONST_DOUBLE
|| CONST_INT_P (op
))
1163 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1164 || GET_MODE (op
) == VOIDmode
));
1167 /* Return 1 if OP is a general operand that is not an immediate operand. */
1170 nonimmediate_operand (rtx op
, enum machine_mode mode
)
1172 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1175 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1178 nonmemory_operand (rtx op
, enum machine_mode mode
)
1180 if (CONSTANT_P (op
))
1181 return immediate_operand (op
, mode
);
1183 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1186 if (GET_CODE (op
) == SUBREG
)
1188 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1189 because it is guaranteed to be reloaded into one.
1190 Just make sure the MEM is valid in itself.
1191 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1192 but currently it does result from (SUBREG (REG)...) where the
1193 reg went on the stack.) */
1194 if (! reload_completed
&& MEM_P (SUBREG_REG (op
)))
1195 return general_operand (op
, mode
);
1196 op
= SUBREG_REG (op
);
1200 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1201 || in_hard_reg_set_p (operand_reg_set
,
1202 GET_MODE (op
), REGNO (op
))));
1205 /* Return 1 if OP is a valid operand that stands for pushing a
1206 value of mode MODE onto the stack.
1208 The main use of this function is as a predicate in match_operand
1209 expressions in the machine description. */
1212 push_operand (rtx op
, enum machine_mode mode
)
1214 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1216 #ifdef PUSH_ROUNDING
1217 rounded_size
= PUSH_ROUNDING (rounded_size
);
1223 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1228 if (rounded_size
== GET_MODE_SIZE (mode
))
1230 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1235 if (GET_CODE (op
) != PRE_MODIFY
1236 || GET_CODE (XEXP (op
, 1)) != PLUS
1237 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1238 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1239 #ifdef STACK_GROWS_DOWNWARD
1240 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1242 || INTVAL (XEXP (XEXP (op
, 1), 1)) != (int) rounded_size
1248 return XEXP (op
, 0) == stack_pointer_rtx
;
1251 /* Return 1 if OP is a valid operand that stands for popping a
1252 value of mode MODE off the stack.
1254 The main use of this function is as a predicate in match_operand
1255 expressions in the machine description. */
1258 pop_operand (rtx op
, enum machine_mode mode
)
1263 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1268 if (GET_CODE (op
) != STACK_POP_CODE
)
1271 return XEXP (op
, 0) == stack_pointer_rtx
;
1274 /* Return 1 if ADDR is a valid memory address
1275 for mode MODE in address space AS. */
1278 memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1279 rtx addr
, addr_space_t as
)
1281 #ifdef GO_IF_LEGITIMATE_ADDRESS
1282 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1283 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1289 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1293 /* Return 1 if OP is a valid memory reference with mode MODE,
1294 including a valid address.
1296 The main use of this function is as a predicate in match_operand
1297 expressions in the machine description. */
1300 memory_operand (rtx op
, enum machine_mode mode
)
1304 if (! reload_completed
)
1305 /* Note that no SUBREG is a memory operand before end of reload pass,
1306 because (SUBREG (MEM...)) forces reloading into a register. */
1307 return MEM_P (op
) && general_operand (op
, mode
);
1309 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1313 if (GET_CODE (inner
) == SUBREG
)
1314 inner
= SUBREG_REG (inner
);
1316 return (MEM_P (inner
) && general_operand (op
, mode
));
1319 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1320 that is, a memory reference whose address is a general_operand. */
1323 indirect_operand (rtx op
, enum machine_mode mode
)
1325 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1326 if (! reload_completed
1327 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1329 int offset
= SUBREG_BYTE (op
);
1330 rtx inner
= SUBREG_REG (op
);
1332 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1335 /* The only way that we can have a general_operand as the resulting
1336 address is if OFFSET is zero and the address already is an operand
1337 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1340 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1341 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1342 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1343 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1344 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1348 && memory_operand (op
, mode
)
1349 && general_operand (XEXP (op
, 0), Pmode
));
1352 /* Return 1 if this is an ordered comparison operator (not including
1353 ORDERED and UNORDERED). */
1356 ordered_comparison_operator (rtx op
, enum machine_mode mode
)
1358 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1360 switch (GET_CODE (op
))
1378 /* Return 1 if this is a comparison operator. This allows the use of
1379 MATCH_OPERATOR to recognize all the branch insns. */
1382 comparison_operator (rtx op
, enum machine_mode mode
)
1384 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1385 && COMPARISON_P (op
));
1388 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1391 extract_asm_operands (rtx body
)
1394 switch (GET_CODE (body
))
1400 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1401 tmp
= SET_SRC (body
);
1402 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1407 tmp
= XVECEXP (body
, 0, 0);
1408 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1410 if (GET_CODE (tmp
) == SET
)
1412 tmp
= SET_SRC (tmp
);
1413 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1424 /* If BODY is an insn body that uses ASM_OPERANDS,
1425 return the number of operands (both input and output) in the insn.
1426 Otherwise return -1. */
1429 asm_noperands (const_rtx body
)
1431 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1437 if (GET_CODE (body
) == SET
)
1439 else if (GET_CODE (body
) == PARALLEL
)
1442 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1444 /* Multiple output operands, or 1 output plus some clobbers:
1446 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1447 /* Count backwards through CLOBBERs to determine number of SETs. */
1448 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1450 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1452 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1456 /* N_SETS is now number of output operands. */
1459 /* Verify that all the SETs we have
1460 came from a single original asm_operands insn
1461 (so that invalid combinations are blocked). */
1462 for (i
= 0; i
< n_sets
; i
++)
1464 rtx elt
= XVECEXP (body
, 0, i
);
1465 if (GET_CODE (elt
) != SET
)
1467 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1469 /* If these ASM_OPERANDS rtx's came from different original insns
1470 then they aren't allowed together. */
1471 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1472 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1478 /* 0 outputs, but some clobbers:
1479 body is [(asm_operands ...) (clobber (reg ...))...]. */
1480 /* Make sure all the other parallel things really are clobbers. */
1481 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1482 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1487 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1488 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1491 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1492 copy its operands (both input and output) into the vector OPERANDS,
1493 the locations of the operands within the insn into the vector OPERAND_LOCS,
1494 and the constraints for the operands into CONSTRAINTS.
1495 Write the modes of the operands into MODES.
1496 Return the assembler-template.
1498 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1499 we don't store that info. */
1502 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1503 const char **constraints
, enum machine_mode
*modes
,
1506 int nbase
= 0, n
, i
;
1509 switch (GET_CODE (body
))
1512 /* Zero output asm: BODY is (asm_operands ...). */
1517 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1518 asmop
= SET_SRC (body
);
1520 /* The output is in the SET.
1521 Its constraint is in the ASM_OPERANDS itself. */
1523 operands
[0] = SET_DEST (body
);
1525 operand_locs
[0] = &SET_DEST (body
);
1527 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1529 modes
[0] = GET_MODE (SET_DEST (body
));
1535 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1537 asmop
= XVECEXP (body
, 0, 0);
1538 if (GET_CODE (asmop
) == SET
)
1540 asmop
= SET_SRC (asmop
);
1542 /* At least one output, plus some CLOBBERs. The outputs are in
1543 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1544 for (i
= 0; i
< nparallel
; i
++)
1546 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1547 break; /* Past last SET */
1549 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1551 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1553 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1555 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1566 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1567 for (i
= 0; i
< n
; i
++)
1570 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1572 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1574 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1576 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1580 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1581 for (i
= 0; i
< n
; i
++)
1584 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1586 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1588 constraints
[nbase
+ i
] = "";
1590 modes
[nbase
+ i
] = Pmode
;
1594 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1596 return ASM_OPERANDS_TEMPLATE (asmop
);
1599 /* Check if an asm_operand matches its constraints.
1600 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1603 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1607 bool incdec_ok
= false;
1610 /* Use constrain_operands after reload. */
1611 gcc_assert (!reload_completed
);
1613 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1614 many alternatives as required to match the other operands. */
1615 if (*constraint
== '\0')
1620 char c
= *constraint
;
1637 case '0': case '1': case '2': case '3': case '4':
1638 case '5': case '6': case '7': case '8': case '9':
1639 /* If caller provided constraints pointer, look up
1640 the maching constraint. Otherwise, our caller should have
1641 given us the proper matching constraint, but we can't
1642 actually fail the check if they didn't. Indicate that
1643 results are inconclusive. */
1647 unsigned long match
;
1649 match
= strtoul (constraint
, &end
, 10);
1651 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1652 constraint
= (const char *) end
;
1658 while (ISDIGIT (*constraint
));
1665 if (address_operand (op
, VOIDmode
))
1669 case TARGET_MEM_CONSTRAINT
:
1670 case 'V': /* non-offsettable */
1671 if (memory_operand (op
, VOIDmode
))
1675 case 'o': /* offsettable */
1676 if (offsettable_nonstrict_memref_p (op
))
1681 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed to exist,
1682 excepting those that expand_call created. Further, on some
1683 machines which do not have generalized auto inc/dec, an inc/dec
1684 is not a memory_operand.
1686 Match any memory and hope things are resolved after reload. */
1690 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1691 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1701 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1702 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1711 if (GET_CODE (op
) == CONST_DOUBLE
1712 || (GET_CODE (op
) == CONST_VECTOR
1713 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
1718 if (GET_CODE (op
) == CONST_DOUBLE
1719 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', constraint
))
1723 if (GET_CODE (op
) == CONST_DOUBLE
1724 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'H', constraint
))
1729 if (CONST_INT_P (op
)
1730 || (GET_CODE (op
) == CONST_DOUBLE
1731 && GET_MODE (op
) == VOIDmode
))
1736 if (CONSTANT_P (op
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1741 if (CONST_INT_P (op
)
1742 || (GET_CODE (op
) == CONST_DOUBLE
1743 && GET_MODE (op
) == VOIDmode
))
1748 if (CONST_INT_P (op
)
1749 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'I', constraint
))
1753 if (CONST_INT_P (op
)
1754 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'J', constraint
))
1758 if (CONST_INT_P (op
)
1759 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'K', constraint
))
1763 if (CONST_INT_P (op
)
1764 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'L', constraint
))
1768 if (CONST_INT_P (op
)
1769 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'M', constraint
))
1773 if (CONST_INT_P (op
)
1774 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'N', constraint
))
1778 if (CONST_INT_P (op
)
1779 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'O', constraint
))
1783 if (CONST_INT_P (op
)
1784 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'P', constraint
))
1793 if (general_operand (op
, VOIDmode
))
1798 /* For all other letters, we first check for a register class,
1799 otherwise it is an EXTRA_CONSTRAINT. */
1800 if (REG_CLASS_FROM_CONSTRAINT (c
, constraint
) != NO_REGS
)
1803 if (GET_MODE (op
) == BLKmode
)
1805 if (register_operand (op
, VOIDmode
))
1808 #ifdef EXTRA_CONSTRAINT_STR
1809 else if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
))
1810 /* Every memory operand can be reloaded to fit. */
1811 result
= result
|| memory_operand (op
, VOIDmode
);
1812 else if (EXTRA_ADDRESS_CONSTRAINT (c
, constraint
))
1813 /* Every address operand can be reloaded to fit. */
1814 result
= result
|| address_operand (op
, VOIDmode
);
1815 else if (EXTRA_CONSTRAINT_STR (op
, c
, constraint
))
1820 len
= CONSTRAINT_LEN (c
, constraint
);
1823 while (--len
&& *constraint
);
1829 /* For operands without < or > constraints reject side-effects. */
1830 if (!incdec_ok
&& result
&& MEM_P (op
))
1831 switch (GET_CODE (XEXP (op
, 0)))
1848 /* Given an rtx *P, if it is a sum containing an integer constant term,
1849 return the location (type rtx *) of the pointer to that constant term.
1850 Otherwise, return a null pointer. */
1853 find_constant_term_loc (rtx
*p
)
1856 enum rtx_code code
= GET_CODE (*p
);
1858 /* If *P IS such a constant term, P is its location. */
1860 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1864 /* Otherwise, if not a sum, it has no constant term. */
1866 if (GET_CODE (*p
) != PLUS
)
1869 /* If one of the summands is constant, return its location. */
1871 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1872 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1875 /* Otherwise, check each summand for containing a constant term. */
1877 if (XEXP (*p
, 0) != 0)
1879 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1884 if (XEXP (*p
, 1) != 0)
1886 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1894 /* Return 1 if OP is a memory reference
1895 whose address contains no side effects
1896 and remains valid after the addition
1897 of a positive integer less than the
1898 size of the object being referenced.
1900 We assume that the original address is valid and do not check it.
1902 This uses strict_memory_address_p as a subroutine, so
1903 don't use it before reload. */
1906 offsettable_memref_p (rtx op
)
1908 return ((MEM_P (op
))
1909 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1910 MEM_ADDR_SPACE (op
)));
1913 /* Similar, but don't require a strictly valid mem ref:
1914 consider pseudo-regs valid as index or base regs. */
1917 offsettable_nonstrict_memref_p (rtx op
)
1919 return ((MEM_P (op
))
1920 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1921 MEM_ADDR_SPACE (op
)));
1924 /* Return 1 if Y is a memory address which contains no side effects
1925 and would remain valid for address space AS after the addition of
1926 a positive integer less than the size of that mode.
1928 We assume that the original address is valid and do not check it.
1929 We do check that it is valid for narrower modes.
1931 If STRICTP is nonzero, we require a strictly valid address,
1932 for the sake of use in reload.c. */
1935 offsettable_address_addr_space_p (int strictp
, enum machine_mode mode
, rtx y
,
1938 enum rtx_code ycode
= GET_CODE (y
);
1942 int (*addressp
) (enum machine_mode
, rtx
, addr_space_t
) =
1943 (strictp
? strict_memory_address_addr_space_p
1944 : memory_address_addr_space_p
);
1945 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1947 if (CONSTANT_ADDRESS_P (y
))
1950 /* Adjusting an offsettable address involves changing to a narrower mode.
1951 Make sure that's OK. */
1953 if (mode_dependent_address_p (y
))
1956 /* ??? How much offset does an offsettable BLKmode reference need?
1957 Clearly that depends on the situation in which it's being used.
1958 However, the current situation in which we test 0xffffffff is
1959 less than ideal. Caveat user. */
1961 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1963 /* If the expression contains a constant term,
1964 see if it remains valid when max possible offset is added. */
1966 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1971 *y2
= plus_constant (GET_MODE (y
), *y2
, mode_sz
- 1);
1972 /* Use QImode because an odd displacement may be automatically invalid
1973 for any wider mode. But it should be valid for a single byte. */
1974 good
= (*addressp
) (QImode
, y
, as
);
1976 /* In any case, restore old contents of memory. */
1981 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
1984 /* The offset added here is chosen as the maximum offset that
1985 any instruction could need to add when operating on something
1986 of the specified mode. We assume that if Y and Y+c are
1987 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1988 go inside a LO_SUM here, so we do so as well. */
1989 if (GET_CODE (y
) == LO_SUM
1991 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
1992 z
= gen_rtx_LO_SUM (GET_MODE (y
), XEXP (y
, 0),
1993 plus_constant (GET_MODE (y
), XEXP (y
, 1),
1996 z
= plus_constant (GET_MODE (y
), y
, mode_sz
- 1);
1998 /* Use QImode because an odd displacement may be automatically invalid
1999 for any wider mode. But it should be valid for a single byte. */
2000 return (*addressp
) (QImode
, z
, as
);
2003 /* Return 1 if ADDR is an address-expression whose effect depends
2004 on the mode of the memory reference it is used in.
2006 Autoincrement addressing is a typical example of mode-dependence
2007 because the amount of the increment depends on the mode. */
2010 mode_dependent_address_p (rtx addr
)
2012 /* Auto-increment addressing with anything other than post_modify
2013 or pre_modify always introduces a mode dependency. Catch such
2014 cases now instead of deferring to the target. */
2015 if (GET_CODE (addr
) == PRE_INC
2016 || GET_CODE (addr
) == POST_INC
2017 || GET_CODE (addr
) == PRE_DEC
2018 || GET_CODE (addr
) == POST_DEC
)
2021 return targetm
.mode_dependent_address_p (addr
);
2024 /* Like extract_insn, but save insn extracted and don't extract again, when
2025 called again for the same insn expecting that recog_data still contain the
2026 valid information. This is used primary by gen_attr infrastructure that
2027 often does extract insn again and again. */
2029 extract_insn_cached (rtx insn
)
2031 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2033 extract_insn (insn
);
2034 recog_data
.insn
= insn
;
2037 /* Do cached extract_insn, constrain_operands and complain about failures.
2038 Used by insn_attrtab. */
2040 extract_constrain_insn_cached (rtx insn
)
2042 extract_insn_cached (insn
);
2043 if (which_alternative
== -1
2044 && !constrain_operands (reload_completed
))
2045 fatal_insn_not_found (insn
);
2048 /* Do cached constrain_operands and complain about failures. */
2050 constrain_operands_cached (int strict
)
2052 if (which_alternative
== -1)
2053 return constrain_operands (strict
);
2058 /* Analyze INSN and fill in recog_data. */
2061 extract_insn (rtx insn
)
2066 rtx body
= PATTERN (insn
);
2068 recog_data
.n_operands
= 0;
2069 recog_data
.n_alternatives
= 0;
2070 recog_data
.n_dups
= 0;
2071 recog_data
.is_asm
= false;
2073 switch (GET_CODE (body
))
2084 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2089 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2090 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2091 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2097 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2100 /* This insn is an `asm' with operands. */
2102 /* expand_asm_operands makes sure there aren't too many operands. */
2103 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2105 /* Now get the operand values and constraints out of the insn. */
2106 decode_asm_operands (body
, recog_data
.operand
,
2107 recog_data
.operand_loc
,
2108 recog_data
.constraints
,
2109 recog_data
.operand_mode
, NULL
);
2110 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2113 const char *p
= recog_data
.constraints
[0];
2114 recog_data
.n_alternatives
= 1;
2116 recog_data
.n_alternatives
+= (*p
++ == ',');
2118 recog_data
.is_asm
= true;
2121 fatal_insn_not_found (insn
);
2125 /* Ordinary insn: recognize it, get the operands via insn_extract
2126 and get the constraints. */
2128 icode
= recog_memoized (insn
);
2130 fatal_insn_not_found (insn
);
2132 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2133 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2134 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2136 insn_extract (insn
);
2138 for (i
= 0; i
< noperands
; i
++)
2140 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2141 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2142 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2143 /* VOIDmode match_operands gets mode from their real operand. */
2144 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2145 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2148 for (i
= 0; i
< noperands
; i
++)
2149 recog_data
.operand_type
[i
]
2150 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2151 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2154 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2156 if (INSN_CODE (insn
) < 0)
2157 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2158 recog_data
.alternative_enabled_p
[i
] = true;
2161 recog_data
.insn
= insn
;
2162 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2164 which_alternative
= i
;
2165 recog_data
.alternative_enabled_p
[i
] = get_attr_enabled (insn
);
2169 recog_data
.insn
= NULL
;
2170 which_alternative
= -1;
2173 /* After calling extract_insn, you can use this function to extract some
2174 information from the constraint strings into a more usable form.
2175 The collected data is stored in recog_op_alt. */
2177 preprocess_constraints (void)
2181 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2182 memset (recog_op_alt
[i
], 0, (recog_data
.n_alternatives
2183 * sizeof (struct operand_alternative
)));
2185 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2188 struct operand_alternative
*op_alt
;
2189 const char *p
= recog_data
.constraints
[i
];
2191 op_alt
= recog_op_alt
[i
];
2193 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2195 op_alt
[j
].cl
= NO_REGS
;
2196 op_alt
[j
].constraint
= p
;
2197 op_alt
[j
].matches
= -1;
2198 op_alt
[j
].matched
= -1;
2200 if (!recog_data
.alternative_enabled_p
[j
])
2202 p
= skip_alternative (p
);
2206 if (*p
== '\0' || *p
== ',')
2208 op_alt
[j
].anything_ok
= 1;
2218 while (c
!= ',' && c
!= '\0');
2219 if (c
== ',' || c
== '\0')
2227 case '=': case '+': case '*': case '%':
2228 case 'E': case 'F': case 'G': case 'H':
2229 case 's': case 'i': case 'n':
2230 case 'I': case 'J': case 'K': case 'L':
2231 case 'M': case 'N': case 'O': case 'P':
2232 /* These don't say anything we care about. */
2236 op_alt
[j
].reject
+= 6;
2239 op_alt
[j
].reject
+= 600;
2242 op_alt
[j
].earlyclobber
= 1;
2245 case '0': case '1': case '2': case '3': case '4':
2246 case '5': case '6': case '7': case '8': case '9':
2249 op_alt
[j
].matches
= strtoul (p
, &end
, 10);
2250 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2255 case TARGET_MEM_CONSTRAINT
:
2256 op_alt
[j
].memory_ok
= 1;
2259 op_alt
[j
].decmem_ok
= 1;
2262 op_alt
[j
].incmem_ok
= 1;
2265 op_alt
[j
].nonoffmem_ok
= 1;
2268 op_alt
[j
].offmem_ok
= 1;
2271 op_alt
[j
].anything_ok
= 1;
2275 op_alt
[j
].is_address
= 1;
2276 op_alt
[j
].cl
= reg_class_subunion
[(int) op_alt
[j
].cl
]
2277 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2284 reg_class_subunion
[(int) op_alt
[j
].cl
][(int) GENERAL_REGS
];
2288 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
2290 op_alt
[j
].memory_ok
= 1;
2293 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2295 op_alt
[j
].is_address
= 1;
2297 = (reg_class_subunion
2298 [(int) op_alt
[j
].cl
]
2299 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2300 ADDRESS
, SCRATCH
)]);
2305 = (reg_class_subunion
2306 [(int) op_alt
[j
].cl
]
2307 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
2310 p
+= CONSTRAINT_LEN (c
, p
);
2316 /* Check the operands of an insn against the insn's operand constraints
2317 and return 1 if they are valid.
2318 The information about the insn's operands, constraints, operand modes
2319 etc. is obtained from the global variables set up by extract_insn.
2321 WHICH_ALTERNATIVE is set to a number which indicates which
2322 alternative of constraints was matched: 0 for the first alternative,
2323 1 for the next, etc.
2325 In addition, when two operands are required to match
2326 and it happens that the output operand is (reg) while the
2327 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2328 make the output operand look like the input.
2329 This is because the output operand is the one the template will print.
2331 This is used in final, just before printing the assembler code and by
2332 the routines that determine an insn's attribute.
2334 If STRICT is a positive nonzero value, it means that we have been
2335 called after reload has been completed. In that case, we must
2336 do all checks strictly. If it is zero, it means that we have been called
2337 before reload has completed. In that case, we first try to see if we can
2338 find an alternative that matches strictly. If not, we try again, this
2339 time assuming that reload will fix up the insn. This provides a "best
2340 guess" for the alternative and is used to compute attributes of insns prior
2341 to reload. A negative value of STRICT is used for this internal call. */
2349 constrain_operands (int strict
)
2351 const char *constraints
[MAX_RECOG_OPERANDS
];
2352 int matching_operands
[MAX_RECOG_OPERANDS
];
2353 int earlyclobber
[MAX_RECOG_OPERANDS
];
2356 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2357 int funny_match_index
;
2359 which_alternative
= 0;
2360 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2363 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2365 constraints
[c
] = recog_data
.constraints
[c
];
2366 matching_operands
[c
] = -1;
2371 int seen_earlyclobber_at
= -1;
2374 funny_match_index
= 0;
2376 if (!recog_data
.alternative_enabled_p
[which_alternative
])
2380 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2381 constraints
[i
] = skip_alternative (constraints
[i
]);
2383 which_alternative
++;
2387 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2389 rtx op
= recog_data
.operand
[opno
];
2390 enum machine_mode mode
= GET_MODE (op
);
2391 const char *p
= constraints
[opno
];
2397 earlyclobber
[opno
] = 0;
2399 /* A unary operator may be accepted by the predicate, but it
2400 is irrelevant for matching constraints. */
2404 if (GET_CODE (op
) == SUBREG
)
2406 if (REG_P (SUBREG_REG (op
))
2407 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2408 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2409 GET_MODE (SUBREG_REG (op
)),
2412 op
= SUBREG_REG (op
);
2415 /* An empty constraint or empty alternative
2416 allows anything which matched the pattern. */
2417 if (*p
== 0 || *p
== ',')
2421 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2430 case '?': case '!': case '*': case '%':
2435 /* Ignore rest of this alternative as far as
2436 constraint checking is concerned. */
2439 while (*p
&& *p
!= ',');
2444 earlyclobber
[opno
] = 1;
2445 if (seen_earlyclobber_at
< 0)
2446 seen_earlyclobber_at
= opno
;
2449 case '0': case '1': case '2': case '3': case '4':
2450 case '5': case '6': case '7': case '8': case '9':
2452 /* This operand must be the same as a previous one.
2453 This kind of constraint is used for instructions such
2454 as add when they take only two operands.
2456 Note that the lower-numbered operand is passed first.
2458 If we are not testing strictly, assume that this
2459 constraint will be satisfied. */
2464 match
= strtoul (p
, &end
, 10);
2471 rtx op1
= recog_data
.operand
[match
];
2472 rtx op2
= recog_data
.operand
[opno
];
2474 /* A unary operator may be accepted by the predicate,
2475 but it is irrelevant for matching constraints. */
2477 op1
= XEXP (op1
, 0);
2479 op2
= XEXP (op2
, 0);
2481 val
= operands_match_p (op1
, op2
);
2484 matching_operands
[opno
] = match
;
2485 matching_operands
[match
] = opno
;
2490 /* If output is *x and input is *--x, arrange later
2491 to change the output to *--x as well, since the
2492 output op is the one that will be printed. */
2493 if (val
== 2 && strict
> 0)
2495 funny_match
[funny_match_index
].this_op
= opno
;
2496 funny_match
[funny_match_index
++].other
= match
;
2503 /* p is used for address_operands. When we are called by
2504 gen_reload, no one will have checked that the address is
2505 strictly valid, i.e., that all pseudos requiring hard regs
2506 have gotten them. */
2508 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2513 /* No need to check general_operand again;
2514 it was done in insn-recog.c. Well, except that reload
2515 doesn't check the validity of its replacements, but
2516 that should only matter when there's a bug. */
2518 /* Anything goes unless it is a REG and really has a hard reg
2519 but the hard reg is not in the class GENERAL_REGS. */
2523 || GENERAL_REGS
== ALL_REGS
2524 || (reload_in_progress
2525 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2526 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2529 else if (strict
< 0 || general_operand (op
, mode
))
2534 /* This is used for a MATCH_SCRATCH in the cases when
2535 we don't actually need anything. So anything goes
2540 case TARGET_MEM_CONSTRAINT
:
2541 /* Memory operands must be valid, to the extent
2542 required by STRICT. */
2546 && !strict_memory_address_addr_space_p
2547 (GET_MODE (op
), XEXP (op
, 0),
2548 MEM_ADDR_SPACE (op
)))
2551 && !memory_address_addr_space_p
2552 (GET_MODE (op
), XEXP (op
, 0),
2553 MEM_ADDR_SPACE (op
)))
2557 /* Before reload, accept what reload can turn into mem. */
2558 else if (strict
< 0 && CONSTANT_P (op
))
2560 /* During reload, accept a pseudo */
2561 else if (reload_in_progress
&& REG_P (op
)
2562 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2568 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2569 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2575 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2576 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2582 if (GET_CODE (op
) == CONST_DOUBLE
2583 || (GET_CODE (op
) == CONST_VECTOR
2584 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
2590 if (GET_CODE (op
) == CONST_DOUBLE
2591 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
2596 if (CONST_INT_P (op
)
2597 || (GET_CODE (op
) == CONST_DOUBLE
2598 && GET_MODE (op
) == VOIDmode
))
2601 if (CONSTANT_P (op
))
2606 if (CONST_INT_P (op
)
2607 || (GET_CODE (op
) == CONST_DOUBLE
2608 && GET_MODE (op
) == VOIDmode
))
2620 if (CONST_INT_P (op
)
2621 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
2627 && ((strict
> 0 && ! offsettable_memref_p (op
))
2629 && !(CONSTANT_P (op
) || MEM_P (op
)))
2630 || (reload_in_progress
2632 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2637 if ((strict
> 0 && offsettable_memref_p (op
))
2638 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2639 /* Before reload, accept what reload can handle. */
2641 && (CONSTANT_P (op
) || MEM_P (op
)))
2642 /* During reload, accept a pseudo */
2643 || (reload_in_progress
&& REG_P (op
)
2644 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2653 ? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c
, p
));
2659 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2660 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2662 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2665 #ifdef EXTRA_CONSTRAINT_STR
2666 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2669 else if (EXTRA_MEMORY_CONSTRAINT (c
, p
)
2670 /* Every memory operand can be reloaded to fit. */
2671 && ((strict
< 0 && MEM_P (op
))
2672 /* Before reload, accept what reload can turn
2674 || (strict
< 0 && CONSTANT_P (op
))
2675 /* During reload, accept a pseudo */
2676 || (reload_in_progress
&& REG_P (op
)
2677 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2679 else if (EXTRA_ADDRESS_CONSTRAINT (c
, p
)
2680 /* Every address operand can be reloaded to fit. */
2683 /* Cater to architectures like IA-64 that define extra memory
2684 constraints without using define_memory_constraint. */
2685 else if (reload_in_progress
2687 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2688 && reg_renumber
[REGNO (op
)] < 0
2689 && reg_equiv_mem (REGNO (op
)) != 0
2690 && EXTRA_CONSTRAINT_STR
2691 (reg_equiv_mem (REGNO (op
)), c
, p
))
2697 while (p
+= len
, c
);
2699 constraints
[opno
] = p
;
2700 /* If this operand did not win somehow,
2701 this alternative loses. */
2705 /* This alternative won; the operands are ok.
2706 Change whichever operands this alternative says to change. */
2711 /* See if any earlyclobber operand conflicts with some other
2714 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2715 for (eopno
= seen_earlyclobber_at
;
2716 eopno
< recog_data
.n_operands
;
2718 /* Ignore earlyclobber operands now in memory,
2719 because we would often report failure when we have
2720 two memory operands, one of which was formerly a REG. */
2721 if (earlyclobber
[eopno
]
2722 && REG_P (recog_data
.operand
[eopno
]))
2723 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2724 if ((MEM_P (recog_data
.operand
[opno
])
2725 || recog_data
.operand_type
[opno
] != OP_OUT
)
2727 /* Ignore things like match_operator operands. */
2728 && *recog_data
.constraints
[opno
] != 0
2729 && ! (matching_operands
[opno
] == eopno
2730 && operands_match_p (recog_data
.operand
[opno
],
2731 recog_data
.operand
[eopno
]))
2732 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2733 recog_data
.operand
[eopno
]))
2738 while (--funny_match_index
>= 0)
2740 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2741 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2745 /* For operands without < or > constraints reject side-effects. */
2746 if (recog_data
.is_asm
)
2748 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2749 if (MEM_P (recog_data
.operand
[opno
]))
2750 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2758 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2759 && strchr (recog_data
.constraints
[opno
], '>')
2772 which_alternative
++;
2774 while (which_alternative
< recog_data
.n_alternatives
);
2776 which_alternative
= -1;
2777 /* If we are about to reject this, but we are not to test strictly,
2778 try a very loose test. Only return failure if it fails also. */
2780 return constrain_operands (-1);
2785 /* Return true iff OPERAND (assumed to be a REG rtx)
2786 is a hard reg in class CLASS when its regno is offset by OFFSET
2787 and changed to mode MODE.
2788 If REG occupies multiple hard regs, all of them must be in CLASS. */
2791 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2792 enum machine_mode mode
)
2794 unsigned int regno
= REGNO (operand
);
2799 /* Regno must not be a pseudo register. Offset may be negative. */
2800 return (HARD_REGISTER_NUM_P (regno
)
2801 && HARD_REGISTER_NUM_P (regno
+ offset
)
2802 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2806 /* Split single instruction. Helper function for split_all_insns and
2807 split_all_insns_noflow. Return last insn in the sequence if successful,
2808 or NULL if unsuccessful. */
2811 split_insn (rtx insn
)
2813 /* Split insns here to get max fine-grain parallelism. */
2814 rtx first
= PREV_INSN (insn
);
2815 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2816 rtx insn_set
, last_set
, note
;
2821 /* If the original instruction was a single set that was known to be
2822 equivalent to a constant, see if we can say the same about the last
2823 instruction in the split sequence. The two instructions must set
2824 the same destination. */
2825 insn_set
= single_set (insn
);
2828 last_set
= single_set (last
);
2829 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2831 note
= find_reg_equal_equiv_note (insn
);
2832 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2833 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2834 else if (CONSTANT_P (SET_SRC (insn_set
)))
2835 set_unique_reg_note (last
, REG_EQUAL
, SET_SRC (insn_set
));
2839 /* try_split returns the NOTE that INSN became. */
2840 SET_INSN_DELETED (insn
);
2842 /* ??? Coddle to md files that generate subregs in post-reload
2843 splitters instead of computing the proper hard register. */
2844 if (reload_completed
&& first
!= last
)
2846 first
= NEXT_INSN (first
);
2850 cleanup_subreg_operands (first
);
2853 first
= NEXT_INSN (first
);
2860 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2863 split_all_insns (void)
2869 blocks
= sbitmap_alloc (last_basic_block
);
2870 sbitmap_zero (blocks
);
2873 FOR_EACH_BB_REVERSE (bb
)
2876 bool finish
= false;
2878 rtl_profile_for_bb (bb
);
2879 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2881 /* Can't use `next_real_insn' because that might go across
2882 CODE_LABELS and short-out basic blocks. */
2883 next
= NEXT_INSN (insn
);
2884 finish
= (insn
== BB_END (bb
));
2887 rtx set
= single_set (insn
);
2889 /* Don't split no-op move insns. These should silently
2890 disappear later in final. Splitting such insns would
2891 break the code that handles LIBCALL blocks. */
2892 if (set
&& set_noop_p (set
))
2894 /* Nops get in the way while scheduling, so delete them
2895 now if register allocation has already been done. It
2896 is too risky to try to do this before register
2897 allocation, and there are unlikely to be very many
2898 nops then anyways. */
2899 if (reload_completed
)
2900 delete_insn_and_edges (insn
);
2904 if (split_insn (insn
))
2906 SET_BIT (blocks
, bb
->index
);
2914 default_rtl_profile ();
2916 find_many_sub_basic_blocks (blocks
);
2918 #ifdef ENABLE_CHECKING
2919 verify_flow_info ();
2922 sbitmap_free (blocks
);
2925 /* Same as split_all_insns, but do not expect CFG to be available.
2926 Used by machine dependent reorg passes. */
2929 split_all_insns_noflow (void)
2933 for (insn
= get_insns (); insn
; insn
= next
)
2935 next
= NEXT_INSN (insn
);
2938 /* Don't split no-op move insns. These should silently
2939 disappear later in final. Splitting such insns would
2940 break the code that handles LIBCALL blocks. */
2941 rtx set
= single_set (insn
);
2942 if (set
&& set_noop_p (set
))
2944 /* Nops get in the way while scheduling, so delete them
2945 now if register allocation has already been done. It
2946 is too risky to try to do this before register
2947 allocation, and there are unlikely to be very many
2950 ??? Should we use delete_insn when the CFG isn't valid? */
2951 if (reload_completed
)
2952 delete_insn_and_edges (insn
);
2961 #ifdef HAVE_peephole2
2962 struct peep2_insn_data
2968 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
2969 static int peep2_current
;
2971 static bool peep2_do_rebuild_jump_labels
;
2972 static bool peep2_do_cleanup_cfg
;
2974 /* The number of instructions available to match a peep2. */
2975 int peep2_current_count
;
2977 /* A non-insn marker indicating the last insn of the block.
2978 The live_before regset for this element is correct, indicating
2979 DF_LIVE_OUT for the block. */
2980 #define PEEP2_EOB pc_rtx
2982 /* Wrap N to fit into the peep2_insn_data buffer. */
2985 peep2_buf_position (int n
)
2987 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2988 n
-= MAX_INSNS_PER_PEEP2
+ 1;
2992 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2993 does not exist. Used by the recognizer to find the next insn to match
2994 in a multi-insn pattern. */
2997 peep2_next_insn (int n
)
2999 gcc_assert (n
<= peep2_current_count
);
3001 n
= peep2_buf_position (peep2_current
+ n
);
3003 return peep2_insn_data
[n
].insn
;
3006 /* Return true if REGNO is dead before the Nth non-note insn
3010 peep2_regno_dead_p (int ofs
, int regno
)
3012 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3014 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3016 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3018 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3021 /* Similarly for a REG. */
3024 peep2_reg_dead_p (int ofs
, rtx reg
)
3028 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3030 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3032 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3034 regno
= REGNO (reg
);
3035 n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
3037 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
3042 /* Try to find a hard register of mode MODE, matching the register class in
3043 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3044 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3045 in which case the only condition is that the register must be available
3046 before CURRENT_INSN.
3047 Registers that already have bits set in REG_SET will not be considered.
3049 If an appropriate register is available, it will be returned and the
3050 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3054 peep2_find_free_register (int from
, int to
, const char *class_str
,
3055 enum machine_mode mode
, HARD_REG_SET
*reg_set
)
3057 static int search_ofs
;
3063 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3064 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3066 from
= peep2_buf_position (peep2_current
+ from
);
3067 to
= peep2_buf_position (peep2_current
+ to
);
3069 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3070 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3074 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3076 /* Don't use registers set or clobbered by the insn. */
3077 for (def_rec
= DF_INSN_DEFS (peep2_insn_data
[from
].insn
);
3078 *def_rec
; def_rec
++)
3079 SET_HARD_REG_BIT (live
, DF_REF_REGNO (*def_rec
));
3081 from
= peep2_buf_position (from
+ 1);
3084 cl
= (class_str
[0] == 'r' ? GENERAL_REGS
3085 : REG_CLASS_FROM_CONSTRAINT (class_str
[0], class_str
));
3087 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3089 int raw_regno
, regno
, success
, j
;
3091 /* Distribute the free registers as much as possible. */
3092 raw_regno
= search_ofs
+ i
;
3093 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3094 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3095 #ifdef REG_ALLOC_ORDER
3096 regno
= reg_alloc_order
[raw_regno
];
3101 /* Don't allocate fixed registers. */
3102 if (fixed_regs
[regno
])
3104 /* Don't allocate global registers. */
3105 if (global_regs
[regno
])
3107 /* Make sure the register is of the right class. */
3108 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
))
3110 /* And can support the mode we need. */
3111 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3113 /* And that we don't create an extra save/restore. */
3114 if (! call_used_regs
[regno
] && ! df_regs_ever_live_p (regno
))
3116 if (! targetm
.hard_regno_scratch_ok (regno
))
3119 /* And we don't clobber traceback for noreturn functions. */
3120 if ((regno
== FRAME_POINTER_REGNUM
|| regno
== HARD_FRAME_POINTER_REGNUM
)
3121 && (! reload_completed
|| frame_pointer_needed
))
3125 for (j
= hard_regno_nregs
[regno
][mode
] - 1; j
>= 0; j
--)
3127 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3128 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3136 add_to_hard_reg_set (reg_set
, mode
, regno
);
3138 /* Start the next search with the next register. */
3139 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3141 search_ofs
= raw_regno
;
3143 return gen_rtx_REG (mode
, regno
);
3151 /* Forget all currently tracked instructions, only remember current
3155 peep2_reinit_state (regset live
)
3159 /* Indicate that all slots except the last holds invalid data. */
3160 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3161 peep2_insn_data
[i
].insn
= NULL_RTX
;
3162 peep2_current_count
= 0;
3164 /* Indicate that the last slot contains live_after data. */
3165 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3166 peep2_current
= MAX_INSNS_PER_PEEP2
;
3168 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3171 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3172 starting at INSN. Perform the replacement, removing the old insns and
3173 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3174 if the replacement is rejected. */
3177 peep2_attempt (basic_block bb
, rtx insn
, int match_len
, rtx attempt
)
3180 rtx last
, eh_note
, as_note
, before_try
, x
;
3181 rtx old_insn
, new_insn
;
3182 bool was_call
= false;
3184 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3185 match more than one insn, or to be split into more than one insn. */
3186 old_insn
= peep2_insn_data
[peep2_current
].insn
;
3187 if (RTX_FRAME_RELATED_P (old_insn
))
3189 bool any_note
= false;
3195 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3196 may be in the stream for the purpose of register allocation. */
3197 if (active_insn_p (attempt
))
3200 new_insn
= next_active_insn (attempt
);
3201 if (next_active_insn (new_insn
))
3204 /* We have a 1-1 replacement. Copy over any frame-related info. */
3205 RTX_FRAME_RELATED_P (new_insn
) = 1;
3207 /* Allow the backend to fill in a note during the split. */
3208 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3209 switch (REG_NOTE_KIND (note
))
3211 case REG_FRAME_RELATED_EXPR
:
3212 case REG_CFA_DEF_CFA
:
3213 case REG_CFA_ADJUST_CFA
:
3214 case REG_CFA_OFFSET
:
3215 case REG_CFA_REGISTER
:
3216 case REG_CFA_EXPRESSION
:
3217 case REG_CFA_RESTORE
:
3218 case REG_CFA_SET_VDRAP
:
3225 /* If the backend didn't supply a note, copy one over. */
3227 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3228 switch (REG_NOTE_KIND (note
))
3230 case REG_FRAME_RELATED_EXPR
:
3231 case REG_CFA_DEF_CFA
:
3232 case REG_CFA_ADJUST_CFA
:
3233 case REG_CFA_OFFSET
:
3234 case REG_CFA_REGISTER
:
3235 case REG_CFA_EXPRESSION
:
3236 case REG_CFA_RESTORE
:
3237 case REG_CFA_SET_VDRAP
:
3238 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3245 /* If there still isn't a note, make sure the unwind info sees the
3246 same expression as before the split. */
3249 rtx old_set
, new_set
;
3251 /* The old insn had better have been simple, or annotated. */
3252 old_set
= single_set (old_insn
);
3253 gcc_assert (old_set
!= NULL
);
3255 new_set
= single_set (new_insn
);
3256 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3257 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3260 /* Copy prologue/epilogue status. This is required in order to keep
3261 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3262 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3265 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3266 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3267 cfg-related call notes. */
3268 for (i
= 0; i
<= match_len
; ++i
)
3273 j
= peep2_buf_position (peep2_current
+ i
);
3274 old_insn
= peep2_insn_data
[j
].insn
;
3275 if (!CALL_P (old_insn
))
3280 while (new_insn
!= NULL_RTX
)
3282 if (CALL_P (new_insn
))
3284 new_insn
= NEXT_INSN (new_insn
);
3287 gcc_assert (new_insn
!= NULL_RTX
);
3289 CALL_INSN_FUNCTION_USAGE (new_insn
)
3290 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3292 for (note
= REG_NOTES (old_insn
);
3294 note
= XEXP (note
, 1))
3295 switch (REG_NOTE_KIND (note
))
3300 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3304 /* Discard all other reg notes. */
3308 /* Croak if there is another call in the sequence. */
3309 while (++i
<= match_len
)
3311 j
= peep2_buf_position (peep2_current
+ i
);
3312 old_insn
= peep2_insn_data
[j
].insn
;
3313 gcc_assert (!CALL_P (old_insn
));
3318 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3319 move those notes over to the new sequence. */
3321 for (i
= match_len
; i
>= 0; --i
)
3323 int j
= peep2_buf_position (peep2_current
+ i
);
3324 old_insn
= peep2_insn_data
[j
].insn
;
3326 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3331 i
= peep2_buf_position (peep2_current
+ match_len
);
3332 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3334 /* Replace the old sequence with the new. */
3335 last
= emit_insn_after_setloc (attempt
,
3336 peep2_insn_data
[i
].insn
,
3337 INSN_LOCATOR (peep2_insn_data
[i
].insn
));
3338 before_try
= PREV_INSN (insn
);
3339 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3341 /* Re-insert the EH_REGION notes. */
3342 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3347 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3348 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3352 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3355 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3356 if (x
!= BB_END (bb
)
3357 && (can_throw_internal (x
)
3358 || can_nonlocal_goto (x
)))
3363 nfte
= split_block (bb
, x
);
3364 flags
= (eh_edge
->flags
3365 & (EDGE_EH
| EDGE_ABNORMAL
));
3367 flags
|= EDGE_ABNORMAL_CALL
;
3368 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3371 nehe
->probability
= eh_edge
->probability
;
3373 = REG_BR_PROB_BASE
- nehe
->probability
;
3375 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3380 /* Converting possibly trapping insn to non-trapping is
3381 possible. Zap dummy outgoing edges. */
3382 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3385 /* Re-insert the ARGS_SIZE notes. */
3387 fixup_args_size_notes (before_try
, last
, INTVAL (XEXP (as_note
, 0)));
3389 /* If we generated a jump instruction, it won't have
3390 JUMP_LABEL set. Recompute after we're done. */
3391 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3394 peep2_do_rebuild_jump_labels
= true;
3401 /* After performing a replacement in basic block BB, fix up the life
3402 information in our buffer. LAST is the last of the insns that we
3403 emitted as a replacement. PREV is the insn before the start of
3404 the replacement. MATCH_LEN is the number of instructions that were
3405 matched, and which now need to be replaced in the buffer. */
3408 peep2_update_life (basic_block bb
, int match_len
, rtx last
, rtx prev
)
3410 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3414 INIT_REG_SET (&live
);
3415 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3417 gcc_assert (peep2_current_count
>= match_len
+ 1);
3418 peep2_current_count
-= match_len
+ 1;
3426 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3428 peep2_current_count
++;
3430 i
= MAX_INSNS_PER_PEEP2
;
3431 peep2_insn_data
[i
].insn
= x
;
3432 df_simulate_one_insn_backwards (bb
, x
, &live
);
3433 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3439 CLEAR_REG_SET (&live
);
3444 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3445 Return true if we added it, false otherwise. The caller will try to match
3446 peepholes against the buffer if we return false; otherwise it will try to
3447 add more instructions to the buffer. */
3450 peep2_fill_buffer (basic_block bb
, rtx insn
, regset live
)
3454 /* Once we have filled the maximum number of insns the buffer can hold,
3455 allow the caller to match the insns against peepholes. We wait until
3456 the buffer is full in case the target has similar peepholes of different
3457 length; we always want to match the longest if possible. */
3458 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3461 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3462 any other pattern, lest it change the semantics of the frame info. */
3463 if (RTX_FRAME_RELATED_P (insn
))
3465 /* Let the buffer drain first. */
3466 if (peep2_current_count
> 0)
3468 /* Now the insn will be the only thing in the buffer. */
3471 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3472 peep2_insn_data
[pos
].insn
= insn
;
3473 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3474 peep2_current_count
++;
3476 df_simulate_one_insn_forwards (bb
, insn
, live
);
3480 /* Perform the peephole2 optimization pass. */
3483 peephole2_optimize (void)
3490 peep2_do_cleanup_cfg
= false;
3491 peep2_do_rebuild_jump_labels
= false;
3493 df_set_flags (DF_LR_RUN_DCE
);
3494 df_note_add_problem ();
3497 /* Initialize the regsets we're going to use. */
3498 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3499 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3500 live
= BITMAP_ALLOC (®_obstack
);
3502 FOR_EACH_BB_REVERSE (bb
)
3504 bool past_end
= false;
3507 rtl_profile_for_bb (bb
);
3509 /* Start up propagation. */
3510 bitmap_copy (live
, DF_LR_IN (bb
));
3511 df_simulate_initialize_forwards (bb
, live
);
3512 peep2_reinit_state (live
);
3514 insn
= BB_HEAD (bb
);
3520 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3523 insn
= NEXT_INSN (insn
);
3524 if (insn
== NEXT_INSN (BB_END (bb
)))
3528 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3531 /* If we did not fill an empty buffer, it signals the end of the
3533 if (peep2_current_count
== 0)
3536 /* The buffer filled to the current maximum, so try to match. */
3538 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3539 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3540 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3542 /* Match the peephole. */
3543 head
= peep2_insn_data
[peep2_current
].insn
;
3544 attempt
= peephole2_insns (PATTERN (head
), head
, &match_len
);
3545 if (attempt
!= NULL
)
3547 rtx last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3550 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3555 /* No match: advance the buffer by one insn. */
3556 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3557 peep2_current_count
--;
3561 default_rtl_profile ();
3562 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3563 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3565 if (peep2_do_rebuild_jump_labels
)
3566 rebuild_jump_labels (get_insns ());
3568 #endif /* HAVE_peephole2 */
3570 /* Common predicates for use with define_bypass. */
3572 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3573 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3574 must be either a single_set or a PARALLEL with SETs inside. */
3577 store_data_bypass_p (rtx out_insn
, rtx in_insn
)
3579 rtx out_set
, in_set
;
3580 rtx out_pat
, in_pat
;
3581 rtx out_exp
, in_exp
;
3584 in_set
= single_set (in_insn
);
3587 if (!MEM_P (SET_DEST (in_set
)))
3590 out_set
= single_set (out_insn
);
3593 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3598 out_pat
= PATTERN (out_insn
);
3600 if (GET_CODE (out_pat
) != PARALLEL
)
3603 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3605 out_exp
= XVECEXP (out_pat
, 0, i
);
3607 if (GET_CODE (out_exp
) == CLOBBER
)
3610 gcc_assert (GET_CODE (out_exp
) == SET
);
3612 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3619 in_pat
= PATTERN (in_insn
);
3620 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3622 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3624 in_exp
= XVECEXP (in_pat
, 0, i
);
3626 if (GET_CODE (in_exp
) == CLOBBER
)
3629 gcc_assert (GET_CODE (in_exp
) == SET
);
3631 if (!MEM_P (SET_DEST (in_exp
)))
3634 out_set
= single_set (out_insn
);
3637 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3642 out_pat
= PATTERN (out_insn
);
3643 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3645 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3647 out_exp
= XVECEXP (out_pat
, 0, j
);
3649 if (GET_CODE (out_exp
) == CLOBBER
)
3652 gcc_assert (GET_CODE (out_exp
) == SET
);
3654 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3664 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3665 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3666 or multiple set; IN_INSN should be single_set for truth, but for convenience
3667 of insn categorization may be any JUMP or CALL insn. */
3670 if_test_bypass_p (rtx out_insn
, rtx in_insn
)
3672 rtx out_set
, in_set
;
3674 in_set
= single_set (in_insn
);
3677 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3681 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3683 in_set
= SET_SRC (in_set
);
3685 out_set
= single_set (out_insn
);
3688 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3689 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3697 out_pat
= PATTERN (out_insn
);
3698 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3700 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3702 rtx exp
= XVECEXP (out_pat
, 0, i
);
3704 if (GET_CODE (exp
) == CLOBBER
)
3707 gcc_assert (GET_CODE (exp
) == SET
);
3709 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3710 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3719 gate_handle_peephole2 (void)
3721 return (optimize
> 0 && flag_peephole2
);
3725 rest_of_handle_peephole2 (void)
3727 #ifdef HAVE_peephole2
3728 peephole2_optimize ();
3733 struct rtl_opt_pass pass_peephole2
=
3737 "peephole2", /* name */
3738 gate_handle_peephole2
, /* gate */
3739 rest_of_handle_peephole2
, /* execute */
3742 0, /* static_pass_number */
3743 TV_PEEPHOLE2
, /* tv_id */
3744 0, /* properties_required */
3745 0, /* properties_provided */
3746 0, /* properties_destroyed */
3747 0, /* todo_flags_start */
3748 TODO_df_finish
| TODO_verify_rtl_sharing
|
3749 0 /* todo_flags_finish */
3754 rest_of_handle_split_all_insns (void)
3760 struct rtl_opt_pass pass_split_all_insns
=
3764 "split1", /* name */
3766 rest_of_handle_split_all_insns
, /* execute */
3769 0, /* static_pass_number */
3770 TV_NONE
, /* tv_id */
3771 0, /* properties_required */
3772 0, /* properties_provided */
3773 0, /* properties_destroyed */
3774 0, /* todo_flags_start */
3775 0 /* todo_flags_finish */
3780 rest_of_handle_split_after_reload (void)
3782 /* If optimizing, then go ahead and split insns now. */
3790 struct rtl_opt_pass pass_split_after_reload
=
3794 "split2", /* name */
3796 rest_of_handle_split_after_reload
, /* execute */
3799 0, /* static_pass_number */
3800 TV_NONE
, /* tv_id */
3801 0, /* properties_required */
3802 0, /* properties_provided */
3803 0, /* properties_destroyed */
3804 0, /* todo_flags_start */
3805 0 /* todo_flags_finish */
3810 gate_handle_split_before_regstack (void)
3812 #if defined (HAVE_ATTR_length) && defined (STACK_REGS)
3813 /* If flow2 creates new instructions which need splitting
3814 and scheduling after reload is not done, they might not be
3815 split until final which doesn't allow splitting
3816 if HAVE_ATTR_length. */
3817 # ifdef INSN_SCHEDULING
3818 return (optimize
&& !flag_schedule_insns_after_reload
);
3828 rest_of_handle_split_before_regstack (void)
3834 struct rtl_opt_pass pass_split_before_regstack
=
3838 "split3", /* name */
3839 gate_handle_split_before_regstack
, /* gate */
3840 rest_of_handle_split_before_regstack
, /* execute */
3843 0, /* static_pass_number */
3844 TV_NONE
, /* tv_id */
3845 0, /* properties_required */
3846 0, /* properties_provided */
3847 0, /* properties_destroyed */
3848 0, /* todo_flags_start */
3849 0 /* todo_flags_finish */
3854 gate_handle_split_before_sched2 (void)
3856 #ifdef INSN_SCHEDULING
3857 return optimize
> 0 && flag_schedule_insns_after_reload
;
3864 rest_of_handle_split_before_sched2 (void)
3866 #ifdef INSN_SCHEDULING
3872 struct rtl_opt_pass pass_split_before_sched2
=
3876 "split4", /* name */
3877 gate_handle_split_before_sched2
, /* gate */
3878 rest_of_handle_split_before_sched2
, /* execute */
3881 0, /* static_pass_number */
3882 TV_NONE
, /* tv_id */
3883 0, /* properties_required */
3884 0, /* properties_provided */
3885 0, /* properties_destroyed */
3886 0, /* todo_flags_start */
3887 TODO_verify_flow
/* todo_flags_finish */
3891 /* The placement of the splitting that we do for shorten_branches
3892 depends on whether regstack is used by the target or not. */
3894 gate_do_final_split (void)
3896 #if defined (HAVE_ATTR_length) && !defined (STACK_REGS)
3903 struct rtl_opt_pass pass_split_for_shorten_branches
=
3907 "split5", /* name */
3908 gate_do_final_split
, /* gate */
3909 split_all_insns_noflow
, /* execute */
3912 0, /* static_pass_number */
3913 TV_NONE
, /* tv_id */
3914 0, /* properties_required */
3915 0, /* properties_provided */
3916 0, /* properties_destroyed */
3917 0, /* todo_flags_start */
3918 TODO_verify_rtl_sharing
/* todo_flags_finish */