2017-10-15 Paolo Carlini <paolo.carlini@oracle.com>
[official-gcc.git] / gcc / expmed.c
blob27f5ae45d27c8ada700aa35a52f9a5ef37699090
1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987-2017 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "backend.h"
26 #include "target.h"
27 #include "rtl.h"
28 #include "tree.h"
29 #include "predict.h"
30 #include "memmodel.h"
31 #include "tm_p.h"
32 #include "expmed.h"
33 #include "optabs.h"
34 #include "regs.h"
35 #include "emit-rtl.h"
36 #include "diagnostic-core.h"
37 #include "fold-const.h"
38 #include "stor-layout.h"
39 #include "dojump.h"
40 #include "explow.h"
41 #include "expr.h"
42 #include "langhooks.h"
44 struct target_expmed default_target_expmed;
45 #if SWITCHABLE_TARGET
46 struct target_expmed *this_target_expmed = &default_target_expmed;
47 #endif
49 static void store_fixed_bit_field (rtx, opt_scalar_int_mode,
50 unsigned HOST_WIDE_INT,
51 unsigned HOST_WIDE_INT,
52 unsigned HOST_WIDE_INT,
53 unsigned HOST_WIDE_INT,
54 rtx, scalar_int_mode, bool);
55 static void store_fixed_bit_field_1 (rtx, scalar_int_mode,
56 unsigned HOST_WIDE_INT,
57 unsigned HOST_WIDE_INT,
58 rtx, scalar_int_mode, bool);
59 static void store_split_bit_field (rtx, opt_scalar_int_mode,
60 unsigned HOST_WIDE_INT,
61 unsigned HOST_WIDE_INT,
62 unsigned HOST_WIDE_INT,
63 unsigned HOST_WIDE_INT,
64 rtx, scalar_int_mode, bool);
65 static rtx extract_fixed_bit_field (machine_mode, rtx, opt_scalar_int_mode,
66 unsigned HOST_WIDE_INT,
67 unsigned HOST_WIDE_INT, rtx, int, bool);
68 static rtx extract_fixed_bit_field_1 (machine_mode, rtx, scalar_int_mode,
69 unsigned HOST_WIDE_INT,
70 unsigned HOST_WIDE_INT, rtx, int, bool);
71 static rtx lshift_value (machine_mode, unsigned HOST_WIDE_INT, int);
72 static rtx extract_split_bit_field (rtx, opt_scalar_int_mode,
73 unsigned HOST_WIDE_INT,
74 unsigned HOST_WIDE_INT, int, bool);
75 static void do_cmp_and_jump (rtx, rtx, enum rtx_code, machine_mode, rtx_code_label *);
76 static rtx expand_smod_pow2 (scalar_int_mode, rtx, HOST_WIDE_INT);
77 static rtx expand_sdiv_pow2 (scalar_int_mode, rtx, HOST_WIDE_INT);
79 /* Return a constant integer mask value of mode MODE with BITSIZE ones
80 followed by BITPOS zeros, or the complement of that if COMPLEMENT.
81 The mask is truncated if necessary to the width of mode MODE. The
82 mask is zero-extended if BITSIZE+BITPOS is too small for MODE. */
84 static inline rtx
85 mask_rtx (scalar_int_mode mode, int bitpos, int bitsize, bool complement)
87 return immed_wide_int_const
88 (wi::shifted_mask (bitpos, bitsize, complement,
89 GET_MODE_PRECISION (mode)), mode);
92 /* Test whether a value is zero of a power of two. */
93 #define EXACT_POWER_OF_2_OR_ZERO_P(x) \
94 (((x) & ((x) - HOST_WIDE_INT_1U)) == 0)
96 struct init_expmed_rtl
98 rtx reg;
99 rtx plus;
100 rtx neg;
101 rtx mult;
102 rtx sdiv;
103 rtx udiv;
104 rtx sdiv_32;
105 rtx smod_32;
106 rtx wide_mult;
107 rtx wide_lshr;
108 rtx wide_trunc;
109 rtx shift;
110 rtx shift_mult;
111 rtx shift_add;
112 rtx shift_sub0;
113 rtx shift_sub1;
114 rtx zext;
115 rtx trunc;
117 rtx pow2[MAX_BITS_PER_WORD];
118 rtx cint[MAX_BITS_PER_WORD];
121 static void
122 init_expmed_one_conv (struct init_expmed_rtl *all, scalar_int_mode to_mode,
123 scalar_int_mode from_mode, bool speed)
125 int to_size, from_size;
126 rtx which;
128 to_size = GET_MODE_PRECISION (to_mode);
129 from_size = GET_MODE_PRECISION (from_mode);
131 /* Most partial integers have a precision less than the "full"
132 integer it requires for storage. In case one doesn't, for
133 comparison purposes here, reduce the bit size by one in that
134 case. */
135 if (GET_MODE_CLASS (to_mode) == MODE_PARTIAL_INT
136 && pow2p_hwi (to_size))
137 to_size --;
138 if (GET_MODE_CLASS (from_mode) == MODE_PARTIAL_INT
139 && pow2p_hwi (from_size))
140 from_size --;
142 /* Assume cost of zero-extend and sign-extend is the same. */
143 which = (to_size < from_size ? all->trunc : all->zext);
145 PUT_MODE (all->reg, from_mode);
146 set_convert_cost (to_mode, from_mode, speed,
147 set_src_cost (which, to_mode, speed));
150 static void
151 init_expmed_one_mode (struct init_expmed_rtl *all,
152 machine_mode mode, int speed)
154 int m, n, mode_bitsize;
155 machine_mode mode_from;
157 mode_bitsize = GET_MODE_UNIT_BITSIZE (mode);
159 PUT_MODE (all->reg, mode);
160 PUT_MODE (all->plus, mode);
161 PUT_MODE (all->neg, mode);
162 PUT_MODE (all->mult, mode);
163 PUT_MODE (all->sdiv, mode);
164 PUT_MODE (all->udiv, mode);
165 PUT_MODE (all->sdiv_32, mode);
166 PUT_MODE (all->smod_32, mode);
167 PUT_MODE (all->wide_trunc, mode);
168 PUT_MODE (all->shift, mode);
169 PUT_MODE (all->shift_mult, mode);
170 PUT_MODE (all->shift_add, mode);
171 PUT_MODE (all->shift_sub0, mode);
172 PUT_MODE (all->shift_sub1, mode);
173 PUT_MODE (all->zext, mode);
174 PUT_MODE (all->trunc, mode);
176 set_add_cost (speed, mode, set_src_cost (all->plus, mode, speed));
177 set_neg_cost (speed, mode, set_src_cost (all->neg, mode, speed));
178 set_mul_cost (speed, mode, set_src_cost (all->mult, mode, speed));
179 set_sdiv_cost (speed, mode, set_src_cost (all->sdiv, mode, speed));
180 set_udiv_cost (speed, mode, set_src_cost (all->udiv, mode, speed));
182 set_sdiv_pow2_cheap (speed, mode, (set_src_cost (all->sdiv_32, mode, speed)
183 <= 2 * add_cost (speed, mode)));
184 set_smod_pow2_cheap (speed, mode, (set_src_cost (all->smod_32, mode, speed)
185 <= 4 * add_cost (speed, mode)));
187 set_shift_cost (speed, mode, 0, 0);
189 int cost = add_cost (speed, mode);
190 set_shiftadd_cost (speed, mode, 0, cost);
191 set_shiftsub0_cost (speed, mode, 0, cost);
192 set_shiftsub1_cost (speed, mode, 0, cost);
195 n = MIN (MAX_BITS_PER_WORD, mode_bitsize);
196 for (m = 1; m < n; m++)
198 XEXP (all->shift, 1) = all->cint[m];
199 XEXP (all->shift_mult, 1) = all->pow2[m];
201 set_shift_cost (speed, mode, m, set_src_cost (all->shift, mode, speed));
202 set_shiftadd_cost (speed, mode, m, set_src_cost (all->shift_add, mode,
203 speed));
204 set_shiftsub0_cost (speed, mode, m, set_src_cost (all->shift_sub0, mode,
205 speed));
206 set_shiftsub1_cost (speed, mode, m, set_src_cost (all->shift_sub1, mode,
207 speed));
210 scalar_int_mode int_mode_to;
211 if (is_a <scalar_int_mode> (mode, &int_mode_to))
213 for (mode_from = MIN_MODE_INT; mode_from <= MAX_MODE_INT;
214 mode_from = (machine_mode)(mode_from + 1))
215 init_expmed_one_conv (all, int_mode_to,
216 as_a <scalar_int_mode> (mode_from), speed);
218 scalar_int_mode wider_mode;
219 if (GET_MODE_CLASS (int_mode_to) == MODE_INT
220 && GET_MODE_WIDER_MODE (int_mode_to).exists (&wider_mode))
222 PUT_MODE (all->zext, wider_mode);
223 PUT_MODE (all->wide_mult, wider_mode);
224 PUT_MODE (all->wide_lshr, wider_mode);
225 XEXP (all->wide_lshr, 1) = GEN_INT (mode_bitsize);
227 set_mul_widen_cost (speed, wider_mode,
228 set_src_cost (all->wide_mult, wider_mode, speed));
229 set_mul_highpart_cost (speed, int_mode_to,
230 set_src_cost (all->wide_trunc,
231 int_mode_to, speed));
236 void
237 init_expmed (void)
239 struct init_expmed_rtl all;
240 machine_mode mode = QImode;
241 int m, speed;
243 memset (&all, 0, sizeof all);
244 for (m = 1; m < MAX_BITS_PER_WORD; m++)
246 all.pow2[m] = GEN_INT (HOST_WIDE_INT_1 << m);
247 all.cint[m] = GEN_INT (m);
250 /* Avoid using hard regs in ways which may be unsupported. */
251 all.reg = gen_raw_REG (mode, LAST_VIRTUAL_REGISTER + 1);
252 all.plus = gen_rtx_PLUS (mode, all.reg, all.reg);
253 all.neg = gen_rtx_NEG (mode, all.reg);
254 all.mult = gen_rtx_MULT (mode, all.reg, all.reg);
255 all.sdiv = gen_rtx_DIV (mode, all.reg, all.reg);
256 all.udiv = gen_rtx_UDIV (mode, all.reg, all.reg);
257 all.sdiv_32 = gen_rtx_DIV (mode, all.reg, all.pow2[5]);
258 all.smod_32 = gen_rtx_MOD (mode, all.reg, all.pow2[5]);
259 all.zext = gen_rtx_ZERO_EXTEND (mode, all.reg);
260 all.wide_mult = gen_rtx_MULT (mode, all.zext, all.zext);
261 all.wide_lshr = gen_rtx_LSHIFTRT (mode, all.wide_mult, all.reg);
262 all.wide_trunc = gen_rtx_TRUNCATE (mode, all.wide_lshr);
263 all.shift = gen_rtx_ASHIFT (mode, all.reg, all.reg);
264 all.shift_mult = gen_rtx_MULT (mode, all.reg, all.reg);
265 all.shift_add = gen_rtx_PLUS (mode, all.shift_mult, all.reg);
266 all.shift_sub0 = gen_rtx_MINUS (mode, all.shift_mult, all.reg);
267 all.shift_sub1 = gen_rtx_MINUS (mode, all.reg, all.shift_mult);
268 all.trunc = gen_rtx_TRUNCATE (mode, all.reg);
270 for (speed = 0; speed < 2; speed++)
272 crtl->maybe_hot_insn_p = speed;
273 set_zero_cost (speed, set_src_cost (const0_rtx, mode, speed));
275 for (mode = MIN_MODE_INT; mode <= MAX_MODE_INT;
276 mode = (machine_mode)(mode + 1))
277 init_expmed_one_mode (&all, mode, speed);
279 if (MIN_MODE_PARTIAL_INT != VOIDmode)
280 for (mode = MIN_MODE_PARTIAL_INT; mode <= MAX_MODE_PARTIAL_INT;
281 mode = (machine_mode)(mode + 1))
282 init_expmed_one_mode (&all, mode, speed);
284 if (MIN_MODE_VECTOR_INT != VOIDmode)
285 for (mode = MIN_MODE_VECTOR_INT; mode <= MAX_MODE_VECTOR_INT;
286 mode = (machine_mode)(mode + 1))
287 init_expmed_one_mode (&all, mode, speed);
290 if (alg_hash_used_p ())
292 struct alg_hash_entry *p = alg_hash_entry_ptr (0);
293 memset (p, 0, sizeof (*p) * NUM_ALG_HASH_ENTRIES);
295 else
296 set_alg_hash_used_p (true);
297 default_rtl_profile ();
299 ggc_free (all.trunc);
300 ggc_free (all.shift_sub1);
301 ggc_free (all.shift_sub0);
302 ggc_free (all.shift_add);
303 ggc_free (all.shift_mult);
304 ggc_free (all.shift);
305 ggc_free (all.wide_trunc);
306 ggc_free (all.wide_lshr);
307 ggc_free (all.wide_mult);
308 ggc_free (all.zext);
309 ggc_free (all.smod_32);
310 ggc_free (all.sdiv_32);
311 ggc_free (all.udiv);
312 ggc_free (all.sdiv);
313 ggc_free (all.mult);
314 ggc_free (all.neg);
315 ggc_free (all.plus);
316 ggc_free (all.reg);
319 /* Return an rtx representing minus the value of X.
320 MODE is the intended mode of the result,
321 useful if X is a CONST_INT. */
324 negate_rtx (machine_mode mode, rtx x)
326 rtx result = simplify_unary_operation (NEG, mode, x, mode);
328 if (result == 0)
329 result = expand_unop (mode, neg_optab, x, NULL_RTX, 0);
331 return result;
334 /* Whether reverse storage order is supported on the target. */
335 static int reverse_storage_order_supported = -1;
337 /* Check whether reverse storage order is supported on the target. */
339 static void
340 check_reverse_storage_order_support (void)
342 if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN)
344 reverse_storage_order_supported = 0;
345 sorry ("reverse scalar storage order");
347 else
348 reverse_storage_order_supported = 1;
351 /* Whether reverse FP storage order is supported on the target. */
352 static int reverse_float_storage_order_supported = -1;
354 /* Check whether reverse FP storage order is supported on the target. */
356 static void
357 check_reverse_float_storage_order_support (void)
359 if (FLOAT_WORDS_BIG_ENDIAN != WORDS_BIG_ENDIAN)
361 reverse_float_storage_order_supported = 0;
362 sorry ("reverse floating-point scalar storage order");
364 else
365 reverse_float_storage_order_supported = 1;
368 /* Return an rtx representing value of X with reverse storage order.
369 MODE is the intended mode of the result,
370 useful if X is a CONST_INT. */
373 flip_storage_order (machine_mode mode, rtx x)
375 scalar_int_mode int_mode;
376 rtx result;
378 if (mode == QImode)
379 return x;
381 if (COMPLEX_MODE_P (mode))
383 rtx real = read_complex_part (x, false);
384 rtx imag = read_complex_part (x, true);
386 real = flip_storage_order (GET_MODE_INNER (mode), real);
387 imag = flip_storage_order (GET_MODE_INNER (mode), imag);
389 return gen_rtx_CONCAT (mode, real, imag);
392 if (__builtin_expect (reverse_storage_order_supported < 0, 0))
393 check_reverse_storage_order_support ();
395 if (!is_a <scalar_int_mode> (mode, &int_mode))
397 if (FLOAT_MODE_P (mode)
398 && __builtin_expect (reverse_float_storage_order_supported < 0, 0))
399 check_reverse_float_storage_order_support ();
401 if (!int_mode_for_size (GET_MODE_PRECISION (mode), 0).exists (&int_mode))
403 sorry ("reverse storage order for %smode", GET_MODE_NAME (mode));
404 return x;
406 x = gen_lowpart (int_mode, x);
409 result = simplify_unary_operation (BSWAP, int_mode, x, int_mode);
410 if (result == 0)
411 result = expand_unop (int_mode, bswap_optab, x, NULL_RTX, 1);
413 if (int_mode != mode)
414 result = gen_lowpart (mode, result);
416 return result;
419 /* If MODE is set, adjust bitfield memory MEM so that it points to the
420 first unit of mode MODE that contains a bitfield of size BITSIZE at
421 bit position BITNUM. If MODE is not set, return a BLKmode reference
422 to every byte in the bitfield. Set *NEW_BITNUM to the bit position
423 of the field within the new memory. */
425 static rtx
426 narrow_bit_field_mem (rtx mem, opt_scalar_int_mode mode,
427 unsigned HOST_WIDE_INT bitsize,
428 unsigned HOST_WIDE_INT bitnum,
429 unsigned HOST_WIDE_INT *new_bitnum)
431 scalar_int_mode imode;
432 if (mode.exists (&imode))
434 unsigned int unit = GET_MODE_BITSIZE (imode);
435 *new_bitnum = bitnum % unit;
436 HOST_WIDE_INT offset = (bitnum - *new_bitnum) / BITS_PER_UNIT;
437 return adjust_bitfield_address (mem, imode, offset);
439 else
441 *new_bitnum = bitnum % BITS_PER_UNIT;
442 HOST_WIDE_INT offset = bitnum / BITS_PER_UNIT;
443 HOST_WIDE_INT size = ((*new_bitnum + bitsize + BITS_PER_UNIT - 1)
444 / BITS_PER_UNIT);
445 return adjust_bitfield_address_size (mem, BLKmode, offset, size);
449 /* The caller wants to perform insertion or extraction PATTERN on a
450 bitfield of size BITSIZE at BITNUM bits into memory operand OP0.
451 BITREGION_START and BITREGION_END are as for store_bit_field
452 and FIELDMODE is the natural mode of the field.
454 Search for a mode that is compatible with the memory access
455 restrictions and (where applicable) with a register insertion or
456 extraction. Return the new memory on success, storing the adjusted
457 bit position in *NEW_BITNUM. Return null otherwise. */
459 static rtx
460 adjust_bit_field_mem_for_reg (enum extraction_pattern pattern,
461 rtx op0, HOST_WIDE_INT bitsize,
462 HOST_WIDE_INT bitnum,
463 unsigned HOST_WIDE_INT bitregion_start,
464 unsigned HOST_WIDE_INT bitregion_end,
465 machine_mode fieldmode,
466 unsigned HOST_WIDE_INT *new_bitnum)
468 bit_field_mode_iterator iter (bitsize, bitnum, bitregion_start,
469 bitregion_end, MEM_ALIGN (op0),
470 MEM_VOLATILE_P (op0));
471 scalar_int_mode best_mode;
472 if (iter.next_mode (&best_mode))
474 /* We can use a memory in BEST_MODE. See whether this is true for
475 any wider modes. All other things being equal, we prefer to
476 use the widest mode possible because it tends to expose more
477 CSE opportunities. */
478 if (!iter.prefer_smaller_modes ())
480 /* Limit the search to the mode required by the corresponding
481 register insertion or extraction instruction, if any. */
482 scalar_int_mode limit_mode = word_mode;
483 extraction_insn insn;
484 if (get_best_reg_extraction_insn (&insn, pattern,
485 GET_MODE_BITSIZE (best_mode),
486 fieldmode))
487 limit_mode = insn.field_mode;
489 scalar_int_mode wider_mode;
490 while (iter.next_mode (&wider_mode)
491 && GET_MODE_SIZE (wider_mode) <= GET_MODE_SIZE (limit_mode))
492 best_mode = wider_mode;
494 return narrow_bit_field_mem (op0, best_mode, bitsize, bitnum,
495 new_bitnum);
497 return NULL_RTX;
500 /* Return true if a bitfield of size BITSIZE at bit number BITNUM within
501 a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg
502 offset is then BITNUM / BITS_PER_UNIT. */
504 static bool
505 lowpart_bit_field_p (unsigned HOST_WIDE_INT bitnum,
506 unsigned HOST_WIDE_INT bitsize,
507 machine_mode struct_mode)
509 if (BYTES_BIG_ENDIAN)
510 return (bitnum % BITS_PER_UNIT == 0
511 && (bitnum + bitsize == GET_MODE_BITSIZE (struct_mode)
512 || (bitnum + bitsize) % BITS_PER_WORD == 0));
513 else
514 return bitnum % BITS_PER_WORD == 0;
517 /* Return true if -fstrict-volatile-bitfields applies to an access of OP0
518 containing BITSIZE bits starting at BITNUM, with field mode FIELDMODE.
519 Return false if the access would touch memory outside the range
520 BITREGION_START to BITREGION_END for conformance to the C++ memory
521 model. */
523 static bool
524 strict_volatile_bitfield_p (rtx op0, unsigned HOST_WIDE_INT bitsize,
525 unsigned HOST_WIDE_INT bitnum,
526 scalar_int_mode fieldmode,
527 unsigned HOST_WIDE_INT bitregion_start,
528 unsigned HOST_WIDE_INT bitregion_end)
530 unsigned HOST_WIDE_INT modesize = GET_MODE_BITSIZE (fieldmode);
532 /* -fstrict-volatile-bitfields must be enabled and we must have a
533 volatile MEM. */
534 if (!MEM_P (op0)
535 || !MEM_VOLATILE_P (op0)
536 || flag_strict_volatile_bitfields <= 0)
537 return false;
539 /* The bit size must not be larger than the field mode, and
540 the field mode must not be larger than a word. */
541 if (bitsize > modesize || modesize > BITS_PER_WORD)
542 return false;
544 /* Check for cases of unaligned fields that must be split. */
545 if (bitnum % modesize + bitsize > modesize)
546 return false;
548 /* The memory must be sufficiently aligned for a MODESIZE access.
549 This condition guarantees, that the memory access will not
550 touch anything after the end of the structure. */
551 if (MEM_ALIGN (op0) < modesize)
552 return false;
554 /* Check for cases where the C++ memory model applies. */
555 if (bitregion_end != 0
556 && (bitnum - bitnum % modesize < bitregion_start
557 || bitnum - bitnum % modesize + modesize - 1 > bitregion_end))
558 return false;
560 return true;
563 /* Return true if OP is a memory and if a bitfield of size BITSIZE at
564 bit number BITNUM can be treated as a simple value of mode MODE. */
566 static bool
567 simple_mem_bitfield_p (rtx op0, unsigned HOST_WIDE_INT bitsize,
568 unsigned HOST_WIDE_INT bitnum, machine_mode mode)
570 return (MEM_P (op0)
571 && bitnum % BITS_PER_UNIT == 0
572 && bitsize == GET_MODE_BITSIZE (mode)
573 && (!targetm.slow_unaligned_access (mode, MEM_ALIGN (op0))
574 || (bitnum % GET_MODE_ALIGNMENT (mode) == 0
575 && MEM_ALIGN (op0) >= GET_MODE_ALIGNMENT (mode))));
578 /* Try to use instruction INSV to store VALUE into a field of OP0.
579 If OP0_MODE is defined, it is the mode of OP0, otherwise OP0 is a
580 BLKmode MEM. VALUE_MODE is the mode of VALUE. BITSIZE and BITNUM
581 are as for store_bit_field. */
583 static bool
584 store_bit_field_using_insv (const extraction_insn *insv, rtx op0,
585 opt_scalar_int_mode op0_mode,
586 unsigned HOST_WIDE_INT bitsize,
587 unsigned HOST_WIDE_INT bitnum,
588 rtx value, scalar_int_mode value_mode)
590 struct expand_operand ops[4];
591 rtx value1;
592 rtx xop0 = op0;
593 rtx_insn *last = get_last_insn ();
594 bool copy_back = false;
596 scalar_int_mode op_mode = insv->field_mode;
597 unsigned int unit = GET_MODE_BITSIZE (op_mode);
598 if (bitsize == 0 || bitsize > unit)
599 return false;
601 if (MEM_P (xop0))
602 /* Get a reference to the first byte of the field. */
603 xop0 = narrow_bit_field_mem (xop0, insv->struct_mode, bitsize, bitnum,
604 &bitnum);
605 else
607 /* Convert from counting within OP0 to counting in OP_MODE. */
608 if (BYTES_BIG_ENDIAN)
609 bitnum += unit - GET_MODE_BITSIZE (op0_mode.require ());
611 /* If xop0 is a register, we need it in OP_MODE
612 to make it acceptable to the format of insv. */
613 if (GET_CODE (xop0) == SUBREG)
614 /* We can't just change the mode, because this might clobber op0,
615 and we will need the original value of op0 if insv fails. */
616 xop0 = gen_rtx_SUBREG (op_mode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
617 if (REG_P (xop0) && GET_MODE (xop0) != op_mode)
618 xop0 = gen_lowpart_SUBREG (op_mode, xop0);
621 /* If the destination is a paradoxical subreg such that we need a
622 truncate to the inner mode, perform the insertion on a temporary and
623 truncate the result to the original destination. Note that we can't
624 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
625 X) 0)) is (reg:N X). */
626 if (GET_CODE (xop0) == SUBREG
627 && REG_P (SUBREG_REG (xop0))
628 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0)),
629 op_mode))
631 rtx tem = gen_reg_rtx (op_mode);
632 emit_move_insn (tem, xop0);
633 xop0 = tem;
634 copy_back = true;
637 /* There are similar overflow check at the start of store_bit_field_1,
638 but that only check the situation where the field lies completely
639 outside the register, while there do have situation where the field
640 lies partialy in the register, we need to adjust bitsize for this
641 partial overflow situation. Without this fix, pr48335-2.c on big-endian
642 will broken on those arch support bit insert instruction, like arm, aarch64
643 etc. */
644 if (bitsize + bitnum > unit && bitnum < unit)
646 warning (OPT_Wextra, "write of %wu-bit data outside the bound of "
647 "destination object, data truncated into %wu-bit",
648 bitsize, unit - bitnum);
649 bitsize = unit - bitnum;
652 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
653 "backwards" from the size of the unit we are inserting into.
654 Otherwise, we count bits from the most significant on a
655 BYTES/BITS_BIG_ENDIAN machine. */
657 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
658 bitnum = unit - bitsize - bitnum;
660 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
661 value1 = value;
662 if (value_mode != op_mode)
664 if (GET_MODE_BITSIZE (value_mode) >= bitsize)
666 rtx tmp;
667 /* Optimization: Don't bother really extending VALUE
668 if it has all the bits we will actually use. However,
669 if we must narrow it, be sure we do it correctly. */
671 if (GET_MODE_SIZE (value_mode) < GET_MODE_SIZE (op_mode))
673 tmp = simplify_subreg (op_mode, value1, value_mode, 0);
674 if (! tmp)
675 tmp = simplify_gen_subreg (op_mode,
676 force_reg (value_mode, value1),
677 value_mode, 0);
679 else
681 tmp = gen_lowpart_if_possible (op_mode, value1);
682 if (! tmp)
683 tmp = gen_lowpart (op_mode, force_reg (value_mode, value1));
685 value1 = tmp;
687 else if (CONST_INT_P (value))
688 value1 = gen_int_mode (INTVAL (value), op_mode);
689 else
690 /* Parse phase is supposed to make VALUE's data type
691 match that of the component reference, which is a type
692 at least as wide as the field; so VALUE should have
693 a mode that corresponds to that type. */
694 gcc_assert (CONSTANT_P (value));
697 create_fixed_operand (&ops[0], xop0);
698 create_integer_operand (&ops[1], bitsize);
699 create_integer_operand (&ops[2], bitnum);
700 create_input_operand (&ops[3], value1, op_mode);
701 if (maybe_expand_insn (insv->icode, 4, ops))
703 if (copy_back)
704 convert_move (op0, xop0, true);
705 return true;
707 delete_insns_since (last);
708 return false;
711 /* A subroutine of store_bit_field, with the same arguments. Return true
712 if the operation could be implemented.
714 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
715 no other way of implementing the operation. If FALLBACK_P is false,
716 return false instead. */
718 static bool
719 store_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
720 unsigned HOST_WIDE_INT bitnum,
721 unsigned HOST_WIDE_INT bitregion_start,
722 unsigned HOST_WIDE_INT bitregion_end,
723 machine_mode fieldmode,
724 rtx value, bool reverse, bool fallback_p)
726 rtx op0 = str_rtx;
727 rtx orig_value;
729 while (GET_CODE (op0) == SUBREG)
731 bitnum += subreg_memory_offset (op0) * BITS_PER_UNIT;
732 op0 = SUBREG_REG (op0);
735 /* No action is needed if the target is a register and if the field
736 lies completely outside that register. This can occur if the source
737 code contains an out-of-bounds access to a small array. */
738 if (REG_P (op0) && bitnum >= GET_MODE_BITSIZE (GET_MODE (op0)))
739 return true;
741 /* Use vec_set patterns for inserting parts of vectors whenever
742 available. */
743 machine_mode outermode = GET_MODE (op0);
744 scalar_mode innermode = GET_MODE_INNER (outermode);
745 if (VECTOR_MODE_P (outermode)
746 && !MEM_P (op0)
747 && optab_handler (vec_set_optab, outermode) != CODE_FOR_nothing
748 && fieldmode == innermode
749 && bitsize == GET_MODE_BITSIZE (innermode)
750 && !(bitnum % GET_MODE_BITSIZE (innermode)))
752 struct expand_operand ops[3];
753 enum insn_code icode = optab_handler (vec_set_optab, outermode);
754 int pos = bitnum / GET_MODE_BITSIZE (innermode);
756 create_fixed_operand (&ops[0], op0);
757 create_input_operand (&ops[1], value, innermode);
758 create_integer_operand (&ops[2], pos);
759 if (maybe_expand_insn (icode, 3, ops))
760 return true;
763 /* If the target is a register, overwriting the entire object, or storing
764 a full-word or multi-word field can be done with just a SUBREG. */
765 if (!MEM_P (op0)
766 && bitsize == GET_MODE_BITSIZE (fieldmode)
767 && ((bitsize == GET_MODE_BITSIZE (GET_MODE (op0)) && bitnum == 0)
768 || (bitsize % BITS_PER_WORD == 0 && bitnum % BITS_PER_WORD == 0)))
770 /* Use the subreg machinery either to narrow OP0 to the required
771 words or to cope with mode punning between equal-sized modes.
772 In the latter case, use subreg on the rhs side, not lhs. */
773 rtx sub;
775 if (bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
777 sub = simplify_gen_subreg (GET_MODE (op0), value, fieldmode, 0);
778 if (sub)
780 if (reverse)
781 sub = flip_storage_order (GET_MODE (op0), sub);
782 emit_move_insn (op0, sub);
783 return true;
786 else
788 sub = simplify_gen_subreg (fieldmode, op0, GET_MODE (op0),
789 bitnum / BITS_PER_UNIT);
790 if (sub)
792 if (reverse)
793 value = flip_storage_order (fieldmode, value);
794 emit_move_insn (sub, value);
795 return true;
800 /* If the target is memory, storing any naturally aligned field can be
801 done with a simple store. For targets that support fast unaligned
802 memory, any naturally sized, unit aligned field can be done directly. */
803 if (simple_mem_bitfield_p (op0, bitsize, bitnum, fieldmode))
805 op0 = adjust_bitfield_address (op0, fieldmode, bitnum / BITS_PER_UNIT);
806 if (reverse)
807 value = flip_storage_order (fieldmode, value);
808 emit_move_insn (op0, value);
809 return true;
812 /* Make sure we are playing with integral modes. Pun with subregs
813 if we aren't. This must come after the entire register case above,
814 since that case is valid for any mode. The following cases are only
815 valid for integral modes. */
816 opt_scalar_int_mode op0_mode = int_mode_for_mode (GET_MODE (op0));
817 scalar_int_mode imode;
818 if (!op0_mode.exists (&imode) || imode != GET_MODE (op0))
820 if (MEM_P (op0))
821 op0 = adjust_bitfield_address_size (op0, op0_mode.else_blk (),
822 0, MEM_SIZE (op0));
823 else
824 op0 = gen_lowpart (op0_mode.require (), op0);
827 /* Storing an lsb-aligned field in a register
828 can be done with a movstrict instruction. */
830 if (!MEM_P (op0)
831 && !reverse
832 && lowpart_bit_field_p (bitnum, bitsize, GET_MODE (op0))
833 && bitsize == GET_MODE_BITSIZE (fieldmode)
834 && optab_handler (movstrict_optab, fieldmode) != CODE_FOR_nothing)
836 struct expand_operand ops[2];
837 enum insn_code icode = optab_handler (movstrict_optab, fieldmode);
838 rtx arg0 = op0;
839 unsigned HOST_WIDE_INT subreg_off;
841 if (GET_CODE (arg0) == SUBREG)
843 /* Else we've got some float mode source being extracted into
844 a different float mode destination -- this combination of
845 subregs results in Severe Tire Damage. */
846 gcc_assert (GET_MODE (SUBREG_REG (arg0)) == fieldmode
847 || GET_MODE_CLASS (fieldmode) == MODE_INT
848 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT);
849 arg0 = SUBREG_REG (arg0);
852 subreg_off = bitnum / BITS_PER_UNIT;
853 if (validate_subreg (fieldmode, GET_MODE (arg0), arg0, subreg_off))
855 arg0 = gen_rtx_SUBREG (fieldmode, arg0, subreg_off);
857 create_fixed_operand (&ops[0], arg0);
858 /* Shrink the source operand to FIELDMODE. */
859 create_convert_operand_to (&ops[1], value, fieldmode, false);
860 if (maybe_expand_insn (icode, 2, ops))
861 return true;
865 /* Handle fields bigger than a word. */
867 if (bitsize > BITS_PER_WORD)
869 /* Here we transfer the words of the field
870 in the order least significant first.
871 This is because the most significant word is the one which may
872 be less than full.
873 However, only do that if the value is not BLKmode. */
875 const bool backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode;
876 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
877 unsigned int i;
878 rtx_insn *last;
880 /* This is the mode we must force value to, so that there will be enough
881 subwords to extract. Note that fieldmode will often (always?) be
882 VOIDmode, because that is what store_field uses to indicate that this
883 is a bit field, but passing VOIDmode to operand_subword_force
884 is not allowed. */
885 fieldmode = GET_MODE (value);
886 if (fieldmode == VOIDmode)
887 fieldmode = smallest_int_mode_for_size (nwords * BITS_PER_WORD);
889 last = get_last_insn ();
890 for (i = 0; i < nwords; i++)
892 /* If I is 0, use the low-order word in both field and target;
893 if I is 1, use the next to lowest word; and so on. */
894 unsigned int wordnum = (backwards
895 ? GET_MODE_SIZE (fieldmode) / UNITS_PER_WORD
896 - i - 1
897 : i);
898 unsigned int bit_offset = (backwards ^ reverse
899 ? MAX ((int) bitsize - ((int) i + 1)
900 * BITS_PER_WORD,
902 : (int) i * BITS_PER_WORD);
903 rtx value_word = operand_subword_force (value, wordnum, fieldmode);
904 unsigned HOST_WIDE_INT new_bitsize =
905 MIN (BITS_PER_WORD, bitsize - i * BITS_PER_WORD);
907 /* If the remaining chunk doesn't have full wordsize we have
908 to make sure that for big-endian machines the higher order
909 bits are used. */
910 if (new_bitsize < BITS_PER_WORD && BYTES_BIG_ENDIAN && !backwards)
911 value_word = simplify_expand_binop (word_mode, lshr_optab,
912 value_word,
913 GEN_INT (BITS_PER_WORD
914 - new_bitsize),
915 NULL_RTX, true,
916 OPTAB_LIB_WIDEN);
918 if (!store_bit_field_1 (op0, new_bitsize,
919 bitnum + bit_offset,
920 bitregion_start, bitregion_end,
921 word_mode,
922 value_word, reverse, fallback_p))
924 delete_insns_since (last);
925 return false;
928 return true;
931 /* If VALUE has a floating-point or complex mode, access it as an
932 integer of the corresponding size. This can occur on a machine
933 with 64 bit registers that uses SFmode for float. It can also
934 occur for unaligned float or complex fields. */
935 orig_value = value;
936 scalar_int_mode value_mode;
937 if (GET_MODE (value) == VOIDmode)
938 /* By this point we've dealt with values that are bigger than a word,
939 so word_mode is a conservatively correct choice. */
940 value_mode = word_mode;
941 else if (!is_a <scalar_int_mode> (GET_MODE (value), &value_mode))
943 value_mode = int_mode_for_mode (GET_MODE (value)).require ();
944 value = gen_reg_rtx (value_mode);
945 emit_move_insn (gen_lowpart (GET_MODE (orig_value), value), orig_value);
948 /* If OP0 is a multi-word register, narrow it to the affected word.
949 If the region spans two words, defer to store_split_bit_field.
950 Don't do this if op0 is a single hard register wider than word
951 such as a float or vector register. */
952 if (!MEM_P (op0)
953 && GET_MODE_SIZE (op0_mode.require ()) > UNITS_PER_WORD
954 && (!REG_P (op0)
955 || !HARD_REGISTER_P (op0)
956 || hard_regno_nregs (REGNO (op0), op0_mode.require ()) != 1))
958 if (bitnum % BITS_PER_WORD + bitsize > BITS_PER_WORD)
960 if (!fallback_p)
961 return false;
963 store_split_bit_field (op0, op0_mode, bitsize, bitnum,
964 bitregion_start, bitregion_end,
965 value, value_mode, reverse);
966 return true;
968 op0 = simplify_gen_subreg (word_mode, op0, op0_mode.require (),
969 bitnum / BITS_PER_WORD * UNITS_PER_WORD);
970 gcc_assert (op0);
971 op0_mode = word_mode;
972 bitnum %= BITS_PER_WORD;
975 /* From here on we can assume that the field to be stored in fits
976 within a word. If the destination is a register, it too fits
977 in a word. */
979 extraction_insn insv;
980 if (!MEM_P (op0)
981 && !reverse
982 && get_best_reg_extraction_insn (&insv, EP_insv,
983 GET_MODE_BITSIZE (op0_mode.require ()),
984 fieldmode)
985 && store_bit_field_using_insv (&insv, op0, op0_mode,
986 bitsize, bitnum, value, value_mode))
987 return true;
989 /* If OP0 is a memory, try copying it to a register and seeing if a
990 cheap register alternative is available. */
991 if (MEM_P (op0) && !reverse)
993 if (get_best_mem_extraction_insn (&insv, EP_insv, bitsize, bitnum,
994 fieldmode)
995 && store_bit_field_using_insv (&insv, op0, op0_mode,
996 bitsize, bitnum, value, value_mode))
997 return true;
999 rtx_insn *last = get_last_insn ();
1001 /* Try loading part of OP0 into a register, inserting the bitfield
1002 into that, and then copying the result back to OP0. */
1003 unsigned HOST_WIDE_INT bitpos;
1004 rtx xop0 = adjust_bit_field_mem_for_reg (EP_insv, op0, bitsize, bitnum,
1005 bitregion_start, bitregion_end,
1006 fieldmode, &bitpos);
1007 if (xop0)
1009 rtx tempreg = copy_to_reg (xop0);
1010 if (store_bit_field_1 (tempreg, bitsize, bitpos,
1011 bitregion_start, bitregion_end,
1012 fieldmode, orig_value, reverse, false))
1014 emit_move_insn (xop0, tempreg);
1015 return true;
1017 delete_insns_since (last);
1021 if (!fallback_p)
1022 return false;
1024 store_fixed_bit_field (op0, op0_mode, bitsize, bitnum, bitregion_start,
1025 bitregion_end, value, value_mode, reverse);
1026 return true;
1029 /* Generate code to store value from rtx VALUE
1030 into a bit-field within structure STR_RTX
1031 containing BITSIZE bits starting at bit BITNUM.
1033 BITREGION_START is bitpos of the first bitfield in this region.
1034 BITREGION_END is the bitpos of the ending bitfield in this region.
1035 These two fields are 0, if the C++ memory model does not apply,
1036 or we are not interested in keeping track of bitfield regions.
1038 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
1040 If REVERSE is true, the store is to be done in reverse order. */
1042 void
1043 store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1044 unsigned HOST_WIDE_INT bitnum,
1045 unsigned HOST_WIDE_INT bitregion_start,
1046 unsigned HOST_WIDE_INT bitregion_end,
1047 machine_mode fieldmode,
1048 rtx value, bool reverse)
1050 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
1051 scalar_int_mode int_mode;
1052 if (is_a <scalar_int_mode> (fieldmode, &int_mode)
1053 && strict_volatile_bitfield_p (str_rtx, bitsize, bitnum, int_mode,
1054 bitregion_start, bitregion_end))
1056 /* Storing of a full word can be done with a simple store.
1057 We know here that the field can be accessed with one single
1058 instruction. For targets that support unaligned memory,
1059 an unaligned access may be necessary. */
1060 if (bitsize == GET_MODE_BITSIZE (int_mode))
1062 str_rtx = adjust_bitfield_address (str_rtx, int_mode,
1063 bitnum / BITS_PER_UNIT);
1064 if (reverse)
1065 value = flip_storage_order (int_mode, value);
1066 gcc_assert (bitnum % BITS_PER_UNIT == 0);
1067 emit_move_insn (str_rtx, value);
1069 else
1071 rtx temp;
1073 str_rtx = narrow_bit_field_mem (str_rtx, int_mode, bitsize, bitnum,
1074 &bitnum);
1075 gcc_assert (bitnum + bitsize <= GET_MODE_BITSIZE (int_mode));
1076 temp = copy_to_reg (str_rtx);
1077 if (!store_bit_field_1 (temp, bitsize, bitnum, 0, 0,
1078 int_mode, value, reverse, true))
1079 gcc_unreachable ();
1081 emit_move_insn (str_rtx, temp);
1084 return;
1087 /* Under the C++0x memory model, we must not touch bits outside the
1088 bit region. Adjust the address to start at the beginning of the
1089 bit region. */
1090 if (MEM_P (str_rtx) && bitregion_start > 0)
1092 scalar_int_mode best_mode;
1093 machine_mode addr_mode = VOIDmode;
1094 HOST_WIDE_INT offset, size;
1096 gcc_assert ((bitregion_start % BITS_PER_UNIT) == 0);
1098 offset = bitregion_start / BITS_PER_UNIT;
1099 bitnum -= bitregion_start;
1100 size = (bitnum + bitsize + BITS_PER_UNIT - 1) / BITS_PER_UNIT;
1101 bitregion_end -= bitregion_start;
1102 bitregion_start = 0;
1103 if (get_best_mode (bitsize, bitnum,
1104 bitregion_start, bitregion_end,
1105 MEM_ALIGN (str_rtx), INT_MAX,
1106 MEM_VOLATILE_P (str_rtx), &best_mode))
1107 addr_mode = best_mode;
1108 str_rtx = adjust_bitfield_address_size (str_rtx, addr_mode,
1109 offset, size);
1112 if (!store_bit_field_1 (str_rtx, bitsize, bitnum,
1113 bitregion_start, bitregion_end,
1114 fieldmode, value, reverse, true))
1115 gcc_unreachable ();
1118 /* Use shifts and boolean operations to store VALUE into a bit field of
1119 width BITSIZE in OP0, starting at bit BITNUM. If OP0_MODE is defined,
1120 it is the mode of OP0, otherwise OP0 is a BLKmode MEM. VALUE_MODE is
1121 the mode of VALUE.
1123 If REVERSE is true, the store is to be done in reverse order. */
1125 static void
1126 store_fixed_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
1127 unsigned HOST_WIDE_INT bitsize,
1128 unsigned HOST_WIDE_INT bitnum,
1129 unsigned HOST_WIDE_INT bitregion_start,
1130 unsigned HOST_WIDE_INT bitregion_end,
1131 rtx value, scalar_int_mode value_mode, bool reverse)
1133 /* There is a case not handled here:
1134 a structure with a known alignment of just a halfword
1135 and a field split across two aligned halfwords within the structure.
1136 Or likewise a structure with a known alignment of just a byte
1137 and a field split across two bytes.
1138 Such cases are not supposed to be able to occur. */
1140 scalar_int_mode best_mode;
1141 if (MEM_P (op0))
1143 unsigned int max_bitsize = BITS_PER_WORD;
1144 scalar_int_mode imode;
1145 if (op0_mode.exists (&imode) && GET_MODE_BITSIZE (imode) < max_bitsize)
1146 max_bitsize = GET_MODE_BITSIZE (imode);
1148 if (!get_best_mode (bitsize, bitnum, bitregion_start, bitregion_end,
1149 MEM_ALIGN (op0), max_bitsize, MEM_VOLATILE_P (op0),
1150 &best_mode))
1152 /* The only way this should occur is if the field spans word
1153 boundaries. */
1154 store_split_bit_field (op0, op0_mode, bitsize, bitnum,
1155 bitregion_start, bitregion_end,
1156 value, value_mode, reverse);
1157 return;
1160 op0 = narrow_bit_field_mem (op0, best_mode, bitsize, bitnum, &bitnum);
1162 else
1163 best_mode = op0_mode.require ();
1165 store_fixed_bit_field_1 (op0, best_mode, bitsize, bitnum,
1166 value, value_mode, reverse);
1169 /* Helper function for store_fixed_bit_field, stores
1170 the bit field always using MODE, which is the mode of OP0. The other
1171 arguments are as for store_fixed_bit_field. */
1173 static void
1174 store_fixed_bit_field_1 (rtx op0, scalar_int_mode mode,
1175 unsigned HOST_WIDE_INT bitsize,
1176 unsigned HOST_WIDE_INT bitnum,
1177 rtx value, scalar_int_mode value_mode, bool reverse)
1179 rtx temp;
1180 int all_zero = 0;
1181 int all_one = 0;
1183 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1184 for invalid input, such as f5 from gcc.dg/pr48335-2.c. */
1186 if (reverse ? !BYTES_BIG_ENDIAN : BYTES_BIG_ENDIAN)
1187 /* BITNUM is the distance between our msb
1188 and that of the containing datum.
1189 Convert it to the distance from the lsb. */
1190 bitnum = GET_MODE_BITSIZE (mode) - bitsize - bitnum;
1192 /* Now BITNUM is always the distance between our lsb
1193 and that of OP0. */
1195 /* Shift VALUE left by BITNUM bits. If VALUE is not constant,
1196 we must first convert its mode to MODE. */
1198 if (CONST_INT_P (value))
1200 unsigned HOST_WIDE_INT v = UINTVAL (value);
1202 if (bitsize < HOST_BITS_PER_WIDE_INT)
1203 v &= (HOST_WIDE_INT_1U << bitsize) - 1;
1205 if (v == 0)
1206 all_zero = 1;
1207 else if ((bitsize < HOST_BITS_PER_WIDE_INT
1208 && v == (HOST_WIDE_INT_1U << bitsize) - 1)
1209 || (bitsize == HOST_BITS_PER_WIDE_INT
1210 && v == HOST_WIDE_INT_M1U))
1211 all_one = 1;
1213 value = lshift_value (mode, v, bitnum);
1215 else
1217 int must_and = (GET_MODE_BITSIZE (value_mode) != bitsize
1218 && bitnum + bitsize != GET_MODE_BITSIZE (mode));
1220 if (value_mode != mode)
1221 value = convert_to_mode (mode, value, 1);
1223 if (must_and)
1224 value = expand_binop (mode, and_optab, value,
1225 mask_rtx (mode, 0, bitsize, 0),
1226 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1227 if (bitnum > 0)
1228 value = expand_shift (LSHIFT_EXPR, mode, value,
1229 bitnum, NULL_RTX, 1);
1232 if (reverse)
1233 value = flip_storage_order (mode, value);
1235 /* Now clear the chosen bits in OP0,
1236 except that if VALUE is -1 we need not bother. */
1237 /* We keep the intermediates in registers to allow CSE to combine
1238 consecutive bitfield assignments. */
1240 temp = force_reg (mode, op0);
1242 if (! all_one)
1244 rtx mask = mask_rtx (mode, bitnum, bitsize, 1);
1245 if (reverse)
1246 mask = flip_storage_order (mode, mask);
1247 temp = expand_binop (mode, and_optab, temp, mask,
1248 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1249 temp = force_reg (mode, temp);
1252 /* Now logical-or VALUE into OP0, unless it is zero. */
1254 if (! all_zero)
1256 temp = expand_binop (mode, ior_optab, temp, value,
1257 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1258 temp = force_reg (mode, temp);
1261 if (op0 != temp)
1263 op0 = copy_rtx (op0);
1264 emit_move_insn (op0, temp);
1268 /* Store a bit field that is split across multiple accessible memory objects.
1270 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1271 BITSIZE is the field width; BITPOS the position of its first bit
1272 (within the word).
1273 VALUE is the value to store, which has mode VALUE_MODE.
1274 If OP0_MODE is defined, it is the mode of OP0, otherwise OP0 is
1275 a BLKmode MEM.
1277 If REVERSE is true, the store is to be done in reverse order.
1279 This does not yet handle fields wider than BITS_PER_WORD. */
1281 static void
1282 store_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
1283 unsigned HOST_WIDE_INT bitsize,
1284 unsigned HOST_WIDE_INT bitpos,
1285 unsigned HOST_WIDE_INT bitregion_start,
1286 unsigned HOST_WIDE_INT bitregion_end,
1287 rtx value, scalar_int_mode value_mode, bool reverse)
1289 unsigned int unit, total_bits, bitsdone = 0;
1291 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1292 much at a time. */
1293 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
1294 unit = BITS_PER_WORD;
1295 else
1296 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
1298 /* If OP0 is a memory with a mode, then UNIT must not be larger than
1299 OP0's mode as well. Otherwise, store_fixed_bit_field will call us
1300 again, and we will mutually recurse forever. */
1301 if (MEM_P (op0) && op0_mode.exists ())
1302 unit = MIN (unit, GET_MODE_BITSIZE (op0_mode.require ()));
1304 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1305 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1306 that VALUE might be a floating-point constant. */
1307 if (CONSTANT_P (value) && !CONST_INT_P (value))
1309 rtx word = gen_lowpart_common (word_mode, value);
1311 if (word && (value != word))
1312 value = word;
1313 else
1314 value = gen_lowpart_common (word_mode, force_reg (value_mode, value));
1315 value_mode = word_mode;
1318 total_bits = GET_MODE_BITSIZE (value_mode);
1320 while (bitsdone < bitsize)
1322 unsigned HOST_WIDE_INT thissize;
1323 unsigned HOST_WIDE_INT thispos;
1324 unsigned HOST_WIDE_INT offset;
1325 rtx part;
1327 offset = (bitpos + bitsdone) / unit;
1328 thispos = (bitpos + bitsdone) % unit;
1330 /* When region of bytes we can touch is restricted, decrease
1331 UNIT close to the end of the region as needed. If op0 is a REG
1332 or SUBREG of REG, don't do this, as there can't be data races
1333 on a register and we can expand shorter code in some cases. */
1334 if (bitregion_end
1335 && unit > BITS_PER_UNIT
1336 && bitpos + bitsdone - thispos + unit > bitregion_end + 1
1337 && !REG_P (op0)
1338 && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
1340 unit = unit / 2;
1341 continue;
1344 /* THISSIZE must not overrun a word boundary. Otherwise,
1345 store_fixed_bit_field will call us again, and we will mutually
1346 recurse forever. */
1347 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1348 thissize = MIN (thissize, unit - thispos);
1350 if (reverse ? !BYTES_BIG_ENDIAN : BYTES_BIG_ENDIAN)
1352 /* Fetch successively less significant portions. */
1353 if (CONST_INT_P (value))
1354 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
1355 >> (bitsize - bitsdone - thissize))
1356 & ((HOST_WIDE_INT_1 << thissize) - 1));
1357 /* Likewise, but the source is little-endian. */
1358 else if (reverse)
1359 part = extract_fixed_bit_field (word_mode, value, value_mode,
1360 thissize,
1361 bitsize - bitsdone - thissize,
1362 NULL_RTX, 1, false);
1363 else
1364 /* The args are chosen so that the last part includes the
1365 lsb. Give extract_bit_field the value it needs (with
1366 endianness compensation) to fetch the piece we want. */
1367 part = extract_fixed_bit_field (word_mode, value, value_mode,
1368 thissize,
1369 total_bits - bitsize + bitsdone,
1370 NULL_RTX, 1, false);
1372 else
1374 /* Fetch successively more significant portions. */
1375 if (CONST_INT_P (value))
1376 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
1377 >> bitsdone)
1378 & ((HOST_WIDE_INT_1 << thissize) - 1));
1379 /* Likewise, but the source is big-endian. */
1380 else if (reverse)
1381 part = extract_fixed_bit_field (word_mode, value, value_mode,
1382 thissize,
1383 total_bits - bitsdone - thissize,
1384 NULL_RTX, 1, false);
1385 else
1386 part = extract_fixed_bit_field (word_mode, value, value_mode,
1387 thissize, bitsdone, NULL_RTX,
1388 1, false);
1391 /* If OP0 is a register, then handle OFFSET here. */
1392 rtx op0_piece = op0;
1393 opt_scalar_int_mode op0_piece_mode = op0_mode;
1394 if (SUBREG_P (op0) || REG_P (op0))
1396 scalar_int_mode imode;
1397 if (op0_mode.exists (&imode)
1398 && GET_MODE_SIZE (imode) < UNITS_PER_WORD)
1400 if (offset)
1401 op0_piece = const0_rtx;
1403 else
1405 op0_piece = operand_subword_force (op0,
1406 offset * unit / BITS_PER_WORD,
1407 GET_MODE (op0));
1408 op0_piece_mode = word_mode;
1410 offset &= BITS_PER_WORD / unit - 1;
1413 /* OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
1414 it is just an out-of-bounds access. Ignore it. */
1415 if (op0_piece != const0_rtx)
1416 store_fixed_bit_field (op0_piece, op0_piece_mode, thissize,
1417 offset * unit + thispos, bitregion_start,
1418 bitregion_end, part, word_mode, reverse);
1419 bitsdone += thissize;
1423 /* A subroutine of extract_bit_field_1 that converts return value X
1424 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1425 to extract_bit_field. */
1427 static rtx
1428 convert_extracted_bit_field (rtx x, machine_mode mode,
1429 machine_mode tmode, bool unsignedp)
1431 if (GET_MODE (x) == tmode || GET_MODE (x) == mode)
1432 return x;
1434 /* If the x mode is not a scalar integral, first convert to the
1435 integer mode of that size and then access it as a floating-point
1436 value via a SUBREG. */
1437 if (!SCALAR_INT_MODE_P (tmode))
1439 scalar_int_mode int_mode = int_mode_for_mode (tmode).require ();
1440 x = convert_to_mode (int_mode, x, unsignedp);
1441 x = force_reg (int_mode, x);
1442 return gen_lowpart (tmode, x);
1445 return convert_to_mode (tmode, x, unsignedp);
1448 /* Try to use an ext(z)v pattern to extract a field from OP0.
1449 Return the extracted value on success, otherwise return null.
1450 EXTV describes the extraction instruction to use. If OP0_MODE
1451 is defined, it is the mode of OP0, otherwise OP0 is a BLKmode MEM.
1452 The other arguments are as for extract_bit_field. */
1454 static rtx
1455 extract_bit_field_using_extv (const extraction_insn *extv, rtx op0,
1456 opt_scalar_int_mode op0_mode,
1457 unsigned HOST_WIDE_INT bitsize,
1458 unsigned HOST_WIDE_INT bitnum,
1459 int unsignedp, rtx target,
1460 machine_mode mode, machine_mode tmode)
1462 struct expand_operand ops[4];
1463 rtx spec_target = target;
1464 rtx spec_target_subreg = 0;
1465 scalar_int_mode ext_mode = extv->field_mode;
1466 unsigned unit = GET_MODE_BITSIZE (ext_mode);
1468 if (bitsize == 0 || unit < bitsize)
1469 return NULL_RTX;
1471 if (MEM_P (op0))
1472 /* Get a reference to the first byte of the field. */
1473 op0 = narrow_bit_field_mem (op0, extv->struct_mode, bitsize, bitnum,
1474 &bitnum);
1475 else
1477 /* Convert from counting within OP0 to counting in EXT_MODE. */
1478 if (BYTES_BIG_ENDIAN)
1479 bitnum += unit - GET_MODE_BITSIZE (op0_mode.require ());
1481 /* If op0 is a register, we need it in EXT_MODE to make it
1482 acceptable to the format of ext(z)v. */
1483 if (GET_CODE (op0) == SUBREG && op0_mode.require () != ext_mode)
1484 return NULL_RTX;
1485 if (REG_P (op0) && op0_mode.require () != ext_mode)
1486 op0 = gen_lowpart_SUBREG (ext_mode, op0);
1489 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1490 "backwards" from the size of the unit we are extracting from.
1491 Otherwise, we count bits from the most significant on a
1492 BYTES/BITS_BIG_ENDIAN machine. */
1494 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1495 bitnum = unit - bitsize - bitnum;
1497 if (target == 0)
1498 target = spec_target = gen_reg_rtx (tmode);
1500 if (GET_MODE (target) != ext_mode)
1502 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1503 between the mode of the extraction (word_mode) and the target
1504 mode. Instead, create a temporary and use convert_move to set
1505 the target. */
1506 if (REG_P (target)
1507 && TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (target), ext_mode))
1509 target = gen_lowpart (ext_mode, target);
1510 if (partial_subreg_p (GET_MODE (spec_target), ext_mode))
1511 spec_target_subreg = target;
1513 else
1514 target = gen_reg_rtx (ext_mode);
1517 create_output_operand (&ops[0], target, ext_mode);
1518 create_fixed_operand (&ops[1], op0);
1519 create_integer_operand (&ops[2], bitsize);
1520 create_integer_operand (&ops[3], bitnum);
1521 if (maybe_expand_insn (extv->icode, 4, ops))
1523 target = ops[0].value;
1524 if (target == spec_target)
1525 return target;
1526 if (target == spec_target_subreg)
1527 return spec_target;
1528 return convert_extracted_bit_field (target, mode, tmode, unsignedp);
1530 return NULL_RTX;
1533 /* A subroutine of extract_bit_field, with the same arguments.
1534 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1535 if we can find no other means of implementing the operation.
1536 if FALLBACK_P is false, return NULL instead. */
1538 static rtx
1539 extract_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1540 unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target,
1541 machine_mode mode, machine_mode tmode,
1542 bool reverse, bool fallback_p, rtx *alt_rtl)
1544 rtx op0 = str_rtx;
1545 machine_mode mode1;
1547 if (tmode == VOIDmode)
1548 tmode = mode;
1550 while (GET_CODE (op0) == SUBREG)
1552 bitnum += SUBREG_BYTE (op0) * BITS_PER_UNIT;
1553 op0 = SUBREG_REG (op0);
1556 /* If we have an out-of-bounds access to a register, just return an
1557 uninitialized register of the required mode. This can occur if the
1558 source code contains an out-of-bounds access to a small array. */
1559 if (REG_P (op0) && bitnum >= GET_MODE_BITSIZE (GET_MODE (op0)))
1560 return gen_reg_rtx (tmode);
1562 if (REG_P (op0)
1563 && mode == GET_MODE (op0)
1564 && bitnum == 0
1565 && bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
1567 if (reverse)
1568 op0 = flip_storage_order (mode, op0);
1569 /* We're trying to extract a full register from itself. */
1570 return op0;
1573 /* First try to check for vector from vector extractions. */
1574 if (VECTOR_MODE_P (GET_MODE (op0))
1575 && !MEM_P (op0)
1576 && VECTOR_MODE_P (tmode)
1577 && GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (tmode))
1579 machine_mode new_mode = GET_MODE (op0);
1580 if (GET_MODE_INNER (new_mode) != GET_MODE_INNER (tmode))
1582 scalar_mode inner_mode = GET_MODE_INNER (tmode);
1583 unsigned int nunits = (GET_MODE_BITSIZE (GET_MODE (op0))
1584 / GET_MODE_UNIT_BITSIZE (tmode));
1585 if (!mode_for_vector (inner_mode, nunits).exists (&new_mode)
1586 || !VECTOR_MODE_P (new_mode)
1587 || GET_MODE_SIZE (new_mode) != GET_MODE_SIZE (GET_MODE (op0))
1588 || GET_MODE_INNER (new_mode) != GET_MODE_INNER (tmode)
1589 || !targetm.vector_mode_supported_p (new_mode))
1590 new_mode = VOIDmode;
1592 if (new_mode != VOIDmode
1593 && (convert_optab_handler (vec_extract_optab, new_mode, tmode)
1594 != CODE_FOR_nothing)
1595 && ((bitnum + bitsize - 1) / GET_MODE_BITSIZE (tmode)
1596 == bitnum / GET_MODE_BITSIZE (tmode)))
1598 struct expand_operand ops[3];
1599 machine_mode outermode = new_mode;
1600 machine_mode innermode = tmode;
1601 enum insn_code icode
1602 = convert_optab_handler (vec_extract_optab, outermode, innermode);
1603 unsigned HOST_WIDE_INT pos = bitnum / GET_MODE_BITSIZE (innermode);
1605 if (new_mode != GET_MODE (op0))
1606 op0 = gen_lowpart (new_mode, op0);
1607 create_output_operand (&ops[0], target, innermode);
1608 ops[0].target = 1;
1609 create_input_operand (&ops[1], op0, outermode);
1610 create_integer_operand (&ops[2], pos);
1611 if (maybe_expand_insn (icode, 3, ops))
1613 if (alt_rtl && ops[0].target)
1614 *alt_rtl = target;
1615 target = ops[0].value;
1616 if (GET_MODE (target) != mode)
1617 return gen_lowpart (tmode, target);
1618 return target;
1623 /* See if we can get a better vector mode before extracting. */
1624 if (VECTOR_MODE_P (GET_MODE (op0))
1625 && !MEM_P (op0)
1626 && GET_MODE_INNER (GET_MODE (op0)) != tmode)
1628 machine_mode new_mode;
1630 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1631 new_mode = MIN_MODE_VECTOR_FLOAT;
1632 else if (GET_MODE_CLASS (tmode) == MODE_FRACT)
1633 new_mode = MIN_MODE_VECTOR_FRACT;
1634 else if (GET_MODE_CLASS (tmode) == MODE_UFRACT)
1635 new_mode = MIN_MODE_VECTOR_UFRACT;
1636 else if (GET_MODE_CLASS (tmode) == MODE_ACCUM)
1637 new_mode = MIN_MODE_VECTOR_ACCUM;
1638 else if (GET_MODE_CLASS (tmode) == MODE_UACCUM)
1639 new_mode = MIN_MODE_VECTOR_UACCUM;
1640 else
1641 new_mode = MIN_MODE_VECTOR_INT;
1643 FOR_EACH_MODE_FROM (new_mode, new_mode)
1644 if (GET_MODE_SIZE (new_mode) == GET_MODE_SIZE (GET_MODE (op0))
1645 && GET_MODE_UNIT_SIZE (new_mode) == GET_MODE_SIZE (tmode)
1646 && targetm.vector_mode_supported_p (new_mode))
1647 break;
1648 if (new_mode != VOIDmode)
1649 op0 = gen_lowpart (new_mode, op0);
1652 /* Use vec_extract patterns for extracting parts of vectors whenever
1653 available. */
1654 machine_mode outermode = GET_MODE (op0);
1655 scalar_mode innermode = GET_MODE_INNER (outermode);
1656 if (VECTOR_MODE_P (outermode)
1657 && !MEM_P (op0)
1658 && (convert_optab_handler (vec_extract_optab, outermode, innermode)
1659 != CODE_FOR_nothing)
1660 && ((bitnum + bitsize - 1) / GET_MODE_BITSIZE (innermode)
1661 == bitnum / GET_MODE_BITSIZE (innermode)))
1663 struct expand_operand ops[3];
1664 enum insn_code icode
1665 = convert_optab_handler (vec_extract_optab, outermode, innermode);
1666 unsigned HOST_WIDE_INT pos = bitnum / GET_MODE_BITSIZE (innermode);
1668 create_output_operand (&ops[0], target, innermode);
1669 ops[0].target = 1;
1670 create_input_operand (&ops[1], op0, outermode);
1671 create_integer_operand (&ops[2], pos);
1672 if (maybe_expand_insn (icode, 3, ops))
1674 if (alt_rtl && ops[0].target)
1675 *alt_rtl = target;
1676 target = ops[0].value;
1677 if (GET_MODE (target) != mode)
1678 return gen_lowpart (tmode, target);
1679 return target;
1683 /* Make sure we are playing with integral modes. Pun with subregs
1684 if we aren't. */
1685 opt_scalar_int_mode op0_mode = int_mode_for_mode (GET_MODE (op0));
1686 scalar_int_mode imode;
1687 if (!op0_mode.exists (&imode) || imode != GET_MODE (op0))
1689 if (MEM_P (op0))
1690 op0 = adjust_bitfield_address_size (op0, op0_mode.else_blk (),
1691 0, MEM_SIZE (op0));
1692 else if (op0_mode.exists (&imode))
1694 op0 = gen_lowpart (imode, op0);
1696 /* If we got a SUBREG, force it into a register since we
1697 aren't going to be able to do another SUBREG on it. */
1698 if (GET_CODE (op0) == SUBREG)
1699 op0 = force_reg (imode, op0);
1701 else
1703 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (op0));
1704 rtx mem = assign_stack_temp (GET_MODE (op0), size);
1705 emit_move_insn (mem, op0);
1706 op0 = adjust_bitfield_address_size (mem, BLKmode, 0, size);
1710 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1711 If that's wrong, the solution is to test for it and set TARGET to 0
1712 if needed. */
1714 /* Get the mode of the field to use for atomic access or subreg
1715 conversion. */
1716 if (!SCALAR_INT_MODE_P (tmode)
1717 || !mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0).exists (&mode1))
1718 mode1 = mode;
1719 gcc_assert (mode1 != BLKmode);
1721 /* Extraction of a full MODE1 value can be done with a subreg as long
1722 as the least significant bit of the value is the least significant
1723 bit of either OP0 or a word of OP0. */
1724 if (!MEM_P (op0)
1725 && !reverse
1726 && lowpart_bit_field_p (bitnum, bitsize, op0_mode.require ())
1727 && bitsize == GET_MODE_BITSIZE (mode1)
1728 && TRULY_NOOP_TRUNCATION_MODES_P (mode1, op0_mode.require ()))
1730 rtx sub = simplify_gen_subreg (mode1, op0, op0_mode.require (),
1731 bitnum / BITS_PER_UNIT);
1732 if (sub)
1733 return convert_extracted_bit_field (sub, mode, tmode, unsignedp);
1736 /* Extraction of a full MODE1 value can be done with a load as long as
1737 the field is on a byte boundary and is sufficiently aligned. */
1738 if (simple_mem_bitfield_p (op0, bitsize, bitnum, mode1))
1740 op0 = adjust_bitfield_address (op0, mode1, bitnum / BITS_PER_UNIT);
1741 if (reverse)
1742 op0 = flip_storage_order (mode1, op0);
1743 return convert_extracted_bit_field (op0, mode, tmode, unsignedp);
1746 /* Handle fields bigger than a word. */
1748 if (bitsize > BITS_PER_WORD)
1750 /* Here we transfer the words of the field
1751 in the order least significant first.
1752 This is because the most significant word is the one which may
1753 be less than full. */
1755 const bool backwards = WORDS_BIG_ENDIAN;
1756 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
1757 unsigned int i;
1758 rtx_insn *last;
1760 if (target == 0 || !REG_P (target) || !valid_multiword_target_p (target))
1761 target = gen_reg_rtx (mode);
1763 /* In case we're about to clobber a base register or something
1764 (see gcc.c-torture/execute/20040625-1.c). */
1765 if (reg_mentioned_p (target, str_rtx))
1766 target = gen_reg_rtx (mode);
1768 /* Indicate for flow that the entire target reg is being set. */
1769 emit_clobber (target);
1771 last = get_last_insn ();
1772 for (i = 0; i < nwords; i++)
1774 /* If I is 0, use the low-order word in both field and target;
1775 if I is 1, use the next to lowest word; and so on. */
1776 /* Word number in TARGET to use. */
1777 unsigned int wordnum
1778 = (backwards
1779 ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1
1780 : i);
1781 /* Offset from start of field in OP0. */
1782 unsigned int bit_offset = (backwards ^ reverse
1783 ? MAX ((int) bitsize - ((int) i + 1)
1784 * BITS_PER_WORD,
1786 : (int) i * BITS_PER_WORD);
1787 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1788 rtx result_part
1789 = extract_bit_field_1 (op0, MIN (BITS_PER_WORD,
1790 bitsize - i * BITS_PER_WORD),
1791 bitnum + bit_offset, 1, target_part,
1792 mode, word_mode, reverse, fallback_p, NULL);
1794 gcc_assert (target_part);
1795 if (!result_part)
1797 delete_insns_since (last);
1798 return NULL;
1801 if (result_part != target_part)
1802 emit_move_insn (target_part, result_part);
1805 if (unsignedp)
1807 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1808 need to be zero'd out. */
1809 if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD)
1811 unsigned int i, total_words;
1813 total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD;
1814 for (i = nwords; i < total_words; i++)
1815 emit_move_insn
1816 (operand_subword (target,
1817 backwards ? total_words - i - 1 : i,
1818 1, VOIDmode),
1819 const0_rtx);
1821 return target;
1824 /* Signed bit field: sign-extend with two arithmetic shifts. */
1825 target = expand_shift (LSHIFT_EXPR, mode, target,
1826 GET_MODE_BITSIZE (mode) - bitsize, NULL_RTX, 0);
1827 return expand_shift (RSHIFT_EXPR, mode, target,
1828 GET_MODE_BITSIZE (mode) - bitsize, NULL_RTX, 0);
1831 /* If OP0 is a multi-word register, narrow it to the affected word.
1832 If the region spans two words, defer to extract_split_bit_field. */
1833 if (!MEM_P (op0) && GET_MODE_SIZE (op0_mode.require ()) > UNITS_PER_WORD)
1835 if (bitnum % BITS_PER_WORD + bitsize > BITS_PER_WORD)
1837 if (!fallback_p)
1838 return NULL_RTX;
1839 target = extract_split_bit_field (op0, op0_mode, bitsize, bitnum,
1840 unsignedp, reverse);
1841 return convert_extracted_bit_field (target, mode, tmode, unsignedp);
1843 op0 = simplify_gen_subreg (word_mode, op0, op0_mode.require (),
1844 bitnum / BITS_PER_WORD * UNITS_PER_WORD);
1845 op0_mode = word_mode;
1846 bitnum %= BITS_PER_WORD;
1849 /* From here on we know the desired field is smaller than a word.
1850 If OP0 is a register, it too fits within a word. */
1851 enum extraction_pattern pattern = unsignedp ? EP_extzv : EP_extv;
1852 extraction_insn extv;
1853 if (!MEM_P (op0)
1854 && !reverse
1855 /* ??? We could limit the structure size to the part of OP0 that
1856 contains the field, with appropriate checks for endianness
1857 and TARGET_TRULY_NOOP_TRUNCATION. */
1858 && get_best_reg_extraction_insn (&extv, pattern,
1859 GET_MODE_BITSIZE (op0_mode.require ()),
1860 tmode))
1862 rtx result = extract_bit_field_using_extv (&extv, op0, op0_mode,
1863 bitsize, bitnum,
1864 unsignedp, target, mode,
1865 tmode);
1866 if (result)
1867 return result;
1870 /* If OP0 is a memory, try copying it to a register and seeing if a
1871 cheap register alternative is available. */
1872 if (MEM_P (op0) & !reverse)
1874 if (get_best_mem_extraction_insn (&extv, pattern, bitsize, bitnum,
1875 tmode))
1877 rtx result = extract_bit_field_using_extv (&extv, op0, op0_mode,
1878 bitsize, bitnum,
1879 unsignedp, target, mode,
1880 tmode);
1881 if (result)
1882 return result;
1885 rtx_insn *last = get_last_insn ();
1887 /* Try loading part of OP0 into a register and extracting the
1888 bitfield from that. */
1889 unsigned HOST_WIDE_INT bitpos;
1890 rtx xop0 = adjust_bit_field_mem_for_reg (pattern, op0, bitsize, bitnum,
1891 0, 0, tmode, &bitpos);
1892 if (xop0)
1894 xop0 = copy_to_reg (xop0);
1895 rtx result = extract_bit_field_1 (xop0, bitsize, bitpos,
1896 unsignedp, target,
1897 mode, tmode, reverse, false, NULL);
1898 if (result)
1899 return result;
1900 delete_insns_since (last);
1904 if (!fallback_p)
1905 return NULL;
1907 /* Find a correspondingly-sized integer field, so we can apply
1908 shifts and masks to it. */
1909 scalar_int_mode int_mode;
1910 if (!int_mode_for_mode (tmode).exists (&int_mode))
1911 /* If this fails, we should probably push op0 out to memory and then
1912 do a load. */
1913 int_mode = int_mode_for_mode (mode).require ();
1915 target = extract_fixed_bit_field (int_mode, op0, op0_mode, bitsize,
1916 bitnum, target, unsignedp, reverse);
1918 /* Complex values must be reversed piecewise, so we need to undo the global
1919 reversal, convert to the complex mode and reverse again. */
1920 if (reverse && COMPLEX_MODE_P (tmode))
1922 target = flip_storage_order (int_mode, target);
1923 target = convert_extracted_bit_field (target, mode, tmode, unsignedp);
1924 target = flip_storage_order (tmode, target);
1926 else
1927 target = convert_extracted_bit_field (target, mode, tmode, unsignedp);
1929 return target;
1932 /* Generate code to extract a byte-field from STR_RTX
1933 containing BITSIZE bits, starting at BITNUM,
1934 and put it in TARGET if possible (if TARGET is nonzero).
1935 Regardless of TARGET, we return the rtx for where the value is placed.
1937 STR_RTX is the structure containing the byte (a REG or MEM).
1938 UNSIGNEDP is nonzero if this is an unsigned bit field.
1939 MODE is the natural mode of the field value once extracted.
1940 TMODE is the mode the caller would like the value to have;
1941 but the value may be returned with type MODE instead.
1943 If REVERSE is true, the extraction is to be done in reverse order.
1945 If a TARGET is specified and we can store in it at no extra cost,
1946 we do so, and return TARGET.
1947 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1948 if they are equally easy. */
1951 extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1952 unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target,
1953 machine_mode mode, machine_mode tmode, bool reverse,
1954 rtx *alt_rtl)
1956 machine_mode mode1;
1958 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
1959 if (GET_MODE_BITSIZE (GET_MODE (str_rtx)) > 0)
1960 mode1 = GET_MODE (str_rtx);
1961 else if (target && GET_MODE_BITSIZE (GET_MODE (target)) > 0)
1962 mode1 = GET_MODE (target);
1963 else
1964 mode1 = tmode;
1966 scalar_int_mode int_mode;
1967 if (is_a <scalar_int_mode> (mode1, &int_mode)
1968 && strict_volatile_bitfield_p (str_rtx, bitsize, bitnum, int_mode, 0, 0))
1970 /* Extraction of a full INT_MODE value can be done with a simple load.
1971 We know here that the field can be accessed with one single
1972 instruction. For targets that support unaligned memory,
1973 an unaligned access may be necessary. */
1974 if (bitsize == GET_MODE_BITSIZE (int_mode))
1976 rtx result = adjust_bitfield_address (str_rtx, int_mode,
1977 bitnum / BITS_PER_UNIT);
1978 if (reverse)
1979 result = flip_storage_order (int_mode, result);
1980 gcc_assert (bitnum % BITS_PER_UNIT == 0);
1981 return convert_extracted_bit_field (result, mode, tmode, unsignedp);
1984 str_rtx = narrow_bit_field_mem (str_rtx, int_mode, bitsize, bitnum,
1985 &bitnum);
1986 gcc_assert (bitnum + bitsize <= GET_MODE_BITSIZE (int_mode));
1987 str_rtx = copy_to_reg (str_rtx);
1990 return extract_bit_field_1 (str_rtx, bitsize, bitnum, unsignedp,
1991 target, mode, tmode, reverse, true, alt_rtl);
1994 /* Use shifts and boolean operations to extract a field of BITSIZE bits
1995 from bit BITNUM of OP0. If OP0_MODE is defined, it is the mode of OP0,
1996 otherwise OP0 is a BLKmode MEM.
1998 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1999 If REVERSE is true, the extraction is to be done in reverse order.
2001 If TARGET is nonzero, attempts to store the value there
2002 and return TARGET, but this is not guaranteed.
2003 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
2005 static rtx
2006 extract_fixed_bit_field (machine_mode tmode, rtx op0,
2007 opt_scalar_int_mode op0_mode,
2008 unsigned HOST_WIDE_INT bitsize,
2009 unsigned HOST_WIDE_INT bitnum, rtx target,
2010 int unsignedp, bool reverse)
2012 scalar_int_mode mode;
2013 if (MEM_P (op0))
2015 if (!get_best_mode (bitsize, bitnum, 0, 0, MEM_ALIGN (op0),
2016 BITS_PER_WORD, MEM_VOLATILE_P (op0), &mode))
2017 /* The only way this should occur is if the field spans word
2018 boundaries. */
2019 return extract_split_bit_field (op0, op0_mode, bitsize, bitnum,
2020 unsignedp, reverse);
2022 op0 = narrow_bit_field_mem (op0, mode, bitsize, bitnum, &bitnum);
2024 else
2025 mode = op0_mode.require ();
2027 return extract_fixed_bit_field_1 (tmode, op0, mode, bitsize, bitnum,
2028 target, unsignedp, reverse);
2031 /* Helper function for extract_fixed_bit_field, extracts
2032 the bit field always using MODE, which is the mode of OP0.
2033 The other arguments are as for extract_fixed_bit_field. */
2035 static rtx
2036 extract_fixed_bit_field_1 (machine_mode tmode, rtx op0, scalar_int_mode mode,
2037 unsigned HOST_WIDE_INT bitsize,
2038 unsigned HOST_WIDE_INT bitnum, rtx target,
2039 int unsignedp, bool reverse)
2041 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
2042 for invalid input, such as extract equivalent of f5 from
2043 gcc.dg/pr48335-2.c. */
2045 if (reverse ? !BYTES_BIG_ENDIAN : BYTES_BIG_ENDIAN)
2046 /* BITNUM is the distance between our msb and that of OP0.
2047 Convert it to the distance from the lsb. */
2048 bitnum = GET_MODE_BITSIZE (mode) - bitsize - bitnum;
2050 /* Now BITNUM is always the distance between the field's lsb and that of OP0.
2051 We have reduced the big-endian case to the little-endian case. */
2052 if (reverse)
2053 op0 = flip_storage_order (mode, op0);
2055 if (unsignedp)
2057 if (bitnum)
2059 /* If the field does not already start at the lsb,
2060 shift it so it does. */
2061 /* Maybe propagate the target for the shift. */
2062 rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
2063 if (tmode != mode)
2064 subtarget = 0;
2065 op0 = expand_shift (RSHIFT_EXPR, mode, op0, bitnum, subtarget, 1);
2067 /* Convert the value to the desired mode. TMODE must also be a
2068 scalar integer for this conversion to make sense, since we
2069 shouldn't reinterpret the bits. */
2070 scalar_int_mode new_mode = as_a <scalar_int_mode> (tmode);
2071 if (mode != new_mode)
2072 op0 = convert_to_mode (new_mode, op0, 1);
2074 /* Unless the msb of the field used to be the msb when we shifted,
2075 mask out the upper bits. */
2077 if (GET_MODE_BITSIZE (mode) != bitnum + bitsize)
2078 return expand_binop (new_mode, and_optab, op0,
2079 mask_rtx (new_mode, 0, bitsize, 0),
2080 target, 1, OPTAB_LIB_WIDEN);
2081 return op0;
2084 /* To extract a signed bit-field, first shift its msb to the msb of the word,
2085 then arithmetic-shift its lsb to the lsb of the word. */
2086 op0 = force_reg (mode, op0);
2088 /* Find the narrowest integer mode that contains the field. */
2090 opt_scalar_int_mode mode_iter;
2091 FOR_EACH_MODE_IN_CLASS (mode_iter, MODE_INT)
2092 if (GET_MODE_BITSIZE (mode_iter.require ()) >= bitsize + bitnum)
2093 break;
2095 mode = mode_iter.require ();
2096 op0 = convert_to_mode (mode, op0, 0);
2098 if (mode != tmode)
2099 target = 0;
2101 if (GET_MODE_BITSIZE (mode) != (bitsize + bitnum))
2103 int amount = GET_MODE_BITSIZE (mode) - (bitsize + bitnum);
2104 /* Maybe propagate the target for the shift. */
2105 rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
2106 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
2109 return expand_shift (RSHIFT_EXPR, mode, op0,
2110 GET_MODE_BITSIZE (mode) - bitsize, target, 0);
2113 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
2114 VALUE << BITPOS. */
2116 static rtx
2117 lshift_value (machine_mode mode, unsigned HOST_WIDE_INT value,
2118 int bitpos)
2120 return immed_wide_int_const (wi::lshift (value, bitpos), mode);
2123 /* Extract a bit field that is split across two words
2124 and return an RTX for the result.
2126 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
2127 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
2128 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
2129 If OP0_MODE is defined, it is the mode of OP0, otherwise OP0 is
2130 a BLKmode MEM.
2132 If REVERSE is true, the extraction is to be done in reverse order. */
2134 static rtx
2135 extract_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
2136 unsigned HOST_WIDE_INT bitsize,
2137 unsigned HOST_WIDE_INT bitpos, int unsignedp,
2138 bool reverse)
2140 unsigned int unit;
2141 unsigned int bitsdone = 0;
2142 rtx result = NULL_RTX;
2143 int first = 1;
2145 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
2146 much at a time. */
2147 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
2148 unit = BITS_PER_WORD;
2149 else
2150 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
2152 while (bitsdone < bitsize)
2154 unsigned HOST_WIDE_INT thissize;
2155 rtx part;
2156 unsigned HOST_WIDE_INT thispos;
2157 unsigned HOST_WIDE_INT offset;
2159 offset = (bitpos + bitsdone) / unit;
2160 thispos = (bitpos + bitsdone) % unit;
2162 /* THISSIZE must not overrun a word boundary. Otherwise,
2163 extract_fixed_bit_field will call us again, and we will mutually
2164 recurse forever. */
2165 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
2166 thissize = MIN (thissize, unit - thispos);
2168 /* If OP0 is a register, then handle OFFSET here. */
2169 rtx op0_piece = op0;
2170 opt_scalar_int_mode op0_piece_mode = op0_mode;
2171 if (SUBREG_P (op0) || REG_P (op0))
2173 op0_piece = operand_subword_force (op0, offset, op0_mode.require ());
2174 op0_piece_mode = word_mode;
2175 offset = 0;
2178 /* Extract the parts in bit-counting order,
2179 whose meaning is determined by BYTES_PER_UNIT.
2180 OFFSET is in UNITs, and UNIT is in bits. */
2181 part = extract_fixed_bit_field (word_mode, op0_piece, op0_piece_mode,
2182 thissize, offset * unit + thispos,
2183 0, 1, reverse);
2184 bitsdone += thissize;
2186 /* Shift this part into place for the result. */
2187 if (reverse ? !BYTES_BIG_ENDIAN : BYTES_BIG_ENDIAN)
2189 if (bitsize != bitsdone)
2190 part = expand_shift (LSHIFT_EXPR, word_mode, part,
2191 bitsize - bitsdone, 0, 1);
2193 else
2195 if (bitsdone != thissize)
2196 part = expand_shift (LSHIFT_EXPR, word_mode, part,
2197 bitsdone - thissize, 0, 1);
2200 if (first)
2201 result = part;
2202 else
2203 /* Combine the parts with bitwise or. This works
2204 because we extracted each part as an unsigned bit field. */
2205 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
2206 OPTAB_LIB_WIDEN);
2208 first = 0;
2211 /* Unsigned bit field: we are done. */
2212 if (unsignedp)
2213 return result;
2214 /* Signed bit field: sign-extend with two arithmetic shifts. */
2215 result = expand_shift (LSHIFT_EXPR, word_mode, result,
2216 BITS_PER_WORD - bitsize, NULL_RTX, 0);
2217 return expand_shift (RSHIFT_EXPR, word_mode, result,
2218 BITS_PER_WORD - bitsize, NULL_RTX, 0);
2221 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
2222 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
2223 MODE, fill the upper bits with zeros. Fail if the layout of either
2224 mode is unknown (as for CC modes) or if the extraction would involve
2225 unprofitable mode punning. Return the value on success, otherwise
2226 return null.
2228 This is different from gen_lowpart* in these respects:
2230 - the returned value must always be considered an rvalue
2232 - when MODE is wider than SRC_MODE, the extraction involves
2233 a zero extension
2235 - when MODE is smaller than SRC_MODE, the extraction involves
2236 a truncation (and is thus subject to TARGET_TRULY_NOOP_TRUNCATION).
2238 In other words, this routine performs a computation, whereas the
2239 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2240 operations. */
2243 extract_low_bits (machine_mode mode, machine_mode src_mode, rtx src)
2245 scalar_int_mode int_mode, src_int_mode;
2247 if (mode == src_mode)
2248 return src;
2250 if (CONSTANT_P (src))
2252 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2253 fails, it will happily create (subreg (symbol_ref)) or similar
2254 invalid SUBREGs. */
2255 unsigned int byte = subreg_lowpart_offset (mode, src_mode);
2256 rtx ret = simplify_subreg (mode, src, src_mode, byte);
2257 if (ret)
2258 return ret;
2260 if (GET_MODE (src) == VOIDmode
2261 || !validate_subreg (mode, src_mode, src, byte))
2262 return NULL_RTX;
2264 src = force_reg (GET_MODE (src), src);
2265 return gen_rtx_SUBREG (mode, src, byte);
2268 if (GET_MODE_CLASS (mode) == MODE_CC || GET_MODE_CLASS (src_mode) == MODE_CC)
2269 return NULL_RTX;
2271 if (GET_MODE_BITSIZE (mode) == GET_MODE_BITSIZE (src_mode)
2272 && targetm.modes_tieable_p (mode, src_mode))
2274 rtx x = gen_lowpart_common (mode, src);
2275 if (x)
2276 return x;
2279 if (!int_mode_for_mode (src_mode).exists (&src_int_mode)
2280 || !int_mode_for_mode (mode).exists (&int_mode))
2281 return NULL_RTX;
2283 if (!targetm.modes_tieable_p (src_int_mode, src_mode))
2284 return NULL_RTX;
2285 if (!targetm.modes_tieable_p (int_mode, mode))
2286 return NULL_RTX;
2288 src = gen_lowpart (src_int_mode, src);
2289 src = convert_modes (int_mode, src_int_mode, src, true);
2290 src = gen_lowpart (mode, src);
2291 return src;
2294 /* Add INC into TARGET. */
2296 void
2297 expand_inc (rtx target, rtx inc)
2299 rtx value = expand_binop (GET_MODE (target), add_optab,
2300 target, inc,
2301 target, 0, OPTAB_LIB_WIDEN);
2302 if (value != target)
2303 emit_move_insn (target, value);
2306 /* Subtract DEC from TARGET. */
2308 void
2309 expand_dec (rtx target, rtx dec)
2311 rtx value = expand_binop (GET_MODE (target), sub_optab,
2312 target, dec,
2313 target, 0, OPTAB_LIB_WIDEN);
2314 if (value != target)
2315 emit_move_insn (target, value);
2318 /* Output a shift instruction for expression code CODE,
2319 with SHIFTED being the rtx for the value to shift,
2320 and AMOUNT the rtx for the amount to shift by.
2321 Store the result in the rtx TARGET, if that is convenient.
2322 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2323 Return the rtx for where the value is.
2324 If that cannot be done, abort the compilation unless MAY_FAIL is true,
2325 in which case 0 is returned. */
2327 static rtx
2328 expand_shift_1 (enum tree_code code, machine_mode mode, rtx shifted,
2329 rtx amount, rtx target, int unsignedp, bool may_fail = false)
2331 rtx op1, temp = 0;
2332 int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
2333 int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
2334 optab lshift_optab = ashl_optab;
2335 optab rshift_arith_optab = ashr_optab;
2336 optab rshift_uns_optab = lshr_optab;
2337 optab lrotate_optab = rotl_optab;
2338 optab rrotate_optab = rotr_optab;
2339 machine_mode op1_mode;
2340 machine_mode scalar_mode = mode;
2341 int attempt;
2342 bool speed = optimize_insn_for_speed_p ();
2344 if (VECTOR_MODE_P (mode))
2345 scalar_mode = GET_MODE_INNER (mode);
2346 op1 = amount;
2347 op1_mode = GET_MODE (op1);
2349 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2350 shift amount is a vector, use the vector/vector shift patterns. */
2351 if (VECTOR_MODE_P (mode) && VECTOR_MODE_P (op1_mode))
2353 lshift_optab = vashl_optab;
2354 rshift_arith_optab = vashr_optab;
2355 rshift_uns_optab = vlshr_optab;
2356 lrotate_optab = vrotl_optab;
2357 rrotate_optab = vrotr_optab;
2360 /* Previously detected shift-counts computed by NEGATE_EXPR
2361 and shifted in the other direction; but that does not work
2362 on all machines. */
2364 if (SHIFT_COUNT_TRUNCATED)
2366 if (CONST_INT_P (op1)
2367 && ((unsigned HOST_WIDE_INT) INTVAL (op1) >=
2368 (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (scalar_mode)))
2369 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
2370 % GET_MODE_BITSIZE (scalar_mode));
2371 else if (GET_CODE (op1) == SUBREG
2372 && subreg_lowpart_p (op1)
2373 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op1)))
2374 && SCALAR_INT_MODE_P (GET_MODE (op1)))
2375 op1 = SUBREG_REG (op1);
2378 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
2379 prefer left rotation, if op1 is from bitsize / 2 + 1 to
2380 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
2381 amount instead. */
2382 if (rotate
2383 && CONST_INT_P (op1)
2384 && IN_RANGE (INTVAL (op1), GET_MODE_BITSIZE (scalar_mode) / 2 + left,
2385 GET_MODE_BITSIZE (scalar_mode) - 1))
2387 op1 = GEN_INT (GET_MODE_BITSIZE (scalar_mode) - INTVAL (op1));
2388 left = !left;
2389 code = left ? LROTATE_EXPR : RROTATE_EXPR;
2392 /* Rotation of 16bit values by 8 bits is effectively equivalent to a bswaphi.
2393 Note that this is not the case for bigger values. For instance a rotation
2394 of 0x01020304 by 16 bits gives 0x03040102 which is different from
2395 0x04030201 (bswapsi). */
2396 if (rotate
2397 && CONST_INT_P (op1)
2398 && INTVAL (op1) == BITS_PER_UNIT
2399 && GET_MODE_SIZE (scalar_mode) == 2
2400 && optab_handler (bswap_optab, HImode) != CODE_FOR_nothing)
2401 return expand_unop (HImode, bswap_optab, shifted, NULL_RTX,
2402 unsignedp);
2404 if (op1 == const0_rtx)
2405 return shifted;
2407 /* Check whether its cheaper to implement a left shift by a constant
2408 bit count by a sequence of additions. */
2409 if (code == LSHIFT_EXPR
2410 && CONST_INT_P (op1)
2411 && INTVAL (op1) > 0
2412 && INTVAL (op1) < GET_MODE_PRECISION (scalar_mode)
2413 && INTVAL (op1) < MAX_BITS_PER_WORD
2414 && (shift_cost (speed, mode, INTVAL (op1))
2415 > INTVAL (op1) * add_cost (speed, mode))
2416 && shift_cost (speed, mode, INTVAL (op1)) != MAX_COST)
2418 int i;
2419 for (i = 0; i < INTVAL (op1); i++)
2421 temp = force_reg (mode, shifted);
2422 shifted = expand_binop (mode, add_optab, temp, temp, NULL_RTX,
2423 unsignedp, OPTAB_LIB_WIDEN);
2425 return shifted;
2428 for (attempt = 0; temp == 0 && attempt < 3; attempt++)
2430 enum optab_methods methods;
2432 if (attempt == 0)
2433 methods = OPTAB_DIRECT;
2434 else if (attempt == 1)
2435 methods = OPTAB_WIDEN;
2436 else
2437 methods = OPTAB_LIB_WIDEN;
2439 if (rotate)
2441 /* Widening does not work for rotation. */
2442 if (methods == OPTAB_WIDEN)
2443 continue;
2444 else if (methods == OPTAB_LIB_WIDEN)
2446 /* If we have been unable to open-code this by a rotation,
2447 do it as the IOR of two shifts. I.e., to rotate A
2448 by N bits, compute
2449 (A << N) | ((unsigned) A >> ((-N) & (C - 1)))
2450 where C is the bitsize of A.
2452 It is theoretically possible that the target machine might
2453 not be able to perform either shift and hence we would
2454 be making two libcalls rather than just the one for the
2455 shift (similarly if IOR could not be done). We will allow
2456 this extremely unlikely lossage to avoid complicating the
2457 code below. */
2459 rtx subtarget = target == shifted ? 0 : target;
2460 rtx new_amount, other_amount;
2461 rtx temp1;
2463 new_amount = op1;
2464 if (op1 == const0_rtx)
2465 return shifted;
2466 else if (CONST_INT_P (op1))
2467 other_amount = GEN_INT (GET_MODE_BITSIZE (scalar_mode)
2468 - INTVAL (op1));
2469 else
2471 other_amount
2472 = simplify_gen_unary (NEG, GET_MODE (op1),
2473 op1, GET_MODE (op1));
2474 HOST_WIDE_INT mask = GET_MODE_PRECISION (scalar_mode) - 1;
2475 other_amount
2476 = simplify_gen_binary (AND, GET_MODE (op1), other_amount,
2477 gen_int_mode (mask, GET_MODE (op1)));
2480 shifted = force_reg (mode, shifted);
2482 temp = expand_shift_1 (left ? LSHIFT_EXPR : RSHIFT_EXPR,
2483 mode, shifted, new_amount, 0, 1);
2484 temp1 = expand_shift_1 (left ? RSHIFT_EXPR : LSHIFT_EXPR,
2485 mode, shifted, other_amount,
2486 subtarget, 1);
2487 return expand_binop (mode, ior_optab, temp, temp1, target,
2488 unsignedp, methods);
2491 temp = expand_binop (mode,
2492 left ? lrotate_optab : rrotate_optab,
2493 shifted, op1, target, unsignedp, methods);
2495 else if (unsignedp)
2496 temp = expand_binop (mode,
2497 left ? lshift_optab : rshift_uns_optab,
2498 shifted, op1, target, unsignedp, methods);
2500 /* Do arithmetic shifts.
2501 Also, if we are going to widen the operand, we can just as well
2502 use an arithmetic right-shift instead of a logical one. */
2503 if (temp == 0 && ! rotate
2504 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
2506 enum optab_methods methods1 = methods;
2508 /* If trying to widen a log shift to an arithmetic shift,
2509 don't accept an arithmetic shift of the same size. */
2510 if (unsignedp)
2511 methods1 = OPTAB_MUST_WIDEN;
2513 /* Arithmetic shift */
2515 temp = expand_binop (mode,
2516 left ? lshift_optab : rshift_arith_optab,
2517 shifted, op1, target, unsignedp, methods1);
2520 /* We used to try extzv here for logical right shifts, but that was
2521 only useful for one machine, the VAX, and caused poor code
2522 generation there for lshrdi3, so the code was deleted and a
2523 define_expand for lshrsi3 was added to vax.md. */
2526 gcc_assert (temp != NULL_RTX || may_fail);
2527 return temp;
2530 /* Output a shift instruction for expression code CODE,
2531 with SHIFTED being the rtx for the value to shift,
2532 and AMOUNT the amount to shift by.
2533 Store the result in the rtx TARGET, if that is convenient.
2534 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2535 Return the rtx for where the value is. */
2538 expand_shift (enum tree_code code, machine_mode mode, rtx shifted,
2539 int amount, rtx target, int unsignedp)
2541 return expand_shift_1 (code, mode,
2542 shifted, GEN_INT (amount), target, unsignedp);
2545 /* Likewise, but return 0 if that cannot be done. */
2547 static rtx
2548 maybe_expand_shift (enum tree_code code, machine_mode mode, rtx shifted,
2549 int amount, rtx target, int unsignedp)
2551 return expand_shift_1 (code, mode,
2552 shifted, GEN_INT (amount), target, unsignedp, true);
2555 /* Output a shift instruction for expression code CODE,
2556 with SHIFTED being the rtx for the value to shift,
2557 and AMOUNT the tree for the amount to shift by.
2558 Store the result in the rtx TARGET, if that is convenient.
2559 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2560 Return the rtx for where the value is. */
2563 expand_variable_shift (enum tree_code code, machine_mode mode, rtx shifted,
2564 tree amount, rtx target, int unsignedp)
2566 return expand_shift_1 (code, mode,
2567 shifted, expand_normal (amount), target, unsignedp);
2571 static void synth_mult (struct algorithm *, unsigned HOST_WIDE_INT,
2572 const struct mult_cost *, machine_mode mode);
2573 static rtx expand_mult_const (machine_mode, rtx, HOST_WIDE_INT, rtx,
2574 const struct algorithm *, enum mult_variant);
2575 static unsigned HOST_WIDE_INT invert_mod2n (unsigned HOST_WIDE_INT, int);
2576 static rtx extract_high_half (scalar_int_mode, rtx);
2577 static rtx expmed_mult_highpart (scalar_int_mode, rtx, rtx, rtx, int, int);
2578 static rtx expmed_mult_highpart_optab (scalar_int_mode, rtx, rtx, rtx,
2579 int, int);
2580 /* Compute and return the best algorithm for multiplying by T.
2581 The algorithm must cost less than cost_limit
2582 If retval.cost >= COST_LIMIT, no algorithm was found and all
2583 other field of the returned struct are undefined.
2584 MODE is the machine mode of the multiplication. */
2586 static void
2587 synth_mult (struct algorithm *alg_out, unsigned HOST_WIDE_INT t,
2588 const struct mult_cost *cost_limit, machine_mode mode)
2590 int m;
2591 struct algorithm *alg_in, *best_alg;
2592 struct mult_cost best_cost;
2593 struct mult_cost new_limit;
2594 int op_cost, op_latency;
2595 unsigned HOST_WIDE_INT orig_t = t;
2596 unsigned HOST_WIDE_INT q;
2597 int maxm, hash_index;
2598 bool cache_hit = false;
2599 enum alg_code cache_alg = alg_zero;
2600 bool speed = optimize_insn_for_speed_p ();
2601 scalar_int_mode imode;
2602 struct alg_hash_entry *entry_ptr;
2604 /* Indicate that no algorithm is yet found. If no algorithm
2605 is found, this value will be returned and indicate failure. */
2606 alg_out->cost.cost = cost_limit->cost + 1;
2607 alg_out->cost.latency = cost_limit->latency + 1;
2609 if (cost_limit->cost < 0
2610 || (cost_limit->cost == 0 && cost_limit->latency <= 0))
2611 return;
2613 /* Be prepared for vector modes. */
2614 imode = as_a <scalar_int_mode> (GET_MODE_INNER (mode));
2616 maxm = MIN (BITS_PER_WORD, GET_MODE_BITSIZE (imode));
2618 /* Restrict the bits of "t" to the multiplication's mode. */
2619 t &= GET_MODE_MASK (imode);
2621 /* t == 1 can be done in zero cost. */
2622 if (t == 1)
2624 alg_out->ops = 1;
2625 alg_out->cost.cost = 0;
2626 alg_out->cost.latency = 0;
2627 alg_out->op[0] = alg_m;
2628 return;
2631 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2632 fail now. */
2633 if (t == 0)
2635 if (MULT_COST_LESS (cost_limit, zero_cost (speed)))
2636 return;
2637 else
2639 alg_out->ops = 1;
2640 alg_out->cost.cost = zero_cost (speed);
2641 alg_out->cost.latency = zero_cost (speed);
2642 alg_out->op[0] = alg_zero;
2643 return;
2647 /* We'll be needing a couple extra algorithm structures now. */
2649 alg_in = XALLOCA (struct algorithm);
2650 best_alg = XALLOCA (struct algorithm);
2651 best_cost = *cost_limit;
2653 /* Compute the hash index. */
2654 hash_index = (t ^ (unsigned int) mode ^ (speed * 256)) % NUM_ALG_HASH_ENTRIES;
2656 /* See if we already know what to do for T. */
2657 entry_ptr = alg_hash_entry_ptr (hash_index);
2658 if (entry_ptr->t == t
2659 && entry_ptr->mode == mode
2660 && entry_ptr->speed == speed
2661 && entry_ptr->alg != alg_unknown)
2663 cache_alg = entry_ptr->alg;
2665 if (cache_alg == alg_impossible)
2667 /* The cache tells us that it's impossible to synthesize
2668 multiplication by T within entry_ptr->cost. */
2669 if (!CHEAPER_MULT_COST (&entry_ptr->cost, cost_limit))
2670 /* COST_LIMIT is at least as restrictive as the one
2671 recorded in the hash table, in which case we have no
2672 hope of synthesizing a multiplication. Just
2673 return. */
2674 return;
2676 /* If we get here, COST_LIMIT is less restrictive than the
2677 one recorded in the hash table, so we may be able to
2678 synthesize a multiplication. Proceed as if we didn't
2679 have the cache entry. */
2681 else
2683 if (CHEAPER_MULT_COST (cost_limit, &entry_ptr->cost))
2684 /* The cached algorithm shows that this multiplication
2685 requires more cost than COST_LIMIT. Just return. This
2686 way, we don't clobber this cache entry with
2687 alg_impossible but retain useful information. */
2688 return;
2690 cache_hit = true;
2692 switch (cache_alg)
2694 case alg_shift:
2695 goto do_alg_shift;
2697 case alg_add_t_m2:
2698 case alg_sub_t_m2:
2699 goto do_alg_addsub_t_m2;
2701 case alg_add_factor:
2702 case alg_sub_factor:
2703 goto do_alg_addsub_factor;
2705 case alg_add_t2_m:
2706 goto do_alg_add_t2_m;
2708 case alg_sub_t2_m:
2709 goto do_alg_sub_t2_m;
2711 default:
2712 gcc_unreachable ();
2717 /* If we have a group of zero bits at the low-order part of T, try
2718 multiplying by the remaining bits and then doing a shift. */
2720 if ((t & 1) == 0)
2722 do_alg_shift:
2723 m = ctz_or_zero (t); /* m = number of low zero bits */
2724 if (m < maxm)
2726 q = t >> m;
2727 /* The function expand_shift will choose between a shift and
2728 a sequence of additions, so the observed cost is given as
2729 MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). */
2730 op_cost = m * add_cost (speed, mode);
2731 if (shift_cost (speed, mode, m) < op_cost)
2732 op_cost = shift_cost (speed, mode, m);
2733 new_limit.cost = best_cost.cost - op_cost;
2734 new_limit.latency = best_cost.latency - op_cost;
2735 synth_mult (alg_in, q, &new_limit, mode);
2737 alg_in->cost.cost += op_cost;
2738 alg_in->cost.latency += op_cost;
2739 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2741 best_cost = alg_in->cost;
2742 std::swap (alg_in, best_alg);
2743 best_alg->log[best_alg->ops] = m;
2744 best_alg->op[best_alg->ops] = alg_shift;
2747 /* See if treating ORIG_T as a signed number yields a better
2748 sequence. Try this sequence only for a negative ORIG_T
2749 as it would be useless for a non-negative ORIG_T. */
2750 if ((HOST_WIDE_INT) orig_t < 0)
2752 /* Shift ORIG_T as follows because a right shift of a
2753 negative-valued signed type is implementation
2754 defined. */
2755 q = ~(~orig_t >> m);
2756 /* The function expand_shift will choose between a shift
2757 and a sequence of additions, so the observed cost is
2758 given as MIN (m * add_cost(speed, mode),
2759 shift_cost(speed, mode, m)). */
2760 op_cost = m * add_cost (speed, mode);
2761 if (shift_cost (speed, mode, m) < op_cost)
2762 op_cost = shift_cost (speed, mode, m);
2763 new_limit.cost = best_cost.cost - op_cost;
2764 new_limit.latency = best_cost.latency - op_cost;
2765 synth_mult (alg_in, q, &new_limit, mode);
2767 alg_in->cost.cost += op_cost;
2768 alg_in->cost.latency += op_cost;
2769 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2771 best_cost = alg_in->cost;
2772 std::swap (alg_in, best_alg);
2773 best_alg->log[best_alg->ops] = m;
2774 best_alg->op[best_alg->ops] = alg_shift;
2778 if (cache_hit)
2779 goto done;
2782 /* If we have an odd number, add or subtract one. */
2783 if ((t & 1) != 0)
2785 unsigned HOST_WIDE_INT w;
2787 do_alg_addsub_t_m2:
2788 for (w = 1; (w & t) != 0; w <<= 1)
2790 /* If T was -1, then W will be zero after the loop. This is another
2791 case where T ends with ...111. Handling this with (T + 1) and
2792 subtract 1 produces slightly better code and results in algorithm
2793 selection much faster than treating it like the ...0111 case
2794 below. */
2795 if (w == 0
2796 || (w > 2
2797 /* Reject the case where t is 3.
2798 Thus we prefer addition in that case. */
2799 && t != 3))
2801 /* T ends with ...111. Multiply by (T + 1) and subtract T. */
2803 op_cost = add_cost (speed, mode);
2804 new_limit.cost = best_cost.cost - op_cost;
2805 new_limit.latency = best_cost.latency - op_cost;
2806 synth_mult (alg_in, t + 1, &new_limit, mode);
2808 alg_in->cost.cost += op_cost;
2809 alg_in->cost.latency += op_cost;
2810 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2812 best_cost = alg_in->cost;
2813 std::swap (alg_in, best_alg);
2814 best_alg->log[best_alg->ops] = 0;
2815 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2818 else
2820 /* T ends with ...01 or ...011. Multiply by (T - 1) and add T. */
2822 op_cost = add_cost (speed, mode);
2823 new_limit.cost = best_cost.cost - op_cost;
2824 new_limit.latency = best_cost.latency - op_cost;
2825 synth_mult (alg_in, t - 1, &new_limit, mode);
2827 alg_in->cost.cost += op_cost;
2828 alg_in->cost.latency += op_cost;
2829 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2831 best_cost = alg_in->cost;
2832 std::swap (alg_in, best_alg);
2833 best_alg->log[best_alg->ops] = 0;
2834 best_alg->op[best_alg->ops] = alg_add_t_m2;
2838 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2839 quickly with a - a * n for some appropriate constant n. */
2840 m = exact_log2 (-orig_t + 1);
2841 if (m >= 0 && m < maxm)
2843 op_cost = add_cost (speed, mode) + shift_cost (speed, mode, m);
2844 /* If the target has a cheap shift-and-subtract insn use
2845 that in preference to a shift insn followed by a sub insn.
2846 Assume that the shift-and-sub is "atomic" with a latency
2847 equal to it's cost, otherwise assume that on superscalar
2848 hardware the shift may be executed concurrently with the
2849 earlier steps in the algorithm. */
2850 if (shiftsub1_cost (speed, mode, m) <= op_cost)
2852 op_cost = shiftsub1_cost (speed, mode, m);
2853 op_latency = op_cost;
2855 else
2856 op_latency = add_cost (speed, mode);
2858 new_limit.cost = best_cost.cost - op_cost;
2859 new_limit.latency = best_cost.latency - op_latency;
2860 synth_mult (alg_in, (unsigned HOST_WIDE_INT) (-orig_t + 1) >> m,
2861 &new_limit, mode);
2863 alg_in->cost.cost += op_cost;
2864 alg_in->cost.latency += op_latency;
2865 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2867 best_cost = alg_in->cost;
2868 std::swap (alg_in, best_alg);
2869 best_alg->log[best_alg->ops] = m;
2870 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2874 if (cache_hit)
2875 goto done;
2878 /* Look for factors of t of the form
2879 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2880 If we find such a factor, we can multiply by t using an algorithm that
2881 multiplies by q, shift the result by m and add/subtract it to itself.
2883 We search for large factors first and loop down, even if large factors
2884 are less probable than small; if we find a large factor we will find a
2885 good sequence quickly, and therefore be able to prune (by decreasing
2886 COST_LIMIT) the search. */
2888 do_alg_addsub_factor:
2889 for (m = floor_log2 (t - 1); m >= 2; m--)
2891 unsigned HOST_WIDE_INT d;
2893 d = (HOST_WIDE_INT_1U << m) + 1;
2894 if (t % d == 0 && t > d && m < maxm
2895 && (!cache_hit || cache_alg == alg_add_factor))
2897 op_cost = add_cost (speed, mode) + shift_cost (speed, mode, m);
2898 if (shiftadd_cost (speed, mode, m) <= op_cost)
2899 op_cost = shiftadd_cost (speed, mode, m);
2901 op_latency = op_cost;
2904 new_limit.cost = best_cost.cost - op_cost;
2905 new_limit.latency = best_cost.latency - op_latency;
2906 synth_mult (alg_in, t / d, &new_limit, mode);
2908 alg_in->cost.cost += op_cost;
2909 alg_in->cost.latency += op_latency;
2910 if (alg_in->cost.latency < op_cost)
2911 alg_in->cost.latency = op_cost;
2912 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2914 best_cost = alg_in->cost;
2915 std::swap (alg_in, best_alg);
2916 best_alg->log[best_alg->ops] = m;
2917 best_alg->op[best_alg->ops] = alg_add_factor;
2919 /* Other factors will have been taken care of in the recursion. */
2920 break;
2923 d = (HOST_WIDE_INT_1U << m) - 1;
2924 if (t % d == 0 && t > d && m < maxm
2925 && (!cache_hit || cache_alg == alg_sub_factor))
2927 op_cost = add_cost (speed, mode) + shift_cost (speed, mode, m);
2928 if (shiftsub0_cost (speed, mode, m) <= op_cost)
2929 op_cost = shiftsub0_cost (speed, mode, m);
2931 op_latency = op_cost;
2933 new_limit.cost = best_cost.cost - op_cost;
2934 new_limit.latency = best_cost.latency - op_latency;
2935 synth_mult (alg_in, t / d, &new_limit, mode);
2937 alg_in->cost.cost += op_cost;
2938 alg_in->cost.latency += op_latency;
2939 if (alg_in->cost.latency < op_cost)
2940 alg_in->cost.latency = op_cost;
2941 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2943 best_cost = alg_in->cost;
2944 std::swap (alg_in, best_alg);
2945 best_alg->log[best_alg->ops] = m;
2946 best_alg->op[best_alg->ops] = alg_sub_factor;
2948 break;
2951 if (cache_hit)
2952 goto done;
2954 /* Try shift-and-add (load effective address) instructions,
2955 i.e. do a*3, a*5, a*9. */
2956 if ((t & 1) != 0)
2958 do_alg_add_t2_m:
2959 q = t - 1;
2960 m = ctz_hwi (q);
2961 if (q && m < maxm)
2963 op_cost = shiftadd_cost (speed, mode, m);
2964 new_limit.cost = best_cost.cost - op_cost;
2965 new_limit.latency = best_cost.latency - op_cost;
2966 synth_mult (alg_in, (t - 1) >> m, &new_limit, mode);
2968 alg_in->cost.cost += op_cost;
2969 alg_in->cost.latency += op_cost;
2970 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2972 best_cost = alg_in->cost;
2973 std::swap (alg_in, best_alg);
2974 best_alg->log[best_alg->ops] = m;
2975 best_alg->op[best_alg->ops] = alg_add_t2_m;
2978 if (cache_hit)
2979 goto done;
2981 do_alg_sub_t2_m:
2982 q = t + 1;
2983 m = ctz_hwi (q);
2984 if (q && m < maxm)
2986 op_cost = shiftsub0_cost (speed, mode, m);
2987 new_limit.cost = best_cost.cost - op_cost;
2988 new_limit.latency = best_cost.latency - op_cost;
2989 synth_mult (alg_in, (t + 1) >> m, &new_limit, mode);
2991 alg_in->cost.cost += op_cost;
2992 alg_in->cost.latency += op_cost;
2993 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2995 best_cost = alg_in->cost;
2996 std::swap (alg_in, best_alg);
2997 best_alg->log[best_alg->ops] = m;
2998 best_alg->op[best_alg->ops] = alg_sub_t2_m;
3001 if (cache_hit)
3002 goto done;
3005 done:
3006 /* If best_cost has not decreased, we have not found any algorithm. */
3007 if (!CHEAPER_MULT_COST (&best_cost, cost_limit))
3009 /* We failed to find an algorithm. Record alg_impossible for
3010 this case (that is, <T, MODE, COST_LIMIT>) so that next time
3011 we are asked to find an algorithm for T within the same or
3012 lower COST_LIMIT, we can immediately return to the
3013 caller. */
3014 entry_ptr->t = t;
3015 entry_ptr->mode = mode;
3016 entry_ptr->speed = speed;
3017 entry_ptr->alg = alg_impossible;
3018 entry_ptr->cost = *cost_limit;
3019 return;
3022 /* Cache the result. */
3023 if (!cache_hit)
3025 entry_ptr->t = t;
3026 entry_ptr->mode = mode;
3027 entry_ptr->speed = speed;
3028 entry_ptr->alg = best_alg->op[best_alg->ops];
3029 entry_ptr->cost.cost = best_cost.cost;
3030 entry_ptr->cost.latency = best_cost.latency;
3033 /* If we are getting a too long sequence for `struct algorithm'
3034 to record, make this search fail. */
3035 if (best_alg->ops == MAX_BITS_PER_WORD)
3036 return;
3038 /* Copy the algorithm from temporary space to the space at alg_out.
3039 We avoid using structure assignment because the majority of
3040 best_alg is normally undefined, and this is a critical function. */
3041 alg_out->ops = best_alg->ops + 1;
3042 alg_out->cost = best_cost;
3043 memcpy (alg_out->op, best_alg->op,
3044 alg_out->ops * sizeof *alg_out->op);
3045 memcpy (alg_out->log, best_alg->log,
3046 alg_out->ops * sizeof *alg_out->log);
3049 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
3050 Try three variations:
3052 - a shift/add sequence based on VAL itself
3053 - a shift/add sequence based on -VAL, followed by a negation
3054 - a shift/add sequence based on VAL - 1, followed by an addition.
3056 Return true if the cheapest of these cost less than MULT_COST,
3057 describing the algorithm in *ALG and final fixup in *VARIANT. */
3059 bool
3060 choose_mult_variant (machine_mode mode, HOST_WIDE_INT val,
3061 struct algorithm *alg, enum mult_variant *variant,
3062 int mult_cost)
3064 struct algorithm alg2;
3065 struct mult_cost limit;
3066 int op_cost;
3067 bool speed = optimize_insn_for_speed_p ();
3069 /* Fail quickly for impossible bounds. */
3070 if (mult_cost < 0)
3071 return false;
3073 /* Ensure that mult_cost provides a reasonable upper bound.
3074 Any constant multiplication can be performed with less
3075 than 2 * bits additions. */
3076 op_cost = 2 * GET_MODE_UNIT_BITSIZE (mode) * add_cost (speed, mode);
3077 if (mult_cost > op_cost)
3078 mult_cost = op_cost;
3080 *variant = basic_variant;
3081 limit.cost = mult_cost;
3082 limit.latency = mult_cost;
3083 synth_mult (alg, val, &limit, mode);
3085 /* This works only if the inverted value actually fits in an
3086 `unsigned int' */
3087 if (HOST_BITS_PER_INT >= GET_MODE_UNIT_BITSIZE (mode))
3089 op_cost = neg_cost (speed, mode);
3090 if (MULT_COST_LESS (&alg->cost, mult_cost))
3092 limit.cost = alg->cost.cost - op_cost;
3093 limit.latency = alg->cost.latency - op_cost;
3095 else
3097 limit.cost = mult_cost - op_cost;
3098 limit.latency = mult_cost - op_cost;
3101 synth_mult (&alg2, -val, &limit, mode);
3102 alg2.cost.cost += op_cost;
3103 alg2.cost.latency += op_cost;
3104 if (CHEAPER_MULT_COST (&alg2.cost, &alg->cost))
3105 *alg = alg2, *variant = negate_variant;
3108 /* This proves very useful for division-by-constant. */
3109 op_cost = add_cost (speed, mode);
3110 if (MULT_COST_LESS (&alg->cost, mult_cost))
3112 limit.cost = alg->cost.cost - op_cost;
3113 limit.latency = alg->cost.latency - op_cost;
3115 else
3117 limit.cost = mult_cost - op_cost;
3118 limit.latency = mult_cost - op_cost;
3121 synth_mult (&alg2, val - 1, &limit, mode);
3122 alg2.cost.cost += op_cost;
3123 alg2.cost.latency += op_cost;
3124 if (CHEAPER_MULT_COST (&alg2.cost, &alg->cost))
3125 *alg = alg2, *variant = add_variant;
3127 return MULT_COST_LESS (&alg->cost, mult_cost);
3130 /* A subroutine of expand_mult, used for constant multiplications.
3131 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
3132 convenient. Use the shift/add sequence described by ALG and apply
3133 the final fixup specified by VARIANT. */
3135 static rtx
3136 expand_mult_const (machine_mode mode, rtx op0, HOST_WIDE_INT val,
3137 rtx target, const struct algorithm *alg,
3138 enum mult_variant variant)
3140 unsigned HOST_WIDE_INT val_so_far;
3141 rtx_insn *insn;
3142 rtx accum, tem;
3143 int opno;
3144 machine_mode nmode;
3146 /* Avoid referencing memory over and over and invalid sharing
3147 on SUBREGs. */
3148 op0 = force_reg (mode, op0);
3150 /* ACCUM starts out either as OP0 or as a zero, depending on
3151 the first operation. */
3153 if (alg->op[0] == alg_zero)
3155 accum = copy_to_mode_reg (mode, CONST0_RTX (mode));
3156 val_so_far = 0;
3158 else if (alg->op[0] == alg_m)
3160 accum = copy_to_mode_reg (mode, op0);
3161 val_so_far = 1;
3163 else
3164 gcc_unreachable ();
3166 for (opno = 1; opno < alg->ops; opno++)
3168 int log = alg->log[opno];
3169 rtx shift_subtarget = optimize ? 0 : accum;
3170 rtx add_target
3171 = (opno == alg->ops - 1 && target != 0 && variant != add_variant
3172 && !optimize)
3173 ? target : 0;
3174 rtx accum_target = optimize ? 0 : accum;
3175 rtx accum_inner;
3177 switch (alg->op[opno])
3179 case alg_shift:
3180 tem = expand_shift (LSHIFT_EXPR, mode, accum, log, NULL_RTX, 0);
3181 /* REG_EQUAL note will be attached to the following insn. */
3182 emit_move_insn (accum, tem);
3183 val_so_far <<= log;
3184 break;
3186 case alg_add_t_m2:
3187 tem = expand_shift (LSHIFT_EXPR, mode, op0, log, NULL_RTX, 0);
3188 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
3189 add_target ? add_target : accum_target);
3190 val_so_far += HOST_WIDE_INT_1U << log;
3191 break;
3193 case alg_sub_t_m2:
3194 tem = expand_shift (LSHIFT_EXPR, mode, op0, log, NULL_RTX, 0);
3195 accum = force_operand (gen_rtx_MINUS (mode, accum, tem),
3196 add_target ? add_target : accum_target);
3197 val_so_far -= HOST_WIDE_INT_1U << log;
3198 break;
3200 case alg_add_t2_m:
3201 accum = expand_shift (LSHIFT_EXPR, mode, accum,
3202 log, shift_subtarget, 0);
3203 accum = force_operand (gen_rtx_PLUS (mode, accum, op0),
3204 add_target ? add_target : accum_target);
3205 val_so_far = (val_so_far << log) + 1;
3206 break;
3208 case alg_sub_t2_m:
3209 accum = expand_shift (LSHIFT_EXPR, mode, accum,
3210 log, shift_subtarget, 0);
3211 accum = force_operand (gen_rtx_MINUS (mode, accum, op0),
3212 add_target ? add_target : accum_target);
3213 val_so_far = (val_so_far << log) - 1;
3214 break;
3216 case alg_add_factor:
3217 tem = expand_shift (LSHIFT_EXPR, mode, accum, log, NULL_RTX, 0);
3218 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
3219 add_target ? add_target : accum_target);
3220 val_so_far += val_so_far << log;
3221 break;
3223 case alg_sub_factor:
3224 tem = expand_shift (LSHIFT_EXPR, mode, accum, log, NULL_RTX, 0);
3225 accum = force_operand (gen_rtx_MINUS (mode, tem, accum),
3226 (add_target
3227 ? add_target : (optimize ? 0 : tem)));
3228 val_so_far = (val_so_far << log) - val_so_far;
3229 break;
3231 default:
3232 gcc_unreachable ();
3235 if (SCALAR_INT_MODE_P (mode))
3237 /* Write a REG_EQUAL note on the last insn so that we can cse
3238 multiplication sequences. Note that if ACCUM is a SUBREG,
3239 we've set the inner register and must properly indicate that. */
3240 tem = op0, nmode = mode;
3241 accum_inner = accum;
3242 if (GET_CODE (accum) == SUBREG)
3244 accum_inner = SUBREG_REG (accum);
3245 nmode = GET_MODE (accum_inner);
3246 tem = gen_lowpart (nmode, op0);
3249 insn = get_last_insn ();
3250 set_dst_reg_note (insn, REG_EQUAL,
3251 gen_rtx_MULT (nmode, tem,
3252 gen_int_mode (val_so_far, nmode)),
3253 accum_inner);
3257 if (variant == negate_variant)
3259 val_so_far = -val_so_far;
3260 accum = expand_unop (mode, neg_optab, accum, target, 0);
3262 else if (variant == add_variant)
3264 val_so_far = val_so_far + 1;
3265 accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target);
3268 /* Compare only the bits of val and val_so_far that are significant
3269 in the result mode, to avoid sign-/zero-extension confusion. */
3270 nmode = GET_MODE_INNER (mode);
3271 val &= GET_MODE_MASK (nmode);
3272 val_so_far &= GET_MODE_MASK (nmode);
3273 gcc_assert (val == (HOST_WIDE_INT) val_so_far);
3275 return accum;
3278 /* Perform a multiplication and return an rtx for the result.
3279 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3280 TARGET is a suggestion for where to store the result (an rtx).
3282 We check specially for a constant integer as OP1.
3283 If you want this check for OP0 as well, then before calling
3284 you should swap the two operands if OP0 would be constant. */
3287 expand_mult (machine_mode mode, rtx op0, rtx op1, rtx target,
3288 int unsignedp)
3290 enum mult_variant variant;
3291 struct algorithm algorithm;
3292 rtx scalar_op1;
3293 int max_cost;
3294 bool speed = optimize_insn_for_speed_p ();
3295 bool do_trapv = flag_trapv && SCALAR_INT_MODE_P (mode) && !unsignedp;
3297 if (CONSTANT_P (op0))
3298 std::swap (op0, op1);
3300 /* For vectors, there are several simplifications that can be made if
3301 all elements of the vector constant are identical. */
3302 scalar_op1 = unwrap_const_vec_duplicate (op1);
3304 if (INTEGRAL_MODE_P (mode))
3306 rtx fake_reg;
3307 HOST_WIDE_INT coeff;
3308 bool is_neg;
3309 int mode_bitsize;
3311 if (op1 == CONST0_RTX (mode))
3312 return op1;
3313 if (op1 == CONST1_RTX (mode))
3314 return op0;
3315 if (op1 == CONSTM1_RTX (mode))
3316 return expand_unop (mode, do_trapv ? negv_optab : neg_optab,
3317 op0, target, 0);
3319 if (do_trapv)
3320 goto skip_synth;
3322 /* If mode is integer vector mode, check if the backend supports
3323 vector lshift (by scalar or vector) at all. If not, we can't use
3324 synthetized multiply. */
3325 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
3326 && optab_handler (vashl_optab, mode) == CODE_FOR_nothing
3327 && optab_handler (ashl_optab, mode) == CODE_FOR_nothing)
3328 goto skip_synth;
3330 /* These are the operations that are potentially turned into
3331 a sequence of shifts and additions. */
3332 mode_bitsize = GET_MODE_UNIT_BITSIZE (mode);
3334 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3335 less than or equal in size to `unsigned int' this doesn't matter.
3336 If the mode is larger than `unsigned int', then synth_mult works
3337 only if the constant value exactly fits in an `unsigned int' without
3338 any truncation. This means that multiplying by negative values does
3339 not work; results are off by 2^32 on a 32 bit machine. */
3340 if (CONST_INT_P (scalar_op1))
3342 coeff = INTVAL (scalar_op1);
3343 is_neg = coeff < 0;
3345 #if TARGET_SUPPORTS_WIDE_INT
3346 else if (CONST_WIDE_INT_P (scalar_op1))
3347 #else
3348 else if (CONST_DOUBLE_AS_INT_P (scalar_op1))
3349 #endif
3351 int shift = wi::exact_log2 (rtx_mode_t (scalar_op1, mode));
3352 /* Perfect power of 2 (other than 1, which is handled above). */
3353 if (shift > 0)
3354 return expand_shift (LSHIFT_EXPR, mode, op0,
3355 shift, target, unsignedp);
3356 else
3357 goto skip_synth;
3359 else
3360 goto skip_synth;
3362 /* We used to test optimize here, on the grounds that it's better to
3363 produce a smaller program when -O is not used. But this causes
3364 such a terrible slowdown sometimes that it seems better to always
3365 use synth_mult. */
3367 /* Special case powers of two. */
3368 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff)
3369 && !(is_neg && mode_bitsize > HOST_BITS_PER_WIDE_INT))
3370 return expand_shift (LSHIFT_EXPR, mode, op0,
3371 floor_log2 (coeff), target, unsignedp);
3373 fake_reg = gen_raw_REG (mode, LAST_VIRTUAL_REGISTER + 1);
3375 /* Attempt to handle multiplication of DImode values by negative
3376 coefficients, by performing the multiplication by a positive
3377 multiplier and then inverting the result. */
3378 if (is_neg && mode_bitsize > HOST_BITS_PER_WIDE_INT)
3380 /* Its safe to use -coeff even for INT_MIN, as the
3381 result is interpreted as an unsigned coefficient.
3382 Exclude cost of op0 from max_cost to match the cost
3383 calculation of the synth_mult. */
3384 coeff = -(unsigned HOST_WIDE_INT) coeff;
3385 max_cost = (set_src_cost (gen_rtx_MULT (mode, fake_reg, op1),
3386 mode, speed)
3387 - neg_cost (speed, mode));
3388 if (max_cost <= 0)
3389 goto skip_synth;
3391 /* Special case powers of two. */
3392 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff))
3394 rtx temp = expand_shift (LSHIFT_EXPR, mode, op0,
3395 floor_log2 (coeff), target, unsignedp);
3396 return expand_unop (mode, neg_optab, temp, target, 0);
3399 if (choose_mult_variant (mode, coeff, &algorithm, &variant,
3400 max_cost))
3402 rtx temp = expand_mult_const (mode, op0, coeff, NULL_RTX,
3403 &algorithm, variant);
3404 return expand_unop (mode, neg_optab, temp, target, 0);
3406 goto skip_synth;
3409 /* Exclude cost of op0 from max_cost to match the cost
3410 calculation of the synth_mult. */
3411 max_cost = set_src_cost (gen_rtx_MULT (mode, fake_reg, op1), mode, speed);
3412 if (choose_mult_variant (mode, coeff, &algorithm, &variant, max_cost))
3413 return expand_mult_const (mode, op0, coeff, target,
3414 &algorithm, variant);
3416 skip_synth:
3418 /* Expand x*2.0 as x+x. */
3419 if (CONST_DOUBLE_AS_FLOAT_P (scalar_op1)
3420 && real_equal (CONST_DOUBLE_REAL_VALUE (scalar_op1), &dconst2))
3422 op0 = force_reg (GET_MODE (op0), op0);
3423 return expand_binop (mode, add_optab, op0, op0,
3424 target, unsignedp, OPTAB_LIB_WIDEN);
3427 /* This used to use umul_optab if unsigned, but for non-widening multiply
3428 there is no difference between signed and unsigned. */
3429 op0 = expand_binop (mode, do_trapv ? smulv_optab : smul_optab,
3430 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
3431 gcc_assert (op0);
3432 return op0;
3435 /* Return a cost estimate for multiplying a register by the given
3436 COEFFicient in the given MODE and SPEED. */
3439 mult_by_coeff_cost (HOST_WIDE_INT coeff, machine_mode mode, bool speed)
3441 int max_cost;
3442 struct algorithm algorithm;
3443 enum mult_variant variant;
3445 rtx fake_reg = gen_raw_REG (mode, LAST_VIRTUAL_REGISTER + 1);
3446 max_cost = set_src_cost (gen_rtx_MULT (mode, fake_reg, fake_reg),
3447 mode, speed);
3448 if (choose_mult_variant (mode, coeff, &algorithm, &variant, max_cost))
3449 return algorithm.cost.cost;
3450 else
3451 return max_cost;
3454 /* Perform a widening multiplication and return an rtx for the result.
3455 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3456 TARGET is a suggestion for where to store the result (an rtx).
3457 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3458 or smul_widen_optab.
3460 We check specially for a constant integer as OP1, comparing the
3461 cost of a widening multiply against the cost of a sequence of shifts
3462 and adds. */
3465 expand_widening_mult (machine_mode mode, rtx op0, rtx op1, rtx target,
3466 int unsignedp, optab this_optab)
3468 bool speed = optimize_insn_for_speed_p ();
3469 rtx cop1;
3471 if (CONST_INT_P (op1)
3472 && GET_MODE (op0) != VOIDmode
3473 && (cop1 = convert_modes (mode, GET_MODE (op0), op1,
3474 this_optab == umul_widen_optab))
3475 && CONST_INT_P (cop1)
3476 && (INTVAL (cop1) >= 0
3477 || HWI_COMPUTABLE_MODE_P (mode)))
3479 HOST_WIDE_INT coeff = INTVAL (cop1);
3480 int max_cost;
3481 enum mult_variant variant;
3482 struct algorithm algorithm;
3484 if (coeff == 0)
3485 return CONST0_RTX (mode);
3487 /* Special case powers of two. */
3488 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff))
3490 op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab);
3491 return expand_shift (LSHIFT_EXPR, mode, op0,
3492 floor_log2 (coeff), target, unsignedp);
3495 /* Exclude cost of op0 from max_cost to match the cost
3496 calculation of the synth_mult. */
3497 max_cost = mul_widen_cost (speed, mode);
3498 if (choose_mult_variant (mode, coeff, &algorithm, &variant,
3499 max_cost))
3501 op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab);
3502 return expand_mult_const (mode, op0, coeff, target,
3503 &algorithm, variant);
3506 return expand_binop (mode, this_optab, op0, op1, target,
3507 unsignedp, OPTAB_LIB_WIDEN);
3510 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3511 replace division by D, and put the least significant N bits of the result
3512 in *MULTIPLIER_PTR and return the most significant bit.
3514 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3515 needed precision is in PRECISION (should be <= N).
3517 PRECISION should be as small as possible so this function can choose
3518 multiplier more freely.
3520 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3521 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3523 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3524 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3526 unsigned HOST_WIDE_INT
3527 choose_multiplier (unsigned HOST_WIDE_INT d, int n, int precision,
3528 unsigned HOST_WIDE_INT *multiplier_ptr,
3529 int *post_shift_ptr, int *lgup_ptr)
3531 int lgup, post_shift;
3532 int pow, pow2;
3534 /* lgup = ceil(log2(divisor)); */
3535 lgup = ceil_log2 (d);
3537 gcc_assert (lgup <= n);
3539 pow = n + lgup;
3540 pow2 = n + lgup - precision;
3542 /* mlow = 2^(N + lgup)/d */
3543 wide_int val = wi::set_bit_in_zero (pow, HOST_BITS_PER_DOUBLE_INT);
3544 wide_int mlow = wi::udiv_trunc (val, d);
3546 /* mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d */
3547 val |= wi::set_bit_in_zero (pow2, HOST_BITS_PER_DOUBLE_INT);
3548 wide_int mhigh = wi::udiv_trunc (val, d);
3550 /* If precision == N, then mlow, mhigh exceed 2^N
3551 (but they do not exceed 2^(N+1)). */
3553 /* Reduce to lowest terms. */
3554 for (post_shift = lgup; post_shift > 0; post_shift--)
3556 unsigned HOST_WIDE_INT ml_lo = wi::extract_uhwi (mlow, 1,
3557 HOST_BITS_PER_WIDE_INT);
3558 unsigned HOST_WIDE_INT mh_lo = wi::extract_uhwi (mhigh, 1,
3559 HOST_BITS_PER_WIDE_INT);
3560 if (ml_lo >= mh_lo)
3561 break;
3563 mlow = wi::uhwi (ml_lo, HOST_BITS_PER_DOUBLE_INT);
3564 mhigh = wi::uhwi (mh_lo, HOST_BITS_PER_DOUBLE_INT);
3567 *post_shift_ptr = post_shift;
3568 *lgup_ptr = lgup;
3569 if (n < HOST_BITS_PER_WIDE_INT)
3571 unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << n) - 1;
3572 *multiplier_ptr = mhigh.to_uhwi () & mask;
3573 return mhigh.to_uhwi () >= mask;
3575 else
3577 *multiplier_ptr = mhigh.to_uhwi ();
3578 return wi::extract_uhwi (mhigh, HOST_BITS_PER_WIDE_INT, 1);
3582 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3583 congruent to 1 (mod 2**N). */
3585 static unsigned HOST_WIDE_INT
3586 invert_mod2n (unsigned HOST_WIDE_INT x, int n)
3588 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3590 /* The algorithm notes that the choice y = x satisfies
3591 x*y == 1 mod 2^3, since x is assumed odd.
3592 Each iteration doubles the number of bits of significance in y. */
3594 unsigned HOST_WIDE_INT mask;
3595 unsigned HOST_WIDE_INT y = x;
3596 int nbit = 3;
3598 mask = (n == HOST_BITS_PER_WIDE_INT
3599 ? HOST_WIDE_INT_M1U
3600 : (HOST_WIDE_INT_1U << n) - 1);
3602 while (nbit < n)
3604 y = y * (2 - x*y) & mask; /* Modulo 2^N */
3605 nbit *= 2;
3607 return y;
3610 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3611 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3612 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3613 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3614 become signed.
3616 The result is put in TARGET if that is convenient.
3618 MODE is the mode of operation. */
3621 expand_mult_highpart_adjust (scalar_int_mode mode, rtx adj_operand, rtx op0,
3622 rtx op1, rtx target, int unsignedp)
3624 rtx tem;
3625 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
3627 tem = expand_shift (RSHIFT_EXPR, mode, op0,
3628 GET_MODE_BITSIZE (mode) - 1, NULL_RTX, 0);
3629 tem = expand_and (mode, tem, op1, NULL_RTX);
3630 adj_operand
3631 = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
3632 adj_operand);
3634 tem = expand_shift (RSHIFT_EXPR, mode, op1,
3635 GET_MODE_BITSIZE (mode) - 1, NULL_RTX, 0);
3636 tem = expand_and (mode, tem, op0, NULL_RTX);
3637 target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
3638 target);
3640 return target;
3643 /* Subroutine of expmed_mult_highpart. Return the MODE high part of OP. */
3645 static rtx
3646 extract_high_half (scalar_int_mode mode, rtx op)
3648 if (mode == word_mode)
3649 return gen_highpart (mode, op);
3651 scalar_int_mode wider_mode = GET_MODE_WIDER_MODE (mode).require ();
3653 op = expand_shift (RSHIFT_EXPR, wider_mode, op,
3654 GET_MODE_BITSIZE (mode), 0, 1);
3655 return convert_modes (mode, wider_mode, op, 0);
3658 /* Like expmed_mult_highpart, but only consider using a multiplication
3659 optab. OP1 is an rtx for the constant operand. */
3661 static rtx
3662 expmed_mult_highpart_optab (scalar_int_mode mode, rtx op0, rtx op1,
3663 rtx target, int unsignedp, int max_cost)
3665 rtx narrow_op1 = gen_int_mode (INTVAL (op1), mode);
3666 optab moptab;
3667 rtx tem;
3668 int size;
3669 bool speed = optimize_insn_for_speed_p ();
3671 scalar_int_mode wider_mode = GET_MODE_WIDER_MODE (mode).require ();
3673 size = GET_MODE_BITSIZE (mode);
3675 /* Firstly, try using a multiplication insn that only generates the needed
3676 high part of the product, and in the sign flavor of unsignedp. */
3677 if (mul_highpart_cost (speed, mode) < max_cost)
3679 moptab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
3680 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
3681 unsignedp, OPTAB_DIRECT);
3682 if (tem)
3683 return tem;
3686 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3687 Need to adjust the result after the multiplication. */
3688 if (size - 1 < BITS_PER_WORD
3689 && (mul_highpart_cost (speed, mode)
3690 + 2 * shift_cost (speed, mode, size-1)
3691 + 4 * add_cost (speed, mode) < max_cost))
3693 moptab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
3694 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
3695 unsignedp, OPTAB_DIRECT);
3696 if (tem)
3697 /* We used the wrong signedness. Adjust the result. */
3698 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
3699 tem, unsignedp);
3702 /* Try widening multiplication. */
3703 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
3704 if (widening_optab_handler (moptab, wider_mode, mode) != CODE_FOR_nothing
3705 && mul_widen_cost (speed, wider_mode) < max_cost)
3707 tem = expand_binop (wider_mode, moptab, op0, narrow_op1, 0,
3708 unsignedp, OPTAB_WIDEN);
3709 if (tem)
3710 return extract_high_half (mode, tem);
3713 /* Try widening the mode and perform a non-widening multiplication. */
3714 if (optab_handler (smul_optab, wider_mode) != CODE_FOR_nothing
3715 && size - 1 < BITS_PER_WORD
3716 && (mul_cost (speed, wider_mode) + shift_cost (speed, mode, size-1)
3717 < max_cost))
3719 rtx_insn *insns;
3720 rtx wop0, wop1;
3722 /* We need to widen the operands, for example to ensure the
3723 constant multiplier is correctly sign or zero extended.
3724 Use a sequence to clean-up any instructions emitted by
3725 the conversions if things don't work out. */
3726 start_sequence ();
3727 wop0 = convert_modes (wider_mode, mode, op0, unsignedp);
3728 wop1 = convert_modes (wider_mode, mode, op1, unsignedp);
3729 tem = expand_binop (wider_mode, smul_optab, wop0, wop1, 0,
3730 unsignedp, OPTAB_WIDEN);
3731 insns = get_insns ();
3732 end_sequence ();
3734 if (tem)
3736 emit_insn (insns);
3737 return extract_high_half (mode, tem);
3741 /* Try widening multiplication of opposite signedness, and adjust. */
3742 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
3743 if (widening_optab_handler (moptab, wider_mode, mode) != CODE_FOR_nothing
3744 && size - 1 < BITS_PER_WORD
3745 && (mul_widen_cost (speed, wider_mode)
3746 + 2 * shift_cost (speed, mode, size-1)
3747 + 4 * add_cost (speed, mode) < max_cost))
3749 tem = expand_binop (wider_mode, moptab, op0, narrow_op1,
3750 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
3751 if (tem != 0)
3753 tem = extract_high_half (mode, tem);
3754 /* We used the wrong signedness. Adjust the result. */
3755 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
3756 target, unsignedp);
3760 return 0;
3763 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3764 putting the high half of the result in TARGET if that is convenient,
3765 and return where the result is. If the operation can not be performed,
3766 0 is returned.
3768 MODE is the mode of operation and result.
3770 UNSIGNEDP nonzero means unsigned multiply.
3772 MAX_COST is the total allowed cost for the expanded RTL. */
3774 static rtx
3775 expmed_mult_highpart (scalar_int_mode mode, rtx op0, rtx op1,
3776 rtx target, int unsignedp, int max_cost)
3778 unsigned HOST_WIDE_INT cnst1;
3779 int extra_cost;
3780 bool sign_adjust = false;
3781 enum mult_variant variant;
3782 struct algorithm alg;
3783 rtx tem;
3784 bool speed = optimize_insn_for_speed_p ();
3786 /* We can't support modes wider than HOST_BITS_PER_INT. */
3787 gcc_assert (HWI_COMPUTABLE_MODE_P (mode));
3789 cnst1 = INTVAL (op1) & GET_MODE_MASK (mode);
3791 /* We can't optimize modes wider than BITS_PER_WORD.
3792 ??? We might be able to perform double-word arithmetic if
3793 mode == word_mode, however all the cost calculations in
3794 synth_mult etc. assume single-word operations. */
3795 scalar_int_mode wider_mode = GET_MODE_WIDER_MODE (mode).require ();
3796 if (GET_MODE_BITSIZE (wider_mode) > BITS_PER_WORD)
3797 return expmed_mult_highpart_optab (mode, op0, op1, target,
3798 unsignedp, max_cost);
3800 extra_cost = shift_cost (speed, mode, GET_MODE_BITSIZE (mode) - 1);
3802 /* Check whether we try to multiply by a negative constant. */
3803 if (!unsignedp && ((cnst1 >> (GET_MODE_BITSIZE (mode) - 1)) & 1))
3805 sign_adjust = true;
3806 extra_cost += add_cost (speed, mode);
3809 /* See whether shift/add multiplication is cheap enough. */
3810 if (choose_mult_variant (wider_mode, cnst1, &alg, &variant,
3811 max_cost - extra_cost))
3813 /* See whether the specialized multiplication optabs are
3814 cheaper than the shift/add version. */
3815 tem = expmed_mult_highpart_optab (mode, op0, op1, target, unsignedp,
3816 alg.cost.cost + extra_cost);
3817 if (tem)
3818 return tem;
3820 tem = convert_to_mode (wider_mode, op0, unsignedp);
3821 tem = expand_mult_const (wider_mode, tem, cnst1, 0, &alg, variant);
3822 tem = extract_high_half (mode, tem);
3824 /* Adjust result for signedness. */
3825 if (sign_adjust)
3826 tem = force_operand (gen_rtx_MINUS (mode, tem, op0), tem);
3828 return tem;
3830 return expmed_mult_highpart_optab (mode, op0, op1, target,
3831 unsignedp, max_cost);
3835 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3837 static rtx
3838 expand_smod_pow2 (scalar_int_mode mode, rtx op0, HOST_WIDE_INT d)
3840 rtx result, temp, shift;
3841 rtx_code_label *label;
3842 int logd;
3843 int prec = GET_MODE_PRECISION (mode);
3845 logd = floor_log2 (d);
3846 result = gen_reg_rtx (mode);
3848 /* Avoid conditional branches when they're expensive. */
3849 if (BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2
3850 && optimize_insn_for_speed_p ())
3852 rtx signmask = emit_store_flag (result, LT, op0, const0_rtx,
3853 mode, 0, -1);
3854 if (signmask)
3856 HOST_WIDE_INT masklow = (HOST_WIDE_INT_1 << logd) - 1;
3857 signmask = force_reg (mode, signmask);
3858 shift = GEN_INT (GET_MODE_BITSIZE (mode) - logd);
3860 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3861 which instruction sequence to use. If logical right shifts
3862 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3863 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3865 temp = gen_rtx_LSHIFTRT (mode, result, shift);
3866 if (optab_handler (lshr_optab, mode) == CODE_FOR_nothing
3867 || (set_src_cost (temp, mode, optimize_insn_for_speed_p ())
3868 > COSTS_N_INSNS (2)))
3870 temp = expand_binop (mode, xor_optab, op0, signmask,
3871 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3872 temp = expand_binop (mode, sub_optab, temp, signmask,
3873 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3874 temp = expand_binop (mode, and_optab, temp,
3875 gen_int_mode (masklow, mode),
3876 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3877 temp = expand_binop (mode, xor_optab, temp, signmask,
3878 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3879 temp = expand_binop (mode, sub_optab, temp, signmask,
3880 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3882 else
3884 signmask = expand_binop (mode, lshr_optab, signmask, shift,
3885 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3886 signmask = force_reg (mode, signmask);
3888 temp = expand_binop (mode, add_optab, op0, signmask,
3889 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3890 temp = expand_binop (mode, and_optab, temp,
3891 gen_int_mode (masklow, mode),
3892 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3893 temp = expand_binop (mode, sub_optab, temp, signmask,
3894 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3896 return temp;
3900 /* Mask contains the mode's signbit and the significant bits of the
3901 modulus. By including the signbit in the operation, many targets
3902 can avoid an explicit compare operation in the following comparison
3903 against zero. */
3904 wide_int mask = wi::mask (logd, false, prec);
3905 mask = wi::set_bit (mask, prec - 1);
3907 temp = expand_binop (mode, and_optab, op0,
3908 immed_wide_int_const (mask, mode),
3909 result, 1, OPTAB_LIB_WIDEN);
3910 if (temp != result)
3911 emit_move_insn (result, temp);
3913 label = gen_label_rtx ();
3914 do_cmp_and_jump (result, const0_rtx, GE, mode, label);
3916 temp = expand_binop (mode, sub_optab, result, const1_rtx, result,
3917 0, OPTAB_LIB_WIDEN);
3919 mask = wi::mask (logd, true, prec);
3920 temp = expand_binop (mode, ior_optab, temp,
3921 immed_wide_int_const (mask, mode),
3922 result, 1, OPTAB_LIB_WIDEN);
3923 temp = expand_binop (mode, add_optab, temp, const1_rtx, result,
3924 0, OPTAB_LIB_WIDEN);
3925 if (temp != result)
3926 emit_move_insn (result, temp);
3927 emit_label (label);
3928 return result;
3931 /* Expand signed division of OP0 by a power of two D in mode MODE.
3932 This routine is only called for positive values of D. */
3934 static rtx
3935 expand_sdiv_pow2 (scalar_int_mode mode, rtx op0, HOST_WIDE_INT d)
3937 rtx temp;
3938 rtx_code_label *label;
3939 int logd;
3941 logd = floor_log2 (d);
3943 if (d == 2
3944 && BRANCH_COST (optimize_insn_for_speed_p (),
3945 false) >= 1)
3947 temp = gen_reg_rtx (mode);
3948 temp = emit_store_flag (temp, LT, op0, const0_rtx, mode, 0, 1);
3949 temp = expand_binop (mode, add_optab, temp, op0, NULL_RTX,
3950 0, OPTAB_LIB_WIDEN);
3951 return expand_shift (RSHIFT_EXPR, mode, temp, logd, NULL_RTX, 0);
3954 if (HAVE_conditional_move
3955 && BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2)
3957 rtx temp2;
3959 start_sequence ();
3960 temp2 = copy_to_mode_reg (mode, op0);
3961 temp = expand_binop (mode, add_optab, temp2, gen_int_mode (d - 1, mode),
3962 NULL_RTX, 0, OPTAB_LIB_WIDEN);
3963 temp = force_reg (mode, temp);
3965 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3966 temp2 = emit_conditional_move (temp2, LT, temp2, const0_rtx,
3967 mode, temp, temp2, mode, 0);
3968 if (temp2)
3970 rtx_insn *seq = get_insns ();
3971 end_sequence ();
3972 emit_insn (seq);
3973 return expand_shift (RSHIFT_EXPR, mode, temp2, logd, NULL_RTX, 0);
3975 end_sequence ();
3978 if (BRANCH_COST (optimize_insn_for_speed_p (),
3979 false) >= 2)
3981 int ushift = GET_MODE_BITSIZE (mode) - logd;
3983 temp = gen_reg_rtx (mode);
3984 temp = emit_store_flag (temp, LT, op0, const0_rtx, mode, 0, -1);
3985 if (GET_MODE_BITSIZE (mode) >= BITS_PER_WORD
3986 || shift_cost (optimize_insn_for_speed_p (), mode, ushift)
3987 > COSTS_N_INSNS (1))
3988 temp = expand_binop (mode, and_optab, temp, gen_int_mode (d - 1, mode),
3989 NULL_RTX, 0, OPTAB_LIB_WIDEN);
3990 else
3991 temp = expand_shift (RSHIFT_EXPR, mode, temp,
3992 ushift, NULL_RTX, 1);
3993 temp = expand_binop (mode, add_optab, temp, op0, NULL_RTX,
3994 0, OPTAB_LIB_WIDEN);
3995 return expand_shift (RSHIFT_EXPR, mode, temp, logd, NULL_RTX, 0);
3998 label = gen_label_rtx ();
3999 temp = copy_to_mode_reg (mode, op0);
4000 do_cmp_and_jump (temp, const0_rtx, GE, mode, label);
4001 expand_inc (temp, gen_int_mode (d - 1, mode));
4002 emit_label (label);
4003 return expand_shift (RSHIFT_EXPR, mode, temp, logd, NULL_RTX, 0);
4006 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
4007 if that is convenient, and returning where the result is.
4008 You may request either the quotient or the remainder as the result;
4009 specify REM_FLAG nonzero to get the remainder.
4011 CODE is the expression code for which kind of division this is;
4012 it controls how rounding is done. MODE is the machine mode to use.
4013 UNSIGNEDP nonzero means do unsigned division. */
4015 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
4016 and then correct it by or'ing in missing high bits
4017 if result of ANDI is nonzero.
4018 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
4019 This could optimize to a bfexts instruction.
4020 But C doesn't use these operations, so their optimizations are
4021 left for later. */
4022 /* ??? For modulo, we don't actually need the highpart of the first product,
4023 the low part will do nicely. And for small divisors, the second multiply
4024 can also be a low-part only multiply or even be completely left out.
4025 E.g. to calculate the remainder of a division by 3 with a 32 bit
4026 multiply, multiply with 0x55555556 and extract the upper two bits;
4027 the result is exact for inputs up to 0x1fffffff.
4028 The input range can be reduced by using cross-sum rules.
4029 For odd divisors >= 3, the following table gives right shift counts
4030 so that if a number is shifted by an integer multiple of the given
4031 amount, the remainder stays the same:
4032 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
4033 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
4034 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
4035 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
4036 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
4038 Cross-sum rules for even numbers can be derived by leaving as many bits
4039 to the right alone as the divisor has zeros to the right.
4040 E.g. if x is an unsigned 32 bit number:
4041 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
4045 expand_divmod (int rem_flag, enum tree_code code, machine_mode mode,
4046 rtx op0, rtx op1, rtx target, int unsignedp)
4048 machine_mode compute_mode;
4049 rtx tquotient;
4050 rtx quotient = 0, remainder = 0;
4051 rtx_insn *last;
4052 rtx_insn *insn;
4053 optab optab1, optab2;
4054 int op1_is_constant, op1_is_pow2 = 0;
4055 int max_cost, extra_cost;
4056 static HOST_WIDE_INT last_div_const = 0;
4057 bool speed = optimize_insn_for_speed_p ();
4059 op1_is_constant = CONST_INT_P (op1);
4060 if (op1_is_constant)
4062 wide_int ext_op1 = rtx_mode_t (op1, mode);
4063 op1_is_pow2 = (wi::popcount (ext_op1) == 1
4064 || (! unsignedp
4065 && wi::popcount (wi::neg (ext_op1)) == 1));
4069 This is the structure of expand_divmod:
4071 First comes code to fix up the operands so we can perform the operations
4072 correctly and efficiently.
4074 Second comes a switch statement with code specific for each rounding mode.
4075 For some special operands this code emits all RTL for the desired
4076 operation, for other cases, it generates only a quotient and stores it in
4077 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
4078 to indicate that it has not done anything.
4080 Last comes code that finishes the operation. If QUOTIENT is set and
4081 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
4082 QUOTIENT is not set, it is computed using trunc rounding.
4084 We try to generate special code for division and remainder when OP1 is a
4085 constant. If |OP1| = 2**n we can use shifts and some other fast
4086 operations. For other values of OP1, we compute a carefully selected
4087 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
4088 by m.
4090 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
4091 half of the product. Different strategies for generating the product are
4092 implemented in expmed_mult_highpart.
4094 If what we actually want is the remainder, we generate that by another
4095 by-constant multiplication and a subtraction. */
4097 /* We shouldn't be called with OP1 == const1_rtx, but some of the
4098 code below will malfunction if we are, so check here and handle
4099 the special case if so. */
4100 if (op1 == const1_rtx)
4101 return rem_flag ? const0_rtx : op0;
4103 /* When dividing by -1, we could get an overflow.
4104 negv_optab can handle overflows. */
4105 if (! unsignedp && op1 == constm1_rtx)
4107 if (rem_flag)
4108 return const0_rtx;
4109 return expand_unop (mode, flag_trapv && GET_MODE_CLASS (mode) == MODE_INT
4110 ? negv_optab : neg_optab, op0, target, 0);
4113 if (target
4114 /* Don't use the function value register as a target
4115 since we have to read it as well as write it,
4116 and function-inlining gets confused by this. */
4117 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
4118 /* Don't clobber an operand while doing a multi-step calculation. */
4119 || ((rem_flag || op1_is_constant)
4120 && (reg_mentioned_p (target, op0)
4121 || (MEM_P (op0) && MEM_P (target))))
4122 || reg_mentioned_p (target, op1)
4123 || (MEM_P (op1) && MEM_P (target))))
4124 target = 0;
4126 /* Get the mode in which to perform this computation. Normally it will
4127 be MODE, but sometimes we can't do the desired operation in MODE.
4128 If so, pick a wider mode in which we can do the operation. Convert
4129 to that mode at the start to avoid repeated conversions.
4131 First see what operations we need. These depend on the expression
4132 we are evaluating. (We assume that divxx3 insns exist under the
4133 same conditions that modxx3 insns and that these insns don't normally
4134 fail. If these assumptions are not correct, we may generate less
4135 efficient code in some cases.)
4137 Then see if we find a mode in which we can open-code that operation
4138 (either a division, modulus, or shift). Finally, check for the smallest
4139 mode for which we can do the operation with a library call. */
4141 /* We might want to refine this now that we have division-by-constant
4142 optimization. Since expmed_mult_highpart tries so many variants, it is
4143 not straightforward to generalize this. Maybe we should make an array
4144 of possible modes in init_expmed? Save this for GCC 2.7. */
4146 optab1 = (op1_is_pow2
4147 ? (unsignedp ? lshr_optab : ashr_optab)
4148 : (unsignedp ? udiv_optab : sdiv_optab));
4149 optab2 = (op1_is_pow2 ? optab1
4150 : (unsignedp ? udivmod_optab : sdivmod_optab));
4152 FOR_EACH_MODE_FROM (compute_mode, mode)
4153 if (optab_handler (optab1, compute_mode) != CODE_FOR_nothing
4154 || optab_handler (optab2, compute_mode) != CODE_FOR_nothing)
4155 break;
4157 if (compute_mode == VOIDmode)
4158 FOR_EACH_MODE_FROM (compute_mode, mode)
4159 if (optab_libfunc (optab1, compute_mode)
4160 || optab_libfunc (optab2, compute_mode))
4161 break;
4163 /* If we still couldn't find a mode, use MODE, but expand_binop will
4164 probably die. */
4165 if (compute_mode == VOIDmode)
4166 compute_mode = mode;
4168 if (target && GET_MODE (target) == compute_mode)
4169 tquotient = target;
4170 else
4171 tquotient = gen_reg_rtx (compute_mode);
4173 #if 0
4174 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
4175 (mode), and thereby get better code when OP1 is a constant. Do that
4176 later. It will require going over all usages of SIZE below. */
4177 size = GET_MODE_BITSIZE (mode);
4178 #endif
4180 /* Only deduct something for a REM if the last divide done was
4181 for a different constant. Then set the constant of the last
4182 divide. */
4183 max_cost = (unsignedp
4184 ? udiv_cost (speed, compute_mode)
4185 : sdiv_cost (speed, compute_mode));
4186 if (rem_flag && ! (last_div_const != 0 && op1_is_constant
4187 && INTVAL (op1) == last_div_const))
4188 max_cost -= (mul_cost (speed, compute_mode)
4189 + add_cost (speed, compute_mode));
4191 last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0;
4193 /* Now convert to the best mode to use. */
4194 if (compute_mode != mode)
4196 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
4197 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
4199 /* convert_modes may have placed op1 into a register, so we
4200 must recompute the following. */
4201 op1_is_constant = CONST_INT_P (op1);
4202 if (op1_is_constant)
4204 wide_int ext_op1 = rtx_mode_t (op1, compute_mode);
4205 op1_is_pow2 = (wi::popcount (ext_op1) == 1
4206 || (! unsignedp
4207 && wi::popcount (wi::neg (ext_op1)) == 1));
4209 else
4210 op1_is_pow2 = 0;
4213 /* If one of the operands is a volatile MEM, copy it into a register. */
4215 if (MEM_P (op0) && MEM_VOLATILE_P (op0))
4216 op0 = force_reg (compute_mode, op0);
4217 if (MEM_P (op1) && MEM_VOLATILE_P (op1))
4218 op1 = force_reg (compute_mode, op1);
4220 /* If we need the remainder or if OP1 is constant, we need to
4221 put OP0 in a register in case it has any queued subexpressions. */
4222 if (rem_flag || op1_is_constant)
4223 op0 = force_reg (compute_mode, op0);
4225 last = get_last_insn ();
4227 /* Promote floor rounding to trunc rounding for unsigned operations. */
4228 if (unsignedp)
4230 if (code == FLOOR_DIV_EXPR)
4231 code = TRUNC_DIV_EXPR;
4232 if (code == FLOOR_MOD_EXPR)
4233 code = TRUNC_MOD_EXPR;
4234 if (code == EXACT_DIV_EXPR && op1_is_pow2)
4235 code = TRUNC_DIV_EXPR;
4238 if (op1 != const0_rtx)
4239 switch (code)
4241 case TRUNC_MOD_EXPR:
4242 case TRUNC_DIV_EXPR:
4243 if (op1_is_constant)
4245 scalar_int_mode int_mode = as_a <scalar_int_mode> (compute_mode);
4246 int size = GET_MODE_BITSIZE (int_mode);
4247 if (unsignedp)
4249 unsigned HOST_WIDE_INT mh, ml;
4250 int pre_shift, post_shift;
4251 int dummy;
4252 wide_int wd = rtx_mode_t (op1, int_mode);
4253 unsigned HOST_WIDE_INT d = wd.to_uhwi ();
4255 if (wi::popcount (wd) == 1)
4257 pre_shift = floor_log2 (d);
4258 if (rem_flag)
4260 unsigned HOST_WIDE_INT mask
4261 = (HOST_WIDE_INT_1U << pre_shift) - 1;
4262 remainder
4263 = expand_binop (int_mode, and_optab, op0,
4264 gen_int_mode (mask, int_mode),
4265 remainder, 1,
4266 OPTAB_LIB_WIDEN);
4267 if (remainder)
4268 return gen_lowpart (mode, remainder);
4270 quotient = expand_shift (RSHIFT_EXPR, int_mode, op0,
4271 pre_shift, tquotient, 1);
4273 else if (size <= HOST_BITS_PER_WIDE_INT)
4275 if (d >= (HOST_WIDE_INT_1U << (size - 1)))
4277 /* Most significant bit of divisor is set; emit an scc
4278 insn. */
4279 quotient = emit_store_flag_force (tquotient, GEU, op0, op1,
4280 int_mode, 1, 1);
4282 else
4284 /* Find a suitable multiplier and right shift count
4285 instead of multiplying with D. */
4287 mh = choose_multiplier (d, size, size,
4288 &ml, &post_shift, &dummy);
4290 /* If the suggested multiplier is more than SIZE bits,
4291 we can do better for even divisors, using an
4292 initial right shift. */
4293 if (mh != 0 && (d & 1) == 0)
4295 pre_shift = ctz_or_zero (d);
4296 mh = choose_multiplier (d >> pre_shift, size,
4297 size - pre_shift,
4298 &ml, &post_shift, &dummy);
4299 gcc_assert (!mh);
4301 else
4302 pre_shift = 0;
4304 if (mh != 0)
4306 rtx t1, t2, t3, t4;
4308 if (post_shift - 1 >= BITS_PER_WORD)
4309 goto fail1;
4311 extra_cost
4312 = (shift_cost (speed, int_mode, post_shift - 1)
4313 + shift_cost (speed, int_mode, 1)
4314 + 2 * add_cost (speed, int_mode));
4315 t1 = expmed_mult_highpart
4316 (int_mode, op0, gen_int_mode (ml, int_mode),
4317 NULL_RTX, 1, max_cost - extra_cost);
4318 if (t1 == 0)
4319 goto fail1;
4320 t2 = force_operand (gen_rtx_MINUS (int_mode,
4321 op0, t1),
4322 NULL_RTX);
4323 t3 = expand_shift (RSHIFT_EXPR, int_mode,
4324 t2, 1, NULL_RTX, 1);
4325 t4 = force_operand (gen_rtx_PLUS (int_mode,
4326 t1, t3),
4327 NULL_RTX);
4328 quotient = expand_shift
4329 (RSHIFT_EXPR, int_mode, t4,
4330 post_shift - 1, tquotient, 1);
4332 else
4334 rtx t1, t2;
4336 if (pre_shift >= BITS_PER_WORD
4337 || post_shift >= BITS_PER_WORD)
4338 goto fail1;
4340 t1 = expand_shift
4341 (RSHIFT_EXPR, int_mode, op0,
4342 pre_shift, NULL_RTX, 1);
4343 extra_cost
4344 = (shift_cost (speed, int_mode, pre_shift)
4345 + shift_cost (speed, int_mode, post_shift));
4346 t2 = expmed_mult_highpart
4347 (int_mode, t1,
4348 gen_int_mode (ml, int_mode),
4349 NULL_RTX, 1, max_cost - extra_cost);
4350 if (t2 == 0)
4351 goto fail1;
4352 quotient = expand_shift
4353 (RSHIFT_EXPR, int_mode, t2,
4354 post_shift, tquotient, 1);
4358 else /* Too wide mode to use tricky code */
4359 break;
4361 insn = get_last_insn ();
4362 if (insn != last)
4363 set_dst_reg_note (insn, REG_EQUAL,
4364 gen_rtx_UDIV (int_mode, op0, op1),
4365 quotient);
4367 else /* TRUNC_DIV, signed */
4369 unsigned HOST_WIDE_INT ml;
4370 int lgup, post_shift;
4371 rtx mlr;
4372 HOST_WIDE_INT d = INTVAL (op1);
4373 unsigned HOST_WIDE_INT abs_d;
4375 /* Since d might be INT_MIN, we have to cast to
4376 unsigned HOST_WIDE_INT before negating to avoid
4377 undefined signed overflow. */
4378 abs_d = (d >= 0
4379 ? (unsigned HOST_WIDE_INT) d
4380 : - (unsigned HOST_WIDE_INT) d);
4382 /* n rem d = n rem -d */
4383 if (rem_flag && d < 0)
4385 d = abs_d;
4386 op1 = gen_int_mode (abs_d, int_mode);
4389 if (d == 1)
4390 quotient = op0;
4391 else if (d == -1)
4392 quotient = expand_unop (int_mode, neg_optab, op0,
4393 tquotient, 0);
4394 else if (size <= HOST_BITS_PER_WIDE_INT
4395 && abs_d == HOST_WIDE_INT_1U << (size - 1))
4397 /* This case is not handled correctly below. */
4398 quotient = emit_store_flag (tquotient, EQ, op0, op1,
4399 int_mode, 1, 1);
4400 if (quotient == 0)
4401 goto fail1;
4403 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
4404 && (size <= HOST_BITS_PER_WIDE_INT || d >= 0)
4405 && (rem_flag
4406 ? smod_pow2_cheap (speed, int_mode)
4407 : sdiv_pow2_cheap (speed, int_mode))
4408 /* We assume that cheap metric is true if the
4409 optab has an expander for this mode. */
4410 && ((optab_handler ((rem_flag ? smod_optab
4411 : sdiv_optab),
4412 int_mode)
4413 != CODE_FOR_nothing)
4414 || (optab_handler (sdivmod_optab, int_mode)
4415 != CODE_FOR_nothing)))
4417 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d)
4418 && (size <= HOST_BITS_PER_WIDE_INT
4419 || abs_d != (unsigned HOST_WIDE_INT) d))
4421 if (rem_flag)
4423 remainder = expand_smod_pow2 (int_mode, op0, d);
4424 if (remainder)
4425 return gen_lowpart (mode, remainder);
4428 if (sdiv_pow2_cheap (speed, int_mode)
4429 && ((optab_handler (sdiv_optab, int_mode)
4430 != CODE_FOR_nothing)
4431 || (optab_handler (sdivmod_optab, int_mode)
4432 != CODE_FOR_nothing)))
4433 quotient = expand_divmod (0, TRUNC_DIV_EXPR,
4434 int_mode, op0,
4435 gen_int_mode (abs_d,
4436 int_mode),
4437 NULL_RTX, 0);
4438 else
4439 quotient = expand_sdiv_pow2 (int_mode, op0, abs_d);
4441 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4442 negate the quotient. */
4443 if (d < 0)
4445 insn = get_last_insn ();
4446 if (insn != last
4447 && abs_d < (HOST_WIDE_INT_1U
4448 << (HOST_BITS_PER_WIDE_INT - 1)))
4449 set_dst_reg_note (insn, REG_EQUAL,
4450 gen_rtx_DIV (int_mode, op0,
4451 gen_int_mode
4452 (abs_d,
4453 int_mode)),
4454 quotient);
4456 quotient = expand_unop (int_mode, neg_optab,
4457 quotient, quotient, 0);
4460 else if (size <= HOST_BITS_PER_WIDE_INT)
4462 choose_multiplier (abs_d, size, size - 1,
4463 &ml, &post_shift, &lgup);
4464 if (ml < HOST_WIDE_INT_1U << (size - 1))
4466 rtx t1, t2, t3;
4468 if (post_shift >= BITS_PER_WORD
4469 || size - 1 >= BITS_PER_WORD)
4470 goto fail1;
4472 extra_cost = (shift_cost (speed, int_mode, post_shift)
4473 + shift_cost (speed, int_mode, size - 1)
4474 + add_cost (speed, int_mode));
4475 t1 = expmed_mult_highpart
4476 (int_mode, op0, gen_int_mode (ml, int_mode),
4477 NULL_RTX, 0, max_cost - extra_cost);
4478 if (t1 == 0)
4479 goto fail1;
4480 t2 = expand_shift
4481 (RSHIFT_EXPR, int_mode, t1,
4482 post_shift, NULL_RTX, 0);
4483 t3 = expand_shift
4484 (RSHIFT_EXPR, int_mode, op0,
4485 size - 1, NULL_RTX, 0);
4486 if (d < 0)
4487 quotient
4488 = force_operand (gen_rtx_MINUS (int_mode, t3, t2),
4489 tquotient);
4490 else
4491 quotient
4492 = force_operand (gen_rtx_MINUS (int_mode, t2, t3),
4493 tquotient);
4495 else
4497 rtx t1, t2, t3, t4;
4499 if (post_shift >= BITS_PER_WORD
4500 || size - 1 >= BITS_PER_WORD)
4501 goto fail1;
4503 ml |= HOST_WIDE_INT_M1U << (size - 1);
4504 mlr = gen_int_mode (ml, int_mode);
4505 extra_cost = (shift_cost (speed, int_mode, post_shift)
4506 + shift_cost (speed, int_mode, size - 1)
4507 + 2 * add_cost (speed, int_mode));
4508 t1 = expmed_mult_highpart (int_mode, op0, mlr,
4509 NULL_RTX, 0,
4510 max_cost - extra_cost);
4511 if (t1 == 0)
4512 goto fail1;
4513 t2 = force_operand (gen_rtx_PLUS (int_mode, t1, op0),
4514 NULL_RTX);
4515 t3 = expand_shift
4516 (RSHIFT_EXPR, int_mode, t2,
4517 post_shift, NULL_RTX, 0);
4518 t4 = expand_shift
4519 (RSHIFT_EXPR, int_mode, op0,
4520 size - 1, NULL_RTX, 0);
4521 if (d < 0)
4522 quotient
4523 = force_operand (gen_rtx_MINUS (int_mode, t4, t3),
4524 tquotient);
4525 else
4526 quotient
4527 = force_operand (gen_rtx_MINUS (int_mode, t3, t4),
4528 tquotient);
4531 else /* Too wide mode to use tricky code */
4532 break;
4534 insn = get_last_insn ();
4535 if (insn != last)
4536 set_dst_reg_note (insn, REG_EQUAL,
4537 gen_rtx_DIV (int_mode, op0, op1),
4538 quotient);
4540 break;
4542 fail1:
4543 delete_insns_since (last);
4544 break;
4546 case FLOOR_DIV_EXPR:
4547 case FLOOR_MOD_EXPR:
4548 /* We will come here only for signed operations. */
4549 if (op1_is_constant && HWI_COMPUTABLE_MODE_P (compute_mode))
4551 scalar_int_mode int_mode = as_a <scalar_int_mode> (compute_mode);
4552 int size = GET_MODE_BITSIZE (int_mode);
4553 unsigned HOST_WIDE_INT mh, ml;
4554 int pre_shift, lgup, post_shift;
4555 HOST_WIDE_INT d = INTVAL (op1);
4557 if (d > 0)
4559 /* We could just as easily deal with negative constants here,
4560 but it does not seem worth the trouble for GCC 2.6. */
4561 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
4563 pre_shift = floor_log2 (d);
4564 if (rem_flag)
4566 unsigned HOST_WIDE_INT mask
4567 = (HOST_WIDE_INT_1U << pre_shift) - 1;
4568 remainder = expand_binop
4569 (int_mode, and_optab, op0,
4570 gen_int_mode (mask, int_mode),
4571 remainder, 0, OPTAB_LIB_WIDEN);
4572 if (remainder)
4573 return gen_lowpart (mode, remainder);
4575 quotient = expand_shift
4576 (RSHIFT_EXPR, int_mode, op0,
4577 pre_shift, tquotient, 0);
4579 else
4581 rtx t1, t2, t3, t4;
4583 mh = choose_multiplier (d, size, size - 1,
4584 &ml, &post_shift, &lgup);
4585 gcc_assert (!mh);
4587 if (post_shift < BITS_PER_WORD
4588 && size - 1 < BITS_PER_WORD)
4590 t1 = expand_shift
4591 (RSHIFT_EXPR, int_mode, op0,
4592 size - 1, NULL_RTX, 0);
4593 t2 = expand_binop (int_mode, xor_optab, op0, t1,
4594 NULL_RTX, 0, OPTAB_WIDEN);
4595 extra_cost = (shift_cost (speed, int_mode, post_shift)
4596 + shift_cost (speed, int_mode, size - 1)
4597 + 2 * add_cost (speed, int_mode));
4598 t3 = expmed_mult_highpart
4599 (int_mode, t2, gen_int_mode (ml, int_mode),
4600 NULL_RTX, 1, max_cost - extra_cost);
4601 if (t3 != 0)
4603 t4 = expand_shift
4604 (RSHIFT_EXPR, int_mode, t3,
4605 post_shift, NULL_RTX, 1);
4606 quotient = expand_binop (int_mode, xor_optab,
4607 t4, t1, tquotient, 0,
4608 OPTAB_WIDEN);
4613 else
4615 rtx nsign, t1, t2, t3, t4;
4616 t1 = force_operand (gen_rtx_PLUS (int_mode,
4617 op0, constm1_rtx), NULL_RTX);
4618 t2 = expand_binop (int_mode, ior_optab, op0, t1, NULL_RTX,
4619 0, OPTAB_WIDEN);
4620 nsign = expand_shift (RSHIFT_EXPR, int_mode, t2,
4621 size - 1, NULL_RTX, 0);
4622 t3 = force_operand (gen_rtx_MINUS (int_mode, t1, nsign),
4623 NULL_RTX);
4624 t4 = expand_divmod (0, TRUNC_DIV_EXPR, int_mode, t3, op1,
4625 NULL_RTX, 0);
4626 if (t4)
4628 rtx t5;
4629 t5 = expand_unop (int_mode, one_cmpl_optab, nsign,
4630 NULL_RTX, 0);
4631 quotient = force_operand (gen_rtx_PLUS (int_mode, t4, t5),
4632 tquotient);
4637 if (quotient != 0)
4638 break;
4639 delete_insns_since (last);
4641 /* Try using an instruction that produces both the quotient and
4642 remainder, using truncation. We can easily compensate the quotient
4643 or remainder to get floor rounding, once we have the remainder.
4644 Notice that we compute also the final remainder value here,
4645 and return the result right away. */
4646 if (target == 0 || GET_MODE (target) != compute_mode)
4647 target = gen_reg_rtx (compute_mode);
4649 if (rem_flag)
4651 remainder
4652 = REG_P (target) ? target : gen_reg_rtx (compute_mode);
4653 quotient = gen_reg_rtx (compute_mode);
4655 else
4657 quotient
4658 = REG_P (target) ? target : gen_reg_rtx (compute_mode);
4659 remainder = gen_reg_rtx (compute_mode);
4662 if (expand_twoval_binop (sdivmod_optab, op0, op1,
4663 quotient, remainder, 0))
4665 /* This could be computed with a branch-less sequence.
4666 Save that for later. */
4667 rtx tem;
4668 rtx_code_label *label = gen_label_rtx ();
4669 do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label);
4670 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4671 NULL_RTX, 0, OPTAB_WIDEN);
4672 do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label);
4673 expand_dec (quotient, const1_rtx);
4674 expand_inc (remainder, op1);
4675 emit_label (label);
4676 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4679 /* No luck with division elimination or divmod. Have to do it
4680 by conditionally adjusting op0 *and* the result. */
4682 rtx_code_label *label1, *label2, *label3, *label4, *label5;
4683 rtx adjusted_op0;
4684 rtx tem;
4686 quotient = gen_reg_rtx (compute_mode);
4687 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4688 label1 = gen_label_rtx ();
4689 label2 = gen_label_rtx ();
4690 label3 = gen_label_rtx ();
4691 label4 = gen_label_rtx ();
4692 label5 = gen_label_rtx ();
4693 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
4694 do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1);
4695 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4696 quotient, 0, OPTAB_LIB_WIDEN);
4697 if (tem != quotient)
4698 emit_move_insn (quotient, tem);
4699 emit_jump_insn (targetm.gen_jump (label5));
4700 emit_barrier ();
4701 emit_label (label1);
4702 expand_inc (adjusted_op0, const1_rtx);
4703 emit_jump_insn (targetm.gen_jump (label4));
4704 emit_barrier ();
4705 emit_label (label2);
4706 do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3);
4707 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4708 quotient, 0, OPTAB_LIB_WIDEN);
4709 if (tem != quotient)
4710 emit_move_insn (quotient, tem);
4711 emit_jump_insn (targetm.gen_jump (label5));
4712 emit_barrier ();
4713 emit_label (label3);
4714 expand_dec (adjusted_op0, const1_rtx);
4715 emit_label (label4);
4716 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4717 quotient, 0, OPTAB_LIB_WIDEN);
4718 if (tem != quotient)
4719 emit_move_insn (quotient, tem);
4720 expand_dec (quotient, const1_rtx);
4721 emit_label (label5);
4723 break;
4725 case CEIL_DIV_EXPR:
4726 case CEIL_MOD_EXPR:
4727 if (unsignedp)
4729 if (op1_is_constant
4730 && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
4731 && (HWI_COMPUTABLE_MODE_P (compute_mode)
4732 || INTVAL (op1) >= 0))
4734 scalar_int_mode int_mode
4735 = as_a <scalar_int_mode> (compute_mode);
4736 rtx t1, t2, t3;
4737 unsigned HOST_WIDE_INT d = INTVAL (op1);
4738 t1 = expand_shift (RSHIFT_EXPR, int_mode, op0,
4739 floor_log2 (d), tquotient, 1);
4740 t2 = expand_binop (int_mode, and_optab, op0,
4741 gen_int_mode (d - 1, int_mode),
4742 NULL_RTX, 1, OPTAB_LIB_WIDEN);
4743 t3 = gen_reg_rtx (int_mode);
4744 t3 = emit_store_flag (t3, NE, t2, const0_rtx, int_mode, 1, 1);
4745 if (t3 == 0)
4747 rtx_code_label *lab;
4748 lab = gen_label_rtx ();
4749 do_cmp_and_jump (t2, const0_rtx, EQ, int_mode, lab);
4750 expand_inc (t1, const1_rtx);
4751 emit_label (lab);
4752 quotient = t1;
4754 else
4755 quotient = force_operand (gen_rtx_PLUS (int_mode, t1, t3),
4756 tquotient);
4757 break;
4760 /* Try using an instruction that produces both the quotient and
4761 remainder, using truncation. We can easily compensate the
4762 quotient or remainder to get ceiling rounding, once we have the
4763 remainder. Notice that we compute also the final remainder
4764 value here, and return the result right away. */
4765 if (target == 0 || GET_MODE (target) != compute_mode)
4766 target = gen_reg_rtx (compute_mode);
4768 if (rem_flag)
4770 remainder = (REG_P (target)
4771 ? target : gen_reg_rtx (compute_mode));
4772 quotient = gen_reg_rtx (compute_mode);
4774 else
4776 quotient = (REG_P (target)
4777 ? target : gen_reg_rtx (compute_mode));
4778 remainder = gen_reg_rtx (compute_mode);
4781 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
4782 remainder, 1))
4784 /* This could be computed with a branch-less sequence.
4785 Save that for later. */
4786 rtx_code_label *label = gen_label_rtx ();
4787 do_cmp_and_jump (remainder, const0_rtx, EQ,
4788 compute_mode, label);
4789 expand_inc (quotient, const1_rtx);
4790 expand_dec (remainder, op1);
4791 emit_label (label);
4792 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4795 /* No luck with division elimination or divmod. Have to do it
4796 by conditionally adjusting op0 *and* the result. */
4798 rtx_code_label *label1, *label2;
4799 rtx adjusted_op0, tem;
4801 quotient = gen_reg_rtx (compute_mode);
4802 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4803 label1 = gen_label_rtx ();
4804 label2 = gen_label_rtx ();
4805 do_cmp_and_jump (adjusted_op0, const0_rtx, NE,
4806 compute_mode, label1);
4807 emit_move_insn (quotient, const0_rtx);
4808 emit_jump_insn (targetm.gen_jump (label2));
4809 emit_barrier ();
4810 emit_label (label1);
4811 expand_dec (adjusted_op0, const1_rtx);
4812 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
4813 quotient, 1, OPTAB_LIB_WIDEN);
4814 if (tem != quotient)
4815 emit_move_insn (quotient, tem);
4816 expand_inc (quotient, const1_rtx);
4817 emit_label (label2);
4820 else /* signed */
4822 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
4823 && INTVAL (op1) >= 0)
4825 /* This is extremely similar to the code for the unsigned case
4826 above. For 2.7 we should merge these variants, but for
4827 2.6.1 I don't want to touch the code for unsigned since that
4828 get used in C. The signed case will only be used by other
4829 languages (Ada). */
4831 rtx t1, t2, t3;
4832 unsigned HOST_WIDE_INT d = INTVAL (op1);
4833 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4834 floor_log2 (d), tquotient, 0);
4835 t2 = expand_binop (compute_mode, and_optab, op0,
4836 gen_int_mode (d - 1, compute_mode),
4837 NULL_RTX, 1, OPTAB_LIB_WIDEN);
4838 t3 = gen_reg_rtx (compute_mode);
4839 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
4840 compute_mode, 1, 1);
4841 if (t3 == 0)
4843 rtx_code_label *lab;
4844 lab = gen_label_rtx ();
4845 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
4846 expand_inc (t1, const1_rtx);
4847 emit_label (lab);
4848 quotient = t1;
4850 else
4851 quotient = force_operand (gen_rtx_PLUS (compute_mode,
4852 t1, t3),
4853 tquotient);
4854 break;
4857 /* Try using an instruction that produces both the quotient and
4858 remainder, using truncation. We can easily compensate the
4859 quotient or remainder to get ceiling rounding, once we have the
4860 remainder. Notice that we compute also the final remainder
4861 value here, and return the result right away. */
4862 if (target == 0 || GET_MODE (target) != compute_mode)
4863 target = gen_reg_rtx (compute_mode);
4864 if (rem_flag)
4866 remainder= (REG_P (target)
4867 ? target : gen_reg_rtx (compute_mode));
4868 quotient = gen_reg_rtx (compute_mode);
4870 else
4872 quotient = (REG_P (target)
4873 ? target : gen_reg_rtx (compute_mode));
4874 remainder = gen_reg_rtx (compute_mode);
4877 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
4878 remainder, 0))
4880 /* This could be computed with a branch-less sequence.
4881 Save that for later. */
4882 rtx tem;
4883 rtx_code_label *label = gen_label_rtx ();
4884 do_cmp_and_jump (remainder, const0_rtx, EQ,
4885 compute_mode, label);
4886 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4887 NULL_RTX, 0, OPTAB_WIDEN);
4888 do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label);
4889 expand_inc (quotient, const1_rtx);
4890 expand_dec (remainder, op1);
4891 emit_label (label);
4892 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4895 /* No luck with division elimination or divmod. Have to do it
4896 by conditionally adjusting op0 *and* the result. */
4898 rtx_code_label *label1, *label2, *label3, *label4, *label5;
4899 rtx adjusted_op0;
4900 rtx tem;
4902 quotient = gen_reg_rtx (compute_mode);
4903 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4904 label1 = gen_label_rtx ();
4905 label2 = gen_label_rtx ();
4906 label3 = gen_label_rtx ();
4907 label4 = gen_label_rtx ();
4908 label5 = gen_label_rtx ();
4909 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
4910 do_cmp_and_jump (adjusted_op0, const0_rtx, GT,
4911 compute_mode, label1);
4912 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4913 quotient, 0, OPTAB_LIB_WIDEN);
4914 if (tem != quotient)
4915 emit_move_insn (quotient, tem);
4916 emit_jump_insn (targetm.gen_jump (label5));
4917 emit_barrier ();
4918 emit_label (label1);
4919 expand_dec (adjusted_op0, const1_rtx);
4920 emit_jump_insn (targetm.gen_jump (label4));
4921 emit_barrier ();
4922 emit_label (label2);
4923 do_cmp_and_jump (adjusted_op0, const0_rtx, LT,
4924 compute_mode, label3);
4925 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4926 quotient, 0, OPTAB_LIB_WIDEN);
4927 if (tem != quotient)
4928 emit_move_insn (quotient, tem);
4929 emit_jump_insn (targetm.gen_jump (label5));
4930 emit_barrier ();
4931 emit_label (label3);
4932 expand_inc (adjusted_op0, const1_rtx);
4933 emit_label (label4);
4934 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4935 quotient, 0, OPTAB_LIB_WIDEN);
4936 if (tem != quotient)
4937 emit_move_insn (quotient, tem);
4938 expand_inc (quotient, const1_rtx);
4939 emit_label (label5);
4942 break;
4944 case EXACT_DIV_EXPR:
4945 if (op1_is_constant && HWI_COMPUTABLE_MODE_P (compute_mode))
4947 scalar_int_mode int_mode = as_a <scalar_int_mode> (compute_mode);
4948 int size = GET_MODE_BITSIZE (int_mode);
4949 HOST_WIDE_INT d = INTVAL (op1);
4950 unsigned HOST_WIDE_INT ml;
4951 int pre_shift;
4952 rtx t1;
4954 pre_shift = ctz_or_zero (d);
4955 ml = invert_mod2n (d >> pre_shift, size);
4956 t1 = expand_shift (RSHIFT_EXPR, int_mode, op0,
4957 pre_shift, NULL_RTX, unsignedp);
4958 quotient = expand_mult (int_mode, t1, gen_int_mode (ml, int_mode),
4959 NULL_RTX, 1);
4961 insn = get_last_insn ();
4962 set_dst_reg_note (insn, REG_EQUAL,
4963 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4964 int_mode, op0, op1),
4965 quotient);
4967 break;
4969 case ROUND_DIV_EXPR:
4970 case ROUND_MOD_EXPR:
4971 if (unsignedp)
4973 scalar_int_mode int_mode = as_a <scalar_int_mode> (compute_mode);
4974 rtx tem;
4975 rtx_code_label *label;
4976 label = gen_label_rtx ();
4977 quotient = gen_reg_rtx (int_mode);
4978 remainder = gen_reg_rtx (int_mode);
4979 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0)
4981 rtx tem;
4982 quotient = expand_binop (int_mode, udiv_optab, op0, op1,
4983 quotient, 1, OPTAB_LIB_WIDEN);
4984 tem = expand_mult (int_mode, quotient, op1, NULL_RTX, 1);
4985 remainder = expand_binop (int_mode, sub_optab, op0, tem,
4986 remainder, 1, OPTAB_LIB_WIDEN);
4988 tem = plus_constant (int_mode, op1, -1);
4989 tem = expand_shift (RSHIFT_EXPR, int_mode, tem, 1, NULL_RTX, 1);
4990 do_cmp_and_jump (remainder, tem, LEU, int_mode, label);
4991 expand_inc (quotient, const1_rtx);
4992 expand_dec (remainder, op1);
4993 emit_label (label);
4995 else
4997 scalar_int_mode int_mode = as_a <scalar_int_mode> (compute_mode);
4998 int size = GET_MODE_BITSIZE (int_mode);
4999 rtx abs_rem, abs_op1, tem, mask;
5000 rtx_code_label *label;
5001 label = gen_label_rtx ();
5002 quotient = gen_reg_rtx (int_mode);
5003 remainder = gen_reg_rtx (int_mode);
5004 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0)
5006 rtx tem;
5007 quotient = expand_binop (int_mode, sdiv_optab, op0, op1,
5008 quotient, 0, OPTAB_LIB_WIDEN);
5009 tem = expand_mult (int_mode, quotient, op1, NULL_RTX, 0);
5010 remainder = expand_binop (int_mode, sub_optab, op0, tem,
5011 remainder, 0, OPTAB_LIB_WIDEN);
5013 abs_rem = expand_abs (int_mode, remainder, NULL_RTX, 1, 0);
5014 abs_op1 = expand_abs (int_mode, op1, NULL_RTX, 1, 0);
5015 tem = expand_shift (LSHIFT_EXPR, int_mode, abs_rem,
5016 1, NULL_RTX, 1);
5017 do_cmp_and_jump (tem, abs_op1, LTU, int_mode, label);
5018 tem = expand_binop (int_mode, xor_optab, op0, op1,
5019 NULL_RTX, 0, OPTAB_WIDEN);
5020 mask = expand_shift (RSHIFT_EXPR, int_mode, tem,
5021 size - 1, NULL_RTX, 0);
5022 tem = expand_binop (int_mode, xor_optab, mask, const1_rtx,
5023 NULL_RTX, 0, OPTAB_WIDEN);
5024 tem = expand_binop (int_mode, sub_optab, tem, mask,
5025 NULL_RTX, 0, OPTAB_WIDEN);
5026 expand_inc (quotient, tem);
5027 tem = expand_binop (int_mode, xor_optab, mask, op1,
5028 NULL_RTX, 0, OPTAB_WIDEN);
5029 tem = expand_binop (int_mode, sub_optab, tem, mask,
5030 NULL_RTX, 0, OPTAB_WIDEN);
5031 expand_dec (remainder, tem);
5032 emit_label (label);
5034 return gen_lowpart (mode, rem_flag ? remainder : quotient);
5036 default:
5037 gcc_unreachable ();
5040 if (quotient == 0)
5042 if (target && GET_MODE (target) != compute_mode)
5043 target = 0;
5045 if (rem_flag)
5047 /* Try to produce the remainder without producing the quotient.
5048 If we seem to have a divmod pattern that does not require widening,
5049 don't try widening here. We should really have a WIDEN argument
5050 to expand_twoval_binop, since what we'd really like to do here is
5051 1) try a mod insn in compute_mode
5052 2) try a divmod insn in compute_mode
5053 3) try a div insn in compute_mode and multiply-subtract to get
5054 remainder
5055 4) try the same things with widening allowed. */
5056 remainder
5057 = sign_expand_binop (compute_mode, umod_optab, smod_optab,
5058 op0, op1, target,
5059 unsignedp,
5060 ((optab_handler (optab2, compute_mode)
5061 != CODE_FOR_nothing)
5062 ? OPTAB_DIRECT : OPTAB_WIDEN));
5063 if (remainder == 0)
5065 /* No luck there. Can we do remainder and divide at once
5066 without a library call? */
5067 remainder = gen_reg_rtx (compute_mode);
5068 if (! expand_twoval_binop ((unsignedp
5069 ? udivmod_optab
5070 : sdivmod_optab),
5071 op0, op1,
5072 NULL_RTX, remainder, unsignedp))
5073 remainder = 0;
5076 if (remainder)
5077 return gen_lowpart (mode, remainder);
5080 /* Produce the quotient. Try a quotient insn, but not a library call.
5081 If we have a divmod in this mode, use it in preference to widening
5082 the div (for this test we assume it will not fail). Note that optab2
5083 is set to the one of the two optabs that the call below will use. */
5084 quotient
5085 = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
5086 op0, op1, rem_flag ? NULL_RTX : target,
5087 unsignedp,
5088 ((optab_handler (optab2, compute_mode)
5089 != CODE_FOR_nothing)
5090 ? OPTAB_DIRECT : OPTAB_WIDEN));
5092 if (quotient == 0)
5094 /* No luck there. Try a quotient-and-remainder insn,
5095 keeping the quotient alone. */
5096 quotient = gen_reg_rtx (compute_mode);
5097 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
5098 op0, op1,
5099 quotient, NULL_RTX, unsignedp))
5101 quotient = 0;
5102 if (! rem_flag)
5103 /* Still no luck. If we are not computing the remainder,
5104 use a library call for the quotient. */
5105 quotient = sign_expand_binop (compute_mode,
5106 udiv_optab, sdiv_optab,
5107 op0, op1, target,
5108 unsignedp, OPTAB_LIB_WIDEN);
5113 if (rem_flag)
5115 if (target && GET_MODE (target) != compute_mode)
5116 target = 0;
5118 if (quotient == 0)
5120 /* No divide instruction either. Use library for remainder. */
5121 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
5122 op0, op1, target,
5123 unsignedp, OPTAB_LIB_WIDEN);
5124 /* No remainder function. Try a quotient-and-remainder
5125 function, keeping the remainder. */
5126 if (!remainder)
5128 remainder = gen_reg_rtx (compute_mode);
5129 if (!expand_twoval_binop_libfunc
5130 (unsignedp ? udivmod_optab : sdivmod_optab,
5131 op0, op1,
5132 NULL_RTX, remainder,
5133 unsignedp ? UMOD : MOD))
5134 remainder = NULL_RTX;
5137 else
5139 /* We divided. Now finish doing X - Y * (X / Y). */
5140 remainder = expand_mult (compute_mode, quotient, op1,
5141 NULL_RTX, unsignedp);
5142 remainder = expand_binop (compute_mode, sub_optab, op0,
5143 remainder, target, unsignedp,
5144 OPTAB_LIB_WIDEN);
5148 return gen_lowpart (mode, rem_flag ? remainder : quotient);
5151 /* Return a tree node with data type TYPE, describing the value of X.
5152 Usually this is an VAR_DECL, if there is no obvious better choice.
5153 X may be an expression, however we only support those expressions
5154 generated by loop.c. */
5156 tree
5157 make_tree (tree type, rtx x)
5159 tree t;
5161 switch (GET_CODE (x))
5163 case CONST_INT:
5164 case CONST_WIDE_INT:
5165 t = wide_int_to_tree (type, rtx_mode_t (x, TYPE_MODE (type)));
5166 return t;
5168 case CONST_DOUBLE:
5169 STATIC_ASSERT (HOST_BITS_PER_WIDE_INT * 2 <= MAX_BITSIZE_MODE_ANY_INT);
5170 if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (x) == VOIDmode)
5171 t = wide_int_to_tree (type,
5172 wide_int::from_array (&CONST_DOUBLE_LOW (x), 2,
5173 HOST_BITS_PER_WIDE_INT * 2));
5174 else
5175 t = build_real (type, *CONST_DOUBLE_REAL_VALUE (x));
5177 return t;
5179 case CONST_VECTOR:
5181 int units = CONST_VECTOR_NUNITS (x);
5182 tree itype = TREE_TYPE (type);
5183 int i;
5185 /* Build a tree with vector elements. */
5186 auto_vec<tree, 32> elts (units);
5187 for (i = 0; i < units; ++i)
5189 rtx elt = CONST_VECTOR_ELT (x, i);
5190 elts.quick_push (make_tree (itype, elt));
5193 return build_vector (type, elts);
5196 case PLUS:
5197 return fold_build2 (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
5198 make_tree (type, XEXP (x, 1)));
5200 case MINUS:
5201 return fold_build2 (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
5202 make_tree (type, XEXP (x, 1)));
5204 case NEG:
5205 return fold_build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0)));
5207 case MULT:
5208 return fold_build2 (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
5209 make_tree (type, XEXP (x, 1)));
5211 case ASHIFT:
5212 return fold_build2 (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
5213 make_tree (type, XEXP (x, 1)));
5215 case LSHIFTRT:
5216 t = unsigned_type_for (type);
5217 return fold_convert (type, build2 (RSHIFT_EXPR, t,
5218 make_tree (t, XEXP (x, 0)),
5219 make_tree (type, XEXP (x, 1))));
5221 case ASHIFTRT:
5222 t = signed_type_for (type);
5223 return fold_convert (type, build2 (RSHIFT_EXPR, t,
5224 make_tree (t, XEXP (x, 0)),
5225 make_tree (type, XEXP (x, 1))));
5227 case DIV:
5228 if (TREE_CODE (type) != REAL_TYPE)
5229 t = signed_type_for (type);
5230 else
5231 t = type;
5233 return fold_convert (type, build2 (TRUNC_DIV_EXPR, t,
5234 make_tree (t, XEXP (x, 0)),
5235 make_tree (t, XEXP (x, 1))));
5236 case UDIV:
5237 t = unsigned_type_for (type);
5238 return fold_convert (type, build2 (TRUNC_DIV_EXPR, t,
5239 make_tree (t, XEXP (x, 0)),
5240 make_tree (t, XEXP (x, 1))));
5242 case SIGN_EXTEND:
5243 case ZERO_EXTEND:
5244 t = lang_hooks.types.type_for_mode (GET_MODE (XEXP (x, 0)),
5245 GET_CODE (x) == ZERO_EXTEND);
5246 return fold_convert (type, make_tree (t, XEXP (x, 0)));
5248 case CONST:
5249 return make_tree (type, XEXP (x, 0));
5251 case SYMBOL_REF:
5252 t = SYMBOL_REF_DECL (x);
5253 if (t)
5254 return fold_convert (type, build_fold_addr_expr (t));
5255 /* fall through. */
5257 default:
5258 t = build_decl (RTL_LOCATION (x), VAR_DECL, NULL_TREE, type);
5260 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5261 address mode to pointer mode. */
5262 if (POINTER_TYPE_P (type))
5263 x = convert_memory_address_addr_space
5264 (SCALAR_INT_TYPE_MODE (type), x, TYPE_ADDR_SPACE (TREE_TYPE (type)));
5266 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5267 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5268 t->decl_with_rtl.rtl = x;
5270 return t;
5274 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5275 and returning TARGET.
5277 If TARGET is 0, a pseudo-register or constant is returned. */
5280 expand_and (machine_mode mode, rtx op0, rtx op1, rtx target)
5282 rtx tem = 0;
5284 if (GET_MODE (op0) == VOIDmode && GET_MODE (op1) == VOIDmode)
5285 tem = simplify_binary_operation (AND, mode, op0, op1);
5286 if (tem == 0)
5287 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
5289 if (target == 0)
5290 target = tem;
5291 else if (tem != target)
5292 emit_move_insn (target, tem);
5293 return target;
5296 /* Helper function for emit_store_flag. */
5298 emit_cstore (rtx target, enum insn_code icode, enum rtx_code code,
5299 machine_mode mode, machine_mode compare_mode,
5300 int unsignedp, rtx x, rtx y, int normalizep,
5301 machine_mode target_mode)
5303 struct expand_operand ops[4];
5304 rtx op0, comparison, subtarget;
5305 rtx_insn *last;
5306 scalar_int_mode result_mode = targetm.cstore_mode (icode);
5307 scalar_int_mode int_target_mode;
5309 last = get_last_insn ();
5310 x = prepare_operand (icode, x, 2, mode, compare_mode, unsignedp);
5311 y = prepare_operand (icode, y, 3, mode, compare_mode, unsignedp);
5312 if (!x || !y)
5314 delete_insns_since (last);
5315 return NULL_RTX;
5318 if (target_mode == VOIDmode)
5319 int_target_mode = result_mode;
5320 else
5321 int_target_mode = as_a <scalar_int_mode> (target_mode);
5322 if (!target)
5323 target = gen_reg_rtx (int_target_mode);
5325 comparison = gen_rtx_fmt_ee (code, result_mode, x, y);
5327 create_output_operand (&ops[0], optimize ? NULL_RTX : target, result_mode);
5328 create_fixed_operand (&ops[1], comparison);
5329 create_fixed_operand (&ops[2], x);
5330 create_fixed_operand (&ops[3], y);
5331 if (!maybe_expand_insn (icode, 4, ops))
5333 delete_insns_since (last);
5334 return NULL_RTX;
5336 subtarget = ops[0].value;
5338 /* If we are converting to a wider mode, first convert to
5339 INT_TARGET_MODE, then normalize. This produces better combining
5340 opportunities on machines that have a SIGN_EXTRACT when we are
5341 testing a single bit. This mostly benefits the 68k.
5343 If STORE_FLAG_VALUE does not have the sign bit set when
5344 interpreted in MODE, we can do this conversion as unsigned, which
5345 is usually more efficient. */
5346 if (GET_MODE_SIZE (int_target_mode) > GET_MODE_SIZE (result_mode))
5348 convert_move (target, subtarget,
5349 val_signbit_known_clear_p (result_mode,
5350 STORE_FLAG_VALUE));
5351 op0 = target;
5352 result_mode = int_target_mode;
5354 else
5355 op0 = subtarget;
5357 /* If we want to keep subexpressions around, don't reuse our last
5358 target. */
5359 if (optimize)
5360 subtarget = 0;
5362 /* Now normalize to the proper value in MODE. Sometimes we don't
5363 have to do anything. */
5364 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
5366 /* STORE_FLAG_VALUE might be the most negative number, so write
5367 the comparison this way to avoid a compiler-time warning. */
5368 else if (- normalizep == STORE_FLAG_VALUE)
5369 op0 = expand_unop (result_mode, neg_optab, op0, subtarget, 0);
5371 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5372 it hard to use a value of just the sign bit due to ANSI integer
5373 constant typing rules. */
5374 else if (val_signbit_known_set_p (result_mode, STORE_FLAG_VALUE))
5375 op0 = expand_shift (RSHIFT_EXPR, result_mode, op0,
5376 GET_MODE_BITSIZE (result_mode) - 1, subtarget,
5377 normalizep == 1);
5378 else
5380 gcc_assert (STORE_FLAG_VALUE & 1);
5382 op0 = expand_and (result_mode, op0, const1_rtx, subtarget);
5383 if (normalizep == -1)
5384 op0 = expand_unop (result_mode, neg_optab, op0, op0, 0);
5387 /* If we were converting to a smaller mode, do the conversion now. */
5388 if (int_target_mode != result_mode)
5390 convert_move (target, op0, 0);
5391 return target;
5393 else
5394 return op0;
5398 /* A subroutine of emit_store_flag only including "tricks" that do not
5399 need a recursive call. These are kept separate to avoid infinite
5400 loops. */
5402 static rtx
5403 emit_store_flag_1 (rtx target, enum rtx_code code, rtx op0, rtx op1,
5404 machine_mode mode, int unsignedp, int normalizep,
5405 machine_mode target_mode)
5407 rtx subtarget;
5408 enum insn_code icode;
5409 machine_mode compare_mode;
5410 enum mode_class mclass;
5411 enum rtx_code scode;
5413 if (unsignedp)
5414 code = unsigned_condition (code);
5415 scode = swap_condition (code);
5417 /* If one operand is constant, make it the second one. Only do this
5418 if the other operand is not constant as well. */
5420 if (swap_commutative_operands_p (op0, op1))
5422 std::swap (op0, op1);
5423 code = swap_condition (code);
5426 if (mode == VOIDmode)
5427 mode = GET_MODE (op0);
5429 /* For some comparisons with 1 and -1, we can convert this to
5430 comparisons with zero. This will often produce more opportunities for
5431 store-flag insns. */
5433 switch (code)
5435 case LT:
5436 if (op1 == const1_rtx)
5437 op1 = const0_rtx, code = LE;
5438 break;
5439 case LE:
5440 if (op1 == constm1_rtx)
5441 op1 = const0_rtx, code = LT;
5442 break;
5443 case GE:
5444 if (op1 == const1_rtx)
5445 op1 = const0_rtx, code = GT;
5446 break;
5447 case GT:
5448 if (op1 == constm1_rtx)
5449 op1 = const0_rtx, code = GE;
5450 break;
5451 case GEU:
5452 if (op1 == const1_rtx)
5453 op1 = const0_rtx, code = NE;
5454 break;
5455 case LTU:
5456 if (op1 == const1_rtx)
5457 op1 = const0_rtx, code = EQ;
5458 break;
5459 default:
5460 break;
5463 /* If we are comparing a double-word integer with zero or -1, we can
5464 convert the comparison into one involving a single word. */
5465 scalar_int_mode int_mode;
5466 if (is_int_mode (mode, &int_mode)
5467 && GET_MODE_BITSIZE (int_mode) == BITS_PER_WORD * 2
5468 && (!MEM_P (op0) || ! MEM_VOLATILE_P (op0)))
5470 rtx tem;
5471 if ((code == EQ || code == NE)
5472 && (op1 == const0_rtx || op1 == constm1_rtx))
5474 rtx op00, op01;
5476 /* Do a logical OR or AND of the two words and compare the
5477 result. */
5478 op00 = simplify_gen_subreg (word_mode, op0, int_mode, 0);
5479 op01 = simplify_gen_subreg (word_mode, op0, int_mode, UNITS_PER_WORD);
5480 tem = expand_binop (word_mode,
5481 op1 == const0_rtx ? ior_optab : and_optab,
5482 op00, op01, NULL_RTX, unsignedp,
5483 OPTAB_DIRECT);
5485 if (tem != 0)
5486 tem = emit_store_flag (NULL_RTX, code, tem, op1, word_mode,
5487 unsignedp, normalizep);
5489 else if ((code == LT || code == GE) && op1 == const0_rtx)
5491 rtx op0h;
5493 /* If testing the sign bit, can just test on high word. */
5494 op0h = simplify_gen_subreg (word_mode, op0, int_mode,
5495 subreg_highpart_offset (word_mode,
5496 int_mode));
5497 tem = emit_store_flag (NULL_RTX, code, op0h, op1, word_mode,
5498 unsignedp, normalizep);
5500 else
5501 tem = NULL_RTX;
5503 if (tem)
5505 if (target_mode == VOIDmode || GET_MODE (tem) == target_mode)
5506 return tem;
5507 if (!target)
5508 target = gen_reg_rtx (target_mode);
5510 convert_move (target, tem,
5511 !val_signbit_known_set_p (word_mode,
5512 (normalizep ? normalizep
5513 : STORE_FLAG_VALUE)));
5514 return target;
5518 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5519 complement of A (for GE) and shifting the sign bit to the low bit. */
5520 if (op1 == const0_rtx && (code == LT || code == GE)
5521 && is_int_mode (mode, &int_mode)
5522 && (normalizep || STORE_FLAG_VALUE == 1
5523 || val_signbit_p (int_mode, STORE_FLAG_VALUE)))
5525 scalar_int_mode int_target_mode;
5526 subtarget = target;
5528 if (!target)
5529 int_target_mode = int_mode;
5530 else
5532 /* If the result is to be wider than OP0, it is best to convert it
5533 first. If it is to be narrower, it is *incorrect* to convert it
5534 first. */
5535 int_target_mode = as_a <scalar_int_mode> (target_mode);
5536 if (GET_MODE_SIZE (int_target_mode) > GET_MODE_SIZE (int_mode))
5538 op0 = convert_modes (int_target_mode, int_mode, op0, 0);
5539 int_mode = int_target_mode;
5543 if (int_target_mode != int_mode)
5544 subtarget = 0;
5546 if (code == GE)
5547 op0 = expand_unop (int_mode, one_cmpl_optab, op0,
5548 ((STORE_FLAG_VALUE == 1 || normalizep)
5549 ? 0 : subtarget), 0);
5551 if (STORE_FLAG_VALUE == 1 || normalizep)
5552 /* If we are supposed to produce a 0/1 value, we want to do
5553 a logical shift from the sign bit to the low-order bit; for
5554 a -1/0 value, we do an arithmetic shift. */
5555 op0 = expand_shift (RSHIFT_EXPR, int_mode, op0,
5556 GET_MODE_BITSIZE (int_mode) - 1,
5557 subtarget, normalizep != -1);
5559 if (int_mode != int_target_mode)
5560 op0 = convert_modes (int_target_mode, int_mode, op0, 0);
5562 return op0;
5565 mclass = GET_MODE_CLASS (mode);
5566 FOR_EACH_MODE_FROM (compare_mode, mode)
5568 machine_mode optab_mode = mclass == MODE_CC ? CCmode : compare_mode;
5569 icode = optab_handler (cstore_optab, optab_mode);
5570 if (icode != CODE_FOR_nothing)
5572 do_pending_stack_adjust ();
5573 rtx tem = emit_cstore (target, icode, code, mode, compare_mode,
5574 unsignedp, op0, op1, normalizep, target_mode);
5575 if (tem)
5576 return tem;
5578 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5580 tem = emit_cstore (target, icode, scode, mode, compare_mode,
5581 unsignedp, op1, op0, normalizep, target_mode);
5582 if (tem)
5583 return tem;
5585 break;
5589 return 0;
5592 /* Subroutine of emit_store_flag that handles cases in which the operands
5593 are scalar integers. SUBTARGET is the target to use for temporary
5594 operations and TRUEVAL is the value to store when the condition is
5595 true. All other arguments are as for emit_store_flag. */
5598 emit_store_flag_int (rtx target, rtx subtarget, enum rtx_code code, rtx op0,
5599 rtx op1, scalar_int_mode mode, int unsignedp,
5600 int normalizep, rtx trueval)
5602 machine_mode target_mode = target ? GET_MODE (target) : VOIDmode;
5603 rtx_insn *last = get_last_insn ();
5605 /* If this is an equality comparison of integers, we can try to exclusive-or
5606 (or subtract) the two operands and use a recursive call to try the
5607 comparison with zero. Don't do any of these cases if branches are
5608 very cheap. */
5610 if ((code == EQ || code == NE) && op1 != const0_rtx)
5612 rtx tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
5613 OPTAB_WIDEN);
5615 if (tem == 0)
5616 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
5617 OPTAB_WIDEN);
5618 if (tem != 0)
5619 tem = emit_store_flag (target, code, tem, const0_rtx,
5620 mode, unsignedp, normalizep);
5621 if (tem != 0)
5622 return tem;
5624 delete_insns_since (last);
5627 /* For integer comparisons, try the reverse comparison. However, for
5628 small X and if we'd have anyway to extend, implementing "X != 0"
5629 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5630 rtx_code rcode = reverse_condition (code);
5631 if (can_compare_p (rcode, mode, ccp_store_flag)
5632 && ! (optab_handler (cstore_optab, mode) == CODE_FOR_nothing
5633 && code == NE
5634 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5635 && op1 == const0_rtx))
5637 int want_add = ((STORE_FLAG_VALUE == 1 && normalizep == -1)
5638 || (STORE_FLAG_VALUE == -1 && normalizep == 1));
5640 /* Again, for the reverse comparison, use either an addition or a XOR. */
5641 if (want_add
5642 && rtx_cost (GEN_INT (normalizep), mode, PLUS, 1,
5643 optimize_insn_for_speed_p ()) == 0)
5645 rtx tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5646 STORE_FLAG_VALUE, target_mode);
5647 if (tem != 0)
5648 tem = expand_binop (target_mode, add_optab, tem,
5649 gen_int_mode (normalizep, target_mode),
5650 target, 0, OPTAB_WIDEN);
5651 if (tem != 0)
5652 return tem;
5654 else if (!want_add
5655 && rtx_cost (trueval, mode, XOR, 1,
5656 optimize_insn_for_speed_p ()) == 0)
5658 rtx tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5659 normalizep, target_mode);
5660 if (tem != 0)
5661 tem = expand_binop (target_mode, xor_optab, tem, trueval, target,
5662 INTVAL (trueval) >= 0, OPTAB_WIDEN);
5663 if (tem != 0)
5664 return tem;
5667 delete_insns_since (last);
5670 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5671 the constant zero. Reject all other comparisons at this point. Only
5672 do LE and GT if branches are expensive since they are expensive on
5673 2-operand machines. */
5675 if (op1 != const0_rtx
5676 || (code != EQ && code != NE
5677 && (BRANCH_COST (optimize_insn_for_speed_p (),
5678 false) <= 1 || (code != LE && code != GT))))
5679 return 0;
5681 /* Try to put the result of the comparison in the sign bit. Assume we can't
5682 do the necessary operation below. */
5684 rtx tem = 0;
5686 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5687 the sign bit set. */
5689 if (code == LE)
5691 /* This is destructive, so SUBTARGET can't be OP0. */
5692 if (rtx_equal_p (subtarget, op0))
5693 subtarget = 0;
5695 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
5696 OPTAB_WIDEN);
5697 if (tem)
5698 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
5699 OPTAB_WIDEN);
5702 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5703 number of bits in the mode of OP0, minus one. */
5705 if (code == GT)
5707 if (rtx_equal_p (subtarget, op0))
5708 subtarget = 0;
5710 tem = maybe_expand_shift (RSHIFT_EXPR, mode, op0,
5711 GET_MODE_BITSIZE (mode) - 1,
5712 subtarget, 0);
5713 if (tem)
5714 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
5715 OPTAB_WIDEN);
5718 if (code == EQ || code == NE)
5720 /* For EQ or NE, one way to do the comparison is to apply an operation
5721 that converts the operand into a positive number if it is nonzero
5722 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5723 for NE we negate. This puts the result in the sign bit. Then we
5724 normalize with a shift, if needed.
5726 Two operations that can do the above actions are ABS and FFS, so try
5727 them. If that doesn't work, and MODE is smaller than a full word,
5728 we can use zero-extension to the wider mode (an unsigned conversion)
5729 as the operation. */
5731 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5732 that is compensated by the subsequent overflow when subtracting
5733 one / negating. */
5735 if (optab_handler (abs_optab, mode) != CODE_FOR_nothing)
5736 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
5737 else if (optab_handler (ffs_optab, mode) != CODE_FOR_nothing)
5738 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
5739 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5741 tem = convert_modes (word_mode, mode, op0, 1);
5742 mode = word_mode;
5745 if (tem != 0)
5747 if (code == EQ)
5748 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
5749 0, OPTAB_WIDEN);
5750 else
5751 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
5754 /* If we couldn't do it that way, for NE we can "or" the two's complement
5755 of the value with itself. For EQ, we take the one's complement of
5756 that "or", which is an extra insn, so we only handle EQ if branches
5757 are expensive. */
5759 if (tem == 0
5760 && (code == NE
5761 || BRANCH_COST (optimize_insn_for_speed_p (),
5762 false) > 1))
5764 if (rtx_equal_p (subtarget, op0))
5765 subtarget = 0;
5767 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
5768 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
5769 OPTAB_WIDEN);
5771 if (tem && code == EQ)
5772 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
5776 if (tem && normalizep)
5777 tem = maybe_expand_shift (RSHIFT_EXPR, mode, tem,
5778 GET_MODE_BITSIZE (mode) - 1,
5779 subtarget, normalizep == 1);
5781 if (tem)
5783 if (!target)
5785 else if (GET_MODE (tem) != target_mode)
5787 convert_move (target, tem, 0);
5788 tem = target;
5790 else if (!subtarget)
5792 emit_move_insn (target, tem);
5793 tem = target;
5796 else
5797 delete_insns_since (last);
5799 return tem;
5802 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5803 and storing in TARGET. Normally return TARGET.
5804 Return 0 if that cannot be done.
5806 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5807 it is VOIDmode, they cannot both be CONST_INT.
5809 UNSIGNEDP is for the case where we have to widen the operands
5810 to perform the operation. It says to use zero-extension.
5812 NORMALIZEP is 1 if we should convert the result to be either zero
5813 or one. Normalize is -1 if we should convert the result to be
5814 either zero or -1. If NORMALIZEP is zero, the result will be left
5815 "raw" out of the scc insn. */
5818 emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
5819 machine_mode mode, int unsignedp, int normalizep)
5821 machine_mode target_mode = target ? GET_MODE (target) : VOIDmode;
5822 enum rtx_code rcode;
5823 rtx subtarget;
5824 rtx tem, trueval;
5825 rtx_insn *last;
5827 /* If we compare constants, we shouldn't use a store-flag operation,
5828 but a constant load. We can get there via the vanilla route that
5829 usually generates a compare-branch sequence, but will in this case
5830 fold the comparison to a constant, and thus elide the branch. */
5831 if (CONSTANT_P (op0) && CONSTANT_P (op1))
5832 return NULL_RTX;
5834 tem = emit_store_flag_1 (target, code, op0, op1, mode, unsignedp, normalizep,
5835 target_mode);
5836 if (tem)
5837 return tem;
5839 /* If we reached here, we can't do this with a scc insn, however there
5840 are some comparisons that can be done in other ways. Don't do any
5841 of these cases if branches are very cheap. */
5842 if (BRANCH_COST (optimize_insn_for_speed_p (), false) == 0)
5843 return 0;
5845 /* See what we need to return. We can only return a 1, -1, or the
5846 sign bit. */
5848 if (normalizep == 0)
5850 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5851 normalizep = STORE_FLAG_VALUE;
5853 else if (val_signbit_p (mode, STORE_FLAG_VALUE))
5855 else
5856 return 0;
5859 last = get_last_insn ();
5861 /* If optimizing, use different pseudo registers for each insn, instead
5862 of reusing the same pseudo. This leads to better CSE, but slows
5863 down the compiler, since there are more pseudos. */
5864 subtarget = (!optimize
5865 && (target_mode == mode)) ? target : NULL_RTX;
5866 trueval = GEN_INT (normalizep ? normalizep : STORE_FLAG_VALUE);
5868 /* For floating-point comparisons, try the reverse comparison or try
5869 changing the "orderedness" of the comparison. */
5870 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5872 enum rtx_code first_code;
5873 bool and_them;
5875 rcode = reverse_condition_maybe_unordered (code);
5876 if (can_compare_p (rcode, mode, ccp_store_flag)
5877 && (code == ORDERED || code == UNORDERED
5878 || (! HONOR_NANS (mode) && (code == LTGT || code == UNEQ))
5879 || (! HONOR_SNANS (mode) && (code == EQ || code == NE))))
5881 int want_add = ((STORE_FLAG_VALUE == 1 && normalizep == -1)
5882 || (STORE_FLAG_VALUE == -1 && normalizep == 1));
5884 /* For the reverse comparison, use either an addition or a XOR. */
5885 if (want_add
5886 && rtx_cost (GEN_INT (normalizep), mode, PLUS, 1,
5887 optimize_insn_for_speed_p ()) == 0)
5889 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5890 STORE_FLAG_VALUE, target_mode);
5891 if (tem)
5892 return expand_binop (target_mode, add_optab, tem,
5893 gen_int_mode (normalizep, target_mode),
5894 target, 0, OPTAB_WIDEN);
5896 else if (!want_add
5897 && rtx_cost (trueval, mode, XOR, 1,
5898 optimize_insn_for_speed_p ()) == 0)
5900 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5901 normalizep, target_mode);
5902 if (tem)
5903 return expand_binop (target_mode, xor_optab, tem, trueval,
5904 target, INTVAL (trueval) >= 0,
5905 OPTAB_WIDEN);
5909 delete_insns_since (last);
5911 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5912 if (code == ORDERED || code == UNORDERED)
5913 return 0;
5915 and_them = split_comparison (code, mode, &first_code, &code);
5917 /* If there are no NaNs, the first comparison should always fall through.
5918 Effectively change the comparison to the other one. */
5919 if (!HONOR_NANS (mode))
5921 gcc_assert (first_code == (and_them ? ORDERED : UNORDERED));
5922 return emit_store_flag_1 (target, code, op0, op1, mode, 0, normalizep,
5923 target_mode);
5926 if (!HAVE_conditional_move)
5927 return 0;
5929 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5930 conditional move. */
5931 tem = emit_store_flag_1 (subtarget, first_code, op0, op1, mode, 0,
5932 normalizep, target_mode);
5933 if (tem == 0)
5934 return 0;
5936 if (and_them)
5937 tem = emit_conditional_move (target, code, op0, op1, mode,
5938 tem, const0_rtx, GET_MODE (tem), 0);
5939 else
5940 tem = emit_conditional_move (target, code, op0, op1, mode,
5941 trueval, tem, GET_MODE (tem), 0);
5943 if (tem == 0)
5944 delete_insns_since (last);
5945 return tem;
5948 /* The remaining tricks only apply to integer comparisons. */
5950 scalar_int_mode int_mode;
5951 if (is_int_mode (mode, &int_mode))
5952 return emit_store_flag_int (target, subtarget, code, op0, op1, int_mode,
5953 unsignedp, normalizep, trueval);
5955 return 0;
5958 /* Like emit_store_flag, but always succeeds. */
5961 emit_store_flag_force (rtx target, enum rtx_code code, rtx op0, rtx op1,
5962 machine_mode mode, int unsignedp, int normalizep)
5964 rtx tem;
5965 rtx_code_label *label;
5966 rtx trueval, falseval;
5968 /* First see if emit_store_flag can do the job. */
5969 tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep);
5970 if (tem != 0)
5971 return tem;
5973 if (!target)
5974 target = gen_reg_rtx (word_mode);
5976 /* If this failed, we have to do this with set/compare/jump/set code.
5977 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5978 trueval = normalizep ? GEN_INT (normalizep) : const1_rtx;
5979 if (code == NE
5980 && GET_MODE_CLASS (mode) == MODE_INT
5981 && REG_P (target)
5982 && op0 == target
5983 && op1 == const0_rtx)
5985 label = gen_label_rtx ();
5986 do_compare_rtx_and_jump (target, const0_rtx, EQ, unsignedp, mode,
5987 NULL_RTX, NULL, label,
5988 profile_probability::uninitialized ());
5989 emit_move_insn (target, trueval);
5990 emit_label (label);
5991 return target;
5994 if (!REG_P (target)
5995 || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
5996 target = gen_reg_rtx (GET_MODE (target));
5998 /* Jump in the right direction if the target cannot implement CODE
5999 but can jump on its reverse condition. */
6000 falseval = const0_rtx;
6001 if (! can_compare_p (code, mode, ccp_jump)
6002 && (! FLOAT_MODE_P (mode)
6003 || code == ORDERED || code == UNORDERED
6004 || (! HONOR_NANS (mode) && (code == LTGT || code == UNEQ))
6005 || (! HONOR_SNANS (mode) && (code == EQ || code == NE))))
6007 enum rtx_code rcode;
6008 if (FLOAT_MODE_P (mode))
6009 rcode = reverse_condition_maybe_unordered (code);
6010 else
6011 rcode = reverse_condition (code);
6013 /* Canonicalize to UNORDERED for the libcall. */
6014 if (can_compare_p (rcode, mode, ccp_jump)
6015 || (code == ORDERED && ! can_compare_p (ORDERED, mode, ccp_jump)))
6017 falseval = trueval;
6018 trueval = const0_rtx;
6019 code = rcode;
6023 emit_move_insn (target, trueval);
6024 label = gen_label_rtx ();
6025 do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX, NULL,
6026 label, profile_probability::uninitialized ());
6028 emit_move_insn (target, falseval);
6029 emit_label (label);
6031 return target;
6034 /* Perform possibly multi-word comparison and conditional jump to LABEL
6035 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
6036 now a thin wrapper around do_compare_rtx_and_jump. */
6038 static void
6039 do_cmp_and_jump (rtx arg1, rtx arg2, enum rtx_code op, machine_mode mode,
6040 rtx_code_label *label)
6042 int unsignedp = (op == LTU || op == LEU || op == GTU || op == GEU);
6043 do_compare_rtx_and_jump (arg1, arg2, op, unsignedp, mode, NULL_RTX,
6044 NULL, label, profile_probability::uninitialized ());