1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
36 #include "diagnostic-core.h"
42 #include "target-def.h"
46 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
47 #include "sched-int.h"
48 #include "insn-codes.h"
51 enum reg_class regno_reg_class
[] =
53 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
54 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
55 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
56 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
57 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
58 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
63 /* The minimum number of integer registers that we want to save with the
64 movem instruction. Using two movel instructions instead of a single
65 moveml is about 15% faster for the 68020 and 68030 at no expense in
67 #define MIN_MOVEM_REGS 3
69 /* The minimum number of floating point registers that we want to save
70 with the fmovem instruction. */
71 #define MIN_FMOVEM_REGS 1
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
91 unsigned int fpu_mask
;
93 /* Offsets relative to ARG_POINTER. */
94 HOST_WIDE_INT frame_pointer_offset
;
95 HOST_WIDE_INT stack_pointer_offset
;
97 /* Function which the above information refers to. */
101 /* Current frame information calculated by m68k_compute_frame_layout(). */
102 static struct m68k_frame current_frame
;
104 /* Structure describing an m68k address.
106 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
107 with null fields evaluating to 0. Here:
109 - BASE satisfies m68k_legitimate_base_reg_p
110 - INDEX satisfies m68k_legitimate_index_reg_p
111 - OFFSET satisfies m68k_legitimate_constant_address_p
113 INDEX is either HImode or SImode. The other fields are SImode.
115 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
116 the address is (BASE)+. */
117 struct m68k_address
{
125 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
126 static int m68k_sched_issue_rate (void);
127 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
128 static void m68k_sched_md_init_global (FILE *, int, int);
129 static void m68k_sched_md_finish_global (FILE *, int);
130 static void m68k_sched_md_init (FILE *, int, int);
131 static void m68k_sched_dfa_pre_advance_cycle (void);
132 static void m68k_sched_dfa_post_advance_cycle (void);
133 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
135 static bool m68k_can_eliminate (const int, const int);
136 static bool m68k_legitimate_address_p (enum machine_mode
, rtx
, bool);
137 static bool m68k_handle_option (size_t, const char *, int);
138 static void m68k_option_override (void);
139 static rtx
find_addr_reg (rtx
);
140 static const char *singlemove_string (rtx
*);
141 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
142 HOST_WIDE_INT
, tree
);
143 static rtx
m68k_struct_value_rtx (tree
, int);
144 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
145 tree args
, int flags
,
147 static void m68k_compute_frame_layout (void);
148 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
149 static bool m68k_ok_for_sibcall_p (tree
, tree
);
150 static bool m68k_tls_symbol_p (rtx
);
151 static rtx
m68k_legitimize_address (rtx
, rtx
, enum machine_mode
);
152 static bool m68k_rtx_costs (rtx
, int, int, int *, bool);
153 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
154 static bool m68k_return_in_memory (const_tree
, const_tree
);
156 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
157 static void m68k_trampoline_init (rtx
, tree
, rtx
);
158 static int m68k_return_pops_args (tree
, tree
, int);
159 static rtx
m68k_delegitimize_address (rtx
);
160 static void m68k_function_arg_advance (CUMULATIVE_ARGS
*, enum machine_mode
,
162 static rtx
m68k_function_arg (CUMULATIVE_ARGS
*, enum machine_mode
,
166 /* Specify the identification number of the library being built */
167 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
169 /* Initialize the GCC target structure. */
171 #if INT_OP_GROUP == INT_OP_DOT_WORD
172 #undef TARGET_ASM_ALIGNED_HI_OP
173 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
176 #if INT_OP_GROUP == INT_OP_NO_DOT
177 #undef TARGET_ASM_BYTE_OP
178 #define TARGET_ASM_BYTE_OP "\tbyte\t"
179 #undef TARGET_ASM_ALIGNED_HI_OP
180 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
181 #undef TARGET_ASM_ALIGNED_SI_OP
182 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
185 #if INT_OP_GROUP == INT_OP_DC
186 #undef TARGET_ASM_BYTE_OP
187 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
188 #undef TARGET_ASM_ALIGNED_HI_OP
189 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
190 #undef TARGET_ASM_ALIGNED_SI_OP
191 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
194 #undef TARGET_ASM_UNALIGNED_HI_OP
195 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
196 #undef TARGET_ASM_UNALIGNED_SI_OP
197 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
199 #undef TARGET_ASM_OUTPUT_MI_THUNK
200 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
201 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
202 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
204 #undef TARGET_ASM_FILE_START_APP_OFF
205 #define TARGET_ASM_FILE_START_APP_OFF true
207 #undef TARGET_LEGITIMIZE_ADDRESS
208 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
210 #undef TARGET_SCHED_ADJUST_COST
211 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
213 #undef TARGET_SCHED_ISSUE_RATE
214 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
216 #undef TARGET_SCHED_VARIABLE_ISSUE
217 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
219 #undef TARGET_SCHED_INIT_GLOBAL
220 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
222 #undef TARGET_SCHED_FINISH_GLOBAL
223 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
225 #undef TARGET_SCHED_INIT
226 #define TARGET_SCHED_INIT m68k_sched_md_init
228 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
229 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
231 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
232 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
234 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
235 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
236 m68k_sched_first_cycle_multipass_dfa_lookahead
238 #undef TARGET_HANDLE_OPTION
239 #define TARGET_HANDLE_OPTION m68k_handle_option
241 #undef TARGET_OPTION_OVERRIDE
242 #define TARGET_OPTION_OVERRIDE m68k_option_override
244 #undef TARGET_RTX_COSTS
245 #define TARGET_RTX_COSTS m68k_rtx_costs
247 #undef TARGET_ATTRIBUTE_TABLE
248 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
250 #undef TARGET_PROMOTE_PROTOTYPES
251 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
253 #undef TARGET_STRUCT_VALUE_RTX
254 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
256 #undef TARGET_CANNOT_FORCE_CONST_MEM
257 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
259 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
260 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
262 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
263 #undef TARGET_RETURN_IN_MEMORY
264 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
268 #undef TARGET_HAVE_TLS
269 #define TARGET_HAVE_TLS (true)
271 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
272 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
275 #undef TARGET_LEGITIMATE_ADDRESS_P
276 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
278 #undef TARGET_CAN_ELIMINATE
279 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
281 #undef TARGET_TRAMPOLINE_INIT
282 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
284 #undef TARGET_RETURN_POPS_ARGS
285 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
287 #undef TARGET_DELEGITIMIZE_ADDRESS
288 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
290 #undef TARGET_FUNCTION_ARG
291 #define TARGET_FUNCTION_ARG m68k_function_arg
293 #undef TARGET_FUNCTION_ARG_ADVANCE
294 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
296 static const struct attribute_spec m68k_attribute_table
[] =
298 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
299 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
300 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
301 { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
302 { NULL
, 0, 0, false, false, false, NULL
}
305 struct gcc_target targetm
= TARGET_INITIALIZER
;
307 /* Base flags for 68k ISAs. */
308 #define FL_FOR_isa_00 FL_ISA_68000
309 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
310 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
311 generated 68881 code for 68020 and 68030 targets unless explicitly told
313 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
314 | FL_BITFIELD | FL_68881)
315 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
316 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
318 /* Base flags for ColdFire ISAs. */
319 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
320 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
321 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
322 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
323 /* ISA_C is not upwardly compatible with ISA_B. */
324 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
328 /* Traditional 68000 instruction sets. */
334 /* ColdFire instruction set variants. */
342 /* Information about one of the -march, -mcpu or -mtune arguments. */
343 struct m68k_target_selection
345 /* The argument being described. */
348 /* For -mcpu, this is the device selected by the option.
349 For -mtune and -march, it is a representative device
350 for the microarchitecture or ISA respectively. */
351 enum target_device device
;
353 /* The M68K_DEVICE fields associated with DEVICE. See the comment
354 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
356 enum uarch_type microarch
;
361 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
362 static const struct m68k_target_selection all_devices
[] =
364 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
365 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
366 #include "m68k-devices.def"
368 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
371 /* A list of all ISAs, mapping each one to a representative device.
372 Used for -march selection. */
373 static const struct m68k_target_selection all_isas
[] =
375 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
376 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
377 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
378 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
379 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
380 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
381 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
382 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
384 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
386 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
387 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
389 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
392 /* A list of all microarchitectures, mapping each one to a representative
393 device. Used for -mtune selection. */
394 static const struct m68k_target_selection all_microarchs
[] =
396 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
397 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
398 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
399 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
400 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
401 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
402 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
403 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
404 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
405 { "cfv1", mcf51qe
, NULL
, ucfv1
, isa_c
, FL_FOR_isa_c
},
406 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
407 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
409 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
410 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
414 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
417 /* The entries associated with the -mcpu, -march and -mtune settings,
418 or null for options that have not been used. */
419 const struct m68k_target_selection
*m68k_cpu_entry
;
420 const struct m68k_target_selection
*m68k_arch_entry
;
421 const struct m68k_target_selection
*m68k_tune_entry
;
423 /* Which CPU we are generating code for. */
424 enum target_device m68k_cpu
;
426 /* Which microarchitecture to tune for. */
427 enum uarch_type m68k_tune
;
429 /* Which FPU to use. */
430 enum fpu_type m68k_fpu
;
432 /* The set of FL_* flags that apply to the target processor. */
433 unsigned int m68k_cpu_flags
;
435 /* The set of FL_* flags that apply to the processor to be tuned for. */
436 unsigned int m68k_tune_flags
;
438 /* Asm templates for calling or jumping to an arbitrary symbolic address,
439 or NULL if such calls or jumps are not supported. The address is held
441 const char *m68k_symbolic_call
;
442 const char *m68k_symbolic_jump
;
444 /* Enum variable that corresponds to m68k_symbolic_call values. */
445 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
448 /* See whether TABLE has an entry with name NAME. Return true and
449 store the entry in *ENTRY if so, otherwise return false and
450 leave *ENTRY alone. */
453 m68k_find_selection (const struct m68k_target_selection
**entry
,
454 const struct m68k_target_selection
*table
,
459 for (i
= 0; table
[i
].name
; i
++)
460 if (strcmp (table
[i
].name
, name
) == 0)
468 /* Implement TARGET_HANDLE_OPTION. */
471 m68k_handle_option (size_t code
, const char *arg
, int value
)
476 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
479 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
482 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
485 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
488 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
491 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
494 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
497 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
500 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
504 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
507 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
511 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
514 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
516 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
519 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
521 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
524 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
527 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
530 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
533 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
537 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
539 case OPT_mshared_library_id_
:
540 if (value
> MAX_LIBRARY_ID
)
541 error ("-mshared-library-id=%s is not between 0 and %d",
542 arg
, MAX_LIBRARY_ID
);
546 asprintf (&tmp
, "%d", (value
* -4) - 4);
547 m68k_library_id_string
= tmp
;
556 /* Implement TARGET_OPTION_OVERRIDE. */
559 m68k_option_override (void)
561 const struct m68k_target_selection
*entry
;
562 unsigned long target_mask
;
570 -march=ARCH should generate code that runs any processor
571 implementing architecture ARCH. -mcpu=CPU should override -march
572 and should generate code that runs on processor CPU, making free
573 use of any instructions that CPU understands. -mtune=UARCH applies
574 on top of -mcpu or -march and optimizes the code for UARCH. It does
575 not change the target architecture. */
578 /* Complain if the -march setting is for a different microarchitecture,
579 or includes flags that the -mcpu setting doesn't. */
581 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
582 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
583 warning (0, "-mcpu=%s conflicts with -march=%s",
584 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
586 entry
= m68k_cpu_entry
;
589 entry
= m68k_arch_entry
;
592 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
594 m68k_cpu_flags
= entry
->flags
;
596 /* Use the architecture setting to derive default values for
600 /* ColdFire is lenient about alignment. */
601 if (!TARGET_COLDFIRE
)
602 target_mask
|= MASK_STRICT_ALIGNMENT
;
604 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
605 target_mask
|= MASK_BITFIELD
;
606 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
607 target_mask
|= MASK_CF_HWDIV
;
608 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
609 target_mask
|= MASK_HARD_FLOAT
;
610 target_flags
|= target_mask
& ~target_flags_explicit
;
612 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
613 m68k_cpu
= entry
->device
;
616 m68k_tune
= m68k_tune_entry
->microarch
;
617 m68k_tune_flags
= m68k_tune_entry
->flags
;
619 #ifdef M68K_DEFAULT_TUNE
620 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
622 enum target_device dev
;
623 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
624 m68k_tune_flags
= all_devices
[dev
]->flags
;
629 m68k_tune
= entry
->microarch
;
630 m68k_tune_flags
= entry
->flags
;
633 /* Set the type of FPU. */
634 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
635 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
638 /* Sanity check to ensure that msep-data and mid-sahred-library are not
639 * both specified together. Doing so simply doesn't make sense.
641 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
642 error ("cannot specify both -msep-data and -mid-shared-library");
644 /* If we're generating code for a separate A5 relative data segment,
645 * we've got to enable -fPIC as well. This might be relaxable to
646 * -fpic but it hasn't been tested properly.
648 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
651 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
652 error if the target does not support them. */
653 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
654 error ("-mpcrel -fPIC is not currently supported on selected cpu");
656 /* ??? A historic way of turning on pic, or is this intended to
657 be an embedded thing that doesn't have the same name binding
658 significance that it does on hosted ELF systems? */
659 if (TARGET_PCREL
&& flag_pic
== 0)
664 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
666 m68k_symbolic_jump
= "jra %a0";
668 else if (TARGET_ID_SHARED_LIBRARY
)
669 /* All addresses must be loaded from the GOT. */
671 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
674 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
676 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
679 /* No unconditional long branch */;
680 else if (TARGET_PCREL
)
681 m68k_symbolic_jump
= "bra%.l %c0";
683 m68k_symbolic_jump
= "bra%.l %p0";
684 /* Turn off function cse if we are doing PIC. We always want
685 function call to be done as `bsr foo@PLTPC'. */
686 /* ??? It's traditional to do this for -mpcrel too, but it isn't
687 clear how intentional that is. */
688 flag_no_function_cse
= 1;
691 switch (m68k_symbolic_call_var
)
693 case M68K_SYMBOLIC_CALL_JSR
:
694 m68k_symbolic_call
= "jsr %a0";
697 case M68K_SYMBOLIC_CALL_BSR_C
:
698 m68k_symbolic_call
= "bsr%.l %c0";
701 case M68K_SYMBOLIC_CALL_BSR_P
:
702 m68k_symbolic_call
= "bsr%.l %p0";
705 case M68K_SYMBOLIC_CALL_NONE
:
706 gcc_assert (m68k_symbolic_call
== NULL
);
713 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
714 if (align_labels
> 2)
716 warning (0, "-falign-labels=%d is not supported", align_labels
);
721 warning (0, "-falign-loops=%d is not supported", align_loops
);
726 SUBTARGET_OVERRIDE_OPTIONS
;
728 /* Setup scheduling options. */
730 m68k_sched_cpu
= CPU_CFV1
;
732 m68k_sched_cpu
= CPU_CFV2
;
734 m68k_sched_cpu
= CPU_CFV3
;
736 m68k_sched_cpu
= CPU_CFV4
;
739 m68k_sched_cpu
= CPU_UNKNOWN
;
740 flag_schedule_insns
= 0;
741 flag_schedule_insns_after_reload
= 0;
742 flag_modulo_sched
= 0;
745 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
747 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
748 m68k_sched_mac
= MAC_CF_EMAC
;
749 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
750 m68k_sched_mac
= MAC_CF_MAC
;
752 m68k_sched_mac
= MAC_NO
;
756 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
757 given argument and NAME is the argument passed to -mcpu. Return NULL
758 if -mcpu was not passed. */
761 m68k_cpp_cpu_ident (const char *prefix
)
765 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
768 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
769 given argument and NAME is the name of the representative device for
770 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
773 m68k_cpp_cpu_family (const char *prefix
)
777 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
780 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
781 "interrupt_handler" attribute and interrupt_thread if FUNC has an
782 "interrupt_thread" attribute. Otherwise, return
783 m68k_fk_normal_function. */
785 enum m68k_function_kind
786 m68k_get_function_kind (tree func
)
790 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
792 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
794 return m68k_fk_interrupt_handler
;
796 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
798 return m68k_fk_interrupt_handler
;
800 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
802 return m68k_fk_interrupt_thread
;
804 return m68k_fk_normal_function
;
807 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
808 struct attribute_spec.handler. */
810 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
811 tree args ATTRIBUTE_UNUSED
,
812 int flags ATTRIBUTE_UNUSED
,
815 if (TREE_CODE (*node
) != FUNCTION_DECL
)
817 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
819 *no_add_attrs
= true;
822 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
824 error ("multiple interrupt attributes not allowed");
825 *no_add_attrs
= true;
829 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
831 error ("interrupt_thread is available only on fido");
832 *no_add_attrs
= true;
839 m68k_compute_frame_layout (void)
843 enum m68k_function_kind func_kind
=
844 m68k_get_function_kind (current_function_decl
);
845 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
846 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
848 /* Only compute the frame once per function.
849 Don't cache information until reload has been completed. */
850 if (current_frame
.funcdef_no
== current_function_funcdef_no
854 current_frame
.size
= (get_frame_size () + 3) & -4;
858 /* Interrupt thread does not need to save any register. */
859 if (!interrupt_thread
)
860 for (regno
= 0; regno
< 16; regno
++)
861 if (m68k_save_reg (regno
, interrupt_handler
))
863 mask
|= 1 << (regno
- D0_REG
);
866 current_frame
.offset
= saved
* 4;
867 current_frame
.reg_no
= saved
;
868 current_frame
.reg_mask
= mask
;
870 current_frame
.foffset
= 0;
872 if (TARGET_HARD_FLOAT
)
874 /* Interrupt thread does not need to save any register. */
875 if (!interrupt_thread
)
876 for (regno
= 16; regno
< 24; regno
++)
877 if (m68k_save_reg (regno
, interrupt_handler
))
879 mask
|= 1 << (regno
- FP0_REG
);
882 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
883 current_frame
.offset
+= current_frame
.foffset
;
885 current_frame
.fpu_no
= saved
;
886 current_frame
.fpu_mask
= mask
;
888 /* Remember what function this frame refers to. */
889 current_frame
.funcdef_no
= current_function_funcdef_no
;
892 /* Worker function for TARGET_CAN_ELIMINATE. */
895 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
897 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
901 m68k_initial_elimination_offset (int from
, int to
)
904 /* The arg pointer points 8 bytes before the start of the arguments,
905 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
906 frame pointer in most frames. */
907 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
908 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
909 return argptr_offset
;
911 m68k_compute_frame_layout ();
913 gcc_assert (to
== STACK_POINTER_REGNUM
);
916 case ARG_POINTER_REGNUM
:
917 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
918 case FRAME_POINTER_REGNUM
:
919 return current_frame
.offset
+ current_frame
.size
;
925 /* Refer to the array `regs_ever_live' to determine which registers
926 to save; `regs_ever_live[I]' is nonzero if register number I
927 is ever used in the function. This function is responsible for
928 knowing which registers should not be saved even if used.
929 Return true if we need to save REGNO. */
932 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
934 if (flag_pic
&& regno
== PIC_REG
)
936 if (crtl
->saves_all_registers
)
938 if (crtl
->uses_pic_offset_table
)
940 /* Reload may introduce constant pool references into a function
941 that thitherto didn't need a PIC register. Note that the test
942 above will not catch that case because we will only set
943 crtl->uses_pic_offset_table when emitting
944 the address reloads. */
945 if (crtl
->uses_const_pool
)
949 if (crtl
->calls_eh_return
)
954 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
955 if (test
== INVALID_REGNUM
)
962 /* Fixed regs we never touch. */
963 if (fixed_regs
[regno
])
966 /* The frame pointer (if it is such) is handled specially. */
967 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
970 /* Interrupt handlers must also save call_used_regs
971 if they are live or when calling nested functions. */
972 if (interrupt_handler
)
974 if (df_regs_ever_live_p (regno
))
977 if (!current_function_is_leaf
&& call_used_regs
[regno
])
981 /* Never need to save registers that aren't touched. */
982 if (!df_regs_ever_live_p (regno
))
985 /* Otherwise save everything that isn't call-clobbered. */
986 return !call_used_regs
[regno
];
989 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
990 the lowest memory address. COUNT is the number of registers to be
991 moved, with register REGNO + I being moved if bit I of MASK is set.
992 STORE_P specifies the direction of the move and ADJUST_STACK_P says
993 whether or not this is pre-decrement (if STORE_P) or post-increment
994 (if !STORE_P) operation. */
997 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
998 unsigned int count
, unsigned int regno
,
999 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
1002 rtx body
, addr
, src
, operands
[2];
1003 enum machine_mode mode
;
1005 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
1006 mode
= reg_raw_mode
[regno
];
1011 src
= plus_constant (base
, (count
1012 * GET_MODE_SIZE (mode
)
1013 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
1014 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
1017 for (; mask
!= 0; mask
>>= 1, regno
++)
1020 addr
= plus_constant (base
, offset
);
1021 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
1022 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
1023 XVECEXP (body
, 0, i
++)
1024 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
1025 offset
+= GET_MODE_SIZE (mode
);
1027 gcc_assert (i
== XVECLEN (body
, 0));
1029 return emit_insn (body
);
1032 /* Make INSN a frame-related instruction. */
1035 m68k_set_frame_related (rtx insn
)
1040 RTX_FRAME_RELATED_P (insn
) = 1;
1041 body
= PATTERN (insn
);
1042 if (GET_CODE (body
) == PARALLEL
)
1043 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
1044 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
1047 /* Emit RTL for the "prologue" define_expand. */
1050 m68k_expand_prologue (void)
1052 HOST_WIDE_INT fsize_with_regs
;
1053 rtx limit
, src
, dest
;
1055 m68k_compute_frame_layout ();
1057 /* If the stack limit is a symbol, we can check it here,
1058 before actually allocating the space. */
1059 if (crtl
->limit_stack
1060 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1062 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
1063 if (!LEGITIMATE_CONSTANT_P (limit
))
1065 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1066 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1068 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1069 stack_pointer_rtx
, limit
),
1070 stack_pointer_rtx
, limit
,
1074 fsize_with_regs
= current_frame
.size
;
1075 if (TARGET_COLDFIRE
)
1077 /* ColdFire's move multiple instructions do not allow pre-decrement
1078 addressing. Add the size of movem saves to the initial stack
1079 allocation instead. */
1080 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1081 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1082 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1083 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1086 if (frame_pointer_needed
)
1088 if (fsize_with_regs
== 0 && TUNE_68040
)
1090 /* On the 68040, two separate moves are faster than link.w 0. */
1091 dest
= gen_frame_mem (Pmode
,
1092 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1093 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1094 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1095 stack_pointer_rtx
));
1097 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1098 m68k_set_frame_related
1099 (emit_insn (gen_link (frame_pointer_rtx
,
1100 GEN_INT (-4 - fsize_with_regs
))));
1103 m68k_set_frame_related
1104 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1105 m68k_set_frame_related
1106 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1108 GEN_INT (-fsize_with_regs
))));
1111 /* If the frame pointer is needed, emit a special barrier that
1112 will prevent the scheduler from moving stores to the frame
1113 before the stack adjustment. */
1114 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1116 else if (fsize_with_regs
!= 0)
1117 m68k_set_frame_related
1118 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1120 GEN_INT (-fsize_with_regs
))));
1122 if (current_frame
.fpu_mask
)
1124 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1126 m68k_set_frame_related
1127 (m68k_emit_movem (stack_pointer_rtx
,
1128 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1129 current_frame
.fpu_no
, FP0_REG
,
1130 current_frame
.fpu_mask
, true, true));
1135 /* If we're using moveml to save the integer registers,
1136 the stack pointer will point to the bottom of the moveml
1137 save area. Find the stack offset of the first FP register. */
1138 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1141 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1142 m68k_set_frame_related
1143 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1144 current_frame
.fpu_no
, FP0_REG
,
1145 current_frame
.fpu_mask
, true, false));
1149 /* If the stack limit is not a symbol, check it here.
1150 This has the disadvantage that it may be too late... */
1151 if (crtl
->limit_stack
)
1153 if (REG_P (stack_limit_rtx
))
1154 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1156 stack_pointer_rtx
, stack_limit_rtx
,
1159 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1160 warning (0, "stack limit expression is not supported");
1163 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1165 /* Store each register separately in the same order moveml does. */
1168 for (i
= 16; i
-- > 0; )
1169 if (current_frame
.reg_mask
& (1 << i
))
1171 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1172 dest
= gen_frame_mem (SImode
,
1173 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1174 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1179 if (TARGET_COLDFIRE
)
1180 /* The required register save space has already been allocated.
1181 The first register should be stored at (%sp). */
1182 m68k_set_frame_related
1183 (m68k_emit_movem (stack_pointer_rtx
, 0,
1184 current_frame
.reg_no
, D0_REG
,
1185 current_frame
.reg_mask
, true, false));
1187 m68k_set_frame_related
1188 (m68k_emit_movem (stack_pointer_rtx
,
1189 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1190 current_frame
.reg_no
, D0_REG
,
1191 current_frame
.reg_mask
, true, true));
1194 if (!TARGET_SEP_DATA
1195 && crtl
->uses_pic_offset_table
)
1196 emit_insn (gen_load_got (pic_offset_table_rtx
));
1199 /* Return true if a simple (return) instruction is sufficient for this
1200 instruction (i.e. if no epilogue is needed). */
1203 m68k_use_return_insn (void)
1205 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1208 m68k_compute_frame_layout ();
1209 return current_frame
.offset
== 0;
1212 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1213 SIBCALL_P says which.
1215 The function epilogue should not depend on the current stack pointer!
1216 It should use the frame pointer only, if there is a frame pointer.
1217 This is mandatory because of alloca; we also take advantage of it to
1218 omit stack adjustments before returning. */
1221 m68k_expand_epilogue (bool sibcall_p
)
1223 HOST_WIDE_INT fsize
, fsize_with_regs
;
1224 bool big
, restore_from_sp
;
1226 m68k_compute_frame_layout ();
1228 fsize
= current_frame
.size
;
1230 restore_from_sp
= false;
1232 /* FIXME : current_function_is_leaf below is too strong.
1233 What we really need to know there is if there could be pending
1234 stack adjustment needed at that point. */
1235 restore_from_sp
= (!frame_pointer_needed
1236 || (!cfun
->calls_alloca
1237 && current_function_is_leaf
));
1239 /* fsize_with_regs is the size we need to adjust the sp when
1240 popping the frame. */
1241 fsize_with_regs
= fsize
;
1242 if (TARGET_COLDFIRE
&& restore_from_sp
)
1244 /* ColdFire's move multiple instructions do not allow post-increment
1245 addressing. Add the size of movem loads to the final deallocation
1247 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1248 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1249 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1250 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1253 if (current_frame
.offset
+ fsize
>= 0x8000
1255 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1258 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1259 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1261 /* ColdFire's move multiple instructions do not support the
1262 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1263 stack-based restore. */
1264 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1265 GEN_INT (-(current_frame
.offset
+ fsize
)));
1266 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1267 gen_rtx_REG (Pmode
, A1_REG
),
1268 frame_pointer_rtx
));
1269 restore_from_sp
= true;
1273 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1279 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1281 /* Restore each register separately in the same order moveml does. */
1283 HOST_WIDE_INT offset
;
1285 offset
= current_frame
.offset
+ fsize
;
1286 for (i
= 0; i
< 16; i
++)
1287 if (current_frame
.reg_mask
& (1 << i
))
1293 /* Generate the address -OFFSET(%fp,%a1.l). */
1294 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1295 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1296 addr
= plus_constant (addr
, -offset
);
1298 else if (restore_from_sp
)
1299 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1301 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1302 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1303 gen_frame_mem (SImode
, addr
));
1304 offset
-= GET_MODE_SIZE (SImode
);
1307 else if (current_frame
.reg_mask
)
1310 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1311 gen_rtx_REG (Pmode
, A1_REG
),
1313 -(current_frame
.offset
+ fsize
),
1314 current_frame
.reg_no
, D0_REG
,
1315 current_frame
.reg_mask
, false, false);
1316 else if (restore_from_sp
)
1317 m68k_emit_movem (stack_pointer_rtx
, 0,
1318 current_frame
.reg_no
, D0_REG
,
1319 current_frame
.reg_mask
, false,
1322 m68k_emit_movem (frame_pointer_rtx
,
1323 -(current_frame
.offset
+ fsize
),
1324 current_frame
.reg_no
, D0_REG
,
1325 current_frame
.reg_mask
, false, false);
1328 if (current_frame
.fpu_no
> 0)
1331 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1332 gen_rtx_REG (Pmode
, A1_REG
),
1334 -(current_frame
.foffset
+ fsize
),
1335 current_frame
.fpu_no
, FP0_REG
,
1336 current_frame
.fpu_mask
, false, false);
1337 else if (restore_from_sp
)
1339 if (TARGET_COLDFIRE
)
1343 /* If we used moveml to restore the integer registers, the
1344 stack pointer will still point to the bottom of the moveml
1345 save area. Find the stack offset of the first FP
1347 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1350 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1351 m68k_emit_movem (stack_pointer_rtx
, offset
,
1352 current_frame
.fpu_no
, FP0_REG
,
1353 current_frame
.fpu_mask
, false, false);
1356 m68k_emit_movem (stack_pointer_rtx
, 0,
1357 current_frame
.fpu_no
, FP0_REG
,
1358 current_frame
.fpu_mask
, false, true);
1361 m68k_emit_movem (frame_pointer_rtx
,
1362 -(current_frame
.foffset
+ fsize
),
1363 current_frame
.fpu_no
, FP0_REG
,
1364 current_frame
.fpu_mask
, false, false);
1367 if (frame_pointer_needed
)
1368 emit_insn (gen_unlink (frame_pointer_rtx
));
1369 else if (fsize_with_regs
)
1370 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1372 GEN_INT (fsize_with_regs
)));
1374 if (crtl
->calls_eh_return
)
1375 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1377 EH_RETURN_STACKADJ_RTX
));
1380 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
1383 /* Return true if X is a valid comparison operator for the dbcc
1386 Note it rejects floating point comparison operators.
1387 (In the future we could use Fdbcc).
1389 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1392 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1394 switch (GET_CODE (x
))
1396 case EQ
: case NE
: case GTU
: case LTU
:
1400 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1402 case GT
: case LT
: case GE
: case LE
:
1403 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1409 /* Return nonzero if flags are currently in the 68881 flag register. */
1411 flags_in_68881 (void)
1413 /* We could add support for these in the future */
1414 return cc_status
.flags
& CC_IN_68881
;
1417 /* Return true if PARALLEL contains register REGNO. */
1419 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1423 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1426 if (GET_CODE (parallel
) != PARALLEL
)
1429 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1433 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1434 if (REG_P (x
) && REGNO (x
) == regno
)
1441 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1444 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1446 enum m68k_function_kind kind
;
1448 /* We cannot use sibcalls for nested functions because we use the
1449 static chain register for indirect calls. */
1450 if (CALL_EXPR_STATIC_CHAIN (exp
))
1453 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1455 /* Check that the return value locations are the same. For
1456 example that we aren't returning a value from the sibling in
1457 a D0 register but then need to transfer it to a A0 register. */
1461 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1463 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1465 /* Check that the values are equal or that the result the callee
1466 function returns is superset of what the current function returns. */
1467 if (!(rtx_equal_p (cfun_value
, call_value
)
1468 || (REG_P (cfun_value
)
1469 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1473 kind
= m68k_get_function_kind (current_function_decl
);
1474 if (kind
== m68k_fk_normal_function
)
1475 /* We can always sibcall from a normal function, because it's
1476 undefined if it is calling an interrupt function. */
1479 /* Otherwise we can only sibcall if the function kind is known to be
1481 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1487 /* On the m68k all args are always pushed. */
1490 m68k_function_arg (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
1491 enum machine_mode mode ATTRIBUTE_UNUSED
,
1492 const_tree type ATTRIBUTE_UNUSED
,
1493 bool named ATTRIBUTE_UNUSED
)
1499 m68k_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1500 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1502 *cum
+= (mode
!= BLKmode
1503 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1504 : (int_size_in_bytes (type
) + 3) & ~3);
1507 /* Convert X to a legitimate function call memory reference and return the
1511 m68k_legitimize_call_address (rtx x
)
1513 gcc_assert (MEM_P (x
));
1514 if (call_operand (XEXP (x
, 0), VOIDmode
))
1516 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1519 /* Likewise for sibling calls. */
1522 m68k_legitimize_sibcall_address (rtx x
)
1524 gcc_assert (MEM_P (x
));
1525 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1528 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1529 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1532 /* Convert X to a legitimate address and return it if successful. Otherwise
1535 For the 68000, we handle X+REG by loading X into a register R and
1536 using R+REG. R will go in an address reg and indexing will be used.
1537 However, if REG is a broken-out memory address or multiplication,
1538 nothing needs to be done because REG can certainly go in an address reg. */
1541 m68k_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
1543 if (m68k_tls_symbol_p (x
))
1544 return m68k_legitimize_tls_address (x
);
1546 if (GET_CODE (x
) == PLUS
)
1548 int ch
= (x
) != (oldx
);
1551 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1553 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1556 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1558 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1561 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1565 if (GET_CODE (XEXP (x
, 1)) == REG
1566 && GET_CODE (XEXP (x
, 0)) == REG
)
1568 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1571 x
= force_operand (x
, 0);
1575 if (memory_address_p (mode
, x
))
1578 if (GET_CODE (XEXP (x
, 0)) == REG
1579 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1580 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1581 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1583 rtx temp
= gen_reg_rtx (Pmode
);
1584 rtx val
= force_operand (XEXP (x
, 1), 0);
1585 emit_move_insn (temp
, val
);
1588 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1589 && GET_CODE (XEXP (x
, 0)) == REG
)
1590 x
= force_operand (x
, 0);
1592 else if (GET_CODE (XEXP (x
, 1)) == REG
1593 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1594 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1595 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1597 rtx temp
= gen_reg_rtx (Pmode
);
1598 rtx val
= force_operand (XEXP (x
, 0), 0);
1599 emit_move_insn (temp
, val
);
1602 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1603 && GET_CODE (XEXP (x
, 1)) == REG
)
1604 x
= force_operand (x
, 0);
1612 /* Output a dbCC; jCC sequence. Note we do not handle the
1613 floating point version of this sequence (Fdbcc). We also
1614 do not handle alternative conditions when CC_NO_OVERFLOW is
1615 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1616 kick those out before we get here. */
1619 output_dbcc_and_branch (rtx
*operands
)
1621 switch (GET_CODE (operands
[3]))
1624 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1628 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1632 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1636 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1640 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1644 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1648 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1652 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1656 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1660 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1667 /* If the decrement is to be done in SImode, then we have
1668 to compensate for the fact that dbcc decrements in HImode. */
1669 switch (GET_MODE (operands
[0]))
1672 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1684 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1687 enum rtx_code op_code
= GET_CODE (op
);
1689 /* This does not produce a useful cc. */
1692 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1693 below. Swap the operands and change the op if these requirements
1694 are not fulfilled. */
1695 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1699 operand1
= operand2
;
1701 op_code
= swap_condition (op_code
);
1703 loperands
[0] = operand1
;
1704 if (GET_CODE (operand1
) == REG
)
1705 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1707 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1708 if (operand2
!= const0_rtx
)
1710 loperands
[2] = operand2
;
1711 if (GET_CODE (operand2
) == REG
)
1712 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1714 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1716 loperands
[4] = gen_label_rtx ();
1717 if (operand2
!= const0_rtx
)
1718 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1721 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1722 output_asm_insn ("tst%.l %0", loperands
);
1724 output_asm_insn ("cmp%.w #0,%0", loperands
);
1726 output_asm_insn ("jne %l4", loperands
);
1728 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1729 output_asm_insn ("tst%.l %1", loperands
);
1731 output_asm_insn ("cmp%.w #0,%1", loperands
);
1734 loperands
[5] = dest
;
1739 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1740 CODE_LABEL_NUMBER (loperands
[4]));
1741 output_asm_insn ("seq %5", loperands
);
1745 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1746 CODE_LABEL_NUMBER (loperands
[4]));
1747 output_asm_insn ("sne %5", loperands
);
1751 loperands
[6] = gen_label_rtx ();
1752 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1753 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1754 CODE_LABEL_NUMBER (loperands
[4]));
1755 output_asm_insn ("sgt %5", loperands
);
1756 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1757 CODE_LABEL_NUMBER (loperands
[6]));
1761 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1762 CODE_LABEL_NUMBER (loperands
[4]));
1763 output_asm_insn ("shi %5", loperands
);
1767 loperands
[6] = gen_label_rtx ();
1768 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1769 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1770 CODE_LABEL_NUMBER (loperands
[4]));
1771 output_asm_insn ("slt %5", loperands
);
1772 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1773 CODE_LABEL_NUMBER (loperands
[6]));
1777 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1778 CODE_LABEL_NUMBER (loperands
[4]));
1779 output_asm_insn ("scs %5", loperands
);
1783 loperands
[6] = gen_label_rtx ();
1784 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1785 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1786 CODE_LABEL_NUMBER (loperands
[4]));
1787 output_asm_insn ("sge %5", loperands
);
1788 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1789 CODE_LABEL_NUMBER (loperands
[6]));
1793 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1794 CODE_LABEL_NUMBER (loperands
[4]));
1795 output_asm_insn ("scc %5", loperands
);
1799 loperands
[6] = gen_label_rtx ();
1800 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1801 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1802 CODE_LABEL_NUMBER (loperands
[4]));
1803 output_asm_insn ("sle %5", loperands
);
1804 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1805 CODE_LABEL_NUMBER (loperands
[6]));
1809 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1810 CODE_LABEL_NUMBER (loperands
[4]));
1811 output_asm_insn ("sls %5", loperands
);
1821 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1823 operands
[0] = countop
;
1824 operands
[1] = dataop
;
1826 if (GET_CODE (countop
) == CONST_INT
)
1828 register int count
= INTVAL (countop
);
1829 /* If COUNT is bigger than size of storage unit in use,
1830 advance to the containing unit of same size. */
1831 if (count
> signpos
)
1833 int offset
= (count
& ~signpos
) / 8;
1834 count
= count
& signpos
;
1835 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1837 if (count
== signpos
)
1838 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1840 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1842 /* These three statements used to use next_insns_test_no...
1843 but it appears that this should do the same job. */
1845 && next_insn_tests_no_inequality (insn
))
1848 && next_insn_tests_no_inequality (insn
))
1851 && next_insn_tests_no_inequality (insn
))
1853 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1854 On some m68k variants unfortunately that's slower than btst.
1855 On 68000 and higher, that should also work for all HImode operands. */
1856 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1858 if (count
== 3 && DATA_REG_P (operands
[1])
1859 && next_insn_tests_no_inequality (insn
))
1861 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1862 return "move%.w %1,%%ccr";
1864 if (count
== 2 && DATA_REG_P (operands
[1])
1865 && next_insn_tests_no_inequality (insn
))
1867 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1868 return "move%.w %1,%%ccr";
1870 /* count == 1 followed by bvc/bvs and
1871 count == 0 followed by bcc/bcs are also possible, but need
1872 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1875 cc_status
.flags
= CC_NOT_NEGATIVE
;
1877 return "btst %0,%1";
1880 /* Return true if X is a legitimate base register. STRICT_P says
1881 whether we need strict checking. */
1884 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1886 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1887 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1892 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1893 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1896 /* Return true if X is a legitimate index register. STRICT_P says
1897 whether we need strict checking. */
1900 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1902 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1907 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1908 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1911 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1912 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1913 ADDRESS if so. STRICT_P says whether we need strict checking. */
1916 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1920 /* Check for a scale factor. */
1922 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1923 && GET_CODE (x
) == MULT
1924 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1925 && (INTVAL (XEXP (x
, 1)) == 2
1926 || INTVAL (XEXP (x
, 1)) == 4
1927 || (INTVAL (XEXP (x
, 1)) == 8
1928 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1930 scale
= INTVAL (XEXP (x
, 1));
1934 /* Check for a word extension. */
1935 if (!TARGET_COLDFIRE
1936 && GET_CODE (x
) == SIGN_EXTEND
1937 && GET_MODE (XEXP (x
, 0)) == HImode
)
1940 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1942 address
->scale
= scale
;
1950 /* Return true if X is an illegitimate symbolic constant. */
1953 m68k_illegitimate_symbolic_constant_p (rtx x
)
1957 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1959 split_const (x
, &base
, &offset
);
1960 if (GET_CODE (base
) == SYMBOL_REF
1961 && !offset_within_block_p (base
, INTVAL (offset
)))
1964 return m68k_tls_reference_p (x
, false);
1967 /* Return true if X is a legitimate constant address that can reach
1968 bytes in the range [X, X + REACH). STRICT_P says whether we need
1972 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1976 if (!CONSTANT_ADDRESS_P (x
))
1980 && !(strict_p
&& TARGET_PCREL
)
1981 && symbolic_operand (x
, VOIDmode
))
1984 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1986 split_const (x
, &base
, &offset
);
1987 if (GET_CODE (base
) == SYMBOL_REF
1988 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1992 return !m68k_tls_reference_p (x
, false);
1995 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1996 labels will become jump tables. */
1999 m68k_jump_table_ref_p (rtx x
)
2001 if (GET_CODE (x
) != LABEL_REF
)
2005 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
2008 x
= next_nonnote_insn (x
);
2009 return x
&& JUMP_TABLE_DATA_P (x
);
2012 /* Return true if X is a legitimate address for values of mode MODE.
2013 STRICT_P says whether strict checking is needed. If the address
2014 is valid, describe its components in *ADDRESS. */
2017 m68k_decompose_address (enum machine_mode mode
, rtx x
,
2018 bool strict_p
, struct m68k_address
*address
)
2022 memset (address
, 0, sizeof (*address
));
2024 if (mode
== BLKmode
)
2027 reach
= GET_MODE_SIZE (mode
);
2029 /* Check for (An) (mode 2). */
2030 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2036 /* Check for -(An) and (An)+ (modes 3 and 4). */
2037 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
2038 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2040 address
->code
= GET_CODE (x
);
2041 address
->base
= XEXP (x
, 0);
2045 /* Check for (d16,An) (mode 5). */
2046 if (GET_CODE (x
) == PLUS
2047 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2048 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
2049 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2051 address
->base
= XEXP (x
, 0);
2052 address
->offset
= XEXP (x
, 1);
2056 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2057 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2059 if (GET_CODE (x
) == PLUS
2060 && XEXP (x
, 0) == pic_offset_table_rtx
)
2062 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2063 they are invalid in this context. */
2064 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2066 address
->base
= XEXP (x
, 0);
2067 address
->offset
= XEXP (x
, 1);
2072 /* The ColdFire FPU only accepts addressing modes 2-5. */
2073 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2076 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2077 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2078 All these modes are variations of mode 7. */
2079 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2081 address
->offset
= x
;
2085 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2088 ??? do_tablejump creates these addresses before placing the target
2089 label, so we have to assume that unplaced labels are jump table
2090 references. It seems unlikely that we would ever generate indexed
2091 accesses to unplaced labels in other cases. */
2092 if (GET_CODE (x
) == PLUS
2093 && m68k_jump_table_ref_p (XEXP (x
, 1))
2094 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2096 address
->offset
= XEXP (x
, 1);
2100 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2101 (bd,An,Xn.SIZE*SCALE) addresses. */
2105 /* Check for a nonzero base displacement. */
2106 if (GET_CODE (x
) == PLUS
2107 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2109 address
->offset
= XEXP (x
, 1);
2113 /* Check for a suppressed index register. */
2114 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2120 /* Check for a suppressed base register. Do not allow this case
2121 for non-symbolic offsets as it effectively gives gcc freedom
2122 to treat data registers as base registers, which can generate
2125 && symbolic_operand (address
->offset
, VOIDmode
)
2126 && m68k_decompose_index (x
, strict_p
, address
))
2131 /* Check for a nonzero base displacement. */
2132 if (GET_CODE (x
) == PLUS
2133 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2134 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2136 address
->offset
= XEXP (x
, 1);
2141 /* We now expect the sum of a base and an index. */
2142 if (GET_CODE (x
) == PLUS
)
2144 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2145 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2147 address
->base
= XEXP (x
, 0);
2151 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2152 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2154 address
->base
= XEXP (x
, 1);
2161 /* Return true if X is a legitimate address for values of mode MODE.
2162 STRICT_P says whether strict checking is needed. */
2165 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2167 struct m68k_address address
;
2169 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2172 /* Return true if X is a memory, describing its address in ADDRESS if so.
2173 Apply strict checking if called during or after reload. */
2176 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2179 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2180 reload_in_progress
|| reload_completed
,
2184 /* Return true if X matches the 'Q' constraint. It must be a memory
2185 with a base address and no constant offset or index. */
2188 m68k_matches_q_p (rtx x
)
2190 struct m68k_address address
;
2192 return (m68k_legitimate_mem_p (x
, &address
)
2193 && address
.code
== UNKNOWN
2199 /* Return true if X matches the 'U' constraint. It must be a base address
2200 with a constant offset and no index. */
2203 m68k_matches_u_p (rtx x
)
2205 struct m68k_address address
;
2207 return (m68k_legitimate_mem_p (x
, &address
)
2208 && address
.code
== UNKNOWN
2214 /* Return GOT pointer. */
2219 if (pic_offset_table_rtx
== NULL_RTX
)
2220 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2222 crtl
->uses_pic_offset_table
= 1;
2224 return pic_offset_table_rtx
;
2227 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2229 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2230 RELOC_TLSIE
, RELOC_TLSLE
};
2232 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2234 /* Wrap symbol X into unspec representing relocation RELOC.
2235 BASE_REG - register that should be added to the result.
2236 TEMP_REG - if non-null, temporary register. */
2239 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2243 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2245 if (TARGET_COLDFIRE
&& use_x_p
)
2246 /* When compiling with -mx{got, tls} switch the code will look like this:
2248 move.l <X>@<RELOC>,<TEMP_REG>
2249 add.l <BASE_REG>,<TEMP_REG> */
2251 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2252 to put @RELOC after reference. */
2253 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2255 x
= gen_rtx_CONST (Pmode
, x
);
2257 if (temp_reg
== NULL
)
2259 gcc_assert (can_create_pseudo_p ());
2260 temp_reg
= gen_reg_rtx (Pmode
);
2263 emit_move_insn (temp_reg
, x
);
2264 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2269 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2271 x
= gen_rtx_CONST (Pmode
, x
);
2273 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2279 /* Helper for m68k_unwrap_symbol.
2280 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2281 sets *RELOC_PTR to relocation type for the symbol. */
2284 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2285 enum m68k_reloc
*reloc_ptr
)
2287 if (GET_CODE (orig
) == CONST
)
2290 enum m68k_reloc dummy
;
2294 if (reloc_ptr
== NULL
)
2297 /* Handle an addend. */
2298 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2299 && CONST_INT_P (XEXP (x
, 1)))
2302 if (GET_CODE (x
) == UNSPEC
)
2304 switch (XINT (x
, 1))
2306 case UNSPEC_RELOC16
:
2307 orig
= XVECEXP (x
, 0, 0);
2308 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2311 case UNSPEC_RELOC32
:
2312 if (unwrap_reloc32_p
)
2314 orig
= XVECEXP (x
, 0, 0);
2315 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2328 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2329 UNSPEC_RELOC32 wrappers. */
2332 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2334 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2337 /* Helper for m68k_final_prescan_insn. */
2340 m68k_final_prescan_insn_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2344 if (m68k_unwrap_symbol (x
, true) != x
)
2345 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2349 gcc_assert (GET_CODE (x
) == CONST
);
2352 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2357 unspec
= XEXP (plus
, 0);
2358 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2359 addend
= XEXP (plus
, 1);
2360 gcc_assert (CONST_INT_P (addend
));
2362 /* We now have all the pieces, rearrange them. */
2364 /* Move symbol to plus. */
2365 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2367 /* Move plus inside unspec. */
2368 XVECEXP (unspec
, 0, 0) = plus
;
2370 /* Move unspec to top level of const. */
2371 XEXP (x
, 0) = unspec
;
2380 /* Prescan insn before outputing assembler for it. */
2383 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED
,
2384 rtx
*operands
, int n_operands
)
2388 /* Combine and, possibly, other optimizations may do good job
2390 (const (unspec [(symbol)]))
2392 (const (plus (unspec [(symbol)])
2394 The problem with this is emitting @TLS or @GOT decorations.
2395 The decoration is emitted when processing (unspec), so the
2396 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2398 It seems that the easiest solution to this is to convert such
2400 (const (unspec [(plus (symbol)
2402 Note, that the top level of operand remains intact, so we don't have
2403 to patch up anything outside of the operand. */
2405 for (i
= 0; i
< n_operands
; ++i
)
2411 for_each_rtx (&op
, m68k_final_prescan_insn_1
, NULL
);
2415 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2416 If REG is non-null, use it; generate new pseudo otherwise. */
2419 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2423 if (reg
== NULL_RTX
)
2425 gcc_assert (can_create_pseudo_p ());
2426 reg
= gen_reg_rtx (Pmode
);
2429 insn
= emit_move_insn (reg
, x
);
2430 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2432 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2437 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2441 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2443 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2445 x
= gen_rtx_MEM (Pmode
, x
);
2446 MEM_READONLY_P (x
) = 1;
2451 /* Legitimize PIC addresses. If the address is already
2452 position-independent, we return ORIG. Newly generated
2453 position-independent addresses go to REG. If we need more
2454 than one register, we lose.
2456 An address is legitimized by making an indirect reference
2457 through the Global Offset Table with the name of the symbol
2460 The assembler and linker are responsible for placing the
2461 address of the symbol in the GOT. The function prologue
2462 is responsible for initializing a5 to the starting address
2465 The assembler is also responsible for translating a symbol name
2466 into a constant displacement from the start of the GOT.
2468 A quick example may make things a little clearer:
2470 When not generating PIC code to store the value 12345 into _foo
2471 we would generate the following code:
2475 When generating PIC two transformations are made. First, the compiler
2476 loads the address of foo into a register. So the first transformation makes:
2481 The code in movsi will intercept the lea instruction and call this
2482 routine which will transform the instructions into:
2484 movel a5@(_foo:w), a0
2488 That (in a nutshell) is how *all* symbol and label references are
2492 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2497 /* First handle a simple SYMBOL_REF or LABEL_REF */
2498 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2502 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2503 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2505 else if (GET_CODE (orig
) == CONST
)
2509 /* Make sure this has not already been legitimized. */
2510 if (m68k_unwrap_symbol (orig
, true) != orig
)
2515 /* legitimize both operands of the PLUS */
2516 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2518 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2519 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2520 base
== reg
? 0 : reg
);
2522 if (GET_CODE (orig
) == CONST_INT
)
2523 pic_ref
= plus_constant (base
, INTVAL (orig
));
2525 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2531 /* The __tls_get_addr symbol. */
2532 static GTY(()) rtx m68k_tls_get_addr
;
2534 /* Return SYMBOL_REF for __tls_get_addr. */
2537 m68k_get_tls_get_addr (void)
2539 if (m68k_tls_get_addr
== NULL_RTX
)
2540 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2542 return m68k_tls_get_addr
;
2545 /* Return libcall result in A0 instead of usual D0. */
2546 static bool m68k_libcall_value_in_a0_p
= false;
2548 /* Emit instruction sequence that calls __tls_get_addr. X is
2549 the TLS symbol we are referencing and RELOC is the symbol type to use
2550 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2551 emitted. A pseudo register with result of __tls_get_addr call is
2555 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2561 /* Emit the call sequence. */
2564 /* FIXME: Unfortunately, emit_library_call_value does not
2565 consider (plus (%a5) (const (unspec))) to be a good enough
2566 operand for push, so it forces it into a register. The bad
2567 thing about this is that combiner, due to copy propagation and other
2568 optimizations, sometimes can not later fix this. As a consequence,
2569 additional register may be allocated resulting in a spill.
2570 For reference, see args processing loops in
2571 calls.c:emit_library_call_value_1.
2572 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2573 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2575 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2576 is the simpliest way of generating a call. The difference between
2577 __tls_get_addr() and libcall is that the result is returned in D0
2578 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2579 which temporarily switches returning the result to A0. */
2581 m68k_libcall_value_in_a0_p
= true;
2582 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2583 Pmode
, 1, x
, Pmode
);
2584 m68k_libcall_value_in_a0_p
= false;
2586 insns
= get_insns ();
2589 gcc_assert (can_create_pseudo_p ());
2590 dest
= gen_reg_rtx (Pmode
);
2591 emit_libcall_block (insns
, dest
, a0
, eqv
);
2596 /* The __tls_get_addr symbol. */
2597 static GTY(()) rtx m68k_read_tp
;
2599 /* Return SYMBOL_REF for __m68k_read_tp. */
2602 m68k_get_m68k_read_tp (void)
2604 if (m68k_read_tp
== NULL_RTX
)
2605 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2607 return m68k_read_tp
;
2610 /* Emit instruction sequence that calls __m68k_read_tp.
2611 A pseudo register with result of __m68k_read_tp call is returned. */
2614 m68k_call_m68k_read_tp (void)
2623 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2624 is the simpliest way of generating a call. The difference between
2625 __m68k_read_tp() and libcall is that the result is returned in D0
2626 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2627 which temporarily switches returning the result to A0. */
2629 /* Emit the call sequence. */
2630 m68k_libcall_value_in_a0_p
= true;
2631 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2633 m68k_libcall_value_in_a0_p
= false;
2634 insns
= get_insns ();
2637 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2638 share the m68k_read_tp result with other IE/LE model accesses. */
2639 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2641 gcc_assert (can_create_pseudo_p ());
2642 dest
= gen_reg_rtx (Pmode
);
2643 emit_libcall_block (insns
, dest
, a0
, eqv
);
2648 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2649 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2653 m68k_legitimize_tls_address (rtx orig
)
2655 switch (SYMBOL_REF_TLS_MODEL (orig
))
2657 case TLS_MODEL_GLOBAL_DYNAMIC
:
2658 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2661 case TLS_MODEL_LOCAL_DYNAMIC
:
2667 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2668 share the LDM result with other LD model accesses. */
2669 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2672 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2674 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2676 if (can_create_pseudo_p ())
2677 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2683 case TLS_MODEL_INITIAL_EXEC
:
2688 a0
= m68k_call_m68k_read_tp ();
2690 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2691 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2693 if (can_create_pseudo_p ())
2694 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2700 case TLS_MODEL_LOCAL_EXEC
:
2705 a0
= m68k_call_m68k_read_tp ();
2707 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2709 if (can_create_pseudo_p ())
2710 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2723 /* Return true if X is a TLS symbol. */
2726 m68k_tls_symbol_p (rtx x
)
2728 if (!TARGET_HAVE_TLS
)
2731 if (GET_CODE (x
) != SYMBOL_REF
)
2734 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2737 /* Helper for m68k_tls_referenced_p. */
2740 m68k_tls_reference_p_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2742 /* Note: this is not the same as m68k_tls_symbol_p. */
2743 if (GET_CODE (*x_ptr
) == SYMBOL_REF
)
2744 return SYMBOL_REF_TLS_MODEL (*x_ptr
) != 0 ? 1 : 0;
2746 /* Don't recurse into legitimate TLS references. */
2747 if (m68k_tls_reference_p (*x_ptr
, true))
2753 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2754 though illegitimate one.
2755 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2758 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2760 if (!TARGET_HAVE_TLS
)
2764 return for_each_rtx (&x
, m68k_tls_reference_p_1
, NULL
) == 1 ? true : false;
2767 enum m68k_reloc reloc
= RELOC_GOT
;
2769 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2770 && TLS_RELOC_P (reloc
));
2776 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2778 /* Return the type of move that should be used for integer I. */
2781 m68k_const_method (HOST_WIDE_INT i
)
2788 /* The ColdFire doesn't have byte or word operations. */
2789 /* FIXME: This may not be useful for the m68060 either. */
2790 if (!TARGET_COLDFIRE
)
2792 /* if -256 < N < 256 but N is not in range for a moveq
2793 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2794 if (USE_MOVQ (i
^ 0xff))
2796 /* Likewise, try with not.w */
2797 if (USE_MOVQ (i
^ 0xffff))
2799 /* This is the only value where neg.w is useful */
2804 /* Try also with swap. */
2806 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2811 /* Try using MVZ/MVS with an immediate value to load constants. */
2812 if (i
>= 0 && i
<= 65535)
2814 if (i
>= -32768 && i
<= 32767)
2818 /* Otherwise, use move.l */
2822 /* Return the cost of moving constant I into a data register. */
2825 const_int_cost (HOST_WIDE_INT i
)
2827 switch (m68k_const_method (i
))
2830 /* Constants between -128 and 127 are cheap due to moveq. */
2838 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2848 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2849 bool speed ATTRIBUTE_UNUSED
)
2854 /* Constant zero is super cheap due to clr instruction. */
2855 if (x
== const0_rtx
)
2858 *total
= const_int_cost (INTVAL (x
));
2868 /* Make 0.0 cheaper than other floating constants to
2869 encourage creating tstsf and tstdf insns. */
2870 if (outer_code
== COMPARE
2871 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2877 /* These are vaguely right for a 68020. */
2878 /* The costs for long multiply have been adjusted to work properly
2879 in synth_mult on the 68020, relative to an average of the time
2880 for add and the time for shift, taking away a little more because
2881 sometimes move insns are needed. */
2882 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2887 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2888 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2890 : TARGET_COLDFIRE ? 3 : 13)
2895 : TUNE_68000_10 ? 5 \
2896 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2897 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2899 : TARGET_COLDFIRE ? 2 : 8)
2902 (TARGET_CF_HWDIV ? 11 \
2903 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2906 /* An lea costs about three times as much as a simple add. */
2907 if (GET_MODE (x
) == SImode
2908 && GET_CODE (XEXP (x
, 1)) == REG
2909 && GET_CODE (XEXP (x
, 0)) == MULT
2910 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2911 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2912 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2913 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2914 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2916 /* lea an@(dx:l:i),am */
2917 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2927 *total
= COSTS_N_INSNS(1);
2932 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2934 if (INTVAL (XEXP (x
, 1)) < 16)
2935 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2937 /* We're using clrw + swap for these cases. */
2938 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2941 *total
= COSTS_N_INSNS (10); /* Worst case. */
2944 /* A shift by a big integer takes an extra instruction. */
2945 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2946 && (INTVAL (XEXP (x
, 1)) == 16))
2948 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2951 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2952 && !(INTVAL (XEXP (x
, 1)) > 0
2953 && INTVAL (XEXP (x
, 1)) <= 8))
2955 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2961 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2962 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2963 && GET_MODE (x
) == SImode
)
2964 *total
= COSTS_N_INSNS (MULW_COST
);
2965 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2966 *total
= COSTS_N_INSNS (MULW_COST
);
2968 *total
= COSTS_N_INSNS (MULL_COST
);
2975 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2976 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2977 else if (TARGET_CF_HWDIV
)
2978 *total
= COSTS_N_INSNS (18);
2980 *total
= COSTS_N_INSNS (43); /* div.l */
2984 if (outer_code
== COMPARE
)
2993 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2997 output_move_const_into_data_reg (rtx
*operands
)
3001 i
= INTVAL (operands
[1]);
3002 switch (m68k_const_method (i
))
3005 return "mvzw %1,%0";
3007 return "mvsw %1,%0";
3009 return "moveq %1,%0";
3012 operands
[1] = GEN_INT (i
^ 0xff);
3013 return "moveq %1,%0\n\tnot%.b %0";
3016 operands
[1] = GEN_INT (i
^ 0xffff);
3017 return "moveq %1,%0\n\tnot%.w %0";
3020 return "moveq #-128,%0\n\tneg%.w %0";
3025 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
3026 return "moveq %1,%0\n\tswap %0";
3029 return "move%.l %1,%0";
3035 /* Return true if I can be handled by ISA B's mov3q instruction. */
3038 valid_mov3q_const (HOST_WIDE_INT i
)
3040 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
3043 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3044 I is the value of OPERANDS[1]. */
3047 output_move_simode_const (rtx
*operands
)
3053 src
= INTVAL (operands
[1]);
3055 && (DATA_REG_P (dest
) || MEM_P (dest
))
3056 /* clr insns on 68000 read before writing. */
3057 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3058 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3060 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3061 return "mov3q%.l %1,%0";
3062 else if (src
== 0 && ADDRESS_REG_P (dest
))
3063 return "sub%.l %0,%0";
3064 else if (DATA_REG_P (dest
))
3065 return output_move_const_into_data_reg (operands
);
3066 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3068 if (valid_mov3q_const (src
))
3069 return "mov3q%.l %1,%0";
3070 return "move%.w %1,%0";
3072 else if (MEM_P (dest
)
3073 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3074 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3075 && IN_RANGE (src
, -0x8000, 0x7fff))
3077 if (valid_mov3q_const (src
))
3078 return "mov3q%.l %1,%-";
3081 return "move%.l %1,%0";
3085 output_move_simode (rtx
*operands
)
3087 if (GET_CODE (operands
[1]) == CONST_INT
)
3088 return output_move_simode_const (operands
);
3089 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3090 || GET_CODE (operands
[1]) == CONST
)
3091 && push_operand (operands
[0], SImode
))
3093 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3094 || GET_CODE (operands
[1]) == CONST
)
3095 && ADDRESS_REG_P (operands
[0]))
3096 return "lea %a1,%0";
3097 return "move%.l %1,%0";
3101 output_move_himode (rtx
*operands
)
3103 if (GET_CODE (operands
[1]) == CONST_INT
)
3105 if (operands
[1] == const0_rtx
3106 && (DATA_REG_P (operands
[0])
3107 || GET_CODE (operands
[0]) == MEM
)
3108 /* clr insns on 68000 read before writing. */
3109 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3110 || !(GET_CODE (operands
[0]) == MEM
3111 && MEM_VOLATILE_P (operands
[0]))))
3113 else if (operands
[1] == const0_rtx
3114 && ADDRESS_REG_P (operands
[0]))
3115 return "sub%.l %0,%0";
3116 else if (DATA_REG_P (operands
[0])
3117 && INTVAL (operands
[1]) < 128
3118 && INTVAL (operands
[1]) >= -128)
3119 return "moveq %1,%0";
3120 else if (INTVAL (operands
[1]) < 0x8000
3121 && INTVAL (operands
[1]) >= -0x8000)
3122 return "move%.w %1,%0";
3124 else if (CONSTANT_P (operands
[1]))
3125 return "move%.l %1,%0";
3126 return "move%.w %1,%0";
3130 output_move_qimode (rtx
*operands
)
3132 /* 68k family always modifies the stack pointer by at least 2, even for
3133 byte pushes. The 5200 (ColdFire) does not do this. */
3135 /* This case is generated by pushqi1 pattern now. */
3136 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3137 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3138 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3139 && ! ADDRESS_REG_P (operands
[1])
3140 && ! TARGET_COLDFIRE
));
3142 /* clr and st insns on 68000 read before writing. */
3143 if (!ADDRESS_REG_P (operands
[0])
3144 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3145 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3147 if (operands
[1] == const0_rtx
)
3149 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3150 && GET_CODE (operands
[1]) == CONST_INT
3151 && (INTVAL (operands
[1]) & 255) == 255)
3157 if (GET_CODE (operands
[1]) == CONST_INT
3158 && DATA_REG_P (operands
[0])
3159 && INTVAL (operands
[1]) < 128
3160 && INTVAL (operands
[1]) >= -128)
3161 return "moveq %1,%0";
3162 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3163 return "sub%.l %0,%0";
3164 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3165 return "move%.l %1,%0";
3166 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3167 from address registers. */
3168 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3169 return "move%.w %1,%0";
3170 return "move%.b %1,%0";
3174 output_move_stricthi (rtx
*operands
)
3176 if (operands
[1] == const0_rtx
3177 /* clr insns on 68000 read before writing. */
3178 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3179 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3181 return "move%.w %1,%0";
3185 output_move_strictqi (rtx
*operands
)
3187 if (operands
[1] == const0_rtx
3188 /* clr insns on 68000 read before writing. */
3189 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3190 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3192 return "move%.b %1,%0";
3195 /* Return the best assembler insn template
3196 for moving operands[1] into operands[0] as a fullword. */
3199 singlemove_string (rtx
*operands
)
3201 if (GET_CODE (operands
[1]) == CONST_INT
)
3202 return output_move_simode_const (operands
);
3203 return "move%.l %1,%0";
3207 /* Output assembler or rtl code to perform a doubleword move insn
3208 with operands OPERANDS.
3209 Pointers to 3 helper functions should be specified:
3210 HANDLE_REG_ADJUST to adjust a register by a small value,
3211 HANDLE_COMPADR to compute an address and
3212 HANDLE_MOVSI to move 4 bytes. */
3215 handle_move_double (rtx operands
[2],
3216 void (*handle_reg_adjust
) (rtx
, int),
3217 void (*handle_compadr
) (rtx
[2]),
3218 void (*handle_movsi
) (rtx
[2]))
3222 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3227 rtx addreg0
= 0, addreg1
= 0;
3228 int dest_overlapped_low
= 0;
3229 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3234 /* First classify both operands. */
3236 if (REG_P (operands
[0]))
3238 else if (offsettable_memref_p (operands
[0]))
3240 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3242 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3244 else if (GET_CODE (operands
[0]) == MEM
)
3249 if (REG_P (operands
[1]))
3251 else if (CONSTANT_P (operands
[1]))
3253 else if (offsettable_memref_p (operands
[1]))
3255 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3257 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3259 else if (GET_CODE (operands
[1]) == MEM
)
3264 /* Check for the cases that the operand constraints are not supposed
3265 to allow to happen. Generating code for these cases is
3267 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3269 /* If one operand is decrementing and one is incrementing
3270 decrement the former register explicitly
3271 and change that operand into ordinary indexing. */
3273 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3275 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3277 handle_reg_adjust (operands
[0], -size
);
3279 if (GET_MODE (operands
[1]) == XFmode
)
3280 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3281 else if (GET_MODE (operands
[0]) == DFmode
)
3282 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3284 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3287 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3289 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3291 handle_reg_adjust (operands
[1], -size
);
3293 if (GET_MODE (operands
[1]) == XFmode
)
3294 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3295 else if (GET_MODE (operands
[1]) == DFmode
)
3296 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3298 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3302 /* If an operand is an unoffsettable memory ref, find a register
3303 we can increment temporarily to make it refer to the second word. */
3305 if (optype0
== MEMOP
)
3306 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3308 if (optype1
== MEMOP
)
3309 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3311 /* Ok, we can do one word at a time.
3312 Normally we do the low-numbered word first,
3313 but if either operand is autodecrementing then we
3314 do the high-numbered word first.
3316 In either case, set up in LATEHALF the operands to use
3317 for the high-numbered word and in some cases alter the
3318 operands in OPERANDS to be suitable for the low-numbered word. */
3322 if (optype0
== REGOP
)
3324 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3325 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3327 else if (optype0
== OFFSOP
)
3329 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3330 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3334 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3335 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3338 if (optype1
== REGOP
)
3340 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3341 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3343 else if (optype1
== OFFSOP
)
3345 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3346 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3348 else if (optype1
== CNSTOP
)
3350 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3355 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3356 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3357 operands
[1] = GEN_INT (l
[0]);
3358 middlehalf
[1] = GEN_INT (l
[1]);
3359 latehalf
[1] = GEN_INT (l
[2]);
3363 /* No non-CONST_DOUBLE constant should ever appear
3365 gcc_assert (!CONSTANT_P (operands
[1]));
3370 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3371 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3375 /* size is not 12: */
3377 if (optype0
== REGOP
)
3378 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3379 else if (optype0
== OFFSOP
)
3380 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3382 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3384 if (optype1
== REGOP
)
3385 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3386 else if (optype1
== OFFSOP
)
3387 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3388 else if (optype1
== CNSTOP
)
3389 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3391 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3394 /* If insn is effectively movd N(sp),-(sp) then we will do the
3395 high word first. We should use the adjusted operand 1 (which is N+4(sp))
3396 for the low word as well, to compensate for the first decrement of sp. */
3397 if (optype0
== PUSHOP
3398 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
3399 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
3400 operands
[1] = middlehalf
[1] = latehalf
[1];
3402 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3403 if the upper part of reg N does not appear in the MEM, arrange to
3404 emit the move late-half first. Otherwise, compute the MEM address
3405 into the upper part of N and use that as a pointer to the memory
3407 if (optype0
== REGOP
3408 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3410 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3412 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3413 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3415 /* If both halves of dest are used in the src memory address,
3416 compute the address into latehalf of dest.
3417 Note that this can't happen if the dest is two data regs. */
3419 xops
[0] = latehalf
[0];
3420 xops
[1] = XEXP (operands
[1], 0);
3422 handle_compadr (xops
);
3423 if (GET_MODE (operands
[1]) == XFmode
)
3425 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3426 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3427 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3431 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3432 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3436 && reg_overlap_mentioned_p (middlehalf
[0],
3437 XEXP (operands
[1], 0)))
3439 /* Check for two regs used by both source and dest.
3440 Note that this can't happen if the dest is all data regs.
3441 It can happen if the dest is d6, d7, a0.
3442 But in that case, latehalf is an addr reg, so
3443 the code at compadr does ok. */
3445 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3446 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3449 /* JRV says this can't happen: */
3450 gcc_assert (!addreg0
&& !addreg1
);
3452 /* Only the middle reg conflicts; simply put it last. */
3453 handle_movsi (operands
);
3454 handle_movsi (latehalf
);
3455 handle_movsi (middlehalf
);
3459 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3460 /* If the low half of dest is mentioned in the source memory
3461 address, the arrange to emit the move late half first. */
3462 dest_overlapped_low
= 1;
3465 /* If one or both operands autodecrementing,
3466 do the two words, high-numbered first. */
3468 /* Likewise, the first move would clobber the source of the second one,
3469 do them in the other order. This happens only for registers;
3470 such overlap can't happen in memory unless the user explicitly
3471 sets it up, and that is an undefined circumstance. */
3473 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3474 || (optype0
== REGOP
&& optype1
== REGOP
3475 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3476 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3477 || dest_overlapped_low
)
3479 /* Make any unoffsettable addresses point at high-numbered word. */
3481 handle_reg_adjust (addreg0
, size
- 4);
3483 handle_reg_adjust (addreg1
, size
- 4);
3486 handle_movsi (latehalf
);
3488 /* Undo the adds we just did. */
3490 handle_reg_adjust (addreg0
, -4);
3492 handle_reg_adjust (addreg1
, -4);
3496 handle_movsi (middlehalf
);
3499 handle_reg_adjust (addreg0
, -4);
3501 handle_reg_adjust (addreg1
, -4);
3504 /* Do low-numbered word. */
3506 handle_movsi (operands
);
3510 /* Normal case: do the two words, low-numbered first. */
3512 handle_movsi (operands
);
3514 /* Do the middle one of the three words for long double */
3518 handle_reg_adjust (addreg0
, 4);
3520 handle_reg_adjust (addreg1
, 4);
3522 handle_movsi (middlehalf
);
3525 /* Make any unoffsettable addresses point at high-numbered word. */
3527 handle_reg_adjust (addreg0
, 4);
3529 handle_reg_adjust (addreg1
, 4);
3532 handle_movsi (latehalf
);
3534 /* Undo the adds we just did. */
3536 handle_reg_adjust (addreg0
, -(size
- 4));
3538 handle_reg_adjust (addreg1
, -(size
- 4));
3543 /* Output assembler code to adjust REG by N. */
3545 output_reg_adjust (rtx reg
, int n
)
3549 gcc_assert (GET_MODE (reg
) == SImode
3550 && -12 <= n
&& n
!= 0 && n
<= 12);
3555 s
= "add%.l #12,%0";
3559 s
= "addq%.l #8,%0";
3563 s
= "addq%.l #4,%0";
3567 s
= "sub%.l #12,%0";
3571 s
= "subq%.l #8,%0";
3575 s
= "subq%.l #4,%0";
3583 output_asm_insn (s
, ®
);
3586 /* Emit rtl code to adjust REG by N. */
3588 emit_reg_adjust (rtx reg1
, int n
)
3592 gcc_assert (GET_MODE (reg1
) == SImode
3593 && -12 <= n
&& n
!= 0 && n
<= 12);
3595 reg1
= copy_rtx (reg1
);
3596 reg2
= copy_rtx (reg1
);
3599 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3601 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3606 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3608 output_compadr (rtx operands
[2])
3610 output_asm_insn ("lea %a1,%0", operands
);
3613 /* Output the best assembler insn for moving operands[1] into operands[0]
3616 output_movsi (rtx operands
[2])
3618 output_asm_insn (singlemove_string (operands
), operands
);
3621 /* Copy OP and change its mode to MODE. */
3623 copy_operand (rtx op
, enum machine_mode mode
)
3625 /* ??? This looks really ugly. There must be a better way
3626 to change a mode on the operand. */
3627 if (GET_MODE (op
) != VOIDmode
)
3630 op
= gen_rtx_REG (mode
, REGNO (op
));
3634 PUT_MODE (op
, mode
);
3641 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3643 emit_movsi (rtx operands
[2])
3645 operands
[0] = copy_operand (operands
[0], SImode
);
3646 operands
[1] = copy_operand (operands
[1], SImode
);
3648 emit_insn (gen_movsi (operands
[0], operands
[1]));
3651 /* Output assembler code to perform a doubleword move insn
3652 with operands OPERANDS. */
3654 output_move_double (rtx
*operands
)
3656 handle_move_double (operands
,
3657 output_reg_adjust
, output_compadr
, output_movsi
);
3662 /* Output rtl code to perform a doubleword move insn
3663 with operands OPERANDS. */
3665 m68k_emit_move_double (rtx operands
[2])
3667 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3670 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3671 new rtx with the correct mode. */
3674 force_mode (enum machine_mode mode
, rtx orig
)
3676 if (mode
== GET_MODE (orig
))
3679 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3682 return gen_rtx_REG (mode
, REGNO (orig
));
3686 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3688 return reg_renumber
&& FP_REG_P (op
);
3691 /* Emit insns to move operands[1] into operands[0].
3693 Return 1 if we have written out everything that needs to be done to
3694 do the move. Otherwise, return 0 and the caller will emit the move
3697 Note SCRATCH_REG may not be in the proper mode depending on how it
3698 will be used. This routine is responsible for creating a new copy
3699 of SCRATCH_REG in the proper mode. */
3702 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3704 register rtx operand0
= operands
[0];
3705 register rtx operand1
= operands
[1];
3709 && reload_in_progress
&& GET_CODE (operand0
) == REG
3710 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3711 operand0
= reg_equiv_mem
[REGNO (operand0
)];
3712 else if (scratch_reg
3713 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3714 && GET_CODE (SUBREG_REG (operand0
)) == REG
3715 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3717 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3718 the code which tracks sets/uses for delete_output_reload. */
3719 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3720 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
3721 SUBREG_BYTE (operand0
));
3722 operand0
= alter_subreg (&temp
);
3726 && reload_in_progress
&& GET_CODE (operand1
) == REG
3727 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3728 operand1
= reg_equiv_mem
[REGNO (operand1
)];
3729 else if (scratch_reg
3730 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3731 && GET_CODE (SUBREG_REG (operand1
)) == REG
3732 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3734 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3735 the code which tracks sets/uses for delete_output_reload. */
3736 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3737 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
3738 SUBREG_BYTE (operand1
));
3739 operand1
= alter_subreg (&temp
);
3742 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3743 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3744 != XEXP (operand0
, 0)))
3745 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3746 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3747 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3748 != XEXP (operand1
, 0)))
3749 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3751 /* Handle secondary reloads for loads/stores of FP registers where
3752 the address is symbolic by using the scratch register */
3753 if (fp_reg_operand (operand0
, mode
)
3754 && ((GET_CODE (operand1
) == MEM
3755 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3756 || ((GET_CODE (operand1
) == SUBREG
3757 && GET_CODE (XEXP (operand1
, 0)) == MEM
3758 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3761 if (GET_CODE (operand1
) == SUBREG
)
3762 operand1
= XEXP (operand1
, 0);
3764 /* SCRATCH_REG will hold an address. We want
3765 it in SImode regardless of what mode it was originally given
3767 scratch_reg
= force_mode (SImode
, scratch_reg
);
3769 /* D might not fit in 14 bits either; for such cases load D into
3771 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3773 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3774 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3776 XEXP (XEXP (operand1
, 0), 0),
3780 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3781 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3782 gen_rtx_MEM (mode
, scratch_reg
)));
3785 else if (fp_reg_operand (operand1
, mode
)
3786 && ((GET_CODE (operand0
) == MEM
3787 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3788 || ((GET_CODE (operand0
) == SUBREG
)
3789 && GET_CODE (XEXP (operand0
, 0)) == MEM
3790 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3793 if (GET_CODE (operand0
) == SUBREG
)
3794 operand0
= XEXP (operand0
, 0);
3796 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3797 it in SIMODE regardless of what mode it was originally given
3799 scratch_reg
= force_mode (SImode
, scratch_reg
);
3801 /* D might not fit in 14 bits either; for such cases load D into
3803 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3805 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3806 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3809 XEXP (XEXP (operand0
, 0),
3814 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3815 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3819 /* Handle secondary reloads for loads of FP registers from constant
3820 expressions by forcing the constant into memory.
3822 use scratch_reg to hold the address of the memory location.
3824 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3825 NO_REGS when presented with a const_int and an register class
3826 containing only FP registers. Doing so unfortunately creates
3827 more problems than it solves. Fix this for 2.5. */
3828 else if (fp_reg_operand (operand0
, mode
)
3829 && CONSTANT_P (operand1
)
3834 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3835 it in SIMODE regardless of what mode it was originally given
3837 scratch_reg
= force_mode (SImode
, scratch_reg
);
3839 /* Force the constant into memory and put the address of the
3840 memory location into scratch_reg. */
3841 xoperands
[0] = scratch_reg
;
3842 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3843 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3845 /* Now load the destination register. */
3846 emit_insn (gen_rtx_SET (mode
, operand0
,
3847 gen_rtx_MEM (mode
, scratch_reg
)));
3851 /* Now have insn-emit do whatever it normally does. */
3855 /* Split one or more DImode RTL references into pairs of SImode
3856 references. The RTL can be REG, offsettable MEM, integer constant, or
3857 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3858 split and "num" is its length. lo_half and hi_half are output arrays
3859 that parallel "operands". */
3862 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3866 rtx op
= operands
[num
];
3868 /* simplify_subreg refuses to split volatile memory addresses,
3869 but we still have to handle it. */
3870 if (GET_CODE (op
) == MEM
)
3872 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3873 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3877 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3878 GET_MODE (op
) == VOIDmode
3879 ? DImode
: GET_MODE (op
), 4);
3880 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3881 GET_MODE (op
) == VOIDmode
3882 ? DImode
: GET_MODE (op
), 0);
3887 /* Split X into a base and a constant offset, storing them in *BASE
3888 and *OFFSET respectively. */
3891 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3894 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3896 *offset
+= INTVAL (XEXP (x
, 1));
3902 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3903 instruction. STORE_P says whether the move is a load or store.
3905 If the instruction uses post-increment or pre-decrement addressing,
3906 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3907 adjustment. This adjustment will be made by the first element of
3908 PARALLEL, with the loads or stores starting at element 1. If the
3909 instruction does not use post-increment or pre-decrement addressing,
3910 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3911 start at element 0. */
3914 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3915 HOST_WIDE_INT automod_offset
, bool store_p
)
3917 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3918 HOST_WIDE_INT offset
, mem_offset
;
3920 enum reg_class rclass
;
3922 len
= XVECLEN (pattern
, 0);
3923 first
= (automod_base
!= NULL
);
3927 /* Stores must be pre-decrement and loads must be post-increment. */
3928 if (store_p
!= (automod_offset
< 0))
3931 /* Work out the base and offset for lowest memory location. */
3932 base
= automod_base
;
3933 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3937 /* Allow any valid base and offset in the first access. */
3944 for (i
= first
; i
< len
; i
++)
3946 /* We need a plain SET. */
3947 set
= XVECEXP (pattern
, 0, i
);
3948 if (GET_CODE (set
) != SET
)
3951 /* Check that we have a memory location... */
3952 mem
= XEXP (set
, !store_p
);
3953 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3956 /* ...with the right address. */
3959 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3960 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3961 There are no mode restrictions for 680x0 besides the
3962 automodification rules enforced above. */
3964 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3969 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3970 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3974 /* Check that we have a register of the required mode and class. */
3975 reg
= XEXP (set
, store_p
);
3977 || !HARD_REGISTER_P (reg
)
3978 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3983 /* The register must belong to RCLASS and have a higher number
3984 than the register in the previous SET. */
3985 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3986 || REGNO (last_reg
) >= REGNO (reg
))
3991 /* Work out which register class we need. */
3992 if (INT_REGNO_P (REGNO (reg
)))
3993 rclass
= GENERAL_REGS
;
3994 else if (FP_REGNO_P (REGNO (reg
)))
4001 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
4004 /* If we have an automodification, check whether the final offset is OK. */
4005 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
4008 /* Reject unprofitable cases. */
4009 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
4015 /* Return the assembly code template for a movem or fmovem instruction
4016 whose pattern is given by PATTERN. Store the template's operands
4019 If the instruction uses post-increment or pre-decrement addressing,
4020 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
4021 is true if this is a store instruction. */
4024 m68k_output_movem (rtx
*operands
, rtx pattern
,
4025 HOST_WIDE_INT automod_offset
, bool store_p
)
4030 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
4032 first
= (automod_offset
!= 0);
4033 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
4035 /* When using movem with pre-decrement addressing, register X + D0_REG
4036 is controlled by bit 15 - X. For all other addressing modes,
4037 register X + D0_REG is controlled by bit X. Confusingly, the
4038 register mask for fmovem is in the opposite order to that for
4042 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
4043 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
4044 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
4045 if (automod_offset
< 0)
4047 if (FP_REGNO_P (regno
))
4048 mask
|= 1 << (regno
- FP0_REG
);
4050 mask
|= 1 << (15 - (regno
- D0_REG
));
4054 if (FP_REGNO_P (regno
))
4055 mask
|= 1 << (7 - (regno
- FP0_REG
));
4057 mask
|= 1 << (regno
- D0_REG
);
4062 if (automod_offset
== 0)
4063 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4064 else if (automod_offset
< 0)
4065 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4067 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4068 operands
[1] = GEN_INT (mask
);
4069 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4072 return "fmovem %1,%a0";
4074 return "fmovem %a0,%1";
4079 return "movem%.l %1,%a0";
4081 return "movem%.l %a0,%1";
4085 /* Return a REG that occurs in ADDR with coefficient 1.
4086 ADDR can be effectively incremented by incrementing REG. */
4089 find_addr_reg (rtx addr
)
4091 while (GET_CODE (addr
) == PLUS
)
4093 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4094 addr
= XEXP (addr
, 0);
4095 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4096 addr
= XEXP (addr
, 1);
4097 else if (CONSTANT_P (XEXP (addr
, 0)))
4098 addr
= XEXP (addr
, 1);
4099 else if (CONSTANT_P (XEXP (addr
, 1)))
4100 addr
= XEXP (addr
, 0);
4104 gcc_assert (GET_CODE (addr
) == REG
);
4108 /* Output assembler code to perform a 32-bit 3-operand add. */
4111 output_addsi3 (rtx
*operands
)
4113 if (! operands_match_p (operands
[0], operands
[1]))
4115 if (!ADDRESS_REG_P (operands
[1]))
4117 rtx tmp
= operands
[1];
4119 operands
[1] = operands
[2];
4123 /* These insns can result from reloads to access
4124 stack slots over 64k from the frame pointer. */
4125 if (GET_CODE (operands
[2]) == CONST_INT
4126 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4127 return "move%.l %2,%0\n\tadd%.l %1,%0";
4128 if (GET_CODE (operands
[2]) == REG
)
4129 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4130 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4132 if (GET_CODE (operands
[2]) == CONST_INT
)
4134 if (INTVAL (operands
[2]) > 0
4135 && INTVAL (operands
[2]) <= 8)
4136 return "addq%.l %2,%0";
4137 if (INTVAL (operands
[2]) < 0
4138 && INTVAL (operands
[2]) >= -8)
4140 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4141 return "subq%.l %2,%0";
4143 /* On the CPU32 it is faster to use two addql instructions to
4144 add a small integer (8 < N <= 16) to a register.
4145 Likewise for subql. */
4146 if (TUNE_CPU32
&& REG_P (operands
[0]))
4148 if (INTVAL (operands
[2]) > 8
4149 && INTVAL (operands
[2]) <= 16)
4151 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4152 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4154 if (INTVAL (operands
[2]) < -8
4155 && INTVAL (operands
[2]) >= -16)
4157 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4158 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4161 if (ADDRESS_REG_P (operands
[0])
4162 && INTVAL (operands
[2]) >= -0x8000
4163 && INTVAL (operands
[2]) < 0x8000)
4166 return "add%.w %2,%0";
4168 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4171 return "add%.l %2,%0";
4174 /* Store in cc_status the expressions that the condition codes will
4175 describe after execution of an instruction whose pattern is EXP.
4176 Do not alter them if the instruction would not alter the cc's. */
4178 /* On the 68000, all the insns to store in an address register fail to
4179 set the cc's. However, in some cases these instructions can make it
4180 possibly invalid to use the saved cc's. In those cases we clear out
4181 some or all of the saved cc's so they won't be used. */
4184 notice_update_cc (rtx exp
, rtx insn
)
4186 if (GET_CODE (exp
) == SET
)
4188 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4190 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4192 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4193 cc_status
.value1
= 0;
4194 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4195 cc_status
.value2
= 0;
4197 /* fmoves to memory or data registers do not set the condition
4198 codes. Normal moves _do_ set the condition codes, but not in
4199 a way that is appropriate for comparison with 0, because -0.0
4200 would be treated as a negative nonzero number. Note that it
4201 isn't appropriate to conditionalize this restriction on
4202 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4203 we care about the difference between -0.0 and +0.0. */
4204 else if (!FP_REG_P (SET_DEST (exp
))
4205 && SET_DEST (exp
) != cc0_rtx
4206 && (FP_REG_P (SET_SRC (exp
))
4207 || GET_CODE (SET_SRC (exp
)) == FIX
4208 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4210 /* A pair of move insns doesn't produce a useful overall cc. */
4211 else if (!FP_REG_P (SET_DEST (exp
))
4212 && !FP_REG_P (SET_SRC (exp
))
4213 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4214 && (GET_CODE (SET_SRC (exp
)) == REG
4215 || GET_CODE (SET_SRC (exp
)) == MEM
4216 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4218 else if (SET_DEST (exp
) != pc_rtx
)
4220 cc_status
.flags
= 0;
4221 cc_status
.value1
= SET_DEST (exp
);
4222 cc_status
.value2
= SET_SRC (exp
);
4225 else if (GET_CODE (exp
) == PARALLEL
4226 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4228 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4229 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4231 if (ADDRESS_REG_P (dest
))
4233 else if (dest
!= pc_rtx
)
4235 cc_status
.flags
= 0;
4236 cc_status
.value1
= dest
;
4237 cc_status
.value2
= src
;
4242 if (cc_status
.value2
!= 0
4243 && ADDRESS_REG_P (cc_status
.value2
)
4244 && GET_MODE (cc_status
.value2
) == QImode
)
4246 if (cc_status
.value2
!= 0)
4247 switch (GET_CODE (cc_status
.value2
))
4249 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4250 case ROTATE
: case ROTATERT
:
4251 /* These instructions always clear the overflow bit, and set
4252 the carry to the bit shifted out. */
4253 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4256 case PLUS
: case MINUS
: case MULT
:
4257 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4258 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4259 cc_status
.flags
|= CC_NO_OVERFLOW
;
4262 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4263 ends with a move insn moving r2 in r2's mode.
4264 Thus, the cc's are set for r2.
4265 This can set N bit spuriously. */
4266 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4271 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4273 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4274 cc_status
.value2
= 0;
4275 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4276 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4277 cc_status
.flags
= CC_IN_68881
;
4278 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4279 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4281 cc_status
.flags
= CC_IN_68881
;
4282 if (!FP_REG_P (XEXP (cc_status
.value2
, 0)))
4283 cc_status
.flags
|= CC_REVERSED
;
4288 output_move_const_double (rtx
*operands
)
4290 int code
= standard_68881_constant_p (operands
[1]);
4294 static char buf
[40];
4296 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4299 return "fmove%.d %1,%0";
4303 output_move_const_single (rtx
*operands
)
4305 int code
= standard_68881_constant_p (operands
[1]);
4309 static char buf
[40];
4311 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4314 return "fmove%.s %f1,%0";
4317 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4318 from the "fmovecr" instruction.
4319 The value, anded with 0xff, gives the code to use in fmovecr
4320 to get the desired constant. */
4322 /* This code has been fixed for cross-compilation. */
4324 static int inited_68881_table
= 0;
4326 static const char *const strings_68881
[7] = {
4336 static const int codes_68881
[7] = {
4346 REAL_VALUE_TYPE values_68881
[7];
4348 /* Set up values_68881 array by converting the decimal values
4349 strings_68881 to binary. */
4352 init_68881_table (void)
4356 enum machine_mode mode
;
4359 for (i
= 0; i
< 7; i
++)
4363 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4364 values_68881
[i
] = r
;
4366 inited_68881_table
= 1;
4370 standard_68881_constant_p (rtx x
)
4375 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4376 used at all on those chips. */
4380 if (! inited_68881_table
)
4381 init_68881_table ();
4383 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4385 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4387 for (i
= 0; i
< 6; i
++)
4389 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4390 return (codes_68881
[i
]);
4393 if (GET_MODE (x
) == SFmode
)
4396 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4397 return (codes_68881
[6]);
4399 /* larger powers of ten in the constants ram are not used
4400 because they are not equal to a `double' C constant. */
4404 /* If X is a floating-point constant, return the logarithm of X base 2,
4405 or 0 if X is not a power of 2. */
4408 floating_exact_log2 (rtx x
)
4410 REAL_VALUE_TYPE r
, r1
;
4413 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4415 if (REAL_VALUES_LESS (r
, dconst1
))
4418 exp
= real_exponent (&r
);
4419 real_2expN (&r1
, exp
, DFmode
);
4420 if (REAL_VALUES_EQUAL (r1
, r
))
4426 /* A C compound statement to output to stdio stream STREAM the
4427 assembler syntax for an instruction operand X. X is an RTL
4430 CODE is a value that can be used to specify one of several ways
4431 of printing the operand. It is used when identical operands
4432 must be printed differently depending on the context. CODE
4433 comes from the `%' specification that was used to request
4434 printing of the operand. If the specification was just `%DIGIT'
4435 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4436 is the ASCII code for LTR.
4438 If X is a register, this macro should print the register's name.
4439 The names can be found in an array `reg_names' whose type is
4440 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4442 When the machine description has a specification `%PUNCT' (a `%'
4443 followed by a punctuation character), this macro is called with
4444 a null pointer for X and the punctuation character for CODE.
4446 The m68k specific codes are:
4448 '.' for dot needed in Motorola-style opcode names.
4449 '-' for an operand pushing on the stack:
4450 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4451 '+' for an operand pushing on the stack:
4452 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4453 '@' for a reference to the top word on the stack:
4454 sp@, (sp) or (%sp) depending on the style of syntax.
4455 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4456 but & in SGS syntax).
4457 '!' for the cc register (used in an `and to cc' insn).
4458 '$' for the letter `s' in an op code, but only on the 68040.
4459 '&' for the letter `d' in an op code, but only on the 68040.
4460 '/' for register prefix needed by longlong.h.
4461 '?' for m68k_library_id_string
4463 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4464 'd' to force memory addressing to be absolute, not relative.
4465 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4466 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4467 or print pair of registers as rx:ry.
4468 'p' print an address with @PLTPC attached, but only if the operand
4469 is not locally-bound. */
4472 print_operand (FILE *file
, rtx op
, int letter
)
4477 fprintf (file
, ".");
4479 else if (letter
== '#')
4480 asm_fprintf (file
, "%I");
4481 else if (letter
== '-')
4482 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4483 else if (letter
== '+')
4484 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4485 else if (letter
== '@')
4486 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4487 else if (letter
== '!')
4488 asm_fprintf (file
, "%Rfpcr");
4489 else if (letter
== '$')
4492 fprintf (file
, "s");
4494 else if (letter
== '&')
4497 fprintf (file
, "d");
4499 else if (letter
== '/')
4500 asm_fprintf (file
, "%R");
4501 else if (letter
== '?')
4502 asm_fprintf (file
, m68k_library_id_string
);
4503 else if (letter
== 'p')
4505 output_addr_const (file
, op
);
4506 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4507 fprintf (file
, "@PLTPC");
4509 else if (GET_CODE (op
) == REG
)
4512 /* Print out the second register name of a register pair.
4513 I.e., R (6) => 7. */
4514 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4516 fputs (M68K_REGNAME(REGNO (op
)), file
);
4518 else if (GET_CODE (op
) == MEM
)
4520 output_address (XEXP (op
, 0));
4521 if (letter
== 'd' && ! TARGET_68020
4522 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4523 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4524 && INTVAL (XEXP (op
, 0)) < 0x8000
4525 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4526 fprintf (file
, MOTOROLA
? ".l" : ":l");
4528 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4532 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4533 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4534 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4536 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4540 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4541 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4542 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4543 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4545 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4549 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4550 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4551 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4555 /* Use `print_operand_address' instead of `output_addr_const'
4556 to ensure that we print relevant PIC stuff. */
4557 asm_fprintf (file
, "%I");
4559 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4560 print_operand_address (file
, op
);
4562 output_addr_const (file
, op
);
4566 /* Return string for TLS relocation RELOC. */
4569 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4571 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4572 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4579 if (flag_pic
== 1 && TARGET_68020
)
4620 /* m68k implementation of OUTPUT_ADDR_CONST_EXTRA. */
4623 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4625 if (GET_CODE (x
) == UNSPEC
)
4627 switch (XINT (x
, 1))
4629 case UNSPEC_RELOC16
:
4630 case UNSPEC_RELOC32
:
4631 output_addr_const (file
, XVECEXP (x
, 0, 0));
4632 fputs (m68k_get_reloc_decoration
4633 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4644 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4647 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4649 gcc_assert (size
== 4);
4650 fputs ("\t.long\t", file
);
4651 output_addr_const (file
, x
);
4652 fputs ("@TLSLDO+0x8000", file
);
4655 /* In the name of slightly smaller debug output, and to cater to
4656 general assembler lossage, recognize various UNSPEC sequences
4657 and turn them back into a direct symbol reference. */
4660 m68k_delegitimize_address (rtx orig_x
)
4663 struct m68k_address addr
;
4666 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4671 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4674 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4675 || addr
.offset
== NULL_RTX
4676 || GET_CODE (addr
.offset
) != CONST
)
4679 unspec
= XEXP (addr
.offset
, 0);
4680 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4681 unspec
= XEXP (unspec
, 0);
4682 if (GET_CODE (unspec
) != UNSPEC
4683 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4684 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4686 x
= XVECEXP (unspec
, 0, 0);
4687 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4688 if (unspec
!= XEXP (addr
.offset
, 0))
4689 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4692 rtx idx
= addr
.index
;
4693 if (addr
.scale
!= 1)
4694 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4695 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4698 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4700 x
= replace_equiv_address_nv (orig_x
, x
);
4705 /* A C compound statement to output to stdio stream STREAM the
4706 assembler syntax for an instruction operand that is a memory
4707 reference whose address is ADDR. ADDR is an RTL expression.
4709 Note that this contains a kludge that knows that the only reason
4710 we have an address (plus (label_ref...) (reg...)) when not generating
4711 PIC code is in the insn before a tablejump, and we know that m68k.md
4712 generates a label LInnn: on such an insn.
4714 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4715 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4717 This routine is responsible for distinguishing between -fpic and -fPIC
4718 style relocations in an address. When generating -fpic code the
4719 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4720 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4723 print_operand_address (FILE *file
, rtx addr
)
4725 struct m68k_address address
;
4727 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4730 if (address
.code
== PRE_DEC
)
4731 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4732 M68K_REGNAME (REGNO (address
.base
)));
4733 else if (address
.code
== POST_INC
)
4734 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4735 M68K_REGNAME (REGNO (address
.base
)));
4736 else if (!address
.base
&& !address
.index
)
4738 /* A constant address. */
4739 gcc_assert (address
.offset
== addr
);
4740 if (GET_CODE (addr
) == CONST_INT
)
4742 /* (xxx).w or (xxx).l. */
4743 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4744 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4746 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4748 else if (TARGET_PCREL
)
4750 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4752 output_addr_const (file
, addr
);
4753 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4757 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4758 name ends in `.<letter>', as the last 2 characters can be
4759 mistaken as a size suffix. Put the name in parentheses. */
4760 if (GET_CODE (addr
) == SYMBOL_REF
4761 && strlen (XSTR (addr
, 0)) > 2
4762 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4765 output_addr_const (file
, addr
);
4769 output_addr_const (file
, addr
);
4776 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4777 label being accessed, otherwise it is -1. */
4778 labelno
= (address
.offset
4780 && GET_CODE (address
.offset
) == LABEL_REF
4781 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4785 /* Print the "offset(base" component. */
4787 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4791 output_addr_const (file
, address
.offset
);
4795 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4797 /* Print the ",index" component, if any. */
4802 fprintf (file
, "%s.%c",
4803 M68K_REGNAME (REGNO (address
.index
)),
4804 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4805 if (address
.scale
!= 1)
4806 fprintf (file
, "*%d", address
.scale
);
4810 else /* !MOTOROLA */
4812 if (!address
.offset
&& !address
.index
)
4813 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4816 /* Print the "base@(offset" component. */
4818 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4822 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4823 fprintf (file
, "@(");
4825 output_addr_const (file
, address
.offset
);
4827 /* Print the ",index" component, if any. */
4830 fprintf (file
, ",%s:%c",
4831 M68K_REGNAME (REGNO (address
.index
)),
4832 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4833 if (address
.scale
!= 1)
4834 fprintf (file
, ":%d", address
.scale
);
4842 /* Check for cases where a clr insns can be omitted from code using
4843 strict_low_part sets. For example, the second clrl here is not needed:
4844 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4846 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4847 insn we are checking for redundancy. TARGET is the register set by the
4851 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4856 while ((p
= PREV_INSN (p
)))
4858 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4864 /* If it isn't an insn, then give up. */
4868 if (reg_set_p (target
, p
))
4870 rtx set
= single_set (p
);
4873 /* If it isn't an easy to recognize insn, then give up. */
4877 dest
= SET_DEST (set
);
4879 /* If this sets the entire target register to zero, then our
4880 first_insn is redundant. */
4881 if (rtx_equal_p (dest
, target
)
4882 && SET_SRC (set
) == const0_rtx
)
4884 else if (GET_CODE (dest
) == STRICT_LOW_PART
4885 && GET_CODE (XEXP (dest
, 0)) == REG
4886 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4887 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4888 <= GET_MODE_SIZE (mode
)))
4889 /* This is a strict low part set which modifies less than
4890 we are using, so it is safe. */
4900 /* Operand predicates for implementing asymmetric pc-relative addressing
4901 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4902 when used as a source operand, but not as a destination operand.
4904 We model this by restricting the meaning of the basic predicates
4905 (general_operand, memory_operand, etc) to forbid the use of this
4906 addressing mode, and then define the following predicates that permit
4907 this addressing mode. These predicates can then be used for the
4908 source operands of the appropriate instructions.
4910 n.b. While it is theoretically possible to change all machine patterns
4911 to use this addressing more where permitted by the architecture,
4912 it has only been implemented for "common" cases: SImode, HImode, and
4913 QImode operands, and only for the principle operations that would
4914 require this addressing mode: data movement and simple integer operations.
4916 In parallel with these new predicates, two new constraint letters
4917 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4918 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4919 In the pcrel case 's' is only valid in combination with 'a' registers.
4920 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4921 of how these constraints are used.
4923 The use of these predicates is strictly optional, though patterns that
4924 don't will cause an extra reload register to be allocated where one
4927 lea (abc:w,%pc),%a0 ; need to reload address
4928 moveq &1,%d1 ; since write to pc-relative space
4929 movel %d1,%a0@ ; is not allowed
4931 lea (abc:w,%pc),%a1 ; no need to reload address here
4932 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4934 For more info, consult tiemann@cygnus.com.
4937 All of the ugliness with predicates and constraints is due to the
4938 simple fact that the m68k does not allow a pc-relative addressing
4939 mode as a destination. gcc does not distinguish between source and
4940 destination addresses. Hence, if we claim that pc-relative address
4941 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4942 end up with invalid code. To get around this problem, we left
4943 pc-relative modes as invalid addresses, and then added special
4944 predicates and constraints to accept them.
4946 A cleaner way to handle this is to modify gcc to distinguish
4947 between source and destination addresses. We can then say that
4948 pc-relative is a valid source address but not a valid destination
4949 address, and hopefully avoid a lot of the predicate and constraint
4950 hackery. Unfortunately, this would be a pretty big change. It would
4951 be a useful change for a number of ports, but there aren't any current
4952 plans to undertake this.
4954 ***************************************************************************/
4958 output_andsi3 (rtx
*operands
)
4961 if (GET_CODE (operands
[2]) == CONST_INT
4962 && (INTVAL (operands
[2]) | 0xffff) == -1
4963 && (DATA_REG_P (operands
[0])
4964 || offsettable_memref_p (operands
[0]))
4965 && !TARGET_COLDFIRE
)
4967 if (GET_CODE (operands
[0]) != REG
)
4968 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4969 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4970 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4972 if (operands
[2] == const0_rtx
)
4974 return "and%.w %2,%0";
4976 if (GET_CODE (operands
[2]) == CONST_INT
4977 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4978 && (DATA_REG_P (operands
[0])
4979 || offsettable_memref_p (operands
[0])))
4981 if (DATA_REG_P (operands
[0]))
4982 operands
[1] = GEN_INT (logval
);
4985 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4986 operands
[1] = GEN_INT (logval
% 8);
4988 /* This does not set condition codes in a standard way. */
4990 return "bclr %1,%0";
4992 return "and%.l %2,%0";
4996 output_iorsi3 (rtx
*operands
)
4998 register int logval
;
4999 if (GET_CODE (operands
[2]) == CONST_INT
5000 && INTVAL (operands
[2]) >> 16 == 0
5001 && (DATA_REG_P (operands
[0])
5002 || offsettable_memref_p (operands
[0]))
5003 && !TARGET_COLDFIRE
)
5005 if (GET_CODE (operands
[0]) != REG
)
5006 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5007 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5009 if (INTVAL (operands
[2]) == 0xffff)
5010 return "mov%.w %2,%0";
5011 return "or%.w %2,%0";
5013 if (GET_CODE (operands
[2]) == CONST_INT
5014 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5015 && (DATA_REG_P (operands
[0])
5016 || offsettable_memref_p (operands
[0])))
5018 if (DATA_REG_P (operands
[0]))
5019 operands
[1] = GEN_INT (logval
);
5022 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5023 operands
[1] = GEN_INT (logval
% 8);
5026 return "bset %1,%0";
5028 return "or%.l %2,%0";
5032 output_xorsi3 (rtx
*operands
)
5034 register int logval
;
5035 if (GET_CODE (operands
[2]) == CONST_INT
5036 && INTVAL (operands
[2]) >> 16 == 0
5037 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
5038 && !TARGET_COLDFIRE
)
5040 if (! DATA_REG_P (operands
[0]))
5041 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5042 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5044 if (INTVAL (operands
[2]) == 0xffff)
5046 return "eor%.w %2,%0";
5048 if (GET_CODE (operands
[2]) == CONST_INT
5049 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5050 && (DATA_REG_P (operands
[0])
5051 || offsettable_memref_p (operands
[0])))
5053 if (DATA_REG_P (operands
[0]))
5054 operands
[1] = GEN_INT (logval
);
5057 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5058 operands
[1] = GEN_INT (logval
% 8);
5061 return "bchg %1,%0";
5063 return "eor%.l %2,%0";
5066 /* Return the instruction that should be used for a call to address X,
5067 which is known to be in operand 0. */
5072 if (symbolic_operand (x
, VOIDmode
))
5073 return m68k_symbolic_call
;
5078 /* Likewise sibling calls. */
5081 output_sibcall (rtx x
)
5083 if (symbolic_operand (x
, VOIDmode
))
5084 return m68k_symbolic_jump
;
5090 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5091 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5094 rtx this_slot
, offset
, addr
, mem
, insn
, tmp
;
5096 /* Avoid clobbering the struct value reg by using the
5097 static chain reg as a temporary. */
5098 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5100 /* Pretend to be a post-reload pass while generating rtl. */
5101 reload_completed
= 1;
5103 /* The "this" pointer is stored at 4(%sp). */
5104 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
, 4));
5106 /* Add DELTA to THIS. */
5109 /* Make the offset a legitimate operand for memory addition. */
5110 offset
= GEN_INT (delta
);
5111 if ((delta
< -8 || delta
> 8)
5112 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5114 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5115 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5117 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5118 copy_rtx (this_slot
), offset
));
5121 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5122 if (vcall_offset
!= 0)
5124 /* Set the static chain register to *THIS. */
5125 emit_move_insn (tmp
, this_slot
);
5126 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5128 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5129 addr
= plus_constant (tmp
, vcall_offset
);
5130 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5132 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5136 /* Load the offset into %d0 and add it to THIS. */
5137 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5138 gen_rtx_MEM (Pmode
, addr
));
5139 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5140 copy_rtx (this_slot
),
5141 gen_rtx_REG (Pmode
, D0_REG
)));
5144 /* Jump to the target function. Use a sibcall if direct jumps are
5145 allowed, otherwise load the address into a register first. */
5146 mem
= DECL_RTL (function
);
5147 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5149 gcc_assert (flag_pic
);
5151 if (!TARGET_SEP_DATA
)
5153 /* Use the static chain register as a temporary (call-clobbered)
5154 GOT pointer for this function. We can use the static chain
5155 register because it isn't live on entry to the thunk. */
5156 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5157 emit_insn (gen_load_got (pic_offset_table_rtx
));
5159 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5160 mem
= replace_equiv_address (mem
, tmp
);
5162 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5163 SIBLING_CALL_P (insn
) = 1;
5165 /* Run just enough of rest_of_compilation. */
5166 insn
= get_insns ();
5167 split_all_insns_noflow ();
5168 final_start_function (insn
, file
, 1);
5169 final (insn
, file
, 1);
5170 final_end_function ();
5172 /* Clean up the vars set above. */
5173 reload_completed
= 0;
5175 /* Restore the original PIC register. */
5177 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5180 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5183 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5184 int incoming ATTRIBUTE_UNUSED
)
5186 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5189 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5191 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5192 unsigned int new_reg
)
5195 /* Interrupt functions can only use registers that have already been
5196 saved by the prologue, even if they would normally be
5199 if ((m68k_get_function_kind (current_function_decl
)
5200 == m68k_fk_interrupt_handler
)
5201 && !df_regs_ever_live_p (new_reg
))
5207 /* Value is true if hard register REGNO can hold a value of machine-mode
5208 MODE. On the 68000, we let the cpu registers can hold any mode, but
5209 restrict the 68881 registers to floating-point modes. */
5212 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
5214 if (DATA_REGNO_P (regno
))
5216 /* Data Registers, can hold aggregate if fits in. */
5217 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5220 else if (ADDRESS_REGNO_P (regno
))
5222 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5225 else if (FP_REGNO_P (regno
))
5227 /* FPU registers, hold float or complex float of long double or
5229 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5230 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5231 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5237 /* Implement SECONDARY_RELOAD_CLASS. */
5240 m68k_secondary_reload_class (enum reg_class rclass
,
5241 enum machine_mode mode
, rtx x
)
5245 regno
= true_regnum (x
);
5247 /* If one operand of a movqi is an address register, the other
5248 operand must be a general register or constant. Other types
5249 of operand must be reloaded through a data register. */
5250 if (GET_MODE_SIZE (mode
) == 1
5251 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5252 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5255 /* PC-relative addresses must be loaded into an address register first. */
5257 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5258 && symbolic_operand (x
, VOIDmode
))
5264 /* Implement PREFERRED_RELOAD_CLASS. */
5267 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5269 enum reg_class secondary_class
;
5271 /* If RCLASS might need a secondary reload, try restricting it to
5272 a class that doesn't. */
5273 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5274 if (secondary_class
!= NO_REGS
5275 && reg_class_subset_p (secondary_class
, rclass
))
5276 return secondary_class
;
5278 /* Prefer to use moveq for in-range constants. */
5279 if (GET_CODE (x
) == CONST_INT
5280 && reg_class_subset_p (DATA_REGS
, rclass
)
5281 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5284 /* ??? Do we really need this now? */
5285 if (GET_CODE (x
) == CONST_DOUBLE
5286 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5288 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5297 /* Return floating point values in a 68881 register. This makes 68881 code
5298 a little bit faster. It also makes -msoft-float code incompatible with
5299 hard-float code, so people have to be careful not to mix the two.
5300 For ColdFire it was decided the ABI incompatibility is undesirable.
5301 If there is need for a hard-float ABI it is probably worth doing it
5302 properly and also passing function arguments in FP registers. */
5304 m68k_libcall_value (enum machine_mode mode
)
5311 return gen_rtx_REG (mode
, FP0_REG
);
5317 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5320 /* Location in which function value is returned.
5321 NOTE: Due to differences in ABIs, don't call this function directly,
5322 use FUNCTION_VALUE instead. */
5324 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5326 enum machine_mode mode
;
5328 mode
= TYPE_MODE (valtype
);
5334 return gen_rtx_REG (mode
, FP0_REG
);
5340 /* If the function returns a pointer, push that into %a0. */
5341 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5342 /* For compatibility with the large body of existing code which
5343 does not always properly declare external functions returning
5344 pointer types, the m68k/SVR4 convention is to copy the value
5345 returned for pointer functions from a0 to d0 in the function
5346 epilogue, so that callers that have neglected to properly
5347 declare the callee can still find the correct return value in
5349 return gen_rtx_PARALLEL
5352 gen_rtx_EXPR_LIST (VOIDmode
,
5353 gen_rtx_REG (mode
, A0_REG
),
5355 gen_rtx_EXPR_LIST (VOIDmode
,
5356 gen_rtx_REG (mode
, D0_REG
),
5358 else if (POINTER_TYPE_P (valtype
))
5359 return gen_rtx_REG (mode
, A0_REG
);
5361 return gen_rtx_REG (mode
, D0_REG
);
5364 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5365 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5367 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5369 enum machine_mode mode
= TYPE_MODE (type
);
5371 if (mode
== BLKmode
)
5374 /* If TYPE's known alignment is less than the alignment of MODE that
5375 would contain the structure, then return in memory. We need to
5376 do so to maintain the compatibility between code compiled with
5377 -mstrict-align and that compiled with -mno-strict-align. */
5378 if (AGGREGATE_TYPE_P (type
)
5379 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5386 /* CPU to schedule the program for. */
5387 enum attr_cpu m68k_sched_cpu
;
5389 /* MAC to schedule the program for. */
5390 enum attr_mac m68k_sched_mac
;
5398 /* Integer register. */
5404 /* Implicit mem reference (e.g. stack). */
5407 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5410 /* Memory with offset but without indexing. EA mode 5. */
5413 /* Memory with indexing. EA mode 6. */
5416 /* Memory referenced by absolute address. EA mode 7. */
5419 /* Immediate operand that doesn't require extension word. */
5422 /* Immediate 16 bit operand. */
5425 /* Immediate 32 bit operand. */
5429 /* Return type of memory ADDR_RTX refers to. */
5430 static enum attr_op_type
5431 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
5433 struct m68k_address address
;
5435 if (symbolic_operand (addr_rtx
, VOIDmode
))
5436 return OP_TYPE_MEM7
;
5438 if (!m68k_decompose_address (mode
, addr_rtx
,
5439 reload_completed
, &address
))
5441 gcc_assert (!reload_completed
);
5442 /* Reload will likely fix the address to be in the register. */
5443 return OP_TYPE_MEM234
;
5446 if (address
.scale
!= 0)
5447 return OP_TYPE_MEM6
;
5449 if (address
.base
!= NULL_RTX
)
5451 if (address
.offset
== NULL_RTX
)
5452 return OP_TYPE_MEM234
;
5454 return OP_TYPE_MEM5
;
5457 gcc_assert (address
.offset
!= NULL_RTX
);
5459 return OP_TYPE_MEM7
;
5462 /* Return X or Y (depending on OPX_P) operand of INSN. */
5464 sched_get_operand (rtx insn
, bool opx_p
)
5468 if (recog_memoized (insn
) < 0)
5471 extract_constrain_insn_cached (insn
);
5474 i
= get_attr_opx (insn
);
5476 i
= get_attr_opy (insn
);
5478 if (i
>= recog_data
.n_operands
)
5481 return recog_data
.operand
[i
];
5484 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5485 If ADDRESS_P is true, return type of memory location operand refers to. */
5486 static enum attr_op_type
5487 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
5491 op
= sched_get_operand (insn
, opx_p
);
5495 gcc_assert (!reload_completed
);
5500 return sched_address_type (QImode
, op
);
5502 if (memory_operand (op
, VOIDmode
))
5503 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5505 if (register_operand (op
, VOIDmode
))
5507 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5508 || (reload_completed
&& FP_REG_P (op
)))
5514 if (GET_CODE (op
) == CONST_INT
)
5520 /* Check for quick constants. */
5521 switch (get_attr_type (insn
))
5524 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5525 return OP_TYPE_IMM_Q
;
5527 gcc_assert (!reload_completed
);
5531 if (USE_MOVQ (ival
))
5532 return OP_TYPE_IMM_Q
;
5534 gcc_assert (!reload_completed
);
5538 if (valid_mov3q_const (ival
))
5539 return OP_TYPE_IMM_Q
;
5541 gcc_assert (!reload_completed
);
5548 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5549 return OP_TYPE_IMM_W
;
5551 return OP_TYPE_IMM_L
;
5554 if (GET_CODE (op
) == CONST_DOUBLE
)
5556 switch (GET_MODE (op
))
5559 return OP_TYPE_IMM_W
;
5563 return OP_TYPE_IMM_L
;
5570 if (GET_CODE (op
) == CONST
5571 || symbolic_operand (op
, VOIDmode
)
5574 switch (GET_MODE (op
))
5577 return OP_TYPE_IMM_Q
;
5580 return OP_TYPE_IMM_W
;
5583 return OP_TYPE_IMM_L
;
5586 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5588 return OP_TYPE_IMM_W
;
5590 return OP_TYPE_IMM_L
;
5594 gcc_assert (!reload_completed
);
5596 if (FLOAT_MODE_P (GET_MODE (op
)))
5602 /* Implement opx_type attribute.
5603 Return type of INSN's operand X.
5604 If ADDRESS_P is true, return type of memory location operand refers to. */
5606 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
5608 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5614 return OPX_TYPE_FPN
;
5617 return OPX_TYPE_MEM1
;
5619 case OP_TYPE_MEM234
:
5620 return OPX_TYPE_MEM234
;
5623 return OPX_TYPE_MEM5
;
5626 return OPX_TYPE_MEM6
;
5629 return OPX_TYPE_MEM7
;
5632 return OPX_TYPE_IMM_Q
;
5635 return OPX_TYPE_IMM_W
;
5638 return OPX_TYPE_IMM_L
;
5645 /* Implement opy_type attribute.
5646 Return type of INSN's operand Y.
5647 If ADDRESS_P is true, return type of memory location operand refers to. */
5649 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
5651 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5657 return OPY_TYPE_FPN
;
5660 return OPY_TYPE_MEM1
;
5662 case OP_TYPE_MEM234
:
5663 return OPY_TYPE_MEM234
;
5666 return OPY_TYPE_MEM5
;
5669 return OPY_TYPE_MEM6
;
5672 return OPY_TYPE_MEM7
;
5675 return OPY_TYPE_IMM_Q
;
5678 return OPY_TYPE_IMM_W
;
5681 return OPY_TYPE_IMM_L
;
5688 /* Return size of INSN as int. */
5690 sched_get_attr_size_int (rtx insn
)
5694 switch (get_attr_type (insn
))
5697 /* There should be no references to m68k_sched_attr_size for 'ignore'
5711 switch (get_attr_opx_type (insn
))
5717 case OPX_TYPE_MEM234
:
5718 case OPY_TYPE_IMM_Q
:
5723 /* Here we assume that most absolute references are short. */
5725 case OPY_TYPE_IMM_W
:
5729 case OPY_TYPE_IMM_L
:
5737 switch (get_attr_opy_type (insn
))
5743 case OPY_TYPE_MEM234
:
5744 case OPY_TYPE_IMM_Q
:
5749 /* Here we assume that most absolute references are short. */
5751 case OPY_TYPE_IMM_W
:
5755 case OPY_TYPE_IMM_L
:
5765 gcc_assert (!reload_completed
);
5773 /* Return size of INSN as attribute enum value. */
5775 m68k_sched_attr_size (rtx insn
)
5777 switch (sched_get_attr_size_int (insn
))
5793 /* Return operand X or Y (depending on OPX_P) of INSN,
5794 if it is a MEM, or NULL overwise. */
5795 static enum attr_op_type
5796 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5800 switch (get_attr_opx_type (insn
))
5805 case OPX_TYPE_IMM_Q
:
5806 case OPX_TYPE_IMM_W
:
5807 case OPX_TYPE_IMM_L
:
5811 case OPX_TYPE_MEM234
:
5814 return OP_TYPE_MEM1
;
5817 return OP_TYPE_MEM6
;
5825 switch (get_attr_opy_type (insn
))
5830 case OPY_TYPE_IMM_Q
:
5831 case OPY_TYPE_IMM_W
:
5832 case OPY_TYPE_IMM_L
:
5836 case OPY_TYPE_MEM234
:
5839 return OP_TYPE_MEM1
;
5842 return OP_TYPE_MEM6
;
5850 /* Implement op_mem attribute. */
5852 m68k_sched_attr_op_mem (rtx insn
)
5854 enum attr_op_type opx
;
5855 enum attr_op_type opy
;
5857 opx
= sched_get_opxy_mem_type (insn
, true);
5858 opy
= sched_get_opxy_mem_type (insn
, false);
5860 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5863 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5865 switch (get_attr_opx_access (insn
))
5881 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5883 switch (get_attr_opx_access (insn
))
5899 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5902 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5904 switch (get_attr_opx_access (insn
))
5910 gcc_assert (!reload_completed
);
5915 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5917 switch (get_attr_opx_access (insn
))
5923 gcc_assert (!reload_completed
);
5928 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5931 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5933 switch (get_attr_opx_access (insn
))
5939 gcc_assert (!reload_completed
);
5944 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5945 gcc_assert (!reload_completed
);
5949 /* Jump instructions types. Indexed by INSN_UID.
5950 The same rtl insn can be expanded into different asm instructions
5951 depending on the cc0_status. To properly determine type of jump
5952 instructions we scan instruction stream and map jumps types to this
5954 static enum attr_type
*sched_branch_type
;
5956 /* Return the type of the jump insn. */
5958 m68k_sched_branch_type (rtx insn
)
5960 enum attr_type type
;
5962 type
= sched_branch_type
[INSN_UID (insn
)];
5964 gcc_assert (type
!= 0);
5969 /* Data for ColdFire V4 index bypass.
5970 Producer modifies register that is used as index in consumer with
5974 /* Producer instruction. */
5977 /* Consumer instruction. */
5980 /* Scale of indexed memory access within consumer.
5981 Or zero if bypass should not be effective at the moment. */
5983 } sched_cfv4_bypass_data
;
5985 /* An empty state that is used in m68k_sched_adjust_cost. */
5986 static state_t sched_adjust_cost_state
;
5988 /* Implement adjust_cost scheduler hook.
5989 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5991 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5996 if (recog_memoized (def_insn
) < 0
5997 || recog_memoized (insn
) < 0)
6000 if (sched_cfv4_bypass_data
.scale
== 1)
6001 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
6003 /* haifa-sched.c: insn_cost () calls bypass_p () just before
6004 targetm.sched.adjust_cost (). Hence, we can be relatively sure
6005 that the data in sched_cfv4_bypass_data is up to date. */
6006 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
6007 && sched_cfv4_bypass_data
.con
== insn
);
6012 sched_cfv4_bypass_data
.pro
= NULL
;
6013 sched_cfv4_bypass_data
.con
= NULL
;
6014 sched_cfv4_bypass_data
.scale
= 0;
6017 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6018 && sched_cfv4_bypass_data
.con
== NULL
6019 && sched_cfv4_bypass_data
.scale
== 0);
6021 /* Don't try to issue INSN earlier than DFA permits.
6022 This is especially useful for instructions that write to memory,
6023 as their true dependence (default) latency is better to be set to 0
6024 to workaround alias analysis limitations.
6025 This is, in fact, a machine independent tweak, so, probably,
6026 it should be moved to haifa-sched.c: insn_cost (). */
6027 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
6034 /* Return maximal number of insns that can be scheduled on a single cycle. */
6036 m68k_sched_issue_rate (void)
6038 switch (m68k_sched_cpu
)
6054 /* Maximal length of instruction for current CPU.
6055 E.g. it is 3 for any ColdFire core. */
6056 static int max_insn_size
;
6058 /* Data to model instruction buffer of CPU. */
6061 /* True if instruction buffer model is modeled for current CPU. */
6064 /* Size of the instruction buffer in words. */
6067 /* Number of filled words in the instruction buffer. */
6070 /* Additional information about instruction buffer for CPUs that have
6071 a buffer of instruction records, rather then a plain buffer
6072 of instruction words. */
6073 struct _sched_ib_records
6075 /* Size of buffer in records. */
6078 /* Array to hold data on adjustements made to the size of the buffer. */
6081 /* Index of the above array. */
6085 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6089 static struct _sched_ib sched_ib
;
6091 /* ID of memory unit. */
6092 static int sched_mem_unit_code
;
6094 /* Implementation of the targetm.sched.variable_issue () hook.
6095 It is called after INSN was issued. It returns the number of insns
6096 that can possibly get scheduled on the current cycle.
6097 It is used here to determine the effect of INSN on the instruction
6100 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6101 int sched_verbose ATTRIBUTE_UNUSED
,
6102 rtx insn
, int can_issue_more
)
6106 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6108 switch (m68k_sched_cpu
)
6112 insn_size
= sched_get_attr_size_int (insn
);
6116 insn_size
= sched_get_attr_size_int (insn
);
6118 /* ColdFire V3 and V4 cores have instruction buffers that can
6119 accumulate up to 8 instructions regardless of instructions'
6120 sizes. So we should take care not to "prefetch" 24 one-word
6121 or 12 two-words instructions.
6122 To model this behavior we temporarily decrease size of the
6123 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6127 adjust
= max_insn_size
- insn_size
;
6128 sched_ib
.size
-= adjust
;
6130 if (sched_ib
.filled
> sched_ib
.size
)
6131 sched_ib
.filled
= sched_ib
.size
;
6133 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6136 ++sched_ib
.records
.adjust_index
;
6137 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6138 sched_ib
.records
.adjust_index
= 0;
6140 /* Undo adjustement we did 7 instructions ago. */
6142 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6147 gcc_assert (!sched_ib
.enabled_p
);
6155 gcc_assert (insn_size
<= sched_ib
.filled
);
6158 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6159 || asm_noperands (PATTERN (insn
)) >= 0)
6160 insn_size
= sched_ib
.filled
;
6164 sched_ib
.filled
-= insn_size
;
6166 return can_issue_more
;
6169 /* Return how many instructions should scheduler lookahead to choose the
6172 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6174 return m68k_sched_issue_rate () - 1;
6177 /* Implementation of targetm.sched.init_global () hook.
6178 It is invoked once per scheduling pass and is used here
6179 to initialize scheduler constants. */
6181 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6182 int sched_verbose ATTRIBUTE_UNUSED
,
6183 int n_insns ATTRIBUTE_UNUSED
)
6185 /* Init branch types. */
6189 sched_branch_type
= XCNEWVEC (enum attr_type
, get_max_uid () + 1);
6191 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6194 /* !!! FIXME: Implement real scan here. */
6195 sched_branch_type
[INSN_UID (insn
)] = TYPE_BCC
;
6199 #ifdef ENABLE_CHECKING
6200 /* Check that all instructions have DFA reservations and
6201 that all instructions can be issued from a clean state. */
6206 state
= alloca (state_size ());
6208 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6210 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6212 gcc_assert (insn_has_dfa_reservation_p (insn
));
6214 state_reset (state
);
6215 if (state_transition (state
, insn
) >= 0)
6222 /* Setup target cpu. */
6224 /* ColdFire V4 has a set of features to keep its instruction buffer full
6225 (e.g., a separate memory bus for instructions) and, hence, we do not model
6226 buffer for this CPU. */
6227 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6229 switch (m68k_sched_cpu
)
6232 sched_ib
.filled
= 0;
6239 sched_ib
.records
.n_insns
= 0;
6240 sched_ib
.records
.adjust
= NULL
;
6245 sched_ib
.records
.n_insns
= 8;
6246 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6253 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6255 sched_adjust_cost_state
= xmalloc (state_size ());
6256 state_reset (sched_adjust_cost_state
);
6259 emit_insn (gen_ib ());
6260 sched_ib
.insn
= get_insns ();
6264 /* Scheduling pass is now finished. Free/reset static variables. */
6266 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6267 int verbose ATTRIBUTE_UNUSED
)
6269 sched_ib
.insn
= NULL
;
6271 free (sched_adjust_cost_state
);
6272 sched_adjust_cost_state
= NULL
;
6274 sched_mem_unit_code
= 0;
6276 free (sched_ib
.records
.adjust
);
6277 sched_ib
.records
.adjust
= NULL
;
6278 sched_ib
.records
.n_insns
= 0;
6281 free (sched_branch_type
);
6282 sched_branch_type
= NULL
;
6285 /* Implementation of targetm.sched.init () hook.
6286 It is invoked each time scheduler starts on the new block (basic block or
6287 extended basic block). */
6289 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6290 int sched_verbose ATTRIBUTE_UNUSED
,
6291 int n_insns ATTRIBUTE_UNUSED
)
6293 switch (m68k_sched_cpu
)
6301 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6303 memset (sched_ib
.records
.adjust
, 0,
6304 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6305 sched_ib
.records
.adjust_index
= 0;
6309 gcc_assert (!sched_ib
.enabled_p
);
6317 if (sched_ib
.enabled_p
)
6318 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6319 the first cycle. Workaround that. */
6320 sched_ib
.filled
= -2;
6323 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6324 It is invoked just before current cycle finishes and is used here
6325 to track if instruction buffer got its two words this cycle. */
6327 m68k_sched_dfa_pre_advance_cycle (void)
6329 if (!sched_ib
.enabled_p
)
6332 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6334 sched_ib
.filled
+= 2;
6336 if (sched_ib
.filled
> sched_ib
.size
)
6337 sched_ib
.filled
= sched_ib
.size
;
6341 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6342 It is invoked just after new cycle begins and is used here
6343 to setup number of filled words in the instruction buffer so that
6344 instructions which won't have all their words prefetched would be
6345 stalled for a cycle. */
6347 m68k_sched_dfa_post_advance_cycle (void)
6351 if (!sched_ib
.enabled_p
)
6354 /* Setup number of prefetched instruction words in the instruction
6356 i
= max_insn_size
- sched_ib
.filled
;
6360 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6365 /* Return X or Y (depending on OPX_P) operand of INSN,
6366 if it is an integer register, or NULL overwise. */
6368 sched_get_reg_operand (rtx insn
, bool opx_p
)
6374 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6376 op
= sched_get_operand (insn
, true);
6377 gcc_assert (op
!= NULL
);
6379 if (!reload_completed
&& !REG_P (op
))
6385 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6387 op
= sched_get_operand (insn
, false);
6388 gcc_assert (op
!= NULL
);
6390 if (!reload_completed
&& !REG_P (op
))
6398 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6401 sched_mem_operand_p (rtx insn
, bool opx_p
)
6403 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6414 /* Return X or Y (depending on OPX_P) operand of INSN,
6415 if it is a MEM, or NULL overwise. */
6417 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
6437 if (opy_p
&& sched_mem_operand_p (insn
, false))
6438 return sched_get_operand (insn
, false);
6440 if (opx_p
&& sched_mem_operand_p (insn
, true))
6441 return sched_get_operand (insn
, true);
6447 /* Return non-zero if PRO modifies register used as part of
6450 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
6455 pro_x
= sched_get_reg_operand (pro
, true);
6459 con_mem_read
= sched_get_mem_operand (con
, true, false);
6460 gcc_assert (con_mem_read
!= NULL
);
6462 if (reg_mentioned_p (pro_x
, con_mem_read
))
6468 /* Helper function for m68k_sched_indexed_address_bypass_p.
6469 if PRO modifies register used as index in CON,
6470 return scale of indexed memory access in CON. Return zero overwise. */
6472 sched_get_indexed_address_scale (rtx pro
, rtx con
)
6476 struct m68k_address address
;
6478 reg
= sched_get_reg_operand (pro
, true);
6482 mem
= sched_get_mem_operand (con
, true, false);
6483 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6485 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6489 if (REGNO (reg
) == REGNO (address
.index
))
6491 gcc_assert (address
.scale
!= 0);
6492 return address
.scale
;
6498 /* Return non-zero if PRO modifies register used
6499 as index with scale 2 or 4 in CON. */
6501 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
6503 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6504 && sched_cfv4_bypass_data
.con
== NULL
6505 && sched_cfv4_bypass_data
.scale
== 0);
6507 switch (sched_get_indexed_address_scale (pro
, con
))
6510 /* We can't have a variable latency bypass, so
6511 remember to adjust the insn cost in adjust_cost hook. */
6512 sched_cfv4_bypass_data
.pro
= pro
;
6513 sched_cfv4_bypass_data
.con
= con
;
6514 sched_cfv4_bypass_data
.scale
= 1;
6526 /* We generate a two-instructions program at M_TRAMP :
6527 movea.l &CHAIN_VALUE,%a0
6529 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6532 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6534 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6537 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6539 mem
= adjust_address (m_tramp
, HImode
, 0);
6540 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6541 mem
= adjust_address (m_tramp
, SImode
, 2);
6542 emit_move_insn (mem
, chain_value
);
6544 mem
= adjust_address (m_tramp
, HImode
, 6);
6545 emit_move_insn (mem
, GEN_INT(0x4EF9));
6546 mem
= adjust_address (m_tramp
, SImode
, 8);
6547 emit_move_insn (mem
, fnaddr
);
6549 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6552 /* On the 68000, the RTS insn cannot pop anything.
6553 On the 68010, the RTD insn may be used to pop them if the number
6554 of args is fixed, but if the number is variable then the caller
6555 must pop them all. RTD can't be used for library calls now
6556 because the library is compiled with the Unix compiler.
6557 Use of RTD is a selectable option, since it is incompatible with
6558 standard Unix calling sequences. If the option is not selected,
6559 the caller must always pop the args. */
6562 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6566 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6567 && (!stdarg_p (funtype
)))
6571 #include "gt-m68k.h"