1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with modified_between_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
95 #include "stor-layout.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
135 static rtx_insn
*i2mod
;
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 struct reg_stat_type
{
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx_insn
*last_death
;
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 static vec
<reg_stat_type
> reg_stat
;
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
265 static unsigned int reg_n_sets_max
;
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
270 static int mem_last_set
;
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
275 static int last_call_luid
;
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
283 static rtx_insn
*subst_insn
;
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
292 static int subst_low_luid
;
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
297 static HARD_REG_SET newpat_used_regs
;
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
303 static rtx_insn
*added_links_insn
;
305 /* And similarly, for notes. */
307 static rtx_insn
*added_notes_insn
;
309 /* Basic block in which we are performing combines. */
310 static basic_block this_basic_block
;
311 static bool optimize_this_for_speed_p
;
314 /* Length of the currently allocated uid_insn_cost array. */
316 static int max_uid_known
;
318 /* The following array records the insn_cost for every insn
319 in the instruction stream. */
321 static int *uid_insn_cost
;
323 /* The following array records the LOG_LINKS for every insn in the
324 instruction stream as struct insn_link pointers. */
329 struct insn_link
*next
;
332 static struct insn_link
**uid_log_links
;
335 insn_uid_check (const_rtx insn
)
337 int uid
= INSN_UID (insn
);
338 gcc_checking_assert (uid
<= max_uid_known
);
342 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
343 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
345 #define FOR_EACH_LOG_LINK(L, INSN) \
346 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
348 /* Links for LOG_LINKS are allocated from this obstack. */
350 static struct obstack insn_link_obstack
;
352 /* Allocate a link. */
354 static inline struct insn_link
*
355 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
358 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
359 sizeof (struct insn_link
));
366 /* Incremented for each basic block. */
368 static int label_tick
;
370 /* Reset to label_tick for each extended basic block in scanning order. */
372 static int label_tick_ebb_start
;
374 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
375 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
377 static scalar_int_mode nonzero_bits_mode
;
379 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
380 be safely used. It is zero while computing them and after combine has
381 completed. This former test prevents propagating values based on
382 previously set values, which can be incorrect if a variable is modified
385 static int nonzero_sign_valid
;
388 /* Record one modification to rtl structure
389 to be undone by storing old_contents into *where. */
391 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
397 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
398 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
401 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
402 num_undo says how many are currently recorded.
404 other_insn is nonzero if we have modified some other insn in the process
405 of working on subst_insn. It must be verified too. */
411 rtx_insn
*other_insn
;
414 static struct undobuf undobuf
;
416 /* Number of times the pseudo being substituted for
417 was found and replaced. */
419 static int n_occurrences
;
421 static rtx
reg_nonzero_bits_for_combine (const_rtx
, scalar_int_mode
,
423 unsigned HOST_WIDE_INT
*);
424 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, scalar_int_mode
,
427 static void do_SUBST (rtx
*, rtx
);
428 static void do_SUBST_INT (int *, int);
429 static void init_reg_last (void);
430 static void setup_incoming_promotions (rtx_insn
*);
431 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
432 static int cant_combine_insn_p (rtx_insn
*);
433 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
434 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
435 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
436 static int contains_muldiv (rtx
);
437 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
439 static void undo_all (void);
440 static void undo_commit (void);
441 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
442 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
443 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
444 static rtx
simplify_if_then_else (rtx
);
445 static rtx
simplify_set (rtx
);
446 static rtx
simplify_logical (rtx
);
447 static rtx
expand_compound_operation (rtx
);
448 static const_rtx
expand_field_assignment (const_rtx
);
449 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
450 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
451 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
452 unsigned HOST_WIDE_INT
*);
453 static rtx
canon_reg_for_combine (rtx
, rtx
);
454 static rtx
force_int_to_mode (rtx
, scalar_int_mode
, scalar_int_mode
,
455 scalar_int_mode
, unsigned HOST_WIDE_INT
, int);
456 static rtx
force_to_mode (rtx
, machine_mode
,
457 unsigned HOST_WIDE_INT
, int);
458 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
459 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
460 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
461 static rtx
make_field_assignment (rtx
);
462 static rtx
apply_distributive_law (rtx
);
463 static rtx
distribute_and_simplify_rtx (rtx
, int);
464 static rtx
simplify_and_const_int_1 (scalar_int_mode
, rtx
,
465 unsigned HOST_WIDE_INT
);
466 static rtx
simplify_and_const_int (rtx
, scalar_int_mode
, rtx
,
467 unsigned HOST_WIDE_INT
);
468 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
469 HOST_WIDE_INT
, machine_mode
, int *);
470 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
471 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
473 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
474 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
475 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
477 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
478 static void update_table_tick (rtx
);
479 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
480 static void check_promoted_subreg (rtx_insn
*, rtx
);
481 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
482 static void record_dead_and_set_regs (rtx_insn
*);
483 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
484 static rtx
get_last_value (const_rtx
);
485 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
486 static int reg_dead_at_p (rtx
, rtx_insn
*);
487 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
488 static int reg_bitfield_target_p (rtx
, rtx
);
489 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
490 static void distribute_links (struct insn_link
*);
491 static void mark_used_regs_combine (rtx
);
492 static void record_promoted_value (rtx_insn
*, rtx
);
493 static bool unmentioned_reg_p (rtx
, rtx
);
494 static void record_truncated_values (rtx
*, void *);
495 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
496 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
499 /* It is not safe to use ordinary gen_lowpart in combine.
500 See comments in gen_lowpart_for_combine. */
501 #undef RTL_HOOKS_GEN_LOWPART
502 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
504 /* Our implementation of gen_lowpart never emits a new pseudo. */
505 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
506 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
508 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
509 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
511 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
512 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
514 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
515 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
517 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
520 /* Convenience wrapper for the canonicalize_comparison target hook.
521 Target hooks cannot use enum rtx_code. */
523 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
524 bool op0_preserve_value
)
526 int code_int
= (int)*code
;
527 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
528 *code
= (enum rtx_code
)code_int
;
531 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
532 PATTERN can not be split. Otherwise, it returns an insn sequence.
533 This is a wrapper around split_insns which ensures that the
534 reg_stat vector is made larger if the splitter creates a new
538 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
543 ret
= split_insns (pattern
, insn
);
544 nregs
= max_reg_num ();
545 if (nregs
> reg_stat
.length ())
546 reg_stat
.safe_grow_cleared (nregs
);
550 /* This is used by find_single_use to locate an rtx in LOC that
551 contains exactly one use of DEST, which is typically either a REG
552 or CC0. It returns a pointer to the innermost rtx expression
553 containing DEST. Appearances of DEST that are being used to
554 totally replace it are not counted. */
557 find_single_use_1 (rtx dest
, rtx
*loc
)
560 enum rtx_code code
= GET_CODE (x
);
576 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
577 of a REG that occupies all of the REG, the insn uses DEST if
578 it is mentioned in the destination or the source. Otherwise, we
579 need just check the source. */
580 if (GET_CODE (SET_DEST (x
)) != CC0
581 && GET_CODE (SET_DEST (x
)) != PC
582 && !REG_P (SET_DEST (x
))
583 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
584 && REG_P (SUBREG_REG (SET_DEST (x
)))
585 && !read_modify_subreg_p (SET_DEST (x
))))
588 return find_single_use_1 (dest
, &SET_SRC (x
));
592 return find_single_use_1 (dest
, &XEXP (x
, 0));
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
601 fmt
= GET_RTX_FORMAT (code
);
602 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
606 if (dest
== XEXP (x
, i
)
607 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
608 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
611 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
614 result
= this_result
;
615 else if (this_result
)
616 /* Duplicate usage. */
619 else if (fmt
[i
] == 'E')
623 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
625 if (XVECEXP (x
, i
, j
) == dest
627 && REG_P (XVECEXP (x
, i
, j
))
628 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
631 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
634 result
= this_result
;
635 else if (this_result
)
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
660 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
665 struct insn_link
*link
;
669 next
= NEXT_INSN (insn
);
671 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
674 result
= find_single_use_1 (dest
, &PATTERN (next
));
683 bb
= BLOCK_FOR_INSN (insn
);
684 for (next
= NEXT_INSN (insn
);
685 next
&& BLOCK_FOR_INSN (next
) == bb
;
686 next
= NEXT_INSN (next
))
687 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
689 FOR_EACH_LOG_LINK (link
, next
)
690 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
695 result
= find_single_use_1 (dest
, &PATTERN (next
));
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
712 do_SUBST (rtx
*into
, rtx newval
)
717 if (oldval
== newval
)
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
725 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
726 && CONST_INT_P (newval
))
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
730 gcc_assert (INTVAL (newval
)
731 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
739 gcc_assert (!(GET_CODE (oldval
) == SUBREG
740 && CONST_INT_P (SUBREG_REG (oldval
))));
741 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
742 && CONST_INT_P (XEXP (oldval
, 0))));
746 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
748 buf
= XNEW (struct undo
);
750 buf
->kind
= UNDO_RTX
;
752 buf
->old_contents
.r
= oldval
;
755 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
765 do_SUBST_INT (int *into
, int newval
)
770 if (oldval
== newval
)
774 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
776 buf
= XNEW (struct undo
);
778 buf
->kind
= UNDO_INT
;
780 buf
->old_contents
.i
= oldval
;
783 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
794 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
797 machine_mode oldval
= GET_MODE (*into
);
799 if (oldval
== newval
)
803 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
805 buf
= XNEW (struct undo
);
807 buf
->kind
= UNDO_MODE
;
809 buf
->old_contents
.m
= oldval
;
810 adjust_reg_mode (*into
, newval
);
812 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
823 struct insn_link
* oldval
= *into
;
825 if (oldval
== newval
)
829 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
831 buf
= XNEW (struct undo
);
833 buf
->kind
= UNDO_LINKS
;
835 buf
->old_contents
.l
= oldval
;
838 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
852 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
853 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
855 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
856 int new_i2_cost
, new_i3_cost
;
857 int old_cost
, new_cost
;
859 /* Lookup the original insn_costs. */
860 i2_cost
= INSN_COST (i2
);
861 i3_cost
= INSN_COST (i3
);
865 i1_cost
= INSN_COST (i1
);
868 i0_cost
= INSN_COST (i0
);
869 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
870 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
874 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
875 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
881 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
882 i1_cost
= i0_cost
= 0;
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
891 /* Calculate the replacement insn_costs. */
892 rtx tmp
= PATTERN (i3
);
893 PATTERN (i3
) = newpat
;
894 int tmpi
= INSN_CODE (i3
);
896 new_i3_cost
= insn_cost (i3
, optimize_this_for_speed_p
);
898 INSN_CODE (i3
) = tmpi
;
902 PATTERN (i2
) = newi2pat
;
903 tmpi
= INSN_CODE (i2
);
905 new_i2_cost
= insn_cost (i2
, optimize_this_for_speed_p
);
907 INSN_CODE (i2
) = tmpi
;
908 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
909 ? new_i2_cost
+ new_i3_cost
: 0;
913 new_cost
= new_i3_cost
;
917 if (undobuf
.other_insn
)
919 int old_other_cost
, new_other_cost
;
921 old_other_cost
= INSN_COST (undobuf
.other_insn
);
922 tmp
= PATTERN (undobuf
.other_insn
);
923 PATTERN (undobuf
.other_insn
) = newotherpat
;
924 tmpi
= INSN_CODE (undobuf
.other_insn
);
925 INSN_CODE (undobuf
.other_insn
) = -1;
926 new_other_cost
= insn_cost (undobuf
.other_insn
,
927 optimize_this_for_speed_p
);
928 PATTERN (undobuf
.other_insn
) = tmp
;
929 INSN_CODE (undobuf
.other_insn
) = tmpi
;
930 if (old_other_cost
> 0 && new_other_cost
> 0)
932 old_cost
+= old_other_cost
;
933 new_cost
+= new_other_cost
;
939 /* Disallow this combination if both new_cost and old_cost are greater than
940 zero, and new_cost is greater than old cost. */
941 int reject
= old_cost
> 0 && new_cost
> old_cost
;
945 fprintf (dump_file
, "%s combination of insns ",
946 reject
? "rejecting" : "allowing");
948 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
949 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
950 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
951 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
953 fprintf (dump_file
, "original costs ");
955 fprintf (dump_file
, "%d + ", i0_cost
);
956 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
957 fprintf (dump_file
, "%d + ", i1_cost
);
958 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
961 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
962 new_i2_cost
, new_i3_cost
, new_cost
);
964 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
970 /* Update the uid_insn_cost array with the replacement costs. */
971 INSN_COST (i2
) = new_i2_cost
;
972 INSN_COST (i3
) = new_i3_cost
;
984 /* Delete any insns that copy a register to itself. */
987 delete_noop_moves (void)
989 rtx_insn
*insn
, *next
;
992 FOR_EACH_BB_FN (bb
, cfun
)
994 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
996 next
= NEXT_INSN (insn
);
997 if (INSN_P (insn
) && noop_move_p (insn
))
1000 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
1002 delete_insn_and_edges (insn
);
1009 /* Return false if we do not want to (or cannot) combine DEF. */
1011 can_combine_def_p (df_ref def
)
1013 /* Do not consider if it is pre/post modification in MEM. */
1014 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1017 unsigned int regno
= DF_REF_REGNO (def
);
1019 /* Do not combine frame pointer adjustments. */
1020 if ((regno
== FRAME_POINTER_REGNUM
1021 && (!reload_completed
|| frame_pointer_needed
))
1022 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1023 && regno
== HARD_FRAME_POINTER_REGNUM
1024 && (!reload_completed
|| frame_pointer_needed
))
1025 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1026 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1032 /* Return false if we do not want to (or cannot) combine USE. */
1034 can_combine_use_p (df_ref use
)
1036 /* Do not consider the usage of the stack pointer by function call. */
1037 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1043 /* Fill in log links field for all insns. */
1046 create_log_links (void)
1049 rtx_insn
**next_use
;
1053 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1055 /* Pass through each block from the end, recording the uses of each
1056 register and establishing log links when def is encountered.
1057 Note that we do not clear next_use array in order to save time,
1058 so we have to test whether the use is in the same basic block as def.
1060 There are a few cases below when we do not consider the definition or
1061 usage -- these are taken from original flow.c did. Don't ask me why it is
1062 done this way; I don't know and if it works, I don't want to know. */
1064 FOR_EACH_BB_FN (bb
, cfun
)
1066 FOR_BB_INSNS_REVERSE (bb
, insn
)
1068 if (!NONDEBUG_INSN_P (insn
))
1071 /* Log links are created only once. */
1072 gcc_assert (!LOG_LINKS (insn
));
1074 FOR_EACH_INSN_DEF (def
, insn
)
1076 unsigned int regno
= DF_REF_REGNO (def
);
1079 if (!next_use
[regno
])
1082 if (!can_combine_def_p (def
))
1085 use_insn
= next_use
[regno
];
1086 next_use
[regno
] = NULL
;
1088 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1093 We don't build a LOG_LINK for hard registers contained
1094 in ASM_OPERANDs. If these registers get replaced,
1095 we might wind up changing the semantics of the insn,
1096 even if reload can make what appear to be valid
1097 assignments later. */
1098 if (regno
< FIRST_PSEUDO_REGISTER
1099 && asm_noperands (PATTERN (use_insn
)) >= 0)
1102 /* Don't add duplicate links between instructions. */
1103 struct insn_link
*links
;
1104 FOR_EACH_LOG_LINK (links
, use_insn
)
1105 if (insn
== links
->insn
&& regno
== links
->regno
)
1109 LOG_LINKS (use_insn
)
1110 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1113 FOR_EACH_INSN_USE (use
, insn
)
1114 if (can_combine_use_p (use
))
1115 next_use
[DF_REF_REGNO (use
)] = insn
;
1122 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1123 true if we found a LOG_LINK that proves that A feeds B. This only works
1124 if there are no instructions between A and B which could have a link
1125 depending on A, since in that case we would not record a link for B.
1126 We also check the implicit dependency created by a cc0 setter/user
1130 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1132 struct insn_link
*links
;
1133 FOR_EACH_LOG_LINK (links
, b
)
1134 if (links
->insn
== a
)
1136 if (HAVE_cc0
&& sets_cc0_p (a
))
1141 /* Main entry point for combiner. F is the first insn of the function.
1142 NREGS is the first unused pseudo-reg number.
1144 Return nonzero if the combiner has turned an indirect jump
1145 instruction into a direct jump. */
1147 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1149 rtx_insn
*insn
, *next
;
1151 struct insn_link
*links
, *nextlinks
;
1153 basic_block last_bb
;
1155 int new_direct_jump_p
= 0;
1157 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1158 first
= NEXT_INSN (first
);
1162 combine_attempts
= 0;
1165 combine_successes
= 0;
1167 rtl_hooks
= combine_rtl_hooks
;
1169 reg_stat
.safe_grow_cleared (nregs
);
1171 init_recog_no_volatile ();
1173 /* Allocate array for insn info. */
1174 max_uid_known
= get_max_uid ();
1175 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1176 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1177 gcc_obstack_init (&insn_link_obstack
);
1179 nonzero_bits_mode
= int_mode_for_size (HOST_BITS_PER_WIDE_INT
, 0).require ();
1181 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1182 problems when, for example, we have j <<= 1 in a loop. */
1184 nonzero_sign_valid
= 0;
1185 label_tick
= label_tick_ebb_start
= 1;
1187 /* Scan all SETs and see if we can deduce anything about what
1188 bits are known to be zero for some registers and how many copies
1189 of the sign bit are known to exist for those registers.
1191 Also set any known values so that we can use it while searching
1192 for what bits are known to be set. */
1194 setup_incoming_promotions (first
);
1195 /* Allow the entry block and the first block to fall into the same EBB.
1196 Conceptually the incoming promotions are assigned to the entry block. */
1197 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1199 create_log_links ();
1200 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1202 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1207 if (!single_pred_p (this_basic_block
)
1208 || single_pred (this_basic_block
) != last_bb
)
1209 label_tick_ebb_start
= label_tick
;
1210 last_bb
= this_basic_block
;
1212 FOR_BB_INSNS (this_basic_block
, insn
)
1213 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1217 subst_low_luid
= DF_INSN_LUID (insn
);
1220 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1222 record_dead_and_set_regs (insn
);
1225 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1226 if (REG_NOTE_KIND (links
) == REG_INC
)
1227 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1230 /* Record the current insn_cost of this instruction. */
1231 if (NONJUMP_INSN_P (insn
))
1232 INSN_COST (insn
) = insn_cost (insn
, optimize_this_for_speed_p
);
1235 fprintf (dump_file
, "insn_cost %d for ", INSN_COST (insn
));
1236 dump_insn_slim (dump_file
, insn
);
1241 nonzero_sign_valid
= 1;
1243 /* Now scan all the insns in forward order. */
1244 label_tick
= label_tick_ebb_start
= 1;
1246 setup_incoming_promotions (first
);
1247 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1248 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1250 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1252 rtx_insn
*last_combined_insn
= NULL
;
1254 /* Ignore instruction combination in basic blocks that are going to
1255 be removed as unreachable anyway. See PR82386. */
1256 if (EDGE_COUNT (this_basic_block
->preds
) == 0)
1259 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1264 if (!single_pred_p (this_basic_block
)
1265 || single_pred (this_basic_block
) != last_bb
)
1266 label_tick_ebb_start
= label_tick
;
1267 last_bb
= this_basic_block
;
1269 rtl_profile_for_bb (this_basic_block
);
1270 for (insn
= BB_HEAD (this_basic_block
);
1271 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1272 insn
= next
? next
: NEXT_INSN (insn
))
1275 if (!NONDEBUG_INSN_P (insn
))
1278 while (last_combined_insn
1279 && (!NONDEBUG_INSN_P (last_combined_insn
)
1280 || last_combined_insn
->deleted ()))
1281 last_combined_insn
= PREV_INSN (last_combined_insn
);
1282 if (last_combined_insn
== NULL_RTX
1283 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1284 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1285 last_combined_insn
= insn
;
1287 /* See if we know about function return values before this
1288 insn based upon SUBREG flags. */
1289 check_promoted_subreg (insn
, PATTERN (insn
));
1291 /* See if we can find hardregs and subreg of pseudos in
1292 narrower modes. This could help turning TRUNCATEs
1294 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1296 /* Try this insn with each insn it links back to. */
1298 FOR_EACH_LOG_LINK (links
, insn
)
1299 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1300 NULL
, &new_direct_jump_p
,
1301 last_combined_insn
)) != 0)
1303 statistics_counter_event (cfun
, "two-insn combine", 1);
1307 /* Try each sequence of three linked insns ending with this one. */
1309 if (max_combine
>= 3)
1310 FOR_EACH_LOG_LINK (links
, insn
)
1312 rtx_insn
*link
= links
->insn
;
1314 /* If the linked insn has been replaced by a note, then there
1315 is no point in pursuing this chain any further. */
1319 FOR_EACH_LOG_LINK (nextlinks
, link
)
1320 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1321 NULL
, &new_direct_jump_p
,
1322 last_combined_insn
)) != 0)
1324 statistics_counter_event (cfun
, "three-insn combine", 1);
1329 /* Try to combine a jump insn that uses CC0
1330 with a preceding insn that sets CC0, and maybe with its
1331 logical predecessor as well.
1332 This is how we make decrement-and-branch insns.
1333 We need this special code because data flow connections
1334 via CC0 do not get entered in LOG_LINKS. */
1338 && (prev
= prev_nonnote_insn (insn
)) != 0
1339 && NONJUMP_INSN_P (prev
)
1340 && sets_cc0_p (PATTERN (prev
)))
1342 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1344 last_combined_insn
)) != 0)
1347 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1348 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1349 NULL
, &new_direct_jump_p
,
1350 last_combined_insn
)) != 0)
1354 /* Do the same for an insn that explicitly references CC0. */
1355 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1356 && (prev
= prev_nonnote_insn (insn
)) != 0
1357 && NONJUMP_INSN_P (prev
)
1358 && sets_cc0_p (PATTERN (prev
))
1359 && GET_CODE (PATTERN (insn
)) == SET
1360 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1362 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1364 last_combined_insn
)) != 0)
1367 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1368 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1369 NULL
, &new_direct_jump_p
,
1370 last_combined_insn
)) != 0)
1374 /* Finally, see if any of the insns that this insn links to
1375 explicitly references CC0. If so, try this insn, that insn,
1376 and its predecessor if it sets CC0. */
1379 FOR_EACH_LOG_LINK (links
, insn
)
1380 if (NONJUMP_INSN_P (links
->insn
)
1381 && GET_CODE (PATTERN (links
->insn
)) == SET
1382 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1383 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1384 && NONJUMP_INSN_P (prev
)
1385 && sets_cc0_p (PATTERN (prev
))
1386 && (next
= try_combine (insn
, links
->insn
,
1387 prev
, NULL
, &new_direct_jump_p
,
1388 last_combined_insn
)) != 0)
1392 /* Try combining an insn with two different insns whose results it
1394 if (max_combine
>= 3)
1395 FOR_EACH_LOG_LINK (links
, insn
)
1396 for (nextlinks
= links
->next
; nextlinks
;
1397 nextlinks
= nextlinks
->next
)
1398 if ((next
= try_combine (insn
, links
->insn
,
1399 nextlinks
->insn
, NULL
,
1401 last_combined_insn
)) != 0)
1404 statistics_counter_event (cfun
, "three-insn combine", 1);
1408 /* Try four-instruction combinations. */
1409 if (max_combine
>= 4)
1410 FOR_EACH_LOG_LINK (links
, insn
)
1412 struct insn_link
*next1
;
1413 rtx_insn
*link
= links
->insn
;
1415 /* If the linked insn has been replaced by a note, then there
1416 is no point in pursuing this chain any further. */
1420 FOR_EACH_LOG_LINK (next1
, link
)
1422 rtx_insn
*link1
= next1
->insn
;
1425 /* I0 -> I1 -> I2 -> I3. */
1426 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1427 if ((next
= try_combine (insn
, link
, link1
,
1430 last_combined_insn
)) != 0)
1432 statistics_counter_event (cfun
, "four-insn combine", 1);
1435 /* I0, I1 -> I2, I2 -> I3. */
1436 for (nextlinks
= next1
->next
; nextlinks
;
1437 nextlinks
= nextlinks
->next
)
1438 if ((next
= try_combine (insn
, link
, link1
,
1441 last_combined_insn
)) != 0)
1443 statistics_counter_event (cfun
, "four-insn combine", 1);
1448 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1450 rtx_insn
*link1
= next1
->insn
;
1453 /* I0 -> I2; I1, I2 -> I3. */
1454 FOR_EACH_LOG_LINK (nextlinks
, link
)
1455 if ((next
= try_combine (insn
, link
, link1
,
1458 last_combined_insn
)) != 0)
1460 statistics_counter_event (cfun
, "four-insn combine", 1);
1463 /* I0 -> I1; I1, I2 -> I3. */
1464 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1465 if ((next
= try_combine (insn
, link
, link1
,
1468 last_combined_insn
)) != 0)
1470 statistics_counter_event (cfun
, "four-insn combine", 1);
1476 /* Try this insn with each REG_EQUAL note it links back to. */
1477 FOR_EACH_LOG_LINK (links
, insn
)
1480 rtx_insn
*temp
= links
->insn
;
1481 if ((set
= single_set (temp
)) != 0
1482 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1483 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1484 /* Avoid using a register that may already been marked
1485 dead by an earlier instruction. */
1486 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1487 && (GET_MODE (note
) == VOIDmode
1488 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1489 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1490 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1491 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1492 == GET_MODE (note
))))))
1494 /* Temporarily replace the set's source with the
1495 contents of the REG_EQUAL note. The insn will
1496 be deleted or recognized by try_combine. */
1497 rtx orig_src
= SET_SRC (set
);
1498 rtx orig_dest
= SET_DEST (set
);
1499 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1500 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1501 SET_SRC (set
) = note
;
1503 i2mod_old_rhs
= copy_rtx (orig_src
);
1504 i2mod_new_rhs
= copy_rtx (note
);
1505 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1507 last_combined_insn
);
1511 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1514 SET_SRC (set
) = orig_src
;
1515 SET_DEST (set
) = orig_dest
;
1520 record_dead_and_set_regs (insn
);
1527 default_rtl_profile ();
1529 new_direct_jump_p
|= purge_all_dead_edges ();
1530 delete_noop_moves ();
1533 obstack_free (&insn_link_obstack
, NULL
);
1534 free (uid_log_links
);
1535 free (uid_insn_cost
);
1536 reg_stat
.release ();
1539 struct undo
*undo
, *next
;
1540 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1548 total_attempts
+= combine_attempts
;
1549 total_merges
+= combine_merges
;
1550 total_extras
+= combine_extras
;
1551 total_successes
+= combine_successes
;
1553 nonzero_sign_valid
= 0;
1554 rtl_hooks
= general_rtl_hooks
;
1556 /* Make recognizer allow volatile MEMs again. */
1559 return new_direct_jump_p
;
1562 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1565 init_reg_last (void)
1570 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1571 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1574 /* Set up any promoted values for incoming argument registers. */
1577 setup_incoming_promotions (rtx_insn
*first
)
1580 bool strictly_local
= false;
1582 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1583 arg
= DECL_CHAIN (arg
))
1585 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1587 machine_mode mode1
, mode2
, mode3
, mode4
;
1589 /* Only continue if the incoming argument is in a register. */
1593 /* Determine, if possible, whether all call sites of the current
1594 function lie within the current compilation unit. (This does
1595 take into account the exporting of a function via taking its
1596 address, and so forth.) */
1597 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1599 /* The mode and signedness of the argument before any promotions happen
1600 (equal to the mode of the pseudo holding it at that stage). */
1601 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1602 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1604 /* The mode and signedness of the argument after any source language and
1605 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1606 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1607 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1609 /* The mode and signedness of the argument as it is actually passed,
1610 see assign_parm_setup_reg in function.c. */
1611 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1612 TREE_TYPE (cfun
->decl
), 0);
1614 /* The mode of the register in which the argument is being passed. */
1615 mode4
= GET_MODE (reg
);
1617 /* Eliminate sign extensions in the callee when:
1618 (a) A mode promotion has occurred; */
1621 /* (b) The mode of the register is the same as the mode of
1622 the argument as it is passed; */
1625 /* (c) There's no language level extension; */
1628 /* (c.1) All callers are from the current compilation unit. If that's
1629 the case we don't have to rely on an ABI, we only have to know
1630 what we're generating right now, and we know that we will do the
1631 mode1 to mode2 promotion with the given sign. */
1632 else if (!strictly_local
)
1634 /* (c.2) The combination of the two promotions is useful. This is
1635 true when the signs match, or if the first promotion is unsigned.
1636 In the later case, (sign_extend (zero_extend x)) is the same as
1637 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1643 /* Record that the value was promoted from mode1 to mode3,
1644 so that any sign extension at the head of the current
1645 function may be eliminated. */
1646 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1647 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1648 record_value_for_reg (reg
, first
, x
);
1652 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1653 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1654 because some machines (maybe most) will actually do the sign-extension and
1655 this is the conservative approach.
1657 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1661 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1663 scalar_int_mode int_mode
;
1664 if (CONST_INT_P (src
)
1665 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1666 && GET_MODE_PRECISION (int_mode
) < prec
1668 && val_signbit_known_set_p (int_mode
, INTVAL (src
)))
1669 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (int_mode
));
1674 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1678 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1681 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1682 unsigned HOST_WIDE_INT bits
= 0;
1683 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1684 unsigned int num
= 0;
1687 reg_equal
= XEXP (reg_equal_note
, 0);
1689 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1691 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1693 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1696 /* Don't call nonzero_bits if it cannot change anything. */
1697 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1699 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1700 if (reg_equal
&& bits
)
1701 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1702 rsp
->nonzero_bits
|= bits
;
1705 /* Don't call num_sign_bit_copies if it cannot change anything. */
1706 if (rsp
->sign_bit_copies
!= 1)
1708 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1709 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1711 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1712 if (num
== 0 || numeq
> num
)
1715 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1716 rsp
->sign_bit_copies
= num
;
1720 /* Called via note_stores. If X is a pseudo that is narrower than
1721 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1723 If we are setting only a portion of X and we can't figure out what
1724 portion, assume all bits will be used since we don't know what will
1727 Similarly, set how many bits of X are known to be copies of the sign bit
1728 at all locations in the function. This is the smallest number implied
1732 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1734 rtx_insn
*insn
= (rtx_insn
*) data
;
1735 scalar_int_mode mode
;
1738 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1739 /* If this register is undefined at the start of the file, we can't
1740 say what its contents were. */
1741 && ! REGNO_REG_SET_P
1742 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1743 && is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
1744 && HWI_COMPUTABLE_MODE_P (mode
))
1746 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1748 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1750 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1751 rsp
->sign_bit_copies
= 1;
1755 /* If this register is being initialized using itself, and the
1756 register is uninitialized in this basic block, and there are
1757 no LOG_LINKS which set the register, then part of the
1758 register is uninitialized. In that case we can't assume
1759 anything about the number of nonzero bits.
1761 ??? We could do better if we checked this in
1762 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1763 could avoid making assumptions about the insn which initially
1764 sets the register, while still using the information in other
1765 insns. We would have to be careful to check every insn
1766 involved in the combination. */
1769 && reg_referenced_p (x
, PATTERN (insn
))
1770 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1773 struct insn_link
*link
;
1775 FOR_EACH_LOG_LINK (link
, insn
)
1776 if (dead_or_set_p (link
->insn
, x
))
1780 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1781 rsp
->sign_bit_copies
= 1;
1786 /* If this is a complex assignment, see if we can convert it into a
1787 simple assignment. */
1788 set
= expand_field_assignment (set
);
1790 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1791 set what we know about X. */
1793 if (SET_DEST (set
) == x
1794 || (paradoxical_subreg_p (SET_DEST (set
))
1795 && SUBREG_REG (SET_DEST (set
)) == x
))
1796 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1799 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1800 rsp
->sign_bit_copies
= 1;
1805 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1806 optionally insns that were previously combined into I3 or that will be
1807 combined into the merger of INSN and I3. The order is PRED, PRED2,
1808 INSN, SUCC, SUCC2, I3.
1810 Return 0 if the combination is not allowed for any reason.
1812 If the combination is allowed, *PDEST will be set to the single
1813 destination of INSN and *PSRC to the single source, and this function
1817 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1818 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1819 rtx
*pdest
, rtx
*psrc
)
1826 bool all_adjacent
= true;
1827 int (*is_volatile_p
) (const_rtx
);
1833 if (next_active_insn (succ2
) != i3
)
1834 all_adjacent
= false;
1835 if (next_active_insn (succ
) != succ2
)
1836 all_adjacent
= false;
1838 else if (next_active_insn (succ
) != i3
)
1839 all_adjacent
= false;
1840 if (next_active_insn (insn
) != succ
)
1841 all_adjacent
= false;
1843 else if (next_active_insn (insn
) != i3
)
1844 all_adjacent
= false;
1846 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1847 or a PARALLEL consisting of such a SET and CLOBBERs.
1849 If INSN has CLOBBER parallel parts, ignore them for our processing.
1850 By definition, these happen during the execution of the insn. When it
1851 is merged with another insn, all bets are off. If they are, in fact,
1852 needed and aren't also supplied in I3, they may be added by
1853 recog_for_combine. Otherwise, it won't match.
1855 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1858 Get the source and destination of INSN. If more than one, can't
1861 if (GET_CODE (PATTERN (insn
)) == SET
)
1862 set
= PATTERN (insn
);
1863 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1864 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1866 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1868 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1870 switch (GET_CODE (elt
))
1872 /* This is important to combine floating point insns
1873 for the SH4 port. */
1875 /* Combining an isolated USE doesn't make sense.
1876 We depend here on combinable_i3pat to reject them. */
1877 /* The code below this loop only verifies that the inputs of
1878 the SET in INSN do not change. We call reg_set_between_p
1879 to verify that the REG in the USE does not change between
1881 If the USE in INSN was for a pseudo register, the matching
1882 insn pattern will likely match any register; combining this
1883 with any other USE would only be safe if we knew that the
1884 used registers have identical values, or if there was
1885 something to tell them apart, e.g. different modes. For
1886 now, we forgo such complicated tests and simply disallow
1887 combining of USES of pseudo registers with any other USE. */
1888 if (REG_P (XEXP (elt
, 0))
1889 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1891 rtx i3pat
= PATTERN (i3
);
1892 int i
= XVECLEN (i3pat
, 0) - 1;
1893 unsigned int regno
= REGNO (XEXP (elt
, 0));
1897 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1899 if (GET_CODE (i3elt
) == USE
1900 && REG_P (XEXP (i3elt
, 0))
1901 && (REGNO (XEXP (i3elt
, 0)) == regno
1902 ? reg_set_between_p (XEXP (elt
, 0),
1903 PREV_INSN (insn
), i3
)
1904 : regno
>= FIRST_PSEUDO_REGISTER
))
1911 /* We can ignore CLOBBERs. */
1916 /* Ignore SETs whose result isn't used but not those that
1917 have side-effects. */
1918 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1919 && insn_nothrow_p (insn
)
1920 && !side_effects_p (elt
))
1923 /* If we have already found a SET, this is a second one and
1924 so we cannot combine with this insn. */
1932 /* Anything else means we can't combine. */
1938 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1939 so don't do anything with it. */
1940 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1949 /* The simplification in expand_field_assignment may call back to
1950 get_last_value, so set safe guard here. */
1951 subst_low_luid
= DF_INSN_LUID (insn
);
1953 set
= expand_field_assignment (set
);
1954 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1956 /* Do not eliminate user-specified register if it is in an
1957 asm input because we may break the register asm usage defined
1958 in GCC manual if allow to do so.
1959 Be aware that this may cover more cases than we expect but this
1960 should be harmless. */
1961 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1962 && extract_asm_operands (PATTERN (i3
)))
1965 /* Don't eliminate a store in the stack pointer. */
1966 if (dest
== stack_pointer_rtx
1967 /* Don't combine with an insn that sets a register to itself if it has
1968 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1969 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1970 /* Can't merge an ASM_OPERANDS. */
1971 || GET_CODE (src
) == ASM_OPERANDS
1972 /* Can't merge a function call. */
1973 || GET_CODE (src
) == CALL
1974 /* Don't eliminate a function call argument. */
1976 && (find_reg_fusage (i3
, USE
, dest
)
1978 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1979 && global_regs
[REGNO (dest
)])))
1980 /* Don't substitute into an incremented register. */
1981 || FIND_REG_INC_NOTE (i3
, dest
)
1982 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1983 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1984 /* Don't substitute into a non-local goto, this confuses CFG. */
1985 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1986 /* Make sure that DEST is not used after INSN but before SUCC, or
1987 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1990 && (reg_used_between_p (dest
, succ2
, i3
)
1991 || reg_used_between_p (dest
, succ
, succ2
)))
1992 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))
1994 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1995 that case SUCC is not in the insn stream, so use SUCC2
1996 instead for this test. */
1997 && reg_used_between_p (dest
, insn
,
1999 && INSN_UID (succ
) == INSN_UID (succ2
)
2001 /* Make sure that the value that is to be substituted for the register
2002 does not use any registers whose values alter in between. However,
2003 If the insns are adjacent, a use can't cross a set even though we
2004 think it might (this can happen for a sequence of insns each setting
2005 the same destination; last_set of that register might point to
2006 a NOTE). If INSN has a REG_EQUIV note, the register is always
2007 equivalent to the memory so the substitution is valid even if there
2008 are intervening stores. Also, don't move a volatile asm or
2009 UNSPEC_VOLATILE across any other insns. */
2012 || ! find_reg_note (insn
, REG_EQUIV
, src
))
2013 && modified_between_p (src
, insn
, i3
))
2014 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
2015 || GET_CODE (src
) == UNSPEC_VOLATILE
))
2016 /* Don't combine across a CALL_INSN, because that would possibly
2017 change whether the life span of some REGs crosses calls or not,
2018 and it is a pain to update that information.
2019 Exception: if source is a constant, moving it later can't hurt.
2020 Accept that as a special case. */
2021 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
2024 /* DEST must either be a REG or CC0. */
2027 /* If register alignment is being enforced for multi-word items in all
2028 cases except for parameters, it is possible to have a register copy
2029 insn referencing a hard register that is not allowed to contain the
2030 mode being copied and which would not be valid as an operand of most
2031 insns. Eliminate this problem by not combining with such an insn.
2033 Also, on some machines we don't want to extend the life of a hard
2037 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
2038 && !targetm
.hard_regno_mode_ok (REGNO (dest
), GET_MODE (dest
)))
2039 /* Don't extend the life of a hard register unless it is
2040 user variable (if we have few registers) or it can't
2041 fit into the desired register (meaning something special
2043 Also avoid substituting a return register into I3, because
2044 reload can't handle a conflict with constraints of other
2046 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2047 && !targetm
.hard_regno_mode_ok (REGNO (src
),
2051 else if (GET_CODE (dest
) != CC0
)
2055 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2056 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2057 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2059 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2061 /* If the clobber represents an earlyclobber operand, we must not
2062 substitute an expression containing the clobbered register.
2063 As we do not analyze the constraint strings here, we have to
2064 make the conservative assumption. However, if the register is
2065 a fixed hard reg, the clobber cannot represent any operand;
2066 we leave it up to the machine description to either accept or
2067 reject use-and-clobber patterns. */
2069 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2070 || !fixed_regs
[REGNO (reg
)])
2071 if (reg_overlap_mentioned_p (reg
, src
))
2075 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2076 or not), reject, unless nothing volatile comes between it and I3 */
2078 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2080 /* Make sure neither succ nor succ2 contains a volatile reference. */
2081 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2083 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2085 /* We'll check insns between INSN and I3 below. */
2088 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2089 to be an explicit register variable, and was chosen for a reason. */
2091 if (GET_CODE (src
) == ASM_OPERANDS
2092 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2095 /* If INSN contains volatile references (specifically volatile MEMs),
2096 we cannot combine across any other volatile references.
2097 Even if INSN doesn't contain volatile references, any intervening
2098 volatile insn might affect machine state. */
2100 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2104 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2105 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2108 /* If INSN contains an autoincrement or autodecrement, make sure that
2109 register is not used between there and I3, and not already used in
2110 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2111 Also insist that I3 not be a jump; if it were one
2112 and the incremented register were spilled, we would lose. */
2115 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2116 if (REG_NOTE_KIND (link
) == REG_INC
2118 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2119 || (pred
!= NULL_RTX
2120 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2121 || (pred2
!= NULL_RTX
2122 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2123 || (succ
!= NULL_RTX
2124 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2125 || (succ2
!= NULL_RTX
2126 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2127 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2130 /* Don't combine an insn that follows a CC0-setting insn.
2131 An insn that uses CC0 must not be separated from the one that sets it.
2132 We do, however, allow I2 to follow a CC0-setting insn if that insn
2133 is passed as I1; in that case it will be deleted also.
2134 We also allow combining in this case if all the insns are adjacent
2135 because that would leave the two CC0 insns adjacent as well.
2136 It would be more logical to test whether CC0 occurs inside I1 or I2,
2137 but that would be much slower, and this ought to be equivalent. */
2141 p
= prev_nonnote_insn (insn
);
2142 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2147 /* If we get here, we have passed all the tests and the combination is
2156 /* LOC is the location within I3 that contains its pattern or the component
2157 of a PARALLEL of the pattern. We validate that it is valid for combining.
2159 One problem is if I3 modifies its output, as opposed to replacing it
2160 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2161 doing so would produce an insn that is not equivalent to the original insns.
2165 (set (reg:DI 101) (reg:DI 100))
2166 (set (subreg:SI (reg:DI 101) 0) <foo>)
2168 This is NOT equivalent to:
2170 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2171 (set (reg:DI 101) (reg:DI 100))])
2173 Not only does this modify 100 (in which case it might still be valid
2174 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2176 We can also run into a problem if I2 sets a register that I1
2177 uses and I1 gets directly substituted into I3 (not via I2). In that
2178 case, we would be getting the wrong value of I2DEST into I3, so we
2179 must reject the combination. This case occurs when I2 and I1 both
2180 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2181 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2182 of a SET must prevent combination from occurring. The same situation
2183 can occur for I0, in which case I0_NOT_IN_SRC is set.
2185 Before doing the above check, we first try to expand a field assignment
2186 into a set of logical operations.
2188 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2189 we place a register that is both set and used within I3. If more than one
2190 such register is detected, we fail.
2192 Return 1 if the combination is valid, zero otherwise. */
2195 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2196 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2200 if (GET_CODE (x
) == SET
)
2203 rtx dest
= SET_DEST (set
);
2204 rtx src
= SET_SRC (set
);
2205 rtx inner_dest
= dest
;
2208 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2209 || GET_CODE (inner_dest
) == SUBREG
2210 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2211 inner_dest
= XEXP (inner_dest
, 0);
2213 /* Check for the case where I3 modifies its output, as discussed
2214 above. We don't want to prevent pseudos from being combined
2215 into the address of a MEM, so only prevent the combination if
2216 i1 or i2 set the same MEM. */
2217 if ((inner_dest
!= dest
&&
2218 (!MEM_P (inner_dest
)
2219 || rtx_equal_p (i2dest
, inner_dest
)
2220 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2221 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2222 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2223 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2224 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2226 /* This is the same test done in can_combine_p except we can't test
2227 all_adjacent; we don't have to, since this instruction will stay
2228 in place, thus we are not considering increasing the lifetime of
2231 Also, if this insn sets a function argument, combining it with
2232 something that might need a spill could clobber a previous
2233 function argument; the all_adjacent test in can_combine_p also
2234 checks this; here, we do a more specific test for this case. */
2236 || (REG_P (inner_dest
)
2237 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2238 && !targetm
.hard_regno_mode_ok (REGNO (inner_dest
),
2239 GET_MODE (inner_dest
)))
2240 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2241 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2244 /* If DEST is used in I3, it is being killed in this insn, so
2245 record that for later. We have to consider paradoxical
2246 subregs here, since they kill the whole register, but we
2247 ignore partial subregs, STRICT_LOW_PART, etc.
2248 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2249 STACK_POINTER_REGNUM, since these are always considered to be
2250 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2252 if (GET_CODE (subdest
) == SUBREG
&& !partial_subreg_p (subdest
))
2253 subdest
= SUBREG_REG (subdest
);
2256 && reg_referenced_p (subdest
, PATTERN (i3
))
2257 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2258 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2259 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2260 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2261 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2262 || ! fixed_regs
[REGNO (subdest
)]))
2263 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2265 if (*pi3dest_killed
)
2268 *pi3dest_killed
= subdest
;
2272 else if (GET_CODE (x
) == PARALLEL
)
2276 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2277 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2278 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2285 /* Return 1 if X is an arithmetic expression that contains a multiplication
2286 and division. We don't count multiplications by powers of two here. */
2289 contains_muldiv (rtx x
)
2291 switch (GET_CODE (x
))
2293 case MOD
: case DIV
: case UMOD
: case UDIV
:
2297 return ! (CONST_INT_P (XEXP (x
, 1))
2298 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2301 return contains_muldiv (XEXP (x
, 0))
2302 || contains_muldiv (XEXP (x
, 1));
2305 return contains_muldiv (XEXP (x
, 0));
2311 /* Determine whether INSN can be used in a combination. Return nonzero if
2312 not. This is used in try_combine to detect early some cases where we
2313 can't perform combinations. */
2316 cant_combine_insn_p (rtx_insn
*insn
)
2321 /* If this isn't really an insn, we can't do anything.
2322 This can occur when flow deletes an insn that it has merged into an
2323 auto-increment address. */
2324 if (!NONDEBUG_INSN_P (insn
))
2327 /* Never combine loads and stores involving hard regs that are likely
2328 to be spilled. The register allocator can usually handle such
2329 reg-reg moves by tying. If we allow the combiner to make
2330 substitutions of likely-spilled regs, reload might die.
2331 As an exception, we allow combinations involving fixed regs; these are
2332 not available to the register allocator so there's no risk involved. */
2334 set
= single_set (insn
);
2337 src
= SET_SRC (set
);
2338 dest
= SET_DEST (set
);
2339 if (GET_CODE (src
) == SUBREG
)
2340 src
= SUBREG_REG (src
);
2341 if (GET_CODE (dest
) == SUBREG
)
2342 dest
= SUBREG_REG (dest
);
2343 if (REG_P (src
) && REG_P (dest
)
2344 && ((HARD_REGISTER_P (src
)
2345 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2346 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2347 || (HARD_REGISTER_P (dest
)
2348 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2349 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2355 struct likely_spilled_retval_info
2357 unsigned regno
, nregs
;
2361 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2362 hard registers that are known to be written to / clobbered in full. */
2364 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2366 struct likely_spilled_retval_info
*const info
=
2367 (struct likely_spilled_retval_info
*) data
;
2368 unsigned regno
, nregs
;
2371 if (!REG_P (XEXP (set
, 0)))
2374 if (regno
>= info
->regno
+ info
->nregs
)
2376 nregs
= REG_NREGS (x
);
2377 if (regno
+ nregs
<= info
->regno
)
2379 new_mask
= (2U << (nregs
- 1)) - 1;
2380 if (regno
< info
->regno
)
2381 new_mask
>>= info
->regno
- regno
;
2383 new_mask
<<= regno
- info
->regno
;
2384 info
->mask
&= ~new_mask
;
2387 /* Return nonzero iff part of the return value is live during INSN, and
2388 it is likely spilled. This can happen when more than one insn is needed
2389 to copy the return value, e.g. when we consider to combine into the
2390 second copy insn for a complex value. */
2393 likely_spilled_retval_p (rtx_insn
*insn
)
2395 rtx_insn
*use
= BB_END (this_basic_block
);
2398 unsigned regno
, nregs
;
2399 /* We assume here that no machine mode needs more than
2400 32 hard registers when the value overlaps with a register
2401 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2403 struct likely_spilled_retval_info info
;
2405 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2407 reg
= XEXP (PATTERN (use
), 0);
2408 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2410 regno
= REGNO (reg
);
2411 nregs
= REG_NREGS (reg
);
2414 mask
= (2U << (nregs
- 1)) - 1;
2416 /* Disregard parts of the return value that are set later. */
2420 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2422 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2425 /* Check if any of the (probably) live return value registers is
2430 if ((mask
& 1 << nregs
)
2431 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2437 /* Adjust INSN after we made a change to its destination.
2439 Changing the destination can invalidate notes that say something about
2440 the results of the insn and a LOG_LINK pointing to the insn. */
2443 adjust_for_new_dest (rtx_insn
*insn
)
2445 /* For notes, be conservative and simply remove them. */
2446 remove_reg_equal_equiv_notes (insn
);
2448 /* The new insn will have a destination that was previously the destination
2449 of an insn just above it. Call distribute_links to make a LOG_LINK from
2450 the next use of that destination. */
2452 rtx set
= single_set (insn
);
2455 rtx reg
= SET_DEST (set
);
2457 while (GET_CODE (reg
) == ZERO_EXTRACT
2458 || GET_CODE (reg
) == STRICT_LOW_PART
2459 || GET_CODE (reg
) == SUBREG
)
2460 reg
= XEXP (reg
, 0);
2461 gcc_assert (REG_P (reg
));
2463 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2465 df_insn_rescan (insn
);
2468 /* Return TRUE if combine can reuse reg X in mode MODE.
2469 ADDED_SETS is nonzero if the original set is still required. */
2471 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2478 /* Don't change between modes with different underlying register sizes,
2479 since this could lead to invalid subregs. */
2480 if (REGMODE_NATURAL_SIZE (mode
)
2481 != REGMODE_NATURAL_SIZE (GET_MODE (x
)))
2485 /* Allow hard registers if the new mode is legal, and occupies no more
2486 registers than the old mode. */
2487 if (regno
< FIRST_PSEUDO_REGISTER
)
2488 return (targetm
.hard_regno_mode_ok (regno
, mode
)
2489 && REG_NREGS (x
) >= hard_regno_nregs (regno
, mode
));
2491 /* Or a pseudo that is only used once. */
2492 return (regno
< reg_n_sets_max
2493 && REG_N_SETS (regno
) == 1
2495 && !REG_USERVAR_P (x
));
2499 /* Check whether X, the destination of a set, refers to part of
2500 the register specified by REG. */
2503 reg_subword_p (rtx x
, rtx reg
)
2505 /* Check that reg is an integer mode register. */
2506 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2509 if (GET_CODE (x
) == STRICT_LOW_PART
2510 || GET_CODE (x
) == ZERO_EXTRACT
)
2513 return GET_CODE (x
) == SUBREG
2514 && SUBREG_REG (x
) == reg
2515 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2518 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2519 Note that the INSN should be deleted *after* removing dead edges, so
2520 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2521 but not for a (set (pc) (label_ref FOO)). */
2524 update_cfg_for_uncondjump (rtx_insn
*insn
)
2526 basic_block bb
= BLOCK_FOR_INSN (insn
);
2527 gcc_assert (BB_END (bb
) == insn
);
2529 purge_dead_edges (bb
);
2532 if (EDGE_COUNT (bb
->succs
) == 1)
2536 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2538 /* Remove barriers from the footer if there are any. */
2539 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2540 if (BARRIER_P (insn
))
2542 if (PREV_INSN (insn
))
2543 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2545 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2546 if (NEXT_INSN (insn
))
2547 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2549 else if (LABEL_P (insn
))
2554 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2555 by an arbitrary number of CLOBBERs. */
2557 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2559 if (GET_CODE (pat
) != PARALLEL
)
2562 int len
= XVECLEN (pat
, 0);
2567 for (i
= 0; i
< n
; i
++)
2568 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2569 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2571 for ( ; i
< len
; i
++)
2572 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
2573 || XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2579 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2580 CLOBBERs), can be split into individual SETs in that order, without
2581 changing semantics. */
2583 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2585 if (!insn_nothrow_p (insn
))
2588 rtx pat
= PATTERN (insn
);
2591 for (i
= 0; i
< n
; i
++)
2593 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2596 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2598 for (j
= i
+ 1; j
< n
; j
++)
2599 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2606 /* Try to combine the insns I0, I1 and I2 into I3.
2607 Here I0, I1 and I2 appear earlier than I3.
2608 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2611 If we are combining more than two insns and the resulting insn is not
2612 recognized, try splitting it into two insns. If that happens, I2 and I3
2613 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2614 Otherwise, I0, I1 and I2 are pseudo-deleted.
2616 Return 0 if the combination does not work. Then nothing is changed.
2617 If we did the combination, return the insn at which combine should
2620 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2621 new direct jump instruction.
2623 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2624 been I3 passed to an earlier try_combine within the same basic
2628 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2629 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2631 /* New patterns for I3 and I2, respectively. */
2632 rtx newpat
, newi2pat
= 0;
2633 rtvec newpat_vec_with_clobbers
= 0;
2634 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2635 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2637 int added_sets_0
, added_sets_1
, added_sets_2
;
2638 /* Total number of SETs to put into I3. */
2640 /* Nonzero if I2's or I1's body now appears in I3. */
2641 int i2_is_used
= 0, i1_is_used
= 0;
2642 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2643 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2644 /* Contains I3 if the destination of I3 is used in its source, which means
2645 that the old life of I3 is being killed. If that usage is placed into
2646 I2 and not in I3, a REG_DEAD note must be made. */
2647 rtx i3dest_killed
= 0;
2648 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2649 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2650 /* Copy of SET_SRC of I1 and I0, if needed. */
2651 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2652 /* Set if I2DEST was reused as a scratch register. */
2653 bool i2scratch
= false;
2654 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2655 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2656 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2657 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2658 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2659 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2660 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2661 /* Notes that must be added to REG_NOTES in I3 and I2. */
2662 rtx new_i3_notes
, new_i2_notes
;
2663 /* Notes that we substituted I3 into I2 instead of the normal case. */
2664 int i3_subst_into_i2
= 0;
2665 /* Notes that I1, I2 or I3 is a MULT operation. */
2668 int changed_i3_dest
= 0;
2671 rtx_insn
*temp_insn
;
2673 struct insn_link
*link
;
2675 rtx new_other_notes
;
2677 scalar_int_mode dest_mode
, temp_mode
;
2679 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2681 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2684 /* Only try four-insn combinations when there's high likelihood of
2685 success. Look for simple insns, such as loads of constants or
2686 binary operations involving a constant. */
2694 if (!flag_expensive_optimizations
)
2697 for (i
= 0; i
< 4; i
++)
2699 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2700 rtx set
= single_set (insn
);
2704 src
= SET_SRC (set
);
2705 if (CONSTANT_P (src
))
2710 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2712 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2713 || GET_CODE (src
) == LSHIFTRT
)
2717 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2718 are likely manipulating its value. Ideally we'll be able to combine
2719 all four insns into a bitfield insertion of some kind.
2721 Note the source in I0 might be inside a sign/zero extension and the
2722 memory modes in I0 and I3 might be different. So extract the address
2723 from the destination of I3 and search for it in the source of I0.
2725 In the event that there's a match but the source/dest do not actually
2726 refer to the same memory, the worst that happens is we try some
2727 combinations that we wouldn't have otherwise. */
2728 if ((set0
= single_set (i0
))
2729 /* Ensure the source of SET0 is a MEM, possibly buried inside
2731 && (GET_CODE (SET_SRC (set0
)) == MEM
2732 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2733 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2734 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2735 && (set3
= single_set (i3
))
2736 /* Ensure the destination of SET3 is a MEM. */
2737 && GET_CODE (SET_DEST (set3
)) == MEM
2738 /* Would it be better to extract the base address for the MEM
2739 in SET3 and look for that? I don't have cases where it matters
2740 but I could envision such cases. */
2741 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2744 if (ngood
< 2 && nshift
< 2)
2748 /* Exit early if one of the insns involved can't be used for
2751 || (i1
&& CALL_P (i1
))
2752 || (i0
&& CALL_P (i0
))
2753 || cant_combine_insn_p (i3
)
2754 || cant_combine_insn_p (i2
)
2755 || (i1
&& cant_combine_insn_p (i1
))
2756 || (i0
&& cant_combine_insn_p (i0
))
2757 || likely_spilled_retval_p (i3
))
2761 undobuf
.other_insn
= 0;
2763 /* Reset the hard register usage information. */
2764 CLEAR_HARD_REG_SET (newpat_used_regs
);
2766 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2769 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2770 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2772 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2773 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2775 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2776 INSN_UID (i2
), INSN_UID (i3
));
2779 dump_insn_slim (dump_file
, i0
);
2781 dump_insn_slim (dump_file
, i1
);
2782 dump_insn_slim (dump_file
, i2
);
2783 dump_insn_slim (dump_file
, i3
);
2786 /* If multiple insns feed into one of I2 or I3, they can be in any
2787 order. To simplify the code below, reorder them in sequence. */
2788 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2790 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2792 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2795 added_links_insn
= 0;
2796 added_notes_insn
= 0;
2798 /* First check for one important special case that the code below will
2799 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2800 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2801 we may be able to replace that destination with the destination of I3.
2802 This occurs in the common code where we compute both a quotient and
2803 remainder into a structure, in which case we want to do the computation
2804 directly into the structure to avoid register-register copies.
2806 Note that this case handles both multiple sets in I2 and also cases
2807 where I2 has a number of CLOBBERs inside the PARALLEL.
2809 We make very conservative checks below and only try to handle the
2810 most common cases of this. For example, we only handle the case
2811 where I2 and I3 are adjacent to avoid making difficult register
2814 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2815 && REG_P (SET_SRC (PATTERN (i3
)))
2816 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2817 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2818 && GET_CODE (PATTERN (i2
)) == PARALLEL
2819 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2820 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2821 below would need to check what is inside (and reg_overlap_mentioned_p
2822 doesn't support those codes anyway). Don't allow those destinations;
2823 the resulting insn isn't likely to be recognized anyway. */
2824 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2825 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2826 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2827 SET_DEST (PATTERN (i3
)))
2828 && next_active_insn (i2
) == i3
)
2830 rtx p2
= PATTERN (i2
);
2832 /* Make sure that the destination of I3,
2833 which we are going to substitute into one output of I2,
2834 is not used within another output of I2. We must avoid making this:
2835 (parallel [(set (mem (reg 69)) ...)
2836 (set (reg 69) ...)])
2837 which is not well-defined as to order of actions.
2838 (Besides, reload can't handle output reloads for this.)
2840 The problem can also happen if the dest of I3 is a memory ref,
2841 if another dest in I2 is an indirect memory ref.
2843 Neither can this PARALLEL be an asm. We do not allow combining
2844 that usually (see can_combine_p), so do not here either. */
2846 for (i
= 0; ok
&& i
< XVECLEN (p2
, 0); i
++)
2848 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2849 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2850 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2851 SET_DEST (XVECEXP (p2
, 0, i
))))
2853 else if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2854 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2859 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2860 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2861 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2866 subst_low_luid
= DF_INSN_LUID (i2
);
2868 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2869 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2870 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2871 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2873 /* Replace the dest in I2 with our dest and make the resulting
2874 insn the new pattern for I3. Then skip to where we validate
2875 the pattern. Everything was set up above. */
2876 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2878 i3_subst_into_i2
= 1;
2879 goto validate_replacement
;
2883 /* If I2 is setting a pseudo to a constant and I3 is setting some
2884 sub-part of it to another constant, merge them by making a new
2887 && (temp_expr
= single_set (i2
)) != 0
2888 && is_a
<scalar_int_mode
> (GET_MODE (SET_DEST (temp_expr
)), &temp_mode
)
2889 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2890 && GET_CODE (PATTERN (i3
)) == SET
2891 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2892 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2894 rtx dest
= SET_DEST (PATTERN (i3
));
2895 rtx temp_dest
= SET_DEST (temp_expr
);
2899 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2901 if (CONST_INT_P (XEXP (dest
, 1))
2902 && CONST_INT_P (XEXP (dest
, 2))
2903 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (dest
, 0)),
2906 width
= INTVAL (XEXP (dest
, 1));
2907 offset
= INTVAL (XEXP (dest
, 2));
2908 dest
= XEXP (dest
, 0);
2909 if (BITS_BIG_ENDIAN
)
2910 offset
= GET_MODE_PRECISION (dest_mode
) - width
- offset
;
2915 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2916 dest
= XEXP (dest
, 0);
2917 if (is_a
<scalar_int_mode
> (GET_MODE (dest
), &dest_mode
))
2919 width
= GET_MODE_PRECISION (dest_mode
);
2926 /* If this is the low part, we're done. */
2927 if (subreg_lowpart_p (dest
))
2929 /* Handle the case where inner is twice the size of outer. */
2930 else if (GET_MODE_PRECISION (temp_mode
)
2931 == 2 * GET_MODE_PRECISION (dest_mode
))
2932 offset
+= GET_MODE_PRECISION (dest_mode
);
2933 /* Otherwise give up for now. */
2940 rtx inner
= SET_SRC (PATTERN (i3
));
2941 rtx outer
= SET_SRC (temp_expr
);
2943 wide_int o
= wi::insert (rtx_mode_t (outer
, temp_mode
),
2944 rtx_mode_t (inner
, dest_mode
),
2949 subst_low_luid
= DF_INSN_LUID (i2
);
2950 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2952 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2954 /* Replace the source in I2 with the new constant and make the
2955 resulting insn the new pattern for I3. Then skip to where we
2956 validate the pattern. Everything was set up above. */
2957 SUBST (SET_SRC (temp_expr
),
2958 immed_wide_int_const (o
, temp_mode
));
2960 newpat
= PATTERN (i2
);
2962 /* The dest of I3 has been replaced with the dest of I2. */
2963 changed_i3_dest
= 1;
2964 goto validate_replacement
;
2968 /* If we have no I1 and I2 looks like:
2969 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2971 make up a dummy I1 that is
2974 (set (reg:CC X) (compare:CC Y (const_int 0)))
2976 (We can ignore any trailing CLOBBERs.)
2978 This undoes a previous combination and allows us to match a branch-and-
2981 if (!HAVE_cc0
&& i1
== 0
2982 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2983 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2985 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2986 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2987 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2988 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2989 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2990 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2992 /* We make I1 with the same INSN_UID as I2. This gives it
2993 the same DF_INSN_LUID for value tracking. Our fake I1 will
2994 never appear in the insn stream so giving it the same INSN_UID
2995 as I2 will not cause a problem. */
2997 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2998 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
3000 INSN_UID (i1
) = INSN_UID (i2
);
3002 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
3003 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
3004 SET_DEST (PATTERN (i1
)));
3005 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
3006 SUBST_LINK (LOG_LINKS (i2
),
3007 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
3010 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3011 make those two SETs separate I1 and I2 insns, and make an I0 that is
3013 if (!HAVE_cc0
&& i0
== 0
3014 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
3015 && can_split_parallel_of_n_reg_sets (i2
, 2)
3016 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3017 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
)
3018 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3019 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
3021 /* If there is no I1, there is no I0 either. */
3024 /* We make I1 with the same INSN_UID as I2. This gives it
3025 the same DF_INSN_LUID for value tracking. Our fake I1 will
3026 never appear in the insn stream so giving it the same INSN_UID
3027 as I2 will not cause a problem. */
3029 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
3030 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
3032 INSN_UID (i1
) = INSN_UID (i2
);
3034 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
3037 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3038 if (!can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
))
3041 fprintf (dump_file
, "Can't combine i2 into i3\n");
3045 if (i1
&& !can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
, &i1dest
, &i1src
))
3048 fprintf (dump_file
, "Can't combine i1 into i3\n");
3052 if (i0
&& !can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
, &i0dest
, &i0src
))
3055 fprintf (dump_file
, "Can't combine i0 into i3\n");
3060 /* Record whether I2DEST is used in I2SRC and similarly for the other
3061 cases. Knowing this will help in register status updating below. */
3062 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3063 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3064 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3065 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3066 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3067 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3068 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3069 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3070 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3072 /* For the earlier insns, determine which of the subsequent ones they
3074 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3075 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3076 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3077 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3078 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3080 /* Ensure that I3's pattern can be the destination of combines. */
3081 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3082 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3083 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3084 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3091 /* See if any of the insns is a MULT operation. Unless one is, we will
3092 reject a combination that is, since it must be slower. Be conservative
3094 if (GET_CODE (i2src
) == MULT
3095 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3096 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3097 || (GET_CODE (PATTERN (i3
)) == SET
3098 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3101 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3102 We used to do this EXCEPT in one case: I3 has a post-inc in an
3103 output operand. However, that exception can give rise to insns like
3105 which is a famous insn on the PDP-11 where the value of r3 used as the
3106 source was model-dependent. Avoid this sort of thing. */
3109 if (!(GET_CODE (PATTERN (i3
)) == SET
3110 && REG_P (SET_SRC (PATTERN (i3
)))
3111 && MEM_P (SET_DEST (PATTERN (i3
)))
3112 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3113 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3114 /* It's not the exception. */
3119 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3120 if (REG_NOTE_KIND (link
) == REG_INC
3121 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3123 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3130 /* See if the SETs in I1 or I2 need to be kept around in the merged
3131 instruction: whenever the value set there is still needed past I3.
3132 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3134 For the SET in I1, we have two cases: if I1 and I2 independently feed
3135 into I3, the set in I1 needs to be kept around unless I1DEST dies
3136 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3137 in I1 needs to be kept around unless I1DEST dies or is set in either
3138 I2 or I3. The same considerations apply to I0. */
3140 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3143 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3144 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3149 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3150 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3151 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3152 && dead_or_set_p (i2
, i0dest
)));
3156 /* We are about to copy insns for the case where they need to be kept
3157 around. Check that they can be copied in the merged instruction. */
3159 if (targetm
.cannot_copy_insn_p
3160 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3161 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3162 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3168 /* If the set in I2 needs to be kept around, we must make a copy of
3169 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3170 PATTERN (I2), we are only substituting for the original I1DEST, not into
3171 an already-substituted copy. This also prevents making self-referential
3172 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3177 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3178 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3180 i2pat
= copy_rtx (PATTERN (i2
));
3185 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3186 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3188 i1pat
= copy_rtx (PATTERN (i1
));
3193 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3194 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3196 i0pat
= copy_rtx (PATTERN (i0
));
3201 /* Substitute in the latest insn for the regs set by the earlier ones. */
3203 maxreg
= max_reg_num ();
3207 /* Many machines that don't use CC0 have insns that can both perform an
3208 arithmetic operation and set the condition code. These operations will
3209 be represented as a PARALLEL with the first element of the vector
3210 being a COMPARE of an arithmetic operation with the constant zero.
3211 The second element of the vector will set some pseudo to the result
3212 of the same arithmetic operation. If we simplify the COMPARE, we won't
3213 match such a pattern and so will generate an extra insn. Here we test
3214 for this case, where both the comparison and the operation result are
3215 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3216 I2SRC. Later we will make the PARALLEL that contains I2. */
3218 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3219 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3220 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3221 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3224 rtx
*cc_use_loc
= NULL
;
3225 rtx_insn
*cc_use_insn
= NULL
;
3226 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3227 machine_mode compare_mode
, orig_compare_mode
;
3228 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3229 scalar_int_mode mode
;
3231 newpat
= PATTERN (i3
);
3232 newpat_dest
= SET_DEST (newpat
);
3233 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3235 if (undobuf
.other_insn
== 0
3236 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3239 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3240 if (is_a
<scalar_int_mode
> (GET_MODE (i2dest
), &mode
))
3241 compare_code
= simplify_compare_const (compare_code
, mode
,
3243 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3246 /* Do the rest only if op1 is const0_rtx, which may be the
3247 result of simplification. */
3248 if (op1
== const0_rtx
)
3250 /* If a single use of the CC is found, prepare to modify it
3251 when SELECT_CC_MODE returns a new CC-class mode, or when
3252 the above simplify_compare_const() returned a new comparison
3253 operator. undobuf.other_insn is assigned the CC use insn
3254 when modifying it. */
3257 #ifdef SELECT_CC_MODE
3258 machine_mode new_mode
3259 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3260 if (new_mode
!= orig_compare_mode
3261 && can_change_dest_mode (SET_DEST (newpat
),
3262 added_sets_2
, new_mode
))
3264 unsigned int regno
= REGNO (newpat_dest
);
3265 compare_mode
= new_mode
;
3266 if (regno
< FIRST_PSEUDO_REGISTER
)
3267 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3270 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3271 newpat_dest
= regno_reg_rtx
[regno
];
3275 /* Cases for modifying the CC-using comparison. */
3276 if (compare_code
!= orig_compare_code
3277 /* ??? Do we need to verify the zero rtx? */
3278 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3280 /* Replace cc_use_loc with entire new RTX. */
3282 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3283 newpat_dest
, const0_rtx
));
3284 undobuf
.other_insn
= cc_use_insn
;
3286 else if (compare_mode
!= orig_compare_mode
)
3288 /* Just replace the CC reg with a new mode. */
3289 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3290 undobuf
.other_insn
= cc_use_insn
;
3294 /* Now we modify the current newpat:
3295 First, SET_DEST(newpat) is updated if the CC mode has been
3296 altered. For targets without SELECT_CC_MODE, this should be
3298 if (compare_mode
!= orig_compare_mode
)
3299 SUBST (SET_DEST (newpat
), newpat_dest
);
3300 /* This is always done to propagate i2src into newpat. */
3301 SUBST (SET_SRC (newpat
),
3302 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3303 /* Create new version of i2pat if needed; the below PARALLEL
3304 creation needs this to work correctly. */
3305 if (! rtx_equal_p (i2src
, op0
))
3306 i2pat
= gen_rtx_SET (i2dest
, op0
);
3311 if (i2_is_used
== 0)
3313 /* It is possible that the source of I2 or I1 may be performing
3314 an unneeded operation, such as a ZERO_EXTEND of something
3315 that is known to have the high part zero. Handle that case
3316 by letting subst look at the inner insns.
3318 Another way to do this would be to have a function that tries
3319 to simplify a single insn instead of merging two or more
3320 insns. We don't do this because of the potential of infinite
3321 loops and because of the potential extra memory required.
3322 However, doing it the way we are is a bit of a kludge and
3323 doesn't catch all cases.
3325 But only do this if -fexpensive-optimizations since it slows
3326 things down and doesn't usually win.
3328 This is not done in the COMPARE case above because the
3329 unmodified I2PAT is used in the PARALLEL and so a pattern
3330 with a modified I2SRC would not match. */
3332 if (flag_expensive_optimizations
)
3334 /* Pass pc_rtx so no substitutions are done, just
3338 subst_low_luid
= DF_INSN_LUID (i1
);
3339 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3342 subst_low_luid
= DF_INSN_LUID (i2
);
3343 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3346 n_occurrences
= 0; /* `subst' counts here */
3347 subst_low_luid
= DF_INSN_LUID (i2
);
3349 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3350 copy of I2SRC each time we substitute it, in order to avoid creating
3351 self-referential RTL when we will be substituting I1SRC for I1DEST
3352 later. Likewise if I0 feeds into I2, either directly or indirectly
3353 through I1, and I0DEST is in I0SRC. */
3354 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3355 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3356 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3357 && i0dest_in_i0src
));
3360 /* Record whether I2's body now appears within I3's body. */
3361 i2_is_used
= n_occurrences
;
3364 /* If we already got a failure, don't try to do more. Otherwise, try to
3365 substitute I1 if we have it. */
3367 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3369 /* Check that an autoincrement side-effect on I1 has not been lost.
3370 This happens if I1DEST is mentioned in I2 and dies there, and
3371 has disappeared from the new pattern. */
3372 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3374 && dead_or_set_p (i2
, i1dest
)
3375 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3376 /* Before we can do this substitution, we must redo the test done
3377 above (see detailed comments there) that ensures I1DEST isn't
3378 mentioned in any SETs in NEWPAT that are field assignments. */
3379 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3387 subst_low_luid
= DF_INSN_LUID (i1
);
3389 /* If the following substitution will modify I1SRC, make a copy of it
3390 for the case where it is substituted for I1DEST in I2PAT later. */
3391 if (added_sets_2
&& i1_feeds_i2_n
)
3392 i1src_copy
= copy_rtx (i1src
);
3394 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3395 copy of I1SRC each time we substitute it, in order to avoid creating
3396 self-referential RTL when we will be substituting I0SRC for I0DEST
3398 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3399 i0_feeds_i1_n
&& i0dest_in_i0src
);
3402 /* Record whether I1's body now appears within I3's body. */
3403 i1_is_used
= n_occurrences
;
3406 /* Likewise for I0 if we have it. */
3408 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3410 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3411 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3412 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3413 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3414 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3421 /* If the following substitution will modify I0SRC, make a copy of it
3422 for the case where it is substituted for I0DEST in I1PAT later. */
3423 if (added_sets_1
&& i0_feeds_i1_n
)
3424 i0src_copy
= copy_rtx (i0src
);
3425 /* And a copy for I0DEST in I2PAT substitution. */
3426 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3427 || (i0_feeds_i2_n
)))
3428 i0src_copy2
= copy_rtx (i0src
);
3431 subst_low_luid
= DF_INSN_LUID (i0
);
3432 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3436 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3437 to count all the ways that I2SRC and I1SRC can be used. */
3438 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3439 && i2_is_used
+ added_sets_2
> 1)
3440 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3441 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3443 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3444 && (n_occurrences
+ added_sets_0
3445 + (added_sets_1
&& i0_feeds_i1_n
)
3446 + (added_sets_2
&& i0_feeds_i2_n
)
3448 /* Fail if we tried to make a new register. */
3449 || max_reg_num () != maxreg
3450 /* Fail if we couldn't do something and have a CLOBBER. */
3451 || GET_CODE (newpat
) == CLOBBER
3452 /* Fail if this new pattern is a MULT and we didn't have one before
3453 at the outer level. */
3454 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3461 /* If the actions of the earlier insns must be kept
3462 in addition to substituting them into the latest one,
3463 we must make a new PARALLEL for the latest insn
3464 to hold additional the SETs. */
3466 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3468 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3471 if (GET_CODE (newpat
) == PARALLEL
)
3473 rtvec old
= XVEC (newpat
, 0);
3474 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3475 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3476 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3477 sizeof (old
->elem
[0]) * old
->num_elem
);
3482 total_sets
= 1 + extra_sets
;
3483 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3484 XVECEXP (newpat
, 0, 0) = old
;
3488 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3494 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3496 XVECEXP (newpat
, 0, --total_sets
) = t
;
3502 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3503 i0_feeds_i1_n
&& i0dest_in_i0src
);
3504 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3505 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3507 XVECEXP (newpat
, 0, --total_sets
) = t
;
3511 validate_replacement
:
3513 /* Note which hard regs this insn has as inputs. */
3514 mark_used_regs_combine (newpat
);
3516 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3517 consider splitting this pattern, we might need these clobbers. */
3518 if (i1
&& GET_CODE (newpat
) == PARALLEL
3519 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3521 int len
= XVECLEN (newpat
, 0);
3523 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3524 for (i
= 0; i
< len
; i
++)
3525 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3528 /* We have recognized nothing yet. */
3529 insn_code_number
= -1;
3531 /* See if this is a PARALLEL of two SETs where one SET's destination is
3532 a register that is unused and this isn't marked as an instruction that
3533 might trap in an EH region. In that case, we just need the other SET.
3534 We prefer this over the PARALLEL.
3536 This can occur when simplifying a divmod insn. We *must* test for this
3537 case here because the code below that splits two independent SETs doesn't
3538 handle this case correctly when it updates the register status.
3540 It's pointless doing this if we originally had two sets, one from
3541 i3, and one from i2. Combining then splitting the parallel results
3542 in the original i2 again plus an invalid insn (which we delete).
3543 The net effect is only to move instructions around, which makes
3544 debug info less accurate.
3546 If the remaining SET came from I2 its destination should not be used
3547 between I2 and I3. See PR82024. */
3549 if (!(added_sets_2
&& i1
== 0)
3550 && is_parallel_of_n_reg_sets (newpat
, 2)
3551 && asm_noperands (newpat
) < 0)
3553 rtx set0
= XVECEXP (newpat
, 0, 0);
3554 rtx set1
= XVECEXP (newpat
, 0, 1);
3555 rtx oldpat
= newpat
;
3557 if (((REG_P (SET_DEST (set1
))
3558 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3559 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3560 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3561 && insn_nothrow_p (i3
)
3562 && !side_effects_p (SET_SRC (set1
)))
3565 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3568 else if (((REG_P (SET_DEST (set0
))
3569 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3570 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3571 && find_reg_note (i3
, REG_UNUSED
,
3572 SUBREG_REG (SET_DEST (set0
)))))
3573 && insn_nothrow_p (i3
)
3574 && !side_effects_p (SET_SRC (set0
)))
3576 rtx dest
= SET_DEST (set1
);
3577 if (GET_CODE (dest
) == SUBREG
)
3578 dest
= SUBREG_REG (dest
);
3579 if (!reg_used_between_p (dest
, i2
, i3
))
3582 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3584 if (insn_code_number
>= 0)
3585 changed_i3_dest
= 1;
3589 if (insn_code_number
< 0)
3593 /* Is the result of combination a valid instruction? */
3594 if (insn_code_number
< 0)
3595 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3597 /* If we were combining three insns and the result is a simple SET
3598 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3599 insns. There are two ways to do this. It can be split using a
3600 machine-specific method (like when you have an addition of a large
3601 constant) or by combine in the function find_split_point. */
3603 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3604 && asm_noperands (newpat
) < 0)
3606 rtx parallel
, *split
;
3607 rtx_insn
*m_split_insn
;
3609 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3610 use I2DEST as a scratch register will help. In the latter case,
3611 convert I2DEST to the mode of the source of NEWPAT if we can. */
3613 m_split_insn
= combine_split_insns (newpat
, i3
);
3615 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3616 inputs of NEWPAT. */
3618 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3619 possible to try that as a scratch reg. This would require adding
3620 more code to make it work though. */
3622 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3624 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3626 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3627 (temporarily, until we are committed to this instruction
3628 combination) does not work: for example, any call to nonzero_bits
3629 on the register (from a splitter in the MD file, for example)
3630 will get the old information, which is invalid.
3632 Since nowadays we can create registers during combine just fine,
3633 we should just create a new one here, not reuse i2dest. */
3635 /* First try to split using the original register as a
3636 scratch register. */
3637 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3638 gen_rtvec (2, newpat
,
3639 gen_rtx_CLOBBER (VOIDmode
,
3641 m_split_insn
= combine_split_insns (parallel
, i3
);
3643 /* If that didn't work, try changing the mode of I2DEST if
3645 if (m_split_insn
== 0
3646 && new_mode
!= GET_MODE (i2dest
)
3647 && new_mode
!= VOIDmode
3648 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3650 machine_mode old_mode
= GET_MODE (i2dest
);
3653 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3654 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3657 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3658 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3661 parallel
= (gen_rtx_PARALLEL
3663 gen_rtvec (2, newpat
,
3664 gen_rtx_CLOBBER (VOIDmode
,
3666 m_split_insn
= combine_split_insns (parallel
, i3
);
3668 if (m_split_insn
== 0
3669 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3673 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3674 buf
= undobuf
.undos
;
3675 undobuf
.undos
= buf
->next
;
3676 buf
->next
= undobuf
.frees
;
3677 undobuf
.frees
= buf
;
3681 i2scratch
= m_split_insn
!= 0;
3684 /* If recog_for_combine has discarded clobbers, try to use them
3685 again for the split. */
3686 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3688 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3689 m_split_insn
= combine_split_insns (parallel
, i3
);
3692 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3694 rtx m_split_pat
= PATTERN (m_split_insn
);
3695 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3696 if (insn_code_number
>= 0)
3697 newpat
= m_split_pat
;
3699 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3700 && (next_nonnote_nondebug_insn (i2
) == i3
3701 || !modified_between_p (PATTERN (m_split_insn
), i2
, i3
)))
3704 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3705 newi2pat
= PATTERN (m_split_insn
);
3707 i3set
= single_set (NEXT_INSN (m_split_insn
));
3708 i2set
= single_set (m_split_insn
);
3710 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3712 /* If I2 or I3 has multiple SETs, we won't know how to track
3713 register status, so don't use these insns. If I2's destination
3714 is used between I2 and I3, we also can't use these insns. */
3716 if (i2_code_number
>= 0 && i2set
&& i3set
3717 && (next_nonnote_nondebug_insn (i2
) == i3
3718 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3719 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3721 if (insn_code_number
>= 0)
3724 /* It is possible that both insns now set the destination of I3.
3725 If so, we must show an extra use of it. */
3727 if (insn_code_number
>= 0)
3729 rtx new_i3_dest
= SET_DEST (i3set
);
3730 rtx new_i2_dest
= SET_DEST (i2set
);
3732 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3733 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3734 || GET_CODE (new_i3_dest
) == SUBREG
)
3735 new_i3_dest
= XEXP (new_i3_dest
, 0);
3737 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3738 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3739 || GET_CODE (new_i2_dest
) == SUBREG
)
3740 new_i2_dest
= XEXP (new_i2_dest
, 0);
3742 if (REG_P (new_i3_dest
)
3743 && REG_P (new_i2_dest
)
3744 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3745 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3746 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3750 /* If we can split it and use I2DEST, go ahead and see if that
3751 helps things be recognized. Verify that none of the registers
3752 are set between I2 and I3. */
3753 if (insn_code_number
< 0
3754 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3755 && (!HAVE_cc0
|| REG_P (i2dest
))
3756 /* We need I2DEST in the proper mode. If it is a hard register
3757 or the only use of a pseudo, we can change its mode.
3758 Make sure we don't change a hard register to have a mode that
3759 isn't valid for it, or change the number of registers. */
3760 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3761 || GET_MODE (*split
) == VOIDmode
3762 || can_change_dest_mode (i2dest
, added_sets_2
,
3764 && (next_nonnote_nondebug_insn (i2
) == i3
3765 || !modified_between_p (*split
, i2
, i3
))
3766 /* We can't overwrite I2DEST if its value is still used by
3768 && ! reg_referenced_p (i2dest
, newpat
))
3770 rtx newdest
= i2dest
;
3771 enum rtx_code split_code
= GET_CODE (*split
);
3772 machine_mode split_mode
= GET_MODE (*split
);
3773 bool subst_done
= false;
3774 newi2pat
= NULL_RTX
;
3778 /* *SPLIT may be part of I2SRC, so make sure we have the
3779 original expression around for later debug processing.
3780 We should not need I2SRC any more in other cases. */
3781 if (MAY_HAVE_DEBUG_BIND_INSNS
)
3782 i2src
= copy_rtx (i2src
);
3786 /* Get NEWDEST as a register in the proper mode. We have already
3787 validated that we can do this. */
3788 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3790 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3791 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3794 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3795 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3799 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3800 an ASHIFT. This can occur if it was inside a PLUS and hence
3801 appeared to be a memory address. This is a kludge. */
3802 if (split_code
== MULT
3803 && CONST_INT_P (XEXP (*split
, 1))
3804 && INTVAL (XEXP (*split
, 1)) > 0
3805 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3807 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3808 XEXP (*split
, 0), GEN_INT (i
)));
3809 /* Update split_code because we may not have a multiply
3811 split_code
= GET_CODE (*split
);
3814 /* Similarly for (plus (mult FOO (const_int pow2))). */
3815 if (split_code
== PLUS
3816 && GET_CODE (XEXP (*split
, 0)) == MULT
3817 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3818 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3819 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3821 rtx nsplit
= XEXP (*split
, 0);
3822 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3823 XEXP (nsplit
, 0), GEN_INT (i
)));
3824 /* Update split_code because we may not have a multiply
3826 split_code
= GET_CODE (*split
);
3829 #ifdef INSN_SCHEDULING
3830 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3831 be written as a ZERO_EXTEND. */
3832 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3834 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3835 what it really is. */
3836 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3838 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3839 SUBREG_REG (*split
)));
3841 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3842 SUBREG_REG (*split
)));
3846 /* Attempt to split binary operators using arithmetic identities. */
3847 if (BINARY_P (SET_SRC (newpat
))
3848 && split_mode
== GET_MODE (SET_SRC (newpat
))
3849 && ! side_effects_p (SET_SRC (newpat
)))
3851 rtx setsrc
= SET_SRC (newpat
);
3852 machine_mode mode
= GET_MODE (setsrc
);
3853 enum rtx_code code
= GET_CODE (setsrc
);
3854 rtx src_op0
= XEXP (setsrc
, 0);
3855 rtx src_op1
= XEXP (setsrc
, 1);
3857 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3858 if (rtx_equal_p (src_op0
, src_op1
))
3860 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3861 SUBST (XEXP (setsrc
, 0), newdest
);
3862 SUBST (XEXP (setsrc
, 1), newdest
);
3865 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3866 else if ((code
== PLUS
|| code
== MULT
)
3867 && GET_CODE (src_op0
) == code
3868 && GET_CODE (XEXP (src_op0
, 0)) == code
3869 && (INTEGRAL_MODE_P (mode
)
3870 || (FLOAT_MODE_P (mode
)
3871 && flag_unsafe_math_optimizations
)))
3873 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3874 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3875 rtx r
= XEXP (src_op0
, 1);
3878 /* Split both "((X op Y) op X) op Y" and
3879 "((X op Y) op Y) op X" as "T op T" where T is
3881 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3882 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3884 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3885 SUBST (XEXP (setsrc
, 0), newdest
);
3886 SUBST (XEXP (setsrc
, 1), newdest
);
3889 /* Split "((X op X) op Y) op Y)" as "T op T" where
3891 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3893 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3894 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3895 SUBST (XEXP (setsrc
, 0), newdest
);
3896 SUBST (XEXP (setsrc
, 1), newdest
);
3904 newi2pat
= gen_rtx_SET (newdest
, *split
);
3905 SUBST (*split
, newdest
);
3908 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3910 /* recog_for_combine might have added CLOBBERs to newi2pat.
3911 Make sure NEWPAT does not depend on the clobbered regs. */
3912 if (GET_CODE (newi2pat
) == PARALLEL
)
3913 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3914 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3916 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3917 if (reg_overlap_mentioned_p (reg
, newpat
))
3924 /* If the split point was a MULT and we didn't have one before,
3925 don't use one now. */
3926 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3927 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3931 /* Check for a case where we loaded from memory in a narrow mode and
3932 then sign extended it, but we need both registers. In that case,
3933 we have a PARALLEL with both loads from the same memory location.
3934 We can split this into a load from memory followed by a register-register
3935 copy. This saves at least one insn, more if register allocation can
3938 We cannot do this if the destination of the first assignment is a
3939 condition code register or cc0. We eliminate this case by making sure
3940 the SET_DEST and SET_SRC have the same mode.
3942 We cannot do this if the destination of the second assignment is
3943 a register that we have already assumed is zero-extended. Similarly
3944 for a SUBREG of such a register. */
3946 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3947 && GET_CODE (newpat
) == PARALLEL
3948 && XVECLEN (newpat
, 0) == 2
3949 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3950 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3951 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3952 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3953 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3954 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3955 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3956 && !modified_between_p (SET_SRC (XVECEXP (newpat
, 0, 1)), i2
, i3
)
3957 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3958 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3959 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3961 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3962 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3963 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3964 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3965 != GET_MODE_MASK (word_mode
))))
3966 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3967 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3969 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3970 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3971 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3972 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3973 != GET_MODE_MASK (word_mode
)))))
3974 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3975 SET_SRC (XVECEXP (newpat
, 0, 1)))
3976 && ! find_reg_note (i3
, REG_UNUSED
,
3977 SET_DEST (XVECEXP (newpat
, 0, 0))))
3981 newi2pat
= XVECEXP (newpat
, 0, 0);
3982 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3983 newpat
= XVECEXP (newpat
, 0, 1);
3984 SUBST (SET_SRC (newpat
),
3985 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3986 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3988 if (i2_code_number
>= 0)
3989 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3991 if (insn_code_number
>= 0)
3995 /* Similarly, check for a case where we have a PARALLEL of two independent
3996 SETs but we started with three insns. In this case, we can do the sets
3997 as two separate insns. This case occurs when some SET allows two
3998 other insns to combine, but the destination of that SET is still live.
4000 Also do this if we started with two insns and (at least) one of the
4001 resulting sets is a noop; this noop will be deleted later. */
4003 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
4004 && GET_CODE (newpat
) == PARALLEL
4005 && XVECLEN (newpat
, 0) == 2
4006 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
4007 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
4008 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
4009 || set_noop_p (XVECEXP (newpat
, 0, 1)))
4010 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
4011 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
4012 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
4013 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
4014 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
4015 XVECEXP (newpat
, 0, 0))
4016 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
4017 XVECEXP (newpat
, 0, 1))
4018 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
4019 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
4021 rtx set0
= XVECEXP (newpat
, 0, 0);
4022 rtx set1
= XVECEXP (newpat
, 0, 1);
4024 /* Normally, it doesn't matter which of the two is done first,
4025 but the one that references cc0 can't be the second, and
4026 one which uses any regs/memory set in between i2 and i3 can't
4027 be first. The PARALLEL might also have been pre-existing in i3,
4028 so we need to make sure that we won't wrongly hoist a SET to i2
4029 that would conflict with a death note present in there. */
4030 if (!modified_between_p (SET_SRC (set1
), i2
, i3
)
4031 && !(REG_P (SET_DEST (set1
))
4032 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
4033 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
4034 && find_reg_note (i2
, REG_DEAD
,
4035 SUBREG_REG (SET_DEST (set1
))))
4036 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
4037 /* If I3 is a jump, ensure that set0 is a jump so that
4038 we do not create invalid RTL. */
4039 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
4045 else if (!modified_between_p (SET_SRC (set0
), i2
, i3
)
4046 && !(REG_P (SET_DEST (set0
))
4047 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
4048 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
4049 && find_reg_note (i2
, REG_DEAD
,
4050 SUBREG_REG (SET_DEST (set0
))))
4051 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
4052 /* If I3 is a jump, ensure that set1 is a jump so that
4053 we do not create invalid RTL. */
4054 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
4066 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4068 if (i2_code_number
>= 0)
4070 /* recog_for_combine might have added CLOBBERs to newi2pat.
4071 Make sure NEWPAT does not depend on the clobbered regs. */
4072 if (GET_CODE (newi2pat
) == PARALLEL
)
4074 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4075 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4077 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4078 if (reg_overlap_mentioned_p (reg
, newpat
))
4086 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4090 /* If it still isn't recognized, fail and change things back the way they
4092 if ((insn_code_number
< 0
4093 /* Is the result a reasonable ASM_OPERANDS? */
4094 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4100 /* If we had to change another insn, make sure it is valid also. */
4101 if (undobuf
.other_insn
)
4103 CLEAR_HARD_REG_SET (newpat_used_regs
);
4105 other_pat
= PATTERN (undobuf
.other_insn
);
4106 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4109 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4116 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4117 they are adjacent to each other or not. */
4120 rtx_insn
*p
= prev_nonnote_insn (i3
);
4121 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4122 && sets_cc0_p (newi2pat
))
4129 /* Only allow this combination if insn_cost reports that the
4130 replacement instructions are cheaper than the originals. */
4131 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4137 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4141 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4142 if (undo
->kind
== UNDO_MODE
)
4144 rtx reg
= *undo
->where
.r
;
4145 machine_mode new_mode
= GET_MODE (reg
);
4146 machine_mode old_mode
= undo
->old_contents
.m
;
4148 /* Temporarily revert mode back. */
4149 adjust_reg_mode (reg
, old_mode
);
4151 if (reg
== i2dest
&& i2scratch
)
4153 /* If we used i2dest as a scratch register with a
4154 different mode, substitute it for the original
4155 i2src while its original mode is temporarily
4156 restored, and then clear i2scratch so that we don't
4157 do it again later. */
4158 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4161 /* Put back the new mode. */
4162 adjust_reg_mode (reg
, new_mode
);
4166 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4167 rtx_insn
*first
, *last
;
4172 last
= last_combined_insn
;
4177 last
= undobuf
.other_insn
;
4179 if (DF_INSN_LUID (last
)
4180 < DF_INSN_LUID (last_combined_insn
))
4181 last
= last_combined_insn
;
4184 /* We're dealing with a reg that changed mode but not
4185 meaning, so we want to turn it into a subreg for
4186 the new mode. However, because of REG sharing and
4187 because its mode had already changed, we have to do
4188 it in two steps. First, replace any debug uses of
4189 reg, with its original mode temporarily restored,
4190 with this copy we have created; then, replace the
4191 copy with the SUBREG of the original shared reg,
4192 once again changed to the new mode. */
4193 propagate_for_debug (first
, last
, reg
, tempreg
,
4195 adjust_reg_mode (reg
, new_mode
);
4196 propagate_for_debug (first
, last
, tempreg
,
4197 lowpart_subreg (old_mode
, reg
, new_mode
),
4203 /* If we will be able to accept this, we have made a
4204 change to the destination of I3. This requires us to
4205 do a few adjustments. */
4207 if (changed_i3_dest
)
4209 PATTERN (i3
) = newpat
;
4210 adjust_for_new_dest (i3
);
4213 /* We now know that we can do this combination. Merge the insns and
4214 update the status of registers and LOG_LINKS. */
4216 if (undobuf
.other_insn
)
4220 PATTERN (undobuf
.other_insn
) = other_pat
;
4222 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4223 ensure that they are still valid. Then add any non-duplicate
4224 notes added by recog_for_combine. */
4225 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4227 next
= XEXP (note
, 1);
4229 if ((REG_NOTE_KIND (note
) == REG_DEAD
4230 && !reg_referenced_p (XEXP (note
, 0),
4231 PATTERN (undobuf
.other_insn
)))
4232 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4233 && !reg_set_p (XEXP (note
, 0),
4234 PATTERN (undobuf
.other_insn
)))
4235 /* Simply drop equal note since it may be no longer valid
4236 for other_insn. It may be possible to record that CC
4237 register is changed and only discard those notes, but
4238 in practice it's unnecessary complication and doesn't
4239 give any meaningful improvement.
4242 || REG_NOTE_KIND (note
) == REG_EQUAL
4243 || REG_NOTE_KIND (note
) == REG_EQUIV
)
4244 remove_note (undobuf
.other_insn
, note
);
4247 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4248 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4255 struct insn_link
*link
;
4258 /* I3 now uses what used to be its destination and which is now
4259 I2's destination. This requires us to do a few adjustments. */
4260 PATTERN (i3
) = newpat
;
4261 adjust_for_new_dest (i3
);
4263 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4266 However, some later insn might be using I2's dest and have
4267 a LOG_LINK pointing at I3. We must remove this link.
4268 The simplest way to remove the link is to point it at I1,
4269 which we know will be a NOTE. */
4271 /* newi2pat is usually a SET here; however, recog_for_combine might
4272 have added some clobbers. */
4273 if (GET_CODE (newi2pat
) == PARALLEL
)
4274 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4276 ni2dest
= SET_DEST (newi2pat
);
4278 for (insn
= NEXT_INSN (i3
);
4279 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4280 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4281 insn
= NEXT_INSN (insn
))
4283 if (NONDEBUG_INSN_P (insn
)
4284 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4286 FOR_EACH_LOG_LINK (link
, insn
)
4287 if (link
->insn
== i3
)
4296 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4297 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4300 /* Compute which registers we expect to eliminate. newi2pat may be setting
4301 either i3dest or i2dest, so we must check it. */
4302 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4303 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4306 /* For i1, we need to compute both local elimination and global
4307 elimination information with respect to newi2pat because i1dest
4308 may be the same as i3dest, in which case newi2pat may be setting
4309 i1dest. Global information is used when distributing REG_DEAD
4310 note for i2 and i3, in which case it does matter if newi2pat sets
4313 Local information is used when distributing REG_DEAD note for i1,
4314 in which case it doesn't matter if newi2pat sets i1dest or not.
4315 See PR62151, if we have four insns combination:
4317 i1: r1 <- i1src (using r0)
4319 i2: r0 <- i2src (using r1)
4320 i3: r3 <- i3src (using r0)
4322 From i1's point of view, r0 is eliminated, no matter if it is set
4323 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4324 should be discarded.
4326 Note local information only affects cases in forms like "I1->I2->I3",
4327 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4328 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4330 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4333 rtx elim_i1
= (local_elim_i1
== 0
4334 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4336 /* Same case as i1. */
4337 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4339 rtx elim_i0
= (local_elim_i0
== 0
4340 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4343 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4345 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4346 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4348 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4350 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4352 /* Ensure that we do not have something that should not be shared but
4353 occurs multiple times in the new insns. Check this by first
4354 resetting all the `used' flags and then copying anything is shared. */
4356 reset_used_flags (i3notes
);
4357 reset_used_flags (i2notes
);
4358 reset_used_flags (i1notes
);
4359 reset_used_flags (i0notes
);
4360 reset_used_flags (newpat
);
4361 reset_used_flags (newi2pat
);
4362 if (undobuf
.other_insn
)
4363 reset_used_flags (PATTERN (undobuf
.other_insn
));
4365 i3notes
= copy_rtx_if_shared (i3notes
);
4366 i2notes
= copy_rtx_if_shared (i2notes
);
4367 i1notes
= copy_rtx_if_shared (i1notes
);
4368 i0notes
= copy_rtx_if_shared (i0notes
);
4369 newpat
= copy_rtx_if_shared (newpat
);
4370 newi2pat
= copy_rtx_if_shared (newi2pat
);
4371 if (undobuf
.other_insn
)
4372 reset_used_flags (PATTERN (undobuf
.other_insn
));
4374 INSN_CODE (i3
) = insn_code_number
;
4375 PATTERN (i3
) = newpat
;
4377 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4379 for (rtx link
= CALL_INSN_FUNCTION_USAGE (i3
); link
;
4380 link
= XEXP (link
, 1))
4384 /* I2SRC must still be meaningful at this point. Some
4385 splitting operations can invalidate I2SRC, but those
4386 operations do not apply to calls. */
4388 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4392 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4395 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4400 if (undobuf
.other_insn
)
4401 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4403 /* We had one special case above where I2 had more than one set and
4404 we replaced a destination of one of those sets with the destination
4405 of I3. In that case, we have to update LOG_LINKS of insns later
4406 in this basic block. Note that this (expensive) case is rare.
4408 Also, in this case, we must pretend that all REG_NOTEs for I2
4409 actually came from I3, so that REG_UNUSED notes from I2 will be
4410 properly handled. */
4412 if (i3_subst_into_i2
)
4414 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4415 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4416 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4417 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4418 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4419 && ! find_reg_note (i2
, REG_UNUSED
,
4420 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4421 for (temp_insn
= NEXT_INSN (i2
);
4423 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4424 || BB_HEAD (this_basic_block
) != temp_insn
);
4425 temp_insn
= NEXT_INSN (temp_insn
))
4426 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4427 FOR_EACH_LOG_LINK (link
, temp_insn
)
4428 if (link
->insn
== i2
)
4434 while (XEXP (link
, 1))
4435 link
= XEXP (link
, 1);
4436 XEXP (link
, 1) = i2notes
;
4443 LOG_LINKS (i3
) = NULL
;
4445 LOG_LINKS (i2
) = NULL
;
4450 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2scratch
)
4451 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4453 INSN_CODE (i2
) = i2_code_number
;
4454 PATTERN (i2
) = newi2pat
;
4458 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2src
)
4459 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4461 SET_INSN_DELETED (i2
);
4466 LOG_LINKS (i1
) = NULL
;
4468 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4469 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4471 SET_INSN_DELETED (i1
);
4476 LOG_LINKS (i0
) = NULL
;
4478 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4479 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4481 SET_INSN_DELETED (i0
);
4484 /* Get death notes for everything that is now used in either I3 or
4485 I2 and used to die in a previous insn. If we built two new
4486 patterns, move from I1 to I2 then I2 to I3 so that we get the
4487 proper movement on registers that I2 modifies. */
4490 from_luid
= DF_INSN_LUID (i0
);
4492 from_luid
= DF_INSN_LUID (i1
);
4494 from_luid
= DF_INSN_LUID (i2
);
4496 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4497 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4499 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4501 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4502 elim_i2
, elim_i1
, elim_i0
);
4504 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4505 elim_i2
, elim_i1
, elim_i0
);
4507 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4508 elim_i2
, local_elim_i1
, local_elim_i0
);
4510 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4511 elim_i2
, elim_i1
, local_elim_i0
);
4513 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4514 elim_i2
, elim_i1
, elim_i0
);
4516 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4517 know these are REG_UNUSED and want them to go to the desired insn,
4518 so we always pass it as i3. */
4520 if (newi2pat
&& new_i2_notes
)
4521 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4525 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4528 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4529 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4530 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4531 in that case, it might delete I2. Similarly for I2 and I1.
4532 Show an additional death due to the REG_DEAD note we make here. If
4533 we discard it in distribute_notes, we will decrement it again. */
4537 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4538 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4539 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4542 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4543 elim_i2
, elim_i1
, elim_i0
);
4546 if (i2dest_in_i2src
)
4548 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4549 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4550 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4551 NULL_RTX
, NULL_RTX
);
4553 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4554 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4557 if (i1dest_in_i1src
)
4559 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4560 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4561 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4562 NULL_RTX
, NULL_RTX
);
4564 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4565 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4568 if (i0dest_in_i0src
)
4570 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4571 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4572 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4573 NULL_RTX
, NULL_RTX
);
4575 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4576 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4579 distribute_links (i3links
);
4580 distribute_links (i2links
);
4581 distribute_links (i1links
);
4582 distribute_links (i0links
);
4586 struct insn_link
*link
;
4587 rtx_insn
*i2_insn
= 0;
4588 rtx i2_val
= 0, set
;
4590 /* The insn that used to set this register doesn't exist, and
4591 this life of the register may not exist either. See if one of
4592 I3's links points to an insn that sets I2DEST. If it does,
4593 that is now the last known value for I2DEST. If we don't update
4594 this and I2 set the register to a value that depended on its old
4595 contents, we will get confused. If this insn is used, thing
4596 will be set correctly in combine_instructions. */
4597 FOR_EACH_LOG_LINK (link
, i3
)
4598 if ((set
= single_set (link
->insn
)) != 0
4599 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4600 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4602 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4604 /* If the reg formerly set in I2 died only once and that was in I3,
4605 zero its use count so it won't make `reload' do any work. */
4607 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4608 && ! i2dest_in_i2src
4609 && REGNO (i2dest
) < reg_n_sets_max
)
4610 INC_REG_N_SETS (REGNO (i2dest
), -1);
4613 if (i1
&& REG_P (i1dest
))
4615 struct insn_link
*link
;
4616 rtx_insn
*i1_insn
= 0;
4617 rtx i1_val
= 0, set
;
4619 FOR_EACH_LOG_LINK (link
, i3
)
4620 if ((set
= single_set (link
->insn
)) != 0
4621 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4622 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4624 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4627 && ! i1dest_in_i1src
4628 && REGNO (i1dest
) < reg_n_sets_max
)
4629 INC_REG_N_SETS (REGNO (i1dest
), -1);
4632 if (i0
&& REG_P (i0dest
))
4634 struct insn_link
*link
;
4635 rtx_insn
*i0_insn
= 0;
4636 rtx i0_val
= 0, set
;
4638 FOR_EACH_LOG_LINK (link
, i3
)
4639 if ((set
= single_set (link
->insn
)) != 0
4640 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4641 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4643 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4646 && ! i0dest_in_i0src
4647 && REGNO (i0dest
) < reg_n_sets_max
)
4648 INC_REG_N_SETS (REGNO (i0dest
), -1);
4651 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4652 been made to this insn. The order is important, because newi2pat
4653 can affect nonzero_bits of newpat. */
4655 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4656 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4659 if (undobuf
.other_insn
!= NULL_RTX
)
4663 fprintf (dump_file
, "modifying other_insn ");
4664 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4666 df_insn_rescan (undobuf
.other_insn
);
4669 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4673 fprintf (dump_file
, "modifying insn i0 ");
4674 dump_insn_slim (dump_file
, i0
);
4676 df_insn_rescan (i0
);
4679 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4683 fprintf (dump_file
, "modifying insn i1 ");
4684 dump_insn_slim (dump_file
, i1
);
4686 df_insn_rescan (i1
);
4689 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4693 fprintf (dump_file
, "modifying insn i2 ");
4694 dump_insn_slim (dump_file
, i2
);
4696 df_insn_rescan (i2
);
4699 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4703 fprintf (dump_file
, "modifying insn i3 ");
4704 dump_insn_slim (dump_file
, i3
);
4706 df_insn_rescan (i3
);
4709 /* Set new_direct_jump_p if a new return or simple jump instruction
4710 has been created. Adjust the CFG accordingly. */
4711 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4713 *new_direct_jump_p
= 1;
4714 mark_jump_label (PATTERN (i3
), i3
, 0);
4715 update_cfg_for_uncondjump (i3
);
4718 if (undobuf
.other_insn
!= NULL_RTX
4719 && (returnjump_p (undobuf
.other_insn
)
4720 || any_uncondjump_p (undobuf
.other_insn
)))
4722 *new_direct_jump_p
= 1;
4723 update_cfg_for_uncondjump (undobuf
.other_insn
);
4726 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4727 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4729 basic_block bb
= BLOCK_FOR_INSN (i3
);
4731 remove_edge (split_block (bb
, i3
));
4732 emit_barrier_after_bb (bb
);
4733 *new_direct_jump_p
= 1;
4736 if (undobuf
.other_insn
4737 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4738 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4740 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4742 remove_edge (split_block (bb
, undobuf
.other_insn
));
4743 emit_barrier_after_bb (bb
);
4744 *new_direct_jump_p
= 1;
4747 /* A noop might also need cleaning up of CFG, if it comes from the
4748 simplification of a jump. */
4750 && GET_CODE (newpat
) == SET
4751 && SET_SRC (newpat
) == pc_rtx
4752 && SET_DEST (newpat
) == pc_rtx
)
4754 *new_direct_jump_p
= 1;
4755 update_cfg_for_uncondjump (i3
);
4758 if (undobuf
.other_insn
!= NULL_RTX
4759 && JUMP_P (undobuf
.other_insn
)
4760 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4761 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4762 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4764 *new_direct_jump_p
= 1;
4765 update_cfg_for_uncondjump (undobuf
.other_insn
);
4768 combine_successes
++;
4771 rtx_insn
*ret
= newi2pat
? i2
: i3
;
4772 if (added_links_insn
&& DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (ret
))
4773 ret
= added_links_insn
;
4774 if (added_notes_insn
&& DF_INSN_LUID (added_notes_insn
) < DF_INSN_LUID (ret
))
4775 ret
= added_notes_insn
;
4780 /* Get a marker for undoing to the current state. */
4783 get_undo_marker (void)
4785 return undobuf
.undos
;
4788 /* Undo the modifications up to the marker. */
4791 undo_to_marker (void *marker
)
4793 struct undo
*undo
, *next
;
4795 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4803 *undo
->where
.r
= undo
->old_contents
.r
;
4806 *undo
->where
.i
= undo
->old_contents
.i
;
4809 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4812 *undo
->where
.l
= undo
->old_contents
.l
;
4818 undo
->next
= undobuf
.frees
;
4819 undobuf
.frees
= undo
;
4822 undobuf
.undos
= (struct undo
*) marker
;
4825 /* Undo all the modifications recorded in undobuf. */
4833 /* We've committed to accepting the changes we made. Move all
4834 of the undos to the free list. */
4839 struct undo
*undo
, *next
;
4841 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4844 undo
->next
= undobuf
.frees
;
4845 undobuf
.frees
= undo
;
4850 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4851 where we have an arithmetic expression and return that point. LOC will
4854 try_combine will call this function to see if an insn can be split into
4858 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4861 enum rtx_code code
= GET_CODE (x
);
4863 unsigned HOST_WIDE_INT len
= 0;
4864 HOST_WIDE_INT pos
= 0;
4866 rtx inner
= NULL_RTX
;
4867 scalar_int_mode mode
, inner_mode
;
4869 /* First special-case some codes. */
4873 #ifdef INSN_SCHEDULING
4874 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4876 if (MEM_P (SUBREG_REG (x
)))
4879 return find_split_point (&SUBREG_REG (x
), insn
, false);
4882 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4883 using LO_SUM and HIGH. */
4884 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4885 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4887 machine_mode address_mode
= get_address_mode (x
);
4890 gen_rtx_LO_SUM (address_mode
,
4891 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4893 return &XEXP (XEXP (x
, 0), 0);
4896 /* If we have a PLUS whose second operand is a constant and the
4897 address is not valid, perhaps will can split it up using
4898 the machine-specific way to split large constants. We use
4899 the first pseudo-reg (one of the virtual regs) as a placeholder;
4900 it will not remain in the result. */
4901 if (GET_CODE (XEXP (x
, 0)) == PLUS
4902 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4903 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4904 MEM_ADDR_SPACE (x
)))
4906 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4907 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4910 /* This should have produced two insns, each of which sets our
4911 placeholder. If the source of the second is a valid address,
4912 we can make put both sources together and make a split point
4916 && NEXT_INSN (seq
) != NULL_RTX
4917 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4918 && NONJUMP_INSN_P (seq
)
4919 && GET_CODE (PATTERN (seq
)) == SET
4920 && SET_DEST (PATTERN (seq
)) == reg
4921 && ! reg_mentioned_p (reg
,
4922 SET_SRC (PATTERN (seq
)))
4923 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4924 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4925 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4926 && memory_address_addr_space_p
4927 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4928 MEM_ADDR_SPACE (x
)))
4930 rtx src1
= SET_SRC (PATTERN (seq
));
4931 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4933 /* Replace the placeholder in SRC2 with SRC1. If we can
4934 find where in SRC2 it was placed, that can become our
4935 split point and we can replace this address with SRC2.
4936 Just try two obvious places. */
4938 src2
= replace_rtx (src2
, reg
, src1
);
4940 if (XEXP (src2
, 0) == src1
)
4941 split
= &XEXP (src2
, 0);
4942 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4943 && XEXP (XEXP (src2
, 0), 0) == src1
)
4944 split
= &XEXP (XEXP (src2
, 0), 0);
4948 SUBST (XEXP (x
, 0), src2
);
4953 /* If that didn't work, perhaps the first operand is complex and
4954 needs to be computed separately, so make a split point there.
4955 This will occur on machines that just support REG + CONST
4956 and have a constant moved through some previous computation. */
4958 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4959 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4960 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4961 return &XEXP (XEXP (x
, 0), 0);
4964 /* If we have a PLUS whose first operand is complex, try computing it
4965 separately by making a split there. */
4966 if (GET_CODE (XEXP (x
, 0)) == PLUS
4967 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4969 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4970 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4971 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4972 return &XEXP (XEXP (x
, 0), 0);
4976 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4977 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4978 we need to put the operand into a register. So split at that
4981 if (SET_DEST (x
) == cc0_rtx
4982 && GET_CODE (SET_SRC (x
)) != COMPARE
4983 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4984 && !OBJECT_P (SET_SRC (x
))
4985 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4986 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4987 return &SET_SRC (x
);
4989 /* See if we can split SET_SRC as it stands. */
4990 split
= find_split_point (&SET_SRC (x
), insn
, true);
4991 if (split
&& split
!= &SET_SRC (x
))
4994 /* See if we can split SET_DEST as it stands. */
4995 split
= find_split_point (&SET_DEST (x
), insn
, false);
4996 if (split
&& split
!= &SET_DEST (x
))
4999 /* See if this is a bitfield assignment with everything constant. If
5000 so, this is an IOR of an AND, so split it into that. */
5001 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5002 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_DEST (x
), 0)),
5004 && HWI_COMPUTABLE_MODE_P (inner_mode
)
5005 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
5006 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
5007 && CONST_INT_P (SET_SRC (x
))
5008 && ((INTVAL (XEXP (SET_DEST (x
), 1))
5009 + INTVAL (XEXP (SET_DEST (x
), 2)))
5010 <= GET_MODE_PRECISION (inner_mode
))
5011 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
5013 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
5014 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
5015 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
5016 rtx dest
= XEXP (SET_DEST (x
), 0);
5017 unsigned HOST_WIDE_INT mask
5018 = (HOST_WIDE_INT_1U
<< len
) - 1;
5021 if (BITS_BIG_ENDIAN
)
5022 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5024 or_mask
= gen_int_mode (src
<< pos
, inner_mode
);
5027 simplify_gen_binary (IOR
, inner_mode
, dest
, or_mask
));
5030 rtx negmask
= gen_int_mode (~(mask
<< pos
), inner_mode
);
5032 simplify_gen_binary (IOR
, inner_mode
,
5033 simplify_gen_binary (AND
, inner_mode
,
5038 SUBST (SET_DEST (x
), dest
);
5040 split
= find_split_point (&SET_SRC (x
), insn
, true);
5041 if (split
&& split
!= &SET_SRC (x
))
5045 /* Otherwise, see if this is an operation that we can split into two.
5046 If so, try to split that. */
5047 code
= GET_CODE (SET_SRC (x
));
5052 /* If we are AND'ing with a large constant that is only a single
5053 bit and the result is only being used in a context where we
5054 need to know if it is zero or nonzero, replace it with a bit
5055 extraction. This will avoid the large constant, which might
5056 have taken more than one insn to make. If the constant were
5057 not a valid argument to the AND but took only one insn to make,
5058 this is no worse, but if it took more than one insn, it will
5061 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5062 && REG_P (XEXP (SET_SRC (x
), 0))
5063 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
5064 && REG_P (SET_DEST (x
))
5065 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
5066 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
5067 && XEXP (*split
, 0) == SET_DEST (x
)
5068 && XEXP (*split
, 1) == const0_rtx
)
5070 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
5071 XEXP (SET_SRC (x
), 0),
5072 pos
, NULL_RTX
, 1, 1, 0, 0);
5073 if (extraction
!= 0)
5075 SUBST (SET_SRC (x
), extraction
);
5076 return find_split_point (loc
, insn
, false);
5082 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5083 is known to be on, this can be converted into a NEG of a shift. */
5084 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
5085 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
5086 && 1 <= (pos
= exact_log2
5087 (nonzero_bits (XEXP (SET_SRC (x
), 0),
5088 GET_MODE (XEXP (SET_SRC (x
), 0))))))
5090 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
5094 gen_rtx_LSHIFTRT (mode
,
5095 XEXP (SET_SRC (x
), 0),
5098 split
= find_split_point (&SET_SRC (x
), insn
, true);
5099 if (split
&& split
!= &SET_SRC (x
))
5105 inner
= XEXP (SET_SRC (x
), 0);
5107 /* We can't optimize if either mode is a partial integer
5108 mode as we don't know how many bits are significant
5110 if (!is_int_mode (GET_MODE (inner
), &inner_mode
)
5111 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5115 len
= GET_MODE_PRECISION (inner_mode
);
5121 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_SRC (x
), 0)),
5123 && CONST_INT_P (XEXP (SET_SRC (x
), 1))
5124 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5126 inner
= XEXP (SET_SRC (x
), 0);
5127 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5128 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5130 if (BITS_BIG_ENDIAN
)
5131 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5132 unsignedp
= (code
== ZERO_EXTRACT
);
5141 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
))
5142 && is_a
<scalar_int_mode
> (GET_MODE (SET_SRC (x
)), &mode
))
5144 /* For unsigned, we have a choice of a shift followed by an
5145 AND or two shifts. Use two shifts for field sizes where the
5146 constant might be too large. We assume here that we can
5147 always at least get 8-bit constants in an AND insn, which is
5148 true for every current RISC. */
5150 if (unsignedp
&& len
<= 8)
5152 unsigned HOST_WIDE_INT mask
5153 = (HOST_WIDE_INT_1U
<< len
) - 1;
5157 (mode
, gen_lowpart (mode
, inner
),
5159 gen_int_mode (mask
, mode
)));
5161 split
= find_split_point (&SET_SRC (x
), insn
, true);
5162 if (split
&& split
!= &SET_SRC (x
))
5169 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5170 gen_rtx_ASHIFT (mode
,
5171 gen_lowpart (mode
, inner
),
5172 GEN_INT (GET_MODE_PRECISION (mode
)
5174 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5176 split
= find_split_point (&SET_SRC (x
), insn
, true);
5177 if (split
&& split
!= &SET_SRC (x
))
5182 /* See if this is a simple operation with a constant as the second
5183 operand. It might be that this constant is out of range and hence
5184 could be used as a split point. */
5185 if (BINARY_P (SET_SRC (x
))
5186 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5187 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5188 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5189 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5190 return &XEXP (SET_SRC (x
), 1);
5192 /* Finally, see if this is a simple operation with its first operand
5193 not in a register. The operation might require this operand in a
5194 register, so return it as a split point. We can always do this
5195 because if the first operand were another operation, we would have
5196 already found it as a split point. */
5197 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5198 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5199 return &XEXP (SET_SRC (x
), 0);
5205 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5206 it is better to write this as (not (ior A B)) so we can split it.
5207 Similarly for IOR. */
5208 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5211 gen_rtx_NOT (GET_MODE (x
),
5212 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5214 XEXP (XEXP (x
, 0), 0),
5215 XEXP (XEXP (x
, 1), 0))));
5216 return find_split_point (loc
, insn
, set_src
);
5219 /* Many RISC machines have a large set of logical insns. If the
5220 second operand is a NOT, put it first so we will try to split the
5221 other operand first. */
5222 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5224 rtx tem
= XEXP (x
, 0);
5225 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5226 SUBST (XEXP (x
, 1), tem
);
5232 /* Canonicalization can produce (minus A (mult B C)), where C is a
5233 constant. It may be better to try splitting (plus (mult B -C) A)
5234 instead if this isn't a multiply by a power of two. */
5235 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5236 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5237 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5239 machine_mode mode
= GET_MODE (x
);
5240 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5241 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5242 SUBST (*loc
, gen_rtx_PLUS (mode
,
5244 XEXP (XEXP (x
, 1), 0),
5245 gen_int_mode (other_int
,
5248 return find_split_point (loc
, insn
, set_src
);
5251 /* Split at a multiply-accumulate instruction. However if this is
5252 the SET_SRC, we likely do not have such an instruction and it's
5253 worthless to try this split. */
5255 && (GET_CODE (XEXP (x
, 0)) == MULT
5256 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5257 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5264 /* Otherwise, select our actions depending on our rtx class. */
5265 switch (GET_RTX_CLASS (code
))
5267 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5269 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5274 case RTX_COMM_ARITH
:
5276 case RTX_COMM_COMPARE
:
5277 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5282 /* Some machines have (and (shift ...) ...) insns. If X is not
5283 an AND, but XEXP (X, 0) is, use it as our split point. */
5284 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5285 return &XEXP (x
, 0);
5287 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5293 /* Otherwise, we don't have a split point. */
5298 /* Throughout X, replace FROM with TO, and return the result.
5299 The result is TO if X is FROM;
5300 otherwise the result is X, but its contents may have been modified.
5301 If they were modified, a record was made in undobuf so that
5302 undo_all will (among other things) return X to its original state.
5304 If the number of changes necessary is too much to record to undo,
5305 the excess changes are not made, so the result is invalid.
5306 The changes already made can still be undone.
5307 undobuf.num_undo is incremented for such changes, so by testing that
5308 the caller can tell whether the result is valid.
5310 `n_occurrences' is incremented each time FROM is replaced.
5312 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5314 IN_COND is nonzero if we are at the top level of a condition.
5316 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5317 by copying if `n_occurrences' is nonzero. */
5320 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5322 enum rtx_code code
= GET_CODE (x
);
5323 machine_mode op0_mode
= VOIDmode
;
5328 /* Two expressions are equal if they are identical copies of a shared
5329 RTX or if they are both registers with the same register number
5332 #define COMBINE_RTX_EQUAL_P(X,Y) \
5334 || (REG_P (X) && REG_P (Y) \
5335 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5337 /* Do not substitute into clobbers of regs -- this will never result in
5339 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5342 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5345 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5348 /* If X and FROM are the same register but different modes, they
5349 will not have been seen as equal above. However, the log links code
5350 will make a LOG_LINKS entry for that case. If we do nothing, we
5351 will try to rerecognize our original insn and, when it succeeds,
5352 we will delete the feeding insn, which is incorrect.
5354 So force this insn not to match in this (rare) case. */
5355 if (! in_dest
&& code
== REG
&& REG_P (from
)
5356 && reg_overlap_mentioned_p (x
, from
))
5357 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5359 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5360 of which may contain things that can be combined. */
5361 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5364 /* It is possible to have a subexpression appear twice in the insn.
5365 Suppose that FROM is a register that appears within TO.
5366 Then, after that subexpression has been scanned once by `subst',
5367 the second time it is scanned, TO may be found. If we were
5368 to scan TO here, we would find FROM within it and create a
5369 self-referent rtl structure which is completely wrong. */
5370 if (COMBINE_RTX_EQUAL_P (x
, to
))
5373 /* Parallel asm_operands need special attention because all of the
5374 inputs are shared across the arms. Furthermore, unsharing the
5375 rtl results in recognition failures. Failure to handle this case
5376 specially can result in circular rtl.
5378 Solve this by doing a normal pass across the first entry of the
5379 parallel, and only processing the SET_DESTs of the subsequent
5382 if (code
== PARALLEL
5383 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5384 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5386 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5388 /* If this substitution failed, this whole thing fails. */
5389 if (GET_CODE (new_rtx
) == CLOBBER
5390 && XEXP (new_rtx
, 0) == const0_rtx
)
5393 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5395 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5397 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5400 && GET_CODE (dest
) != CC0
5401 && GET_CODE (dest
) != PC
)
5403 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5405 /* If this substitution failed, this whole thing fails. */
5406 if (GET_CODE (new_rtx
) == CLOBBER
5407 && XEXP (new_rtx
, 0) == const0_rtx
)
5410 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5416 len
= GET_RTX_LENGTH (code
);
5417 fmt
= GET_RTX_FORMAT (code
);
5419 /* We don't need to process a SET_DEST that is a register, CC0,
5420 or PC, so set up to skip this common case. All other cases
5421 where we want to suppress replacing something inside a
5422 SET_SRC are handled via the IN_DEST operand. */
5424 && (REG_P (SET_DEST (x
))
5425 || GET_CODE (SET_DEST (x
)) == CC0
5426 || GET_CODE (SET_DEST (x
)) == PC
))
5429 /* Trying to simplify the operands of a widening MULT is not likely
5430 to create RTL matching a machine insn. */
5432 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5433 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5434 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5435 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5436 && REG_P (XEXP (XEXP (x
, 0), 0))
5437 && REG_P (XEXP (XEXP (x
, 1), 0))
5442 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5445 op0_mode
= GET_MODE (XEXP (x
, 0));
5447 for (i
= 0; i
< len
; i
++)
5452 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5454 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5456 new_rtx
= (unique_copy
&& n_occurrences
5457 ? copy_rtx (to
) : to
);
5462 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5465 /* If this substitution failed, this whole thing
5467 if (GET_CODE (new_rtx
) == CLOBBER
5468 && XEXP (new_rtx
, 0) == const0_rtx
)
5472 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5475 else if (fmt
[i
] == 'e')
5477 /* If this is a register being set, ignore it. */
5478 new_rtx
= XEXP (x
, i
);
5481 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5483 || code
== STRICT_LOW_PART
))
5486 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5488 /* In general, don't install a subreg involving two
5489 modes not tieable. It can worsen register
5490 allocation, and can even make invalid reload
5491 insns, since the reg inside may need to be copied
5492 from in the outside mode, and that may be invalid
5493 if it is an fp reg copied in integer mode.
5495 We allow two exceptions to this: It is valid if
5496 it is inside another SUBREG and the mode of that
5497 SUBREG and the mode of the inside of TO is
5498 tieable and it is valid if X is a SET that copies
5501 if (GET_CODE (to
) == SUBREG
5502 && !targetm
.modes_tieable_p (GET_MODE (to
),
5503 GET_MODE (SUBREG_REG (to
)))
5504 && ! (code
== SUBREG
5505 && (targetm
.modes_tieable_p
5506 (GET_MODE (x
), GET_MODE (SUBREG_REG (to
)))))
5510 && XEXP (x
, 0) == cc0_rtx
))))
5511 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5515 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5516 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5519 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5521 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5525 /* If we are in a SET_DEST, suppress most cases unless we
5526 have gone inside a MEM, in which case we want to
5527 simplify the address. We assume here that things that
5528 are actually part of the destination have their inner
5529 parts in the first expression. This is true for SUBREG,
5530 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5531 things aside from REG and MEM that should appear in a
5533 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5535 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5536 || code
== ZERO_EXTRACT
))
5539 code
== IF_THEN_ELSE
&& i
== 0,
5542 /* If we found that we will have to reject this combination,
5543 indicate that by returning the CLOBBER ourselves, rather than
5544 an expression containing it. This will speed things up as
5545 well as prevent accidents where two CLOBBERs are considered
5546 to be equal, thus producing an incorrect simplification. */
5548 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5551 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5553 machine_mode mode
= GET_MODE (x
);
5555 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5556 GET_MODE (SUBREG_REG (x
)),
5559 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5561 else if (CONST_SCALAR_INT_P (new_rtx
)
5562 && GET_CODE (x
) == ZERO_EXTEND
)
5564 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5565 new_rtx
, GET_MODE (XEXP (x
, 0)));
5569 SUBST (XEXP (x
, i
), new_rtx
);
5574 /* Check if we are loading something from the constant pool via float
5575 extension; in this case we would undo compress_float_constant
5576 optimization and degenerate constant load to an immediate value. */
5577 if (GET_CODE (x
) == FLOAT_EXTEND
5578 && MEM_P (XEXP (x
, 0))
5579 && MEM_READONLY_P (XEXP (x
, 0)))
5581 rtx tmp
= avoid_constant_pool_reference (x
);
5586 /* Try to simplify X. If the simplification changed the code, it is likely
5587 that further simplification will help, so loop, but limit the number
5588 of repetitions that will be performed. */
5590 for (i
= 0; i
< 4; i
++)
5592 /* If X is sufficiently simple, don't bother trying to do anything
5594 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5595 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5597 if (GET_CODE (x
) == code
)
5600 code
= GET_CODE (x
);
5602 /* We no longer know the original mode of operand 0 since we
5603 have changed the form of X) */
5604 op0_mode
= VOIDmode
;
5610 /* If X is a commutative operation whose operands are not in the canonical
5611 order, use substitutions to swap them. */
5614 maybe_swap_commutative_operands (rtx x
)
5616 if (COMMUTATIVE_ARITH_P (x
)
5617 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5619 rtx temp
= XEXP (x
, 0);
5620 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5621 SUBST (XEXP (x
, 1), temp
);
5625 /* Simplify X, a piece of RTL. We just operate on the expression at the
5626 outer level; call `subst' to simplify recursively. Return the new
5629 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5630 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5634 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5637 enum rtx_code code
= GET_CODE (x
);
5638 machine_mode mode
= GET_MODE (x
);
5639 scalar_int_mode int_mode
;
5643 /* If this is a commutative operation, put a constant last and a complex
5644 expression first. We don't need to do this for comparisons here. */
5645 maybe_swap_commutative_operands (x
);
5647 /* Try to fold this expression in case we have constants that weren't
5650 switch (GET_RTX_CLASS (code
))
5653 if (op0_mode
== VOIDmode
)
5654 op0_mode
= GET_MODE (XEXP (x
, 0));
5655 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5658 case RTX_COMM_COMPARE
:
5660 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5661 if (cmp_mode
== VOIDmode
)
5663 cmp_mode
= GET_MODE (XEXP (x
, 1));
5664 if (cmp_mode
== VOIDmode
)
5665 cmp_mode
= op0_mode
;
5667 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5668 XEXP (x
, 0), XEXP (x
, 1));
5671 case RTX_COMM_ARITH
:
5673 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5675 case RTX_BITFIELD_OPS
:
5677 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5678 XEXP (x
, 1), XEXP (x
, 2));
5687 code
= GET_CODE (temp
);
5688 op0_mode
= VOIDmode
;
5689 mode
= GET_MODE (temp
);
5692 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5693 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5694 things. Check for cases where both arms are testing the same
5697 Don't do anything if all operands are very simple. */
5700 && ((!OBJECT_P (XEXP (x
, 0))
5701 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5702 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5703 || (!OBJECT_P (XEXP (x
, 1))
5704 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5705 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5707 && (!OBJECT_P (XEXP (x
, 0))
5708 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5709 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5711 rtx cond
, true_rtx
, false_rtx
;
5713 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5715 /* If everything is a comparison, what we have is highly unlikely
5716 to be simpler, so don't use it. */
5717 && ! (COMPARISON_P (x
)
5718 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5720 rtx cop1
= const0_rtx
;
5721 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5723 if (cond_code
== NE
&& COMPARISON_P (cond
))
5726 /* Simplify the alternative arms; this may collapse the true and
5727 false arms to store-flag values. Be careful to use copy_rtx
5728 here since true_rtx or false_rtx might share RTL with x as a
5729 result of the if_then_else_cond call above. */
5730 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5731 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5733 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5734 is unlikely to be simpler. */
5735 if (general_operand (true_rtx
, VOIDmode
)
5736 && general_operand (false_rtx
, VOIDmode
))
5738 enum rtx_code reversed
;
5740 /* Restarting if we generate a store-flag expression will cause
5741 us to loop. Just drop through in this case. */
5743 /* If the result values are STORE_FLAG_VALUE and zero, we can
5744 just make the comparison operation. */
5745 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5746 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5748 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5749 && ((reversed
= reversed_comparison_code_parts
5750 (cond_code
, cond
, cop1
, NULL
))
5752 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5755 /* Likewise, we can make the negate of a comparison operation
5756 if the result values are - STORE_FLAG_VALUE and zero. */
5757 else if (CONST_INT_P (true_rtx
)
5758 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5759 && false_rtx
== const0_rtx
)
5760 x
= simplify_gen_unary (NEG
, mode
,
5761 simplify_gen_relational (cond_code
,
5765 else if (CONST_INT_P (false_rtx
)
5766 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5767 && true_rtx
== const0_rtx
5768 && ((reversed
= reversed_comparison_code_parts
5769 (cond_code
, cond
, cop1
, NULL
))
5771 x
= simplify_gen_unary (NEG
, mode
,
5772 simplify_gen_relational (reversed
,
5777 return gen_rtx_IF_THEN_ELSE (mode
,
5778 simplify_gen_relational (cond_code
,
5783 true_rtx
, false_rtx
);
5785 code
= GET_CODE (x
);
5786 op0_mode
= VOIDmode
;
5791 /* First see if we can apply the inverse distributive law. */
5792 if (code
== PLUS
|| code
== MINUS
5793 || code
== AND
|| code
== IOR
|| code
== XOR
)
5795 x
= apply_distributive_law (x
);
5796 code
= GET_CODE (x
);
5797 op0_mode
= VOIDmode
;
5800 /* If CODE is an associative operation not otherwise handled, see if we
5801 can associate some operands. This can win if they are constants or
5802 if they are logically related (i.e. (a & b) & a). */
5803 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5804 || code
== AND
|| code
== IOR
|| code
== XOR
5805 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5806 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5807 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5809 if (GET_CODE (XEXP (x
, 0)) == code
)
5811 rtx other
= XEXP (XEXP (x
, 0), 0);
5812 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5813 rtx inner_op1
= XEXP (x
, 1);
5816 /* Make sure we pass the constant operand if any as the second
5817 one if this is a commutative operation. */
5818 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5819 std::swap (inner_op0
, inner_op1
);
5820 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5821 : code
== DIV
? MULT
5823 mode
, inner_op0
, inner_op1
);
5825 /* For commutative operations, try the other pair if that one
5827 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5829 other
= XEXP (XEXP (x
, 0), 1);
5830 inner
= simplify_binary_operation (code
, mode
,
5831 XEXP (XEXP (x
, 0), 0),
5836 return simplify_gen_binary (code
, mode
, other
, inner
);
5840 /* A little bit of algebraic simplification here. */
5844 /* Ensure that our address has any ASHIFTs converted to MULT in case
5845 address-recognizing predicates are called later. */
5846 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5847 SUBST (XEXP (x
, 0), temp
);
5851 if (op0_mode
== VOIDmode
)
5852 op0_mode
= GET_MODE (SUBREG_REG (x
));
5854 /* See if this can be moved to simplify_subreg. */
5855 if (CONSTANT_P (SUBREG_REG (x
))
5856 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5857 /* Don't call gen_lowpart if the inner mode
5858 is VOIDmode and we cannot simplify it, as SUBREG without
5859 inner mode is invalid. */
5860 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5861 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5862 return gen_lowpart (mode
, SUBREG_REG (x
));
5864 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5868 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5873 /* If op is known to have all lower bits zero, the result is zero. */
5874 scalar_int_mode int_mode
, int_op0_mode
;
5876 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5877 && is_a
<scalar_int_mode
> (op0_mode
, &int_op0_mode
)
5878 && (GET_MODE_PRECISION (int_mode
)
5879 < GET_MODE_PRECISION (int_op0_mode
))
5880 && (subreg_lowpart_offset (int_mode
, int_op0_mode
)
5882 && HWI_COMPUTABLE_MODE_P (int_op0_mode
)
5883 && (nonzero_bits (SUBREG_REG (x
), int_op0_mode
)
5884 & GET_MODE_MASK (int_mode
)) == 0)
5885 return CONST0_RTX (int_mode
);
5888 /* Don't change the mode of the MEM if that would change the meaning
5890 if (MEM_P (SUBREG_REG (x
))
5891 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5892 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5893 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5894 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5896 /* Note that we cannot do any narrowing for non-constants since
5897 we might have been counting on using the fact that some bits were
5898 zero. We now do this in the SET. */
5903 temp
= expand_compound_operation (XEXP (x
, 0));
5905 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5906 replaced by (lshiftrt X C). This will convert
5907 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5909 if (GET_CODE (temp
) == ASHIFTRT
5910 && CONST_INT_P (XEXP (temp
, 1))
5911 && INTVAL (XEXP (temp
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
5912 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5913 INTVAL (XEXP (temp
, 1)));
5915 /* If X has only a single bit that might be nonzero, say, bit I, convert
5916 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5917 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5918 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5919 or a SUBREG of one since we'd be making the expression more
5920 complex if it was just a register. */
5923 && ! (GET_CODE (temp
) == SUBREG
5924 && REG_P (SUBREG_REG (temp
)))
5925 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5926 && (i
= exact_log2 (nonzero_bits (temp
, int_mode
))) >= 0)
5928 rtx temp1
= simplify_shift_const
5929 (NULL_RTX
, ASHIFTRT
, int_mode
,
5930 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
, temp
,
5931 GET_MODE_PRECISION (int_mode
) - 1 - i
),
5932 GET_MODE_PRECISION (int_mode
) - 1 - i
);
5934 /* If all we did was surround TEMP with the two shifts, we
5935 haven't improved anything, so don't use it. Otherwise,
5936 we are better off with TEMP1. */
5937 if (GET_CODE (temp1
) != ASHIFTRT
5938 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5939 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5945 /* We can't handle truncation to a partial integer mode here
5946 because we don't know the real bitsize of the partial
5948 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5951 if (HWI_COMPUTABLE_MODE_P (mode
))
5953 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5954 GET_MODE_MASK (mode
), 0));
5956 /* We can truncate a constant value and return it. */
5957 if (CONST_INT_P (XEXP (x
, 0)))
5958 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5960 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5961 whose value is a comparison can be replaced with a subreg if
5962 STORE_FLAG_VALUE permits. */
5963 if (HWI_COMPUTABLE_MODE_P (mode
)
5964 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5965 && (temp
= get_last_value (XEXP (x
, 0)))
5966 && COMPARISON_P (temp
))
5967 return gen_lowpart (mode
, XEXP (x
, 0));
5971 /* (const (const X)) can become (const X). Do it this way rather than
5972 returning the inner CONST since CONST can be shared with a
5974 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5975 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5979 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5980 can add in an offset. find_split_point will split this address up
5981 again if it doesn't match. */
5982 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5983 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5988 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5989 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5990 bit-field and can be replaced by either a sign_extend or a
5991 sign_extract. The `and' may be a zero_extend and the two
5992 <c>, -<c> constants may be reversed. */
5993 if (GET_CODE (XEXP (x
, 0)) == XOR
5994 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5995 && CONST_INT_P (XEXP (x
, 1))
5996 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5997 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5998 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5999 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
6000 && HWI_COMPUTABLE_MODE_P (int_mode
)
6001 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
6002 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6003 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6004 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
6005 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
6006 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
6007 == (unsigned int) i
+ 1))))
6008 return simplify_shift_const
6009 (NULL_RTX
, ASHIFTRT
, int_mode
,
6010 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6011 XEXP (XEXP (XEXP (x
, 0), 0), 0),
6012 GET_MODE_PRECISION (int_mode
) - (i
+ 1)),
6013 GET_MODE_PRECISION (int_mode
) - (i
+ 1));
6015 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6016 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6017 the bitsize of the mode - 1. This allows simplification of
6018 "a = (b & 8) == 0;" */
6019 if (XEXP (x
, 1) == constm1_rtx
6020 && !REG_P (XEXP (x
, 0))
6021 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
6022 && REG_P (SUBREG_REG (XEXP (x
, 0))))
6023 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6024 && nonzero_bits (XEXP (x
, 0), int_mode
) == 1)
6025 return simplify_shift_const
6026 (NULL_RTX
, ASHIFTRT
, int_mode
,
6027 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6028 gen_rtx_XOR (int_mode
, XEXP (x
, 0),
6030 GET_MODE_PRECISION (int_mode
) - 1),
6031 GET_MODE_PRECISION (int_mode
) - 1);
6033 /* If we are adding two things that have no bits in common, convert
6034 the addition into an IOR. This will often be further simplified,
6035 for example in cases like ((a & 1) + (a & 2)), which can
6038 if (HWI_COMPUTABLE_MODE_P (mode
)
6039 && (nonzero_bits (XEXP (x
, 0), mode
)
6040 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
6042 /* Try to simplify the expression further. */
6043 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
6044 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
6046 /* If we could, great. If not, do not go ahead with the IOR
6047 replacement, since PLUS appears in many special purpose
6048 address arithmetic instructions. */
6049 if (GET_CODE (temp
) != CLOBBER
6050 && (GET_CODE (temp
) != IOR
6051 || ((XEXP (temp
, 0) != XEXP (x
, 0)
6052 || XEXP (temp
, 1) != XEXP (x
, 1))
6053 && (XEXP (temp
, 0) != XEXP (x
, 1)
6054 || XEXP (temp
, 1) != XEXP (x
, 0)))))
6058 /* Canonicalize x + x into x << 1. */
6059 if (GET_MODE_CLASS (mode
) == MODE_INT
6060 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
6061 && !side_effects_p (XEXP (x
, 0)))
6062 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
6067 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6068 (and <foo> (const_int pow2-1)) */
6069 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6070 && GET_CODE (XEXP (x
, 1)) == AND
6071 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
6072 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
6073 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6074 return simplify_and_const_int (NULL_RTX
, int_mode
, XEXP (x
, 0),
6075 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
6079 /* If we have (mult (plus A B) C), apply the distributive law and then
6080 the inverse distributive law to see if things simplify. This
6081 occurs mostly in addresses, often when unrolling loops. */
6083 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
6085 rtx result
= distribute_and_simplify_rtx (x
, 0);
6090 /* Try simplify a*(b/c) as (a*b)/c. */
6091 if (FLOAT_MODE_P (mode
) && flag_associative_math
6092 && GET_CODE (XEXP (x
, 0)) == DIV
)
6094 rtx tem
= simplify_binary_operation (MULT
, mode
,
6095 XEXP (XEXP (x
, 0), 0),
6098 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
6103 /* If this is a divide by a power of two, treat it as a shift if
6104 its first operand is a shift. */
6105 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6106 && CONST_INT_P (XEXP (x
, 1))
6107 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6108 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6109 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6110 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6111 || GET_CODE (XEXP (x
, 0)) == ROTATE
6112 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6113 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, int_mode
,
6118 case GT
: case GTU
: case GE
: case GEU
:
6119 case LT
: case LTU
: case LE
: case LEU
:
6120 case UNEQ
: case LTGT
:
6121 case UNGT
: case UNGE
:
6122 case UNLT
: case UNLE
:
6123 case UNORDERED
: case ORDERED
:
6124 /* If the first operand is a condition code, we can't do anything
6126 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6127 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
6128 && ! CC0_P (XEXP (x
, 0))))
6130 rtx op0
= XEXP (x
, 0);
6131 rtx op1
= XEXP (x
, 1);
6132 enum rtx_code new_code
;
6134 if (GET_CODE (op0
) == COMPARE
)
6135 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6137 /* Simplify our comparison, if possible. */
6138 new_code
= simplify_comparison (code
, &op0
, &op1
);
6140 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6141 if only the low-order bit is possibly nonzero in X (such as when
6142 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6143 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6144 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6147 Remove any ZERO_EXTRACT we made when thinking this was a
6148 comparison. It may now be simpler to use, e.g., an AND. If a
6149 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6150 the call to make_compound_operation in the SET case.
6152 Don't apply these optimizations if the caller would
6153 prefer a comparison rather than a value.
6154 E.g., for the condition in an IF_THEN_ELSE most targets need
6155 an explicit comparison. */
6160 else if (STORE_FLAG_VALUE
== 1
6162 && is_int_mode (mode
, &int_mode
)
6163 && op1
== const0_rtx
6164 && int_mode
== GET_MODE (op0
)
6165 && nonzero_bits (op0
, int_mode
) == 1)
6166 return gen_lowpart (int_mode
,
6167 expand_compound_operation (op0
));
6169 else if (STORE_FLAG_VALUE
== 1
6171 && is_int_mode (mode
, &int_mode
)
6172 && op1
== const0_rtx
6173 && int_mode
== GET_MODE (op0
)
6174 && (num_sign_bit_copies (op0
, int_mode
)
6175 == GET_MODE_PRECISION (int_mode
)))
6177 op0
= expand_compound_operation (op0
);
6178 return simplify_gen_unary (NEG
, int_mode
,
6179 gen_lowpart (int_mode
, op0
),
6183 else if (STORE_FLAG_VALUE
== 1
6185 && is_int_mode (mode
, &int_mode
)
6186 && op1
== const0_rtx
6187 && int_mode
== GET_MODE (op0
)
6188 && nonzero_bits (op0
, int_mode
) == 1)
6190 op0
= expand_compound_operation (op0
);
6191 return simplify_gen_binary (XOR
, int_mode
,
6192 gen_lowpart (int_mode
, op0
),
6196 else if (STORE_FLAG_VALUE
== 1
6198 && is_int_mode (mode
, &int_mode
)
6199 && op1
== const0_rtx
6200 && int_mode
== GET_MODE (op0
)
6201 && (num_sign_bit_copies (op0
, int_mode
)
6202 == GET_MODE_PRECISION (int_mode
)))
6204 op0
= expand_compound_operation (op0
);
6205 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), 1);
6208 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6213 else if (STORE_FLAG_VALUE
== -1
6215 && is_int_mode (mode
, &int_mode
)
6216 && op1
== const0_rtx
6217 && int_mode
== GET_MODE (op0
)
6218 && (num_sign_bit_copies (op0
, int_mode
)
6219 == GET_MODE_PRECISION (int_mode
)))
6220 return gen_lowpart (int_mode
, expand_compound_operation (op0
));
6222 else if (STORE_FLAG_VALUE
== -1
6224 && is_int_mode (mode
, &int_mode
)
6225 && op1
== const0_rtx
6226 && int_mode
== GET_MODE (op0
)
6227 && nonzero_bits (op0
, int_mode
) == 1)
6229 op0
= expand_compound_operation (op0
);
6230 return simplify_gen_unary (NEG
, int_mode
,
6231 gen_lowpart (int_mode
, op0
),
6235 else if (STORE_FLAG_VALUE
== -1
6237 && is_int_mode (mode
, &int_mode
)
6238 && op1
== const0_rtx
6239 && int_mode
== GET_MODE (op0
)
6240 && (num_sign_bit_copies (op0
, int_mode
)
6241 == GET_MODE_PRECISION (int_mode
)))
6243 op0
= expand_compound_operation (op0
);
6244 return simplify_gen_unary (NOT
, int_mode
,
6245 gen_lowpart (int_mode
, op0
),
6249 /* If X is 0/1, (eq X 0) is X-1. */
6250 else if (STORE_FLAG_VALUE
== -1
6252 && is_int_mode (mode
, &int_mode
)
6253 && op1
== const0_rtx
6254 && int_mode
== GET_MODE (op0
)
6255 && nonzero_bits (op0
, int_mode
) == 1)
6257 op0
= expand_compound_operation (op0
);
6258 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), -1);
6261 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6262 one bit that might be nonzero, we can convert (ne x 0) to
6263 (ashift x c) where C puts the bit in the sign bit. Remove any
6264 AND with STORE_FLAG_VALUE when we are done, since we are only
6265 going to test the sign bit. */
6267 && is_int_mode (mode
, &int_mode
)
6268 && HWI_COMPUTABLE_MODE_P (int_mode
)
6269 && val_signbit_p (int_mode
, STORE_FLAG_VALUE
)
6270 && op1
== const0_rtx
6271 && int_mode
== GET_MODE (op0
)
6272 && (i
= exact_log2 (nonzero_bits (op0
, int_mode
))) >= 0)
6274 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6275 expand_compound_operation (op0
),
6276 GET_MODE_PRECISION (int_mode
) - 1 - i
);
6277 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6283 /* If the code changed, return a whole new comparison.
6284 We also need to avoid using SUBST in cases where
6285 simplify_comparison has widened a comparison with a CONST_INT,
6286 since in that case the wider CONST_INT may fail the sanity
6287 checks in do_SUBST. */
6288 if (new_code
!= code
6289 || (CONST_INT_P (op1
)
6290 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6291 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6292 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6294 /* Otherwise, keep this operation, but maybe change its operands.
6295 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6296 SUBST (XEXP (x
, 0), op0
);
6297 SUBST (XEXP (x
, 1), op1
);
6302 return simplify_if_then_else (x
);
6308 /* If we are processing SET_DEST, we are done. */
6312 return expand_compound_operation (x
);
6315 return simplify_set (x
);
6319 return simplify_logical (x
);
6326 /* If this is a shift by a constant amount, simplify it. */
6327 if (CONST_INT_P (XEXP (x
, 1)))
6328 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6329 INTVAL (XEXP (x
, 1)));
6331 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6333 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6335 << exact_log2 (GET_MODE_UNIT_BITSIZE
6348 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6351 simplify_if_then_else (rtx x
)
6353 machine_mode mode
= GET_MODE (x
);
6354 rtx cond
= XEXP (x
, 0);
6355 rtx true_rtx
= XEXP (x
, 1);
6356 rtx false_rtx
= XEXP (x
, 2);
6357 enum rtx_code true_code
= GET_CODE (cond
);
6358 int comparison_p
= COMPARISON_P (cond
);
6361 enum rtx_code false_code
;
6363 scalar_int_mode int_mode
, inner_mode
;
6365 /* Simplify storing of the truth value. */
6366 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6367 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6368 XEXP (cond
, 0), XEXP (cond
, 1));
6370 /* Also when the truth value has to be reversed. */
6372 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6373 && (reversed
= reversed_comparison (cond
, mode
)))
6376 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6377 in it is being compared against certain values. Get the true and false
6378 comparisons and see if that says anything about the value of each arm. */
6381 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6383 && REG_P (XEXP (cond
, 0)))
6386 rtx from
= XEXP (cond
, 0);
6387 rtx true_val
= XEXP (cond
, 1);
6388 rtx false_val
= true_val
;
6391 /* If FALSE_CODE is EQ, swap the codes and arms. */
6393 if (false_code
== EQ
)
6395 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6396 std::swap (true_rtx
, false_rtx
);
6399 scalar_int_mode from_mode
;
6400 if (is_a
<scalar_int_mode
> (GET_MODE (from
), &from_mode
))
6402 /* If we are comparing against zero and the expression being
6403 tested has only a single bit that might be nonzero, that is
6404 its value when it is not equal to zero. Similarly if it is
6405 known to be -1 or 0. */
6407 && true_val
== const0_rtx
6408 && pow2p_hwi (nzb
= nonzero_bits (from
, from_mode
)))
6411 false_val
= gen_int_mode (nzb
, from_mode
);
6413 else if (true_code
== EQ
6414 && true_val
== const0_rtx
6415 && (num_sign_bit_copies (from
, from_mode
)
6416 == GET_MODE_PRECISION (from_mode
)))
6419 false_val
= constm1_rtx
;
6423 /* Now simplify an arm if we know the value of the register in the
6424 branch and it is used in the arm. Be careful due to the potential
6425 of locally-shared RTL. */
6427 if (reg_mentioned_p (from
, true_rtx
))
6428 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6430 pc_rtx
, pc_rtx
, 0, 0, 0);
6431 if (reg_mentioned_p (from
, false_rtx
))
6432 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6434 pc_rtx
, pc_rtx
, 0, 0, 0);
6436 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6437 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6439 true_rtx
= XEXP (x
, 1);
6440 false_rtx
= XEXP (x
, 2);
6441 true_code
= GET_CODE (cond
);
6444 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6445 reversed, do so to avoid needing two sets of patterns for
6446 subtract-and-branch insns. Similarly if we have a constant in the true
6447 arm, the false arm is the same as the first operand of the comparison, or
6448 the false arm is more complicated than the true arm. */
6451 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6452 && (true_rtx
== pc_rtx
6453 || (CONSTANT_P (true_rtx
)
6454 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6455 || true_rtx
== const0_rtx
6456 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6457 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6458 && !OBJECT_P (false_rtx
))
6459 || reg_mentioned_p (true_rtx
, false_rtx
)
6460 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6462 true_code
= reversed_comparison_code (cond
, NULL
);
6463 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6464 SUBST (XEXP (x
, 1), false_rtx
);
6465 SUBST (XEXP (x
, 2), true_rtx
);
6467 std::swap (true_rtx
, false_rtx
);
6470 /* It is possible that the conditional has been simplified out. */
6471 true_code
= GET_CODE (cond
);
6472 comparison_p
= COMPARISON_P (cond
);
6475 /* If the two arms are identical, we don't need the comparison. */
6477 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6480 /* Convert a == b ? b : a to "a". */
6481 if (true_code
== EQ
&& ! side_effects_p (cond
)
6482 && !HONOR_NANS (mode
)
6483 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6484 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6486 else if (true_code
== NE
&& ! side_effects_p (cond
)
6487 && !HONOR_NANS (mode
)
6488 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6489 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6492 /* Look for cases where we have (abs x) or (neg (abs X)). */
6494 if (GET_MODE_CLASS (mode
) == MODE_INT
6496 && XEXP (cond
, 1) == const0_rtx
6497 && GET_CODE (false_rtx
) == NEG
6498 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6499 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6500 && ! side_effects_p (true_rtx
))
6505 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6509 simplify_gen_unary (NEG
, mode
,
6510 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6516 /* Look for MIN or MAX. */
6518 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6520 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6521 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6522 && ! side_effects_p (cond
))
6527 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6530 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6533 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6536 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6541 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6542 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6543 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6544 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6545 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6546 neither 1 or -1, but it isn't worth checking for. */
6548 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6550 && is_int_mode (mode
, &int_mode
)
6551 && ! side_effects_p (x
))
6553 rtx t
= make_compound_operation (true_rtx
, SET
);
6554 rtx f
= make_compound_operation (false_rtx
, SET
);
6555 rtx cond_op0
= XEXP (cond
, 0);
6556 rtx cond_op1
= XEXP (cond
, 1);
6557 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6558 scalar_int_mode m
= int_mode
;
6559 rtx z
= 0, c1
= NULL_RTX
;
6561 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6562 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6563 || GET_CODE (t
) == ASHIFT
6564 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6565 && rtx_equal_p (XEXP (t
, 0), f
))
6566 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6568 /* If an identity-zero op is commutative, check whether there
6569 would be a match if we swapped the operands. */
6570 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6571 || GET_CODE (t
) == XOR
)
6572 && rtx_equal_p (XEXP (t
, 1), f
))
6573 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6574 else if (GET_CODE (t
) == SIGN_EXTEND
6575 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6576 && (GET_CODE (XEXP (t
, 0)) == PLUS
6577 || GET_CODE (XEXP (t
, 0)) == MINUS
6578 || GET_CODE (XEXP (t
, 0)) == IOR
6579 || GET_CODE (XEXP (t
, 0)) == XOR
6580 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6581 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6582 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6583 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6584 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6585 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6586 && (num_sign_bit_copies (f
, GET_MODE (f
))
6588 (GET_MODE_PRECISION (int_mode
)
6589 - GET_MODE_PRECISION (inner_mode
))))
6591 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6592 extend_op
= SIGN_EXTEND
;
6595 else if (GET_CODE (t
) == SIGN_EXTEND
6596 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6597 && (GET_CODE (XEXP (t
, 0)) == PLUS
6598 || GET_CODE (XEXP (t
, 0)) == IOR
6599 || GET_CODE (XEXP (t
, 0)) == XOR
)
6600 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6601 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6602 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6603 && (num_sign_bit_copies (f
, GET_MODE (f
))
6605 (GET_MODE_PRECISION (int_mode
)
6606 - GET_MODE_PRECISION (inner_mode
))))
6608 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6609 extend_op
= SIGN_EXTEND
;
6612 else if (GET_CODE (t
) == ZERO_EXTEND
6613 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6614 && (GET_CODE (XEXP (t
, 0)) == PLUS
6615 || GET_CODE (XEXP (t
, 0)) == MINUS
6616 || GET_CODE (XEXP (t
, 0)) == IOR
6617 || GET_CODE (XEXP (t
, 0)) == XOR
6618 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6619 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6620 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6621 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6622 && HWI_COMPUTABLE_MODE_P (int_mode
)
6623 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6624 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6625 && ((nonzero_bits (f
, GET_MODE (f
))
6626 & ~GET_MODE_MASK (inner_mode
))
6629 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6630 extend_op
= ZERO_EXTEND
;
6633 else if (GET_CODE (t
) == ZERO_EXTEND
6634 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6635 && (GET_CODE (XEXP (t
, 0)) == PLUS
6636 || GET_CODE (XEXP (t
, 0)) == IOR
6637 || GET_CODE (XEXP (t
, 0)) == XOR
)
6638 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6639 && HWI_COMPUTABLE_MODE_P (int_mode
)
6640 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6641 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6642 && ((nonzero_bits (f
, GET_MODE (f
))
6643 & ~GET_MODE_MASK (inner_mode
))
6646 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6647 extend_op
= ZERO_EXTEND
;
6653 machine_mode cm
= m
;
6654 if ((op
== ASHIFT
|| op
== LSHIFTRT
|| op
== ASHIFTRT
)
6655 && GET_MODE (c1
) != VOIDmode
)
6657 temp
= subst (simplify_gen_relational (true_code
, cm
, VOIDmode
,
6658 cond_op0
, cond_op1
),
6659 pc_rtx
, pc_rtx
, 0, 0, 0);
6660 temp
= simplify_gen_binary (MULT
, cm
, temp
,
6661 simplify_gen_binary (MULT
, cm
, c1
,
6663 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6664 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6666 if (extend_op
!= UNKNOWN
)
6667 temp
= simplify_gen_unary (extend_op
, int_mode
, temp
, m
);
6673 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6674 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6675 negation of a single bit, we can convert this operation to a shift. We
6676 can actually do this more generally, but it doesn't seem worth it. */
6679 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6680 && XEXP (cond
, 1) == const0_rtx
6681 && false_rtx
== const0_rtx
6682 && CONST_INT_P (true_rtx
)
6683 && ((1 == nonzero_bits (XEXP (cond
, 0), int_mode
)
6684 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6685 || ((num_sign_bit_copies (XEXP (cond
, 0), int_mode
)
6686 == GET_MODE_PRECISION (int_mode
))
6687 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6689 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6690 gen_lowpart (int_mode
, XEXP (cond
, 0)), i
);
6692 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6693 non-zero bit in A is C1. */
6694 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6695 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6696 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6697 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (cond
, 0)), &inner_mode
)
6698 && (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))
6699 == nonzero_bits (XEXP (cond
, 0), inner_mode
)
6700 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))) >= 0)
6702 rtx val
= XEXP (cond
, 0);
6703 if (inner_mode
== int_mode
)
6705 else if (GET_MODE_PRECISION (inner_mode
) < GET_MODE_PRECISION (int_mode
))
6706 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, val
, inner_mode
);
6712 /* Simplify X, a SET expression. Return the new expression. */
6715 simplify_set (rtx x
)
6717 rtx src
= SET_SRC (x
);
6718 rtx dest
= SET_DEST (x
);
6720 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6721 rtx_insn
*other_insn
;
6723 scalar_int_mode int_mode
;
6725 /* (set (pc) (return)) gets written as (return). */
6726 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6729 /* Now that we know for sure which bits of SRC we are using, see if we can
6730 simplify the expression for the object knowing that we only need the
6733 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6735 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6736 SUBST (SET_SRC (x
), src
);
6739 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6740 the comparison result and try to simplify it unless we already have used
6741 undobuf.other_insn. */
6742 if ((GET_MODE_CLASS (mode
) == MODE_CC
6743 || GET_CODE (src
) == COMPARE
6745 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6746 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6747 && COMPARISON_P (*cc_use
)
6748 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6750 enum rtx_code old_code
= GET_CODE (*cc_use
);
6751 enum rtx_code new_code
;
6753 int other_changed
= 0;
6754 rtx inner_compare
= NULL_RTX
;
6755 machine_mode compare_mode
= GET_MODE (dest
);
6757 if (GET_CODE (src
) == COMPARE
)
6759 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6760 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6762 inner_compare
= op0
;
6763 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6767 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6769 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6772 new_code
= old_code
;
6773 else if (!CONSTANT_P (tmp
))
6775 new_code
= GET_CODE (tmp
);
6776 op0
= XEXP (tmp
, 0);
6777 op1
= XEXP (tmp
, 1);
6781 rtx pat
= PATTERN (other_insn
);
6782 undobuf
.other_insn
= other_insn
;
6783 SUBST (*cc_use
, tmp
);
6785 /* Attempt to simplify CC user. */
6786 if (GET_CODE (pat
) == SET
)
6788 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6789 if (new_rtx
!= NULL_RTX
)
6790 SUBST (SET_SRC (pat
), new_rtx
);
6793 /* Convert X into a no-op move. */
6794 SUBST (SET_DEST (x
), pc_rtx
);
6795 SUBST (SET_SRC (x
), pc_rtx
);
6799 /* Simplify our comparison, if possible. */
6800 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6802 #ifdef SELECT_CC_MODE
6803 /* If this machine has CC modes other than CCmode, check to see if we
6804 need to use a different CC mode here. */
6805 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6806 compare_mode
= GET_MODE (op0
);
6807 else if (inner_compare
6808 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6809 && new_code
== old_code
6810 && op0
== XEXP (inner_compare
, 0)
6811 && op1
== XEXP (inner_compare
, 1))
6812 compare_mode
= GET_MODE (inner_compare
);
6814 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6816 /* If the mode changed, we have to change SET_DEST, the mode in the
6817 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6818 a hard register, just build new versions with the proper mode. If it
6819 is a pseudo, we lose unless it is only time we set the pseudo, in
6820 which case we can safely change its mode. */
6821 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6823 if (can_change_dest_mode (dest
, 0, compare_mode
))
6825 unsigned int regno
= REGNO (dest
);
6828 if (regno
< FIRST_PSEUDO_REGISTER
)
6829 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6832 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6833 new_dest
= regno_reg_rtx
[regno
];
6836 SUBST (SET_DEST (x
), new_dest
);
6837 SUBST (XEXP (*cc_use
, 0), new_dest
);
6843 #endif /* SELECT_CC_MODE */
6845 /* If the code changed, we have to build a new comparison in
6846 undobuf.other_insn. */
6847 if (new_code
!= old_code
)
6849 int other_changed_previously
= other_changed
;
6850 unsigned HOST_WIDE_INT mask
;
6851 rtx old_cc_use
= *cc_use
;
6853 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6857 /* If the only change we made was to change an EQ into an NE or
6858 vice versa, OP0 has only one bit that might be nonzero, and OP1
6859 is zero, check if changing the user of the condition code will
6860 produce a valid insn. If it won't, we can keep the original code
6861 in that insn by surrounding our operation with an XOR. */
6863 if (((old_code
== NE
&& new_code
== EQ
)
6864 || (old_code
== EQ
&& new_code
== NE
))
6865 && ! other_changed_previously
&& op1
== const0_rtx
6866 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6867 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6869 rtx pat
= PATTERN (other_insn
), note
= 0;
6871 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6872 && ! check_asm_operands (pat
)))
6874 *cc_use
= old_cc_use
;
6877 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6885 undobuf
.other_insn
= other_insn
;
6887 /* Don't generate a compare of a CC with 0, just use that CC. */
6888 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6890 SUBST (SET_SRC (x
), op0
);
6893 /* Otherwise, if we didn't previously have the same COMPARE we
6894 want, create it from scratch. */
6895 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6896 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6898 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6904 /* Get SET_SRC in a form where we have placed back any
6905 compound expressions. Then do the checks below. */
6906 src
= make_compound_operation (src
, SET
);
6907 SUBST (SET_SRC (x
), src
);
6910 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6911 and X being a REG or (subreg (reg)), we may be able to convert this to
6912 (set (subreg:m2 x) (op)).
6914 We can always do this if M1 is narrower than M2 because that means that
6915 we only care about the low bits of the result.
6917 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6918 perform a narrower operation than requested since the high-order bits will
6919 be undefined. On machine where it is defined, this transformation is safe
6920 as long as M1 and M2 have the same number of words. */
6922 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6923 && !OBJECT_P (SUBREG_REG (src
))
6924 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6926 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6927 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6928 && (WORD_REGISTER_OPERATIONS
|| !paradoxical_subreg_p (src
))
6929 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6930 && !REG_CAN_CHANGE_MODE_P (REGNO (dest
),
6931 GET_MODE (SUBREG_REG (src
)),
6934 || (GET_CODE (dest
) == SUBREG
6935 && REG_P (SUBREG_REG (dest
)))))
6937 SUBST (SET_DEST (x
),
6938 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6940 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6942 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6945 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6948 && partial_subreg_p (src
)
6949 && subreg_lowpart_p (src
))
6951 rtx inner
= SUBREG_REG (src
);
6952 machine_mode inner_mode
= GET_MODE (inner
);
6954 /* Here we make sure that we don't have a sign bit on. */
6955 if (val_signbit_known_clear_p (GET_MODE (src
),
6956 nonzero_bits (inner
, inner_mode
)))
6958 SUBST (SET_SRC (x
), inner
);
6963 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6964 would require a paradoxical subreg. Replace the subreg with a
6965 zero_extend to avoid the reload that would otherwise be required.
6966 Don't do this for vector modes, as the transformation is incorrect. */
6968 enum rtx_code extend_op
;
6969 if (paradoxical_subreg_p (src
)
6970 && MEM_P (SUBREG_REG (src
))
6971 && !VECTOR_MODE_P (GET_MODE (src
))
6972 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
6975 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
6980 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6981 are comparing an item known to be 0 or -1 against 0, use a logical
6982 operation instead. Check for one of the arms being an IOR of the other
6983 arm with some value. We compute three terms to be IOR'ed together. In
6984 practice, at most two will be nonzero. Then we do the IOR's. */
6986 if (GET_CODE (dest
) != PC
6987 && GET_CODE (src
) == IF_THEN_ELSE
6988 && is_int_mode (GET_MODE (src
), &int_mode
)
6989 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6990 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6991 && int_mode
== GET_MODE (XEXP (XEXP (src
, 0), 0))
6992 && (!HAVE_conditional_move
6993 || ! can_conditionally_move_p (int_mode
))
6994 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0), int_mode
)
6995 == GET_MODE_PRECISION (int_mode
))
6996 && ! side_effects_p (src
))
6998 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6999 ? XEXP (src
, 1) : XEXP (src
, 2));
7000 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7001 ? XEXP (src
, 2) : XEXP (src
, 1));
7002 rtx term1
= const0_rtx
, term2
, term3
;
7004 if (GET_CODE (true_rtx
) == IOR
7005 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
7006 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
7007 else if (GET_CODE (true_rtx
) == IOR
7008 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
7009 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
7010 else if (GET_CODE (false_rtx
) == IOR
7011 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
7012 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
7013 else if (GET_CODE (false_rtx
) == IOR
7014 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
7015 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
7017 term2
= simplify_gen_binary (AND
, int_mode
,
7018 XEXP (XEXP (src
, 0), 0), true_rtx
);
7019 term3
= simplify_gen_binary (AND
, int_mode
,
7020 simplify_gen_unary (NOT
, int_mode
,
7021 XEXP (XEXP (src
, 0), 0),
7026 simplify_gen_binary (IOR
, int_mode
,
7027 simplify_gen_binary (IOR
, int_mode
,
7034 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7035 whole thing fail. */
7036 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
7038 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
7041 /* Convert this into a field assignment operation, if possible. */
7042 return make_field_assignment (x
);
7045 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7049 simplify_logical (rtx x
)
7051 rtx op0
= XEXP (x
, 0);
7052 rtx op1
= XEXP (x
, 1);
7053 scalar_int_mode mode
;
7055 switch (GET_CODE (x
))
7058 /* We can call simplify_and_const_int only if we don't lose
7059 any (sign) bits when converting INTVAL (op1) to
7060 "unsigned HOST_WIDE_INT". */
7061 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
7062 && CONST_INT_P (op1
)
7063 && (HWI_COMPUTABLE_MODE_P (mode
)
7064 || INTVAL (op1
) > 0))
7066 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
7067 if (GET_CODE (x
) != AND
)
7074 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7075 apply the distributive law and then the inverse distributive
7076 law to see if things simplify. */
7077 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
7079 rtx result
= distribute_and_simplify_rtx (x
, 0);
7083 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
7085 rtx result
= distribute_and_simplify_rtx (x
, 1);
7092 /* If we have (ior (and A B) C), apply the distributive law and then
7093 the inverse distributive law to see if things simplify. */
7095 if (GET_CODE (op0
) == AND
)
7097 rtx result
= distribute_and_simplify_rtx (x
, 0);
7102 if (GET_CODE (op1
) == AND
)
7104 rtx result
= distribute_and_simplify_rtx (x
, 1);
7117 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7118 operations" because they can be replaced with two more basic operations.
7119 ZERO_EXTEND is also considered "compound" because it can be replaced with
7120 an AND operation, which is simpler, though only one operation.
7122 The function expand_compound_operation is called with an rtx expression
7123 and will convert it to the appropriate shifts and AND operations,
7124 simplifying at each stage.
7126 The function make_compound_operation is called to convert an expression
7127 consisting of shifts and ANDs into the equivalent compound expression.
7128 It is the inverse of this function, loosely speaking. */
7131 expand_compound_operation (rtx x
)
7133 unsigned HOST_WIDE_INT pos
= 0, len
;
7135 unsigned int modewidth
;
7137 scalar_int_mode inner_mode
;
7139 switch (GET_CODE (x
))
7145 /* We can't necessarily use a const_int for a multiword mode;
7146 it depends on implicitly extending the value.
7147 Since we don't know the right way to extend it,
7148 we can't tell whether the implicit way is right.
7150 Even for a mode that is no wider than a const_int,
7151 we can't win, because we need to sign extend one of its bits through
7152 the rest of it, and we don't know which bit. */
7153 if (CONST_INT_P (XEXP (x
, 0)))
7156 /* Reject modes that aren't scalar integers because turning vector
7157 or complex modes into shifts causes problems. */
7158 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7161 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7162 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7163 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7164 reloaded. If not for that, MEM's would very rarely be safe.
7166 Reject modes bigger than a word, because we might not be able
7167 to reference a two-register group starting with an arbitrary register
7168 (and currently gen_lowpart might crash for a SUBREG). */
7170 if (GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7173 len
= GET_MODE_PRECISION (inner_mode
);
7174 /* If the inner object has VOIDmode (the only way this can happen
7175 is if it is an ASM_OPERANDS), we can't do anything since we don't
7176 know how much masking to do. */
7188 /* If the operand is a CLOBBER, just return it. */
7189 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7192 if (!CONST_INT_P (XEXP (x
, 1))
7193 || !CONST_INT_P (XEXP (x
, 2)))
7196 /* Reject modes that aren't scalar integers because turning vector
7197 or complex modes into shifts causes problems. */
7198 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7201 len
= INTVAL (XEXP (x
, 1));
7202 pos
= INTVAL (XEXP (x
, 2));
7204 /* This should stay within the object being extracted, fail otherwise. */
7205 if (len
+ pos
> GET_MODE_PRECISION (inner_mode
))
7208 if (BITS_BIG_ENDIAN
)
7209 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
7217 /* We've rejected non-scalar operations by now. */
7218 scalar_int_mode mode
= as_a
<scalar_int_mode
> (GET_MODE (x
));
7220 /* Convert sign extension to zero extension, if we know that the high
7221 bit is not set, as this is easier to optimize. It will be converted
7222 back to cheaper alternative in make_extraction. */
7223 if (GET_CODE (x
) == SIGN_EXTEND
7224 && HWI_COMPUTABLE_MODE_P (mode
)
7225 && ((nonzero_bits (XEXP (x
, 0), inner_mode
)
7226 & ~(((unsigned HOST_WIDE_INT
) GET_MODE_MASK (inner_mode
)) >> 1))
7229 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7230 rtx temp2
= expand_compound_operation (temp
);
7232 /* Make sure this is a profitable operation. */
7233 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7234 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7236 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7237 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7243 /* We can optimize some special cases of ZERO_EXTEND. */
7244 if (GET_CODE (x
) == ZERO_EXTEND
)
7246 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7247 know that the last value didn't have any inappropriate bits
7249 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7250 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7251 && HWI_COMPUTABLE_MODE_P (mode
)
7252 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
)
7253 & ~GET_MODE_MASK (inner_mode
)) == 0)
7254 return XEXP (XEXP (x
, 0), 0);
7256 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7257 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7258 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7259 && subreg_lowpart_p (XEXP (x
, 0))
7260 && HWI_COMPUTABLE_MODE_P (mode
)
7261 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), mode
)
7262 & ~GET_MODE_MASK (inner_mode
)) == 0)
7263 return SUBREG_REG (XEXP (x
, 0));
7265 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7266 is a comparison and STORE_FLAG_VALUE permits. This is like
7267 the first case, but it works even when MODE is larger
7268 than HOST_WIDE_INT. */
7269 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7270 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7271 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7272 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7273 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7274 return XEXP (XEXP (x
, 0), 0);
7276 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7277 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7278 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7279 && subreg_lowpart_p (XEXP (x
, 0))
7280 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7281 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7282 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7283 return SUBREG_REG (XEXP (x
, 0));
7287 /* If we reach here, we want to return a pair of shifts. The inner
7288 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7289 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7290 logical depending on the value of UNSIGNEDP.
7292 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7293 converted into an AND of a shift.
7295 We must check for the case where the left shift would have a negative
7296 count. This can happen in a case like (x >> 31) & 255 on machines
7297 that can't shift by a constant. On those machines, we would first
7298 combine the shift with the AND to produce a variable-position
7299 extraction. Then the constant of 31 would be substituted in
7300 to produce such a position. */
7302 modewidth
= GET_MODE_PRECISION (mode
);
7303 if (modewidth
>= pos
+ len
)
7305 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7306 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7308 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7309 tem
, modewidth
- pos
- len
);
7310 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7311 mode
, tem
, modewidth
- len
);
7313 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7314 tem
= simplify_and_const_int (NULL_RTX
, mode
,
7315 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7318 (HOST_WIDE_INT_1U
<< len
) - 1);
7320 /* Any other cases we can't handle. */
7323 /* If we couldn't do this for some reason, return the original
7325 if (GET_CODE (tem
) == CLOBBER
)
7331 /* X is a SET which contains an assignment of one object into
7332 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7333 or certain SUBREGS). If possible, convert it into a series of
7336 We half-heartedly support variable positions, but do not at all
7337 support variable lengths. */
7340 expand_field_assignment (const_rtx x
)
7343 rtx pos
; /* Always counts from low bit. */
7345 rtx mask
, cleared
, masked
;
7346 scalar_int_mode compute_mode
;
7348 /* Loop until we find something we can't simplify. */
7351 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7352 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7354 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7355 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7356 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7358 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7359 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7361 inner
= XEXP (SET_DEST (x
), 0);
7362 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7363 pos
= XEXP (SET_DEST (x
), 2);
7365 /* A constant position should stay within the width of INNER. */
7366 if (CONST_INT_P (pos
)
7367 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7370 if (BITS_BIG_ENDIAN
)
7372 if (CONST_INT_P (pos
))
7373 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7375 else if (GET_CODE (pos
) == MINUS
7376 && CONST_INT_P (XEXP (pos
, 1))
7377 && (INTVAL (XEXP (pos
, 1))
7378 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7379 /* If position is ADJUST - X, new position is X. */
7380 pos
= XEXP (pos
, 0);
7383 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7384 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7385 gen_int_mode (prec
- len
,
7392 /* If the destination is a subreg that overwrites the whole of the inner
7393 register, we can move the subreg to the source. */
7394 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7395 /* We need SUBREGs to compute nonzero_bits properly. */
7396 && nonzero_sign_valid
7397 && !read_modify_subreg_p (SET_DEST (x
)))
7399 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7401 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7408 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7409 inner
= SUBREG_REG (inner
);
7411 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7412 if (!is_a
<scalar_int_mode
> (GET_MODE (inner
), &compute_mode
))
7414 /* Don't do anything for vector or complex integral types. */
7415 if (! FLOAT_MODE_P (GET_MODE (inner
)))
7418 /* Try to find an integral mode to pun with. */
7419 if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner
)), 0)
7420 .exists (&compute_mode
))
7423 inner
= gen_lowpart (compute_mode
, inner
);
7426 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7427 if (len
>= HOST_BITS_PER_WIDE_INT
)
7430 /* Don't try to compute in too wide unsupported modes. */
7431 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7434 /* Now compute the equivalent expression. Make a copy of INNER
7435 for the SET_DEST in case it is a MEM into which we will substitute;
7436 we don't want shared RTL in that case. */
7437 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7439 cleared
= simplify_gen_binary (AND
, compute_mode
,
7440 simplify_gen_unary (NOT
, compute_mode
,
7441 simplify_gen_binary (ASHIFT
,
7446 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7447 simplify_gen_binary (
7449 gen_lowpart (compute_mode
, SET_SRC (x
)),
7453 x
= gen_rtx_SET (copy_rtx (inner
),
7454 simplify_gen_binary (IOR
, compute_mode
,
7461 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7462 it is an RTX that represents the (variable) starting position; otherwise,
7463 POS is the (constant) starting bit position. Both are counted from the LSB.
7465 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7467 IN_DEST is nonzero if this is a reference in the destination of a SET.
7468 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7469 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7472 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7473 ZERO_EXTRACT should be built even for bits starting at bit 0.
7475 MODE is the desired mode of the result (if IN_DEST == 0).
7477 The result is an RTX for the extraction or NULL_RTX if the target
7481 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7482 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7483 int in_dest
, int in_compare
)
7485 /* This mode describes the size of the storage area
7486 to fetch the overall value from. Within that, we
7487 ignore the POS lowest bits, etc. */
7488 machine_mode is_mode
= GET_MODE (inner
);
7489 machine_mode inner_mode
;
7490 scalar_int_mode wanted_inner_mode
;
7491 scalar_int_mode wanted_inner_reg_mode
= word_mode
;
7492 scalar_int_mode pos_mode
= word_mode
;
7493 machine_mode extraction_mode
= word_mode
;
7495 rtx orig_pos_rtx
= pos_rtx
;
7496 HOST_WIDE_INT orig_pos
;
7498 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7499 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7501 if (GET_CODE (inner
) == SUBREG
7502 && subreg_lowpart_p (inner
)
7503 && (paradoxical_subreg_p (inner
)
7504 /* If trying or potentionally trying to extract
7505 bits outside of is_mode, don't look through
7506 non-paradoxical SUBREGs. See PR82192. */
7507 || (pos_rtx
== NULL_RTX
7508 && pos
+ len
<= GET_MODE_PRECISION (is_mode
))))
7510 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7511 consider just the QI as the memory to extract from.
7512 The subreg adds or removes high bits; its mode is
7513 irrelevant to the meaning of this extraction,
7514 since POS and LEN count from the lsb. */
7515 if (MEM_P (SUBREG_REG (inner
)))
7516 is_mode
= GET_MODE (SUBREG_REG (inner
));
7517 inner
= SUBREG_REG (inner
);
7519 else if (GET_CODE (inner
) == ASHIFT
7520 && CONST_INT_P (XEXP (inner
, 1))
7521 && pos_rtx
== 0 && pos
== 0
7522 && len
> UINTVAL (XEXP (inner
, 1)))
7524 /* We're extracting the least significant bits of an rtx
7525 (ashift X (const_int C)), where LEN > C. Extract the
7526 least significant (LEN - C) bits of X, giving an rtx
7527 whose mode is MODE, then shift it left C times. */
7528 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7529 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7530 unsignedp
, in_dest
, in_compare
);
7532 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7534 else if (GET_CODE (inner
) == TRUNCATE
7535 /* If trying or potentionally trying to extract
7536 bits outside of is_mode, don't look through
7537 TRUNCATE. See PR82192. */
7538 && pos_rtx
== NULL_RTX
7539 && pos
+ len
<= GET_MODE_PRECISION (is_mode
))
7540 inner
= XEXP (inner
, 0);
7542 inner_mode
= GET_MODE (inner
);
7544 /* See if this can be done without an extraction. We never can if the
7545 width of the field is not the same as that of some integer mode. For
7546 registers, we can only avoid the extraction if the position is at the
7547 low-order bit and this is either not in the destination or we have the
7548 appropriate STRICT_LOW_PART operation available.
7550 For MEM, we can avoid an extract if the field starts on an appropriate
7551 boundary and we can change the mode of the memory reference. */
7553 scalar_int_mode tmode
;
7554 if (int_mode_for_size (len
, 1).exists (&tmode
)
7555 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7557 && (pos
== 0 || REG_P (inner
))
7558 && (inner_mode
== tmode
7560 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7561 || reg_truncated_to_mode (tmode
, inner
))
7564 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7565 || (MEM_P (inner
) && pos_rtx
== 0
7567 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7568 : BITS_PER_UNIT
)) == 0
7569 /* We can't do this if we are widening INNER_MODE (it
7570 may not be aligned, for one thing). */
7571 && !paradoxical_subreg_p (tmode
, inner_mode
)
7572 && (inner_mode
== tmode
7573 || (! mode_dependent_address_p (XEXP (inner
, 0),
7574 MEM_ADDR_SPACE (inner
))
7575 && ! MEM_VOLATILE_P (inner
))))))
7577 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7578 field. If the original and current mode are the same, we need not
7579 adjust the offset. Otherwise, we do if bytes big endian.
7581 If INNER is not a MEM, get a piece consisting of just the field
7582 of interest (in this case POS % BITS_PER_WORD must be 0). */
7586 HOST_WIDE_INT offset
;
7588 /* POS counts from lsb, but make OFFSET count in memory order. */
7589 if (BYTES_BIG_ENDIAN
)
7590 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7592 offset
= pos
/ BITS_PER_UNIT
;
7594 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7596 else if (REG_P (inner
))
7598 if (tmode
!= inner_mode
)
7600 /* We can't call gen_lowpart in a DEST since we
7601 always want a SUBREG (see below) and it would sometimes
7602 return a new hard register. */
7606 = subreg_offset_from_lsb (tmode
, inner_mode
, pos
);
7608 /* Avoid creating invalid subregs, for example when
7609 simplifying (x>>32)&255. */
7610 if (!validate_subreg (tmode
, inner_mode
, inner
, offset
))
7613 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, offset
);
7616 new_rtx
= gen_lowpart (tmode
, inner
);
7622 new_rtx
= force_to_mode (inner
, tmode
,
7623 len
>= HOST_BITS_PER_WIDE_INT
7625 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7627 /* If this extraction is going into the destination of a SET,
7628 make a STRICT_LOW_PART unless we made a MEM. */
7631 return (MEM_P (new_rtx
) ? new_rtx
7632 : (GET_CODE (new_rtx
) != SUBREG
7633 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7634 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7639 if (CONST_SCALAR_INT_P (new_rtx
))
7640 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7641 mode
, new_rtx
, tmode
);
7643 /* If we know that no extraneous bits are set, and that the high
7644 bit is not set, convert the extraction to the cheaper of
7645 sign and zero extension, that are equivalent in these cases. */
7646 if (flag_expensive_optimizations
7647 && (HWI_COMPUTABLE_MODE_P (tmode
)
7648 && ((nonzero_bits (new_rtx
, tmode
)
7649 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7652 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7653 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7655 /* Prefer ZERO_EXTENSION, since it gives more information to
7657 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7658 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7663 /* Otherwise, sign- or zero-extend unless we already are in the
7666 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7670 /* Unless this is a COMPARE or we have a funny memory reference,
7671 don't do anything with zero-extending field extracts starting at
7672 the low-order bit since they are simple AND operations. */
7673 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7674 && ! in_compare
&& unsignedp
)
7677 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7678 if the position is not a constant and the length is not 1. In all
7679 other cases, we would only be going outside our object in cases when
7680 an original shift would have been undefined. */
7682 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7683 || (pos_rtx
!= 0 && len
!= 1)))
7686 enum extraction_pattern pattern
= (in_dest
? EP_insv
7687 : unsignedp
? EP_extzv
: EP_extv
);
7689 /* If INNER is not from memory, we want it to have the mode of a register
7690 extraction pattern's structure operand, or word_mode if there is no
7691 such pattern. The same applies to extraction_mode and pos_mode
7692 and their respective operands.
7694 For memory, assume that the desired extraction_mode and pos_mode
7695 are the same as for a register operation, since at present we don't
7696 have named patterns for aligned memory structures. */
7697 struct extraction_insn insn
;
7698 if (get_best_reg_extraction_insn (&insn
, pattern
,
7699 GET_MODE_BITSIZE (inner_mode
), mode
))
7701 wanted_inner_reg_mode
= insn
.struct_mode
.require ();
7702 pos_mode
= insn
.pos_mode
;
7703 extraction_mode
= insn
.field_mode
;
7706 /* Never narrow an object, since that might not be safe. */
7708 if (mode
!= VOIDmode
7709 && partial_subreg_p (extraction_mode
, mode
))
7710 extraction_mode
= mode
;
7713 wanted_inner_mode
= wanted_inner_reg_mode
;
7716 /* Be careful not to go beyond the extracted object and maintain the
7717 natural alignment of the memory. */
7718 wanted_inner_mode
= smallest_int_mode_for_size (len
);
7719 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7720 > GET_MODE_BITSIZE (wanted_inner_mode
))
7721 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
).require ();
7726 if (BITS_BIG_ENDIAN
)
7728 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7729 BITS_BIG_ENDIAN style. If position is constant, compute new
7730 position. Otherwise, build subtraction.
7731 Note that POS is relative to the mode of the original argument.
7732 If it's a MEM we need to recompute POS relative to that.
7733 However, if we're extracting from (or inserting into) a register,
7734 we want to recompute POS relative to wanted_inner_mode. */
7735 int width
= (MEM_P (inner
)
7736 ? GET_MODE_BITSIZE (is_mode
)
7737 : GET_MODE_BITSIZE (wanted_inner_mode
));
7740 pos
= width
- len
- pos
;
7743 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7744 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7746 /* POS may be less than 0 now, but we check for that below.
7747 Note that it can only be less than 0 if !MEM_P (inner). */
7750 /* If INNER has a wider mode, and this is a constant extraction, try to
7751 make it smaller and adjust the byte to point to the byte containing
7753 if (wanted_inner_mode
!= VOIDmode
7754 && inner_mode
!= wanted_inner_mode
7756 && partial_subreg_p (wanted_inner_mode
, is_mode
)
7758 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7759 && ! MEM_VOLATILE_P (inner
))
7763 /* The computations below will be correct if the machine is big
7764 endian in both bits and bytes or little endian in bits and bytes.
7765 If it is mixed, we must adjust. */
7767 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7768 adjust OFFSET to compensate. */
7769 if (BYTES_BIG_ENDIAN
7770 && paradoxical_subreg_p (is_mode
, inner_mode
))
7771 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7773 /* We can now move to the desired byte. */
7774 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7775 * GET_MODE_SIZE (wanted_inner_mode
);
7776 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7778 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7779 && is_mode
!= wanted_inner_mode
)
7780 offset
= (GET_MODE_SIZE (is_mode
)
7781 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7783 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7786 /* If INNER is not memory, get it into the proper mode. If we are changing
7787 its mode, POS must be a constant and smaller than the size of the new
7789 else if (!MEM_P (inner
))
7791 /* On the LHS, don't create paradoxical subregs implicitely truncating
7792 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7794 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7798 if (GET_MODE (inner
) != wanted_inner_mode
7800 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7806 inner
= force_to_mode (inner
, wanted_inner_mode
,
7808 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7810 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7815 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7816 have to zero extend. Otherwise, we can just use a SUBREG.
7818 We dealt with constant rtxes earlier, so pos_rtx cannot
7819 have VOIDmode at this point. */
7821 && (GET_MODE_SIZE (pos_mode
)
7822 > GET_MODE_SIZE (as_a
<scalar_int_mode
> (GET_MODE (pos_rtx
)))))
7824 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7825 GET_MODE (pos_rtx
));
7827 /* If we know that no extraneous bits are set, and that the high
7828 bit is not set, convert extraction to cheaper one - either
7829 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7831 if (flag_expensive_optimizations
7832 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7833 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7834 & ~(((unsigned HOST_WIDE_INT
)
7835 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7839 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7840 GET_MODE (pos_rtx
));
7842 /* Prefer ZERO_EXTENSION, since it gives more information to
7844 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7845 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7851 /* Make POS_RTX unless we already have it and it is correct. If we don't
7852 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7854 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7855 pos_rtx
= orig_pos_rtx
;
7857 else if (pos_rtx
== 0)
7858 pos_rtx
= GEN_INT (pos
);
7860 /* Make the required operation. See if we can use existing rtx. */
7861 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7862 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7864 new_rtx
= gen_lowpart (mode
, new_rtx
);
7869 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7870 can be commuted with any other operations in X. Return X without
7871 that shift if so. */
7874 extract_left_shift (scalar_int_mode mode
, rtx x
, int count
)
7876 enum rtx_code code
= GET_CODE (x
);
7882 /* This is the shift itself. If it is wide enough, we will return
7883 either the value being shifted if the shift count is equal to
7884 COUNT or a shift for the difference. */
7885 if (CONST_INT_P (XEXP (x
, 1))
7886 && INTVAL (XEXP (x
, 1)) >= count
)
7887 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7888 INTVAL (XEXP (x
, 1)) - count
);
7892 if ((tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
7893 return simplify_gen_unary (code
, mode
, tem
, mode
);
7897 case PLUS
: case IOR
: case XOR
: case AND
:
7898 /* If we can safely shift this constant and we find the inner shift,
7899 make a new operation. */
7900 if (CONST_INT_P (XEXP (x
, 1))
7901 && (UINTVAL (XEXP (x
, 1))
7902 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7903 && (tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
7905 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7906 return simplify_gen_binary (code
, mode
, tem
,
7907 gen_int_mode (val
, mode
));
7918 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7919 level of the expression and MODE is its mode. IN_CODE is as for
7920 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7921 that should be used when recursing on operands of *X_PTR.
7923 There are two possible actions:
7925 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7926 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7928 - Return a new rtx, which the caller returns directly. */
7931 make_compound_operation_int (scalar_int_mode mode
, rtx
*x_ptr
,
7932 enum rtx_code in_code
,
7933 enum rtx_code
*next_code_ptr
)
7936 enum rtx_code next_code
= *next_code_ptr
;
7937 enum rtx_code code
= GET_CODE (x
);
7938 int mode_width
= GET_MODE_PRECISION (mode
);
7943 scalar_int_mode inner_mode
;
7944 bool equality_comparison
= false;
7948 equality_comparison
= true;
7952 /* Process depending on the code of this operation. If NEW is set
7953 nonzero, it will be returned. */
7958 /* Convert shifts by constants into multiplications if inside
7960 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7961 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7962 && INTVAL (XEXP (x
, 1)) >= 0)
7964 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7965 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
7967 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7968 if (GET_CODE (new_rtx
) == NEG
)
7970 new_rtx
= XEXP (new_rtx
, 0);
7973 multval
= trunc_int_for_mode (multval
, mode
);
7974 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7981 lhs
= make_compound_operation (lhs
, next_code
);
7982 rhs
= make_compound_operation (rhs
, next_code
);
7983 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
7985 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7987 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7989 else if (GET_CODE (lhs
) == MULT
7990 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7992 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7993 simplify_gen_unary (NEG
, mode
,
7996 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8000 SUBST (XEXP (x
, 0), lhs
);
8001 SUBST (XEXP (x
, 1), rhs
);
8003 maybe_swap_commutative_operands (x
);
8009 lhs
= make_compound_operation (lhs
, next_code
);
8010 rhs
= make_compound_operation (rhs
, next_code
);
8011 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
8013 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
8015 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8017 else if (GET_CODE (rhs
) == MULT
8018 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
8020 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
8021 simplify_gen_unary (NEG
, mode
,
8024 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8028 SUBST (XEXP (x
, 0), lhs
);
8029 SUBST (XEXP (x
, 1), rhs
);
8034 /* If the second operand is not a constant, we can't do anything
8036 if (!CONST_INT_P (XEXP (x
, 1)))
8039 /* If the constant is a power of two minus one and the first operand
8040 is a logical right shift, make an extraction. */
8041 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8042 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8044 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8045 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1),
8046 i
, 1, 0, in_code
== COMPARE
);
8049 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8050 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
8051 && subreg_lowpart_p (XEXP (x
, 0))
8052 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (XEXP (x
, 0))),
8054 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
8055 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8057 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
8058 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
8059 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
8061 i
, 1, 0, in_code
== COMPARE
);
8063 /* If we narrowed the mode when dropping the subreg, then we lose. */
8064 if (GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (mode
))
8067 /* If that didn't give anything, see if the AND simplifies on
8069 if (!new_rtx
&& i
>= 0)
8071 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8072 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
8073 0, in_code
== COMPARE
);
8076 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8077 else if ((GET_CODE (XEXP (x
, 0)) == XOR
8078 || GET_CODE (XEXP (x
, 0)) == IOR
)
8079 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
8080 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
8081 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8083 /* Apply the distributive law, and then try to make extractions. */
8084 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
8085 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
8087 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
8089 new_rtx
= make_compound_operation (new_rtx
, in_code
);
8092 /* If we are have (and (rotate X C) M) and C is larger than the number
8093 of bits in M, this is an extraction. */
8095 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
8096 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8097 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
8098 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
8100 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8101 new_rtx
= make_extraction (mode
, new_rtx
,
8102 (GET_MODE_PRECISION (mode
)
8103 - INTVAL (XEXP (XEXP (x
, 0), 1))),
8104 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8107 /* On machines without logical shifts, if the operand of the AND is
8108 a logical shift and our mask turns off all the propagated sign
8109 bits, we can replace the logical shift with an arithmetic shift. */
8110 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8111 && !have_insn_for (LSHIFTRT
, mode
)
8112 && have_insn_for (ASHIFTRT
, mode
)
8113 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8114 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8115 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8116 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8118 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8120 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8121 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8123 gen_rtx_ASHIFTRT (mode
,
8124 make_compound_operation (XEXP (XEXP (x
,
8128 XEXP (XEXP (x
, 0), 1)));
8131 /* If the constant is one less than a power of two, this might be
8132 representable by an extraction even if no shift is present.
8133 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8134 we are in a COMPARE. */
8135 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8136 new_rtx
= make_extraction (mode
,
8137 make_compound_operation (XEXP (x
, 0),
8139 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8141 /* If we are in a comparison and this is an AND with a power of two,
8142 convert this into the appropriate bit extract. */
8143 else if (in_code
== COMPARE
8144 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8145 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8146 new_rtx
= make_extraction (mode
,
8147 make_compound_operation (XEXP (x
, 0),
8149 i
, NULL_RTX
, 1, 1, 0, 1);
8151 /* If the one operand is a paradoxical subreg of a register or memory and
8152 the constant (limited to the smaller mode) has only zero bits where
8153 the sub expression has known zero bits, this can be expressed as
8155 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8159 sub
= XEXP (XEXP (x
, 0), 0);
8160 machine_mode sub_mode
= GET_MODE (sub
);
8161 if ((REG_P (sub
) || MEM_P (sub
))
8162 && GET_MODE_PRECISION (sub_mode
) < mode_width
)
8164 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8165 unsigned HOST_WIDE_INT mask
;
8167 /* original AND constant with all the known zero bits set */
8168 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8169 if ((mask
& mode_mask
) == mode_mask
)
8171 new_rtx
= make_compound_operation (sub
, next_code
);
8172 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0,
8173 GET_MODE_PRECISION (sub_mode
),
8174 1, 0, in_code
== COMPARE
);
8182 /* If the sign bit is known to be zero, replace this with an
8183 arithmetic shift. */
8184 if (have_insn_for (ASHIFTRT
, mode
)
8185 && ! have_insn_for (LSHIFTRT
, mode
)
8186 && mode_width
<= HOST_BITS_PER_WIDE_INT
8187 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8189 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8190 make_compound_operation (XEXP (x
, 0),
8202 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8203 this is a SIGN_EXTRACT. */
8204 if (CONST_INT_P (rhs
)
8205 && GET_CODE (lhs
) == ASHIFT
8206 && CONST_INT_P (XEXP (lhs
, 1))
8207 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8208 && INTVAL (XEXP (lhs
, 1)) >= 0
8209 && INTVAL (rhs
) < mode_width
)
8211 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8212 new_rtx
= make_extraction (mode
, new_rtx
,
8213 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8214 NULL_RTX
, mode_width
- INTVAL (rhs
),
8215 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8219 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8220 If so, try to merge the shifts into a SIGN_EXTEND. We could
8221 also do this for some cases of SIGN_EXTRACT, but it doesn't
8222 seem worth the effort; the case checked for occurs on Alpha. */
8225 && ! (GET_CODE (lhs
) == SUBREG
8226 && (OBJECT_P (SUBREG_REG (lhs
))))
8227 && CONST_INT_P (rhs
)
8228 && INTVAL (rhs
) >= 0
8229 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8230 && INTVAL (rhs
) < mode_width
8231 && (new_rtx
= extract_left_shift (mode
, lhs
, INTVAL (rhs
))) != 0)
8232 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
,
8234 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8235 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8240 /* Call ourselves recursively on the inner expression. If we are
8241 narrowing the object and it has a different RTL code from
8242 what it originally did, do this SUBREG as a force_to_mode. */
8244 rtx inner
= SUBREG_REG (x
), simplified
;
8245 enum rtx_code subreg_code
= in_code
;
8247 /* If the SUBREG is masking of a logical right shift,
8248 make an extraction. */
8249 if (GET_CODE (inner
) == LSHIFTRT
8250 && is_a
<scalar_int_mode
> (GET_MODE (inner
), &inner_mode
)
8251 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (inner_mode
)
8252 && CONST_INT_P (XEXP (inner
, 1))
8253 && UINTVAL (XEXP (inner
, 1)) < GET_MODE_PRECISION (inner_mode
)
8254 && subreg_lowpart_p (x
))
8256 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8257 int width
= GET_MODE_PRECISION (inner_mode
)
8258 - INTVAL (XEXP (inner
, 1));
8259 if (width
> mode_width
)
8261 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8262 width
, 1, 0, in_code
== COMPARE
);
8266 /* If in_code is COMPARE, it isn't always safe to pass it through
8267 to the recursive make_compound_operation call. */
8268 if (subreg_code
== COMPARE
8269 && (!subreg_lowpart_p (x
)
8270 || GET_CODE (inner
) == SUBREG
8271 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8272 is (const_int 0), rather than
8273 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8274 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8275 for non-equality comparisons against 0 is not equivalent
8276 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8277 || (GET_CODE (inner
) == AND
8278 && CONST_INT_P (XEXP (inner
, 1))
8279 && partial_subreg_p (x
)
8280 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8281 >= GET_MODE_BITSIZE (mode
) - 1)))
8284 tem
= make_compound_operation (inner
, subreg_code
);
8287 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8291 if (GET_CODE (tem
) != GET_CODE (inner
)
8292 && partial_subreg_p (x
)
8293 && subreg_lowpart_p (x
))
8296 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8298 /* If we have something other than a SUBREG, we might have
8299 done an expansion, so rerun ourselves. */
8300 if (GET_CODE (newer
) != SUBREG
)
8301 newer
= make_compound_operation (newer
, in_code
);
8303 /* force_to_mode can expand compounds. If it just re-expanded
8304 the compound, use gen_lowpart to convert to the desired
8306 if (rtx_equal_p (newer
, x
)
8307 /* Likewise if it re-expanded the compound only partially.
8308 This happens for SUBREG of ZERO_EXTRACT if they extract
8309 the same number of bits. */
8310 || (GET_CODE (newer
) == SUBREG
8311 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8312 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8313 && GET_CODE (inner
) == AND
8314 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8315 return gen_lowpart (GET_MODE (x
), tem
);
8330 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8331 *next_code_ptr
= next_code
;
8335 /* Look at the expression rooted at X. Look for expressions
8336 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8337 Form these expressions.
8339 Return the new rtx, usually just X.
8341 Also, for machines like the VAX that don't have logical shift insns,
8342 try to convert logical to arithmetic shift operations in cases where
8343 they are equivalent. This undoes the canonicalizations to logical
8344 shifts done elsewhere.
8346 We try, as much as possible, to re-use rtl expressions to save memory.
8348 IN_CODE says what kind of expression we are processing. Normally, it is
8349 SET. In a memory address it is MEM. When processing the arguments of
8350 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8351 precisely it is an equality comparison against zero. */
8354 make_compound_operation (rtx x
, enum rtx_code in_code
)
8356 enum rtx_code code
= GET_CODE (x
);
8359 enum rtx_code next_code
;
8362 /* Select the code to be used in recursive calls. Once we are inside an
8363 address, we stay there. If we have a comparison, set to COMPARE,
8364 but once inside, go back to our default of SET. */
8366 next_code
= (code
== MEM
? MEM
8367 : ((code
== COMPARE
|| COMPARISON_P (x
))
8368 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8369 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8371 scalar_int_mode mode
;
8372 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
8374 rtx new_rtx
= make_compound_operation_int (mode
, &x
, in_code
,
8378 code
= GET_CODE (x
);
8381 /* Now recursively process each operand of this operation. We need to
8382 handle ZERO_EXTEND specially so that we don't lose track of the
8384 if (code
== ZERO_EXTEND
)
8386 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8387 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8388 new_rtx
, GET_MODE (XEXP (x
, 0)));
8391 SUBST (XEXP (x
, 0), new_rtx
);
8395 fmt
= GET_RTX_FORMAT (code
);
8396 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8399 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8400 SUBST (XEXP (x
, i
), new_rtx
);
8402 else if (fmt
[i
] == 'E')
8403 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8405 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8406 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8409 maybe_swap_commutative_operands (x
);
8413 /* Given M see if it is a value that would select a field of bits
8414 within an item, but not the entire word. Return -1 if not.
8415 Otherwise, return the starting position of the field, where 0 is the
8418 *PLEN is set to the length of the field. */
8421 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8423 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8424 int pos
= m
? ctz_hwi (m
) : -1;
8428 /* Now shift off the low-order zero bits and see if we have a
8429 power of two minus 1. */
8430 len
= exact_log2 ((m
>> pos
) + 1);
8439 /* If X refers to a register that equals REG in value, replace these
8440 references with REG. */
8442 canon_reg_for_combine (rtx x
, rtx reg
)
8449 enum rtx_code code
= GET_CODE (x
);
8450 switch (GET_RTX_CLASS (code
))
8453 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8454 if (op0
!= XEXP (x
, 0))
8455 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8460 case RTX_COMM_ARITH
:
8461 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8462 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8463 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8464 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8468 case RTX_COMM_COMPARE
:
8469 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8470 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8471 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8472 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8473 GET_MODE (op0
), op0
, op1
);
8477 case RTX_BITFIELD_OPS
:
8478 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8479 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8480 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8481 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8482 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8483 GET_MODE (op0
), op0
, op1
, op2
);
8489 if (rtx_equal_p (get_last_value (reg
), x
)
8490 || rtx_equal_p (reg
, get_last_value (x
)))
8499 fmt
= GET_RTX_FORMAT (code
);
8501 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8504 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8505 if (op
!= XEXP (x
, i
))
8515 else if (fmt
[i
] == 'E')
8518 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8520 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8521 if (op
!= XVECEXP (x
, i
, j
))
8528 XVECEXP (x
, i
, j
) = op
;
8539 /* Return X converted to MODE. If the value is already truncated to
8540 MODE we can just return a subreg even though in the general case we
8541 would need an explicit truncation. */
8544 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8546 if (!CONST_INT_P (x
)
8547 && partial_subreg_p (mode
, GET_MODE (x
))
8548 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8549 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8551 /* Bit-cast X into an integer mode. */
8552 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8553 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)).require (), x
);
8554 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
).require (),
8558 return gen_lowpart (mode
, x
);
8561 /* See if X can be simplified knowing that we will only refer to it in
8562 MODE and will only refer to those bits that are nonzero in MASK.
8563 If other bits are being computed or if masking operations are done
8564 that select a superset of the bits in MASK, they can sometimes be
8567 Return a possibly simplified expression, but always convert X to
8568 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8570 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8571 are all off in X. This is used when X will be complemented, by either
8572 NOT, NEG, or XOR. */
8575 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8578 enum rtx_code code
= GET_CODE (x
);
8579 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8580 machine_mode op_mode
;
8581 unsigned HOST_WIDE_INT nonzero
;
8583 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8584 code below will do the wrong thing since the mode of such an
8585 expression is VOIDmode.
8587 Also do nothing if X is a CLOBBER; this can happen if X was
8588 the return value from a call to gen_lowpart. */
8589 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8592 /* We want to perform the operation in its present mode unless we know
8593 that the operation is valid in MODE, in which case we do the operation
8595 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8596 && have_insn_for (code
, mode
))
8597 ? mode
: GET_MODE (x
));
8599 /* It is not valid to do a right-shift in a narrower mode
8600 than the one it came in with. */
8601 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8602 && partial_subreg_p (mode
, GET_MODE (x
)))
8603 op_mode
= GET_MODE (x
);
8605 /* Truncate MASK to fit OP_MODE. */
8607 mask
&= GET_MODE_MASK (op_mode
);
8609 /* Determine what bits of X are guaranteed to be (non)zero. */
8610 nonzero
= nonzero_bits (x
, mode
);
8612 /* If none of the bits in X are needed, return a zero. */
8613 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8616 /* If X is a CONST_INT, return a new one. Do this here since the
8617 test below will fail. */
8618 if (CONST_INT_P (x
))
8620 if (SCALAR_INT_MODE_P (mode
))
8621 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8624 x
= GEN_INT (INTVAL (x
) & mask
);
8625 return gen_lowpart_common (mode
, x
);
8629 /* If X is narrower than MODE and we want all the bits in X's mode, just
8630 get X in the proper mode. */
8631 if (paradoxical_subreg_p (mode
, GET_MODE (x
))
8632 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8633 return gen_lowpart (mode
, x
);
8635 /* We can ignore the effect of a SUBREG if it narrows the mode or
8636 if the constant masks to zero all the bits the mode doesn't have. */
8637 if (GET_CODE (x
) == SUBREG
8638 && subreg_lowpart_p (x
)
8639 && (partial_subreg_p (x
)
8641 & GET_MODE_MASK (GET_MODE (x
))
8642 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8643 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8645 scalar_int_mode int_mode
, xmode
;
8646 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
8647 && is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
8648 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8650 return force_int_to_mode (x
, int_mode
, xmode
,
8651 as_a
<scalar_int_mode
> (op_mode
),
8654 return gen_lowpart_or_truncate (mode
, x
);
8657 /* Subroutine of force_to_mode that handles cases in which both X and
8658 the result are scalar integers. MODE is the mode of the result,
8659 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8660 is preferred for simplified versions of X. The other arguments
8661 are as for force_to_mode. */
8664 force_int_to_mode (rtx x
, scalar_int_mode mode
, scalar_int_mode xmode
,
8665 scalar_int_mode op_mode
, unsigned HOST_WIDE_INT mask
,
8668 enum rtx_code code
= GET_CODE (x
);
8669 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8670 unsigned HOST_WIDE_INT fuller_mask
;
8673 /* When we have an arithmetic operation, or a shift whose count we
8674 do not know, we need to assume that all bits up to the highest-order
8675 bit in MASK will be needed. This is how we form such a mask. */
8676 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8677 fuller_mask
= HOST_WIDE_INT_M1U
;
8679 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8685 /* If X is a (clobber (const_int)), return it since we know we are
8686 generating something that won't match. */
8693 x
= expand_compound_operation (x
);
8694 if (GET_CODE (x
) != code
)
8695 return force_to_mode (x
, mode
, mask
, next_select
);
8699 /* Similarly for a truncate. */
8700 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8703 /* If this is an AND with a constant, convert it into an AND
8704 whose constant is the AND of that constant with MASK. If it
8705 remains an AND of MASK, delete it since it is redundant. */
8707 if (CONST_INT_P (XEXP (x
, 1)))
8709 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8710 mask
& INTVAL (XEXP (x
, 1)));
8713 /* If X is still an AND, see if it is an AND with a mask that
8714 is just some low-order bits. If so, and it is MASK, we don't
8717 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8718 && (INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (xmode
)) == mask
)
8721 /* If it remains an AND, try making another AND with the bits
8722 in the mode mask that aren't in MASK turned on. If the
8723 constant in the AND is wide enough, this might make a
8724 cheaper constant. */
8726 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8727 && GET_MODE_MASK (xmode
) != mask
8728 && HWI_COMPUTABLE_MODE_P (xmode
))
8730 unsigned HOST_WIDE_INT cval
8731 = UINTVAL (XEXP (x
, 1)) | (GET_MODE_MASK (xmode
) & ~mask
);
8734 y
= simplify_gen_binary (AND
, xmode
, XEXP (x
, 0),
8735 gen_int_mode (cval
, xmode
));
8736 if (set_src_cost (y
, xmode
, optimize_this_for_speed_p
)
8737 < set_src_cost (x
, xmode
, optimize_this_for_speed_p
))
8747 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8748 low-order bits (as in an alignment operation) and FOO is already
8749 aligned to that boundary, mask C1 to that boundary as well.
8750 This may eliminate that PLUS and, later, the AND. */
8753 unsigned int width
= GET_MODE_PRECISION (mode
);
8754 unsigned HOST_WIDE_INT smask
= mask
;
8756 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8757 number, sign extend it. */
8759 if (width
< HOST_BITS_PER_WIDE_INT
8760 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8761 smask
|= HOST_WIDE_INT_M1U
<< width
;
8763 if (CONST_INT_P (XEXP (x
, 1))
8764 && pow2p_hwi (- smask
)
8765 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8766 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8767 return force_to_mode (plus_constant (xmode
, XEXP (x
, 0),
8768 (INTVAL (XEXP (x
, 1)) & smask
)),
8769 mode
, smask
, next_select
);
8775 /* Substituting into the operands of a widening MULT is not likely to
8776 create RTL matching a machine insn. */
8778 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8779 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8780 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8781 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8782 && REG_P (XEXP (XEXP (x
, 0), 0))
8783 && REG_P (XEXP (XEXP (x
, 1), 0)))
8784 return gen_lowpart_or_truncate (mode
, x
);
8786 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8787 most significant bit in MASK since carries from those bits will
8788 affect the bits we are interested in. */
8793 /* If X is (minus C Y) where C's least set bit is larger than any bit
8794 in the mask, then we may replace with (neg Y). */
8795 if (CONST_INT_P (XEXP (x
, 0))
8796 && least_bit_hwi (UINTVAL (XEXP (x
, 0))) > mask
)
8798 x
= simplify_gen_unary (NEG
, xmode
, XEXP (x
, 1), xmode
);
8799 return force_to_mode (x
, mode
, mask
, next_select
);
8802 /* Similarly, if C contains every bit in the fuller_mask, then we may
8803 replace with (not Y). */
8804 if (CONST_INT_P (XEXP (x
, 0))
8805 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8807 x
= simplify_gen_unary (NOT
, xmode
, XEXP (x
, 1), xmode
);
8808 return force_to_mode (x
, mode
, mask
, next_select
);
8816 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8817 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8818 operation which may be a bitfield extraction. Ensure that the
8819 constant we form is not wider than the mode of X. */
8821 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8822 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8823 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8824 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8825 && CONST_INT_P (XEXP (x
, 1))
8826 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8827 + floor_log2 (INTVAL (XEXP (x
, 1))))
8828 < GET_MODE_PRECISION (xmode
))
8829 && (UINTVAL (XEXP (x
, 1))
8830 & ~nonzero_bits (XEXP (x
, 0), xmode
)) == 0)
8832 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8833 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8835 temp
= simplify_gen_binary (GET_CODE (x
), xmode
,
8836 XEXP (XEXP (x
, 0), 0), temp
);
8837 x
= simplify_gen_binary (LSHIFTRT
, xmode
, temp
,
8838 XEXP (XEXP (x
, 0), 1));
8839 return force_to_mode (x
, mode
, mask
, next_select
);
8843 /* For most binary operations, just propagate into the operation and
8844 change the mode if we have an operation of that mode. */
8846 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8847 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8849 /* If we ended up truncating both operands, truncate the result of the
8850 operation instead. */
8851 if (GET_CODE (op0
) == TRUNCATE
8852 && GET_CODE (op1
) == TRUNCATE
)
8854 op0
= XEXP (op0
, 0);
8855 op1
= XEXP (op1
, 0);
8858 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8859 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8861 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8863 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8869 /* For left shifts, do the same, but just for the first operand.
8870 However, we cannot do anything with shifts where we cannot
8871 guarantee that the counts are smaller than the size of the mode
8872 because such a count will have a different meaning in a
8875 if (! (CONST_INT_P (XEXP (x
, 1))
8876 && INTVAL (XEXP (x
, 1)) >= 0
8877 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8878 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8879 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8880 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8883 /* If the shift count is a constant and we can do arithmetic in
8884 the mode of the shift, refine which bits we need. Otherwise, use the
8885 conservative form of the mask. */
8886 if (CONST_INT_P (XEXP (x
, 1))
8887 && INTVAL (XEXP (x
, 1)) >= 0
8888 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8889 && HWI_COMPUTABLE_MODE_P (op_mode
))
8890 mask
>>= INTVAL (XEXP (x
, 1));
8894 op0
= gen_lowpart_or_truncate (op_mode
,
8895 force_to_mode (XEXP (x
, 0), op_mode
,
8896 mask
, next_select
));
8898 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
8900 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8906 /* Here we can only do something if the shift count is a constant,
8907 this shift constant is valid for the host, and we can do arithmetic
8910 if (CONST_INT_P (XEXP (x
, 1))
8911 && INTVAL (XEXP (x
, 1)) >= 0
8912 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8913 && HWI_COMPUTABLE_MODE_P (op_mode
))
8915 rtx inner
= XEXP (x
, 0);
8916 unsigned HOST_WIDE_INT inner_mask
;
8918 /* Select the mask of the bits we need for the shift operand. */
8919 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8921 /* We can only change the mode of the shift if we can do arithmetic
8922 in the mode of the shift and INNER_MASK is no wider than the
8923 width of X's mode. */
8924 if ((inner_mask
& ~GET_MODE_MASK (xmode
)) != 0)
8927 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8929 if (xmode
!= op_mode
|| inner
!= XEXP (x
, 0))
8931 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8936 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8937 shift and AND produces only copies of the sign bit (C2 is one less
8938 than a power of two), we can do this with just a shift. */
8940 if (GET_CODE (x
) == LSHIFTRT
8941 && CONST_INT_P (XEXP (x
, 1))
8942 /* The shift puts one of the sign bit copies in the least significant
8944 && ((INTVAL (XEXP (x
, 1))
8945 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8946 >= GET_MODE_PRECISION (xmode
))
8947 && pow2p_hwi (mask
+ 1)
8948 /* Number of bits left after the shift must be more than the mask
8950 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8951 <= GET_MODE_PRECISION (xmode
))
8952 /* Must be more sign bit copies than the mask needs. */
8953 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8954 >= exact_log2 (mask
+ 1)))
8955 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0),
8956 GEN_INT (GET_MODE_PRECISION (xmode
)
8957 - exact_log2 (mask
+ 1)));
8962 /* If we are just looking for the sign bit, we don't need this shift at
8963 all, even if it has a variable count. */
8964 if (val_signbit_p (xmode
, mask
))
8965 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8967 /* If this is a shift by a constant, get a mask that contains those bits
8968 that are not copies of the sign bit. We then have two cases: If
8969 MASK only includes those bits, this can be a logical shift, which may
8970 allow simplifications. If MASK is a single-bit field not within
8971 those bits, we are requesting a copy of the sign bit and hence can
8972 shift the sign bit to the appropriate location. */
8974 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8975 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8977 unsigned HOST_WIDE_INT nonzero
;
8980 /* If the considered data is wider than HOST_WIDE_INT, we can't
8981 represent a mask for all its bits in a single scalar.
8982 But we only care about the lower bits, so calculate these. */
8984 if (GET_MODE_PRECISION (xmode
) > HOST_BITS_PER_WIDE_INT
)
8986 nonzero
= HOST_WIDE_INT_M1U
;
8988 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8989 is the number of bits a full-width mask would have set.
8990 We need only shift if these are fewer than nonzero can
8991 hold. If not, we must keep all bits set in nonzero. */
8993 if (GET_MODE_PRECISION (xmode
) - INTVAL (XEXP (x
, 1))
8994 < HOST_BITS_PER_WIDE_INT
)
8995 nonzero
>>= INTVAL (XEXP (x
, 1))
8996 + HOST_BITS_PER_WIDE_INT
8997 - GET_MODE_PRECISION (xmode
);
9001 nonzero
= GET_MODE_MASK (xmode
);
9002 nonzero
>>= INTVAL (XEXP (x
, 1));
9005 if ((mask
& ~nonzero
) == 0)
9007 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, xmode
,
9008 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
9009 if (GET_CODE (x
) != ASHIFTRT
)
9010 return force_to_mode (x
, mode
, mask
, next_select
);
9013 else if ((i
= exact_log2 (mask
)) >= 0)
9015 x
= simplify_shift_const
9016 (NULL_RTX
, LSHIFTRT
, xmode
, XEXP (x
, 0),
9017 GET_MODE_PRECISION (xmode
) - 1 - i
);
9019 if (GET_CODE (x
) != ASHIFTRT
)
9020 return force_to_mode (x
, mode
, mask
, next_select
);
9024 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9025 even if the shift count isn't a constant. */
9027 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0), XEXP (x
, 1));
9031 /* If this is a zero- or sign-extension operation that just affects bits
9032 we don't care about, remove it. Be sure the call above returned
9033 something that is still a shift. */
9035 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
9036 && CONST_INT_P (XEXP (x
, 1))
9037 && INTVAL (XEXP (x
, 1)) >= 0
9038 && (INTVAL (XEXP (x
, 1))
9039 <= GET_MODE_PRECISION (xmode
) - (floor_log2 (mask
) + 1))
9040 && GET_CODE (XEXP (x
, 0)) == ASHIFT
9041 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
9042 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
9049 /* If the shift count is constant and we can do computations
9050 in the mode of X, compute where the bits we care about are.
9051 Otherwise, we can't do anything. Don't change the mode of
9052 the shift or propagate MODE into the shift, though. */
9053 if (CONST_INT_P (XEXP (x
, 1))
9054 && INTVAL (XEXP (x
, 1)) >= 0)
9056 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
9057 xmode
, gen_int_mode (mask
, xmode
),
9059 if (temp
&& CONST_INT_P (temp
))
9060 x
= simplify_gen_binary (code
, xmode
,
9061 force_to_mode (XEXP (x
, 0), xmode
,
9062 INTVAL (temp
), next_select
),
9068 /* If we just want the low-order bit, the NEG isn't needed since it
9069 won't change the low-order bit. */
9071 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
9073 /* We need any bits less significant than the most significant bit in
9074 MASK since carries from those bits will affect the bits we are
9080 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9081 same as the XOR case above. Ensure that the constant we form is not
9082 wider than the mode of X. */
9084 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
9085 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
9086 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
9087 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
9088 < GET_MODE_PRECISION (xmode
))
9089 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
9091 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)), xmode
);
9092 temp
= simplify_gen_binary (XOR
, xmode
, XEXP (XEXP (x
, 0), 0), temp
);
9093 x
= simplify_gen_binary (LSHIFTRT
, xmode
,
9094 temp
, XEXP (XEXP (x
, 0), 1));
9096 return force_to_mode (x
, mode
, mask
, next_select
);
9099 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9100 use the full mask inside the NOT. */
9104 op0
= gen_lowpart_or_truncate (op_mode
,
9105 force_to_mode (XEXP (x
, 0), mode
, mask
,
9107 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
9109 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
9115 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9116 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9117 which is equal to STORE_FLAG_VALUE. */
9118 if ((mask
& ~STORE_FLAG_VALUE
) == 0
9119 && XEXP (x
, 1) == const0_rtx
9120 && GET_MODE (XEXP (x
, 0)) == mode
9121 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
9122 && (nonzero_bits (XEXP (x
, 0), mode
)
9123 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
9124 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9129 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9130 written in a narrower mode. We play it safe and do not do so. */
9132 op0
= gen_lowpart_or_truncate (xmode
,
9133 force_to_mode (XEXP (x
, 1), mode
,
9134 mask
, next_select
));
9135 op1
= gen_lowpart_or_truncate (xmode
,
9136 force_to_mode (XEXP (x
, 2), mode
,
9137 mask
, next_select
));
9138 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
9139 x
= simplify_gen_ternary (IF_THEN_ELSE
, xmode
,
9140 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
9148 /* Ensure we return a value of the proper mode. */
9149 return gen_lowpart_or_truncate (mode
, x
);
9152 /* Return nonzero if X is an expression that has one of two values depending on
9153 whether some other value is zero or nonzero. In that case, we return the
9154 value that is being tested, *PTRUE is set to the value if the rtx being
9155 returned has a nonzero value, and *PFALSE is set to the other alternative.
9157 If we return zero, we set *PTRUE and *PFALSE to X. */
9160 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9162 machine_mode mode
= GET_MODE (x
);
9163 enum rtx_code code
= GET_CODE (x
);
9164 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9165 unsigned HOST_WIDE_INT nz
;
9166 scalar_int_mode int_mode
;
9168 /* If we are comparing a value against zero, we are done. */
9169 if ((code
== NE
|| code
== EQ
)
9170 && XEXP (x
, 1) == const0_rtx
)
9172 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9173 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9177 /* If this is a unary operation whose operand has one of two values, apply
9178 our opcode to compute those values. */
9179 else if (UNARY_P (x
)
9180 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9182 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9183 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9184 GET_MODE (XEXP (x
, 0)));
9188 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9189 make can't possibly match and would suppress other optimizations. */
9190 else if (code
== COMPARE
)
9193 /* If this is a binary operation, see if either side has only one of two
9194 values. If either one does or if both do and they are conditional on
9195 the same value, compute the new true and false values. */
9196 else if (BINARY_P (x
))
9198 rtx op0
= XEXP (x
, 0);
9199 rtx op1
= XEXP (x
, 1);
9200 cond0
= if_then_else_cond (op0
, &true0
, &false0
);
9201 cond1
= if_then_else_cond (op1
, &true1
, &false1
);
9203 if ((cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
))
9204 && (REG_P (op0
) || REG_P (op1
)))
9206 /* Try to enable a simplification by undoing work done by
9207 if_then_else_cond if it converted a REG into something more
9212 true0
= false0
= op0
;
9217 true1
= false1
= op1
;
9221 if ((cond0
!= 0 || cond1
!= 0)
9222 && ! (cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
)))
9224 /* If if_then_else_cond returned zero, then true/false are the
9225 same rtl. We must copy one of them to prevent invalid rtl
9228 true0
= copy_rtx (true0
);
9229 else if (cond1
== 0)
9230 true1
= copy_rtx (true1
);
9232 if (COMPARISON_P (x
))
9234 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9236 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9241 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9242 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9245 return cond0
? cond0
: cond1
;
9248 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9249 operands is zero when the other is nonzero, and vice-versa,
9250 and STORE_FLAG_VALUE is 1 or -1. */
9252 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9253 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9255 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9257 rtx op0
= XEXP (XEXP (x
, 0), 1);
9258 rtx op1
= XEXP (XEXP (x
, 1), 1);
9260 cond0
= XEXP (XEXP (x
, 0), 0);
9261 cond1
= XEXP (XEXP (x
, 1), 0);
9263 if (COMPARISON_P (cond0
)
9264 && COMPARISON_P (cond1
)
9265 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9266 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9267 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9268 || ((swap_condition (GET_CODE (cond0
))
9269 == reversed_comparison_code (cond1
, NULL
))
9270 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9271 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9272 && ! side_effects_p (x
))
9274 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9275 *pfalse
= simplify_gen_binary (MULT
, mode
,
9277 ? simplify_gen_unary (NEG
, mode
,
9285 /* Similarly for MULT, AND and UMIN, except that for these the result
9287 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9288 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9289 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9291 cond0
= XEXP (XEXP (x
, 0), 0);
9292 cond1
= XEXP (XEXP (x
, 1), 0);
9294 if (COMPARISON_P (cond0
)
9295 && COMPARISON_P (cond1
)
9296 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9297 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9298 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9299 || ((swap_condition (GET_CODE (cond0
))
9300 == reversed_comparison_code (cond1
, NULL
))
9301 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9302 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9303 && ! side_effects_p (x
))
9305 *ptrue
= *pfalse
= const0_rtx
;
9311 else if (code
== IF_THEN_ELSE
)
9313 /* If we have IF_THEN_ELSE already, extract the condition and
9314 canonicalize it if it is NE or EQ. */
9315 cond0
= XEXP (x
, 0);
9316 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9317 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9318 return XEXP (cond0
, 0);
9319 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9321 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9322 return XEXP (cond0
, 0);
9328 /* If X is a SUBREG, we can narrow both the true and false values
9329 if the inner expression, if there is a condition. */
9330 else if (code
== SUBREG
9331 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9334 true0
= simplify_gen_subreg (mode
, true0
,
9335 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9336 false0
= simplify_gen_subreg (mode
, false0
,
9337 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9338 if (true0
&& false0
)
9346 /* If X is a constant, this isn't special and will cause confusions
9347 if we treat it as such. Likewise if it is equivalent to a constant. */
9348 else if (CONSTANT_P (x
)
9349 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9352 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9353 will be least confusing to the rest of the compiler. */
9354 else if (mode
== BImode
)
9356 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9360 /* If X is known to be either 0 or -1, those are the true and
9361 false values when testing X. */
9362 else if (x
== constm1_rtx
|| x
== const0_rtx
9363 || (is_a
<scalar_int_mode
> (mode
, &int_mode
)
9364 && (num_sign_bit_copies (x
, int_mode
)
9365 == GET_MODE_PRECISION (int_mode
))))
9367 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9371 /* Likewise for 0 or a single bit. */
9372 else if (HWI_COMPUTABLE_MODE_P (mode
)
9373 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9375 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9379 /* Otherwise fail; show no condition with true and false values the same. */
9380 *ptrue
= *pfalse
= x
;
9384 /* Return the value of expression X given the fact that condition COND
9385 is known to be true when applied to REG as its first operand and VAL
9386 as its second. X is known to not be shared and so can be modified in
9389 We only handle the simplest cases, and specifically those cases that
9390 arise with IF_THEN_ELSE expressions. */
9393 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9395 enum rtx_code code
= GET_CODE (x
);
9399 if (side_effects_p (x
))
9402 /* If either operand of the condition is a floating point value,
9403 then we have to avoid collapsing an EQ comparison. */
9405 && rtx_equal_p (x
, reg
)
9406 && ! FLOAT_MODE_P (GET_MODE (x
))
9407 && ! FLOAT_MODE_P (GET_MODE (val
)))
9410 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9413 /* If X is (abs REG) and we know something about REG's relationship
9414 with zero, we may be able to simplify this. */
9416 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9419 case GE
: case GT
: case EQ
:
9422 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9424 GET_MODE (XEXP (x
, 0)));
9429 /* The only other cases we handle are MIN, MAX, and comparisons if the
9430 operands are the same as REG and VAL. */
9432 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9434 if (rtx_equal_p (XEXP (x
, 0), val
))
9436 std::swap (val
, reg
);
9437 cond
= swap_condition (cond
);
9440 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9442 if (COMPARISON_P (x
))
9444 if (comparison_dominates_p (cond
, code
))
9445 return const_true_rtx
;
9447 code
= reversed_comparison_code (x
, NULL
);
9449 && comparison_dominates_p (cond
, code
))
9454 else if (code
== SMAX
|| code
== SMIN
9455 || code
== UMIN
|| code
== UMAX
)
9457 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9459 /* Do not reverse the condition when it is NE or EQ.
9460 This is because we cannot conclude anything about
9461 the value of 'SMAX (x, y)' when x is not equal to y,
9462 but we can when x equals y. */
9463 if ((code
== SMAX
|| code
== UMAX
)
9464 && ! (cond
== EQ
|| cond
== NE
))
9465 cond
= reverse_condition (cond
);
9470 return unsignedp
? x
: XEXP (x
, 1);
9472 return unsignedp
? x
: XEXP (x
, 0);
9474 return unsignedp
? XEXP (x
, 1) : x
;
9476 return unsignedp
? XEXP (x
, 0) : x
;
9483 else if (code
== SUBREG
)
9485 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9486 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9488 if (SUBREG_REG (x
) != r
)
9490 /* We must simplify subreg here, before we lose track of the
9491 original inner_mode. */
9492 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9493 inner_mode
, SUBREG_BYTE (x
));
9497 SUBST (SUBREG_REG (x
), r
);
9502 /* We don't have to handle SIGN_EXTEND here, because even in the
9503 case of replacing something with a modeless CONST_INT, a
9504 CONST_INT is already (supposed to be) a valid sign extension for
9505 its narrower mode, which implies it's already properly
9506 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9507 story is different. */
9508 else if (code
== ZERO_EXTEND
)
9510 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9511 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9513 if (XEXP (x
, 0) != r
)
9515 /* We must simplify the zero_extend here, before we lose
9516 track of the original inner_mode. */
9517 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9522 SUBST (XEXP (x
, 0), r
);
9528 fmt
= GET_RTX_FORMAT (code
);
9529 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9532 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9533 else if (fmt
[i
] == 'E')
9534 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9535 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9542 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9543 assignment as a field assignment. */
9546 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9548 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9550 if (paradoxical_subreg_p (GET_MODE (x
), GET_MODE (y
)))
9552 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9554 x
= adjust_address_nv (x
, GET_MODE (y
),
9555 byte_lowpart_offset (GET_MODE (y
),
9559 if (x
== y
|| rtx_equal_p (x
, y
))
9562 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9565 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9566 Note that all SUBREGs of MEM are paradoxical; otherwise they
9567 would have been rewritten. */
9568 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9569 && MEM_P (SUBREG_REG (y
))
9570 && rtx_equal_p (SUBREG_REG (y
),
9571 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9574 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9575 && MEM_P (SUBREG_REG (x
))
9576 && rtx_equal_p (SUBREG_REG (x
),
9577 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9580 /* We used to see if get_last_value of X and Y were the same but that's
9581 not correct. In one direction, we'll cause the assignment to have
9582 the wrong destination and in the case, we'll import a register into this
9583 insn that might have already have been dead. So fail if none of the
9584 above cases are true. */
9588 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9589 Return that assignment if so.
9591 We only handle the most common cases. */
9594 make_field_assignment (rtx x
)
9596 rtx dest
= SET_DEST (x
);
9597 rtx src
= SET_SRC (x
);
9602 unsigned HOST_WIDE_INT len
;
9605 /* All the rules in this function are specific to scalar integers. */
9606 scalar_int_mode mode
;
9607 if (!is_a
<scalar_int_mode
> (GET_MODE (dest
), &mode
))
9610 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9611 a clear of a one-bit field. We will have changed it to
9612 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9615 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9616 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9617 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9618 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9620 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9623 return gen_rtx_SET (assign
, const0_rtx
);
9627 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9628 && subreg_lowpart_p (XEXP (src
, 0))
9629 && partial_subreg_p (XEXP (src
, 0))
9630 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9631 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9632 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9633 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9635 assign
= make_extraction (VOIDmode
, dest
, 0,
9636 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9639 return gen_rtx_SET (assign
, const0_rtx
);
9643 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9645 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9646 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9647 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9649 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9652 return gen_rtx_SET (assign
, const1_rtx
);
9656 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9657 SRC is an AND with all bits of that field set, then we can discard
9659 if (GET_CODE (dest
) == ZERO_EXTRACT
9660 && CONST_INT_P (XEXP (dest
, 1))
9661 && GET_CODE (src
) == AND
9662 && CONST_INT_P (XEXP (src
, 1)))
9664 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9665 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9666 unsigned HOST_WIDE_INT ze_mask
;
9668 if (width
>= HOST_BITS_PER_WIDE_INT
)
9671 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9673 /* Complete overlap. We can remove the source AND. */
9674 if ((and_mask
& ze_mask
) == ze_mask
)
9675 return gen_rtx_SET (dest
, XEXP (src
, 0));
9677 /* Partial overlap. We can reduce the source AND. */
9678 if ((and_mask
& ze_mask
) != and_mask
)
9680 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9681 gen_int_mode (and_mask
& ze_mask
, mode
));
9682 return gen_rtx_SET (dest
, src
);
9686 /* The other case we handle is assignments into a constant-position
9687 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9688 a mask that has all one bits except for a group of zero bits and
9689 OTHER is known to have zeros where C1 has ones, this is such an
9690 assignment. Compute the position and length from C1. Shift OTHER
9691 to the appropriate position, force it to the required mode, and
9692 make the extraction. Check for the AND in both operands. */
9694 /* One or more SUBREGs might obscure the constant-position field
9695 assignment. The first one we are likely to encounter is an outer
9696 narrowing SUBREG, which we can just strip for the purposes of
9697 identifying the constant-field assignment. */
9698 scalar_int_mode src_mode
= mode
;
9699 if (GET_CODE (src
) == SUBREG
9700 && subreg_lowpart_p (src
)
9701 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (src
)), &src_mode
))
9702 src
= SUBREG_REG (src
);
9704 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9707 rhs
= expand_compound_operation (XEXP (src
, 0));
9708 lhs
= expand_compound_operation (XEXP (src
, 1));
9710 if (GET_CODE (rhs
) == AND
9711 && CONST_INT_P (XEXP (rhs
, 1))
9712 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9713 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9714 /* The second SUBREG that might get in the way is a paradoxical
9715 SUBREG around the first operand of the AND. We want to
9716 pretend the operand is as wide as the destination here. We
9717 do this by adjusting the MEM to wider mode for the sole
9718 purpose of the call to rtx_equal_for_field_assignment_p. Also
9719 note this trick only works for MEMs. */
9720 else if (GET_CODE (rhs
) == AND
9721 && paradoxical_subreg_p (XEXP (rhs
, 0))
9722 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9723 && CONST_INT_P (XEXP (rhs
, 1))
9724 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9726 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9727 else if (GET_CODE (lhs
) == AND
9728 && CONST_INT_P (XEXP (lhs
, 1))
9729 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9730 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9731 /* The second SUBREG that might get in the way is a paradoxical
9732 SUBREG around the first operand of the AND. We want to
9733 pretend the operand is as wide as the destination here. We
9734 do this by adjusting the MEM to wider mode for the sole
9735 purpose of the call to rtx_equal_for_field_assignment_p. Also
9736 note this trick only works for MEMs. */
9737 else if (GET_CODE (lhs
) == AND
9738 && paradoxical_subreg_p (XEXP (lhs
, 0))
9739 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9740 && CONST_INT_P (XEXP (lhs
, 1))
9741 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9743 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9747 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (mode
), &len
);
9749 || pos
+ len
> GET_MODE_PRECISION (mode
)
9750 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
9751 || (c1
& nonzero_bits (other
, mode
)) != 0)
9754 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9758 /* The mode to use for the source is the mode of the assignment, or of
9759 what is inside a possible STRICT_LOW_PART. */
9760 machine_mode new_mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9761 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9763 /* Shift OTHER right POS places and make it the source, restricting it
9764 to the proper length and mode. */
9766 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9767 src_mode
, other
, pos
),
9769 src
= force_to_mode (src
, new_mode
,
9770 len
>= HOST_BITS_PER_WIDE_INT
9772 : (HOST_WIDE_INT_1U
<< len
) - 1,
9775 /* If SRC is masked by an AND that does not make a difference in
9776 the value being stored, strip it. */
9777 if (GET_CODE (assign
) == ZERO_EXTRACT
9778 && CONST_INT_P (XEXP (assign
, 1))
9779 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9780 && GET_CODE (src
) == AND
9781 && CONST_INT_P (XEXP (src
, 1))
9782 && UINTVAL (XEXP (src
, 1))
9783 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9784 src
= XEXP (src
, 0);
9786 return gen_rtx_SET (assign
, src
);
9789 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9793 apply_distributive_law (rtx x
)
9795 enum rtx_code code
= GET_CODE (x
);
9796 enum rtx_code inner_code
;
9797 rtx lhs
, rhs
, other
;
9800 /* Distributivity is not true for floating point as it can change the
9801 value. So we don't do it unless -funsafe-math-optimizations. */
9802 if (FLOAT_MODE_P (GET_MODE (x
))
9803 && ! flag_unsafe_math_optimizations
)
9806 /* The outer operation can only be one of the following: */
9807 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9808 && code
!= PLUS
&& code
!= MINUS
)
9814 /* If either operand is a primitive we can't do anything, so get out
9816 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9819 lhs
= expand_compound_operation (lhs
);
9820 rhs
= expand_compound_operation (rhs
);
9821 inner_code
= GET_CODE (lhs
);
9822 if (inner_code
!= GET_CODE (rhs
))
9825 /* See if the inner and outer operations distribute. */
9832 /* These all distribute except over PLUS. */
9833 if (code
== PLUS
|| code
== MINUS
)
9838 if (code
!= PLUS
&& code
!= MINUS
)
9843 /* This is also a multiply, so it distributes over everything. */
9846 /* This used to handle SUBREG, but this turned out to be counter-
9847 productive, since (subreg (op ...)) usually is not handled by
9848 insn patterns, and this "optimization" therefore transformed
9849 recognizable patterns into unrecognizable ones. Therefore the
9850 SUBREG case was removed from here.
9852 It is possible that distributing SUBREG over arithmetic operations
9853 leads to an intermediate result than can then be optimized further,
9854 e.g. by moving the outer SUBREG to the other side of a SET as done
9855 in simplify_set. This seems to have been the original intent of
9856 handling SUBREGs here.
9858 However, with current GCC this does not appear to actually happen,
9859 at least on major platforms. If some case is found where removing
9860 the SUBREG case here prevents follow-on optimizations, distributing
9861 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9867 /* Set LHS and RHS to the inner operands (A and B in the example
9868 above) and set OTHER to the common operand (C in the example).
9869 There is only one way to do this unless the inner operation is
9871 if (COMMUTATIVE_ARITH_P (lhs
)
9872 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9873 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9874 else if (COMMUTATIVE_ARITH_P (lhs
)
9875 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9876 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9877 else if (COMMUTATIVE_ARITH_P (lhs
)
9878 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9879 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9880 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9881 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9885 /* Form the new inner operation, seeing if it simplifies first. */
9886 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9888 /* There is one exception to the general way of distributing:
9889 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9890 if (code
== XOR
&& inner_code
== IOR
)
9893 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9896 /* We may be able to continuing distributing the result, so call
9897 ourselves recursively on the inner operation before forming the
9898 outer operation, which we return. */
9899 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9900 apply_distributive_law (tem
), other
);
9903 /* See if X is of the form (* (+ A B) C), and if so convert to
9904 (+ (* A C) (* B C)) and try to simplify.
9906 Most of the time, this results in no change. However, if some of
9907 the operands are the same or inverses of each other, simplifications
9910 For example, (and (ior A B) (not B)) can occur as the result of
9911 expanding a bit field assignment. When we apply the distributive
9912 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9913 which then simplifies to (and (A (not B))).
9915 Note that no checks happen on the validity of applying the inverse
9916 distributive law. This is pointless since we can do it in the
9917 few places where this routine is called.
9919 N is the index of the term that is decomposed (the arithmetic operation,
9920 i.e. (+ A B) in the first example above). !N is the index of the term that
9921 is distributed, i.e. of C in the first example above. */
9923 distribute_and_simplify_rtx (rtx x
, int n
)
9926 enum rtx_code outer_code
, inner_code
;
9927 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9929 /* Distributivity is not true for floating point as it can change the
9930 value. So we don't do it unless -funsafe-math-optimizations. */
9931 if (FLOAT_MODE_P (GET_MODE (x
))
9932 && ! flag_unsafe_math_optimizations
)
9935 decomposed
= XEXP (x
, n
);
9936 if (!ARITHMETIC_P (decomposed
))
9939 mode
= GET_MODE (x
);
9940 outer_code
= GET_CODE (x
);
9941 distributed
= XEXP (x
, !n
);
9943 inner_code
= GET_CODE (decomposed
);
9944 inner_op0
= XEXP (decomposed
, 0);
9945 inner_op1
= XEXP (decomposed
, 1);
9947 /* Special case (and (xor B C) (not A)), which is equivalent to
9948 (xor (ior A B) (ior A C)) */
9949 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9951 distributed
= XEXP (distributed
, 0);
9957 /* Distribute the second term. */
9958 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9959 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9963 /* Distribute the first term. */
9964 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9965 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9968 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9970 if (GET_CODE (tmp
) != outer_code
9971 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
9972 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
9978 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9979 in MODE. Return an equivalent form, if different from (and VAROP
9980 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9983 simplify_and_const_int_1 (scalar_int_mode mode
, rtx varop
,
9984 unsigned HOST_WIDE_INT constop
)
9986 unsigned HOST_WIDE_INT nonzero
;
9987 unsigned HOST_WIDE_INT orig_constop
;
9992 orig_constop
= constop
;
9993 if (GET_CODE (varop
) == CLOBBER
)
9996 /* Simplify VAROP knowing that we will be only looking at some of the
9999 Note by passing in CONSTOP, we guarantee that the bits not set in
10000 CONSTOP are not significant and will never be examined. We must
10001 ensure that is the case by explicitly masking out those bits
10002 before returning. */
10003 varop
= force_to_mode (varop
, mode
, constop
, 0);
10005 /* If VAROP is a CLOBBER, we will fail so return it. */
10006 if (GET_CODE (varop
) == CLOBBER
)
10009 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10010 to VAROP and return the new constant. */
10011 if (CONST_INT_P (varop
))
10012 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
10014 /* See what bits may be nonzero in VAROP. Unlike the general case of
10015 a call to nonzero_bits, here we don't care about bits outside
10018 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
10020 /* Turn off all bits in the constant that are known to already be zero.
10021 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10022 which is tested below. */
10024 constop
&= nonzero
;
10026 /* If we don't have any bits left, return zero. */
10030 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10031 a power of two, we can replace this with an ASHIFT. */
10032 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
10033 && (i
= exact_log2 (constop
)) >= 0)
10034 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
10036 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10037 or XOR, then try to apply the distributive law. This may eliminate
10038 operations if either branch can be simplified because of the AND.
10039 It may also make some cases more complex, but those cases probably
10040 won't match a pattern either with or without this. */
10042 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
10044 scalar_int_mode varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10048 apply_distributive_law
10049 (simplify_gen_binary (GET_CODE (varop
), varop_mode
,
10050 simplify_and_const_int (NULL_RTX
, varop_mode
,
10053 simplify_and_const_int (NULL_RTX
, varop_mode
,
10058 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10059 the AND and see if one of the operands simplifies to zero. If so, we
10060 may eliminate it. */
10062 if (GET_CODE (varop
) == PLUS
10063 && pow2p_hwi (constop
+ 1))
10067 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
10068 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
10069 if (o0
== const0_rtx
)
10071 if (o1
== const0_rtx
)
10075 /* Make a SUBREG if necessary. If we can't make it, fail. */
10076 varop
= gen_lowpart (mode
, varop
);
10077 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10080 /* If we are only masking insignificant bits, return VAROP. */
10081 if (constop
== nonzero
)
10084 if (varop
== orig_varop
&& constop
== orig_constop
)
10087 /* Otherwise, return an AND. */
10088 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
10092 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10095 Return an equivalent form, if different from X. Otherwise, return X. If
10096 X is zero, we are to always construct the equivalent form. */
10099 simplify_and_const_int (rtx x
, scalar_int_mode mode
, rtx varop
,
10100 unsigned HOST_WIDE_INT constop
)
10102 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
10107 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
10108 gen_int_mode (constop
, mode
));
10109 if (GET_MODE (x
) != mode
)
10110 x
= gen_lowpart (mode
, x
);
10114 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10115 We don't care about bits outside of those defined in MODE.
10117 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10118 a shift, AND, or zero_extract, we can do better. */
10121 reg_nonzero_bits_for_combine (const_rtx x
, scalar_int_mode xmode
,
10122 scalar_int_mode mode
,
10123 unsigned HOST_WIDE_INT
*nonzero
)
10126 reg_stat_type
*rsp
;
10128 /* If X is a register whose nonzero bits value is current, use it.
10129 Otherwise, if X is a register whose value we can find, use that
10130 value. Otherwise, use the previously-computed global nonzero bits
10131 for this register. */
10133 rsp
= ®_stat
[REGNO (x
)];
10134 if (rsp
->last_set_value
!= 0
10135 && (rsp
->last_set_mode
== mode
10136 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
10137 && GET_MODE_CLASS (mode
) == MODE_INT
))
10138 && ((rsp
->last_set_label
>= label_tick_ebb_start
10139 && rsp
->last_set_label
< label_tick
)
10140 || (rsp
->last_set_label
== label_tick
10141 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10142 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10143 && REGNO (x
) < reg_n_sets_max
10144 && REG_N_SETS (REGNO (x
)) == 1
10145 && !REGNO_REG_SET_P
10146 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10149 /* Note that, even if the precision of last_set_mode is lower than that
10150 of mode, record_value_for_reg invoked nonzero_bits on the register
10151 with nonzero_bits_mode (because last_set_mode is necessarily integral
10152 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10153 are all valid, hence in mode too since nonzero_bits_mode is defined
10154 to the largest HWI_COMPUTABLE_MODE_P mode. */
10155 *nonzero
&= rsp
->last_set_nonzero_bits
;
10159 tem
= get_last_value (x
);
10162 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
10163 tem
= sign_extend_short_imm (tem
, xmode
, GET_MODE_PRECISION (mode
));
10168 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
10170 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
10172 if (GET_MODE_PRECISION (xmode
) < GET_MODE_PRECISION (mode
))
10173 /* We don't know anything about the upper bits. */
10174 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (xmode
);
10182 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10183 end of X that are known to be equal to the sign bit. X will be used
10184 in mode MODE; the returned value will always be between 1 and the
10185 number of bits in MODE. */
10188 reg_num_sign_bit_copies_for_combine (const_rtx x
, scalar_int_mode xmode
,
10189 scalar_int_mode mode
,
10190 unsigned int *result
)
10193 reg_stat_type
*rsp
;
10195 rsp
= ®_stat
[REGNO (x
)];
10196 if (rsp
->last_set_value
!= 0
10197 && rsp
->last_set_mode
== mode
10198 && ((rsp
->last_set_label
>= label_tick_ebb_start
10199 && rsp
->last_set_label
< label_tick
)
10200 || (rsp
->last_set_label
== label_tick
10201 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10202 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10203 && REGNO (x
) < reg_n_sets_max
10204 && REG_N_SETS (REGNO (x
)) == 1
10205 && !REGNO_REG_SET_P
10206 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10209 *result
= rsp
->last_set_sign_bit_copies
;
10213 tem
= get_last_value (x
);
10217 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10218 && GET_MODE_PRECISION (xmode
) == GET_MODE_PRECISION (mode
))
10219 *result
= rsp
->sign_bit_copies
;
10224 /* Return the number of "extended" bits there are in X, when interpreted
10225 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10226 unsigned quantities, this is the number of high-order zero bits.
10227 For signed quantities, this is the number of copies of the sign bit
10228 minus 1. In both case, this function returns the number of "spare"
10229 bits. For example, if two quantities for which this function returns
10230 at least 1 are added, the addition is known not to overflow.
10232 This function will always return 0 unless called during combine, which
10233 implies that it must be called from a define_split. */
10236 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10238 if (nonzero_sign_valid
== 0)
10241 scalar_int_mode int_mode
;
10243 ? (is_a
<scalar_int_mode
> (mode
, &int_mode
)
10244 && HWI_COMPUTABLE_MODE_P (int_mode
)
10245 ? (unsigned int) (GET_MODE_PRECISION (int_mode
) - 1
10246 - floor_log2 (nonzero_bits (x
, int_mode
)))
10248 : num_sign_bit_copies (x
, mode
) - 1);
10251 /* This function is called from `simplify_shift_const' to merge two
10252 outer operations. Specifically, we have already found that we need
10253 to perform operation *POP0 with constant *PCONST0 at the outermost
10254 position. We would now like to also perform OP1 with constant CONST1
10255 (with *POP0 being done last).
10257 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10258 the resulting operation. *PCOMP_P is set to 1 if we would need to
10259 complement the innermost operand, otherwise it is unchanged.
10261 MODE is the mode in which the operation will be done. No bits outside
10262 the width of this mode matter. It is assumed that the width of this mode
10263 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10265 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10266 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10267 result is simply *PCONST0.
10269 If the resulting operation cannot be expressed as one operation, we
10270 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10273 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10275 enum rtx_code op0
= *pop0
;
10276 HOST_WIDE_INT const0
= *pconst0
;
10278 const0
&= GET_MODE_MASK (mode
);
10279 const1
&= GET_MODE_MASK (mode
);
10281 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10285 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10288 if (op1
== UNKNOWN
|| op0
== SET
)
10291 else if (op0
== UNKNOWN
)
10292 op0
= op1
, const0
= const1
;
10294 else if (op0
== op1
)
10318 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10319 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10322 /* If the two constants aren't the same, we can't do anything. The
10323 remaining six cases can all be done. */
10324 else if (const0
!= const1
)
10332 /* (a & b) | b == b */
10334 else /* op1 == XOR */
10335 /* (a ^ b) | b == a | b */
10341 /* (a & b) ^ b == (~a) & b */
10342 op0
= AND
, *pcomp_p
= 1;
10343 else /* op1 == IOR */
10344 /* (a | b) ^ b == a & ~b */
10345 op0
= AND
, const0
= ~const0
;
10350 /* (a | b) & b == b */
10352 else /* op1 == XOR */
10353 /* (a ^ b) & b) == (~a) & b */
10360 /* Check for NO-OP cases. */
10361 const0
&= GET_MODE_MASK (mode
);
10363 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10365 else if (const0
== 0 && op0
== AND
)
10367 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10373 /* ??? Slightly redundant with the above mask, but not entirely.
10374 Moving this above means we'd have to sign-extend the mode mask
10375 for the final test. */
10376 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10377 *pconst0
= trunc_int_for_mode (const0
, mode
);
10382 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10383 the shift in. The original shift operation CODE is performed on OP in
10384 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10385 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10386 result of the shift is subject to operation OUTER_CODE with operand
10389 static scalar_int_mode
10390 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10391 scalar_int_mode orig_mode
, scalar_int_mode mode
,
10392 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10394 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10396 /* In general we can't perform in wider mode for right shift and rotate. */
10400 /* We can still widen if the bits brought in from the left are identical
10401 to the sign bit of ORIG_MODE. */
10402 if (num_sign_bit_copies (op
, mode
)
10403 > (unsigned) (GET_MODE_PRECISION (mode
)
10404 - GET_MODE_PRECISION (orig_mode
)))
10409 /* Similarly here but with zero bits. */
10410 if (HWI_COMPUTABLE_MODE_P (mode
)
10411 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10414 /* We can also widen if the bits brought in will be masked off. This
10415 operation is performed in ORIG_MODE. */
10416 if (outer_code
== AND
)
10418 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10421 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10430 gcc_unreachable ();
10437 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10438 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10439 if we cannot simplify it. Otherwise, return a simplified value.
10441 The shift is normally computed in the widest mode we find in VAROP, as
10442 long as it isn't a different number of words than RESULT_MODE. Exceptions
10443 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10446 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10447 rtx varop
, int orig_count
)
10449 enum rtx_code orig_code
= code
;
10450 rtx orig_varop
= varop
;
10452 machine_mode mode
= result_mode
;
10453 machine_mode shift_mode
;
10454 scalar_int_mode tmode
, inner_mode
, int_mode
, int_varop_mode
, int_result_mode
;
10455 unsigned int mode_words
10456 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10457 /* We form (outer_op (code varop count) (outer_const)). */
10458 enum rtx_code outer_op
= UNKNOWN
;
10459 HOST_WIDE_INT outer_const
= 0;
10460 int complement_p
= 0;
10463 /* Make sure and truncate the "natural" shift on the way in. We don't
10464 want to do this inside the loop as it makes it more difficult to
10466 if (SHIFT_COUNT_TRUNCATED
)
10467 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10469 /* If we were given an invalid count, don't do anything except exactly
10470 what was requested. */
10472 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10475 count
= orig_count
;
10477 /* Unless one of the branches of the `if' in this loop does a `continue',
10478 we will `break' the loop after the `if'. */
10482 /* If we have an operand of (clobber (const_int 0)), fail. */
10483 if (GET_CODE (varop
) == CLOBBER
)
10486 /* Convert ROTATERT to ROTATE. */
10487 if (code
== ROTATERT
)
10489 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10491 count
= bitsize
- count
;
10494 shift_mode
= result_mode
;
10495 if (shift_mode
!= mode
)
10497 /* We only change the modes of scalar shifts. */
10498 int_mode
= as_a
<scalar_int_mode
> (mode
);
10499 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10500 shift_mode
= try_widen_shift_mode (code
, varop
, count
,
10501 int_result_mode
, int_mode
,
10502 outer_op
, outer_const
);
10505 scalar_int_mode shift_unit_mode
10506 = as_a
<scalar_int_mode
> (GET_MODE_INNER (shift_mode
));
10508 /* Handle cases where the count is greater than the size of the mode
10509 minus 1. For ASHIFT, use the size minus one as the count (this can
10510 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10511 take the count modulo the size. For other shifts, the result is
10514 Since these shifts are being produced by the compiler by combining
10515 multiple operations, each of which are defined, we know what the
10516 result is supposed to be. */
10518 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10520 if (code
== ASHIFTRT
)
10521 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10522 else if (code
== ROTATE
|| code
== ROTATERT
)
10523 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10526 /* We can't simply return zero because there may be an
10528 varop
= const0_rtx
;
10534 /* If we discovered we had to complement VAROP, leave. Making a NOT
10535 here would cause an infinite loop. */
10539 if (shift_mode
== shift_unit_mode
)
10541 /* An arithmetic right shift of a quantity known to be -1 or 0
10543 if (code
== ASHIFTRT
10544 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10545 == GET_MODE_PRECISION (shift_unit_mode
)))
10551 /* If we are doing an arithmetic right shift and discarding all but
10552 the sign bit copies, this is equivalent to doing a shift by the
10553 bitsize minus one. Convert it into that shift because it will
10554 often allow other simplifications. */
10556 if (code
== ASHIFTRT
10557 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10558 >= GET_MODE_PRECISION (shift_unit_mode
)))
10559 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10561 /* We simplify the tests below and elsewhere by converting
10562 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10563 `make_compound_operation' will convert it to an ASHIFTRT for
10564 those machines (such as VAX) that don't have an LSHIFTRT. */
10565 if (code
== ASHIFTRT
10566 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10567 && val_signbit_known_clear_p (shift_unit_mode
,
10568 nonzero_bits (varop
,
10572 if (((code
== LSHIFTRT
10573 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10574 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10576 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10577 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10578 & GET_MODE_MASK (shift_unit_mode
))))
10579 && !side_effects_p (varop
))
10580 varop
= const0_rtx
;
10583 switch (GET_CODE (varop
))
10589 new_rtx
= expand_compound_operation (varop
);
10590 if (new_rtx
!= varop
)
10598 /* The following rules apply only to scalars. */
10599 if (shift_mode
!= shift_unit_mode
)
10601 int_mode
= as_a
<scalar_int_mode
> (mode
);
10603 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10604 minus the width of a smaller mode, we can do this with a
10605 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10606 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10607 && ! mode_dependent_address_p (XEXP (varop
, 0),
10608 MEM_ADDR_SPACE (varop
))
10609 && ! MEM_VOLATILE_P (varop
)
10610 && (int_mode_for_size (GET_MODE_BITSIZE (int_mode
) - count
, 1)
10613 new_rtx
= adjust_address_nv (varop
, tmode
,
10614 BYTES_BIG_ENDIAN
? 0
10615 : count
/ BITS_PER_UNIT
);
10617 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10618 : ZERO_EXTEND
, int_mode
, new_rtx
);
10625 /* The following rules apply only to scalars. */
10626 if (shift_mode
!= shift_unit_mode
)
10628 int_mode
= as_a
<scalar_int_mode
> (mode
);
10629 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10631 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10632 the same number of words as what we've seen so far. Then store
10633 the widest mode in MODE. */
10634 if (subreg_lowpart_p (varop
)
10635 && is_int_mode (GET_MODE (SUBREG_REG (varop
)), &inner_mode
)
10636 && GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_varop_mode
)
10637 && (unsigned int) ((GET_MODE_SIZE (inner_mode
)
10638 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10640 && GET_MODE_CLASS (int_varop_mode
) == MODE_INT
)
10642 varop
= SUBREG_REG (varop
);
10643 if (GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_mode
))
10650 /* Some machines use MULT instead of ASHIFT because MULT
10651 is cheaper. But it is still better on those machines to
10652 merge two shifts into one. */
10653 if (CONST_INT_P (XEXP (varop
, 1))
10654 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10657 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10659 GEN_INT (exact_log2 (
10660 UINTVAL (XEXP (varop
, 1)))));
10666 /* Similar, for when divides are cheaper. */
10667 if (CONST_INT_P (XEXP (varop
, 1))
10668 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10671 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10673 GEN_INT (exact_log2 (
10674 UINTVAL (XEXP (varop
, 1)))));
10680 /* If we are extracting just the sign bit of an arithmetic
10681 right shift, that shift is not needed. However, the sign
10682 bit of a wider mode may be different from what would be
10683 interpreted as the sign bit in a narrower mode, so, if
10684 the result is narrower, don't discard the shift. */
10685 if (code
== LSHIFTRT
10686 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10687 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10688 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10690 varop
= XEXP (varop
, 0);
10699 /* The following rules apply only to scalars. */
10700 if (shift_mode
!= shift_unit_mode
)
10702 int_mode
= as_a
<scalar_int_mode
> (mode
);
10703 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10704 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10706 /* Here we have two nested shifts. The result is usually the
10707 AND of a new shift with a mask. We compute the result below. */
10708 if (CONST_INT_P (XEXP (varop
, 1))
10709 && INTVAL (XEXP (varop
, 1)) >= 0
10710 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (int_varop_mode
)
10711 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
10712 && HWI_COMPUTABLE_MODE_P (int_mode
))
10714 enum rtx_code first_code
= GET_CODE (varop
);
10715 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10716 unsigned HOST_WIDE_INT mask
;
10719 /* We have one common special case. We can't do any merging if
10720 the inner code is an ASHIFTRT of a smaller mode. However, if
10721 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10722 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10723 we can convert it to
10724 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10725 This simplifies certain SIGN_EXTEND operations. */
10726 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10727 && count
== (GET_MODE_PRECISION (int_result_mode
)
10728 - GET_MODE_PRECISION (int_varop_mode
)))
10730 /* C3 has the low-order C1 bits zero. */
10732 mask
= GET_MODE_MASK (int_mode
)
10733 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10735 varop
= simplify_and_const_int (NULL_RTX
, int_result_mode
,
10736 XEXP (varop
, 0), mask
);
10737 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
,
10738 int_result_mode
, varop
, count
);
10739 count
= first_count
;
10744 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10745 than C1 high-order bits equal to the sign bit, we can convert
10746 this to either an ASHIFT or an ASHIFTRT depending on the
10749 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10751 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10752 && int_varop_mode
== shift_unit_mode
10753 && (num_sign_bit_copies (XEXP (varop
, 0), shift_unit_mode
)
10756 varop
= XEXP (varop
, 0);
10757 count
-= first_count
;
10767 /* There are some cases we can't do. If CODE is ASHIFTRT,
10768 we can only do this if FIRST_CODE is also ASHIFTRT.
10770 We can't do the case when CODE is ROTATE and FIRST_CODE is
10773 If the mode of this shift is not the mode of the outer shift,
10774 we can't do this if either shift is a right shift or ROTATE.
10776 Finally, we can't do any of these if the mode is too wide
10777 unless the codes are the same.
10779 Handle the case where the shift codes are the same
10782 if (code
== first_code
)
10784 if (int_varop_mode
!= int_result_mode
10785 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10786 || code
== ROTATE
))
10789 count
+= first_count
;
10790 varop
= XEXP (varop
, 0);
10794 if (code
== ASHIFTRT
10795 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10796 || GET_MODE_PRECISION (int_mode
) > HOST_BITS_PER_WIDE_INT
10797 || (int_varop_mode
!= int_result_mode
10798 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10799 || first_code
== ROTATE
10800 || code
== ROTATE
)))
10803 /* To compute the mask to apply after the shift, shift the
10804 nonzero bits of the inner shift the same way the
10805 outer shift will. */
10807 mask_rtx
= gen_int_mode (nonzero_bits (varop
, int_varop_mode
),
10811 = simplify_const_binary_operation (code
, int_result_mode
,
10812 mask_rtx
, GEN_INT (count
));
10814 /* Give up if we can't compute an outer operation to use. */
10816 || !CONST_INT_P (mask_rtx
)
10817 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10819 int_result_mode
, &complement_p
))
10822 /* If the shifts are in the same direction, we add the
10823 counts. Otherwise, we subtract them. */
10824 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10825 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10826 count
+= first_count
;
10828 count
-= first_count
;
10830 /* If COUNT is positive, the new shift is usually CODE,
10831 except for the two exceptions below, in which case it is
10832 FIRST_CODE. If the count is negative, FIRST_CODE should
10835 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10836 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10838 else if (count
< 0)
10839 code
= first_code
, count
= -count
;
10841 varop
= XEXP (varop
, 0);
10845 /* If we have (A << B << C) for any shift, we can convert this to
10846 (A << C << B). This wins if A is a constant. Only try this if
10847 B is not a constant. */
10849 else if (GET_CODE (varop
) == code
10850 && CONST_INT_P (XEXP (varop
, 0))
10851 && !CONST_INT_P (XEXP (varop
, 1)))
10853 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10854 sure the result will be masked. See PR70222. */
10855 if (code
== LSHIFTRT
10856 && int_mode
!= int_result_mode
10857 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10858 GET_MODE_MASK (int_result_mode
)
10859 >> orig_count
, int_result_mode
,
10862 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10863 up outer sign extension (often left and right shift) is
10864 hardly more efficient than the original. See PR70429. */
10865 if (code
== ASHIFTRT
&& int_mode
!= int_result_mode
)
10868 rtx new_rtx
= simplify_const_binary_operation (code
, int_mode
,
10871 varop
= gen_rtx_fmt_ee (code
, int_mode
, new_rtx
, XEXP (varop
, 1));
10878 /* The following rules apply only to scalars. */
10879 if (shift_mode
!= shift_unit_mode
)
10882 /* Make this fit the case below. */
10883 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10889 /* The following rules apply only to scalars. */
10890 if (shift_mode
!= shift_unit_mode
)
10892 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10893 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10895 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10896 with C the size of VAROP - 1 and the shift is logical if
10897 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10898 we have an (le X 0) operation. If we have an arithmetic shift
10899 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10900 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10902 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10903 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10904 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10905 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10906 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
10907 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10910 varop
= gen_rtx_LE (int_varop_mode
, XEXP (varop
, 1),
10913 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10914 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
10919 /* If we have (shift (logical)), move the logical to the outside
10920 to allow it to possibly combine with another logical and the
10921 shift to combine with another shift. This also canonicalizes to
10922 what a ZERO_EXTRACT looks like. Also, some machines have
10923 (and (shift)) insns. */
10925 if (CONST_INT_P (XEXP (varop
, 1))
10926 /* We can't do this if we have (ashiftrt (xor)) and the
10927 constant has its sign bit set in shift_unit_mode with
10928 shift_unit_mode wider than result_mode. */
10929 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10930 && int_result_mode
!= shift_unit_mode
10931 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10933 && (new_rtx
= simplify_const_binary_operation
10934 (code
, int_result_mode
,
10935 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
10936 GEN_INT (count
))) != 0
10937 && CONST_INT_P (new_rtx
)
10938 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10939 INTVAL (new_rtx
), int_result_mode
,
10942 varop
= XEXP (varop
, 0);
10946 /* If we can't do that, try to simplify the shift in each arm of the
10947 logical expression, make a new logical expression, and apply
10948 the inverse distributive law. This also can't be done for
10949 (ashiftrt (xor)) where we've widened the shift and the constant
10950 changes the sign bit. */
10951 if (CONST_INT_P (XEXP (varop
, 1))
10952 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10953 && int_result_mode
!= shift_unit_mode
10954 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10957 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
10958 XEXP (varop
, 0), count
);
10959 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
10960 XEXP (varop
, 1), count
);
10962 varop
= simplify_gen_binary (GET_CODE (varop
), shift_unit_mode
,
10964 varop
= apply_distributive_law (varop
);
10972 /* The following rules apply only to scalars. */
10973 if (shift_mode
!= shift_unit_mode
)
10975 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10977 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10978 says that the sign bit can be tested, FOO has mode MODE, C is
10979 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10980 that may be nonzero. */
10981 if (code
== LSHIFTRT
10982 && XEXP (varop
, 1) == const0_rtx
10983 && GET_MODE (XEXP (varop
, 0)) == int_result_mode
10984 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
10985 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
10986 && STORE_FLAG_VALUE
== -1
10987 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
10988 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
10989 int_result_mode
, &complement_p
))
10991 varop
= XEXP (varop
, 0);
10998 /* The following rules apply only to scalars. */
10999 if (shift_mode
!= shift_unit_mode
)
11001 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11003 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11004 than the number of bits in the mode is equivalent to A. */
11005 if (code
== LSHIFTRT
11006 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11007 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1)
11009 varop
= XEXP (varop
, 0);
11014 /* NEG commutes with ASHIFT since it is multiplication. Move the
11015 NEG outside to allow shifts to combine. */
11017 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0,
11018 int_result_mode
, &complement_p
))
11020 varop
= XEXP (varop
, 0);
11026 /* The following rules apply only to scalars. */
11027 if (shift_mode
!= shift_unit_mode
)
11029 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11031 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11032 is one less than the number of bits in the mode is
11033 equivalent to (xor A 1). */
11034 if (code
== LSHIFTRT
11035 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11036 && XEXP (varop
, 1) == constm1_rtx
11037 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
11038 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
11039 int_result_mode
, &complement_p
))
11042 varop
= XEXP (varop
, 0);
11046 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11047 that might be nonzero in BAR are those being shifted out and those
11048 bits are known zero in FOO, we can replace the PLUS with FOO.
11049 Similarly in the other operand order. This code occurs when
11050 we are computing the size of a variable-size array. */
11052 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11053 && count
< HOST_BITS_PER_WIDE_INT
11054 && nonzero_bits (XEXP (varop
, 1), int_result_mode
) >> count
== 0
11055 && (nonzero_bits (XEXP (varop
, 1), int_result_mode
)
11056 & nonzero_bits (XEXP (varop
, 0), int_result_mode
)) == 0)
11058 varop
= XEXP (varop
, 0);
11061 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11062 && count
< HOST_BITS_PER_WIDE_INT
11063 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
11064 && 0 == (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11066 && 0 == (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11067 & nonzero_bits (XEXP (varop
, 1), int_result_mode
)))
11069 varop
= XEXP (varop
, 1);
11073 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11075 && CONST_INT_P (XEXP (varop
, 1))
11076 && (new_rtx
= simplify_const_binary_operation
11077 (ASHIFT
, int_result_mode
,
11078 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11079 GEN_INT (count
))) != 0
11080 && CONST_INT_P (new_rtx
)
11081 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
11082 INTVAL (new_rtx
), int_result_mode
,
11085 varop
= XEXP (varop
, 0);
11089 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11090 signbit', and attempt to change the PLUS to an XOR and move it to
11091 the outer operation as is done above in the AND/IOR/XOR case
11092 leg for shift(logical). See details in logical handling above
11093 for reasoning in doing so. */
11094 if (code
== LSHIFTRT
11095 && CONST_INT_P (XEXP (varop
, 1))
11096 && mode_signbit_p (int_result_mode
, XEXP (varop
, 1))
11097 && (new_rtx
= simplify_const_binary_operation
11098 (code
, int_result_mode
,
11099 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11100 GEN_INT (count
))) != 0
11101 && CONST_INT_P (new_rtx
)
11102 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
11103 INTVAL (new_rtx
), int_result_mode
,
11106 varop
= XEXP (varop
, 0);
11113 /* The following rules apply only to scalars. */
11114 if (shift_mode
!= shift_unit_mode
)
11116 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
11118 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11119 with C the size of VAROP - 1 and the shift is logical if
11120 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11121 we have a (gt X 0) operation. If the shift is arithmetic with
11122 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11123 we have a (neg (gt X 0)) operation. */
11125 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
11126 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
11127 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
11128 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11129 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11130 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
11131 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11134 varop
= gen_rtx_GT (int_varop_mode
, XEXP (varop
, 1),
11137 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11138 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
11145 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11146 if the truncate does not affect the value. */
11147 if (code
== LSHIFTRT
11148 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
11149 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11150 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
11151 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
11152 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
11154 rtx varop_inner
= XEXP (varop
, 0);
11157 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
11158 XEXP (varop_inner
, 0),
11160 (count
+ INTVAL (XEXP (varop_inner
, 1))));
11161 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
11174 shift_mode
= result_mode
;
11175 if (shift_mode
!= mode
)
11177 /* We only change the modes of scalar shifts. */
11178 int_mode
= as_a
<scalar_int_mode
> (mode
);
11179 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11180 shift_mode
= try_widen_shift_mode (code
, varop
, count
, int_result_mode
,
11181 int_mode
, outer_op
, outer_const
);
11184 /* We have now finished analyzing the shift. The result should be
11185 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11186 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11187 to the result of the shift. OUTER_CONST is the relevant constant,
11188 but we must turn off all bits turned off in the shift. */
11190 if (outer_op
== UNKNOWN
11191 && orig_code
== code
&& orig_count
== count
11192 && varop
== orig_varop
11193 && shift_mode
== GET_MODE (varop
))
11196 /* Make a SUBREG if necessary. If we can't make it, fail. */
11197 varop
= gen_lowpart (shift_mode
, varop
);
11198 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11201 /* If we have an outer operation and we just made a shift, it is
11202 possible that we could have simplified the shift were it not
11203 for the outer operation. So try to do the simplification
11206 if (outer_op
!= UNKNOWN
)
11207 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11212 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
11214 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11215 turn off all the bits that the shift would have turned off. */
11216 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11217 /* We only change the modes of scalar shifts. */
11218 x
= simplify_and_const_int (NULL_RTX
, as_a
<scalar_int_mode
> (shift_mode
),
11219 x
, GET_MODE_MASK (result_mode
) >> orig_count
);
11221 /* Do the remainder of the processing in RESULT_MODE. */
11222 x
= gen_lowpart_or_truncate (result_mode
, x
);
11224 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11227 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11229 if (outer_op
!= UNKNOWN
)
11231 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11233 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11234 && GET_MODE_PRECISION (int_result_mode
) < HOST_BITS_PER_WIDE_INT
)
11235 outer_const
= trunc_int_for_mode (outer_const
, int_result_mode
);
11237 if (outer_op
== AND
)
11238 x
= simplify_and_const_int (NULL_RTX
, int_result_mode
, x
, outer_const
);
11239 else if (outer_op
== SET
)
11241 /* This means that we have determined that the result is
11242 equivalent to a constant. This should be rare. */
11243 if (!side_effects_p (x
))
11244 x
= GEN_INT (outer_const
);
11246 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11247 x
= simplify_gen_unary (outer_op
, int_result_mode
, x
, int_result_mode
);
11249 x
= simplify_gen_binary (outer_op
, int_result_mode
, x
,
11250 GEN_INT (outer_const
));
11256 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11257 The result of the shift is RESULT_MODE. If we cannot simplify it,
11258 return X or, if it is NULL, synthesize the expression with
11259 simplify_gen_binary. Otherwise, return a simplified value.
11261 The shift is normally computed in the widest mode we find in VAROP, as
11262 long as it isn't a different number of words than RESULT_MODE. Exceptions
11263 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11266 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11267 rtx varop
, int count
)
11269 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11274 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
11275 if (GET_MODE (x
) != result_mode
)
11276 x
= gen_lowpart (result_mode
, x
);
11281 /* A subroutine of recog_for_combine. See there for arguments and
11285 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11287 rtx pat
= *pnewpat
;
11288 rtx pat_without_clobbers
;
11289 int insn_code_number
;
11290 int num_clobbers_to_add
= 0;
11292 rtx notes
= NULL_RTX
;
11293 rtx old_notes
, old_pat
;
11296 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11297 we use to indicate that something didn't match. If we find such a
11298 thing, force rejection. */
11299 if (GET_CODE (pat
) == PARALLEL
)
11300 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11301 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11302 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11305 old_pat
= PATTERN (insn
);
11306 old_notes
= REG_NOTES (insn
);
11307 PATTERN (insn
) = pat
;
11308 REG_NOTES (insn
) = NULL_RTX
;
11310 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11311 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11313 if (insn_code_number
< 0)
11314 fputs ("Failed to match this instruction:\n", dump_file
);
11316 fputs ("Successfully matched this instruction:\n", dump_file
);
11317 print_rtl_single (dump_file
, pat
);
11320 /* If it isn't, there is the possibility that we previously had an insn
11321 that clobbered some register as a side effect, but the combined
11322 insn doesn't need to do that. So try once more without the clobbers
11323 unless this represents an ASM insn. */
11325 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11326 && GET_CODE (pat
) == PARALLEL
)
11330 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11331 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11334 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11338 SUBST_INT (XVECLEN (pat
, 0), pos
);
11341 pat
= XVECEXP (pat
, 0, 0);
11343 PATTERN (insn
) = pat
;
11344 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11345 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11347 if (insn_code_number
< 0)
11348 fputs ("Failed to match this instruction:\n", dump_file
);
11350 fputs ("Successfully matched this instruction:\n", dump_file
);
11351 print_rtl_single (dump_file
, pat
);
11355 pat_without_clobbers
= pat
;
11357 PATTERN (insn
) = old_pat
;
11358 REG_NOTES (insn
) = old_notes
;
11360 /* Recognize all noop sets, these will be killed by followup pass. */
11361 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11362 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11364 /* If we had any clobbers to add, make a new pattern than contains
11365 them. Then check to make sure that all of them are dead. */
11366 if (num_clobbers_to_add
)
11368 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11369 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11370 ? (XVECLEN (pat
, 0)
11371 + num_clobbers_to_add
)
11372 : num_clobbers_to_add
+ 1));
11374 if (GET_CODE (pat
) == PARALLEL
)
11375 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11376 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11378 XVECEXP (newpat
, 0, 0) = pat
;
11380 add_clobbers (newpat
, insn_code_number
);
11382 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11383 i
< XVECLEN (newpat
, 0); i
++)
11385 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11386 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11388 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11390 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11391 notes
= alloc_reg_note (REG_UNUSED
,
11392 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11398 if (insn_code_number
>= 0
11399 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11401 old_pat
= PATTERN (insn
);
11402 old_notes
= REG_NOTES (insn
);
11403 old_icode
= INSN_CODE (insn
);
11404 PATTERN (insn
) = pat
;
11405 REG_NOTES (insn
) = notes
;
11406 INSN_CODE (insn
) = insn_code_number
;
11408 /* Allow targets to reject combined insn. */
11409 if (!targetm
.legitimate_combined_insn (insn
))
11411 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11412 fputs ("Instruction not appropriate for target.",
11415 /* Callers expect recog_for_combine to strip
11416 clobbers from the pattern on failure. */
11417 pat
= pat_without_clobbers
;
11420 insn_code_number
= -1;
11423 PATTERN (insn
) = old_pat
;
11424 REG_NOTES (insn
) = old_notes
;
11425 INSN_CODE (insn
) = old_icode
;
11431 return insn_code_number
;
11434 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11435 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11436 Return whether anything was so changed. */
11439 change_zero_ext (rtx pat
)
11441 bool changed
= false;
11442 rtx
*src
= &SET_SRC (pat
);
11444 subrtx_ptr_iterator::array_type array
;
11445 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11448 scalar_int_mode mode
, inner_mode
;
11449 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
11453 if (GET_CODE (x
) == ZERO_EXTRACT
11454 && CONST_INT_P (XEXP (x
, 1))
11455 && CONST_INT_P (XEXP (x
, 2))
11456 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
)
11457 && GET_MODE_PRECISION (inner_mode
) <= GET_MODE_PRECISION (mode
))
11459 size
= INTVAL (XEXP (x
, 1));
11461 int start
= INTVAL (XEXP (x
, 2));
11462 if (BITS_BIG_ENDIAN
)
11463 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11466 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0), GEN_INT (start
));
11469 if (mode
!= inner_mode
)
11470 x
= gen_lowpart_SUBREG (mode
, x
);
11472 else if (GET_CODE (x
) == ZERO_EXTEND
11473 && GET_CODE (XEXP (x
, 0)) == SUBREG
11474 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11475 && !paradoxical_subreg_p (XEXP (x
, 0))
11476 && subreg_lowpart_p (XEXP (x
, 0)))
11478 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11479 size
= GET_MODE_PRECISION (inner_mode
);
11480 x
= SUBREG_REG (XEXP (x
, 0));
11481 if (GET_MODE (x
) != mode
)
11482 x
= gen_lowpart_SUBREG (mode
, x
);
11484 else if (GET_CODE (x
) == ZERO_EXTEND
11485 && REG_P (XEXP (x
, 0))
11486 && HARD_REGISTER_P (XEXP (x
, 0))
11487 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11489 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11490 size
= GET_MODE_PRECISION (inner_mode
);
11491 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11496 if (!(GET_CODE (x
) == LSHIFTRT
11497 && CONST_INT_P (XEXP (x
, 1))
11498 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11500 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11501 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11509 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11510 maybe_swap_commutative_operands (**iter
);
11512 rtx
*dst
= &SET_DEST (pat
);
11513 scalar_int_mode mode
;
11514 if (GET_CODE (*dst
) == ZERO_EXTRACT
11515 && REG_P (XEXP (*dst
, 0))
11516 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (*dst
, 0)), &mode
)
11517 && CONST_INT_P (XEXP (*dst
, 1))
11518 && CONST_INT_P (XEXP (*dst
, 2)))
11520 rtx reg
= XEXP (*dst
, 0);
11521 int width
= INTVAL (XEXP (*dst
, 1));
11522 int offset
= INTVAL (XEXP (*dst
, 2));
11523 int reg_width
= GET_MODE_PRECISION (mode
);
11524 if (BITS_BIG_ENDIAN
)
11525 offset
= reg_width
- width
- offset
;
11528 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11529 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11530 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11532 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11535 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11536 w
= gen_rtx_IOR (mode
, x
, z
);
11537 SUBST (SET_DEST (pat
), reg
);
11538 SUBST (SET_SRC (pat
), w
);
11546 /* Like recog, but we receive the address of a pointer to a new pattern.
11547 We try to match the rtx that the pointer points to.
11548 If that fails, we may try to modify or replace the pattern,
11549 storing the replacement into the same pointer object.
11551 Modifications include deletion or addition of CLOBBERs. If the
11552 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11553 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11554 (and undo if that fails).
11556 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11557 the CLOBBERs are placed.
11559 The value is the final insn code from the pattern ultimately matched,
11563 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11565 rtx pat
= *pnewpat
;
11566 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11567 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11568 return insn_code_number
;
11570 void *marker
= get_undo_marker ();
11571 bool changed
= false;
11573 if (GET_CODE (pat
) == SET
)
11574 changed
= change_zero_ext (pat
);
11575 else if (GET_CODE (pat
) == PARALLEL
)
11578 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11580 rtx set
= XVECEXP (pat
, 0, i
);
11581 if (GET_CODE (set
) == SET
)
11582 changed
|= change_zero_ext (set
);
11588 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11590 if (insn_code_number
< 0)
11591 undo_to_marker (marker
);
11594 return insn_code_number
;
11597 /* Like gen_lowpart_general but for use by combine. In combine it
11598 is not possible to create any new pseudoregs. However, it is
11599 safe to create invalid memory addresses, because combine will
11600 try to recognize them and all they will do is make the combine
11603 If for some reason this cannot do its job, an rtx
11604 (clobber (const_int 0)) is returned.
11605 An insn containing that will not be recognized. */
11608 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11610 machine_mode imode
= GET_MODE (x
);
11611 unsigned int osize
= GET_MODE_SIZE (omode
);
11612 unsigned int isize
= GET_MODE_SIZE (imode
);
11615 if (omode
== imode
)
11618 /* We can only support MODE being wider than a word if X is a
11619 constant integer or has a mode the same size. */
11620 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11621 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11624 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11625 won't know what to do. So we will strip off the SUBREG here and
11626 process normally. */
11627 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11629 x
= SUBREG_REG (x
);
11631 /* For use in case we fall down into the address adjustments
11632 further below, we need to adjust the known mode and size of
11633 x; imode and isize, since we just adjusted x. */
11634 imode
= GET_MODE (x
);
11636 if (imode
== omode
)
11639 isize
= GET_MODE_SIZE (imode
);
11642 result
= gen_lowpart_common (omode
, x
);
11649 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11651 if (MEM_VOLATILE_P (x
)
11652 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11655 /* If we want to refer to something bigger than the original memref,
11656 generate a paradoxical subreg instead. That will force a reload
11657 of the original memref X. */
11658 if (paradoxical_subreg_p (omode
, imode
))
11659 return gen_rtx_SUBREG (omode
, x
, 0);
11661 HOST_WIDE_INT offset
= byte_lowpart_offset (omode
, imode
);
11662 return adjust_address_nv (x
, omode
, offset
);
11665 /* If X is a comparison operator, rewrite it in a new mode. This
11666 probably won't match, but may allow further simplifications. */
11667 else if (COMPARISON_P (x
))
11668 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11670 /* If we couldn't simplify X any other way, just enclose it in a
11671 SUBREG. Normally, this SUBREG won't match, but some patterns may
11672 include an explicit SUBREG or we may simplify it further in combine. */
11677 if (imode
== VOIDmode
)
11679 imode
= int_mode_for_mode (omode
).require ();
11680 x
= gen_lowpart_common (imode
, x
);
11684 res
= lowpart_subreg (omode
, x
, imode
);
11690 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11693 /* Try to simplify a comparison between OP0 and a constant OP1,
11694 where CODE is the comparison code that will be tested, into a
11695 (CODE OP0 const0_rtx) form.
11697 The result is a possibly different comparison code to use.
11698 *POP1 may be updated. */
11700 static enum rtx_code
11701 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11702 rtx op0
, rtx
*pop1
)
11704 scalar_int_mode int_mode
;
11705 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11707 /* Get the constant we are comparing against and turn off all bits
11708 not on in our mode. */
11709 if (mode
!= VOIDmode
)
11710 const_op
= trunc_int_for_mode (const_op
, mode
);
11712 /* If we are comparing against a constant power of two and the value
11713 being compared can only have that single bit nonzero (e.g., it was
11714 `and'ed with that bit), we can replace this with a comparison
11717 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11718 || code
== LT
|| code
== LTU
)
11719 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11720 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11721 && pow2p_hwi (const_op
& GET_MODE_MASK (int_mode
))
11722 && (nonzero_bits (op0
, int_mode
)
11723 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (int_mode
))))
11725 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11729 /* Similarly, if we are comparing a value known to be either -1 or
11730 0 with -1, change it to the opposite comparison against zero. */
11732 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11733 || code
== GEU
|| code
== LTU
)
11734 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11735 && num_sign_bit_copies (op0
, int_mode
) == GET_MODE_PRECISION (int_mode
))
11737 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11741 /* Do some canonicalizations based on the comparison code. We prefer
11742 comparisons against zero and then prefer equality comparisons.
11743 If we can reduce the size of a constant, we will do that too. */
11747 /* < C is equivalent to <= (C - 1) */
11752 /* ... fall through to LE case below. */
11753 gcc_fallthrough ();
11759 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11766 /* If we are doing a <= 0 comparison on a value known to have
11767 a zero sign bit, we can replace this with == 0. */
11768 else if (const_op
== 0
11769 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11770 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11771 && (nonzero_bits (op0
, int_mode
)
11772 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11778 /* >= C is equivalent to > (C - 1). */
11783 /* ... fall through to GT below. */
11784 gcc_fallthrough ();
11790 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11797 /* If we are doing a > 0 comparison on a value known to have
11798 a zero sign bit, we can replace this with != 0. */
11799 else if (const_op
== 0
11800 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11801 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11802 && (nonzero_bits (op0
, int_mode
)
11803 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11809 /* < C is equivalent to <= (C - 1). */
11814 /* ... fall through ... */
11815 gcc_fallthrough ();
11817 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11818 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11819 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11820 && ((unsigned HOST_WIDE_INT
) const_op
11821 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11831 /* unsigned <= 0 is equivalent to == 0 */
11834 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11835 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11836 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11837 && ((unsigned HOST_WIDE_INT
) const_op
11838 == ((HOST_WIDE_INT_1U
11839 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1)))
11847 /* >= C is equivalent to > (C - 1). */
11852 /* ... fall through ... */
11853 gcc_fallthrough ();
11856 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11857 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11858 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11859 && ((unsigned HOST_WIDE_INT
) const_op
11860 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11870 /* unsigned > 0 is equivalent to != 0 */
11873 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11874 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11875 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11876 && ((unsigned HOST_WIDE_INT
) const_op
11877 == (HOST_WIDE_INT_1U
11878 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1))
11889 *pop1
= GEN_INT (const_op
);
11893 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11894 comparison code that will be tested.
11896 The result is a possibly different comparison code to use. *POP0 and
11897 *POP1 may be updated.
11899 It is possible that we might detect that a comparison is either always
11900 true or always false. However, we do not perform general constant
11901 folding in combine, so this knowledge isn't useful. Such tautologies
11902 should have been detected earlier. Hence we ignore all such cases. */
11904 static enum rtx_code
11905 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11911 scalar_int_mode mode
, inner_mode
, tmode
;
11912 opt_scalar_int_mode tmode_iter
;
11914 /* Try a few ways of applying the same transformation to both operands. */
11917 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11918 so check specially. */
11919 if (!WORD_REGISTER_OPERATIONS
11920 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11921 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11922 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11923 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11924 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11925 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11926 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &mode
)
11927 && (is_a
<scalar_int_mode
>
11928 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))), &inner_mode
))
11929 && inner_mode
== GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0)))
11930 && CONST_INT_P (XEXP (op0
, 1))
11931 && XEXP (op0
, 1) == XEXP (op1
, 1)
11932 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11933 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11934 && (INTVAL (XEXP (op0
, 1))
11935 == (GET_MODE_PRECISION (mode
)
11936 - GET_MODE_PRECISION (inner_mode
))))
11938 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11939 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11942 /* If both operands are the same constant shift, see if we can ignore the
11943 shift. We can if the shift is a rotate or if the bits shifted out of
11944 this shift are known to be zero for both inputs and if the type of
11945 comparison is compatible with the shift. */
11946 if (GET_CODE (op0
) == GET_CODE (op1
)
11947 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11948 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11949 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11950 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11951 || (GET_CODE (op0
) == ASHIFTRT
11952 && (code
!= GTU
&& code
!= LTU
11953 && code
!= GEU
&& code
!= LEU
)))
11954 && CONST_INT_P (XEXP (op0
, 1))
11955 && INTVAL (XEXP (op0
, 1)) >= 0
11956 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11957 && XEXP (op0
, 1) == XEXP (op1
, 1))
11959 machine_mode mode
= GET_MODE (op0
);
11960 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11961 int shift_count
= INTVAL (XEXP (op0
, 1));
11963 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11964 mask
&= (mask
>> shift_count
) << shift_count
;
11965 else if (GET_CODE (op0
) == ASHIFT
)
11966 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11968 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11969 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11970 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11975 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11976 SUBREGs are of the same mode, and, in both cases, the AND would
11977 be redundant if the comparison was done in the narrower mode,
11978 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11979 and the operand's possibly nonzero bits are 0xffffff01; in that case
11980 if we only care about QImode, we don't need the AND). This case
11981 occurs if the output mode of an scc insn is not SImode and
11982 STORE_FLAG_VALUE == 1 (e.g., the 386).
11984 Similarly, check for a case where the AND's are ZERO_EXTEND
11985 operations from some narrower mode even though a SUBREG is not
11988 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11989 && CONST_INT_P (XEXP (op0
, 1))
11990 && CONST_INT_P (XEXP (op1
, 1)))
11992 rtx inner_op0
= XEXP (op0
, 0);
11993 rtx inner_op1
= XEXP (op1
, 0);
11994 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11995 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11998 if (paradoxical_subreg_p (inner_op0
)
11999 && GET_CODE (inner_op1
) == SUBREG
12000 && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0
)))
12001 && (GET_MODE (SUBREG_REG (inner_op0
))
12002 == GET_MODE (SUBREG_REG (inner_op1
)))
12003 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
12004 GET_MODE (SUBREG_REG (inner_op0
)))))
12005 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
12006 GET_MODE (SUBREG_REG (inner_op1
))))))
12008 op0
= SUBREG_REG (inner_op0
);
12009 op1
= SUBREG_REG (inner_op1
);
12011 /* The resulting comparison is always unsigned since we masked
12012 off the original sign bit. */
12013 code
= unsigned_condition (code
);
12019 FOR_EACH_MODE_UNTIL (tmode
,
12020 as_a
<scalar_int_mode
> (GET_MODE (op0
)))
12021 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
12023 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
12024 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
12025 code
= unsigned_condition (code
);
12034 /* If both operands are NOT, we can strip off the outer operation
12035 and adjust the comparison code for swapped operands; similarly for
12036 NEG, except that this must be an equality comparison. */
12037 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
12038 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
12039 && (code
== EQ
|| code
== NE
)))
12040 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
12046 /* If the first operand is a constant, swap the operands and adjust the
12047 comparison code appropriately, but don't do this if the second operand
12048 is already a constant integer. */
12049 if (swap_commutative_operands_p (op0
, op1
))
12051 std::swap (op0
, op1
);
12052 code
= swap_condition (code
);
12055 /* We now enter a loop during which we will try to simplify the comparison.
12056 For the most part, we only are concerned with comparisons with zero,
12057 but some things may really be comparisons with zero but not start
12058 out looking that way. */
12060 while (CONST_INT_P (op1
))
12062 machine_mode raw_mode
= GET_MODE (op0
);
12063 scalar_int_mode int_mode
;
12064 int equality_comparison_p
;
12065 int sign_bit_comparison_p
;
12066 int unsigned_comparison_p
;
12067 HOST_WIDE_INT const_op
;
12069 /* We only want to handle integral modes. This catches VOIDmode,
12070 CCmode, and the floating-point modes. An exception is that we
12071 can handle VOIDmode if OP0 is a COMPARE or a comparison
12074 if (GET_MODE_CLASS (raw_mode
) != MODE_INT
12075 && ! (raw_mode
== VOIDmode
12076 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
12079 /* Try to simplify the compare to constant, possibly changing the
12080 comparison op, and/or changing op1 to zero. */
12081 code
= simplify_compare_const (code
, raw_mode
, op0
, &op1
);
12082 const_op
= INTVAL (op1
);
12084 /* Compute some predicates to simplify code below. */
12086 equality_comparison_p
= (code
== EQ
|| code
== NE
);
12087 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
12088 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
12091 /* If this is a sign bit comparison and we can do arithmetic in
12092 MODE, say that we will only be needing the sign bit of OP0. */
12093 if (sign_bit_comparison_p
12094 && is_a
<scalar_int_mode
> (raw_mode
, &int_mode
)
12095 && HWI_COMPUTABLE_MODE_P (int_mode
))
12096 op0
= force_to_mode (op0
, int_mode
,
12098 << (GET_MODE_PRECISION (int_mode
) - 1),
12101 if (COMPARISON_P (op0
))
12103 /* We can't do anything if OP0 is a condition code value, rather
12104 than an actual data value. */
12106 || CC0_P (XEXP (op0
, 0))
12107 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12110 /* Get the two operands being compared. */
12111 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12112 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12114 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12116 /* Check for the cases where we simply want the result of the
12117 earlier test or the opposite of that result. */
12118 if (code
== NE
|| code
== EQ
12119 || (val_signbit_known_set_p (raw_mode
, STORE_FLAG_VALUE
)
12120 && (code
== LT
|| code
== GE
)))
12122 enum rtx_code new_code
;
12123 if (code
== LT
|| code
== NE
)
12124 new_code
= GET_CODE (op0
);
12126 new_code
= reversed_comparison_code (op0
, NULL
);
12128 if (new_code
!= UNKNOWN
)
12139 if (raw_mode
== VOIDmode
)
12141 scalar_int_mode mode
= as_a
<scalar_int_mode
> (raw_mode
);
12143 /* Now try cases based on the opcode of OP0. If none of the cases
12144 does a "continue", we exit this loop immediately after the
12147 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
12148 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12149 switch (GET_CODE (op0
))
12152 /* If we are extracting a single bit from a variable position in
12153 a constant that has only a single bit set and are comparing it
12154 with zero, we can convert this into an equality comparison
12155 between the position and the location of the single bit. */
12156 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12157 have already reduced the shift count modulo the word size. */
12158 if (!SHIFT_COUNT_TRUNCATED
12159 && CONST_INT_P (XEXP (op0
, 0))
12160 && XEXP (op0
, 1) == const1_rtx
12161 && equality_comparison_p
&& const_op
== 0
12162 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
12164 if (BITS_BIG_ENDIAN
)
12165 i
= BITS_PER_WORD
- 1 - i
;
12167 op0
= XEXP (op0
, 2);
12171 /* Result is nonzero iff shift count is equal to I. */
12172 code
= reverse_condition (code
);
12179 tem
= expand_compound_operation (op0
);
12188 /* If testing for equality, we can take the NOT of the constant. */
12189 if (equality_comparison_p
12190 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
12192 op0
= XEXP (op0
, 0);
12197 /* If just looking at the sign bit, reverse the sense of the
12199 if (sign_bit_comparison_p
)
12201 op0
= XEXP (op0
, 0);
12202 code
= (code
== GE
? LT
: GE
);
12208 /* If testing for equality, we can take the NEG of the constant. */
12209 if (equality_comparison_p
12210 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
12212 op0
= XEXP (op0
, 0);
12217 /* The remaining cases only apply to comparisons with zero. */
12221 /* When X is ABS or is known positive,
12222 (neg X) is < 0 if and only if X != 0. */
12224 if (sign_bit_comparison_p
12225 && (GET_CODE (XEXP (op0
, 0)) == ABS
12226 || (mode_width
<= HOST_BITS_PER_WIDE_INT
12227 && (nonzero_bits (XEXP (op0
, 0), mode
)
12228 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12231 op0
= XEXP (op0
, 0);
12232 code
= (code
== LT
? NE
: EQ
);
12236 /* If we have NEG of something whose two high-order bits are the
12237 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12238 if (num_sign_bit_copies (op0
, mode
) >= 2)
12240 op0
= XEXP (op0
, 0);
12241 code
= swap_condition (code
);
12247 /* If we are testing equality and our count is a constant, we
12248 can perform the inverse operation on our RHS. */
12249 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12250 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
12251 op1
, XEXP (op0
, 1))) != 0)
12253 op0
= XEXP (op0
, 0);
12258 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12259 a particular bit. Convert it to an AND of a constant of that
12260 bit. This will be converted into a ZERO_EXTRACT. */
12261 if (const_op
== 0 && sign_bit_comparison_p
12262 && CONST_INT_P (XEXP (op0
, 1))
12263 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12265 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12268 - INTVAL (XEXP (op0
, 1)))));
12269 code
= (code
== LT
? NE
: EQ
);
12273 /* Fall through. */
12276 /* ABS is ignorable inside an equality comparison with zero. */
12277 if (const_op
== 0 && equality_comparison_p
)
12279 op0
= XEXP (op0
, 0);
12285 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12286 (compare FOO CONST) if CONST fits in FOO's mode and we
12287 are either testing inequality or have an unsigned
12288 comparison with ZERO_EXTEND or a signed comparison with
12289 SIGN_EXTEND. But don't do it if we don't have a compare
12290 insn of the given mode, since we'd have to revert it
12291 later on, and then we wouldn't know whether to sign- or
12293 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12294 && ! unsigned_comparison_p
12295 && HWI_COMPUTABLE_MODE_P (mode
)
12296 && trunc_int_for_mode (const_op
, mode
) == const_op
12297 && have_insn_for (COMPARE
, mode
))
12299 op0
= XEXP (op0
, 0);
12305 /* Check for the case where we are comparing A - C1 with C2, that is
12307 (subreg:MODE (plus (A) (-C1))) op (C2)
12309 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12310 comparison in the wider mode. One of the following two conditions
12311 must be true in order for this to be valid:
12313 1. The mode extension results in the same bit pattern being added
12314 on both sides and the comparison is equality or unsigned. As
12315 C2 has been truncated to fit in MODE, the pattern can only be
12318 2. The mode extension results in the sign bit being copied on
12321 The difficulty here is that we have predicates for A but not for
12322 (A - C1) so we need to check that C1 is within proper bounds so
12323 as to perturbate A as little as possible. */
12325 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12326 && subreg_lowpart_p (op0
)
12327 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op0
)),
12329 && GET_MODE_PRECISION (inner_mode
) > mode_width
12330 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12331 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12333 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12334 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12337 && (unsigned HOST_WIDE_INT
) c1
12338 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12339 && (equality_comparison_p
|| unsigned_comparison_p
)
12340 /* (A - C1) zero-extends if it is positive and sign-extends
12341 if it is negative, C2 both zero- and sign-extends. */
12342 && ((0 == (nonzero_bits (a
, inner_mode
)
12343 & ~GET_MODE_MASK (mode
))
12345 /* (A - C1) sign-extends if it is positive and 1-extends
12346 if it is negative, C2 both sign- and 1-extends. */
12347 || (num_sign_bit_copies (a
, inner_mode
)
12348 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12351 || ((unsigned HOST_WIDE_INT
) c1
12352 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12353 /* (A - C1) always sign-extends, like C2. */
12354 && num_sign_bit_copies (a
, inner_mode
)
12355 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12356 - (mode_width
- 1))))
12358 op0
= SUBREG_REG (op0
);
12363 /* If the inner mode is narrower and we are extracting the low part,
12364 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12365 if (paradoxical_subreg_p (op0
))
12367 else if (subreg_lowpart_p (op0
)
12368 && GET_MODE_CLASS (mode
) == MODE_INT
12369 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12370 && (code
== NE
|| code
== EQ
)
12371 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
12372 && !paradoxical_subreg_p (op0
)
12373 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
12374 & ~GET_MODE_MASK (mode
)) == 0)
12376 /* Remove outer subregs that don't do anything. */
12377 tem
= gen_lowpart (inner_mode
, op1
);
12379 if ((nonzero_bits (tem
, inner_mode
)
12380 & ~GET_MODE_MASK (mode
)) == 0)
12382 op0
= SUBREG_REG (op0
);
12394 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12395 && (unsigned_comparison_p
|| equality_comparison_p
)
12396 && HWI_COMPUTABLE_MODE_P (mode
)
12397 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12399 && have_insn_for (COMPARE
, mode
))
12401 op0
= XEXP (op0
, 0);
12407 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12408 this for equality comparisons due to pathological cases involving
12410 if (equality_comparison_p
12411 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12412 op1
, XEXP (op0
, 1))))
12414 op0
= XEXP (op0
, 0);
12419 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12420 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12421 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12423 op0
= XEXP (XEXP (op0
, 0), 0);
12424 code
= (code
== LT
? EQ
: NE
);
12430 /* We used to optimize signed comparisons against zero, but that
12431 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12432 arrive here as equality comparisons, or (GEU, LTU) are
12433 optimized away. No need to special-case them. */
12435 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12436 (eq B (minus A C)), whichever simplifies. We can only do
12437 this for equality comparisons due to pathological cases involving
12439 if (equality_comparison_p
12440 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
12441 XEXP (op0
, 1), op1
)))
12443 op0
= XEXP (op0
, 0);
12448 if (equality_comparison_p
12449 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12450 XEXP (op0
, 0), op1
)))
12452 op0
= XEXP (op0
, 1);
12457 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12458 of bits in X minus 1, is one iff X > 0. */
12459 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12460 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12461 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12462 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12464 op0
= XEXP (op0
, 1);
12465 code
= (code
== GE
? LE
: GT
);
12471 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12472 if C is zero or B is a constant. */
12473 if (equality_comparison_p
12474 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
12475 XEXP (op0
, 1), op1
)))
12477 op0
= XEXP (op0
, 0);
12485 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12487 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12488 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12489 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12491 op0
= XEXP (op0
, 1);
12492 code
= (code
== GE
? GT
: LE
);
12498 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12499 will be converted to a ZERO_EXTRACT later. */
12500 if (const_op
== 0 && equality_comparison_p
12501 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12502 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12504 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12505 XEXP (XEXP (op0
, 0), 1));
12506 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12510 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12511 zero and X is a comparison and C1 and C2 describe only bits set
12512 in STORE_FLAG_VALUE, we can compare with X. */
12513 if (const_op
== 0 && equality_comparison_p
12514 && mode_width
<= HOST_BITS_PER_WIDE_INT
12515 && CONST_INT_P (XEXP (op0
, 1))
12516 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12517 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12518 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12519 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12521 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12522 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12523 if ((~STORE_FLAG_VALUE
& mask
) == 0
12524 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12525 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12526 && COMPARISON_P (tem
))))
12528 op0
= XEXP (XEXP (op0
, 0), 0);
12533 /* If we are doing an equality comparison of an AND of a bit equal
12534 to the sign bit, replace this with a LT or GE comparison of
12535 the underlying value. */
12536 if (equality_comparison_p
12538 && CONST_INT_P (XEXP (op0
, 1))
12539 && mode_width
<= HOST_BITS_PER_WIDE_INT
12540 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12541 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12543 op0
= XEXP (op0
, 0);
12544 code
= (code
== EQ
? GE
: LT
);
12548 /* If this AND operation is really a ZERO_EXTEND from a narrower
12549 mode, the constant fits within that mode, and this is either an
12550 equality or unsigned comparison, try to do this comparison in
12555 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12556 -> (ne:DI (reg:SI 4) (const_int 0))
12558 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12559 known to hold a value of the required mode the
12560 transformation is invalid. */
12561 if ((equality_comparison_p
|| unsigned_comparison_p
)
12562 && CONST_INT_P (XEXP (op0
, 1))
12563 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12564 & GET_MODE_MASK (mode
))
12566 && const_op
>> i
== 0
12567 && int_mode_for_size (i
, 1).exists (&tmode
))
12569 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12573 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12574 fits in both M1 and M2 and the SUBREG is either paradoxical
12575 or represents the low part, permute the SUBREG and the AND
12577 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12578 && CONST_INT_P (XEXP (op0
, 1)))
12580 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12581 /* Require an integral mode, to avoid creating something like
12583 if ((is_a
<scalar_int_mode
>
12584 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))), &tmode
))
12585 /* It is unsafe to commute the AND into the SUBREG if the
12586 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12587 not defined. As originally written the upper bits
12588 have a defined value due to the AND operation.
12589 However, if we commute the AND inside the SUBREG then
12590 they no longer have defined values and the meaning of
12591 the code has been changed.
12592 Also C1 should not change value in the smaller mode,
12593 see PR67028 (a positive C1 can become negative in the
12594 smaller mode, so that the AND does no longer mask the
12596 && ((WORD_REGISTER_OPERATIONS
12597 && mode_width
> GET_MODE_PRECISION (tmode
)
12598 && mode_width
<= BITS_PER_WORD
12599 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12600 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12601 && subreg_lowpart_p (XEXP (op0
, 0))))
12602 && mode_width
<= HOST_BITS_PER_WIDE_INT
12603 && HWI_COMPUTABLE_MODE_P (tmode
)
12604 && (c1
& ~mask
) == 0
12605 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12607 && c1
!= GET_MODE_MASK (tmode
))
12609 op0
= simplify_gen_binary (AND
, tmode
,
12610 SUBREG_REG (XEXP (op0
, 0)),
12611 gen_int_mode (c1
, tmode
));
12612 op0
= gen_lowpart (mode
, op0
);
12617 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12618 if (const_op
== 0 && equality_comparison_p
12619 && XEXP (op0
, 1) == const1_rtx
12620 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12622 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12623 XEXP (XEXP (op0
, 0), 0), 1);
12624 code
= (code
== NE
? EQ
: NE
);
12628 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12629 (eq (and (lshiftrt X) 1) 0).
12630 Also handle the case where (not X) is expressed using xor. */
12631 if (const_op
== 0 && equality_comparison_p
12632 && XEXP (op0
, 1) == const1_rtx
12633 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12635 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12636 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12638 if (GET_CODE (shift_op
) == NOT
12639 || (GET_CODE (shift_op
) == XOR
12640 && CONST_INT_P (XEXP (shift_op
, 1))
12641 && CONST_INT_P (shift_count
)
12642 && HWI_COMPUTABLE_MODE_P (mode
)
12643 && (UINTVAL (XEXP (shift_op
, 1))
12644 == HOST_WIDE_INT_1U
12645 << INTVAL (shift_count
))))
12648 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12649 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12650 code
= (code
== NE
? EQ
: NE
);
12657 /* If we have (compare (ashift FOO N) (const_int C)) and
12658 the high order N bits of FOO (N+1 if an inequality comparison)
12659 are known to be zero, we can do this by comparing FOO with C
12660 shifted right N bits so long as the low-order N bits of C are
12662 if (CONST_INT_P (XEXP (op0
, 1))
12663 && INTVAL (XEXP (op0
, 1)) >= 0
12664 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12665 < HOST_BITS_PER_WIDE_INT
)
12666 && (((unsigned HOST_WIDE_INT
) const_op
12667 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12669 && mode_width
<= HOST_BITS_PER_WIDE_INT
12670 && (nonzero_bits (XEXP (op0
, 0), mode
)
12671 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12672 + ! equality_comparison_p
))) == 0)
12674 /* We must perform a logical shift, not an arithmetic one,
12675 as we want the top N bits of C to be zero. */
12676 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12678 temp
>>= INTVAL (XEXP (op0
, 1));
12679 op1
= gen_int_mode (temp
, mode
);
12680 op0
= XEXP (op0
, 0);
12684 /* If we are doing a sign bit comparison, it means we are testing
12685 a particular bit. Convert it to the appropriate AND. */
12686 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12687 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12689 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12692 - INTVAL (XEXP (op0
, 1)))));
12693 code
= (code
== LT
? NE
: EQ
);
12697 /* If this an equality comparison with zero and we are shifting
12698 the low bit to the sign bit, we can convert this to an AND of the
12700 if (const_op
== 0 && equality_comparison_p
12701 && CONST_INT_P (XEXP (op0
, 1))
12702 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12704 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12710 /* If this is an equality comparison with zero, we can do this
12711 as a logical shift, which might be much simpler. */
12712 if (equality_comparison_p
&& const_op
== 0
12713 && CONST_INT_P (XEXP (op0
, 1)))
12715 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12717 INTVAL (XEXP (op0
, 1)));
12721 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12722 do the comparison in a narrower mode. */
12723 if (! unsigned_comparison_p
12724 && CONST_INT_P (XEXP (op0
, 1))
12725 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12726 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12727 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12729 && (((unsigned HOST_WIDE_INT
) const_op
12730 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12731 <= GET_MODE_MASK (tmode
)))
12733 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12737 /* Likewise if OP0 is a PLUS of a sign extension with a
12738 constant, which is usually represented with the PLUS
12739 between the shifts. */
12740 if (! unsigned_comparison_p
12741 && CONST_INT_P (XEXP (op0
, 1))
12742 && GET_CODE (XEXP (op0
, 0)) == PLUS
12743 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12744 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12745 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12746 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12748 && (((unsigned HOST_WIDE_INT
) const_op
12749 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12750 <= GET_MODE_MASK (tmode
)))
12752 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12753 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12754 rtx new_const
= simplify_gen_binary (ASHIFTRT
, mode
,
12755 add_const
, XEXP (op0
, 1));
12757 op0
= simplify_gen_binary (PLUS
, tmode
,
12758 gen_lowpart (tmode
, inner
),
12765 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12766 the low order N bits of FOO are known to be zero, we can do this
12767 by comparing FOO with C shifted left N bits so long as no
12768 overflow occurs. Even if the low order N bits of FOO aren't known
12769 to be zero, if the comparison is >= or < we can use the same
12770 optimization and for > or <= by setting all the low
12771 order N bits in the comparison constant. */
12772 if (CONST_INT_P (XEXP (op0
, 1))
12773 && INTVAL (XEXP (op0
, 1)) > 0
12774 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12775 && mode_width
<= HOST_BITS_PER_WIDE_INT
12776 && (((unsigned HOST_WIDE_INT
) const_op
12777 + (GET_CODE (op0
) != LSHIFTRT
12778 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12781 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12783 unsigned HOST_WIDE_INT low_bits
12784 = (nonzero_bits (XEXP (op0
, 0), mode
)
12785 & ((HOST_WIDE_INT_1U
12786 << INTVAL (XEXP (op0
, 1))) - 1));
12787 if (low_bits
== 0 || !equality_comparison_p
)
12789 /* If the shift was logical, then we must make the condition
12791 if (GET_CODE (op0
) == LSHIFTRT
)
12792 code
= unsigned_condition (code
);
12794 const_op
= (unsigned HOST_WIDE_INT
) const_op
12795 << INTVAL (XEXP (op0
, 1));
12797 && (code
== GT
|| code
== GTU
12798 || code
== LE
|| code
== LEU
))
12800 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12801 op1
= GEN_INT (const_op
);
12802 op0
= XEXP (op0
, 0);
12807 /* If we are using this shift to extract just the sign bit, we
12808 can replace this with an LT or GE comparison. */
12810 && (equality_comparison_p
|| sign_bit_comparison_p
)
12811 && CONST_INT_P (XEXP (op0
, 1))
12812 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12814 op0
= XEXP (op0
, 0);
12815 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12827 /* Now make any compound operations involved in this comparison. Then,
12828 check for an outmost SUBREG on OP0 that is not doing anything or is
12829 paradoxical. The latter transformation must only be performed when
12830 it is known that the "extra" bits will be the same in op0 and op1 or
12831 that they don't matter. There are three cases to consider:
12833 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12834 care bits and we can assume they have any convenient value. So
12835 making the transformation is safe.
12837 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12838 In this case the upper bits of op0 are undefined. We should not make
12839 the simplification in that case as we do not know the contents of
12842 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12843 In that case we know those bits are zeros or ones. We must also be
12844 sure that they are the same as the upper bits of op1.
12846 We can never remove a SUBREG for a non-equality comparison because
12847 the sign bit is in a different place in the underlying object. */
12849 rtx_code op0_mco_code
= SET
;
12850 if (op1
== const0_rtx
)
12851 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
12853 op0
= make_compound_operation (op0
, op0_mco_code
);
12854 op1
= make_compound_operation (op1
, SET
);
12856 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12857 && is_int_mode (GET_MODE (op0
), &mode
)
12858 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12859 && (code
== NE
|| code
== EQ
))
12861 if (paradoxical_subreg_p (op0
))
12863 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12865 if (REG_P (SUBREG_REG (op0
)))
12867 op0
= SUBREG_REG (op0
);
12868 op1
= gen_lowpart (inner_mode
, op1
);
12871 else if (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
12872 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
12873 & ~GET_MODE_MASK (mode
)) == 0)
12875 tem
= gen_lowpart (inner_mode
, op1
);
12877 if ((nonzero_bits (tem
, inner_mode
) & ~GET_MODE_MASK (mode
)) == 0)
12878 op0
= SUBREG_REG (op0
), op1
= tem
;
12882 /* We now do the opposite procedure: Some machines don't have compare
12883 insns in all modes. If OP0's mode is an integer mode smaller than a
12884 word and we can't do a compare in that mode, see if there is a larger
12885 mode for which we can do the compare. There are a number of cases in
12886 which we can use the wider mode. */
12888 if (is_int_mode (GET_MODE (op0
), &mode
)
12889 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12890 && ! have_insn_for (COMPARE
, mode
))
12891 FOR_EACH_WIDER_MODE (tmode_iter
, mode
)
12893 tmode
= tmode_iter
.require ();
12894 if (!HWI_COMPUTABLE_MODE_P (tmode
))
12896 if (have_insn_for (COMPARE
, tmode
))
12900 /* If this is a test for negative, we can make an explicit
12901 test of the sign bit. Test this first so we can use
12902 a paradoxical subreg to extend OP0. */
12904 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12905 && HWI_COMPUTABLE_MODE_P (mode
))
12907 unsigned HOST_WIDE_INT sign
12908 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
12909 op0
= simplify_gen_binary (AND
, tmode
,
12910 gen_lowpart (tmode
, op0
),
12911 gen_int_mode (sign
, tmode
));
12912 code
= (code
== LT
) ? NE
: EQ
;
12916 /* If the only nonzero bits in OP0 and OP1 are those in the
12917 narrower mode and this is an equality or unsigned comparison,
12918 we can use the wider mode. Similarly for sign-extended
12919 values, in which case it is true for all comparisons. */
12920 zero_extended
= ((code
== EQ
|| code
== NE
12921 || code
== GEU
|| code
== GTU
12922 || code
== LEU
|| code
== LTU
)
12923 && (nonzero_bits (op0
, tmode
)
12924 & ~GET_MODE_MASK (mode
)) == 0
12925 && ((CONST_INT_P (op1
)
12926 || (nonzero_bits (op1
, tmode
)
12927 & ~GET_MODE_MASK (mode
)) == 0)));
12930 || ((num_sign_bit_copies (op0
, tmode
)
12931 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12932 - GET_MODE_PRECISION (mode
)))
12933 && (num_sign_bit_copies (op1
, tmode
)
12934 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12935 - GET_MODE_PRECISION (mode
)))))
12937 /* If OP0 is an AND and we don't have an AND in MODE either,
12938 make a new AND in the proper mode. */
12939 if (GET_CODE (op0
) == AND
12940 && !have_insn_for (AND
, mode
))
12941 op0
= simplify_gen_binary (AND
, tmode
,
12942 gen_lowpart (tmode
,
12944 gen_lowpart (tmode
,
12950 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
12952 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
12957 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
12959 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
12968 /* We may have changed the comparison operands. Re-canonicalize. */
12969 if (swap_commutative_operands_p (op0
, op1
))
12971 std::swap (op0
, op1
);
12972 code
= swap_condition (code
);
12975 /* If this machine only supports a subset of valid comparisons, see if we
12976 can convert an unsupported one into a supported one. */
12977 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12985 /* Utility function for record_value_for_reg. Count number of
12990 enum rtx_code code
= GET_CODE (x
);
12994 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12995 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12997 rtx x0
= XEXP (x
, 0);
12998 rtx x1
= XEXP (x
, 1);
13001 return 1 + 2 * count_rtxs (x0
);
13003 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
13004 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
13005 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13006 return 2 + 2 * count_rtxs (x0
)
13007 + count_rtxs (x
== XEXP (x1
, 0)
13008 ? XEXP (x1
, 1) : XEXP (x1
, 0));
13010 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
13011 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
13012 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13013 return 2 + 2 * count_rtxs (x1
)
13014 + count_rtxs (x
== XEXP (x0
, 0)
13015 ? XEXP (x0
, 1) : XEXP (x0
, 0));
13018 fmt
= GET_RTX_FORMAT (code
);
13019 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13021 ret
+= count_rtxs (XEXP (x
, i
));
13022 else if (fmt
[i
] == 'E')
13023 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13024 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
13029 /* Utility function for following routine. Called when X is part of a value
13030 being stored into last_set_value. Sets last_set_table_tick
13031 for each register mentioned. Similar to mention_regs in cse.c */
13034 update_table_tick (rtx x
)
13036 enum rtx_code code
= GET_CODE (x
);
13037 const char *fmt
= GET_RTX_FORMAT (code
);
13042 unsigned int regno
= REGNO (x
);
13043 unsigned int endregno
= END_REGNO (x
);
13046 for (r
= regno
; r
< endregno
; r
++)
13048 reg_stat_type
*rsp
= ®_stat
[r
];
13049 rsp
->last_set_table_tick
= label_tick
;
13055 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13058 /* Check for identical subexpressions. If x contains
13059 identical subexpression we only have to traverse one of
13061 if (i
== 0 && ARITHMETIC_P (x
))
13063 /* Note that at this point x1 has already been
13065 rtx x0
= XEXP (x
, 0);
13066 rtx x1
= XEXP (x
, 1);
13068 /* If x0 and x1 are identical then there is no need to
13073 /* If x0 is identical to a subexpression of x1 then while
13074 processing x1, x0 has already been processed. Thus we
13075 are done with x. */
13076 if (ARITHMETIC_P (x1
)
13077 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13080 /* If x1 is identical to a subexpression of x0 then we
13081 still have to process the rest of x0. */
13082 if (ARITHMETIC_P (x0
)
13083 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13085 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
13090 update_table_tick (XEXP (x
, i
));
13092 else if (fmt
[i
] == 'E')
13093 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13094 update_table_tick (XVECEXP (x
, i
, j
));
13097 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13098 are saying that the register is clobbered and we no longer know its
13099 value. If INSN is zero, don't update reg_stat[].last_set; this is
13100 only permitted with VALUE also zero and is used to invalidate the
13104 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
13106 unsigned int regno
= REGNO (reg
);
13107 unsigned int endregno
= END_REGNO (reg
);
13109 reg_stat_type
*rsp
;
13111 /* If VALUE contains REG and we have a previous value for REG, substitute
13112 the previous value. */
13113 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
13117 /* Set things up so get_last_value is allowed to see anything set up to
13119 subst_low_luid
= DF_INSN_LUID (insn
);
13120 tem
= get_last_value (reg
);
13122 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13123 it isn't going to be useful and will take a lot of time to process,
13124 so just use the CLOBBER. */
13128 if (ARITHMETIC_P (tem
)
13129 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
13130 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
13131 tem
= XEXP (tem
, 0);
13132 else if (count_occurrences (value
, reg
, 1) >= 2)
13134 /* If there are two or more occurrences of REG in VALUE,
13135 prevent the value from growing too much. */
13136 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
13137 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
13140 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
13144 /* For each register modified, show we don't know its value, that
13145 we don't know about its bitwise content, that its value has been
13146 updated, and that we don't know the location of the death of the
13148 for (i
= regno
; i
< endregno
; i
++)
13150 rsp
= ®_stat
[i
];
13153 rsp
->last_set
= insn
;
13155 rsp
->last_set_value
= 0;
13156 rsp
->last_set_mode
= VOIDmode
;
13157 rsp
->last_set_nonzero_bits
= 0;
13158 rsp
->last_set_sign_bit_copies
= 0;
13159 rsp
->last_death
= 0;
13160 rsp
->truncated_to_mode
= VOIDmode
;
13163 /* Mark registers that are being referenced in this value. */
13165 update_table_tick (value
);
13167 /* Now update the status of each register being set.
13168 If someone is using this register in this block, set this register
13169 to invalid since we will get confused between the two lives in this
13170 basic block. This makes using this register always invalid. In cse, we
13171 scan the table to invalidate all entries using this register, but this
13172 is too much work for us. */
13174 for (i
= regno
; i
< endregno
; i
++)
13176 rsp
= ®_stat
[i
];
13177 rsp
->last_set_label
= label_tick
;
13179 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
13180 rsp
->last_set_invalid
= 1;
13182 rsp
->last_set_invalid
= 0;
13185 /* The value being assigned might refer to X (like in "x++;"). In that
13186 case, we must replace it with (clobber (const_int 0)) to prevent
13188 rsp
= ®_stat
[regno
];
13189 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
13191 value
= copy_rtx (value
);
13192 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
13196 /* For the main register being modified, update the value, the mode, the
13197 nonzero bits, and the number of sign bit copies. */
13199 rsp
->last_set_value
= value
;
13203 machine_mode mode
= GET_MODE (reg
);
13204 subst_low_luid
= DF_INSN_LUID (insn
);
13205 rsp
->last_set_mode
= mode
;
13206 if (GET_MODE_CLASS (mode
) == MODE_INT
13207 && HWI_COMPUTABLE_MODE_P (mode
))
13208 mode
= nonzero_bits_mode
;
13209 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
13210 rsp
->last_set_sign_bit_copies
13211 = num_sign_bit_copies (value
, GET_MODE (reg
));
13215 /* Called via note_stores from record_dead_and_set_regs to handle one
13216 SET or CLOBBER in an insn. DATA is the instruction in which the
13217 set is occurring. */
13220 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13222 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13224 if (GET_CODE (dest
) == SUBREG
)
13225 dest
= SUBREG_REG (dest
);
13227 if (!record_dead_insn
)
13230 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13236 /* If we are setting the whole register, we know its value. Otherwise
13237 show that we don't know the value. We can handle SUBREG in
13239 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13240 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13241 else if (GET_CODE (setter
) == SET
13242 && GET_CODE (SET_DEST (setter
)) == SUBREG
13243 && SUBREG_REG (SET_DEST (setter
)) == dest
13244 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
13245 && subreg_lowpart_p (SET_DEST (setter
)))
13246 record_value_for_reg (dest
, record_dead_insn
,
13247 gen_lowpart (GET_MODE (dest
),
13248 SET_SRC (setter
)));
13250 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13252 else if (MEM_P (dest
)
13253 /* Ignore pushes, they clobber nothing. */
13254 && ! push_operand (dest
, GET_MODE (dest
)))
13255 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13258 /* Update the records of when each REG was most recently set or killed
13259 for the things done by INSN. This is the last thing done in processing
13260 INSN in the combiner loop.
13262 We update reg_stat[], in particular fields last_set, last_set_value,
13263 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13264 last_death, and also the similar information mem_last_set (which insn
13265 most recently modified memory) and last_call_luid (which insn was the
13266 most recent subroutine call). */
13269 record_dead_and_set_regs (rtx_insn
*insn
)
13274 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13276 if (REG_NOTE_KIND (link
) == REG_DEAD
13277 && REG_P (XEXP (link
, 0)))
13279 unsigned int regno
= REGNO (XEXP (link
, 0));
13280 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13282 for (i
= regno
; i
< endregno
; i
++)
13284 reg_stat_type
*rsp
;
13286 rsp
= ®_stat
[i
];
13287 rsp
->last_death
= insn
;
13290 else if (REG_NOTE_KIND (link
) == REG_INC
)
13291 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13296 hard_reg_set_iterator hrsi
;
13297 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
13299 reg_stat_type
*rsp
;
13301 rsp
= ®_stat
[i
];
13302 rsp
->last_set_invalid
= 1;
13303 rsp
->last_set
= insn
;
13304 rsp
->last_set_value
= 0;
13305 rsp
->last_set_mode
= VOIDmode
;
13306 rsp
->last_set_nonzero_bits
= 0;
13307 rsp
->last_set_sign_bit_copies
= 0;
13308 rsp
->last_death
= 0;
13309 rsp
->truncated_to_mode
= VOIDmode
;
13312 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13314 /* We can't combine into a call pattern. Remember, though, that
13315 the return value register is set at this LUID. We could
13316 still replace a register with the return value from the
13317 wrong subroutine call! */
13318 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
13321 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
13324 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13325 register present in the SUBREG, so for each such SUBREG go back and
13326 adjust nonzero and sign bit information of the registers that are
13327 known to have some zero/sign bits set.
13329 This is needed because when combine blows the SUBREGs away, the
13330 information on zero/sign bits is lost and further combines can be
13331 missed because of that. */
13334 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13336 struct insn_link
*links
;
13338 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13339 machine_mode mode
= GET_MODE (subreg
);
13341 if (!HWI_COMPUTABLE_MODE_P (mode
))
13344 for (links
= LOG_LINKS (insn
); links
;)
13346 reg_stat_type
*rsp
;
13348 insn
= links
->insn
;
13349 set
= single_set (insn
);
13351 if (! set
|| !REG_P (SET_DEST (set
))
13352 || REGNO (SET_DEST (set
)) != regno
13353 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13355 links
= links
->next
;
13359 rsp
= ®_stat
[regno
];
13360 if (rsp
->last_set
== insn
)
13362 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13363 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13366 if (REG_P (SET_SRC (set
)))
13368 regno
= REGNO (SET_SRC (set
));
13369 links
= LOG_LINKS (insn
);
13376 /* Check if X, a register, is known to contain a value already
13377 truncated to MODE. In this case we can use a subreg to refer to
13378 the truncated value even though in the generic case we would need
13379 an explicit truncation. */
13382 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13384 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13385 machine_mode truncated
= rsp
->truncated_to_mode
;
13388 || rsp
->truncation_label
< label_tick_ebb_start
)
13390 if (!partial_subreg_p (mode
, truncated
))
13392 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13397 /* If X is a hard reg or a subreg record the mode that the register is
13398 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13399 able to turn a truncate into a subreg using this information. Return true
13400 if traversing X is complete. */
13403 record_truncated_value (rtx x
)
13405 machine_mode truncated_mode
;
13406 reg_stat_type
*rsp
;
13408 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13410 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13411 truncated_mode
= GET_MODE (x
);
13413 if (!partial_subreg_p (truncated_mode
, original_mode
))
13416 truncated_mode
= GET_MODE (x
);
13417 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13420 x
= SUBREG_REG (x
);
13422 /* ??? For hard-regs we now record everything. We might be able to
13423 optimize this using last_set_mode. */
13424 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13425 truncated_mode
= GET_MODE (x
);
13429 rsp
= ®_stat
[REGNO (x
)];
13430 if (rsp
->truncated_to_mode
== 0
13431 || rsp
->truncation_label
< label_tick_ebb_start
13432 || partial_subreg_p (truncated_mode
, rsp
->truncated_to_mode
))
13434 rsp
->truncated_to_mode
= truncated_mode
;
13435 rsp
->truncation_label
= label_tick
;
13441 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13442 the modes they are used in. This can help truning TRUNCATEs into
13446 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13448 subrtx_var_iterator::array_type array
;
13449 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13450 if (record_truncated_value (*iter
))
13451 iter
.skip_subrtxes ();
13454 /* Scan X for promoted SUBREGs. For each one found,
13455 note what it implies to the registers used in it. */
13458 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13460 if (GET_CODE (x
) == SUBREG
13461 && SUBREG_PROMOTED_VAR_P (x
)
13462 && REG_P (SUBREG_REG (x
)))
13463 record_promoted_value (insn
, x
);
13466 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13469 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13473 check_promoted_subreg (insn
, XEXP (x
, i
));
13477 if (XVEC (x
, i
) != 0)
13478 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13479 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13485 /* Verify that all the registers and memory references mentioned in *LOC are
13486 still valid. *LOC was part of a value set in INSN when label_tick was
13487 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13488 the invalid references with (clobber (const_int 0)) and return 1. This
13489 replacement is useful because we often can get useful information about
13490 the form of a value (e.g., if it was produced by a shift that always
13491 produces -1 or 0) even though we don't know exactly what registers it
13492 was produced from. */
13495 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13498 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13499 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13504 unsigned int regno
= REGNO (x
);
13505 unsigned int endregno
= END_REGNO (x
);
13508 for (j
= regno
; j
< endregno
; j
++)
13510 reg_stat_type
*rsp
= ®_stat
[j
];
13511 if (rsp
->last_set_invalid
13512 /* If this is a pseudo-register that was only set once and not
13513 live at the beginning of the function, it is always valid. */
13514 || (! (regno
>= FIRST_PSEUDO_REGISTER
13515 && regno
< reg_n_sets_max
13516 && REG_N_SETS (regno
) == 1
13517 && (!REGNO_REG_SET_P
13518 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13520 && rsp
->last_set_label
> tick
))
13523 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13530 /* If this is a memory reference, make sure that there were no stores after
13531 it that might have clobbered the value. We don't have alias info, so we
13532 assume any store invalidates it. Moreover, we only have local UIDs, so
13533 we also assume that there were stores in the intervening basic blocks. */
13534 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13535 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13538 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13542 for (i
= 0; i
< len
; i
++)
13546 /* Check for identical subexpressions. If x contains
13547 identical subexpression we only have to traverse one of
13549 if (i
== 1 && ARITHMETIC_P (x
))
13551 /* Note that at this point x0 has already been checked
13552 and found valid. */
13553 rtx x0
= XEXP (x
, 0);
13554 rtx x1
= XEXP (x
, 1);
13556 /* If x0 and x1 are identical then x is also valid. */
13560 /* If x1 is identical to a subexpression of x0 then
13561 while checking x0, x1 has already been checked. Thus
13562 it is valid and so as x. */
13563 if (ARITHMETIC_P (x0
)
13564 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13567 /* If x0 is identical to a subexpression of x1 then x is
13568 valid iff the rest of x1 is valid. */
13569 if (ARITHMETIC_P (x1
)
13570 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13572 get_last_value_validate (&XEXP (x1
,
13573 x0
== XEXP (x1
, 0) ? 1 : 0),
13574 insn
, tick
, replace
);
13577 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13581 else if (fmt
[i
] == 'E')
13582 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13583 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13584 insn
, tick
, replace
) == 0)
13588 /* If we haven't found a reason for it to be invalid, it is valid. */
13592 /* Get the last value assigned to X, if known. Some registers
13593 in the value may be replaced with (clobber (const_int 0)) if their value
13594 is known longer known reliably. */
13597 get_last_value (const_rtx x
)
13599 unsigned int regno
;
13601 reg_stat_type
*rsp
;
13603 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13604 then convert it to the desired mode. If this is a paradoxical SUBREG,
13605 we cannot predict what values the "extra" bits might have. */
13606 if (GET_CODE (x
) == SUBREG
13607 && subreg_lowpart_p (x
)
13608 && !paradoxical_subreg_p (x
)
13609 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13610 return gen_lowpart (GET_MODE (x
), value
);
13616 rsp
= ®_stat
[regno
];
13617 value
= rsp
->last_set_value
;
13619 /* If we don't have a value, or if it isn't for this basic block and
13620 it's either a hard register, set more than once, or it's a live
13621 at the beginning of the function, return 0.
13623 Because if it's not live at the beginning of the function then the reg
13624 is always set before being used (is never used without being set).
13625 And, if it's set only once, and it's always set before use, then all
13626 uses must have the same last value, even if it's not from this basic
13630 || (rsp
->last_set_label
< label_tick_ebb_start
13631 && (regno
< FIRST_PSEUDO_REGISTER
13632 || regno
>= reg_n_sets_max
13633 || REG_N_SETS (regno
) != 1
13635 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13638 /* If the value was set in a later insn than the ones we are processing,
13639 we can't use it even if the register was only set once. */
13640 if (rsp
->last_set_label
== label_tick
13641 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13644 /* If fewer bits were set than what we are asked for now, we cannot use
13646 if (GET_MODE_PRECISION (rsp
->last_set_mode
)
13647 < GET_MODE_PRECISION (GET_MODE (x
)))
13650 /* If the value has all its registers valid, return it. */
13651 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13654 /* Otherwise, make a copy and replace any invalid register with
13655 (clobber (const_int 0)). If that fails for some reason, return 0. */
13657 value
= copy_rtx (value
);
13658 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13664 /* Define three variables used for communication between the following
13667 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13668 static int reg_dead_flag
;
13670 /* Function called via note_stores from reg_dead_at_p.
13672 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13673 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13676 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13678 unsigned int regno
, endregno
;
13683 regno
= REGNO (dest
);
13684 endregno
= END_REGNO (dest
);
13685 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13686 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13689 /* Return nonzero if REG is known to be dead at INSN.
13691 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13692 referencing REG, it is dead. If we hit a SET referencing REG, it is
13693 live. Otherwise, see if it is live or dead at the start of the basic
13694 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13695 must be assumed to be always live. */
13698 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13703 /* Set variables for reg_dead_at_p_1. */
13704 reg_dead_regno
= REGNO (reg
);
13705 reg_dead_endregno
= END_REGNO (reg
);
13709 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13710 we allow the machine description to decide whether use-and-clobber
13711 patterns are OK. */
13712 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13714 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13715 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13719 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13720 beginning of basic block. */
13721 block
= BLOCK_FOR_INSN (insn
);
13726 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13729 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13731 return reg_dead_flag
== 1 ? 1 : 0;
13733 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13737 if (insn
== BB_HEAD (block
))
13740 insn
= PREV_INSN (insn
);
13743 /* Look at live-in sets for the basic block that we were in. */
13744 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13745 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13751 /* Note hard registers in X that are used. */
13754 mark_used_regs_combine (rtx x
)
13756 RTX_CODE code
= GET_CODE (x
);
13757 unsigned int regno
;
13768 case ADDR_DIFF_VEC
:
13770 /* CC0 must die in the insn after it is set, so we don't need to take
13771 special note of it here. */
13776 /* If we are clobbering a MEM, mark any hard registers inside the
13777 address as used. */
13778 if (MEM_P (XEXP (x
, 0)))
13779 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13784 /* A hard reg in a wide mode may really be multiple registers.
13785 If so, mark all of them just like the first. */
13786 if (regno
< FIRST_PSEUDO_REGISTER
)
13788 /* None of this applies to the stack, frame or arg pointers. */
13789 if (regno
== STACK_POINTER_REGNUM
13790 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13791 && regno
== HARD_FRAME_POINTER_REGNUM
)
13792 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13793 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13794 || regno
== FRAME_POINTER_REGNUM
)
13797 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13803 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13805 rtx testreg
= SET_DEST (x
);
13807 while (GET_CODE (testreg
) == SUBREG
13808 || GET_CODE (testreg
) == ZERO_EXTRACT
13809 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13810 testreg
= XEXP (testreg
, 0);
13812 if (MEM_P (testreg
))
13813 mark_used_regs_combine (XEXP (testreg
, 0));
13815 mark_used_regs_combine (SET_SRC (x
));
13823 /* Recursively scan the operands of this expression. */
13826 const char *fmt
= GET_RTX_FORMAT (code
);
13828 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13831 mark_used_regs_combine (XEXP (x
, i
));
13832 else if (fmt
[i
] == 'E')
13836 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13837 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13843 /* Remove register number REGNO from the dead registers list of INSN.
13845 Return the note used to record the death, if there was one. */
13848 remove_death (unsigned int regno
, rtx_insn
*insn
)
13850 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13853 remove_note (insn
, note
);
13858 /* For each register (hardware or pseudo) used within expression X, if its
13859 death is in an instruction with luid between FROM_LUID (inclusive) and
13860 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13861 list headed by PNOTES.
13863 That said, don't move registers killed by maybe_kill_insn.
13865 This is done when X is being merged by combination into TO_INSN. These
13866 notes will then be distributed as needed. */
13869 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13874 enum rtx_code code
= GET_CODE (x
);
13878 unsigned int regno
= REGNO (x
);
13879 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13881 /* If we do not know where the register died, it may still die between
13882 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
13883 if (!where_dead
|| DF_INSN_LUID (where_dead
) >= DF_INSN_LUID (to_insn
))
13885 rtx_insn
*insn
= prev_real_insn (to_insn
);
13887 && BLOCK_FOR_INSN (insn
) == BLOCK_FOR_INSN (to_insn
)
13888 && DF_INSN_LUID (insn
) >= from_luid
)
13890 if (dead_or_set_regno_p (insn
, regno
))
13892 if (find_regno_note (insn
, REG_DEAD
, regno
))
13897 insn
= prev_real_insn (insn
);
13901 /* Don't move the register if it gets killed in between from and to. */
13902 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13903 && ! reg_referenced_p (x
, maybe_kill_insn
))
13907 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13908 && DF_INSN_LUID (where_dead
) >= from_luid
13909 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13911 rtx note
= remove_death (regno
, where_dead
);
13913 /* It is possible for the call above to return 0. This can occur
13914 when last_death points to I2 or I1 that we combined with.
13915 In that case make a new note.
13917 We must also check for the case where X is a hard register
13918 and NOTE is a death note for a range of hard registers
13919 including X. In that case, we must put REG_DEAD notes for
13920 the remaining registers in place of NOTE. */
13922 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13923 && partial_subreg_p (GET_MODE (x
), GET_MODE (XEXP (note
, 0))))
13925 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13926 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13927 unsigned int ourend
= END_REGNO (x
);
13930 for (i
= deadregno
; i
< deadend
; i
++)
13931 if (i
< regno
|| i
>= ourend
)
13932 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13935 /* If we didn't find any note, or if we found a REG_DEAD note that
13936 covers only part of the given reg, and we have a multi-reg hard
13937 register, then to be safe we must check for REG_DEAD notes
13938 for each register other than the first. They could have
13939 their own REG_DEAD notes lying around. */
13940 else if ((note
== 0
13942 && partial_subreg_p (GET_MODE (XEXP (note
, 0)),
13944 && regno
< FIRST_PSEUDO_REGISTER
13945 && REG_NREGS (x
) > 1)
13947 unsigned int ourend
= END_REGNO (x
);
13948 unsigned int i
, offset
;
13952 offset
= hard_regno_nregs (regno
, GET_MODE (XEXP (note
, 0)));
13956 for (i
= regno
+ offset
; i
< ourend
; i
++)
13957 move_deaths (regno_reg_rtx
[i
],
13958 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13961 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13963 XEXP (note
, 1) = *pnotes
;
13967 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13973 else if (GET_CODE (x
) == SET
)
13975 rtx dest
= SET_DEST (x
);
13977 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13979 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13980 that accesses one word of a multi-word item, some
13981 piece of everything register in the expression is used by
13982 this insn, so remove any old death. */
13983 /* ??? So why do we test for equality of the sizes? */
13985 if (GET_CODE (dest
) == ZERO_EXTRACT
13986 || GET_CODE (dest
) == STRICT_LOW_PART
13987 || (GET_CODE (dest
) == SUBREG
13988 && !read_modify_subreg_p (dest
)))
13990 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13994 /* If this is some other SUBREG, we know it replaces the entire
13995 value, so use that as the destination. */
13996 if (GET_CODE (dest
) == SUBREG
)
13997 dest
= SUBREG_REG (dest
);
13999 /* If this is a MEM, adjust deaths of anything used in the address.
14000 For a REG (the only other possibility), the entire value is
14001 being replaced so the old value is not used in this insn. */
14004 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
14009 else if (GET_CODE (x
) == CLOBBER
)
14012 len
= GET_RTX_LENGTH (code
);
14013 fmt
= GET_RTX_FORMAT (code
);
14015 for (i
= 0; i
< len
; i
++)
14020 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
14021 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
14024 else if (fmt
[i
] == 'e')
14025 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14029 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14030 pattern of an insn. X must be a REG. */
14033 reg_bitfield_target_p (rtx x
, rtx body
)
14037 if (GET_CODE (body
) == SET
)
14039 rtx dest
= SET_DEST (body
);
14041 unsigned int regno
, tregno
, endregno
, endtregno
;
14043 if (GET_CODE (dest
) == ZERO_EXTRACT
)
14044 target
= XEXP (dest
, 0);
14045 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
14046 target
= SUBREG_REG (XEXP (dest
, 0));
14050 if (GET_CODE (target
) == SUBREG
)
14051 target
= SUBREG_REG (target
);
14053 if (!REG_P (target
))
14056 tregno
= REGNO (target
), regno
= REGNO (x
);
14057 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
14058 return target
== x
;
14060 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
14061 endregno
= end_hard_regno (GET_MODE (x
), regno
);
14063 return endregno
> tregno
&& regno
< endtregno
;
14066 else if (GET_CODE (body
) == PARALLEL
)
14067 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
14068 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
14074 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14075 as appropriate. I3 and I2 are the insns resulting from the combination
14076 insns including FROM (I2 may be zero).
14078 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14079 not need REG_DEAD notes because they are being substituted for. This
14080 saves searching in the most common cases.
14082 Each note in the list is either ignored or placed on some insns, depending
14083 on the type of note. */
14086 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
14087 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
14089 rtx note
, next_note
;
14091 rtx_insn
*tem_insn
;
14093 for (note
= notes
; note
; note
= next_note
)
14095 rtx_insn
*place
= 0, *place2
= 0;
14097 next_note
= XEXP (note
, 1);
14098 switch (REG_NOTE_KIND (note
))
14102 /* Doesn't matter much where we put this, as long as it's somewhere.
14103 It is preferable to keep these notes on branches, which is most
14104 likely to be i3. */
14108 case REG_NON_LOCAL_GOTO
:
14113 gcc_assert (i2
&& JUMP_P (i2
));
14118 case REG_EH_REGION
:
14119 /* These notes must remain with the call or trapping instruction. */
14122 else if (i2
&& CALL_P (i2
))
14126 gcc_assert (cfun
->can_throw_non_call_exceptions
);
14127 if (may_trap_p (i3
))
14129 else if (i2
&& may_trap_p (i2
))
14131 /* ??? Otherwise assume we've combined things such that we
14132 can now prove that the instructions can't trap. Drop the
14133 note in this case. */
14137 case REG_ARGS_SIZE
:
14138 /* ??? How to distribute between i3-i1. Assume i3 contains the
14139 entire adjustment. Assert i3 contains at least some adjust. */
14140 if (!noop_move_p (i3
))
14142 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
14143 /* fixup_args_size_notes looks at REG_NORETURN note,
14144 so ensure the note is placed there first. */
14148 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
14149 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
14153 XEXP (n
, 1) = REG_NOTES (i3
);
14154 REG_NOTES (i3
) = n
;
14158 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
14159 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14160 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14161 gcc_assert (old_size
!= args_size
14163 && !ACCUMULATE_OUTGOING_ARGS
14164 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
14171 case REG_CALL_DECL
:
14172 case REG_CALL_NOCF_CHECK
:
14173 /* These notes must remain with the call. It should not be
14174 possible for both I2 and I3 to be a call. */
14179 gcc_assert (i2
&& CALL_P (i2
));
14185 /* Any clobbers for i3 may still exist, and so we must process
14186 REG_UNUSED notes from that insn.
14188 Any clobbers from i2 or i1 can only exist if they were added by
14189 recog_for_combine. In that case, recog_for_combine created the
14190 necessary REG_UNUSED notes. Trying to keep any original
14191 REG_UNUSED notes from these insns can cause incorrect output
14192 if it is for the same register as the original i3 dest.
14193 In that case, we will notice that the register is set in i3,
14194 and then add a REG_UNUSED note for the destination of i3, which
14195 is wrong. However, it is possible to have REG_UNUSED notes from
14196 i2 or i1 for register which were both used and clobbered, so
14197 we keep notes from i2 or i1 if they will turn into REG_DEAD
14200 /* If this register is set or clobbered in I3, put the note there
14201 unless there is one already. */
14202 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14204 if (from_insn
!= i3
)
14207 if (! (REG_P (XEXP (note
, 0))
14208 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14209 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14212 /* Otherwise, if this register is used by I3, then this register
14213 now dies here, so we must put a REG_DEAD note here unless there
14215 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14216 && ! (REG_P (XEXP (note
, 0))
14217 ? find_regno_note (i3
, REG_DEAD
,
14218 REGNO (XEXP (note
, 0)))
14219 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14221 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14225 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14226 but we can't tell which at this point. We must reset any
14227 expectations we had about the value that was previously
14228 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14229 and, if appropriate, restore its previous value, but we
14230 don't have enough information for that at this point. */
14233 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14235 /* Otherwise, if this register is now referenced in i2
14236 then the register used to be modified in one of the
14237 original insns. If it was i3 (say, in an unused
14238 parallel), it's now completely gone, so the note can
14239 be discarded. But if it was modified in i2, i1 or i0
14240 and we still reference it in i2, then we're
14241 referencing the previous value, and since the
14242 register was modified and REG_UNUSED, we know that
14243 the previous value is now dead. So, if we only
14244 reference the register in i2, we change the note to
14245 REG_DEAD, to reflect the previous value. However, if
14246 we're also setting or clobbering the register as
14247 scratch, we know (because the register was not
14248 referenced in i3) that it's unused, just as it was
14249 unused before, and we place the note in i2. */
14250 if (from_insn
!= i3
&& i2
&& INSN_P (i2
)
14251 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14253 if (!reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14254 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14255 if (! (REG_P (XEXP (note
, 0))
14256 ? find_regno_note (i2
, REG_NOTE_KIND (note
),
14257 REGNO (XEXP (note
, 0)))
14258 : find_reg_note (i2
, REG_NOTE_KIND (note
),
14269 /* These notes say something about results of an insn. We can
14270 only support them if they used to be on I3 in which case they
14271 remain on I3. Otherwise they are ignored.
14273 If the note refers to an expression that is not a constant, we
14274 must also ignore the note since we cannot tell whether the
14275 equivalence is still true. It might be possible to do
14276 slightly better than this (we only have a problem if I2DEST
14277 or I1DEST is present in the expression), but it doesn't
14278 seem worth the trouble. */
14280 if (from_insn
== i3
14281 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14286 /* These notes say something about how a register is used. They must
14287 be present on any use of the register in I2 or I3. */
14288 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14291 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14300 case REG_LABEL_TARGET
:
14301 case REG_LABEL_OPERAND
:
14302 /* This can show up in several ways -- either directly in the
14303 pattern, or hidden off in the constant pool with (or without?)
14304 a REG_EQUAL note. */
14305 /* ??? Ignore the without-reg_equal-note problem for now. */
14306 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14307 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14308 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14309 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14313 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14314 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14315 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14316 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14324 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14325 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14327 if (place
&& JUMP_P (place
)
14328 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14329 && (JUMP_LABEL (place
) == NULL
14330 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14332 rtx label
= JUMP_LABEL (place
);
14335 JUMP_LABEL (place
) = XEXP (note
, 0);
14336 else if (LABEL_P (label
))
14337 LABEL_NUSES (label
)--;
14340 if (place2
&& JUMP_P (place2
)
14341 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14342 && (JUMP_LABEL (place2
) == NULL
14343 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14345 rtx label
= JUMP_LABEL (place2
);
14348 JUMP_LABEL (place2
) = XEXP (note
, 0);
14349 else if (LABEL_P (label
))
14350 LABEL_NUSES (label
)--;
14356 /* This note says something about the value of a register prior
14357 to the execution of an insn. It is too much trouble to see
14358 if the note is still correct in all situations. It is better
14359 to simply delete it. */
14363 /* If we replaced the right hand side of FROM_INSN with a
14364 REG_EQUAL note, the original use of the dying register
14365 will not have been combined into I3 and I2. In such cases,
14366 FROM_INSN is guaranteed to be the first of the combined
14367 instructions, so we simply need to search back before
14368 FROM_INSN for the previous use or set of this register,
14369 then alter the notes there appropriately.
14371 If the register is used as an input in I3, it dies there.
14372 Similarly for I2, if it is nonzero and adjacent to I3.
14374 If the register is not used as an input in either I3 or I2
14375 and it is not one of the registers we were supposed to eliminate,
14376 there are two possibilities. We might have a non-adjacent I2
14377 or we might have somehow eliminated an additional register
14378 from a computation. For example, we might have had A & B where
14379 we discover that B will always be zero. In this case we will
14380 eliminate the reference to A.
14382 In both cases, we must search to see if we can find a previous
14383 use of A and put the death note there. */
14386 && from_insn
== i2mod
14387 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14388 tem_insn
= from_insn
;
14392 && CALL_P (from_insn
)
14393 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14395 else if (i2
&& reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14397 /* If the new I2 sets the same register that is marked
14398 dead in the note, we do not in general know where to
14399 put the note. One important case we _can_ handle is
14400 when the note comes from I3. */
14401 if (from_insn
== i3
)
14406 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14408 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14409 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14411 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14413 && reg_overlap_mentioned_p (XEXP (note
, 0),
14415 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14416 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14423 basic_block bb
= this_basic_block
;
14425 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14427 if (!NONDEBUG_INSN_P (tem_insn
))
14429 if (tem_insn
== BB_HEAD (bb
))
14434 /* If the register is being set at TEM_INSN, see if that is all
14435 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14436 into a REG_UNUSED note instead. Don't delete sets to
14437 global register vars. */
14438 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14439 || !global_regs
[REGNO (XEXP (note
, 0))])
14440 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14442 rtx set
= single_set (tem_insn
);
14443 rtx inner_dest
= 0;
14444 rtx_insn
*cc0_setter
= NULL
;
14447 for (inner_dest
= SET_DEST (set
);
14448 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14449 || GET_CODE (inner_dest
) == SUBREG
14450 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14451 inner_dest
= XEXP (inner_dest
, 0))
14454 /* Verify that it was the set, and not a clobber that
14455 modified the register.
14457 CC0 targets must be careful to maintain setter/user
14458 pairs. If we cannot delete the setter due to side
14459 effects, mark the user with an UNUSED note instead
14462 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14463 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14465 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14466 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14467 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14469 /* Move the notes and links of TEM_INSN elsewhere.
14470 This might delete other dead insns recursively.
14471 First set the pattern to something that won't use
14473 rtx old_notes
= REG_NOTES (tem_insn
);
14475 PATTERN (tem_insn
) = pc_rtx
;
14476 REG_NOTES (tem_insn
) = NULL
;
14478 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14479 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14480 distribute_links (LOG_LINKS (tem_insn
));
14482 unsigned int regno
= REGNO (XEXP (note
, 0));
14483 reg_stat_type
*rsp
= ®_stat
[regno
];
14484 if (rsp
->last_set
== tem_insn
)
14485 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14487 SET_INSN_DELETED (tem_insn
);
14488 if (tem_insn
== i2
)
14491 /* Delete the setter too. */
14494 PATTERN (cc0_setter
) = pc_rtx
;
14495 old_notes
= REG_NOTES (cc0_setter
);
14496 REG_NOTES (cc0_setter
) = NULL
;
14498 distribute_notes (old_notes
, cc0_setter
,
14500 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14501 distribute_links (LOG_LINKS (cc0_setter
));
14503 SET_INSN_DELETED (cc0_setter
);
14504 if (cc0_setter
== i2
)
14510 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14512 /* If there isn't already a REG_UNUSED note, put one
14513 here. Do not place a REG_DEAD note, even if
14514 the register is also used here; that would not
14515 match the algorithm used in lifetime analysis
14516 and can cause the consistency check in the
14517 scheduler to fail. */
14518 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14519 REGNO (XEXP (note
, 0))))
14524 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14525 || (CALL_P (tem_insn
)
14526 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14530 /* If we are doing a 3->2 combination, and we have a
14531 register which formerly died in i3 and was not used
14532 by i2, which now no longer dies in i3 and is used in
14533 i2 but does not die in i2, and place is between i2
14534 and i3, then we may need to move a link from place to
14536 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14538 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14539 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14541 struct insn_link
*links
= LOG_LINKS (place
);
14542 LOG_LINKS (place
) = NULL
;
14543 distribute_links (links
);
14548 if (tem_insn
== BB_HEAD (bb
))
14554 /* If the register is set or already dead at PLACE, we needn't do
14555 anything with this note if it is still a REG_DEAD note.
14556 We check here if it is set at all, not if is it totally replaced,
14557 which is what `dead_or_set_p' checks, so also check for it being
14560 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14562 unsigned int regno
= REGNO (XEXP (note
, 0));
14563 reg_stat_type
*rsp
= ®_stat
[regno
];
14565 if (dead_or_set_p (place
, XEXP (note
, 0))
14566 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14568 /* Unless the register previously died in PLACE, clear
14569 last_death. [I no longer understand why this is
14571 if (rsp
->last_death
!= place
)
14572 rsp
->last_death
= 0;
14576 rsp
->last_death
= place
;
14578 /* If this is a death note for a hard reg that is occupying
14579 multiple registers, ensure that we are still using all
14580 parts of the object. If we find a piece of the object
14581 that is unused, we must arrange for an appropriate REG_DEAD
14582 note to be added for it. However, we can't just emit a USE
14583 and tag the note to it, since the register might actually
14584 be dead; so we recourse, and the recursive call then finds
14585 the previous insn that used this register. */
14587 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14589 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14590 bool all_used
= true;
14593 for (i
= regno
; i
< endregno
; i
++)
14594 if ((! refers_to_regno_p (i
, PATTERN (place
))
14595 && ! find_regno_fusage (place
, USE
, i
))
14596 || dead_or_set_regno_p (place
, i
))
14604 /* Put only REG_DEAD notes for pieces that are
14605 not already dead or set. */
14607 for (i
= regno
; i
< endregno
;
14608 i
+= hard_regno_nregs (i
, reg_raw_mode
[i
]))
14610 rtx piece
= regno_reg_rtx
[i
];
14611 basic_block bb
= this_basic_block
;
14613 if (! dead_or_set_p (place
, piece
)
14614 && ! reg_bitfield_target_p (piece
,
14617 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14620 distribute_notes (new_note
, place
, place
,
14621 NULL
, NULL_RTX
, NULL_RTX
,
14624 else if (! refers_to_regno_p (i
, PATTERN (place
))
14625 && ! find_regno_fusage (place
, USE
, i
))
14626 for (tem_insn
= PREV_INSN (place
); ;
14627 tem_insn
= PREV_INSN (tem_insn
))
14629 if (!NONDEBUG_INSN_P (tem_insn
))
14631 if (tem_insn
== BB_HEAD (bb
))
14635 if (dead_or_set_p (tem_insn
, piece
)
14636 || reg_bitfield_target_p (piece
,
14637 PATTERN (tem_insn
)))
14639 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14652 /* Any other notes should not be present at this point in the
14654 gcc_unreachable ();
14659 XEXP (note
, 1) = REG_NOTES (place
);
14660 REG_NOTES (place
) = note
;
14662 /* Set added_notes_insn to the earliest insn we added a note to. */
14663 if (added_notes_insn
== 0
14664 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place
))
14665 added_notes_insn
= place
;
14670 add_shallow_copy_of_reg_note (place2
, note
);
14672 /* Set added_notes_insn to the earliest insn we added a note to. */
14673 if (added_notes_insn
== 0
14674 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place2
))
14675 added_notes_insn
= place2
;
14680 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14681 I3, I2, and I1 to new locations. This is also called to add a link
14682 pointing at I3 when I3's destination is changed. */
14685 distribute_links (struct insn_link
*links
)
14687 struct insn_link
*link
, *next_link
;
14689 for (link
= links
; link
; link
= next_link
)
14691 rtx_insn
*place
= 0;
14695 next_link
= link
->next
;
14697 /* If the insn that this link points to is a NOTE, ignore it. */
14698 if (NOTE_P (link
->insn
))
14702 rtx pat
= PATTERN (link
->insn
);
14703 if (GET_CODE (pat
) == SET
)
14705 else if (GET_CODE (pat
) == PARALLEL
)
14708 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14710 set
= XVECEXP (pat
, 0, i
);
14711 if (GET_CODE (set
) != SET
)
14714 reg
= SET_DEST (set
);
14715 while (GET_CODE (reg
) == ZERO_EXTRACT
14716 || GET_CODE (reg
) == STRICT_LOW_PART
14717 || GET_CODE (reg
) == SUBREG
)
14718 reg
= XEXP (reg
, 0);
14723 if (REGNO (reg
) == link
->regno
)
14726 if (i
== XVECLEN (pat
, 0))
14732 reg
= SET_DEST (set
);
14734 while (GET_CODE (reg
) == ZERO_EXTRACT
14735 || GET_CODE (reg
) == STRICT_LOW_PART
14736 || GET_CODE (reg
) == SUBREG
)
14737 reg
= XEXP (reg
, 0);
14739 /* A LOG_LINK is defined as being placed on the first insn that uses
14740 a register and points to the insn that sets the register. Start
14741 searching at the next insn after the target of the link and stop
14742 when we reach a set of the register or the end of the basic block.
14744 Note that this correctly handles the link that used to point from
14745 I3 to I2. Also note that not much searching is typically done here
14746 since most links don't point very far away. */
14748 for (insn
= NEXT_INSN (link
->insn
);
14749 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14750 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14751 insn
= NEXT_INSN (insn
))
14752 if (DEBUG_INSN_P (insn
))
14754 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14756 if (reg_referenced_p (reg
, PATTERN (insn
)))
14760 else if (CALL_P (insn
)
14761 && find_reg_fusage (insn
, USE
, reg
))
14766 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14769 /* If we found a place to put the link, place it there unless there
14770 is already a link to the same insn as LINK at that point. */
14774 struct insn_link
*link2
;
14776 FOR_EACH_LOG_LINK (link2
, place
)
14777 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14782 link
->next
= LOG_LINKS (place
);
14783 LOG_LINKS (place
) = link
;
14785 /* Set added_links_insn to the earliest insn we added a
14787 if (added_links_insn
== 0
14788 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14789 added_links_insn
= place
;
14795 /* Check for any register or memory mentioned in EQUIV that is not
14796 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14797 of EXPR where some registers may have been replaced by constants. */
14800 unmentioned_reg_p (rtx equiv
, rtx expr
)
14802 subrtx_iterator::array_type array
;
14803 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14805 const_rtx x
= *iter
;
14806 if ((REG_P (x
) || MEM_P (x
))
14807 && !reg_mentioned_p (x
, expr
))
14813 DEBUG_FUNCTION
void
14814 dump_combine_stats (FILE *file
)
14818 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14819 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14823 dump_combine_total_stats (FILE *file
)
14827 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14828 total_attempts
, total_merges
, total_extras
, total_successes
);
14831 /* Try combining insns through substitution. */
14832 static unsigned int
14833 rest_of_handle_combine (void)
14835 int rebuild_jump_labels_after_combine
;
14837 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14838 df_note_add_problem ();
14841 regstat_init_n_sets_and_refs ();
14842 reg_n_sets_max
= max_reg_num ();
14844 rebuild_jump_labels_after_combine
14845 = combine_instructions (get_insns (), max_reg_num ());
14847 /* Combining insns may have turned an indirect jump into a
14848 direct jump. Rebuild the JUMP_LABEL fields of jumping
14850 if (rebuild_jump_labels_after_combine
)
14852 if (dom_info_available_p (CDI_DOMINATORS
))
14853 free_dominance_info (CDI_DOMINATORS
);
14854 timevar_push (TV_JUMP
);
14855 rebuild_jump_labels (get_insns ());
14857 timevar_pop (TV_JUMP
);
14860 regstat_free_n_sets_and_refs ();
14866 const pass_data pass_data_combine
=
14868 RTL_PASS
, /* type */
14869 "combine", /* name */
14870 OPTGROUP_NONE
, /* optinfo_flags */
14871 TV_COMBINE
, /* tv_id */
14872 PROP_cfglayout
, /* properties_required */
14873 0, /* properties_provided */
14874 0, /* properties_destroyed */
14875 0, /* todo_flags_start */
14876 TODO_df_finish
, /* todo_flags_finish */
14879 class pass_combine
: public rtl_opt_pass
14882 pass_combine (gcc::context
*ctxt
)
14883 : rtl_opt_pass (pass_data_combine
, ctxt
)
14886 /* opt_pass methods: */
14887 virtual bool gate (function
*) { return (optimize
> 0); }
14888 virtual unsigned int execute (function
*)
14890 return rest_of_handle_combine ();
14893 }; // class pass_combine
14895 } // anon namespace
14898 make_pass_combine (gcc::context
*ctxt
)
14900 return new pass_combine (ctxt
);