1 /* Target Code for TI C6X
2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
3 Contributed by Andrew Jenner <andrew@codesourcery.com>
4 Contributed by Bernd Schmidt <bernds@codesourcery.com>
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
26 #include "coretypes.h"
31 #include "gimple-expr.h"
36 #include "stringpool.h"
43 #include "diagnostic-core.h"
44 #include "stor-layout.h"
48 #include "insn-attr.h"
52 #include "sched-int.h"
53 #include "tm-constrs.h"
54 #include "langhooks.h"
55 #include "sel-sched.h"
57 #include "hw-doloop.h"
58 #include "regrename.h"
62 /* This file should be included last. */
63 #include "target-def.h"
65 /* Table of supported architecture variants. */
69 enum c6x_cpu_type type
;
70 unsigned short features
;
73 /* A list of all ISAs, mapping each one to a representative device.
74 Used for -march selection. */
75 static const c6x_arch_table all_isas
[] =
77 #define C6X_ISA(NAME,DEVICE,FLAGS) \
78 { NAME, DEVICE, FLAGS },
79 #include "c6x-isas.def"
81 { NULL
, C6X_CPU_C62X
, 0 }
84 /* This is the parsed result of the "-march=" option, if given. */
85 enum c6x_cpu_type c6x_arch
= C6X_DEFAULT_ARCH
;
87 /* A mask of insn types that are allowed by the architecture selected by
89 unsigned long c6x_insn_mask
= C6X_DEFAULT_INSN_MASK
;
91 /* The instruction that is being output (as obtained from FINAL_PRESCAN_INSN).
93 static rtx_insn
*c6x_current_insn
= NULL
;
95 /* A decl we build to access __c6xabi_DSBT_base. */
96 static GTY(()) tree dsbt_decl
;
98 /* Determines whether we run our final scheduling pass or not. We always
99 avoid the normal second scheduling pass. */
100 static int c6x_flag_schedule_insns2
;
102 /* Determines whether we run variable tracking in machine dependent
104 static int c6x_flag_var_tracking
;
106 /* Determines whether we use modulo scheduling. */
107 static int c6x_flag_modulo_sched
;
109 /* Record the state of flag_pic before we set it to 1 for DSBT. */
110 int c6x_initial_flag_pic
;
114 /* We record the clock cycle for every insn during scheduling. */
116 /* After scheduling, we run assign_reservations to choose unit
117 reservations for all insns. These are recorded here. */
119 /* Records the new condition for insns which must be made
120 conditional after scheduling. An entry of NULL_RTX means no such
121 change is necessary. */
123 /* True for the first insn that was scheduled in an ebb. */
125 /* The scheduler state after the insn, transformed into a mask of UNIT_QID
126 bits rather than storing the state. Meaningful only for the last
128 unsigned int unit_mask
;
129 } c6x_sched_insn_info
;
132 /* Record a c6x_sched_insn_info structure for every insn in the function. */
133 static vec
<c6x_sched_insn_info
> insn_info
;
135 #define INSN_INFO_LENGTH (insn_info).length ()
136 #define INSN_INFO_ENTRY(N) (insn_info[(N)])
138 static bool done_cfi_sections
;
140 #define RESERVATION_FLAG_D 1
141 #define RESERVATION_FLAG_L 2
142 #define RESERVATION_FLAG_S 4
143 #define RESERVATION_FLAG_M 8
144 #define RESERVATION_FLAG_DL (RESERVATION_FLAG_D | RESERVATION_FLAG_L)
145 #define RESERVATION_FLAG_DS (RESERVATION_FLAG_D | RESERVATION_FLAG_S)
146 #define RESERVATION_FLAG_LS (RESERVATION_FLAG_L | RESERVATION_FLAG_S)
147 #define RESERVATION_FLAG_DLS (RESERVATION_FLAG_D | RESERVATION_FLAG_LS)
149 /* The DFA names of the units. */
150 static const char *const c6x_unit_names
[] =
152 "d1", "l1", "s1", "m1", "fps1", "fpl1", "adddps1", "adddpl1",
153 "d2", "l2", "s2", "m2", "fps2", "fpl2", "adddps2", "adddpl2"
156 /* The DFA unit number for each unit in c6x_unit_names[]. */
157 static int c6x_unit_codes
[ARRAY_SIZE (c6x_unit_names
)];
159 /* Unit query IDs. */
160 #define UNIT_QID_D1 0
161 #define UNIT_QID_L1 1
162 #define UNIT_QID_S1 2
163 #define UNIT_QID_M1 3
164 #define UNIT_QID_FPS1 4
165 #define UNIT_QID_FPL1 5
166 #define UNIT_QID_ADDDPS1 6
167 #define UNIT_QID_ADDDPL1 7
168 #define UNIT_QID_SIDE_OFFSET 8
170 #define RESERVATION_S1 2
171 #define RESERVATION_S2 10
173 /* An enum for the unit requirements we count in the UNIT_REQS table. */
189 /* A table used to count unit requirements. Used when computing minimum
190 iteration intervals. */
191 typedef int unit_req_table
[2][UNIT_REQ_MAX
];
192 static unit_req_table unit_reqs
;
194 /* Register map for debugging. */
195 unsigned const dbx_register_map
[FIRST_PSEUDO_REGISTER
] =
197 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, /* A0 - A15. */
198 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, /* A16 - A32. */
200 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, /* B0 - B15. */
202 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, /* B16 - B32. */
204 -1, -1, -1 /* FP, ARGP, ILC. */
207 /* Allocate a new, cleared machine_function structure. */
209 static struct machine_function
*
210 c6x_init_machine_status (void)
212 return ggc_cleared_alloc
<machine_function
> ();
215 /* Implement TARGET_OPTION_OVERRIDE. */
218 c6x_option_override (void)
222 if (global_options_set
.x_c6x_arch_option
)
224 c6x_arch
= all_isas
[c6x_arch_option
].type
;
225 c6x_insn_mask
&= ~C6X_INSNS_ALL_CPU_BITS
;
226 c6x_insn_mask
|= all_isas
[c6x_arch_option
].features
;
229 c6x_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
230 flag_schedule_insns_after_reload
= 0;
232 c6x_flag_modulo_sched
= flag_modulo_sched
;
233 flag_modulo_sched
= 0;
235 init_machine_status
= c6x_init_machine_status
;
237 for (i
= 0; i
< ARRAY_SIZE (c6x_unit_names
); i
++)
238 c6x_unit_codes
[i
] = get_cpu_unit_code (c6x_unit_names
[i
]);
240 if (flag_pic
&& !TARGET_DSBT
)
242 error ("-fpic and -fPIC not supported without -mdsbt on this target");
245 c6x_initial_flag_pic
= flag_pic
;
246 if (TARGET_DSBT
&& !flag_pic
)
251 /* Implement the TARGET_CONDITIONAL_REGISTER_USAGE hook. */
254 c6x_conditional_register_usage (void)
257 if (c6x_arch
== C6X_CPU_C62X
|| c6x_arch
== C6X_CPU_C67X
)
258 for (i
= 16; i
< 32; i
++)
261 fixed_regs
[32 + i
] = 1;
265 SET_HARD_REG_BIT (reg_class_contents
[(int)PREDICATE_A_REGS
],
267 SET_HARD_REG_BIT (reg_class_contents
[(int)PREDICATE_REGS
],
269 CLEAR_HARD_REG_BIT (reg_class_contents
[(int)NONPREDICATE_A_REGS
],
271 CLEAR_HARD_REG_BIT (reg_class_contents
[(int)NONPREDICATE_REGS
],
276 static GTY(()) rtx eqdf_libfunc
;
277 static GTY(()) rtx nedf_libfunc
;
278 static GTY(()) rtx ledf_libfunc
;
279 static GTY(()) rtx ltdf_libfunc
;
280 static GTY(()) rtx gedf_libfunc
;
281 static GTY(()) rtx gtdf_libfunc
;
282 static GTY(()) rtx eqsf_libfunc
;
283 static GTY(()) rtx nesf_libfunc
;
284 static GTY(()) rtx lesf_libfunc
;
285 static GTY(()) rtx ltsf_libfunc
;
286 static GTY(()) rtx gesf_libfunc
;
287 static GTY(()) rtx gtsf_libfunc
;
288 static GTY(()) rtx strasgi_libfunc
;
289 static GTY(()) rtx strasgi64p_libfunc
;
291 /* Implement the TARGET_INIT_LIBFUNCS macro. We use this to rename library
292 functions to match the C6x ABI. */
295 c6x_init_libfuncs (void)
297 /* Double-precision floating-point arithmetic. */
298 set_optab_libfunc (add_optab
, DFmode
, "__c6xabi_addd");
299 set_optab_libfunc (sdiv_optab
, DFmode
, "__c6xabi_divd");
300 set_optab_libfunc (smul_optab
, DFmode
, "__c6xabi_mpyd");
301 set_optab_libfunc (neg_optab
, DFmode
, "__c6xabi_negd");
302 set_optab_libfunc (sub_optab
, DFmode
, "__c6xabi_subd");
304 /* Single-precision floating-point arithmetic. */
305 set_optab_libfunc (add_optab
, SFmode
, "__c6xabi_addf");
306 set_optab_libfunc (sdiv_optab
, SFmode
, "__c6xabi_divf");
307 set_optab_libfunc (smul_optab
, SFmode
, "__c6xabi_mpyf");
308 set_optab_libfunc (neg_optab
, SFmode
, "__c6xabi_negf");
309 set_optab_libfunc (sub_optab
, SFmode
, "__c6xabi_subf");
311 /* Floating-point comparisons. */
312 eqsf_libfunc
= init_one_libfunc ("__c6xabi_eqf");
313 nesf_libfunc
= init_one_libfunc ("__c6xabi_neqf");
314 lesf_libfunc
= init_one_libfunc ("__c6xabi_lef");
315 ltsf_libfunc
= init_one_libfunc ("__c6xabi_ltf");
316 gesf_libfunc
= init_one_libfunc ("__c6xabi_gef");
317 gtsf_libfunc
= init_one_libfunc ("__c6xabi_gtf");
318 eqdf_libfunc
= init_one_libfunc ("__c6xabi_eqd");
319 nedf_libfunc
= init_one_libfunc ("__c6xabi_neqd");
320 ledf_libfunc
= init_one_libfunc ("__c6xabi_led");
321 ltdf_libfunc
= init_one_libfunc ("__c6xabi_ltd");
322 gedf_libfunc
= init_one_libfunc ("__c6xabi_ged");
323 gtdf_libfunc
= init_one_libfunc ("__c6xabi_gtd");
325 set_optab_libfunc (eq_optab
, SFmode
, NULL
);
326 set_optab_libfunc (ne_optab
, SFmode
, "__c6xabi_neqf");
327 set_optab_libfunc (gt_optab
, SFmode
, NULL
);
328 set_optab_libfunc (ge_optab
, SFmode
, NULL
);
329 set_optab_libfunc (lt_optab
, SFmode
, NULL
);
330 set_optab_libfunc (le_optab
, SFmode
, NULL
);
331 set_optab_libfunc (unord_optab
, SFmode
, "__c6xabi_unordf");
332 set_optab_libfunc (eq_optab
, DFmode
, NULL
);
333 set_optab_libfunc (ne_optab
, DFmode
, "__c6xabi_neqd");
334 set_optab_libfunc (gt_optab
, DFmode
, NULL
);
335 set_optab_libfunc (ge_optab
, DFmode
, NULL
);
336 set_optab_libfunc (lt_optab
, DFmode
, NULL
);
337 set_optab_libfunc (le_optab
, DFmode
, NULL
);
338 set_optab_libfunc (unord_optab
, DFmode
, "__c6xabi_unordd");
340 /* Floating-point to integer conversions. */
341 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__c6xabi_fixdi");
342 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__c6xabi_fixdu");
343 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__c6xabi_fixdlli");
344 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__c6xabi_fixdull");
345 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__c6xabi_fixfi");
346 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__c6xabi_fixfu");
347 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__c6xabi_fixflli");
348 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__c6xabi_fixfull");
350 /* Conversions between floating types. */
351 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__c6xabi_cvtdf");
352 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__c6xabi_cvtfd");
354 /* Integer to floating-point conversions. */
355 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__c6xabi_fltid");
356 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__c6xabi_fltud");
357 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__c6xabi_fltllid");
358 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__c6xabi_fltulld");
359 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__c6xabi_fltif");
360 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__c6xabi_fltuf");
361 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__c6xabi_fltllif");
362 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__c6xabi_fltullf");
365 set_optab_libfunc (smul_optab
, DImode
, "__c6xabi_mpyll");
366 set_optab_libfunc (ashl_optab
, DImode
, "__c6xabi_llshl");
367 set_optab_libfunc (lshr_optab
, DImode
, "__c6xabi_llshru");
368 set_optab_libfunc (ashr_optab
, DImode
, "__c6xabi_llshr");
370 set_optab_libfunc (sdiv_optab
, SImode
, "__c6xabi_divi");
371 set_optab_libfunc (udiv_optab
, SImode
, "__c6xabi_divu");
372 set_optab_libfunc (smod_optab
, SImode
, "__c6xabi_remi");
373 set_optab_libfunc (umod_optab
, SImode
, "__c6xabi_remu");
374 set_optab_libfunc (sdivmod_optab
, SImode
, "__c6xabi_divremi");
375 set_optab_libfunc (udivmod_optab
, SImode
, "__c6xabi_divremu");
376 set_optab_libfunc (sdiv_optab
, DImode
, "__c6xabi_divlli");
377 set_optab_libfunc (udiv_optab
, DImode
, "__c6xabi_divull");
378 set_optab_libfunc (smod_optab
, DImode
, "__c6xabi_remlli");
379 set_optab_libfunc (umod_optab
, DImode
, "__c6xabi_remull");
380 set_optab_libfunc (udivmod_optab
, DImode
, "__c6xabi_divremull");
383 strasgi_libfunc
= init_one_libfunc ("__c6xabi_strasgi");
384 strasgi64p_libfunc
= init_one_libfunc ("__c6xabi_strasgi_64plus");
387 /* Begin the assembly file. */
390 c6x_file_start (void)
392 /* Variable tracking should be run after all optimizations which change order
393 of insns. It also needs a valid CFG. This can't be done in
394 c6x_override_options, because flag_var_tracking is finalized after
396 c6x_flag_var_tracking
= flag_var_tracking
;
397 flag_var_tracking
= 0;
399 done_cfi_sections
= false;
400 default_file_start ();
402 /* Arrays are aligned to 8-byte boundaries. */
403 asm_fprintf (asm_out_file
,
404 "\t.c6xabi_attribute Tag_ABI_array_object_alignment, 0\n");
405 asm_fprintf (asm_out_file
,
406 "\t.c6xabi_attribute Tag_ABI_array_object_align_expected, 0\n");
408 /* Stack alignment is 8 bytes. */
409 asm_fprintf (asm_out_file
,
410 "\t.c6xabi_attribute Tag_ABI_stack_align_needed, 0\n");
411 asm_fprintf (asm_out_file
,
412 "\t.c6xabi_attribute Tag_ABI_stack_align_preserved, 0\n");
414 #if 0 /* FIXME: Reenable when TI's tools are fixed. */
415 /* ??? Ideally we'd check flag_short_wchar somehow. */
416 asm_fprintf (asm_out_file
, "\t.c6xabi_attribute Tag_ABI_wchar_t, %d\n", 2);
419 /* We conform to version 1.0 of the ABI. */
420 asm_fprintf (asm_out_file
,
421 "\t.c6xabi_attribute Tag_ABI_conformance, \"1.0\"\n");
425 /* The LTO frontend only enables exceptions when it sees a function that
426 uses it. This changes the return value of dwarf2out_do_frame, so we
427 have to check before every function. */
430 c6x_output_file_unwind (FILE * f
)
432 if (done_cfi_sections
)
435 /* Output a .cfi_sections directive. */
436 if (dwarf2out_do_frame ())
438 if (flag_unwind_tables
|| flag_exceptions
)
440 if (write_symbols
== DWARF2_DEBUG
441 || write_symbols
== VMS_AND_DWARF2_DEBUG
)
442 asm_fprintf (f
, "\t.cfi_sections .debug_frame, .c6xabi.exidx\n");
444 asm_fprintf (f
, "\t.cfi_sections .c6xabi.exidx\n");
447 asm_fprintf (f
, "\t.cfi_sections .debug_frame\n");
448 done_cfi_sections
= true;
452 /* Output unwind directives at the end of a function. */
455 c6x_output_fn_unwind (FILE * f
)
457 /* Return immediately if we are not generating unwinding tables. */
458 if (! (flag_unwind_tables
|| flag_exceptions
))
461 /* If this function will never be unwound, then mark it as such. */
462 if (!(flag_unwind_tables
|| crtl
->uses_eh_lsda
)
463 && (TREE_NOTHROW (current_function_decl
)
464 || crtl
->all_throwers_are_sibcalls
))
465 fputs("\t.cantunwind\n", f
);
467 fputs ("\t.endp\n", f
);
471 /* Stack and Calling. */
473 int argument_registers
[10] =
482 /* Implements the macro INIT_CUMULATIVE_ARGS defined in c6x.h. */
485 c6x_init_cumulative_args (CUMULATIVE_ARGS
*cum
, const_tree fntype
, rtx libname
,
486 int n_named_args ATTRIBUTE_UNUSED
)
490 if (!libname
&& fntype
)
492 /* We need to find out the number of named arguments. Unfortunately,
493 for incoming arguments, N_NAMED_ARGS is set to -1. */
494 if (stdarg_p (fntype
))
495 cum
->nregs
= type_num_arguments (fntype
) - 1;
501 /* Implements the macro FUNCTION_ARG defined in c6x.h. */
504 c6x_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
505 const_tree type
, bool named ATTRIBUTE_UNUSED
)
507 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
508 if (cum
->count
>= cum
->nregs
)
512 HOST_WIDE_INT size
= int_size_in_bytes (type
);
513 if (TARGET_BIG_ENDIAN
&& AGGREGATE_TYPE_P (type
))
517 rtx reg1
= gen_rtx_REG (SImode
, argument_registers
[cum
->count
] + 1);
518 rtx reg2
= gen_rtx_REG (SImode
, argument_registers
[cum
->count
]);
519 rtvec vec
= gen_rtvec (2, gen_rtx_EXPR_LIST (VOIDmode
, reg1
, const0_rtx
),
520 gen_rtx_EXPR_LIST (VOIDmode
, reg2
, GEN_INT (4)));
521 return gen_rtx_PARALLEL (mode
, vec
);
525 return gen_rtx_REG (mode
, argument_registers
[cum
->count
]);
529 c6x_function_arg_advance (cumulative_args_t cum_v
,
530 machine_mode mode ATTRIBUTE_UNUSED
,
531 const_tree type ATTRIBUTE_UNUSED
,
532 bool named ATTRIBUTE_UNUSED
)
534 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
539 /* Return true if BLOCK_REG_PADDING (MODE, TYPE, FIRST) should return
540 upward rather than downward. */
543 c6x_block_reg_pad_upward (machine_mode mode ATTRIBUTE_UNUSED
,
544 const_tree type
, bool first
)
548 if (!TARGET_BIG_ENDIAN
)
554 size
= int_size_in_bytes (type
);
558 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. */
561 c6x_function_arg_boundary (machine_mode mode
, const_tree type
)
563 unsigned int boundary
= type
? TYPE_ALIGN (type
) : GET_MODE_BITSIZE (mode
);
565 if (boundary
> BITS_PER_WORD
)
566 return 2 * BITS_PER_WORD
;
570 HOST_WIDE_INT size
= int_size_in_bytes (type
);
572 return 2 * BITS_PER_WORD
;
573 if (boundary
< BITS_PER_WORD
)
576 return BITS_PER_WORD
;
578 return 2 * BITS_PER_UNIT
;
584 /* Implement TARGET_FUNCTION_ARG_ROUND_BOUNDARY. */
586 c6x_function_arg_round_boundary (machine_mode mode
, const_tree type
)
588 return c6x_function_arg_boundary (mode
, type
);
591 /* TARGET_FUNCTION_VALUE implementation. Returns an RTX representing the place
592 where function FUNC returns or receives a value of data type TYPE. */
595 c6x_function_value (const_tree type
, const_tree func ATTRIBUTE_UNUSED
,
596 bool outgoing ATTRIBUTE_UNUSED
)
598 /* Functions return values in register A4. When returning aggregates, we may
599 have to adjust for endianness. */
600 if (TARGET_BIG_ENDIAN
&& type
&& AGGREGATE_TYPE_P (type
))
602 HOST_WIDE_INT size
= int_size_in_bytes (type
);
606 rtx reg1
= gen_rtx_REG (SImode
, REG_A4
+ 1);
607 rtx reg2
= gen_rtx_REG (SImode
, REG_A4
);
608 rtvec vec
= gen_rtvec (2, gen_rtx_EXPR_LIST (VOIDmode
, reg1
, const0_rtx
),
609 gen_rtx_EXPR_LIST (VOIDmode
, reg2
, GEN_INT (4)));
610 return gen_rtx_PARALLEL (TYPE_MODE (type
), vec
);
613 return gen_rtx_REG (TYPE_MODE (type
), REG_A4
);
616 /* Implement TARGET_LIBCALL_VALUE. */
619 c6x_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
621 return gen_rtx_REG (mode
, REG_A4
);
624 /* TARGET_STRUCT_VALUE_RTX implementation. */
627 c6x_struct_value_rtx (tree type ATTRIBUTE_UNUSED
, int incoming ATTRIBUTE_UNUSED
)
629 return gen_rtx_REG (Pmode
, REG_A3
);
632 /* Implement TARGET_FUNCTION_VALUE_REGNO_P. */
635 c6x_function_value_regno_p (const unsigned int regno
)
637 return regno
== REG_A4
;
640 /* Types larger than 64 bit, and variable sized types, are passed by
641 reference. The callee must copy them; see c6x_callee_copies. */
644 c6x_pass_by_reference (cumulative_args_t cum_v ATTRIBUTE_UNUSED
,
645 machine_mode mode
, const_tree type
,
646 bool named ATTRIBUTE_UNUSED
)
650 size
= int_size_in_bytes (type
);
651 else if (mode
!= VOIDmode
)
652 size
= GET_MODE_SIZE (mode
);
653 return size
> 2 * UNITS_PER_WORD
|| size
== -1;
656 /* Decide whether a type should be returned in memory (true)
657 or in a register (false). This is called by the macro
658 TARGET_RETURN_IN_MEMORY. */
661 c6x_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
663 int size
= int_size_in_bytes (type
);
664 return size
> 2 * UNITS_PER_WORD
|| size
== -1;
667 /* Values which must be returned in the most-significant end of the return
671 c6x_return_in_msb (const_tree valtype
)
673 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
674 return TARGET_BIG_ENDIAN
&& AGGREGATE_TYPE_P (valtype
) && size
== 3;
677 /* Implement TARGET_CALLEE_COPIES. */
680 c6x_callee_copies (cumulative_args_t cum_v ATTRIBUTE_UNUSED
,
681 machine_mode mode ATTRIBUTE_UNUSED
,
682 const_tree type ATTRIBUTE_UNUSED
,
683 bool named ATTRIBUTE_UNUSED
)
688 /* Return the type to use as __builtin_va_list. */
690 c6x_build_builtin_va_list (void)
692 return build_pointer_type (char_type_node
);
696 c6x_asm_trampoline_template (FILE *f
)
698 fprintf (f
, "\t.long\t0x0000002b\n"); /* mvkl .s2 fnlow,B0 */
699 fprintf (f
, "\t.long\t0x01000028\n"); /* || mvkl .s1 sclow,A2 */
700 fprintf (f
, "\t.long\t0x0000006b\n"); /* mvkh .s2 fnhigh,B0 */
701 fprintf (f
, "\t.long\t0x01000068\n"); /* || mvkh .s1 schigh,A2 */
702 fprintf (f
, "\t.long\t0x00000362\n"); /* b .s2 B0 */
703 fprintf (f
, "\t.long\t0x00008000\n"); /* nop 5 */
704 fprintf (f
, "\t.long\t0x00000000\n"); /* nop */
705 fprintf (f
, "\t.long\t0x00000000\n"); /* nop */
708 /* Emit RTL insns to initialize the variable parts of a trampoline at
709 TRAMP. FNADDR is an RTX for the address of the function's pure
710 code. CXT is an RTX for the static chain value for the function. */
713 c6x_initialize_trampoline (rtx tramp
, tree fndecl
, rtx cxt
)
715 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
716 rtx t1
= copy_to_reg (fnaddr
);
717 rtx t2
= copy_to_reg (cxt
);
718 rtx mask
= gen_reg_rtx (SImode
);
721 emit_block_move (tramp
, assemble_trampoline_template (),
722 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
724 emit_move_insn (mask
, GEN_INT (0xffff << 7));
726 for (i
= 0; i
< 4; i
++)
728 rtx mem
= adjust_address (tramp
, SImode
, i
* 4);
729 rtx t
= (i
& 1) ? t2
: t1
;
730 rtx v1
= gen_reg_rtx (SImode
);
731 rtx v2
= gen_reg_rtx (SImode
);
732 emit_move_insn (v1
, mem
);
734 emit_insn (gen_ashlsi3 (v2
, t
, GEN_INT (7)));
736 emit_insn (gen_lshrsi3 (v2
, t
, GEN_INT (9)));
737 emit_insn (gen_andsi3 (v2
, v2
, mask
));
738 emit_insn (gen_iorsi3 (v2
, v2
, v1
));
739 emit_move_insn (mem
, v2
);
741 #ifdef CLEAR_INSN_CACHE
742 tramp
= XEXP (tramp
, 0);
743 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__gnu_clear_cache"),
744 LCT_NORMAL
, VOIDmode
, tramp
, Pmode
,
745 plus_constant (Pmode
, tramp
, TRAMPOLINE_SIZE
), Pmode
);
749 /* Determine whether c6x_output_mi_thunk can succeed. */
752 c6x_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED
,
753 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
754 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
755 const_tree function ATTRIBUTE_UNUSED
)
757 return !TARGET_LONG_CALLS
;
760 /* Output the assembler code for a thunk function. THUNK is the
761 declaration for the thunk function itself, FUNCTION is the decl for
762 the target function. DELTA is an immediate constant offset to be
763 added to THIS. If VCALL_OFFSET is nonzero, the word at
764 *(*this + vcall_offset) should be added to THIS. */
767 c6x_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED
,
768 tree thunk ATTRIBUTE_UNUSED
, HOST_WIDE_INT delta
,
769 HOST_WIDE_INT vcall_offset
, tree function
)
772 /* The this parameter is passed as the first argument. */
773 rtx this_rtx
= gen_rtx_REG (Pmode
, REG_A4
);
775 c6x_current_insn
= NULL
;
777 xops
[4] = XEXP (DECL_RTL (function
), 0);
780 output_asm_insn ("b .s2 \t%4", xops
);
782 output_asm_insn ("nop 5", xops
);
785 /* Adjust the this parameter by a fixed constant. */
788 xops
[0] = GEN_INT (delta
);
790 if (delta
>= -16 && delta
<= 15)
792 output_asm_insn ("add .s1 %0, %1, %1", xops
);
794 output_asm_insn ("nop 4", xops
);
796 else if (delta
>= 16 && delta
< 32)
798 output_asm_insn ("add .d1 %0, %1, %1", xops
);
800 output_asm_insn ("nop 4", xops
);
802 else if (delta
>= -32768 && delta
< 32768)
804 output_asm_insn ("mvk .s1 %0, A0", xops
);
805 output_asm_insn ("add .d1 %1, A0, %1", xops
);
807 output_asm_insn ("nop 3", xops
);
811 output_asm_insn ("mvkl .s1 %0, A0", xops
);
812 output_asm_insn ("mvkh .s1 %0, A0", xops
);
813 output_asm_insn ("add .d1 %1, A0, %1", xops
);
815 output_asm_insn ("nop 3", xops
);
819 /* Adjust the this parameter by a value stored in the vtable. */
822 rtx a0tmp
= gen_rtx_REG (Pmode
, REG_A0
);
823 rtx a3tmp
= gen_rtx_REG (Pmode
, REG_A3
);
827 xops
[3] = gen_rtx_MEM (Pmode
, a0tmp
);
828 output_asm_insn ("mv .s1 a4, %2", xops
);
829 output_asm_insn ("ldw .d1t1 %3, %2", xops
);
831 /* Adjust the this parameter. */
832 xops
[0] = gen_rtx_MEM (Pmode
, plus_constant (Pmode
, a0tmp
,
834 if (!memory_operand (xops
[0], Pmode
))
836 rtx tmp2
= gen_rtx_REG (Pmode
, REG_A1
);
837 xops
[0] = GEN_INT (vcall_offset
);
839 output_asm_insn ("mvkl .s1 %0, %1", xops
);
840 output_asm_insn ("mvkh .s1 %0, %1", xops
);
841 output_asm_insn ("nop 2", xops
);
842 output_asm_insn ("add .d1 %2, %1, %2", xops
);
843 xops
[0] = gen_rtx_MEM (Pmode
, a0tmp
);
846 output_asm_insn ("nop 4", xops
);
848 output_asm_insn ("ldw .d1t1 %0, %1", xops
);
849 output_asm_insn ("|| b .s2 \t%4", xops
);
850 output_asm_insn ("nop 4", xops
);
851 output_asm_insn ("add .d1 %2, %1, %2", xops
);
855 /* Return true if EXP goes in small data/bss. */
858 c6x_in_small_data_p (const_tree exp
)
860 /* We want to merge strings, so we never consider them small data. */
861 if (TREE_CODE (exp
) == STRING_CST
)
864 /* Functions are never small data. */
865 if (TREE_CODE (exp
) == FUNCTION_DECL
)
868 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_WEAK (exp
))
871 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
873 const char *section
= DECL_SECTION_NAME (exp
);
875 if (strcmp (section
, ".neardata") == 0
876 || strncmp (section
, ".neardata.", 10) == 0
877 || strncmp (section
, ".gnu.linkonce.s.", 16) == 0
878 || strcmp (section
, ".bss") == 0
879 || strncmp (section
, ".bss.", 5) == 0
880 || strncmp (section
, ".gnu.linkonce.sb.", 17) == 0
881 || strcmp (section
, ".rodata") == 0
882 || strncmp (section
, ".rodata.", 8) == 0
883 || strncmp (section
, ".gnu.linkonce.s2.", 17) == 0)
887 return PLACE_IN_SDATA_P (exp
);
892 /* Return a section for X. The only special thing we do here is to
893 honor small data. We don't have a tree type, so we can't use the
894 PLACE_IN_SDATA_P macro we use everywhere else; we choose to place
895 everything sized 8 bytes or smaller into small data. */
898 c6x_select_rtx_section (machine_mode mode
, rtx x
,
899 unsigned HOST_WIDE_INT align
)
901 if (c6x_sdata_mode
== C6X_SDATA_ALL
902 || (c6x_sdata_mode
!= C6X_SDATA_NONE
&& GET_MODE_SIZE (mode
) <= 8))
903 /* ??? Consider using mergeable sdata sections. */
904 return sdata_section
;
906 return default_elf_select_rtx_section (mode
, x
, align
);
910 c6x_elf_select_section (tree decl
, int reloc
,
911 unsigned HOST_WIDE_INT align
)
913 const char *sname
= NULL
;
914 unsigned int flags
= SECTION_WRITE
;
915 if (c6x_in_small_data_p (decl
))
917 switch (categorize_decl_for_section (decl
, reloc
))
928 flags
|= SECTION_BSS
;
935 switch (categorize_decl_for_section (decl
, reloc
))
940 case SECCAT_DATA_REL
:
941 sname
= ".fardata.rel";
943 case SECCAT_DATA_REL_LOCAL
:
944 sname
= ".fardata.rel.local";
946 case SECCAT_DATA_REL_RO
:
947 sname
= ".fardata.rel.ro";
949 case SECCAT_DATA_REL_RO_LOCAL
:
950 sname
= ".fardata.rel.ro.local";
954 flags
|= SECTION_BSS
;
970 /* We might get called with string constants, but get_named_section
971 doesn't like them as they are not DECLs. Also, we need to set
972 flags in that case. */
974 return get_section (sname
, flags
, NULL
);
975 return get_named_section (decl
, sname
, reloc
);
978 return default_elf_select_section (decl
, reloc
, align
);
981 /* Build up a unique section name, expressed as a
982 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
983 RELOC indicates whether the initial value of EXP requires
984 link-time relocations. */
986 static void ATTRIBUTE_UNUSED
987 c6x_elf_unique_section (tree decl
, int reloc
)
989 const char *prefix
= NULL
;
990 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
991 bool one_only
= DECL_COMDAT_GROUP (decl
) && !HAVE_COMDAT_GROUP
;
993 if (c6x_in_small_data_p (decl
))
995 switch (categorize_decl_for_section (decl
, reloc
))
998 prefix
= one_only
? ".s" : ".neardata";
1001 prefix
= one_only
? ".sb" : ".bss";
1003 case SECCAT_SRODATA
:
1004 prefix
= one_only
? ".s2" : ".rodata";
1006 case SECCAT_RODATA_MERGE_STR
:
1007 case SECCAT_RODATA_MERGE_STR_INIT
:
1008 case SECCAT_RODATA_MERGE_CONST
:
1011 case SECCAT_DATA_REL
:
1012 case SECCAT_DATA_REL_LOCAL
:
1013 case SECCAT_DATA_REL_RO
:
1014 case SECCAT_DATA_REL_RO_LOCAL
:
1017 /* Everything else we place into default sections and hope for the
1024 switch (categorize_decl_for_section (decl
, reloc
))
1027 case SECCAT_DATA_REL
:
1028 case SECCAT_DATA_REL_LOCAL
:
1029 case SECCAT_DATA_REL_RO
:
1030 case SECCAT_DATA_REL_RO_LOCAL
:
1031 prefix
= one_only
? ".fd" : ".fardata";
1034 prefix
= one_only
? ".fb" : ".far";
1037 case SECCAT_RODATA_MERGE_STR
:
1038 case SECCAT_RODATA_MERGE_STR_INIT
:
1039 case SECCAT_RODATA_MERGE_CONST
:
1040 prefix
= one_only
? ".fr" : ".const";
1042 case SECCAT_SRODATA
:
1053 const char *name
, *linkonce
;
1056 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
1057 name
= targetm
.strip_name_encoding (name
);
1059 /* If we're using one_only, then there needs to be a .gnu.linkonce
1060 prefix to the section name. */
1061 linkonce
= one_only
? ".gnu.linkonce" : "";
1063 string
= ACONCAT ((linkonce
, prefix
, ".", name
, NULL
));
1065 set_decl_section_name (decl
, string
);
1068 default_unique_section (decl
, reloc
);
1072 c6x_section_type_flags (tree decl
, const char *name
, int reloc
)
1074 unsigned int flags
= 0;
1076 if (strcmp (name
, ".far") == 0
1077 || strncmp (name
, ".far.", 5) == 0)
1078 flags
|= SECTION_BSS
;
1080 flags
|= default_section_type_flags (decl
, name
, reloc
);
1085 /* Checks whether the given CALL_EXPR would use a caller saved
1086 register. This is used to decide whether sibling call optimization
1087 could be performed on the respective function call. */
1090 c6x_call_saved_register_used (tree call_expr
)
1092 CUMULATIVE_ARGS cum_v
;
1093 cumulative_args_t cum
;
1094 HARD_REG_SET call_saved_regset
;
1101 INIT_CUMULATIVE_ARGS (cum_v
, NULL
, NULL
, 0, 0);
1102 cum
= pack_cumulative_args (&cum_v
);
1104 COMPL_HARD_REG_SET (call_saved_regset
, call_used_reg_set
);
1105 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
1107 parameter
= CALL_EXPR_ARG (call_expr
, i
);
1108 gcc_assert (parameter
);
1110 /* For an undeclared variable passed as parameter we will get
1111 an ERROR_MARK node here. */
1112 if (TREE_CODE (parameter
) == ERROR_MARK
)
1115 type
= TREE_TYPE (parameter
);
1118 mode
= TYPE_MODE (type
);
1121 if (pass_by_reference (&cum_v
, mode
, type
, true))
1124 type
= build_pointer_type (type
);
1127 parm_rtx
= c6x_function_arg (cum
, mode
, type
, 0);
1129 c6x_function_arg_advance (cum
, mode
, type
, 0);
1134 if (REG_P (parm_rtx
)
1135 && overlaps_hard_reg_set_p (call_saved_regset
, GET_MODE (parm_rtx
),
1138 if (GET_CODE (parm_rtx
) == PARALLEL
)
1140 int n
= XVECLEN (parm_rtx
, 0);
1143 rtx x
= XEXP (XVECEXP (parm_rtx
, 0, n
), 0);
1145 && overlaps_hard_reg_set_p (call_saved_regset
,
1146 GET_MODE (x
), REGNO (x
)))
1154 /* Decide whether we can make a sibling call to a function. DECL is the
1155 declaration of the function being targeted by the call and EXP is the
1156 CALL_EXPR representing the call. */
1159 c6x_function_ok_for_sibcall (tree decl
, tree exp
)
1161 /* Registers A10, A12, B10 and B12 are available as arguments
1162 register but unfortunately caller saved. This makes functions
1163 needing these registers for arguments not suitable for
1165 if (c6x_call_saved_register_used (exp
))
1173 /* When compiling for DSBT, the calling function must be local,
1174 so that when we reload B14 in the sibcall epilogue, it will
1175 not change its value. */
1176 struct cgraph_local_info
*this_func
;
1179 /* Not enough information. */
1182 this_func
= cgraph_node::local_info (current_function_decl
);
1183 return this_func
->local
;
1189 /* Return true if DECL is known to be linked into section SECTION. */
1192 c6x_function_in_section_p (tree decl
, section
*section
)
1194 /* We can only be certain about functions defined in the same
1195 compilation unit. */
1196 if (!TREE_STATIC (decl
))
1199 /* Make sure that SYMBOL always binds to the definition in this
1200 compilation unit. */
1201 if (!targetm
.binds_local_p (decl
))
1204 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
1205 if (!DECL_SECTION_NAME (decl
))
1207 /* Make sure that we will not create a unique section for DECL. */
1208 if (flag_function_sections
|| DECL_COMDAT_GROUP (decl
))
1212 return function_section (decl
) == section
;
1215 /* Return true if a call to OP, which is a SYMBOL_REF, must be expanded
1218 c6x_long_call_p (rtx op
)
1222 if (!TARGET_LONG_CALLS
)
1225 decl
= SYMBOL_REF_DECL (op
);
1227 /* Try to determine whether the symbol is in the same section as the current
1228 function. Be conservative, and only cater for cases in which the
1229 whole of the current function is placed in the same section. */
1230 if (decl
!= NULL_TREE
1231 && !flag_reorder_blocks_and_partition
1232 && TREE_CODE (decl
) == FUNCTION_DECL
1233 && c6x_function_in_section_p (decl
, current_function_section ()))
1239 /* Emit the sequence for a call. */
1241 c6x_expand_call (rtx retval
, rtx address
, bool sibcall
)
1243 rtx callee
= XEXP (address
, 0);
1246 if (!c6x_call_operand (callee
, Pmode
))
1248 callee
= force_reg (Pmode
, callee
);
1249 address
= change_address (address
, Pmode
, callee
);
1251 call_insn
= gen_rtx_CALL (VOIDmode
, address
, const0_rtx
);
1254 call_insn
= emit_call_insn (call_insn
);
1255 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
1256 gen_rtx_REG (Pmode
, REG_B3
));
1260 if (retval
== NULL_RTX
)
1261 call_insn
= emit_call_insn (call_insn
);
1263 call_insn
= emit_call_insn (gen_rtx_SET (retval
, call_insn
));
1266 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), pic_offset_table_rtx
);
1269 /* Legitimize PIC addresses. If the address is already position-independent,
1270 we return ORIG. Newly generated position-independent addresses go into a
1271 reg. This is REG if nonzero, otherwise we allocate register(s) as
1272 necessary. PICREG is the register holding the pointer to the PIC offset
1276 legitimize_pic_address (rtx orig
, rtx reg
, rtx picreg
)
1281 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
1283 int unspec
= UNSPEC_LOAD_GOT
;
1288 gcc_assert (can_create_pseudo_p ());
1289 reg
= gen_reg_rtx (Pmode
);
1293 if (can_create_pseudo_p ())
1294 tmp
= gen_reg_rtx (Pmode
);
1297 emit_insn (gen_movsi_gotoff_high (tmp
, addr
));
1298 emit_insn (gen_movsi_gotoff_lo_sum (tmp
, tmp
, addr
));
1299 emit_insn (gen_load_got_gotoff (reg
, picreg
, tmp
));
1303 tmp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), unspec
);
1304 new_rtx
= gen_const_mem (Pmode
, gen_rtx_PLUS (Pmode
, picreg
, tmp
));
1306 emit_move_insn (reg
, new_rtx
);
1308 if (picreg
== pic_offset_table_rtx
)
1309 crtl
->uses_pic_offset_table
= 1;
1313 else if (GET_CODE (addr
) == CONST
|| GET_CODE (addr
) == PLUS
)
1317 if (GET_CODE (addr
) == CONST
)
1319 addr
= XEXP (addr
, 0);
1320 gcc_assert (GET_CODE (addr
) == PLUS
);
1323 if (XEXP (addr
, 0) == picreg
)
1328 gcc_assert (can_create_pseudo_p ());
1329 reg
= gen_reg_rtx (Pmode
);
1332 base
= legitimize_pic_address (XEXP (addr
, 0), reg
, picreg
);
1333 addr
= legitimize_pic_address (XEXP (addr
, 1),
1334 base
== reg
? NULL_RTX
: reg
,
1337 if (GET_CODE (addr
) == CONST_INT
)
1339 gcc_assert (! reload_in_progress
&& ! reload_completed
);
1340 addr
= force_reg (Pmode
, addr
);
1343 if (GET_CODE (addr
) == PLUS
&& CONSTANT_P (XEXP (addr
, 1)))
1345 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (addr
, 0));
1346 addr
= XEXP (addr
, 1);
1349 return gen_rtx_PLUS (Pmode
, base
, addr
);
1355 /* Expand a move operation in mode MODE. The operands are in OPERANDS.
1356 Returns true if no further code must be generated, false if the caller
1357 should generate an insn to move OPERANDS[1] to OPERANDS[0]. */
1360 expand_move (rtx
*operands
, machine_mode mode
)
1362 rtx dest
= operands
[0];
1363 rtx op
= operands
[1];
1365 if ((reload_in_progress
| reload_completed
) == 0
1366 && GET_CODE (dest
) == MEM
&& GET_CODE (op
) != REG
)
1367 operands
[1] = force_reg (mode
, op
);
1368 else if (mode
== SImode
&& symbolic_operand (op
, SImode
))
1372 if (sdata_symbolic_operand (op
, SImode
))
1374 emit_insn (gen_load_sdata_pic (dest
, pic_offset_table_rtx
, op
));
1375 crtl
->uses_pic_offset_table
= 1;
1380 rtx temp
= (reload_completed
|| reload_in_progress
1381 ? dest
: gen_reg_rtx (Pmode
));
1383 operands
[1] = legitimize_pic_address (op
, temp
,
1384 pic_offset_table_rtx
);
1387 else if (reload_completed
1388 && !sdata_symbolic_operand (op
, SImode
))
1390 emit_insn (gen_movsi_high (dest
, op
));
1391 emit_insn (gen_movsi_lo_sum (dest
, dest
, op
));
1398 /* This function is called when we're about to expand an integer compare
1399 operation which performs COMPARISON. It examines the second operand,
1400 and if it is an integer constant that cannot be used directly on the
1401 current machine in a comparison insn, it returns true. */
1403 c6x_force_op_for_comparison_p (enum rtx_code code
, rtx op
)
1405 if (!CONST_INT_P (op
) || satisfies_constraint_Iu4 (op
))
1408 if ((code
== EQ
|| code
== LT
|| code
== GT
)
1409 && !satisfies_constraint_Is5 (op
))
1411 if ((code
== GTU
|| code
== LTU
)
1412 && (!TARGET_INSNS_64
|| !satisfies_constraint_Iu5 (op
)))
1418 /* Emit comparison instruction if necessary, returning the expression
1419 that holds the compare result in the proper mode. Return the comparison
1420 that should be used in the jump insn. */
1423 c6x_expand_compare (rtx comparison
, machine_mode mode
)
1425 enum rtx_code code
= GET_CODE (comparison
);
1426 rtx op0
= XEXP (comparison
, 0);
1427 rtx op1
= XEXP (comparison
, 1);
1429 enum rtx_code jump_code
= code
;
1430 machine_mode op_mode
= GET_MODE (op0
);
1432 if (op_mode
== DImode
&& (code
== NE
|| code
== EQ
) && op1
== const0_rtx
)
1434 rtx t
= gen_reg_rtx (SImode
);
1435 emit_insn (gen_iorsi3 (t
, gen_lowpart (SImode
, op0
),
1436 gen_highpart (SImode
, op0
)));
1440 else if (op_mode
== DImode
)
1445 if (code
== NE
|| code
== GEU
|| code
== LEU
|| code
== GE
|| code
== LE
)
1447 code
= reverse_condition (code
);
1453 split_di (&op0
, 1, lo
, high
);
1454 split_di (&op1
, 1, lo
+ 1, high
+ 1);
1456 if (c6x_force_op_for_comparison_p (code
, high
[1])
1457 || c6x_force_op_for_comparison_p (EQ
, high
[1]))
1458 high
[1] = force_reg (SImode
, high
[1]);
1460 cmp1
= gen_reg_rtx (SImode
);
1461 cmp2
= gen_reg_rtx (SImode
);
1462 emit_insn (gen_rtx_SET (cmp1
, gen_rtx_fmt_ee (code
, SImode
,
1463 high
[0], high
[1])));
1466 if (c6x_force_op_for_comparison_p (code
, lo
[1]))
1467 lo
[1] = force_reg (SImode
, lo
[1]);
1468 emit_insn (gen_rtx_SET (cmp2
, gen_rtx_fmt_ee (code
, SImode
,
1470 emit_insn (gen_andsi3 (cmp1
, cmp1
, cmp2
));
1474 emit_insn (gen_rtx_SET (cmp2
, gen_rtx_EQ (SImode
, high
[0],
1478 else if (code
== LT
)
1480 if (c6x_force_op_for_comparison_p (code
, lo
[1]))
1481 lo
[1] = force_reg (SImode
, lo
[1]);
1482 emit_insn (gen_cmpsi_and (cmp2
, gen_rtx_fmt_ee (code
, SImode
,
1484 lo
[0], lo
[1], cmp2
));
1485 emit_insn (gen_iorsi3 (cmp1
, cmp1
, cmp2
));
1489 else if (TARGET_FP
&& !flag_finite_math_only
1490 && (op_mode
== DFmode
|| op_mode
== SFmode
)
1491 && code
!= EQ
&& code
!= NE
&& code
!= LT
&& code
!= GT
1492 && code
!= UNLE
&& code
!= UNGE
)
1494 enum rtx_code code1
, code2
, code3
;
1495 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
1507 code1
= code
== LE
|| code
== UNGT
? LT
: GT
;
1532 cmp
= gen_reg_rtx (SImode
);
1533 emit_insn (gen_rtx_SET (cmp
, gen_rtx_fmt_ee (code1
, SImode
, op0
, op1
)));
1534 fn
= op_mode
== DFmode
? gen_cmpdf_ior
: gen_cmpsf_ior
;
1535 emit_insn (fn (cmp
, gen_rtx_fmt_ee (code2
, SImode
, op0
, op1
),
1537 if (code3
!= UNKNOWN
)
1538 emit_insn (fn (cmp
, gen_rtx_fmt_ee (code3
, SImode
, op0
, op1
),
1541 else if (op_mode
== SImode
&& (code
== NE
|| code
== EQ
) && op1
== const0_rtx
)
1546 is_fp_libfunc
= !TARGET_FP
&& (op_mode
== DFmode
|| op_mode
== SFmode
);
1548 if ((code
== NE
|| code
== GEU
|| code
== LEU
|| code
== GE
|| code
== LE
)
1551 code
= reverse_condition (code
);
1554 else if (code
== UNGE
)
1559 else if (code
== UNLE
)
1574 libfunc
= op_mode
== DFmode
? eqdf_libfunc
: eqsf_libfunc
;
1577 libfunc
= op_mode
== DFmode
? nedf_libfunc
: nesf_libfunc
;
1580 libfunc
= op_mode
== DFmode
? gtdf_libfunc
: gtsf_libfunc
;
1583 libfunc
= op_mode
== DFmode
? gedf_libfunc
: gesf_libfunc
;
1586 libfunc
= op_mode
== DFmode
? ltdf_libfunc
: ltsf_libfunc
;
1589 libfunc
= op_mode
== DFmode
? ledf_libfunc
: lesf_libfunc
;
1596 cmp
= emit_library_call_value (libfunc
, 0, LCT_CONST
, SImode
,
1597 op0
, op_mode
, op1
, op_mode
);
1598 insns
= get_insns ();
1601 emit_libcall_block (insns
, cmp
, cmp
,
1602 gen_rtx_fmt_ee (code
, SImode
, op0
, op1
));
1606 cmp
= gen_reg_rtx (SImode
);
1607 if (c6x_force_op_for_comparison_p (code
, op1
))
1608 op1
= force_reg (SImode
, op1
);
1609 emit_insn (gen_rtx_SET (cmp
, gen_rtx_fmt_ee (code
, SImode
,
1614 return gen_rtx_fmt_ee (jump_code
, mode
, cmp
, const0_rtx
);
1617 /* Return one word of double-word value OP. HIGH_P is true to select the
1618 high part, false to select the low part. When encountering auto-increment
1619 addressing, we make the assumption that the low part is going to be accessed
1623 c6x_subword (rtx op
, bool high_p
)
1628 mode
= GET_MODE (op
);
1629 if (mode
== VOIDmode
)
1632 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
1633 byte
= UNITS_PER_WORD
;
1639 rtx addr
= XEXP (op
, 0);
1640 if (GET_CODE (addr
) == PLUS
|| REG_P (addr
))
1641 return adjust_address (op
, word_mode
, byte
);
1642 /* FIXME: should really support autoincrement addressing for
1643 multi-word modes. */
1647 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
1650 /* Split one or more DImode RTL references into pairs of SImode
1651 references. The RTL can be REG, offsettable MEM, integer constant, or
1652 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
1653 split and "num" is its length. lo_half and hi_half are output arrays
1654 that parallel "operands". */
1657 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
1661 rtx op
= operands
[num
];
1663 lo_half
[num
] = c6x_subword (op
, false);
1664 hi_half
[num
] = c6x_subword (op
, true);
1668 /* Return true if VAL is a mask valid for a clr instruction. */
1670 c6x_valid_mask_p (HOST_WIDE_INT val
)
1673 for (i
= 0; i
< 32; i
++)
1674 if (!(val
& ((unsigned HOST_WIDE_INT
)1 << i
)))
1677 if (val
& ((unsigned HOST_WIDE_INT
)1 << i
))
1680 if (!(val
& ((unsigned HOST_WIDE_INT
)1 << i
)))
1685 /* Expand a block move for a movmemM pattern. */
1688 c6x_expand_movmem (rtx dst
, rtx src
, rtx count_exp
, rtx align_exp
,
1689 rtx expected_align_exp ATTRIBUTE_UNUSED
,
1690 rtx expected_size_exp ATTRIBUTE_UNUSED
)
1692 unsigned HOST_WIDE_INT align
= 1;
1693 unsigned HOST_WIDE_INT src_mem_align
, dst_mem_align
, min_mem_align
;
1694 unsigned HOST_WIDE_INT count
= 0, offset
= 0;
1695 unsigned int biggest_move
= TARGET_STDW
? 8 : 4;
1697 if (CONST_INT_P (align_exp
))
1698 align
= INTVAL (align_exp
);
1700 src_mem_align
= MEM_ALIGN (src
) / BITS_PER_UNIT
;
1701 dst_mem_align
= MEM_ALIGN (dst
) / BITS_PER_UNIT
;
1702 min_mem_align
= MIN (src_mem_align
, dst_mem_align
);
1704 if (min_mem_align
> align
)
1705 align
= min_mem_align
/ BITS_PER_UNIT
;
1706 if (src_mem_align
< align
)
1707 src_mem_align
= align
;
1708 if (dst_mem_align
< align
)
1709 dst_mem_align
= align
;
1711 if (CONST_INT_P (count_exp
))
1712 count
= INTVAL (count_exp
);
1716 /* Make sure we don't need to care about overflow later on. */
1717 if (count
> ((unsigned HOST_WIDE_INT
) 1 << 30))
1720 if (count
>= 28 && (count
& 3) == 0 && align
>= 4)
1722 tree dst_expr
= MEM_EXPR (dst
);
1723 tree src_expr
= MEM_EXPR (src
);
1724 rtx fn
= TARGET_INSNS_64PLUS
? strasgi64p_libfunc
: strasgi_libfunc
;
1725 rtx srcreg
= force_reg (Pmode
, XEXP (src
, 0));
1726 rtx dstreg
= force_reg (Pmode
, XEXP (dst
, 0));
1729 mark_addressable (src_expr
);
1731 mark_addressable (dst_expr
);
1732 emit_library_call (fn
, LCT_NORMAL
, VOIDmode
,
1733 dstreg
, Pmode
, srcreg
, Pmode
, count_exp
, SImode
);
1737 if (biggest_move
> align
&& !TARGET_INSNS_64
)
1738 biggest_move
= align
;
1740 if (count
/ biggest_move
> 7)
1745 rtx reg
, reg_lowpart
;
1746 machine_mode srcmode
, dstmode
;
1747 unsigned HOST_WIDE_INT src_size
, dst_size
, src_left
;
1751 while (biggest_move
> count
)
1754 src_size
= dst_size
= biggest_move
;
1755 if (src_size
> src_mem_align
&& src_size
== 2)
1757 if (dst_size
> dst_mem_align
&& dst_size
== 2)
1760 if (dst_size
> src_size
)
1761 dst_size
= src_size
;
1763 srcmode
= int_mode_for_size (src_size
* BITS_PER_UNIT
, 0).require ();
1764 dstmode
= int_mode_for_size (dst_size
* BITS_PER_UNIT
, 0).require ();
1766 reg_lowpart
= reg
= gen_reg_rtx (srcmode
);
1769 reg
= gen_reg_rtx (SImode
);
1770 reg_lowpart
= gen_lowpart (srcmode
, reg
);
1773 srcmem
= adjust_address (copy_rtx (src
), srcmode
, offset
);
1775 if (src_size
> src_mem_align
)
1777 enum insn_code icode
= (srcmode
== SImode
? CODE_FOR_movmisalignsi
1778 : CODE_FOR_movmisaligndi
);
1779 emit_insn (GEN_FCN (icode
) (reg_lowpart
, srcmem
));
1782 emit_move_insn (reg_lowpart
, srcmem
);
1784 src_left
= src_size
;
1785 shift
= TARGET_BIG_ENDIAN
? (src_size
- dst_size
) * BITS_PER_UNIT
: 0;
1786 while (src_left
> 0)
1788 rtx dstreg
= reg_lowpart
;
1790 if (src_size
> dst_size
)
1793 int shift_amount
= shift
& (BITS_PER_WORD
- 1);
1795 srcword
= operand_subword_force (srcword
, src_left
>= 4 ? 0 : 4,
1797 if (shift_amount
> 0)
1799 dstreg
= gen_reg_rtx (SImode
);
1800 emit_insn (gen_lshrsi3 (dstreg
, srcword
,
1801 GEN_INT (shift_amount
)));
1805 dstreg
= gen_lowpart (dstmode
, dstreg
);
1808 dstmem
= adjust_address (copy_rtx (dst
), dstmode
, offset
);
1809 if (dst_size
> dst_mem_align
)
1811 enum insn_code icode
= (dstmode
== SImode
? CODE_FOR_movmisalignsi
1812 : CODE_FOR_movmisaligndi
);
1813 emit_insn (GEN_FCN (icode
) (dstmem
, dstreg
));
1816 emit_move_insn (dstmem
, dstreg
);
1818 if (TARGET_BIG_ENDIAN
)
1819 shift
-= dst_size
* BITS_PER_UNIT
;
1821 shift
+= dst_size
* BITS_PER_UNIT
;
1823 src_left
-= dst_size
;
1830 /* Subroutine of print_address_operand, print a single address offset OFF for
1831 a memory access of mode MEM_MODE, choosing between normal form and scaled
1832 form depending on the type of the insn. Misaligned memory references must
1833 use the scaled form. */
1836 print_address_offset (FILE *file
, rtx off
, machine_mode mem_mode
)
1840 if (c6x_current_insn
!= NULL_RTX
)
1842 pat
= PATTERN (c6x_current_insn
);
1843 if (GET_CODE (pat
) == COND_EXEC
)
1844 pat
= COND_EXEC_CODE (pat
);
1845 if (GET_CODE (pat
) == PARALLEL
)
1846 pat
= XVECEXP (pat
, 0, 0);
1848 if (GET_CODE (pat
) == SET
1849 && GET_CODE (SET_SRC (pat
)) == UNSPEC
1850 && XINT (SET_SRC (pat
), 1) == UNSPEC_MISALIGNED_ACCESS
)
1852 gcc_assert (CONST_INT_P (off
)
1853 && (INTVAL (off
) & (GET_MODE_SIZE (mem_mode
) - 1)) == 0);
1854 fprintf (file
, "[" HOST_WIDE_INT_PRINT_DEC
"]",
1855 INTVAL (off
) / GET_MODE_SIZE (mem_mode
));
1860 output_address (mem_mode
, off
);
1865 c6x_print_operand_punct_valid_p (unsigned char c
)
1867 return c
== '$' || c
== '.' || c
== '|';
1870 static void c6x_print_operand (FILE *, rtx
, int);
1872 /* Subroutine of c6x_print_operand; used to print a memory reference X to FILE. */
1875 c6x_print_address_operand (FILE *file
, rtx x
, machine_mode mem_mode
)
1878 switch (GET_CODE (x
))
1882 if (GET_CODE (x
) == POST_MODIFY
)
1883 output_address (mem_mode
, XEXP (x
, 0));
1884 off
= XEXP (XEXP (x
, 1), 1);
1885 if (XEXP (x
, 0) == stack_pointer_rtx
)
1887 if (GET_CODE (x
) == PRE_MODIFY
)
1888 gcc_assert (INTVAL (off
) > 0);
1890 gcc_assert (INTVAL (off
) < 0);
1892 if (CONST_INT_P (off
) && INTVAL (off
) < 0)
1894 fprintf (file
, "--");
1895 off
= GEN_INT (-INTVAL (off
));
1898 fprintf (file
, "++");
1899 if (GET_CODE (x
) == PRE_MODIFY
)
1900 output_address (mem_mode
, XEXP (x
, 0));
1901 print_address_offset (file
, off
, mem_mode
);
1906 if (CONST_INT_P (off
) && INTVAL (off
) < 0)
1908 fprintf (file
, "-");
1909 off
= GEN_INT (-INTVAL (off
));
1912 fprintf (file
, "+");
1913 output_address (mem_mode
, XEXP (x
, 0));
1914 print_address_offset (file
, off
, mem_mode
);
1918 gcc_assert (XEXP (x
, 0) != stack_pointer_rtx
);
1919 fprintf (file
, "--");
1920 output_address (mem_mode
, XEXP (x
, 0));
1921 fprintf (file
, "[1]");
1924 fprintf (file
, "++");
1925 output_address (mem_mode
, XEXP (x
, 0));
1926 fprintf (file
, "[1]");
1929 gcc_assert (XEXP (x
, 0) != stack_pointer_rtx
);
1930 output_address (mem_mode
, XEXP (x
, 0));
1931 fprintf (file
, "++[1]");
1934 output_address (mem_mode
, XEXP (x
, 0));
1935 fprintf (file
, "--[1]");
1941 gcc_assert (sdata_symbolic_operand (x
, Pmode
));
1942 fprintf (file
, "+B14(");
1943 output_addr_const (file
, x
);
1944 fprintf (file
, ")");
1948 switch (XINT (x
, 1))
1950 case UNSPEC_LOAD_GOT
:
1951 fputs ("$GOT(", file
);
1952 output_addr_const (file
, XVECEXP (x
, 0, 0));
1955 case UNSPEC_LOAD_SDATA
:
1956 output_addr_const (file
, XVECEXP (x
, 0, 0));
1964 gcc_assert (GET_CODE (x
) != MEM
);
1965 c6x_print_operand (file
, x
, 0);
1970 /* Return a single character, which is either 'l', 's', 'd' or 'm', which
1971 specifies the functional unit used by INSN. */
1974 c6x_get_unit_specifier (rtx_insn
*insn
)
1976 enum attr_units units
;
1978 if (insn_info
.exists ())
1980 int unit
= INSN_INFO_ENTRY (INSN_UID (insn
)).reservation
;
1981 return c6x_unit_names
[unit
][0];
1984 units
= get_attr_units (insn
);
2005 /* Prints the unit specifier field. */
2007 c6x_print_unit_specifier_field (FILE *file
, rtx_insn
*insn
)
2009 enum attr_units units
= get_attr_units (insn
);
2010 enum attr_cross cross
= get_attr_cross (insn
);
2011 enum attr_dest_regfile rf
= get_attr_dest_regfile (insn
);
2015 if (units
== UNITS_D_ADDR
)
2017 enum attr_addr_regfile arf
= get_attr_addr_regfile (insn
);
2019 gcc_assert (arf
!= ADDR_REGFILE_UNKNOWN
);
2020 half
= arf
== ADDR_REGFILE_A
? 1 : 2;
2021 t_half
= rf
== DEST_REGFILE_A
? 1 : 2;
2022 fprintf (file
, ".d%dt%d", half
, t_half
);
2026 if (insn_info
.exists ())
2028 int unit
= INSN_INFO_ENTRY (INSN_UID (insn
)).reservation
;
2030 fputs (c6x_unit_names
[unit
], file
);
2031 if (cross
== CROSS_Y
)
2036 gcc_assert (rf
!= DEST_REGFILE_UNKNOWN
);
2037 unitspec
= c6x_get_unit_specifier (insn
);
2038 half
= rf
== DEST_REGFILE_A
? 1 : 2;
2039 fprintf (file
, ".%c%d%s", unitspec
, half
, cross
== CROSS_Y
? "x" : "");
2042 /* Output assembly language output for the address ADDR to FILE. */
2044 c6x_print_operand_address (FILE *file
, machine_mode mode
, rtx addr
)
2046 c6x_print_address_operand (file
, addr
, mode
);
2049 /* Print an operand, X, to FILE, with an optional modifier in CODE.
2052 $ -- print the unit specifier field for the instruction.
2053 . -- print the predicate for the instruction or an emptry string for an
2055 | -- print "||" if the insn should be issued in parallel with the previous
2058 C -- print an opcode suffix for a reversed condition
2059 d -- H, W or D as a suffix for ADDA, based on the factor given by the
2061 D -- print either B, H, W or D as a suffix for ADDA, based on the size of
2063 J -- print a predicate
2064 j -- like J, but use reverse predicate
2065 k -- treat a CONST_INT as a register number and print it as a register
2066 k -- like k, but print out a doubleword register
2067 n -- print an integer operand, negated
2068 p -- print the low part of a DImode register
2069 P -- print the high part of a DImode register
2070 r -- print the absolute value of an integer operand, shifted right by 1
2071 R -- print the absolute value of an integer operand, shifted right by 2
2072 f -- the first clear bit in an integer operand assumed to be a mask for
2074 F -- the last clear bit in such a mask
2075 s -- the first set bit in an integer operand assumed to be a mask for
2077 S -- the last set bit in such a mask
2078 U -- print either 1 or 2, depending on the side of the machine used by
2082 c6x_print_operand (FILE *file
, rtx x
, int code
)
2091 if (GET_MODE (c6x_current_insn
) != TImode
)
2097 c6x_print_unit_specifier_field (file
, c6x_current_insn
);
2103 x
= current_insn_predicate
;
2106 unsigned int regno
= REGNO (XEXP (x
, 0));
2108 if (GET_CODE (x
) == EQ
)
2110 fputs (reg_names
[regno
], file
);
2116 mode
= GET_MODE (x
);
2123 enum rtx_code c
= GET_CODE (x
);
2125 c
= swap_condition (c
);
2126 fputs (GET_RTX_NAME (c
), file
);
2133 unsigned int regno
= REGNO (XEXP (x
, 0));
2134 if ((GET_CODE (x
) == EQ
) == (code
== 'J'))
2136 fputs (reg_names
[regno
], file
);
2141 gcc_assert (GET_CODE (x
) == CONST_INT
);
2143 fprintf (file
, "%s", reg_names
[v
]);
2146 gcc_assert (GET_CODE (x
) == CONST_INT
);
2148 gcc_assert ((v
& 1) == 0);
2149 fprintf (file
, "%s:%s", reg_names
[v
+ 1], reg_names
[v
]);
2156 gcc_assert (GET_CODE (x
) == CONST_INT
);
2158 for (i
= 0; i
< 32; i
++)
2160 HOST_WIDE_INT tst
= v
& 1;
2161 if (((code
== 'f' || code
== 'F') && !tst
)
2162 || ((code
== 's' || code
== 'S') && tst
))
2166 if (code
== 'f' || code
== 's')
2168 fprintf (file
, "%d", i
);
2173 HOST_WIDE_INT tst
= v
& 1;
2174 if ((code
== 'F' && tst
) || (code
== 'S' && !tst
))
2178 fprintf (file
, "%d", i
- 1);
2182 gcc_assert (GET_CODE (x
) == CONST_INT
);
2183 output_addr_const (file
, GEN_INT (-INTVAL (x
)));
2187 gcc_assert (GET_CODE (x
) == CONST_INT
);
2191 output_addr_const (file
, GEN_INT (v
>> 1));
2195 gcc_assert (GET_CODE (x
) == CONST_INT
);
2199 output_addr_const (file
, GEN_INT (v
>> 2));
2203 gcc_assert (GET_CODE (x
) == CONST_INT
);
2205 fputs (v
== 2 ? "h" : v
== 4 ? "w" : "d", file
);
2210 gcc_assert (GET_CODE (x
) == REG
);
2214 fputs (reg_names
[v
], file
);
2219 if (GET_CODE (x
) == CONST
)
2222 gcc_assert (GET_CODE (x
) == PLUS
);
2223 gcc_assert (GET_CODE (XEXP (x
, 1)) == CONST_INT
);
2224 v
= INTVAL (XEXP (x
, 1));
2228 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
2230 t
= SYMBOL_REF_DECL (x
);
2232 v
|= DECL_ALIGN_UNIT (t
);
2234 v
|= TYPE_ALIGN_UNIT (TREE_TYPE (t
));
2247 if (GET_CODE (x
) == PLUS
2248 || GET_RTX_CLASS (GET_CODE (x
)) == RTX_AUTOINC
)
2250 if (GET_CODE (x
) == CONST
|| GET_CODE (x
) == SYMBOL_REF
)
2252 gcc_assert (sdata_symbolic_operand (x
, Pmode
));
2257 gcc_assert (REG_P (x
));
2258 if (A_REGNO_P (REGNO (x
)))
2260 if (B_REGNO_P (REGNO (x
)))
2265 switch (GET_CODE (x
))
2268 if (GET_MODE_SIZE (mode
) == 8)
2269 fprintf (file
, "%s:%s", reg_names
[REGNO (x
) + 1],
2270 reg_names
[REGNO (x
)]);
2272 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
2277 gcc_assert (XEXP (x
, 0) != stack_pointer_rtx
);
2278 c6x_print_address_operand (file
, XEXP (x
, 0), GET_MODE (x
));
2283 output_addr_const (file
, x
);
2288 output_addr_const (file
, x
);
2292 output_operand_lossage ("invalid const_double operand");
2296 output_addr_const (file
, x
);
2301 /* Return TRUE if OP is a valid memory address with a base register of
2302 class C. If SMALL_OFFSET is true, we disallow memory references which would
2303 require a long offset with B14/B15. */
2306 c6x_mem_operand (rtx op
, enum reg_class c
, bool small_offset
)
2308 machine_mode mode
= GET_MODE (op
);
2309 rtx base
= XEXP (op
, 0);
2310 switch (GET_CODE (base
))
2316 && (XEXP (base
, 0) == stack_pointer_rtx
2317 || XEXP (base
, 0) == pic_offset_table_rtx
))
2319 if (!c6x_legitimate_address_p_1 (mode
, base
, true, true))
2330 base
= XEXP (base
, 0);
2336 gcc_assert (sdata_symbolic_operand (base
, Pmode
));
2337 return !small_offset
&& c
== B_REGS
;
2342 return TEST_HARD_REG_BIT (reg_class_contents
[ (int) (c
)], REGNO (base
));
2345 /* Returns true if X is a valid address for use in a memory reference
2346 of mode MODE. If STRICT is true, we do not allow pseudo registers
2347 in the address. NO_LARGE_OFFSET is true if we are examining an
2348 address for use in a load or store misaligned instruction, or
2349 recursively examining an operand inside a PRE/POST_MODIFY. */
2352 c6x_legitimate_address_p_1 (machine_mode mode
, rtx x
, bool strict
,
2353 bool no_large_offset
)
2357 enum rtx_code code
= GET_CODE (x
);
2363 /* We can't split these into word-sized pieces yet. */
2364 if (!TARGET_STDW
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
2366 if (GET_CODE (XEXP (x
, 1)) != PLUS
)
2368 if (!c6x_legitimate_address_p_1 (mode
, XEXP (x
, 1), strict
, true))
2370 if (!rtx_equal_p (XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)))
2378 /* We can't split these into word-sized pieces yet. */
2379 if (!TARGET_STDW
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
2388 return REGNO_OK_FOR_BASE_STRICT_P (REGNO (x
));
2390 return REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
));
2393 if (!REG_P (XEXP (x
, 0))
2394 || !c6x_legitimate_address_p_1 (mode
, XEXP (x
, 0), strict
, false))
2396 /* We cannot ensure currently that both registers end up in the
2397 same register file. */
2398 if (REG_P (XEXP (x
, 1)))
2401 if (mode
== BLKmode
)
2403 else if (mode
== VOIDmode
)
2404 /* ??? This can happen during ivopts. */
2407 size
= GET_MODE_SIZE (mode
);
2410 && GET_CODE (XEXP (x
, 1)) == UNSPEC
2411 && XINT (XEXP (x
, 1), 1) == UNSPEC_LOAD_SDATA
2412 && XEXP (x
, 0) == pic_offset_table_rtx
2413 && sdata_symbolic_operand (XVECEXP (XEXP (x
, 1), 0, 0), SImode
))
2414 return !no_large_offset
&& size
<= 4;
2417 && GET_CODE (XEXP (x
, 1)) == UNSPEC
2418 && XINT (XEXP (x
, 1), 1) == UNSPEC_LOAD_GOT
2419 && XEXP (x
, 0) == pic_offset_table_rtx
2420 && (GET_CODE (XVECEXP (XEXP (x
, 1), 0, 0)) == SYMBOL_REF
2421 || GET_CODE (XVECEXP (XEXP (x
, 1), 0, 0)) == LABEL_REF
))
2422 return !no_large_offset
;
2423 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2426 off
= INTVAL (XEXP (x
, 1));
2428 /* If the machine does not have doubleword load/stores, we'll use
2429 word size accesses. */
2431 if (size
== 2 * UNITS_PER_WORD
&& !TARGET_STDW
)
2432 size
= UNITS_PER_WORD
;
2434 if (((HOST_WIDE_INT
)size1
- 1) & off
)
2437 if (off
> -32 && off
< (size1
== size
? 32 : 28))
2439 if (no_large_offset
|| code
!= PLUS
|| XEXP (x
, 0) != stack_pointer_rtx
2440 || size1
> UNITS_PER_WORD
)
2442 return off
>= 0 && off
< 32768;
2447 return (!no_large_offset
2448 /* With -fpic, we must wrap it in an unspec to show the B14
2451 && GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
2452 && sdata_symbolic_operand (x
, Pmode
));
2460 c6x_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
2462 return c6x_legitimate_address_p_1 (mode
, x
, strict
, false);
2466 c6x_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
,
2467 rtx x ATTRIBUTE_UNUSED
)
2472 /* Implements TARGET_PREFERRED_RENAME_CLASS. */
2474 c6x_preferred_rename_class (reg_class_t cl
)
2477 return NONPREDICATE_A_REGS
;
2479 return NONPREDICATE_B_REGS
;
2480 if (cl
== ALL_REGS
|| cl
== GENERAL_REGS
)
2481 return NONPREDICATE_REGS
;
2485 /* Implements FINAL_PRESCAN_INSN. */
2487 c6x_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec ATTRIBUTE_UNUSED
,
2488 int noperands ATTRIBUTE_UNUSED
)
2490 c6x_current_insn
= insn
;
2493 /* A structure to describe the stack layout of a function. The layout is
2496 [saved frame pointer (or possibly padding0)]
2497 --> incoming stack pointer, new hard frame pointer
2498 [saved call-used regs]
2500 --> soft frame pointer
2502 [outgoing arguments]
2505 The structure members are laid out in this order. */
2510 /* Number of registers to save. */
2513 HOST_WIDE_INT frame
;
2514 int outgoing_arguments_size
;
2517 HOST_WIDE_INT to_allocate
;
2518 /* The offsets relative to the incoming stack pointer (which
2519 becomes HARD_FRAME_POINTER). */
2520 HOST_WIDE_INT frame_pointer_offset
;
2521 HOST_WIDE_INT b3_offset
;
2523 /* True if we should call push_rts/pop_rts to save and restore
2528 /* Return true if we need to save and modify the PIC register in the
2532 must_reload_pic_reg_p (void)
2534 struct cgraph_local_info
*i
= NULL
;
2539 i
= cgraph_node::local_info (current_function_decl
);
2541 if ((crtl
->uses_pic_offset_table
|| !crtl
->is_leaf
) && !i
->local
)
2546 /* Return 1 if we need to save REGNO. */
2548 c6x_save_reg (unsigned int regno
)
2550 return ((df_regs_ever_live_p (regno
)
2551 && !call_used_regs
[regno
]
2552 && !fixed_regs
[regno
])
2553 || (regno
== RETURN_ADDR_REGNO
2554 && (df_regs_ever_live_p (regno
)
2556 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& must_reload_pic_reg_p ()));
2559 /* Examine the number of regs NREGS we've determined we must save.
2560 Return true if we should use __c6xabi_push_rts/__c6xabi_pop_rts for
2561 prologue and epilogue. */
2564 use_push_rts_p (int nregs
)
2566 if (TARGET_INSNS_64PLUS
&& optimize_function_for_size_p (cfun
)
2567 && !cfun
->machine
->contains_sibcall
2568 && !cfun
->returns_struct
2569 && !TARGET_LONG_CALLS
2570 && nregs
>= 6 && !frame_pointer_needed
)
2575 /* Return number of saved general prupose registers. */
2578 c6x_nsaved_regs (void)
2583 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2584 if (c6x_save_reg (regno
))
2589 /* The safe debug order mandated by the ABI. */
2590 static unsigned reg_save_order
[] =
2592 REG_A10
, REG_A11
, REG_A12
, REG_A13
,
2594 REG_B10
, REG_B11
, REG_B12
, REG_B13
,
2598 #define N_SAVE_ORDER (sizeof reg_save_order / sizeof *reg_save_order)
2600 /* Compute the layout of the stack frame and store it in FRAME. */
2603 c6x_compute_frame_layout (struct c6x_frame
*frame
)
2605 HOST_WIDE_INT size
= get_frame_size ();
2606 HOST_WIDE_INT offset
;
2609 /* We use the four bytes which are technically inside the caller's frame,
2610 usually to save the frame pointer. */
2612 frame
->padding0
= 0;
2613 nregs
= c6x_nsaved_regs ();
2614 frame
->push_rts
= false;
2615 frame
->b3_offset
= 0;
2616 if (use_push_rts_p (nregs
))
2618 frame
->push_rts
= true;
2619 frame
->b3_offset
= (TARGET_BIG_ENDIAN
? -12 : -13) * 4;
2622 else if (c6x_save_reg (REG_B3
))
2625 for (idx
= N_SAVE_ORDER
- 1; reg_save_order
[idx
] != REG_B3
; idx
--)
2627 if (c6x_save_reg (reg_save_order
[idx
]))
2628 frame
->b3_offset
-= 4;
2631 frame
->nregs
= nregs
;
2633 if (size
== 0 && nregs
== 0)
2635 frame
->padding0
= 4;
2636 frame
->padding1
= frame
->padding2
= 0;
2637 frame
->frame_pointer_offset
= frame
->to_allocate
= 0;
2638 frame
->outgoing_arguments_size
= 0;
2642 if (!frame
->push_rts
)
2643 offset
+= frame
->nregs
* 4;
2645 if (offset
== 0 && size
== 0 && crtl
->outgoing_args_size
== 0
2647 /* Don't use the bottom of the caller's frame if we have no
2648 allocation of our own and call other functions. */
2649 frame
->padding0
= frame
->padding1
= 4;
2650 else if (offset
& 4)
2651 frame
->padding1
= 4;
2653 frame
->padding1
= 0;
2655 offset
+= frame
->padding0
+ frame
->padding1
;
2656 frame
->frame_pointer_offset
= offset
;
2659 frame
->outgoing_arguments_size
= crtl
->outgoing_args_size
;
2660 offset
+= frame
->outgoing_arguments_size
;
2662 if ((offset
& 4) == 0)
2663 frame
->padding2
= 8;
2665 frame
->padding2
= 4;
2666 frame
->to_allocate
= offset
+ frame
->padding2
;
2669 /* Return the offset between two registers, one to be eliminated, and the other
2670 its replacement, at the start of a routine. */
2673 c6x_initial_elimination_offset (int from
, int to
)
2675 struct c6x_frame frame
;
2676 c6x_compute_frame_layout (&frame
);
2678 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
2680 else if (from
== FRAME_POINTER_REGNUM
2681 && to
== HARD_FRAME_POINTER_REGNUM
)
2682 return -frame
.frame_pointer_offset
;
2685 gcc_assert (to
== STACK_POINTER_REGNUM
);
2687 if (from
== ARG_POINTER_REGNUM
)
2688 return frame
.to_allocate
+ (frame
.push_rts
? 56 : 0);
2690 gcc_assert (from
== FRAME_POINTER_REGNUM
);
2691 return frame
.to_allocate
- frame
.frame_pointer_offset
;
2695 /* Given FROM and TO register numbers, say whether this elimination is
2696 allowed. Frame pointer elimination is automatically handled. */
2699 c6x_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
2701 if (to
== STACK_POINTER_REGNUM
)
2702 return !frame_pointer_needed
;
2706 /* Emit insns to increment the stack pointer by OFFSET. If
2707 FRAME_RELATED_P, set the RTX_FRAME_RELATED_P flag on the insns.
2708 Does nothing if the offset is zero. */
2711 emit_add_sp_const (HOST_WIDE_INT offset
, bool frame_related_p
)
2713 rtx to_add
= GEN_INT (offset
);
2714 rtx orig_to_add
= to_add
;
2720 if (offset
< -32768 || offset
> 32767)
2722 rtx reg
= gen_rtx_REG (SImode
, REG_A0
);
2723 rtx low
= GEN_INT (trunc_int_for_mode (offset
, HImode
));
2725 insn
= emit_insn (gen_movsi_high (reg
, low
));
2726 if (frame_related_p
)
2727 RTX_FRAME_RELATED_P (insn
) = 1;
2728 insn
= emit_insn (gen_movsi_lo_sum (reg
, reg
, to_add
));
2729 if (frame_related_p
)
2730 RTX_FRAME_RELATED_P (insn
) = 1;
2733 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2735 if (frame_related_p
)
2738 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
2739 gen_rtx_SET (stack_pointer_rtx
,
2740 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
2743 RTX_FRAME_RELATED_P (insn
) = 1;
2747 /* Prologue and epilogue. */
2749 c6x_expand_prologue (void)
2751 struct c6x_frame frame
;
2755 HOST_WIDE_INT initial_offset
, off
, added_already
;
2757 c6x_compute_frame_layout (&frame
);
2759 if (flag_stack_usage_info
)
2760 current_function_static_stack_size
= frame
.to_allocate
;
2762 initial_offset
= -frame
.to_allocate
;
2765 emit_insn (gen_push_rts ());
2766 nsaved
= frame
.nregs
;
2769 /* If the offsets would be too large for the memory references we will
2770 create to save registers, do the stack allocation in two parts.
2771 Ensure by subtracting 8 that we don't store to the word pointed to
2772 by the stack pointer. */
2773 if (initial_offset
< -32768)
2774 initial_offset
= -frame
.frame_pointer_offset
- 8;
2776 if (frame
.to_allocate
> 0)
2777 gcc_assert (initial_offset
!= 0);
2779 off
= -initial_offset
+ 4 - frame
.padding0
;
2781 mem
= gen_frame_mem (Pmode
, stack_pointer_rtx
);
2784 if (frame_pointer_needed
)
2786 rtx fp_reg
= gen_rtx_REG (SImode
, REG_A15
);
2787 /* We go through some contortions here to both follow the ABI's
2788 recommendation that FP == incoming SP, and to avoid writing or
2789 reading the word pointed to by the stack pointer. */
2790 rtx addr
= gen_rtx_POST_MODIFY (Pmode
, stack_pointer_rtx
,
2791 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
2793 insn
= emit_move_insn (gen_frame_mem (Pmode
, addr
), fp_reg
);
2794 RTX_FRAME_RELATED_P (insn
) = 1;
2796 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, stack_pointer_rtx
,
2798 RTX_FRAME_RELATED_P (insn
) = 1;
2803 emit_add_sp_const (initial_offset
- added_already
, true);
2805 if (nsaved
< frame
.nregs
)
2809 for (i
= 0; i
< N_SAVE_ORDER
; i
++)
2811 int idx
= N_SAVE_ORDER
- i
- 1;
2812 unsigned regno
= reg_save_order
[idx
];
2814 machine_mode save_mode
= SImode
;
2816 if (regno
== REG_A15
&& frame_pointer_needed
)
2817 /* Already saved. */
2819 if (!c6x_save_reg (regno
))
2822 if (TARGET_STDW
&& (off
& 4) == 0 && off
<= 256
2824 && i
+ 1 < N_SAVE_ORDER
2825 && reg_save_order
[idx
- 1] == regno
- 1
2826 && c6x_save_reg (regno
- 1))
2832 reg
= gen_rtx_REG (save_mode
, regno
);
2833 off
-= GET_MODE_SIZE (save_mode
);
2835 insn
= emit_move_insn (adjust_address (mem
, save_mode
, off
),
2837 RTX_FRAME_RELATED_P (insn
) = 1;
2839 nsaved
+= hard_regno_nregs (regno
, save_mode
);
2842 gcc_assert (nsaved
== frame
.nregs
);
2843 emit_add_sp_const (-frame
.to_allocate
- initial_offset
, true);
2844 if (must_reload_pic_reg_p ())
2846 if (dsbt_decl
== NULL
)
2850 t
= build_index_type (integer_one_node
);
2851 t
= build_array_type (integer_type_node
, t
);
2852 t
= build_decl (BUILTINS_LOCATION
, VAR_DECL
,
2853 get_identifier ("__c6xabi_DSBT_BASE"), t
);
2854 DECL_ARTIFICIAL (t
) = 1;
2855 DECL_IGNORED_P (t
) = 1;
2856 DECL_EXTERNAL (t
) = 1;
2857 TREE_STATIC (t
) = 1;
2858 TREE_PUBLIC (t
) = 1;
2863 emit_insn (gen_setup_dsbt (pic_offset_table_rtx
,
2864 XEXP (DECL_RTL (dsbt_decl
), 0)));
2869 c6x_expand_epilogue (bool sibcall
)
2872 struct c6x_frame frame
;
2877 c6x_compute_frame_layout (&frame
);
2879 mem
= gen_frame_mem (Pmode
, stack_pointer_rtx
);
2881 /* Insert a dummy set/use of the stack pointer. This creates a
2882 scheduler barrier between the prologue saves and epilogue restores. */
2883 emit_insn (gen_epilogue_barrier (stack_pointer_rtx
, stack_pointer_rtx
));
2885 /* If the offsets would be too large for the memory references we will
2886 create to restore registers, do a preliminary stack adjustment here. */
2887 off
= frame
.to_allocate
- frame
.frame_pointer_offset
+ frame
.padding1
;
2890 nsaved
= frame
.nregs
;
2894 if (frame
.to_allocate
> 32768)
2896 /* Don't add the entire offset so that we leave an unused word
2897 above the stack pointer. */
2898 emit_add_sp_const ((off
- 16) & ~7, false);
2902 for (i
= 0; i
< N_SAVE_ORDER
; i
++)
2904 unsigned regno
= reg_save_order
[i
];
2906 machine_mode save_mode
= SImode
;
2908 if (!c6x_save_reg (regno
))
2910 if (regno
== REG_A15
&& frame_pointer_needed
)
2913 if (TARGET_STDW
&& (off
& 4) == 0 && off
< 256
2915 && i
+ 1 < N_SAVE_ORDER
2916 && reg_save_order
[i
+ 1] == regno
+ 1
2917 && c6x_save_reg (regno
+ 1))
2922 reg
= gen_rtx_REG (save_mode
, regno
);
2924 emit_move_insn (reg
, adjust_address (mem
, save_mode
, off
));
2926 off
+= GET_MODE_SIZE (save_mode
);
2927 nsaved
+= hard_regno_nregs (regno
, save_mode
);
2930 if (!frame_pointer_needed
)
2931 emit_add_sp_const (off
+ frame
.padding0
- 4, false);
2934 rtx fp_reg
= gen_rtx_REG (SImode
, REG_A15
);
2935 rtx addr
= gen_rtx_PRE_MODIFY (Pmode
, stack_pointer_rtx
,
2936 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
2938 emit_insn (gen_addsi3 (stack_pointer_rtx
, hard_frame_pointer_rtx
,
2940 emit_move_insn (fp_reg
, gen_frame_mem (Pmode
, addr
));
2943 gcc_assert (nsaved
== frame
.nregs
);
2947 emit_jump_insn (gen_pop_rts ());
2949 emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode
,
2950 RETURN_ADDR_REGNO
)));
2954 /* Return the value of the return address for the frame COUNT steps up
2955 from the current frame, after the prologue.
2956 We punt for everything but the current frame by returning const0_rtx. */
2959 c6x_return_addr_rtx (int count
)
2964 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNO
);
2967 /* Return true iff TYPE is one of the shadow types. */
2969 shadow_type_p (enum attr_type type
)
2971 return (type
== TYPE_SHADOW
|| type
== TYPE_LOAD_SHADOW
2972 || type
== TYPE_MULT_SHADOW
);
2975 /* Return true iff INSN is a shadow pattern. */
2977 shadow_p (rtx_insn
*insn
)
2979 if (!NONDEBUG_INSN_P (insn
) || recog_memoized (insn
) < 0)
2981 return shadow_type_p (get_attr_type (insn
));
2984 /* Return true iff INSN is a shadow or blockage pattern. */
2986 shadow_or_blockage_p (rtx_insn
*insn
)
2988 enum attr_type type
;
2989 if (!NONDEBUG_INSN_P (insn
) || recog_memoized (insn
) < 0)
2991 type
= get_attr_type (insn
);
2992 return shadow_type_p (type
) || type
== TYPE_BLOCKAGE
;
2995 /* Translate UNITS into a bitmask of units we can reserve for this
2998 get_reservation_flags (enum attr_units units
)
3004 return RESERVATION_FLAG_D
;
3006 return RESERVATION_FLAG_L
;
3008 return RESERVATION_FLAG_S
;
3010 return RESERVATION_FLAG_M
;
3012 return RESERVATION_FLAG_LS
;
3014 return RESERVATION_FLAG_DL
;
3016 return RESERVATION_FLAG_DS
;
3018 return RESERVATION_FLAG_DLS
;
3024 /* Compute the side of the machine used by INSN, which reserves UNITS.
3025 This must match the reservations in the scheduling description. */
3027 get_insn_side (rtx_insn
*insn
, enum attr_units units
)
3029 if (units
== UNITS_D_ADDR
)
3030 return (get_attr_addr_regfile (insn
) == ADDR_REGFILE_A
? 0 : 1);
3033 enum attr_dest_regfile rf
= get_attr_dest_regfile (insn
);
3034 if (rf
== DEST_REGFILE_ANY
)
3035 return get_attr_type (insn
) == TYPE_BRANCH
? 0 : 1;
3037 return rf
== DEST_REGFILE_A
? 0 : 1;
3041 /* After scheduling, walk the insns between HEAD and END and assign unit
3044 assign_reservations (rtx_insn
*head
, rtx_insn
*end
)
3047 for (insn
= head
; insn
!= NEXT_INSN (end
); insn
= NEXT_INSN (insn
))
3049 unsigned int sched_mask
, reserved
;
3050 rtx_insn
*within
, *last
;
3053 int rsrv_count
[2][4];
3056 if (GET_MODE (insn
) != TImode
)
3061 /* Find the last insn in the packet. It has a state recorded for it,
3062 which we can use to determine the units we should be using. */
3064 (within
!= NEXT_INSN (end
)
3065 && (within
== insn
|| GET_MODE (within
) != TImode
));
3066 within
= NEXT_INSN (within
))
3069 if (!NONDEBUG_INSN_P (within
))
3071 icode
= recog_memoized (within
);
3074 if (shadow_p (within
))
3076 if (INSN_INFO_ENTRY (INSN_UID (within
)).reservation
!= 0)
3077 reserved
|= 1 << INSN_INFO_ENTRY (INSN_UID (within
)).reservation
;
3080 if (last
== NULL_RTX
)
3083 sched_mask
= INSN_INFO_ENTRY (INSN_UID (last
)).unit_mask
;
3084 sched_mask
&= ~reserved
;
3086 memset (rsrv_count
, 0, sizeof rsrv_count
);
3087 rsrv
[0] = rsrv
[1] = ~0;
3088 for (i
= 0; i
< 8; i
++)
3092 unsigned unit_bit
= 1 << (unit
+ side
* UNIT_QID_SIDE_OFFSET
);
3093 /* Clear the bits which we expect to reserve in the following loop,
3094 leaving the ones set which aren't present in the scheduler's
3095 state and shouldn't be reserved. */
3096 if (sched_mask
& unit_bit
)
3097 rsrv
[i
/ 4] &= ~(1 << unit
);
3100 /* Walk through the insns that occur in the same cycle. We use multiple
3101 passes to assign units, assigning for insns with the most specific
3102 requirements first. */
3103 for (pass
= 0; pass
< 4; pass
++)
3105 (within
!= NEXT_INSN (end
)
3106 && (within
== insn
|| GET_MODE (within
) != TImode
));
3107 within
= NEXT_INSN (within
))
3109 int uid
= INSN_UID (within
);
3110 int this_rsrv
, side
;
3112 enum attr_units units
;
3113 enum attr_type type
;
3116 if (!NONDEBUG_INSN_P (within
))
3118 icode
= recog_memoized (within
);
3121 if (INSN_INFO_ENTRY (uid
).reservation
!= 0)
3123 units
= get_attr_units (within
);
3124 type
= get_attr_type (within
);
3125 this_rsrv
= get_reservation_flags (units
);
3128 side
= get_insn_side (within
, units
);
3130 /* Certain floating point instructions are treated specially. If
3131 an insn can choose between units it can reserve, and its
3132 reservation spans more than one cycle, the reservation contains
3133 special markers in the first cycle to help us reconstruct what
3134 the automaton chose. */
3135 if ((type
== TYPE_ADDDP
|| type
== TYPE_FP4
)
3136 && units
== UNITS_LS
)
3138 int test1_code
= ((type
== TYPE_FP4
? UNIT_QID_FPL1
: UNIT_QID_ADDDPL1
)
3139 + side
* UNIT_QID_SIDE_OFFSET
);
3140 int test2_code
= ((type
== TYPE_FP4
? UNIT_QID_FPS1
: UNIT_QID_ADDDPS1
)
3141 + side
* UNIT_QID_SIDE_OFFSET
);
3142 if ((sched_mask
& (1 << test1_code
)) != 0)
3144 this_rsrv
= RESERVATION_FLAG_L
;
3145 sched_mask
&= ~(1 << test1_code
);
3147 else if ((sched_mask
& (1 << test2_code
)) != 0)
3149 this_rsrv
= RESERVATION_FLAG_S
;
3150 sched_mask
&= ~(1 << test2_code
);
3154 if ((this_rsrv
& (this_rsrv
- 1)) == 0)
3156 int t
= exact_log2 (this_rsrv
) + side
* UNIT_QID_SIDE_OFFSET
;
3157 rsrv
[side
] |= this_rsrv
;
3158 INSN_INFO_ENTRY (uid
).reservation
= t
;
3164 for (j
= 0; j
< 4; j
++)
3165 if (this_rsrv
& (1 << j
))
3166 rsrv_count
[side
][j
]++;
3169 if ((pass
== 2 && this_rsrv
!= RESERVATION_FLAG_DLS
)
3170 || (pass
== 3 && this_rsrv
== RESERVATION_FLAG_DLS
))
3172 int best
= -1, best_cost
= INT_MAX
;
3173 for (j
= 0; j
< 4; j
++)
3174 if ((this_rsrv
& (1 << j
))
3175 && !(rsrv
[side
] & (1 << j
))
3176 && rsrv_count
[side
][j
] < best_cost
)
3178 best_cost
= rsrv_count
[side
][j
];
3181 gcc_assert (best
!= -1);
3182 rsrv
[side
] |= 1 << best
;
3183 for (j
= 0; j
< 4; j
++)
3184 if ((this_rsrv
& (1 << j
)) && j
!= best
)
3185 rsrv_count
[side
][j
]--;
3187 INSN_INFO_ENTRY (uid
).reservation
3188 = best
+ side
* UNIT_QID_SIDE_OFFSET
;
3194 /* Return a factor by which to weight unit imbalances for a reservation
3197 unit_req_factor (enum unitreqs r
)
3219 /* Examine INSN, and store in REQ1/SIDE1 and REQ2/SIDE2 the unit
3220 requirements. Returns zero if INSN can't be handled, otherwise
3221 either one or two to show how many of the two pairs are in use.
3222 REQ1 is always used, it holds what is normally thought of as the
3223 instructions reservation, e.g. UNIT_REQ_DL. REQ2 is used to either
3224 describe a cross path, or for loads/stores, the T unit. */
3226 get_unit_reqs (rtx_insn
*insn
, int *req1
, int *side1
, int *req2
, int *side2
)
3228 enum attr_units units
;
3229 enum attr_cross cross
;
3232 if (!NONDEBUG_INSN_P (insn
) || recog_memoized (insn
) < 0)
3234 units
= get_attr_units (insn
);
3235 if (units
== UNITS_UNKNOWN
)
3237 side
= get_insn_side (insn
, units
);
3238 cross
= get_attr_cross (insn
);
3240 req
= (units
== UNITS_D
? UNIT_REQ_D
3241 : units
== UNITS_D_ADDR
? UNIT_REQ_D
3242 : units
== UNITS_DL
? UNIT_REQ_DL
3243 : units
== UNITS_DS
? UNIT_REQ_DS
3244 : units
== UNITS_L
? UNIT_REQ_L
3245 : units
== UNITS_LS
? UNIT_REQ_LS
3246 : units
== UNITS_S
? UNIT_REQ_S
3247 : units
== UNITS_M
? UNIT_REQ_M
3248 : units
== UNITS_DLS
? UNIT_REQ_DLS
3250 gcc_assert (req
!= -1);
3253 if (units
== UNITS_D_ADDR
)
3256 *side2
= side
^ (cross
== CROSS_Y
? 1 : 0);
3259 else if (cross
== CROSS_Y
)
3268 /* Walk the insns between and including HEAD and TAIL, and mark the
3269 resource requirements in the unit_reqs table. */
3271 count_unit_reqs (unit_req_table reqs
, rtx_insn
*head
, rtx_insn
*tail
)
3275 memset (reqs
, 0, sizeof (unit_req_table
));
3277 for (insn
= head
; insn
!= NEXT_INSN (tail
); insn
= NEXT_INSN (insn
))
3279 int side1
, side2
, req1
, req2
;
3281 switch (get_unit_reqs (insn
, &req1
, &side1
, &req2
, &side2
))
3284 reqs
[side2
][req2
]++;
3287 reqs
[side1
][req1
]++;
3293 /* Update the table REQS by merging more specific unit reservations into
3294 more general ones, i.e. counting (for example) UNIT_REQ_D also in
3295 UNIT_REQ_DL, DS, and DLS. */
3297 merge_unit_reqs (unit_req_table reqs
)
3300 for (side
= 0; side
< 2; side
++)
3302 int d
= reqs
[side
][UNIT_REQ_D
];
3303 int l
= reqs
[side
][UNIT_REQ_L
];
3304 int s
= reqs
[side
][UNIT_REQ_S
];
3305 int dl
= reqs
[side
][UNIT_REQ_DL
];
3306 int ls
= reqs
[side
][UNIT_REQ_LS
];
3307 int ds
= reqs
[side
][UNIT_REQ_DS
];
3309 reqs
[side
][UNIT_REQ_DL
] += d
;
3310 reqs
[side
][UNIT_REQ_DL
] += l
;
3311 reqs
[side
][UNIT_REQ_DS
] += d
;
3312 reqs
[side
][UNIT_REQ_DS
] += s
;
3313 reqs
[side
][UNIT_REQ_LS
] += l
;
3314 reqs
[side
][UNIT_REQ_LS
] += s
;
3315 reqs
[side
][UNIT_REQ_DLS
] += ds
+ dl
+ ls
+ d
+ l
+ s
;
3319 /* Examine the table REQS and return a measure of unit imbalance by comparing
3320 the two sides of the machine. If, for example, D1 is used twice and D2
3321 used not at all, the return value should be 1 in the absence of other
3324 unit_req_imbalance (unit_req_table reqs
)
3329 for (i
= 0; i
< UNIT_REQ_MAX
; i
++)
3331 int factor
= unit_req_factor ((enum unitreqs
) i
);
3332 int diff
= abs (reqs
[0][i
] - reqs
[1][i
]);
3333 val
+= (diff
+ factor
- 1) / factor
/ 2;
3338 /* Return the resource-constrained minimum iteration interval given the
3339 data in the REQS table. This must have been processed with
3340 merge_unit_reqs already. */
3342 res_mii (unit_req_table reqs
)
3346 for (side
= 0; side
< 2; side
++)
3347 for (req
= 0; req
< UNIT_REQ_MAX
; req
++)
3349 int factor
= unit_req_factor ((enum unitreqs
) req
);
3350 worst
= MAX ((reqs
[side
][UNIT_REQ_D
] + factor
- 1) / factor
, worst
);
3356 /* Examine INSN, and store in PMASK1 and PMASK2 bitmasks that represent
3357 the operands that are involved in the (up to) two reservations, as
3358 found by get_unit_reqs. Return true if we did this successfully, false
3359 if we couldn't identify what to do with INSN. */
3361 get_unit_operand_masks (rtx_insn
*insn
, unsigned int *pmask1
,
3362 unsigned int *pmask2
)
3364 enum attr_op_pattern op_pat
;
3366 if (recog_memoized (insn
) < 0)
3368 if (GET_CODE (PATTERN (insn
)) == COND_EXEC
)
3370 extract_insn (insn
);
3371 op_pat
= get_attr_op_pattern (insn
);
3372 if (op_pat
== OP_PATTERN_DT
)
3374 gcc_assert (recog_data
.n_operands
== 2);
3379 else if (op_pat
== OP_PATTERN_TD
)
3381 gcc_assert (recog_data
.n_operands
== 2);
3386 else if (op_pat
== OP_PATTERN_SXS
)
3388 gcc_assert (recog_data
.n_operands
== 3);
3389 *pmask1
= (1 << 0) | (1 << 2);
3393 else if (op_pat
== OP_PATTERN_SX
)
3395 gcc_assert (recog_data
.n_operands
== 2);
3400 else if (op_pat
== OP_PATTERN_SSX
)
3402 gcc_assert (recog_data
.n_operands
== 3);
3403 *pmask1
= (1 << 0) | (1 << 1);
3410 /* Try to replace a register in INSN, which has corresponding rename info
3411 from regrename_analyze in INFO. OP_MASK and ORIG_SIDE provide information
3412 about the operands that must be renamed and the side they are on.
3413 REQS is the table of unit reservations in the loop between HEAD and TAIL.
3414 We recompute this information locally after our transformation, and keep
3415 it only if we managed to improve the balance. */
3417 try_rename_operands (rtx_insn
*head
, rtx_insn
*tail
, unit_req_table reqs
,
3419 insn_rr_info
*info
, unsigned int op_mask
, int orig_side
)
3421 enum reg_class super_class
= orig_side
== 0 ? B_REGS
: A_REGS
;
3422 HARD_REG_SET unavailable
;
3423 du_head_p this_head
;
3424 struct du_chain
*chain
;
3427 int best_reg
, old_reg
;
3428 vec
<du_head_p
> involved_chains
= vNULL
;
3429 unit_req_table new_reqs
;
3432 for (i
= 0, tmp_mask
= op_mask
; tmp_mask
; i
++)
3435 if ((tmp_mask
& (1 << i
)) == 0)
3437 if (info
->op_info
[i
].n_chains
!= 1)
3439 op_chain
= regrename_chain_from_id (info
->op_info
[i
].heads
[0]->id
);
3440 involved_chains
.safe_push (op_chain
);
3441 tmp_mask
&= ~(1 << i
);
3444 if (involved_chains
.length () > 1)
3447 this_head
= involved_chains
[0];
3448 if (this_head
->cannot_rename
)
3451 for (chain
= this_head
->first
; chain
; chain
= chain
->next_use
)
3453 unsigned int mask1
, mask2
, mask_changed
;
3454 int count
, side1
, side2
, req1
, req2
;
3455 insn_rr_info
*this_rr
= &insn_rr
[INSN_UID (chain
->insn
)];
3457 count
= get_unit_reqs (chain
->insn
, &req1
, &side1
, &req2
, &side2
);
3462 if (!get_unit_operand_masks (chain
->insn
, &mask1
, &mask2
))
3465 extract_insn (chain
->insn
);
3468 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3471 int n_this_op
= this_rr
->op_info
[i
].n_chains
;
3472 for (j
= 0; j
< n_this_op
; j
++)
3474 du_head_p other
= this_rr
->op_info
[i
].heads
[j
];
3475 if (regrename_chain_from_id (other
->id
) == this_head
)
3483 mask_changed
|= 1 << i
;
3485 gcc_assert (mask_changed
!= 0);
3486 if (mask_changed
!= mask1
&& mask_changed
!= mask2
)
3490 /* If we get here, we can do the renaming. */
3491 COMPL_HARD_REG_SET (unavailable
, reg_class_contents
[(int) super_class
]);
3493 old_reg
= this_head
->regno
;
3495 find_rename_reg (this_head
, super_class
, &unavailable
, old_reg
, true);
3497 ok
= regrename_do_replace (this_head
, best_reg
);
3500 count_unit_reqs (new_reqs
, head
, PREV_INSN (tail
));
3501 merge_unit_reqs (new_reqs
);
3504 fprintf (dump_file
, "reshuffle for insn %d, op_mask %x, "
3505 "original side %d, new reg %d\n",
3506 INSN_UID (insn
), op_mask
, orig_side
, best_reg
);
3507 fprintf (dump_file
, " imbalance %d -> %d\n",
3508 unit_req_imbalance (reqs
), unit_req_imbalance (new_reqs
));
3510 if (unit_req_imbalance (new_reqs
) > unit_req_imbalance (reqs
))
3512 ok
= regrename_do_replace (this_head
, old_reg
);
3516 memcpy (reqs
, new_reqs
, sizeof (unit_req_table
));
3519 involved_chains
.release ();
3522 /* Find insns in LOOP which would, if shifted to the other side
3523 of the machine, reduce an imbalance in the unit reservations. */
3525 reshuffle_units (basic_block loop
)
3527 rtx_insn
*head
= BB_HEAD (loop
);
3528 rtx_insn
*tail
= BB_END (loop
);
3530 unit_req_table reqs
;
3535 count_unit_reqs (reqs
, head
, PREV_INSN (tail
));
3536 merge_unit_reqs (reqs
);
3538 regrename_init (true);
3540 bitmap_initialize (&bbs
, &bitmap_default_obstack
);
3542 FOR_EACH_EDGE (e
, ei
, loop
->preds
)
3543 bitmap_set_bit (&bbs
, e
->src
->index
);
3545 bitmap_set_bit (&bbs
, loop
->index
);
3546 regrename_analyze (&bbs
);
3548 for (insn
= head
; insn
!= NEXT_INSN (tail
); insn
= NEXT_INSN (insn
))
3550 enum attr_units units
;
3551 int count
, side1
, side2
, req1
, req2
;
3552 unsigned int mask1
, mask2
;
3555 if (!NONDEBUG_INSN_P (insn
))
3558 count
= get_unit_reqs (insn
, &req1
, &side1
, &req2
, &side2
);
3563 if (!get_unit_operand_masks (insn
, &mask1
, &mask2
))
3566 info
= &insn_rr
[INSN_UID (insn
)];
3567 if (info
->op_info
== NULL
)
3570 if (reqs
[side1
][req1
] > 1
3571 && reqs
[side1
][req1
] > 2 * reqs
[side1
^ 1][req1
])
3573 try_rename_operands (head
, tail
, reqs
, insn
, info
, mask1
, side1
);
3576 units
= get_attr_units (insn
);
3577 if (units
== UNITS_D_ADDR
)
3579 gcc_assert (count
== 2);
3580 if (reqs
[side2
][req2
] > 1
3581 && reqs
[side2
][req2
] > 2 * reqs
[side2
^ 1][req2
])
3583 try_rename_operands (head
, tail
, reqs
, insn
, info
, mask2
, side2
);
3587 regrename_finish ();
3590 /* Backend scheduling state. */
3591 typedef struct c6x_sched_context
3593 /* The current scheduler clock, saved in the sched_reorder hook. */
3594 int curr_sched_clock
;
3596 /* Number of insns issued so far in this cycle. */
3597 int issued_this_cycle
;
3599 /* We record the time at which each jump occurs in JUMP_CYCLES. The
3600 theoretical maximum for number of jumps in flight is 12: 2 every
3601 cycle, with a latency of 6 cycles each. This is a circular
3602 buffer; JUMP_CYCLE_INDEX is the pointer to the start. Earlier
3603 jumps have a higher index. This array should be accessed through
3604 the jump_cycle function. */
3605 int jump_cycles
[12];
3606 int jump_cycle_index
;
3608 /* In parallel with jump_cycles, this array records the opposite of
3609 the condition used in each pending jump. This is used to
3610 predicate insns that are scheduled in the jump's delay slots. If
3611 this is NULL_RTX no such predication happens. */
3614 /* Similar to the jump_cycles mechanism, but here we take into
3615 account all insns with delay slots, to avoid scheduling asms into
3617 int delays_finished_at
;
3619 /* The following variable value is the last issued insn. */
3620 rtx_insn
*last_scheduled_insn
;
3621 /* The last issued insn that isn't a shadow of another. */
3622 rtx_insn
*last_scheduled_iter0
;
3624 /* The following variable value is DFA state before issuing the
3625 first insn in the current clock cycle. We do not use this member
3626 of the structure directly; we copy the data in and out of
3627 prev_cycle_state. */
3628 state_t prev_cycle_state_ctx
;
3630 int reg_n_accesses
[FIRST_PSEUDO_REGISTER
];
3631 int reg_n_xaccesses
[FIRST_PSEUDO_REGISTER
];
3632 int reg_set_in_cycle
[FIRST_PSEUDO_REGISTER
];
3634 int tmp_reg_n_accesses
[FIRST_PSEUDO_REGISTER
];
3635 int tmp_reg_n_xaccesses
[FIRST_PSEUDO_REGISTER
];
3636 } *c6x_sched_context_t
;
3638 /* The current scheduling state. */
3639 static struct c6x_sched_context ss
;
3641 /* The following variable value is DFA state before issuing the first insn
3642 in the current clock cycle. This is used in c6x_variable_issue for
3643 comparison with the state after issuing the last insn in a cycle. */
3644 static state_t prev_cycle_state
;
3646 /* Set when we discover while processing an insn that it would lead to too
3647 many accesses of the same register. */
3648 static bool reg_access_stall
;
3650 /* The highest insn uid after delayed insns were split, but before loop bodies
3651 were copied by the modulo scheduling code. */
3652 static int sploop_max_uid_iter0
;
3654 /* Look up the jump cycle with index N. For an out-of-bounds N, we return 0,
3655 so the caller does not specifically have to test for it. */
3657 get_jump_cycle (int n
)
3661 n
+= ss
.jump_cycle_index
;
3664 return ss
.jump_cycles
[n
];
3667 /* Look up the jump condition with index N. */
3669 get_jump_cond (int n
)
3673 n
+= ss
.jump_cycle_index
;
3676 return ss
.jump_cond
[n
];
3679 /* Return the index of the first jump that occurs after CLOCK_VAR. If no jump
3680 has delay slots beyond CLOCK_VAR, return -1. */
3682 first_jump_index (int clock_var
)
3688 int t
= get_jump_cycle (n
);
3697 /* Add a new entry in our scheduling state for a jump that occurs in CYCLE
3698 and has the opposite condition of COND. */
3700 record_jump (int cycle
, rtx cond
)
3702 if (ss
.jump_cycle_index
== 0)
3703 ss
.jump_cycle_index
= 11;
3705 ss
.jump_cycle_index
--;
3706 ss
.jump_cycles
[ss
.jump_cycle_index
] = cycle
;
3707 ss
.jump_cond
[ss
.jump_cycle_index
] = cond
;
3710 /* Set the clock cycle of INSN to CYCLE. Also clears the insn's entry in
3713 insn_set_clock (rtx insn
, int cycle
)
3715 unsigned uid
= INSN_UID (insn
);
3717 if (uid
>= INSN_INFO_LENGTH
)
3718 insn_info
.safe_grow (uid
* 5 / 4 + 10);
3720 INSN_INFO_ENTRY (uid
).clock
= cycle
;
3721 INSN_INFO_ENTRY (uid
).new_cond
= NULL
;
3722 INSN_INFO_ENTRY (uid
).reservation
= 0;
3723 INSN_INFO_ENTRY (uid
).ebb_start
= false;
3726 /* Return the clock cycle we set for the insn with uid UID. */
3728 insn_uid_get_clock (int uid
)
3730 return INSN_INFO_ENTRY (uid
).clock
;
3733 /* Return the clock cycle we set for INSN. */
3735 insn_get_clock (rtx insn
)
3737 return insn_uid_get_clock (INSN_UID (insn
));
3740 /* Examine INSN, and if it is a conditional jump of any kind, return
3741 the opposite of the condition in which it branches. Otherwise,
3744 condjump_opposite_condition (rtx insn
)
3746 rtx pat
= PATTERN (insn
);
3747 int icode
= INSN_CODE (insn
);
3750 if (icode
== CODE_FOR_br_true
|| icode
== CODE_FOR_br_false
)
3752 x
= XEXP (SET_SRC (pat
), 0);
3753 if (icode
== CODE_FOR_br_false
)
3756 if (GET_CODE (pat
) == COND_EXEC
)
3758 rtx t
= COND_EXEC_CODE (pat
);
3759 if ((GET_CODE (t
) == PARALLEL
3760 && GET_CODE (XVECEXP (t
, 0, 0)) == RETURN
)
3761 || (GET_CODE (t
) == UNSPEC
&& XINT (t
, 1) == UNSPEC_REAL_JUMP
)
3762 || (GET_CODE (t
) == SET
&& SET_DEST (t
) == pc_rtx
))
3763 x
= COND_EXEC_TEST (pat
);
3768 enum rtx_code code
= GET_CODE (x
);
3769 x
= gen_rtx_fmt_ee (code
== EQ
? NE
: EQ
,
3770 GET_MODE (x
), XEXP (x
, 0),
3776 /* Return true iff COND1 and COND2 are exactly opposite conditions
3777 one of them NE and the other EQ. */
3779 conditions_opposite_p (rtx cond1
, rtx cond2
)
3781 return (rtx_equal_p (XEXP (cond1
, 0), XEXP (cond2
, 0))
3782 && rtx_equal_p (XEXP (cond1
, 1), XEXP (cond2
, 1))
3783 && GET_CODE (cond1
) == reverse_condition (GET_CODE (cond2
)));
3786 /* Return true if we can add a predicate COND to INSN, or if INSN
3787 already has that predicate. If DOIT is true, also perform the
3790 predicate_insn (rtx_insn
*insn
, rtx cond
, bool doit
)
3793 if (cond
== NULL_RTX
)
3799 if (get_attr_predicable (insn
) == PREDICABLE_YES
3800 && GET_CODE (PATTERN (insn
)) != COND_EXEC
)
3804 cond
= copy_rtx (cond
);
3805 rtx newpat
= gen_rtx_COND_EXEC (VOIDmode
, cond
, PATTERN (insn
));
3806 PATTERN (insn
) = newpat
;
3807 INSN_CODE (insn
) = -1;
3811 if (GET_CODE (PATTERN (insn
)) == COND_EXEC
3812 && rtx_equal_p (COND_EXEC_TEST (PATTERN (insn
)), cond
))
3814 icode
= INSN_CODE (insn
);
3815 if (icode
== CODE_FOR_real_jump
3816 || icode
== CODE_FOR_jump
3817 || icode
== CODE_FOR_indirect_jump
)
3819 rtx pat
= PATTERN (insn
);
3820 rtx dest
= (icode
== CODE_FOR_real_jump
? XVECEXP (pat
, 0, 0)
3821 : icode
== CODE_FOR_jump
? XEXP (SET_SRC (pat
), 0)
3827 newpat
= gen_rtx_COND_EXEC (VOIDmode
, cond
, PATTERN (insn
));
3829 newpat
= gen_br_true (cond
, XEXP (cond
, 0), dest
);
3830 PATTERN (insn
) = newpat
;
3831 INSN_CODE (insn
) = -1;
3835 if (INSN_CODE (insn
) == CODE_FOR_br_true
)
3837 rtx br_cond
= XEXP (SET_SRC (PATTERN (insn
)), 0);
3838 return rtx_equal_p (br_cond
, cond
);
3840 if (INSN_CODE (insn
) == CODE_FOR_br_false
)
3842 rtx br_cond
= XEXP (SET_SRC (PATTERN (insn
)), 0);
3843 return conditions_opposite_p (br_cond
, cond
);
3848 /* Initialize SC. Used by c6x_init_sched_context and c6x_sched_init. */
3850 init_sched_state (c6x_sched_context_t sc
)
3852 sc
->last_scheduled_insn
= NULL
;
3853 sc
->last_scheduled_iter0
= NULL
;
3854 sc
->issued_this_cycle
= 0;
3855 memset (sc
->jump_cycles
, 0, sizeof sc
->jump_cycles
);
3856 memset (sc
->jump_cond
, 0, sizeof sc
->jump_cond
);
3857 sc
->jump_cycle_index
= 0;
3858 sc
->delays_finished_at
= 0;
3859 sc
->curr_sched_clock
= 0;
3861 sc
->prev_cycle_state_ctx
= xmalloc (dfa_state_size
);
3863 memset (sc
->reg_n_accesses
, 0, sizeof sc
->reg_n_accesses
);
3864 memset (sc
->reg_n_xaccesses
, 0, sizeof sc
->reg_n_xaccesses
);
3865 memset (sc
->reg_set_in_cycle
, 0, sizeof sc
->reg_set_in_cycle
);
3867 state_reset (sc
->prev_cycle_state_ctx
);
3870 /* Allocate store for new scheduling context. */
3872 c6x_alloc_sched_context (void)
3874 return xmalloc (sizeof (struct c6x_sched_context
));
3877 /* If CLEAN_P is true then initializes _SC with clean data,
3878 and from the global context otherwise. */
3880 c6x_init_sched_context (void *_sc
, bool clean_p
)
3882 c6x_sched_context_t sc
= (c6x_sched_context_t
) _sc
;
3886 init_sched_state (sc
);
3891 sc
->prev_cycle_state_ctx
= xmalloc (dfa_state_size
);
3892 memcpy (sc
->prev_cycle_state_ctx
, prev_cycle_state
, dfa_state_size
);
3896 /* Sets the global scheduling context to the one pointed to by _SC. */
3898 c6x_set_sched_context (void *_sc
)
3900 c6x_sched_context_t sc
= (c6x_sched_context_t
) _sc
;
3902 gcc_assert (sc
!= NULL
);
3904 memcpy (prev_cycle_state
, sc
->prev_cycle_state_ctx
, dfa_state_size
);
3907 /* Clear data in _SC. */
3909 c6x_clear_sched_context (void *_sc
)
3911 c6x_sched_context_t sc
= (c6x_sched_context_t
) _sc
;
3912 gcc_assert (_sc
!= NULL
);
3914 free (sc
->prev_cycle_state_ctx
);
3919 c6x_free_sched_context (void *_sc
)
3924 /* True if we are currently performing a preliminary scheduling
3925 pass before modulo scheduling; we can't allow the scheduler to
3926 modify instruction patterns using packetization assumptions,
3927 since there will be another scheduling pass later if modulo
3928 scheduling fails. */
3929 static bool in_hwloop
;
3931 /* Provide information about speculation capabilities, and set the
3932 DO_BACKTRACKING flag. */
3934 c6x_set_sched_flags (spec_info_t spec_info
)
3936 unsigned int *flags
= &(current_sched_info
->flags
);
3938 if (*flags
& SCHED_EBB
)
3940 *flags
|= DO_BACKTRACKING
| DO_PREDICATION
;
3943 *flags
|= DONT_BREAK_DEPENDENCIES
;
3945 spec_info
->mask
= 0;
3948 /* Implement the TARGET_SCHED_ISSUE_RATE hook. */
3951 c6x_issue_rate (void)
3956 /* Used together with the collapse_ndfa option, this ensures that we reach a
3957 deterministic automaton state before trying to advance a cycle.
3958 With collapse_ndfa, genautomata creates advance cycle arcs only for
3959 such deterministic states. */
3962 c6x_sched_dfa_pre_cycle_insn (void)
3967 /* We're beginning a new block. Initialize data structures as necessary. */
3970 c6x_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
3971 int sched_verbose ATTRIBUTE_UNUSED
,
3972 int max_ready ATTRIBUTE_UNUSED
)
3974 if (prev_cycle_state
== NULL
)
3976 prev_cycle_state
= xmalloc (dfa_state_size
);
3978 init_sched_state (&ss
);
3979 state_reset (prev_cycle_state
);
3982 /* We are about to being issuing INSN. Return nonzero if we cannot
3983 issue it on given cycle CLOCK and return zero if we should not sort
3984 the ready queue on the next clock start.
3985 For C6X, we use this function just to copy the previous DFA state
3986 for comparison purposes. */
3989 c6x_dfa_new_cycle (FILE *dump ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
3990 rtx_insn
*insn ATTRIBUTE_UNUSED
,
3991 int last_clock ATTRIBUTE_UNUSED
,
3992 int clock ATTRIBUTE_UNUSED
, int *sort_p ATTRIBUTE_UNUSED
)
3994 if (clock
!= last_clock
)
3995 memcpy (prev_cycle_state
, curr_state
, dfa_state_size
);
4000 c6x_mark_regno_read (int regno
, bool cross
)
4002 int t
= ++ss
.tmp_reg_n_accesses
[regno
];
4005 reg_access_stall
= true;
4009 int set_cycle
= ss
.reg_set_in_cycle
[regno
];
4010 /* This must be done in this way rather than by tweaking things in
4011 adjust_cost, since the stall occurs even for insns with opposite
4012 predicates, and the scheduler may not even see a dependency. */
4013 if (set_cycle
> 0 && set_cycle
== ss
.curr_sched_clock
)
4014 reg_access_stall
= true;
4015 /* This doesn't quite do anything yet as we're only modeling one
4017 ++ss
.tmp_reg_n_xaccesses
[regno
];
4021 /* Note that REG is read in the insn being examined. If CROSS, it
4022 means the access is through a cross path. Update the temporary reg
4023 access arrays, and set REG_ACCESS_STALL if the insn can't be issued
4024 in the current cycle. */
4027 c6x_mark_reg_read (rtx reg
, bool cross
)
4029 unsigned regno
= REGNO (reg
);
4030 unsigned nregs
= REG_NREGS (reg
);
4033 c6x_mark_regno_read (regno
+ nregs
, cross
);
4036 /* Note that register REG is written in cycle CYCLES. */
4039 c6x_mark_reg_written (rtx reg
, int cycles
)
4041 unsigned regno
= REGNO (reg
);
4042 unsigned nregs
= REG_NREGS (reg
);
4045 ss
.reg_set_in_cycle
[regno
+ nregs
] = cycles
;
4048 /* Update the register state information for an instruction whose
4049 body is X. Return true if the instruction has to be delayed until the
4053 c6x_registers_update (rtx_insn
*insn
)
4055 enum attr_cross cross
;
4056 enum attr_dest_regfile destrf
;
4060 if (!reload_completed
|| recog_memoized (insn
) < 0)
4063 reg_access_stall
= false;
4064 memcpy (ss
.tmp_reg_n_accesses
, ss
.reg_n_accesses
,
4065 sizeof ss
.tmp_reg_n_accesses
);
4066 memcpy (ss
.tmp_reg_n_xaccesses
, ss
.reg_n_xaccesses
,
4067 sizeof ss
.tmp_reg_n_xaccesses
);
4069 extract_insn (insn
);
4071 cross
= get_attr_cross (insn
);
4072 destrf
= get_attr_dest_regfile (insn
);
4074 nops
= recog_data
.n_operands
;
4076 if (GET_CODE (x
) == COND_EXEC
)
4078 c6x_mark_reg_read (XEXP (XEXP (x
, 0), 0), false);
4082 for (i
= 0; i
< nops
; i
++)
4084 rtx op
= recog_data
.operand
[i
];
4085 if (recog_data
.operand_type
[i
] == OP_OUT
)
4089 bool this_cross
= cross
;
4090 if (destrf
== DEST_REGFILE_A
&& A_REGNO_P (REGNO (op
)))
4092 if (destrf
== DEST_REGFILE_B
&& B_REGNO_P (REGNO (op
)))
4094 c6x_mark_reg_read (op
, this_cross
);
4096 else if (MEM_P (op
))
4099 switch (GET_CODE (op
))
4108 c6x_mark_reg_read (op
, false);
4113 gcc_assert (GET_CODE (op
) == PLUS
);
4116 c6x_mark_reg_read (XEXP (op
, 0), false);
4117 if (REG_P (XEXP (op
, 1)))
4118 c6x_mark_reg_read (XEXP (op
, 1), false);
4123 c6x_mark_regno_read (REG_B14
, false);
4129 else if (!CONSTANT_P (op
) && strlen (recog_data
.constraints
[i
]) > 0)
4132 return reg_access_stall
;
4135 /* Helper function for the TARGET_SCHED_REORDER and
4136 TARGET_SCHED_REORDER2 hooks. If scheduling an insn would be unsafe
4137 in the current cycle, move it down in the ready list and return the
4138 number of non-unsafe insns. */
4141 c6x_sched_reorder_1 (rtx_insn
**ready
, int *pn_ready
, int clock_var
)
4143 int n_ready
= *pn_ready
;
4144 rtx_insn
**e_ready
= ready
+ n_ready
;
4148 /* Keep track of conflicts due to a limit number of register accesses,
4149 and due to stalls incurred by too early accesses of registers using
4152 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
4154 rtx_insn
*insn
= *insnp
;
4155 int icode
= recog_memoized (insn
);
4156 bool is_asm
= (icode
< 0
4157 && (GET_CODE (PATTERN (insn
)) == ASM_INPUT
4158 || asm_noperands (PATTERN (insn
)) >= 0));
4159 bool no_parallel
= (is_asm
|| icode
== CODE_FOR_sploop
4161 && get_attr_type (insn
) == TYPE_ATOMIC
));
4163 /* We delay asm insns until all delay slots are exhausted. We can't
4164 accurately tell how many cycles an asm takes, and the main scheduling
4165 code always assumes at least 1 cycle, which may be wrong. */
4167 && (ss
.issued_this_cycle
> 0 || clock_var
< ss
.delays_finished_at
))
4168 || c6x_registers_update (insn
)
4169 || (ss
.issued_this_cycle
> 0 && icode
== CODE_FOR_sploop
))
4171 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
4176 else if (shadow_p (insn
))
4178 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
4183 /* Ensure that no other jump is scheduled in jump delay slots, since
4184 it would put the machine into the wrong state. Also, we must
4185 avoid scheduling insns that have a latency longer than the
4186 remaining jump delay slots, as the code at the jump destination
4187 won't be prepared for it.
4189 However, we can relax this condition somewhat. The rest of the
4190 scheduler will automatically avoid scheduling an insn on which
4191 the jump shadow depends so late that its side effect happens
4192 after the jump. This means that if we see an insn with a longer
4193 latency here, it can safely be scheduled if we can ensure that it
4194 has a predicate opposite of the previous jump: the side effect
4195 will happen in what we think of as the same basic block. In
4196 c6x_variable_issue, we will record the necessary predicate in
4197 new_conditions, and after scheduling is finished, we will modify
4200 Special care must be taken whenever there is more than one jump
4203 first_jump
= first_jump_index (clock_var
);
4204 if (first_jump
!= -1)
4206 int first_cycle
= get_jump_cycle (first_jump
);
4207 rtx first_cond
= get_jump_cond (first_jump
);
4208 int second_cycle
= 0;
4211 second_cycle
= get_jump_cycle (first_jump
- 1);
4213 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
4215 rtx_insn
*insn
= *insnp
;
4216 int icode
= recog_memoized (insn
);
4217 bool is_asm
= (icode
< 0
4218 && (GET_CODE (PATTERN (insn
)) == ASM_INPUT
4219 || asm_noperands (PATTERN (insn
)) >= 0));
4220 int this_cycles
, rsrv_cycles
;
4221 enum attr_type type
;
4223 gcc_assert (!is_asm
);
4226 this_cycles
= get_attr_cycles (insn
);
4227 rsrv_cycles
= get_attr_reserve_cycles (insn
);
4228 type
= get_attr_type (insn
);
4229 /* Treat branches specially; there is also a hazard if two jumps
4230 end at the same cycle. */
4231 if (type
== TYPE_BRANCH
|| type
== TYPE_CALL
)
4233 if (clock_var
+ this_cycles
<= first_cycle
)
4235 if ((first_jump
> 0 && clock_var
+ this_cycles
> second_cycle
)
4236 || clock_var
+ rsrv_cycles
> first_cycle
4237 || !predicate_insn (insn
, first_cond
, false))
4239 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
4250 /* Implement the TARGET_SCHED_REORDER hook. We save the current clock
4251 for later and clear the register access information for the new
4252 cycle. We also move asm statements out of the way if they would be
4253 scheduled in a delay slot. */
4256 c6x_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
,
4257 int sched_verbose ATTRIBUTE_UNUSED
,
4258 rtx_insn
**ready ATTRIBUTE_UNUSED
,
4259 int *pn_ready ATTRIBUTE_UNUSED
, int clock_var
)
4261 ss
.curr_sched_clock
= clock_var
;
4262 ss
.issued_this_cycle
= 0;
4263 memset (ss
.reg_n_accesses
, 0, sizeof ss
.reg_n_accesses
);
4264 memset (ss
.reg_n_xaccesses
, 0, sizeof ss
.reg_n_xaccesses
);
4269 return c6x_sched_reorder_1 (ready
, pn_ready
, clock_var
);
4272 /* Implement the TARGET_SCHED_REORDER2 hook. We use this to record the clock
4273 cycle for every insn. */
4276 c6x_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
4277 int sched_verbose ATTRIBUTE_UNUSED
,
4278 rtx_insn
**ready ATTRIBUTE_UNUSED
,
4279 int *pn_ready ATTRIBUTE_UNUSED
, int clock_var
)
4281 /* FIXME: the assembler rejects labels inside an execute packet.
4282 This can occur if prologue insns are scheduled in parallel with
4283 others, so we avoid this here. Also make sure that nothing is
4284 scheduled in parallel with a TYPE_ATOMIC insn or after a jump. */
4285 if (RTX_FRAME_RELATED_P (ss
.last_scheduled_insn
)
4286 || JUMP_P (ss
.last_scheduled_insn
)
4287 || (recog_memoized (ss
.last_scheduled_insn
) >= 0
4288 && get_attr_type (ss
.last_scheduled_insn
) == TYPE_ATOMIC
))
4290 int n_ready
= *pn_ready
;
4291 rtx_insn
**e_ready
= ready
+ n_ready
;
4294 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
4296 rtx_insn
*insn
= *insnp
;
4297 if (!shadow_p (insn
))
4299 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
4308 return c6x_sched_reorder_1 (ready
, pn_ready
, clock_var
);
4311 /* Subroutine of maybe_clobber_cond, called through note_stores. */
4314 clobber_cond_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data1
)
4316 rtx
*cond
= (rtx
*)data1
;
4317 if (*cond
!= NULL_RTX
&& reg_overlap_mentioned_p (x
, *cond
))
4321 /* Examine INSN, and if it destroys the conditions have recorded for
4322 any of the jumps in flight, clear that condition so that we don't
4323 predicate any more insns. CLOCK_VAR helps us limit the search to
4324 only those jumps which are still in flight. */
4327 maybe_clobber_cond (rtx insn
, int clock_var
)
4330 idx
= ss
.jump_cycle_index
;
4331 for (n
= 0; n
< 12; n
++, idx
++)
4338 cycle
= ss
.jump_cycles
[idx
];
4339 if (cycle
<= clock_var
)
4342 cond
= ss
.jump_cond
[idx
];
4343 if (cond
== NULL_RTX
)
4348 ss
.jump_cond
[idx
] = NULL_RTX
;
4352 note_stores (PATTERN (insn
), clobber_cond_1
, ss
.jump_cond
+ idx
);
4353 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
4354 if (REG_NOTE_KIND (link
) == REG_INC
)
4355 clobber_cond_1 (XEXP (link
, 0), NULL_RTX
, ss
.jump_cond
+ idx
);
4359 /* Implement the TARGET_SCHED_VARIABLE_ISSUE hook. We are about to
4360 issue INSN. Return the number of insns left on the ready queue
4361 that can be issued this cycle.
4362 We use this hook to record clock cycles and reservations for every insn. */
4365 c6x_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
4366 int sched_verbose ATTRIBUTE_UNUSED
,
4367 rtx_insn
*insn
, int can_issue_more ATTRIBUTE_UNUSED
)
4369 ss
.last_scheduled_insn
= insn
;
4370 if (INSN_UID (insn
) < sploop_max_uid_iter0
&& !JUMP_P (insn
))
4371 ss
.last_scheduled_iter0
= insn
;
4372 if (GET_CODE (PATTERN (insn
)) != USE
&& GET_CODE (PATTERN (insn
)) != CLOBBER
)
4373 ss
.issued_this_cycle
++;
4374 if (insn_info
.exists ())
4376 state_t st_after
= alloca (dfa_state_size
);
4377 int curr_clock
= ss
.curr_sched_clock
;
4378 int uid
= INSN_UID (insn
);
4379 int icode
= recog_memoized (insn
);
4381 int first
, first_cycle
;
4385 insn_set_clock (insn
, curr_clock
);
4386 INSN_INFO_ENTRY (uid
).ebb_start
4387 = curr_clock
== 0 && ss
.issued_this_cycle
== 1;
4389 first
= first_jump_index (ss
.curr_sched_clock
);
4393 first_cond
= NULL_RTX
;
4397 first_cycle
= get_jump_cycle (first
);
4398 first_cond
= get_jump_cond (first
);
4401 && first_cycle
> curr_clock
4402 && first_cond
!= NULL_RTX
4403 && (curr_clock
+ get_attr_cycles (insn
) > first_cycle
4404 || get_attr_type (insn
) == TYPE_BRANCH
4405 || get_attr_type (insn
) == TYPE_CALL
))
4406 INSN_INFO_ENTRY (uid
).new_cond
= first_cond
;
4408 memcpy (st_after
, curr_state
, dfa_state_size
);
4409 state_transition (st_after
, const0_rtx
);
4412 for (i
= 0; i
< 2 * UNIT_QID_SIDE_OFFSET
; i
++)
4413 if (cpu_unit_reservation_p (st_after
, c6x_unit_codes
[i
])
4414 && !cpu_unit_reservation_p (prev_cycle_state
, c6x_unit_codes
[i
]))
4416 INSN_INFO_ENTRY (uid
).unit_mask
= mask
;
4418 maybe_clobber_cond (insn
, curr_clock
);
4424 c6x_registers_update (insn
);
4425 memcpy (ss
.reg_n_accesses
, ss
.tmp_reg_n_accesses
,
4426 sizeof ss
.reg_n_accesses
);
4427 memcpy (ss
.reg_n_xaccesses
, ss
.tmp_reg_n_accesses
,
4428 sizeof ss
.reg_n_xaccesses
);
4430 cycles
= get_attr_cycles (insn
);
4431 if (ss
.delays_finished_at
< ss
.curr_sched_clock
+ cycles
)
4432 ss
.delays_finished_at
= ss
.curr_sched_clock
+ cycles
;
4433 if (get_attr_type (insn
) == TYPE_BRANCH
4434 || get_attr_type (insn
) == TYPE_CALL
)
4436 rtx opposite
= condjump_opposite_condition (insn
);
4437 record_jump (ss
.curr_sched_clock
+ cycles
, opposite
);
4440 /* Mark the cycles in which the destination registers are written.
4441 This is used for calculating stalls when using cross units. */
4442 extract_insn (insn
);
4443 /* Cross-path stalls don't apply to results of load insns. */
4444 if (get_attr_type (insn
) == TYPE_LOAD
4445 || get_attr_type (insn
) == TYPE_LOADN
4446 || get_attr_type (insn
) == TYPE_LOAD_SHADOW
)
4448 for (i
= 0; i
< recog_data
.n_operands
; i
++)
4450 rtx op
= recog_data
.operand
[i
];
4453 rtx addr
= XEXP (op
, 0);
4454 if (GET_RTX_CLASS (GET_CODE (addr
)) == RTX_AUTOINC
)
4455 c6x_mark_reg_written (XEXP (addr
, 0),
4456 insn_uid_get_clock (uid
) + 1);
4458 if (recog_data
.operand_type
[i
] != OP_IN
4461 c6x_mark_reg_written (op
,
4462 insn_uid_get_clock (uid
) + cycles
);
4467 return can_issue_more
;
4470 /* Implement the TARGET_SCHED_ADJUST_COST hook. We need special handling for
4471 anti- and output dependencies. */
4474 c6x_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
, int cost
,
4477 enum attr_type insn_type
= TYPE_UNKNOWN
, dep_insn_type
= TYPE_UNKNOWN
;
4478 int dep_insn_code_number
, insn_code_number
;
4479 int shadow_bonus
= 0;
4481 dep_insn_code_number
= recog_memoized (dep_insn
);
4482 insn_code_number
= recog_memoized (insn
);
4484 if (dep_insn_code_number
>= 0)
4485 dep_insn_type
= get_attr_type (dep_insn
);
4487 if (insn_code_number
>= 0)
4488 insn_type
= get_attr_type (insn
);
4490 kind
= (reg_note
) dep_type
;
4493 /* If we have a dependency on a load, and it's not for the result of
4494 the load, it must be for an autoincrement. Reduce the cost in that
4496 if (dep_insn_type
== TYPE_LOAD
)
4498 rtx set
= PATTERN (dep_insn
);
4499 if (GET_CODE (set
) == COND_EXEC
)
4500 set
= COND_EXEC_CODE (set
);
4501 if (GET_CODE (set
) == UNSPEC
)
4505 gcc_assert (GET_CODE (set
) == SET
);
4506 if (!reg_overlap_mentioned_p (SET_DEST (set
), PATTERN (insn
)))
4512 /* A jump shadow needs to have its latency decreased by one. Conceptually,
4513 it occurs in between two cycles, but we schedule it at the end of the
4515 if (shadow_type_p (insn_type
))
4518 /* Anti and output dependencies usually have zero cost, but we want
4519 to insert a stall after a jump, and after certain floating point
4520 insns that take more than one cycle to read their inputs. In the
4521 future, we should try to find a better algorithm for scheduling
4525 /* We can get anti-dependencies against shadow insns. Treat these
4526 like output dependencies, so that the insn is entirely finished
4527 before the branch takes place. */
4528 if (kind
== REG_DEP_ANTI
&& insn_type
== TYPE_SHADOW
)
4529 kind
= REG_DEP_OUTPUT
;
4530 switch (dep_insn_type
)
4536 if (get_attr_has_shadow (dep_insn
) == HAS_SHADOW_Y
)
4537 /* This is a real_jump/real_call insn. These don't have
4538 outputs, and ensuring the validity of scheduling things
4539 in the delay slot is the job of
4540 c6x_sched_reorder_1. */
4542 /* Unsplit calls can happen - e.g. for divide insns. */
4547 if (kind
== REG_DEP_OUTPUT
)
4548 return 5 - shadow_bonus
;
4552 if (kind
== REG_DEP_OUTPUT
)
4553 return 4 - shadow_bonus
;
4556 if (kind
== REG_DEP_OUTPUT
)
4557 return 2 - shadow_bonus
;
4560 if (kind
== REG_DEP_OUTPUT
)
4561 return 2 - shadow_bonus
;
4565 if (kind
== REG_DEP_OUTPUT
)
4566 return 7 - shadow_bonus
;
4569 if (kind
== REG_DEP_OUTPUT
)
4570 return 5 - shadow_bonus
;
4573 if (kind
== REG_DEP_OUTPUT
)
4574 return 9 - shadow_bonus
;
4578 if (kind
== REG_DEP_OUTPUT
)
4579 return 10 - shadow_bonus
;
4583 if (insn_type
== TYPE_SPKERNEL
)
4585 if (kind
== REG_DEP_OUTPUT
)
4586 return 1 - shadow_bonus
;
4592 return cost
- shadow_bonus
;
4595 /* Create a SEQUENCE rtx to replace the instructions in SLOT, of which there
4596 are N_FILLED. REAL_FIRST identifies the slot if the insn that appears
4597 first in the original stream. */
4600 gen_one_bundle (rtx_insn
**slot
, int n_filled
, int real_first
)
4607 seq
= gen_rtx_SEQUENCE (VOIDmode
, gen_rtvec_v (n_filled
, slot
));
4608 bundle
= make_insn_raw (seq
);
4609 BLOCK_FOR_INSN (bundle
) = BLOCK_FOR_INSN (slot
[0]);
4610 INSN_LOCATION (bundle
) = INSN_LOCATION (slot
[0]);
4611 SET_PREV_INSN (bundle
) = SET_PREV_INSN (slot
[real_first
]);
4615 for (i
= 0; i
< n_filled
; i
++)
4617 rtx_insn
*insn
= slot
[i
];
4619 SET_PREV_INSN (insn
) = t
? t
: PREV_INSN (bundle
);
4621 SET_NEXT_INSN (t
) = insn
;
4624 INSN_LOCATION (slot
[i
]) = INSN_LOCATION (bundle
);
4627 SET_NEXT_INSN (bundle
) = NEXT_INSN (PREV_INSN (bundle
));
4628 SET_NEXT_INSN (t
) = NEXT_INSN (bundle
);
4629 SET_NEXT_INSN (PREV_INSN (bundle
)) = bundle
;
4630 SET_PREV_INSN (NEXT_INSN (bundle
)) = bundle
;
4633 /* Move all parallel instructions into SEQUENCEs, so that no subsequent passes
4634 try to insert labels in the middle. */
4637 c6x_gen_bundles (void)
4641 FOR_EACH_BB_FN (bb
, cfun
)
4643 rtx_insn
*insn
, *next
;
4644 /* The machine is eight insns wide. We can have up to six shadow
4645 insns, plus an extra slot for merging the jump shadow. */
4650 for (insn
= BB_HEAD (bb
);; insn
= next
)
4653 rtx delete_this
= NULL_RTX
;
4655 if (NONDEBUG_INSN_P (insn
))
4657 /* Put calls at the start of the sequence. */
4663 memmove (&slot
[1], &slot
[0],
4664 n_filled
* sizeof (slot
[0]));
4666 if (!shadow_p (insn
))
4668 PUT_MODE (insn
, TImode
);
4670 PUT_MODE (slot
[1], VOIDmode
);
4677 slot
[n_filled
++] = insn
;
4681 next
= NEXT_INSN (insn
);
4682 while (next
&& insn
!= BB_END (bb
)
4683 && !(NONDEBUG_INSN_P (next
)
4684 && GET_CODE (PATTERN (next
)) != USE
4685 && GET_CODE (PATTERN (next
)) != CLOBBER
))
4688 next
= NEXT_INSN (insn
);
4691 at_end
= insn
== BB_END (bb
);
4692 if (delete_this
== NULL_RTX
4693 && (at_end
|| (GET_MODE (next
) == TImode
4694 && !(shadow_p (next
) && CALL_P (next
)))))
4697 gen_one_bundle (slot
, n_filled
, first_slot
);
4708 /* Emit a NOP instruction for CYCLES cycles after insn AFTER. Return it. */
4711 emit_nop_after (int cycles
, rtx_insn
*after
)
4715 /* mpydp has 9 delay slots, and we may schedule a stall for a cross-path
4716 operation. We don't need the extra NOP since in this case, the hardware
4717 will automatically insert the required stall. */
4721 gcc_assert (cycles
< 10);
4723 insn
= emit_insn_after (gen_nop_count (GEN_INT (cycles
)), after
);
4724 PUT_MODE (insn
, TImode
);
4729 /* Determine whether INSN is a call that needs to have a return label
4733 returning_call_p (rtx_insn
*insn
)
4736 return (!SIBLING_CALL_P (insn
)
4737 && get_attr_type (insn
) != TYPE_CALLP
4738 && get_attr_type (insn
) != TYPE_SHADOW
);
4739 if (recog_memoized (insn
) < 0)
4741 if (get_attr_type (insn
) == TYPE_CALL
)
4746 /* Determine whether INSN's pattern can be converted to use callp. */
4748 can_use_callp (rtx_insn
*insn
)
4750 int icode
= recog_memoized (insn
);
4751 if (!TARGET_INSNS_64PLUS
4753 || GET_CODE (PATTERN (insn
)) == COND_EXEC
)
4756 return ((icode
== CODE_FOR_real_call
4757 || icode
== CODE_FOR_call_internal
4758 || icode
== CODE_FOR_call_value_internal
)
4759 && get_attr_dest_regfile (insn
) == DEST_REGFILE_ANY
);
4762 /* Convert the pattern of INSN, which must be a CALL_INSN, into a callp. */
4764 convert_to_callp (rtx_insn
*insn
)
4767 extract_insn (insn
);
4768 if (GET_CODE (PATTERN (insn
)) == SET
)
4770 rtx dest
= recog_data
.operand
[0];
4771 lab
= recog_data
.operand
[1];
4772 PATTERN (insn
) = gen_callp_value (dest
, lab
);
4773 INSN_CODE (insn
) = CODE_FOR_callp_value
;
4777 lab
= recog_data
.operand
[0];
4778 PATTERN (insn
) = gen_callp (lab
);
4779 INSN_CODE (insn
) = CODE_FOR_callp
;
4783 /* Scan forwards from INSN until we find the next insn that has mode TImode
4784 (indicating it starts a new cycle), and occurs in cycle CLOCK.
4785 Return it if we find such an insn, NULL_RTX otherwise. */
4787 find_next_cycle_insn (rtx_insn
*insn
, int clock
)
4790 if (GET_MODE (t
) == TImode
)
4791 t
= next_real_insn (t
);
4792 while (t
&& GET_MODE (t
) != TImode
)
4793 t
= next_real_insn (t
);
4795 if (t
&& insn_get_clock (t
) == clock
)
4800 /* If COND_INSN has a COND_EXEC condition, wrap the same condition
4801 around PAT. Return PAT either unchanged or modified in this
4804 duplicate_cond (rtx pat
, rtx cond_insn
)
4806 rtx cond_pat
= PATTERN (cond_insn
);
4807 if (GET_CODE (cond_pat
) == COND_EXEC
)
4808 pat
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (COND_EXEC_TEST (cond_pat
)),
4813 /* Walk forward from INSN to find the last insn that issues in the same clock
4816 find_last_same_clock (rtx_insn
*insn
)
4818 rtx_insn
*retval
= insn
;
4819 rtx_insn
*t
= next_real_insn (insn
);
4821 while (t
&& GET_MODE (t
) != TImode
)
4823 if (!DEBUG_INSN_P (t
) && recog_memoized (t
) >= 0)
4825 t
= next_real_insn (t
);
4830 /* For every call insn in the function, emit code to load the return
4831 address. For each call we create a return label and store it in
4832 CALL_LABELS. If are not scheduling, we emit the labels here,
4833 otherwise the caller will do it later.
4834 This function is called after final insn scheduling, but before creating
4835 the SEQUENCEs that represent execute packets. */
4838 reorg_split_calls (rtx_code_label
**call_labels
)
4840 unsigned int reservation_mask
= 0;
4841 rtx_insn
*insn
= get_insns ();
4842 gcc_assert (NOTE_P (insn
));
4843 insn
= next_real_insn (insn
);
4847 rtx_insn
*next
= next_real_insn (insn
);
4849 if (DEBUG_INSN_P (insn
))
4852 if (GET_MODE (insn
) == TImode
)
4853 reservation_mask
= 0;
4854 uid
= INSN_UID (insn
);
4855 if (c6x_flag_schedule_insns2
&& recog_memoized (insn
) >= 0)
4856 reservation_mask
|= 1 << INSN_INFO_ENTRY (uid
).reservation
;
4858 if (returning_call_p (insn
))
4860 rtx_code_label
*label
= gen_label_rtx ();
4861 rtx labelref
= gen_rtx_LABEL_REF (Pmode
, label
);
4862 rtx reg
= gen_rtx_REG (SImode
, RETURN_ADDR_REGNO
);
4864 LABEL_NUSES (label
) = 2;
4865 if (!c6x_flag_schedule_insns2
)
4867 if (can_use_callp (insn
))
4868 convert_to_callp (insn
);
4873 emit_label_after (label
, insn
);
4875 /* Bundle the call and its delay slots into a single
4876 SEQUENCE. While these do not issue in parallel
4877 we need to group them into a single EH region. */
4879 PUT_MODE (insn
, TImode
);
4880 if (TARGET_INSNS_64
)
4882 t
= gen_addkpc (reg
, labelref
, GEN_INT (4));
4883 slot
[1] = emit_insn_after (duplicate_cond (t
, insn
),
4885 PUT_MODE (slot
[1], TImode
);
4886 gen_one_bundle (slot
, 2, 0);
4890 slot
[3] = emit_insn_after (gen_nop_count (GEN_INT (3)),
4892 PUT_MODE (slot
[3], TImode
);
4893 t
= gen_movsi_lo_sum (reg
, reg
, labelref
);
4894 slot
[2] = emit_insn_after (duplicate_cond (t
, insn
),
4896 PUT_MODE (slot
[2], TImode
);
4897 t
= gen_movsi_high (reg
, labelref
);
4898 slot
[1] = emit_insn_after (duplicate_cond (t
, insn
),
4900 PUT_MODE (slot
[1], TImode
);
4901 gen_one_bundle (slot
, 4, 0);
4907 /* If we scheduled, we reserved the .S2 unit for one or two
4908 cycles after the call. Emit the insns in these slots,
4909 unless it's possible to create a CALLP insn.
4910 Note that this works because the dependencies ensure that
4911 no insn setting/using B3 is scheduled in the delay slots of
4913 int this_clock
= insn_get_clock (insn
);
4916 call_labels
[INSN_UID (insn
)] = label
;
4918 rtx_insn
*last_same_clock
= find_last_same_clock (insn
);
4920 if (can_use_callp (insn
))
4922 /* Find the first insn of the next execute packet. If it
4923 is the shadow insn corresponding to this call, we may
4924 use a CALLP insn. */
4926 next_nonnote_nondebug_insn (last_same_clock
);
4929 && insn_get_clock (shadow
) == this_clock
+ 5)
4931 convert_to_callp (shadow
);
4932 insn_set_clock (shadow
, this_clock
);
4933 INSN_INFO_ENTRY (INSN_UID (shadow
)).reservation
4935 INSN_INFO_ENTRY (INSN_UID (shadow
)).unit_mask
4936 = INSN_INFO_ENTRY (INSN_UID (last_same_clock
)).unit_mask
;
4937 if (GET_MODE (insn
) == TImode
)
4939 rtx_insn
*new_cycle_first
= NEXT_INSN (insn
);
4940 while (!NONDEBUG_INSN_P (new_cycle_first
)
4941 || GET_CODE (PATTERN (new_cycle_first
)) == USE
4942 || GET_CODE (PATTERN (new_cycle_first
)) == CLOBBER
)
4943 new_cycle_first
= NEXT_INSN (new_cycle_first
);
4944 PUT_MODE (new_cycle_first
, TImode
);
4945 if (new_cycle_first
!= shadow
)
4946 PUT_MODE (shadow
, VOIDmode
);
4947 INSN_INFO_ENTRY (INSN_UID (new_cycle_first
)).ebb_start
4948 = INSN_INFO_ENTRY (INSN_UID (insn
)).ebb_start
;
4951 PUT_MODE (shadow
, VOIDmode
);
4956 after1
= find_next_cycle_insn (last_same_clock
, this_clock
+ 1);
4957 if (after1
== NULL_RTX
)
4958 after1
= last_same_clock
;
4960 after1
= find_last_same_clock (after1
);
4961 if (TARGET_INSNS_64
)
4963 rtx x1
= gen_addkpc (reg
, labelref
, const0_rtx
);
4964 x1
= emit_insn_after (duplicate_cond (x1
, insn
), after1
);
4965 insn_set_clock (x1
, this_clock
+ 1);
4966 INSN_INFO_ENTRY (INSN_UID (x1
)).reservation
= RESERVATION_S2
;
4967 if (after1
== last_same_clock
)
4968 PUT_MODE (x1
, TImode
);
4970 INSN_INFO_ENTRY (INSN_UID (x1
)).unit_mask
4971 = INSN_INFO_ENTRY (INSN_UID (after1
)).unit_mask
;
4976 rtx_insn
*after2
= find_next_cycle_insn (after1
,
4978 if (after2
== NULL_RTX
)
4980 x2
= gen_movsi_lo_sum (reg
, reg
, labelref
);
4981 x2
= emit_insn_after (duplicate_cond (x2
, insn
), after2
);
4982 x1
= gen_movsi_high (reg
, labelref
);
4983 x1
= emit_insn_after (duplicate_cond (x1
, insn
), after1
);
4984 insn_set_clock (x1
, this_clock
+ 1);
4985 insn_set_clock (x2
, this_clock
+ 2);
4986 INSN_INFO_ENTRY (INSN_UID (x1
)).reservation
= RESERVATION_S2
;
4987 INSN_INFO_ENTRY (INSN_UID (x2
)).reservation
= RESERVATION_S2
;
4988 if (after1
== last_same_clock
)
4989 PUT_MODE (x1
, TImode
);
4991 INSN_INFO_ENTRY (INSN_UID (x1
)).unit_mask
4992 = INSN_INFO_ENTRY (INSN_UID (after1
)).unit_mask
;
4993 if (after1
== after2
)
4994 PUT_MODE (x2
, TImode
);
4996 INSN_INFO_ENTRY (INSN_UID (x2
)).unit_mask
4997 = INSN_INFO_ENTRY (INSN_UID (after2
)).unit_mask
;
5006 /* Called as part of c6x_reorg. This function emits multi-cycle NOP
5007 insns as required for correctness. CALL_LABELS is the array that
5008 holds the return labels for call insns; we emit these here if
5009 scheduling was run earlier. */
5012 reorg_emit_nops (rtx_code_label
**call_labels
)
5017 int prev_clock
, earliest_bb_end
;
5018 int prev_implicit_nops
;
5019 rtx_insn
*insn
= get_insns ();
5021 /* We look at one insn (or bundle inside a sequence) in each iteration, storing
5022 its issue time in PREV_CLOCK for the next iteration. If there is a gap in
5023 clocks, we must insert a NOP.
5024 EARLIEST_BB_END tracks in which cycle all insns that have been issued in the
5025 current basic block will finish. We must not allow the next basic block to
5026 begin before this cycle.
5027 PREV_IMPLICIT_NOPS tells us whether we've seen an insn that implicitly contains
5028 a multi-cycle nop. The code is scheduled such that subsequent insns will
5029 show the cycle gap, but we needn't insert a real NOP instruction. */
5030 insn
= next_real_insn (insn
);
5031 last_call
= prev
= NULL
;
5033 earliest_bb_end
= 0;
5034 prev_implicit_nops
= 0;
5038 int this_clock
= -1;
5042 next
= next_real_insn (insn
);
5044 if (DEBUG_INSN_P (insn
)
5045 || GET_CODE (PATTERN (insn
)) == USE
5046 || GET_CODE (PATTERN (insn
)) == CLOBBER
5047 || shadow_or_blockage_p (insn
)
5048 || JUMP_TABLE_DATA_P (insn
))
5051 if (!c6x_flag_schedule_insns2
)
5052 /* No scheduling; ensure that no parallel issue happens. */
5053 PUT_MODE (insn
, TImode
);
5058 this_clock
= insn_get_clock (insn
);
5059 if (this_clock
!= prev_clock
)
5061 PUT_MODE (insn
, TImode
);
5065 cycles
= this_clock
- prev_clock
;
5067 cycles
-= prev_implicit_nops
;
5070 rtx nop
= emit_nop_after (cycles
- 1, prev
);
5071 insn_set_clock (nop
, prev_clock
+ prev_implicit_nops
+ 1);
5074 prev_clock
= this_clock
;
5077 && insn_get_clock (last_call
) + 6 <= this_clock
)
5079 emit_label_before (call_labels
[INSN_UID (last_call
)], insn
);
5080 last_call
= NULL_RTX
;
5082 prev_implicit_nops
= 0;
5086 /* Examine how many cycles the current insn takes, and adjust
5087 LAST_CALL, EARLIEST_BB_END and PREV_IMPLICIT_NOPS. */
5088 if (recog_memoized (insn
) >= 0
5089 /* If not scheduling, we've emitted NOPs after calls already. */
5090 && (c6x_flag_schedule_insns2
|| !returning_call_p (insn
)))
5092 max_cycles
= get_attr_cycles (insn
);
5093 if (get_attr_type (insn
) == TYPE_CALLP
)
5094 prev_implicit_nops
= 5;
5098 if (returning_call_p (insn
))
5101 if (c6x_flag_schedule_insns2
)
5103 gcc_assert (this_clock
>= 0);
5104 if (earliest_bb_end
< this_clock
+ max_cycles
)
5105 earliest_bb_end
= this_clock
+ max_cycles
;
5107 else if (max_cycles
> 1)
5108 emit_nop_after (max_cycles
- 1, insn
);
5114 if (c6x_flag_schedule_insns2
5115 && (next
== NULL_RTX
5116 || (GET_MODE (next
) == TImode
5117 && INSN_INFO_ENTRY (INSN_UID (next
)).ebb_start
))
5118 && earliest_bb_end
> 0)
5120 int cycles
= earliest_bb_end
- prev_clock
;
5123 prev
= emit_nop_after (cycles
- 1, prev
);
5124 insn_set_clock (prev
, prev_clock
+ prev_implicit_nops
+ 1);
5126 earliest_bb_end
= 0;
5131 emit_label_after (call_labels
[INSN_UID (last_call
)], prev
);
5132 last_call
= NULL_RTX
;
5138 /* If possible, split INSN, which we know is either a jump or a call, into a real
5139 insn and its shadow. */
5141 split_delayed_branch (rtx_insn
*insn
)
5143 int code
= recog_memoized (insn
);
5146 rtx pat
= PATTERN (insn
);
5148 if (GET_CODE (pat
) == COND_EXEC
)
5149 pat
= COND_EXEC_CODE (pat
);
5153 rtx src
= pat
, dest
= NULL_RTX
;
5155 if (GET_CODE (pat
) == SET
)
5157 dest
= SET_DEST (pat
);
5158 src
= SET_SRC (pat
);
5160 callee
= XEXP (XEXP (src
, 0), 0);
5161 if (SIBLING_CALL_P (insn
))
5164 newpat
= gen_indirect_sibcall_shadow ();
5166 newpat
= gen_sibcall_shadow (callee
);
5167 pat
= gen_real_jump (callee
);
5169 else if (dest
!= NULL_RTX
)
5172 newpat
= gen_indirect_call_value_shadow (dest
);
5174 newpat
= gen_call_value_shadow (dest
, callee
);
5175 pat
= gen_real_call (callee
);
5180 newpat
= gen_indirect_call_shadow ();
5182 newpat
= gen_call_shadow (callee
);
5183 pat
= gen_real_call (callee
);
5185 pat
= duplicate_cond (pat
, insn
);
5186 newpat
= duplicate_cond (newpat
, insn
);
5191 if (GET_CODE (pat
) == PARALLEL
5192 && GET_CODE (XVECEXP (pat
, 0, 0)) == RETURN
)
5194 newpat
= gen_return_shadow ();
5195 pat
= gen_real_ret (XEXP (XVECEXP (pat
, 0, 1), 0));
5196 newpat
= duplicate_cond (newpat
, insn
);
5201 case CODE_FOR_br_true
:
5202 case CODE_FOR_br_false
:
5203 src
= SET_SRC (pat
);
5204 op
= XEXP (src
, code
== CODE_FOR_br_true
? 1 : 2);
5205 newpat
= gen_condjump_shadow (op
);
5206 pat
= gen_real_jump (op
);
5207 if (code
== CODE_FOR_br_true
)
5208 pat
= gen_rtx_COND_EXEC (VOIDmode
, XEXP (src
, 0), pat
);
5210 pat
= gen_rtx_COND_EXEC (VOIDmode
,
5211 reversed_comparison (XEXP (src
, 0),
5218 newpat
= gen_jump_shadow (op
);
5221 case CODE_FOR_indirect_jump
:
5222 newpat
= gen_indirect_jump_shadow ();
5225 case CODE_FOR_return_internal
:
5226 newpat
= gen_return_shadow ();
5227 pat
= gen_real_ret (XEXP (XVECEXP (pat
, 0, 1), 0));
5234 i1
= emit_insn_before (pat
, insn
);
5235 PATTERN (insn
) = newpat
;
5236 INSN_CODE (insn
) = -1;
5237 record_delay_slot_pair (i1
, insn
, 5, 0);
5240 /* If INSN is a multi-cycle insn that should be handled properly in
5241 modulo-scheduling, split it into a real insn and a shadow.
5242 Return true if we made a change.
5244 It is valid for us to fail to split an insn; the caller has to deal
5245 with the possibility. Currently we handle loads and most mpy2 and
5248 split_delayed_nonbranch (rtx_insn
*insn
)
5250 int code
= recog_memoized (insn
);
5251 enum attr_type type
;
5253 rtx newpat
, src
, dest
;
5254 rtx pat
= PATTERN (insn
);
5258 if (GET_CODE (pat
) == COND_EXEC
)
5259 pat
= COND_EXEC_CODE (pat
);
5261 if (code
< 0 || GET_CODE (pat
) != SET
)
5263 src
= SET_SRC (pat
);
5264 dest
= SET_DEST (pat
);
5268 type
= get_attr_type (insn
);
5270 && (type
== TYPE_LOAD
5271 || type
== TYPE_LOADN
))
5274 && (GET_CODE (src
) != ZERO_EXTEND
5275 || !MEM_P (XEXP (src
, 0))))
5278 if (GET_MODE_SIZE (GET_MODE (dest
)) > 4
5279 && (GET_MODE_SIZE (GET_MODE (dest
)) != 8 || !TARGET_LDDW
))
5282 rtv
= gen_rtvec (2, GEN_INT (REGNO (SET_DEST (pat
))),
5284 newpat
= gen_load_shadow (SET_DEST (pat
));
5285 pat
= gen_rtx_UNSPEC (VOIDmode
, rtv
, UNSPEC_REAL_LOAD
);
5289 && (type
== TYPE_MPY2
5290 || type
== TYPE_MPY4
))
5292 /* We don't handle floating point multiplies yet. */
5293 if (GET_MODE (dest
) == SFmode
)
5296 rtv
= gen_rtvec (2, GEN_INT (REGNO (SET_DEST (pat
))),
5298 newpat
= gen_mult_shadow (SET_DEST (pat
));
5299 pat
= gen_rtx_UNSPEC (VOIDmode
, rtv
, UNSPEC_REAL_MULT
);
5300 delay
= type
== TYPE_MPY2
? 1 : 3;
5305 pat
= duplicate_cond (pat
, insn
);
5306 newpat
= duplicate_cond (newpat
, insn
);
5307 i1
= emit_insn_before (pat
, insn
);
5308 PATTERN (insn
) = newpat
;
5309 INSN_CODE (insn
) = -1;
5310 recog_memoized (insn
);
5311 recog_memoized (i1
);
5312 record_delay_slot_pair (i1
, insn
, delay
, 0);
5316 /* Examine if INSN is the result of splitting a load into a real load and a
5317 shadow, and if so, undo the transformation. */
5319 undo_split_delayed_nonbranch (rtx_insn
*insn
)
5321 int icode
= recog_memoized (insn
);
5322 enum attr_type type
;
5323 rtx prev_pat
, insn_pat
;
5328 type
= get_attr_type (insn
);
5329 if (type
!= TYPE_LOAD_SHADOW
&& type
!= TYPE_MULT_SHADOW
)
5331 prev
= PREV_INSN (insn
);
5332 prev_pat
= PATTERN (prev
);
5333 insn_pat
= PATTERN (insn
);
5334 if (GET_CODE (prev_pat
) == COND_EXEC
)
5336 prev_pat
= COND_EXEC_CODE (prev_pat
);
5337 insn_pat
= COND_EXEC_CODE (insn_pat
);
5340 gcc_assert (GET_CODE (prev_pat
) == UNSPEC
5341 && ((XINT (prev_pat
, 1) == UNSPEC_REAL_LOAD
5342 && type
== TYPE_LOAD_SHADOW
)
5343 || (XINT (prev_pat
, 1) == UNSPEC_REAL_MULT
5344 && type
== TYPE_MULT_SHADOW
)));
5345 insn_pat
= gen_rtx_SET (SET_DEST (insn_pat
),
5346 XVECEXP (prev_pat
, 0, 1));
5347 insn_pat
= duplicate_cond (insn_pat
, prev
);
5348 PATTERN (insn
) = insn_pat
;
5349 INSN_CODE (insn
) = -1;
5353 /* Split every insn (i.e. jumps and calls) which can have delay slots into
5354 two parts: the first one is scheduled normally and emits the instruction,
5355 while the second one is a shadow insn which shows the side effect taking
5356 place. The second one is placed in the right cycle by the scheduler, but
5357 not emitted as an assembly instruction. */
5360 split_delayed_insns (void)
5363 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5365 if (JUMP_P (insn
) || CALL_P (insn
))
5366 split_delayed_branch (insn
);
5370 /* For every insn that has an entry in the new_conditions vector, give it
5371 the appropriate predicate. */
5373 conditionalize_after_sched (void)
5377 FOR_EACH_BB_FN (bb
, cfun
)
5378 FOR_BB_INSNS (bb
, insn
)
5380 unsigned uid
= INSN_UID (insn
);
5382 if (!NONDEBUG_INSN_P (insn
) || uid
>= INSN_INFO_LENGTH
)
5384 cond
= INSN_INFO_ENTRY (uid
).new_cond
;
5385 if (cond
== NULL_RTX
)
5388 fprintf (dump_file
, "Conditionalizing insn %d\n", uid
);
5389 predicate_insn (insn
, cond
, true);
5393 /* A callback for the hw-doloop pass. This function examines INSN; if
5394 it is a loop_end pattern we recognize, return the reg rtx for the
5395 loop counter. Otherwise, return NULL_RTX. */
5398 hwloop_pattern_reg (rtx_insn
*insn
)
5402 if (!JUMP_P (insn
) || recog_memoized (insn
) != CODE_FOR_loop_end
)
5405 pat
= PATTERN (insn
);
5406 reg
= SET_DEST (XVECEXP (pat
, 0, 1));
5412 /* Return the number of cycles taken by BB, as computed by scheduling,
5413 including the latencies of all insns with delay slots. IGNORE is
5414 an insn we should ignore in the calculation, usually the final
5417 bb_earliest_end_cycle (basic_block bb
, rtx ignore
)
5422 FOR_BB_INSNS (bb
, insn
)
5424 int cycles
, this_clock
;
5426 if (LABEL_P (insn
) || NOTE_P (insn
) || DEBUG_INSN_P (insn
)
5427 || GET_CODE (PATTERN (insn
)) == USE
5428 || GET_CODE (PATTERN (insn
)) == CLOBBER
5432 this_clock
= insn_get_clock (insn
);
5433 cycles
= get_attr_cycles (insn
);
5435 if (earliest
< this_clock
+ cycles
)
5436 earliest
= this_clock
+ cycles
;
5441 /* Examine the insns in BB and remove all which have a uid greater or
5442 equal to MAX_UID. */
5444 filter_insns_above (basic_block bb
, int max_uid
)
5446 rtx_insn
*insn
, *next
;
5447 bool prev_ti
= false;
5448 int prev_cycle
= -1;
5450 FOR_BB_INSNS_SAFE (bb
, insn
, next
)
5453 if (!NONDEBUG_INSN_P (insn
))
5455 if (insn
== BB_END (bb
))
5457 this_cycle
= insn_get_clock (insn
);
5458 if (prev_ti
&& this_cycle
== prev_cycle
)
5460 gcc_assert (GET_MODE (insn
) != TImode
);
5461 PUT_MODE (insn
, TImode
);
5464 if (INSN_UID (insn
) >= max_uid
)
5466 if (GET_MODE (insn
) == TImode
)
5469 prev_cycle
= this_cycle
;
5476 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
5479 c6x_asm_emit_except_personality (rtx personality
)
5481 fputs ("\t.personality\t", asm_out_file
);
5482 output_addr_const (asm_out_file
, personality
);
5483 fputc ('\n', asm_out_file
);
5486 /* Use a special assembly directive rather than a regular setion for
5487 unwind table data. */
5490 c6x_asm_init_sections (void)
5492 exception_section
= get_unnamed_section (0, output_section_asm_op
,
5496 /* A callback for the hw-doloop pass. Called to optimize LOOP in a
5497 machine-specific fashion; returns true if successful and false if
5498 the hwloop_fail function should be called. */
5501 hwloop_optimize (hwloop_info loop
)
5503 basic_block entry_bb
, bb
;
5504 rtx_insn
*seq
, *insn
, *prev
, *entry_after
, *end_packet
;
5505 rtx_insn
*head_insn
, *tail_insn
, *new_insns
, *last_insn
;
5507 int n_execute_packets
;
5510 int max_uid_before
, delayed_splits
;
5511 int i
, sp_ii
, min_ii
, max_ii
, max_parallel
, n_insns
, n_real_insns
, stages
;
5512 rtx_insn
**orig_vec
;
5514 rtx_insn
***insn_copies
;
5516 if (!c6x_flag_modulo_sched
|| !c6x_flag_schedule_insns2
5517 || !TARGET_INSNS_64PLUS
)
5520 if (loop
->iter_reg_used
|| loop
->depth
> 1)
5522 if (loop
->has_call
|| loop
->has_asm
)
5525 if (loop
->head
!= loop
->tail
)
5528 gcc_assert (loop
->incoming_dest
== loop
->head
);
5531 FOR_EACH_VEC_SAFE_ELT (loop
->incoming
, i
, entry_edge
)
5532 if (entry_edge
->flags
& EDGE_FALLTHRU
)
5534 if (entry_edge
== NULL
)
5537 reshuffle_units (loop
->head
);
5540 schedule_ebbs_init ();
5541 schedule_ebb (BB_HEAD (loop
->tail
), loop
->loop_end
, true);
5542 schedule_ebbs_finish ();
5546 loop_earliest
= bb_earliest_end_cycle (bb
, loop
->loop_end
) + 1;
5548 max_uid_before
= get_max_uid ();
5550 /* Split all multi-cycle operations, such as loads. For normal
5551 scheduling, we only do this for branches, as the generated code
5552 would otherwise not be interrupt-safe. When using sploop, it is
5553 safe and beneficial to split them. If any multi-cycle operations
5554 remain after splitting (because we don't handle them yet), we
5555 cannot pipeline the loop. */
5557 FOR_BB_INSNS (bb
, insn
)
5559 if (NONDEBUG_INSN_P (insn
))
5561 recog_memoized (insn
);
5562 if (split_delayed_nonbranch (insn
))
5564 else if (INSN_CODE (insn
) >= 0
5565 && get_attr_cycles (insn
) > 1)
5570 /* Count the number of insns as well as the number real insns, and save
5571 the original sequence of insns in case we must restore it later. */
5572 n_insns
= n_real_insns
= 0;
5573 FOR_BB_INSNS (bb
, insn
)
5576 if (NONDEBUG_INSN_P (insn
) && insn
!= loop
->loop_end
)
5579 orig_vec
= XNEWVEC (rtx_insn
*, n_insns
);
5581 FOR_BB_INSNS (bb
, insn
)
5582 orig_vec
[n_insns
++] = insn
;
5584 /* Count the unit reservations, and compute a minimum II from that
5586 count_unit_reqs (unit_reqs
, loop
->start_label
,
5587 PREV_INSN (loop
->loop_end
));
5588 merge_unit_reqs (unit_reqs
);
5590 min_ii
= res_mii (unit_reqs
);
5591 max_ii
= loop_earliest
< 15 ? loop_earliest
: 14;
5593 /* Make copies of the loop body, up to a maximum number of stages we want
5595 max_parallel
= loop_earliest
/ min_ii
+ 1;
5597 copies
= XCNEWVEC (rtx_insn
*, (max_parallel
+ 1) * n_real_insns
);
5598 insn_copies
= XNEWVEC (rtx_insn
**, max_parallel
+ 1);
5599 for (i
= 0; i
< max_parallel
+ 1; i
++)
5600 insn_copies
[i
] = copies
+ i
* n_real_insns
;
5602 head_insn
= next_nonnote_nondebug_insn (loop
->start_label
);
5603 tail_insn
= prev_real_insn (BB_END (bb
));
5606 FOR_BB_INSNS (bb
, insn
)
5607 if (NONDEBUG_INSN_P (insn
) && insn
!= loop
->loop_end
)
5608 insn_copies
[0][i
++] = insn
;
5610 sploop_max_uid_iter0
= get_max_uid ();
5612 /* Generate the copies of the loop body, and save them in the
5613 INSN_COPIES array. */
5615 for (i
= 0; i
< max_parallel
; i
++)
5618 rtx_insn
*this_iter
;
5620 this_iter
= duplicate_insn_chain (head_insn
, tail_insn
);
5624 rtx_insn
*prev_stage_insn
= insn_copies
[i
][j
];
5625 gcc_assert (INSN_CODE (this_iter
) == INSN_CODE (prev_stage_insn
));
5627 if (INSN_CODE (this_iter
) >= 0
5628 && (get_attr_type (this_iter
) == TYPE_LOAD_SHADOW
5629 || get_attr_type (this_iter
) == TYPE_MULT_SHADOW
))
5631 rtx_insn
*prev
= PREV_INSN (this_iter
);
5632 record_delay_slot_pair (prev
, this_iter
,
5633 get_attr_cycles (prev
) - 1, 0);
5636 record_delay_slot_pair (prev_stage_insn
, this_iter
, i
, 1);
5638 insn_copies
[i
+ 1][j
] = this_iter
;
5640 this_iter
= next_nonnote_nondebug_insn (this_iter
);
5643 new_insns
= get_insns ();
5644 last_insn
= insn_copies
[max_parallel
][n_real_insns
- 1];
5646 emit_insn_before (new_insns
, BB_END (bb
));
5648 /* Try to schedule the loop using varying initiation intervals,
5649 starting with the smallest possible and incrementing it
5651 for (sp_ii
= min_ii
; sp_ii
<= max_ii
; sp_ii
++)
5655 fprintf (dump_file
, "Trying to schedule for II %d\n", sp_ii
);
5657 df_clear_flags (DF_LR_RUN_DCE
);
5659 schedule_ebbs_init ();
5660 set_modulo_params (sp_ii
, max_parallel
, n_real_insns
,
5661 sploop_max_uid_iter0
);
5662 tmp_bb
= schedule_ebb (BB_HEAD (bb
), last_insn
, true);
5663 schedule_ebbs_finish ();
5668 fprintf (dump_file
, "Found schedule with II %d\n", sp_ii
);
5673 discard_delay_pairs_above (max_uid_before
);
5678 stages
= insn_get_clock (ss
.last_scheduled_iter0
) / sp_ii
+ 1;
5680 if (stages
== 1 && sp_ii
> 5)
5683 /* At this point, we know we've been successful, unless we find later that
5684 there are too many execute packets for the loop buffer to hold. */
5686 /* Assign reservations to the instructions in the loop. We must find
5687 the stage that contains the full loop kernel, and transfer the
5688 reservations of the instructions contained in it to the corresponding
5689 instructions from iteration 0, which are the only ones we'll keep. */
5690 assign_reservations (BB_HEAD (bb
), ss
.last_scheduled_insn
);
5691 SET_PREV_INSN (BB_END (bb
)) = ss
.last_scheduled_iter0
;
5692 SET_NEXT_INSN (ss
.last_scheduled_iter0
) = BB_END (bb
);
5693 filter_insns_above (bb
, sploop_max_uid_iter0
);
5695 for (i
= 0; i
< n_real_insns
; i
++)
5697 rtx insn
= insn_copies
[0][i
];
5698 int uid
= INSN_UID (insn
);
5699 int stage
= insn_uid_get_clock (uid
) / sp_ii
;
5701 if (stage
+ 1 < stages
)
5704 stage
= stages
- stage
- 1;
5705 copy_uid
= INSN_UID (insn_copies
[stage
][i
]);
5706 INSN_INFO_ENTRY (uid
).reservation
5707 = INSN_INFO_ENTRY (copy_uid
).reservation
;
5713 /* Compute the number of execute packets the pipelined form of the loop will
5716 n_execute_packets
= 0;
5717 for (insn
= loop
->start_label
;
5718 insn
!= loop
->loop_end
;
5719 insn
= NEXT_INSN (insn
))
5721 if (NONDEBUG_INSN_P (insn
) && GET_MODE (insn
) == TImode
5722 && !shadow_p (insn
))
5724 n_execute_packets
++;
5725 if (prev
&& insn_get_clock (prev
) + 1 != insn_get_clock (insn
))
5726 /* We need an extra NOP instruction. */
5727 n_execute_packets
++;
5733 end_packet
= ss
.last_scheduled_iter0
;
5734 while (!NONDEBUG_INSN_P (end_packet
) || GET_MODE (end_packet
) != TImode
)
5735 end_packet
= PREV_INSN (end_packet
);
5737 /* The earliest cycle in which we can emit the SPKERNEL instruction. */
5738 loop_earliest
= (stages
- 1) * sp_ii
;
5739 if (loop_earliest
> insn_get_clock (end_packet
))
5741 n_execute_packets
++;
5742 end_packet
= loop
->loop_end
;
5745 loop_earliest
= insn_get_clock (end_packet
);
5747 if (n_execute_packets
> 14)
5750 /* Generate the spkernel instruction, and place it at the appropriate
5752 PUT_MODE (end_packet
, VOIDmode
);
5754 insn
= emit_jump_insn_before (
5755 gen_spkernel (GEN_INT (stages
- 1),
5756 const0_rtx
, JUMP_LABEL (loop
->loop_end
)),
5758 JUMP_LABEL (insn
) = JUMP_LABEL (loop
->loop_end
);
5759 insn_set_clock (insn
, loop_earliest
);
5760 PUT_MODE (insn
, TImode
);
5761 INSN_INFO_ENTRY (INSN_UID (insn
)).ebb_start
= false;
5762 delete_insn (loop
->loop_end
);
5764 /* Place the mvc and sploop instructions before the loop. */
5765 entry_bb
= entry_edge
->src
;
5769 insn
= emit_insn (gen_mvilc (loop
->iter_reg
));
5770 if (loop
->iter_reg_used_outside
)
5771 insn
= emit_move_insn (loop
->iter_reg
, const0_rtx
);
5772 insn
= emit_insn (gen_sploop (GEN_INT (sp_ii
)));
5775 if (!single_succ_p (entry_bb
) || vec_safe_length (loop
->incoming
) > 1)
5781 emit_insn_before (seq
, BB_HEAD (loop
->head
));
5782 seq
= emit_label_before (gen_label_rtx (), seq
);
5784 new_bb
= create_basic_block (seq
, insn
, entry_bb
);
5785 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
5787 if (!(e
->flags
& EDGE_FALLTHRU
))
5788 redirect_edge_and_branch_force (e
, new_bb
);
5790 redirect_edge_succ (e
, new_bb
);
5792 make_edge (new_bb
, loop
->head
, 0);
5796 entry_after
= BB_END (entry_bb
);
5797 while (DEBUG_INSN_P (entry_after
)
5798 || (NOTE_P (entry_after
)
5799 && NOTE_KIND (entry_after
) != NOTE_INSN_BASIC_BLOCK
))
5800 entry_after
= PREV_INSN (entry_after
);
5801 emit_insn_after (seq
, entry_after
);
5806 /* Make sure we don't try to schedule this loop again. */
5807 for (ix
= 0; loop
->blocks
.iterate (ix
, &bb
); ix
++)
5808 bb
->flags
|= BB_DISABLE_SCHEDULE
;
5814 fprintf (dump_file
, "Unable to pipeline loop.\n");
5816 for (i
= 1; i
< n_insns
; i
++)
5818 SET_NEXT_INSN (orig_vec
[i
- 1]) = orig_vec
[i
];
5819 SET_PREV_INSN (orig_vec
[i
]) = orig_vec
[i
- 1];
5821 SET_PREV_INSN (orig_vec
[0]) = PREV_INSN (BB_HEAD (bb
));
5822 SET_NEXT_INSN (PREV_INSN (BB_HEAD (bb
))) = orig_vec
[0];
5823 SET_NEXT_INSN (orig_vec
[n_insns
- 1]) = NEXT_INSN (BB_END (bb
));
5824 SET_PREV_INSN (NEXT_INSN (BB_END (bb
))) = orig_vec
[n_insns
- 1];
5825 BB_HEAD (bb
) = orig_vec
[0];
5826 BB_END (bb
) = orig_vec
[n_insns
- 1];
5828 free_delay_pairs ();
5829 FOR_BB_INSNS (bb
, insn
)
5830 if (NONDEBUG_INSN_P (insn
))
5831 undo_split_delayed_nonbranch (insn
);
5835 /* A callback for the hw-doloop pass. Called when a loop we have discovered
5836 turns out not to be optimizable; we have to split the doloop_end pattern
5837 into a subtract and a test. */
5839 hwloop_fail (hwloop_info loop
)
5841 rtx insn
, test
, testreg
;
5844 fprintf (dump_file
, "splitting doloop insn %d\n",
5845 INSN_UID (loop
->loop_end
));
5846 insn
= gen_addsi3 (loop
->iter_reg
, loop
->iter_reg
, constm1_rtx
);
5847 /* See if we can emit the add at the head of the loop rather than at the
5849 if (loop
->head
== NULL
5850 || loop
->iter_reg_used_outside
5851 || loop
->iter_reg_used
5852 || TEST_HARD_REG_BIT (loop
->regs_set_in_loop
, REGNO (loop
->iter_reg
))
5853 || loop
->incoming_dest
!= loop
->head
5854 || EDGE_COUNT (loop
->head
->preds
) != 2)
5855 emit_insn_before (insn
, loop
->loop_end
);
5858 rtx_insn
*t
= loop
->start_label
;
5859 while (!NOTE_P (t
) || NOTE_KIND (t
) != NOTE_INSN_BASIC_BLOCK
)
5861 emit_insn_after (insn
, t
);
5864 testreg
= SET_DEST (XVECEXP (PATTERN (loop
->loop_end
), 0, 2));
5865 if (GET_CODE (testreg
) == SCRATCH
)
5866 testreg
= loop
->iter_reg
;
5868 emit_insn_before (gen_movsi (testreg
, loop
->iter_reg
), loop
->loop_end
);
5870 test
= gen_rtx_NE (VOIDmode
, testreg
, const0_rtx
);
5871 insn
= emit_jump_insn_before (gen_cbranchsi4 (test
, testreg
, const0_rtx
,
5875 JUMP_LABEL (insn
) = loop
->start_label
;
5876 LABEL_NUSES (loop
->start_label
)++;
5877 delete_insn (loop
->loop_end
);
5880 static struct hw_doloop_hooks c6x_doloop_hooks
=
5887 /* Run the hw-doloop pass to modulo-schedule hardware loops, or split the
5888 doloop_end patterns where such optimizations are impossible. */
5893 reorg_loops (true, &c6x_doloop_hooks
);
5896 /* Implement the TARGET_MACHINE_DEPENDENT_REORG pass. We split call insns here
5897 into a sequence that loads the return register and performs the call,
5898 and emit the return label.
5899 If scheduling after reload is requested, it happens here. */
5905 bool do_selsched
= (c6x_flag_schedule_insns2
&& flag_selective_scheduling2
5906 && !maybe_skip_selective_scheduling ());
5908 /* We are freeing block_for_insn in the toplev to keep compatibility
5909 with old MDEP_REORGS that are not CFG based. Recompute it now. */
5910 compute_bb_for_insn ();
5912 df_clear_flags (DF_LR_RUN_DCE
);
5913 df_note_add_problem ();
5915 /* If optimizing, we'll have split before scheduling. */
5921 if (c6x_flag_schedule_insns2
)
5923 int sz
= get_max_uid () * 3 / 2 + 1;
5925 insn_info
.create (sz
);
5928 /* Make sure the real-jump insns we create are not deleted. When modulo-
5929 scheduling, situations where a reg is only stored in a loop can also
5930 cause dead code when doing the initial unrolling. */
5931 sched_no_dce
= true;
5935 if (c6x_flag_schedule_insns2
)
5937 split_delayed_insns ();
5938 timevar_push (TV_SCHED2
);
5940 run_selective_scheduling ();
5943 conditionalize_after_sched ();
5944 timevar_pop (TV_SCHED2
);
5946 free_delay_pairs ();
5948 sched_no_dce
= false;
5950 rtx_code_label
**call_labels
= XCNEWVEC (rtx_code_label
*, get_max_uid () + 1);
5952 reorg_split_calls (call_labels
);
5954 if (c6x_flag_schedule_insns2
)
5956 FOR_EACH_BB_FN (bb
, cfun
)
5957 if ((bb
->flags
& BB_DISABLE_SCHEDULE
) == 0)
5958 assign_reservations (BB_HEAD (bb
), BB_END (bb
));
5961 if (c6x_flag_var_tracking
)
5963 timevar_push (TV_VAR_TRACKING
);
5964 variable_tracking_main ();
5965 timevar_pop (TV_VAR_TRACKING
);
5968 reorg_emit_nops (call_labels
);
5970 /* Post-process the schedule to move parallel insns into SEQUENCEs. */
5971 if (c6x_flag_schedule_insns2
)
5973 free_delay_pairs ();
5977 df_finish_pass (false);
5980 /* Called when a function has been assembled. It should perform all the
5981 tasks of ASM_DECLARE_FUNCTION_SIZE in elfos.h, plus target-specific
5983 We free the reservation (and other scheduling) information here now that
5984 all insns have been output. */
5986 c6x_function_end (FILE *file
, const char *fname
)
5988 c6x_output_fn_unwind (file
);
5990 insn_info
.release ();
5992 if (!flag_inhibit_size_directive
)
5993 ASM_OUTPUT_MEASURED_SIZE (file
, fname
);
5996 /* Determine whether X is a shift with code CODE and an integer amount
5999 shift_p (rtx x
, enum rtx_code code
, int amount
)
6001 return (GET_CODE (x
) == code
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6002 && INTVAL (XEXP (x
, 1)) == amount
);
6005 /* Compute a (partial) cost for rtx X. Return true if the complete
6006 cost has been computed, and false if subexpressions should be
6007 scanned. In either case, *TOTAL contains the cost result. */
6010 c6x_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno
, int *total
,
6013 int cost2
= COSTS_N_INSNS (1);
6015 int code
= GET_CODE (x
);
6020 if (outer_code
== SET
|| outer_code
== PLUS
)
6021 *total
= satisfies_constraint_IsB (x
) ? 0 : cost2
;
6022 else if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
6023 || outer_code
== MINUS
)
6024 *total
= satisfies_constraint_Is5 (x
) ? 0 : cost2
;
6025 else if (GET_RTX_CLASS (outer_code
) == RTX_COMPARE
6026 || GET_RTX_CLASS (outer_code
) == RTX_COMM_COMPARE
)
6027 *total
= satisfies_constraint_Iu4 (x
) ? 0 : cost2
;
6028 else if (outer_code
== ASHIFT
|| outer_code
== ASHIFTRT
6029 || outer_code
== LSHIFTRT
)
6030 *total
= satisfies_constraint_Iu5 (x
) ? 0 : cost2
;
6039 *total
= COSTS_N_INSNS (2);
6043 /* Recognize a mult_highpart operation. */
6044 if ((mode
== HImode
|| mode
== SImode
)
6045 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6046 && GET_MODE (XEXP (x
, 0)) == GET_MODE_2XWIDER_MODE (mode
).require ()
6047 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
6048 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6049 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
))
6051 rtx mul
= XEXP (XEXP (x
, 0), 0);
6052 rtx op0
= XEXP (mul
, 0);
6053 rtx op1
= XEXP (mul
, 1);
6054 enum rtx_code code0
= GET_CODE (op0
);
6055 enum rtx_code code1
= GET_CODE (op1
);
6058 && (code0
== SIGN_EXTEND
|| code0
== ZERO_EXTEND
))
6060 && code0
== ZERO_EXTEND
&& code1
== SIGN_EXTEND
))
6063 *total
= COSTS_N_INSNS (2);
6065 *total
= COSTS_N_INSNS (12);
6066 mode
= GET_MODE (XEXP (op0
, 0));
6067 *total
+= rtx_cost (XEXP (op0
, 0), mode
, code0
, 0, speed
);
6068 *total
+= rtx_cost (XEXP (op1
, 0), mode
, code1
, 0, speed
);
6078 *total
= COSTS_N_INSNS (CONSTANT_P (XEXP (x
, 1)) ? 4 : 15);
6080 *total
= COSTS_N_INSNS (1);
6085 *total
= COSTS_N_INSNS (1);
6086 op0
= code
== PLUS
? XEXP (x
, 0) : XEXP (x
, 1);
6087 op1
= code
== PLUS
? XEXP (x
, 1) : XEXP (x
, 0);
6088 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6089 && INTEGRAL_MODE_P (mode
)
6090 && GET_CODE (op0
) == MULT
6091 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
6092 && (INTVAL (XEXP (op0
, 1)) == 2
6093 || INTVAL (XEXP (op0
, 1)) == 4
6094 || (code
== PLUS
&& INTVAL (XEXP (op0
, 1)) == 8)))
6096 *total
+= rtx_cost (XEXP (op0
, 0), mode
, ASHIFT
, 0, speed
);
6097 *total
+= rtx_cost (op1
, mode
, (enum rtx_code
) code
, 1, speed
);
6108 *total
= COSTS_N_INSNS (speed
? 10 : 1);
6110 *total
= COSTS_N_INSNS (speed
? 200 : 4);
6112 else if (mode
== SFmode
)
6115 *total
= COSTS_N_INSNS (speed
? 4 : 1);
6117 *total
= COSTS_N_INSNS (speed
? 100 : 4);
6119 else if (mode
== DImode
)
6122 && GET_CODE (op0
) == GET_CODE (op1
)
6123 && (GET_CODE (op0
) == ZERO_EXTEND
6124 || GET_CODE (op0
) == SIGN_EXTEND
))
6126 *total
= COSTS_N_INSNS (speed
? 2 : 1);
6127 op0
= XEXP (op0
, 0);
6128 op1
= XEXP (op1
, 0);
6131 /* Maybe improve this laster. */
6132 *total
= COSTS_N_INSNS (20);
6134 else if (mode
== SImode
)
6136 if (((GET_CODE (op0
) == ZERO_EXTEND
6137 || GET_CODE (op0
) == SIGN_EXTEND
6138 || shift_p (op0
, LSHIFTRT
, 16))
6139 && (GET_CODE (op1
) == SIGN_EXTEND
6140 || GET_CODE (op1
) == ZERO_EXTEND
6141 || scst5_operand (op1
, SImode
)
6142 || shift_p (op1
, ASHIFTRT
, 16)
6143 || shift_p (op1
, LSHIFTRT
, 16)))
6144 || (shift_p (op0
, ASHIFTRT
, 16)
6145 && (GET_CODE (op1
) == SIGN_EXTEND
6146 || shift_p (op1
, ASHIFTRT
, 16))))
6148 *total
= COSTS_N_INSNS (speed
? 2 : 1);
6149 op0
= XEXP (op0
, 0);
6150 if (scst5_operand (op1
, SImode
))
6153 op1
= XEXP (op1
, 0);
6156 *total
= COSTS_N_INSNS (1);
6157 else if (TARGET_MPY32
)
6158 *total
= COSTS_N_INSNS (4);
6160 *total
= COSTS_N_INSNS (6);
6162 else if (mode
== HImode
)
6163 *total
= COSTS_N_INSNS (speed
? 2 : 1);
6165 if (GET_CODE (op0
) != REG
6166 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
6167 *total
+= rtx_cost (op0
, mode
, MULT
, 0, speed
);
6168 if (op1
&& GET_CODE (op1
) != REG
6169 && (GET_CODE (op1
) != SUBREG
|| GET_CODE (SUBREG_REG (op1
)) != REG
))
6170 *total
+= rtx_cost (op1
, mode
, MULT
, 1, speed
);
6175 /* This is a bit random; assuming on average there'll be 16 leading
6176 zeros. FIXME: estimate better for constant dividends. */
6177 *total
= COSTS_N_INSNS (6 + 3 * 16);
6181 /* Recognize the cmp_and/ior patterns. */
6183 if ((GET_CODE (op0
) == EQ
|| GET_CODE (op0
) == NE
)
6184 && REG_P (XEXP (op0
, 0))
6185 && XEXP (op0
, 1) == const0_rtx
6186 && rtx_equal_p (XEXP (x
, 1), XEXP (op0
, 0)))
6188 *total
= rtx_cost (XEXP (x
, 1), VOIDmode
, (enum rtx_code
) outer_code
,
6199 /* Implements target hook vector_mode_supported_p. */
6202 c6x_vector_mode_supported_p (machine_mode mode
)
6217 /* Implements TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
6219 c6x_preferred_simd_mode (scalar_mode mode
)
6233 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
6236 c6x_scalar_mode_supported_p (scalar_mode mode
)
6238 if (ALL_FIXED_POINT_MODE_P (mode
)
6239 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
6242 return default_scalar_mode_supported_p (mode
);
6245 /* Output a reference from a function exception table to the type_info
6246 object X. Output these via a special assembly directive. */
6249 c6x_output_ttype (rtx x
)
6251 /* Use special relocations for symbol references. */
6252 if (GET_CODE (x
) != CONST_INT
)
6253 fputs ("\t.ehtype\t", asm_out_file
);
6255 fputs ("\t.word\t", asm_out_file
);
6256 output_addr_const (asm_out_file
, x
);
6257 fputc ('\n', asm_out_file
);
6262 /* Modify the return address of the current function. */
6265 c6x_set_return_address (rtx source
, rtx scratch
)
6267 struct c6x_frame frame
;
6269 HOST_WIDE_INT offset
;
6271 c6x_compute_frame_layout (&frame
);
6272 if (! c6x_save_reg (RETURN_ADDR_REGNO
))
6273 emit_move_insn (gen_rtx_REG (Pmode
, RETURN_ADDR_REGNO
), source
);
6277 if (frame_pointer_needed
)
6279 addr
= hard_frame_pointer_rtx
;
6280 offset
= frame
.b3_offset
;
6284 addr
= stack_pointer_rtx
;
6285 offset
= frame
.to_allocate
- frame
.b3_offset
;
6288 /* TODO: Use base+offset loads where possible. */
6291 HOST_WIDE_INT low
= trunc_int_for_mode (offset
, HImode
);
6293 emit_insn (gen_movsi_high (scratch
, GEN_INT (low
)));
6295 emit_insn (gen_movsi_lo_sum (scratch
, scratch
, GEN_INT(offset
)));
6296 emit_insn (gen_addsi3 (scratch
, addr
, scratch
));
6300 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
6304 /* We save pairs of registers using a DImode store. Describe the component
6305 registers for DWARF generation code. */
6308 c6x_dwarf_register_span (rtx rtl
)
6311 unsigned real_regno
;
6316 regno
= REGNO (rtl
);
6317 nregs
= REG_NREGS (rtl
);
6321 p
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc(nregs
));
6322 for (i
= 0; i
< nregs
; i
++)
6324 if (TARGET_BIG_ENDIAN
)
6325 real_regno
= regno
+ nregs
- (i
+ 1);
6327 real_regno
= regno
+ i
;
6329 XVECEXP (p
, 0, i
) = gen_rtx_REG (SImode
, real_regno
);
6335 /* Codes for all the C6X builtins. */
6370 static GTY(()) tree c6x_builtin_decls
[C6X_BUILTIN_MAX
];
6372 /* Return the C6X builtin for CODE. */
6374 c6x_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
6376 if (code
>= C6X_BUILTIN_MAX
)
6377 return error_mark_node
;
6379 return c6x_builtin_decls
[code
];
6382 #define def_builtin(NAME, TYPE, CODE) \
6385 bdecl = add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
6387 c6x_builtin_decls[CODE] = bdecl; \
6390 /* Set up all builtin functions for this target. */
6392 c6x_init_builtins (void)
6394 tree V4QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 4);
6395 tree V2HI_type_node
= build_vector_type (intHI_type_node
, 2);
6396 tree V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
6398 = build_function_type_list (integer_type_node
, integer_type_node
,
6400 tree int_ftype_int_int
6401 = build_function_type_list (integer_type_node
, integer_type_node
,
6402 integer_type_node
, NULL_TREE
);
6403 tree v2hi_ftype_v2hi
6404 = build_function_type_list (V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
6405 tree v4qi_ftype_v4qi_v4qi
6406 = build_function_type_list (V4QI_type_node
, V4QI_type_node
,
6407 V4QI_type_node
, NULL_TREE
);
6408 tree v2hi_ftype_v2hi_v2hi
6409 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
6410 V2HI_type_node
, NULL_TREE
);
6411 tree v2si_ftype_v2hi_v2hi
6412 = build_function_type_list (V2SI_type_node
, V2HI_type_node
,
6413 V2HI_type_node
, NULL_TREE
);
6415 def_builtin ("__builtin_c6x_sadd", int_ftype_int_int
,
6417 def_builtin ("__builtin_c6x_ssub", int_ftype_int_int
,
6419 def_builtin ("__builtin_c6x_add2", v2hi_ftype_v2hi_v2hi
,
6421 def_builtin ("__builtin_c6x_sub2", v2hi_ftype_v2hi_v2hi
,
6423 def_builtin ("__builtin_c6x_add4", v4qi_ftype_v4qi_v4qi
,
6425 def_builtin ("__builtin_c6x_sub4", v4qi_ftype_v4qi_v4qi
,
6427 def_builtin ("__builtin_c6x_mpy2", v2si_ftype_v2hi_v2hi
,
6429 def_builtin ("__builtin_c6x_sadd2", v2hi_ftype_v2hi_v2hi
,
6431 def_builtin ("__builtin_c6x_ssub2", v2hi_ftype_v2hi_v2hi
,
6433 def_builtin ("__builtin_c6x_saddu4", v4qi_ftype_v4qi_v4qi
,
6434 C6X_BUILTIN_SADDU4
);
6435 def_builtin ("__builtin_c6x_smpy2", v2si_ftype_v2hi_v2hi
,
6438 def_builtin ("__builtin_c6x_smpy", int_ftype_int_int
,
6440 def_builtin ("__builtin_c6x_smpyh", int_ftype_int_int
,
6442 def_builtin ("__builtin_c6x_smpyhl", int_ftype_int_int
,
6443 C6X_BUILTIN_SMPYHL
);
6444 def_builtin ("__builtin_c6x_smpylh", int_ftype_int_int
,
6445 C6X_BUILTIN_SMPYLH
);
6447 def_builtin ("__builtin_c6x_sshl", int_ftype_int_int
,
6449 def_builtin ("__builtin_c6x_subc", int_ftype_int_int
,
6452 def_builtin ("__builtin_c6x_avg2", v2hi_ftype_v2hi_v2hi
,
6454 def_builtin ("__builtin_c6x_avgu4", v4qi_ftype_v4qi_v4qi
,
6457 def_builtin ("__builtin_c6x_clrr", int_ftype_int_int
,
6459 def_builtin ("__builtin_c6x_extr", int_ftype_int_int
,
6461 def_builtin ("__builtin_c6x_extru", int_ftype_int_int
,
6464 def_builtin ("__builtin_c6x_abs", int_ftype_int
, C6X_BUILTIN_ABS
);
6465 def_builtin ("__builtin_c6x_abs2", v2hi_ftype_v2hi
, C6X_BUILTIN_ABS2
);
6469 struct builtin_description
6471 const enum insn_code icode
;
6472 const char *const name
;
6473 const enum c6x_builtins code
;
6476 static const struct builtin_description bdesc_2arg
[] =
6478 { CODE_FOR_saddsi3
, "__builtin_c6x_sadd", C6X_BUILTIN_SADD
},
6479 { CODE_FOR_ssubsi3
, "__builtin_c6x_ssub", C6X_BUILTIN_SSUB
},
6480 { CODE_FOR_addv2hi3
, "__builtin_c6x_add2", C6X_BUILTIN_ADD2
},
6481 { CODE_FOR_subv2hi3
, "__builtin_c6x_sub2", C6X_BUILTIN_SUB2
},
6482 { CODE_FOR_addv4qi3
, "__builtin_c6x_add4", C6X_BUILTIN_ADD4
},
6483 { CODE_FOR_subv4qi3
, "__builtin_c6x_sub4", C6X_BUILTIN_SUB4
},
6484 { CODE_FOR_ss_addv2hi3
, "__builtin_c6x_sadd2", C6X_BUILTIN_SADD2
},
6485 { CODE_FOR_ss_subv2hi3
, "__builtin_c6x_ssub2", C6X_BUILTIN_SSUB2
},
6486 { CODE_FOR_us_addv4qi3
, "__builtin_c6x_saddu4", C6X_BUILTIN_SADDU4
},
6488 { CODE_FOR_subcsi3
, "__builtin_c6x_subc", C6X_BUILTIN_SUBC
},
6489 { CODE_FOR_ss_ashlsi3
, "__builtin_c6x_sshl", C6X_BUILTIN_SSHL
},
6491 { CODE_FOR_avgv2hi3
, "__builtin_c6x_avg2", C6X_BUILTIN_AVG2
},
6492 { CODE_FOR_uavgv4qi3
, "__builtin_c6x_avgu4", C6X_BUILTIN_AVGU4
},
6494 { CODE_FOR_mulhqsq3
, "__builtin_c6x_smpy", C6X_BUILTIN_SMPY
},
6495 { CODE_FOR_mulhqsq3_hh
, "__builtin_c6x_smpyh", C6X_BUILTIN_SMPYH
},
6496 { CODE_FOR_mulhqsq3_lh
, "__builtin_c6x_smpylh", C6X_BUILTIN_SMPYLH
},
6497 { CODE_FOR_mulhqsq3_hl
, "__builtin_c6x_smpyhl", C6X_BUILTIN_SMPYHL
},
6499 { CODE_FOR_mulv2hqv2sq3
, "__builtin_c6x_smpy2", C6X_BUILTIN_SMPY2
},
6501 { CODE_FOR_clrr
, "__builtin_c6x_clrr", C6X_BUILTIN_CLRR
},
6502 { CODE_FOR_extr
, "__builtin_c6x_extr", C6X_BUILTIN_EXTR
},
6503 { CODE_FOR_extru
, "__builtin_c6x_extru", C6X_BUILTIN_EXTRU
}
6506 static const struct builtin_description bdesc_1arg
[] =
6508 { CODE_FOR_ssabssi2
, "__builtin_c6x_abs", C6X_BUILTIN_ABS
},
6509 { CODE_FOR_ssabsv2hi2
, "__builtin_c6x_abs2", C6X_BUILTIN_ABS2
}
6512 /* Errors in the source file can cause expand_expr to return const0_rtx
6513 where we expect a vector. To avoid crashing, use one of the vector
6514 clear instructions. */
6516 safe_vector_operand (rtx x
, machine_mode mode
)
6518 if (x
!= const0_rtx
)
6520 x
= gen_reg_rtx (SImode
);
6522 emit_insn (gen_movsi (x
, CONST0_RTX (SImode
)));
6523 return gen_lowpart (mode
, x
);
6526 /* Subroutine of c6x_expand_builtin to take care of binop insns. MACFLAG is -1
6527 if this is a normal binary op, or one of the MACFLAG_xxx constants. */
6530 c6x_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
,
6533 int offs
= match_op
? 1 : 0;
6535 tree arg0
= CALL_EXPR_ARG (exp
, 0);
6536 tree arg1
= CALL_EXPR_ARG (exp
, 1);
6537 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6538 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6539 machine_mode op0mode
= GET_MODE (op0
);
6540 machine_mode op1mode
= GET_MODE (op1
);
6541 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6542 machine_mode mode0
= insn_data
[icode
].operand
[1 + offs
].mode
;
6543 machine_mode mode1
= insn_data
[icode
].operand
[2 + offs
].mode
;
6546 if (VECTOR_MODE_P (mode0
))
6547 op0
= safe_vector_operand (op0
, mode0
);
6548 if (VECTOR_MODE_P (mode1
))
6549 op1
= safe_vector_operand (op1
, mode1
);
6552 || GET_MODE (target
) != tmode
6553 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6555 if (tmode
== SQmode
|| tmode
== V2SQmode
)
6557 ret
= gen_reg_rtx (tmode
== SQmode
? SImode
: V2SImode
);
6558 target
= gen_lowpart (tmode
, ret
);
6561 target
= gen_reg_rtx (tmode
);
6564 if ((op0mode
== V2HImode
|| op0mode
== SImode
|| op0mode
== VOIDmode
)
6565 && (mode0
== V2HQmode
|| mode0
== HQmode
|| mode0
== SQmode
))
6568 op0
= gen_lowpart (mode0
, op0
);
6570 if ((op1mode
== V2HImode
|| op1mode
== SImode
|| op1mode
== VOIDmode
)
6571 && (mode1
== V2HQmode
|| mode1
== HQmode
|| mode1
== SQmode
))
6574 op1
= gen_lowpart (mode1
, op1
);
6576 /* In case the insn wants input operands in modes different from
6577 the result, abort. */
6578 gcc_assert ((op0mode
== mode0
|| op0mode
== VOIDmode
)
6579 && (op1mode
== mode1
|| op1mode
== VOIDmode
));
6581 if (! (*insn_data
[icode
].operand
[1 + offs
].predicate
) (op0
, mode0
))
6582 op0
= copy_to_mode_reg (mode0
, op0
);
6583 if (! (*insn_data
[icode
].operand
[2 + offs
].predicate
) (op1
, mode1
))
6584 op1
= copy_to_mode_reg (mode1
, op1
);
6587 pat
= GEN_FCN (icode
) (target
, target
, op0
, op1
);
6589 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
6599 /* Subroutine of c6x_expand_builtin to take care of unop insns. */
6602 c6x_expand_unop_builtin (enum insn_code icode
, tree exp
,
6606 tree arg0
= CALL_EXPR_ARG (exp
, 0);
6607 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
6608 machine_mode op0mode
= GET_MODE (op0
);
6609 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6610 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6613 || GET_MODE (target
) != tmode
6614 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6615 target
= gen_reg_rtx (tmode
);
6617 if (VECTOR_MODE_P (mode0
))
6618 op0
= safe_vector_operand (op0
, mode0
);
6620 if (op0mode
== SImode
&& mode0
== HImode
)
6623 op0
= gen_lowpart (HImode
, op0
);
6625 gcc_assert (op0mode
== mode0
|| op0mode
== VOIDmode
);
6627 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6628 op0
= copy_to_mode_reg (mode0
, op0
);
6630 pat
= GEN_FCN (icode
) (target
, op0
);
6637 /* Expand an expression EXP that calls a built-in function,
6638 with result going to TARGET if that's convenient
6639 (and in mode MODE if that's convenient).
6640 SUBTARGET may be used as the target for computing one of EXP's operands.
6641 IGNORE is nonzero if the value is to be ignored. */
6644 c6x_expand_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
6645 rtx subtarget ATTRIBUTE_UNUSED
,
6646 machine_mode mode ATTRIBUTE_UNUSED
,
6647 int ignore ATTRIBUTE_UNUSED
)
6650 const struct builtin_description
*d
;
6651 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
6652 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6654 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
6655 if (d
->code
== fcode
)
6656 return c6x_expand_binop_builtin (d
->icode
, exp
, target
,
6657 fcode
== C6X_BUILTIN_CLRR
);
6659 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
6660 if (d
->code
== fcode
)
6661 return c6x_expand_unop_builtin (d
->icode
, exp
, target
);
6666 /* Target unwind frame info is generated from dwarf CFI directives, so
6667 always output dwarf2 unwind info. */
6669 static enum unwind_info_type
6670 c6x_debug_unwind_info (void)
6672 if (flag_unwind_tables
|| flag_exceptions
)
6675 return default_debug_unwind_info ();
6678 /* Implement TARGET_HARD_REGNO_MODE_OK. */
6681 c6x_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
6683 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
|| (regno
& 1) == 0;
6686 /* Implement TARGET_MODES_TIEABLE_P. */
6689 c6x_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
6691 return (mode1
== mode2
6692 || (GET_MODE_SIZE (mode1
) <= UNITS_PER_WORD
6693 && GET_MODE_SIZE (mode2
) <= UNITS_PER_WORD
));
6697 /* Target Structure. */
6699 /* Initialize the GCC target structure. */
6700 #undef TARGET_FUNCTION_ARG
6701 #define TARGET_FUNCTION_ARG c6x_function_arg
6702 #undef TARGET_FUNCTION_ARG_ADVANCE
6703 #define TARGET_FUNCTION_ARG_ADVANCE c6x_function_arg_advance
6704 #undef TARGET_FUNCTION_ARG_BOUNDARY
6705 #define TARGET_FUNCTION_ARG_BOUNDARY c6x_function_arg_boundary
6706 #undef TARGET_FUNCTION_ARG_ROUND_BOUNDARY
6707 #define TARGET_FUNCTION_ARG_ROUND_BOUNDARY \
6708 c6x_function_arg_round_boundary
6709 #undef TARGET_FUNCTION_VALUE_REGNO_P
6710 #define TARGET_FUNCTION_VALUE_REGNO_P c6x_function_value_regno_p
6711 #undef TARGET_FUNCTION_VALUE
6712 #define TARGET_FUNCTION_VALUE c6x_function_value
6713 #undef TARGET_LIBCALL_VALUE
6714 #define TARGET_LIBCALL_VALUE c6x_libcall_value
6715 #undef TARGET_RETURN_IN_MEMORY
6716 #define TARGET_RETURN_IN_MEMORY c6x_return_in_memory
6717 #undef TARGET_RETURN_IN_MSB
6718 #define TARGET_RETURN_IN_MSB c6x_return_in_msb
6719 #undef TARGET_PASS_BY_REFERENCE
6720 #define TARGET_PASS_BY_REFERENCE c6x_pass_by_reference
6721 #undef TARGET_CALLEE_COPIES
6722 #define TARGET_CALLEE_COPIES c6x_callee_copies
6723 #undef TARGET_STRUCT_VALUE_RTX
6724 #define TARGET_STRUCT_VALUE_RTX c6x_struct_value_rtx
6725 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
6726 #define TARGET_FUNCTION_OK_FOR_SIBCALL c6x_function_ok_for_sibcall
6728 #undef TARGET_ASM_OUTPUT_MI_THUNK
6729 #define TARGET_ASM_OUTPUT_MI_THUNK c6x_output_mi_thunk
6730 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
6731 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK c6x_can_output_mi_thunk
6733 #undef TARGET_BUILD_BUILTIN_VA_LIST
6734 #define TARGET_BUILD_BUILTIN_VA_LIST c6x_build_builtin_va_list
6736 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
6737 #define TARGET_ASM_TRAMPOLINE_TEMPLATE c6x_asm_trampoline_template
6738 #undef TARGET_TRAMPOLINE_INIT
6739 #define TARGET_TRAMPOLINE_INIT c6x_initialize_trampoline
6741 #undef TARGET_LEGITIMATE_CONSTANT_P
6742 #define TARGET_LEGITIMATE_CONSTANT_P c6x_legitimate_constant_p
6743 #undef TARGET_LEGITIMATE_ADDRESS_P
6744 #define TARGET_LEGITIMATE_ADDRESS_P c6x_legitimate_address_p
6747 #define TARGET_LRA_P hook_bool_void_false
6749 #undef TARGET_IN_SMALL_DATA_P
6750 #define TARGET_IN_SMALL_DATA_P c6x_in_small_data_p
6751 #undef TARGET_ASM_SELECT_RTX_SECTION
6752 #define TARGET_ASM_SELECT_RTX_SECTION c6x_select_rtx_section
6753 #undef TARGET_ASM_SELECT_SECTION
6754 #define TARGET_ASM_SELECT_SECTION c6x_elf_select_section
6755 #undef TARGET_ASM_UNIQUE_SECTION
6756 #define TARGET_ASM_UNIQUE_SECTION c6x_elf_unique_section
6757 #undef TARGET_SECTION_TYPE_FLAGS
6758 #define TARGET_SECTION_TYPE_FLAGS c6x_section_type_flags
6759 #undef TARGET_HAVE_SRODATA_SECTION
6760 #define TARGET_HAVE_SRODATA_SECTION true
6761 #undef TARGET_ASM_MERGEABLE_RODATA_PREFIX
6762 #define TARGET_ASM_MERGEABLE_RODATA_PREFIX ".const"
6764 #undef TARGET_OPTION_OVERRIDE
6765 #define TARGET_OPTION_OVERRIDE c6x_option_override
6766 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6767 #define TARGET_CONDITIONAL_REGISTER_USAGE c6x_conditional_register_usage
6769 #undef TARGET_INIT_LIBFUNCS
6770 #define TARGET_INIT_LIBFUNCS c6x_init_libfuncs
6771 #undef TARGET_LIBFUNC_GNU_PREFIX
6772 #define TARGET_LIBFUNC_GNU_PREFIX true
6774 #undef TARGET_SCALAR_MODE_SUPPORTED_P
6775 #define TARGET_SCALAR_MODE_SUPPORTED_P c6x_scalar_mode_supported_p
6776 #undef TARGET_VECTOR_MODE_SUPPORTED_P
6777 #define TARGET_VECTOR_MODE_SUPPORTED_P c6x_vector_mode_supported_p
6778 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
6779 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE c6x_preferred_simd_mode
6781 #undef TARGET_RTX_COSTS
6782 #define TARGET_RTX_COSTS c6x_rtx_costs
6784 #undef TARGET_SCHED_INIT
6785 #define TARGET_SCHED_INIT c6x_sched_init
6786 #undef TARGET_SCHED_SET_SCHED_FLAGS
6787 #define TARGET_SCHED_SET_SCHED_FLAGS c6x_set_sched_flags
6788 #undef TARGET_SCHED_ADJUST_COST
6789 #define TARGET_SCHED_ADJUST_COST c6x_adjust_cost
6790 #undef TARGET_SCHED_ISSUE_RATE
6791 #define TARGET_SCHED_ISSUE_RATE c6x_issue_rate
6792 #undef TARGET_SCHED_VARIABLE_ISSUE
6793 #define TARGET_SCHED_VARIABLE_ISSUE c6x_variable_issue
6794 #undef TARGET_SCHED_REORDER
6795 #define TARGET_SCHED_REORDER c6x_sched_reorder
6796 #undef TARGET_SCHED_REORDER2
6797 #define TARGET_SCHED_REORDER2 c6x_sched_reorder2
6798 #undef TARGET_SCHED_DFA_NEW_CYCLE
6799 #define TARGET_SCHED_DFA_NEW_CYCLE c6x_dfa_new_cycle
6800 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
6801 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN c6x_sched_dfa_pre_cycle_insn
6802 #undef TARGET_SCHED_EXPOSED_PIPELINE
6803 #define TARGET_SCHED_EXPOSED_PIPELINE true
6805 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
6806 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT c6x_alloc_sched_context
6807 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
6808 #define TARGET_SCHED_INIT_SCHED_CONTEXT c6x_init_sched_context
6809 #undef TARGET_SCHED_SET_SCHED_CONTEXT
6810 #define TARGET_SCHED_SET_SCHED_CONTEXT c6x_set_sched_context
6811 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
6812 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT c6x_clear_sched_context
6813 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
6814 #define TARGET_SCHED_FREE_SCHED_CONTEXT c6x_free_sched_context
6816 #undef TARGET_CAN_ELIMINATE
6817 #define TARGET_CAN_ELIMINATE c6x_can_eliminate
6819 #undef TARGET_PREFERRED_RENAME_CLASS
6820 #define TARGET_PREFERRED_RENAME_CLASS c6x_preferred_rename_class
6822 #undef TARGET_MACHINE_DEPENDENT_REORG
6823 #define TARGET_MACHINE_DEPENDENT_REORG c6x_reorg
6825 #undef TARGET_ASM_FILE_START
6826 #define TARGET_ASM_FILE_START c6x_file_start
6828 #undef TARGET_PRINT_OPERAND
6829 #define TARGET_PRINT_OPERAND c6x_print_operand
6830 #undef TARGET_PRINT_OPERAND_ADDRESS
6831 #define TARGET_PRINT_OPERAND_ADDRESS c6x_print_operand_address
6832 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6833 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P c6x_print_operand_punct_valid_p
6835 /* C6x unwinding tables use a different format for the typeinfo tables. */
6836 #undef TARGET_ASM_TTYPE
6837 #define TARGET_ASM_TTYPE c6x_output_ttype
6839 /* The C6x ABI follows the ARM EABI exception handling rules. */
6840 #undef TARGET_ARM_EABI_UNWINDER
6841 #define TARGET_ARM_EABI_UNWINDER true
6843 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
6844 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY c6x_asm_emit_except_personality
6846 #undef TARGET_ASM_INIT_SECTIONS
6847 #define TARGET_ASM_INIT_SECTIONS c6x_asm_init_sections
6849 #undef TARGET_DEBUG_UNWIND_INFO
6850 #define TARGET_DEBUG_UNWIND_INFO c6x_debug_unwind_info
6852 #undef TARGET_DWARF_REGISTER_SPAN
6853 #define TARGET_DWARF_REGISTER_SPAN c6x_dwarf_register_span
6855 #undef TARGET_INIT_BUILTINS
6856 #define TARGET_INIT_BUILTINS c6x_init_builtins
6857 #undef TARGET_EXPAND_BUILTIN
6858 #define TARGET_EXPAND_BUILTIN c6x_expand_builtin
6859 #undef TARGET_BUILTIN_DECL
6860 #define TARGET_BUILTIN_DECL c6x_builtin_decl
6862 #undef TARGET_HARD_REGNO_MODE_OK
6863 #define TARGET_HARD_REGNO_MODE_OK c6x_hard_regno_mode_ok
6864 #undef TARGET_MODES_TIEABLE_P
6865 #define TARGET_MODES_TIEABLE_P c6x_modes_tieable_p
6867 struct gcc_target targetm
= TARGET_INITIALIZER
;