gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  28   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  29
  30 /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
  31    It is used in nds32_encode_section_info() to store flag in symbol_ref
  32    in case the symbol should be placed in .rodata section.
  33    So that we can check it in nds32_legitimate_address_p().  */
  34 #define NDS32_SYMBOL_FLAG_RODATA \
  35   (SYMBOL_FLAG_MACH_DEP << 0)
  36 #define NDS32_SYMBOL_REF_RODATA_P(x) \
  37   ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
  38
  39 /* Classifies expand result for expand helper function.  */
  40 enum nds32_expand_result_type
  41 {
  42   EXPAND_DONE,
  43   EXPAND_FAIL,
  44   EXPAND_CREATE_TEMPLATE
  45 };
  46
  47 /* Check instruction LS-37-FP-implied form.
  48    Note: actually its immediate range is imm9u
  49          since it is used for lwi37/swi37 instructions.  */
  50 #define NDS32_LS_37_FP_P(rt, ra, imm)       \
  51   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  52    && REGNO (ra) == FP_REGNUM               \
  53    && satisfies_constraint_Iu09 (imm))
  54
  55 /* Check instruction LS-37-SP-implied form.
  56    Note: actually its immediate range is imm9u
  57          since it is used for lwi37/swi37 instructions.  */
  58 #define NDS32_LS_37_SP_P(rt, ra, imm)       \
  59   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  60    && REGNO (ra) == SP_REGNUM               \
  61    && satisfies_constraint_Iu09 (imm))
  62
  63
  64 /* Check load/store instruction form : Rt3, Ra3, imm3u.  */
  65 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
  66
  67 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
  68    Note: no need to check ra because Ra5 means it covers all registers.  */
  69 #define NDS32_LS_450_P(rt, ra, imm)                     \
  70   ((imm == const0_rtx)                                  \
  71    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS         \
  72        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  73
  74 /* Check instruction RRI-333-form.  */
  75 #define NDS32_RRI_333_P(rt, ra, imm)           \
  76   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS    \
  77    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
  78    && satisfies_constraint_Iu03 (imm))
  79
  80 /* Check instruction RI-45-form.  */
  81 #define NDS32_RI_45_P(rt, ra, imm)                     \
  82   (REGNO (rt) == REGNO (ra)                            \
  83    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS        \
  84        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
  85    && satisfies_constraint_Iu05 (imm))
  86
  87
  88 /* Check instruction RR-33-form.  */
  89 #define NDS32_RR_33_P(rt, ra)                   \
  90   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  91    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
  92
  93 /* Check instruction RRR-333-form.  */
  94 #define NDS32_RRR_333_P(rt, ra, rb)             \
  95   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  96    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS  \
  97    && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
  98
  99 /* Check instruction RR-45-form.
 100    Note: no need to check rb because Rb5 means it covers all registers.  */
 101 #define NDS32_RR_45_P(rt, ra, rb)               \
 102   (REGNO (rt) == REGNO (ra)                     \
 103    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
 104        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
 105
 106 /* Classifies address type to distinguish 16-bit/32-bit format.  */
 107 enum nds32_16bit_address_type
 108 {
 109   /* [reg]: 45 format address.  */
 110   ADDRESS_REG,
 111   /* [lo_reg + imm3u]: 333 format address.  */
 112   ADDRESS_LO_REG_IMM3U,
 113   /* post_inc [lo_reg + imm3u]: 333 format address.  */
 114   ADDRESS_POST_INC_LO_REG_IMM3U,
 115   /* post_modify [lo_reg + imm3u]: 333 format address.  */
 116   ADDRESS_POST_MODIFY_LO_REG_IMM3U,
 117   /* [$r8 + imm7u]: r8 imply address.  */
 118   ADDRESS_R8_IMM7U,
 119   /* [$fp + imm7u]: fp imply address.  */
 120   ADDRESS_FP_IMM7U,
 121   /* [$sp + imm7u]: sp imply address.  */
 122   ADDRESS_SP_IMM7U,
 123   /* Other address format.  */
 124   ADDRESS_NOT_16BIT_FORMAT
 125 };
 126
 127
 128 /* ------------------------------------------------------------------------ */
 129
 130 /* Define maximum numbers of registers for passing arguments.  */
 131 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
 132 #define NDS32_MAX_FPR_REGS_FOR_ARGS 6
 133
 134 /* Define the register number for first argument.  */
 135 #define NDS32_GPR_ARG_FIRST_REGNUM 0
 136 #define NDS32_FPR_ARG_FIRST_REGNUM 34
 137
 138 /* Define the register number for return value.  */
 139 #define NDS32_GPR_RET_FIRST_REGNUM 0
 140 #define NDS32_FPR_RET_FIRST_REGNUM 34
 141
 142 /* Define the first integer register number.  */
 143 #define NDS32_FIRST_GPR_REGNUM 0
 144 /* Define the last integer register number.  */
 145 #define NDS32_LAST_GPR_REGNUM 31
 146
 147 #define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6
 148 #define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \
 149   (TARGET_REDUCED_REGS ? 10 : 14)
 150
 151 /* Define the floating-point number of registers.  */
 152 #define NDS32_FLOAT_REGISTER_NUMBER                           \
 153  (((nds32_fp_regnum == NDS32_CONFIG_FPU_0)              \
 154    || (nds32_fp_regnum == NDS32_CONFIG_FPU_4)) ? 8      \
 155   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_1)            \
 156     || (nds32_fp_regnum == NDS32_CONFIG_FPU_5)) ? 16    \
 157   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_2)            \
 158     || (nds32_fp_regnum == NDS32_CONFIG_FPU_6)) ? 32    \
 159   : ((nds32_fp_regnum == NDS32_CONFIG_FPU_3)            \
 160     || (nds32_fp_regnum == NDS32_CONFIG_FPU_7)) ? 64    \
 161   : 32)
 162
 163 #define NDS32_EXT_FPU_DOT_E (nds32_fp_regnum >= 4)
 164
 165 /* Define the first floating-point register number.  */
 166 #define NDS32_FIRST_FPR_REGNUM 34
 167 /* Define the last floating-point register number.  */
 168 #define NDS32_LAST_FPR_REGNUM \
 169   (NDS32_FIRST_FPR_REGNUM + NDS32_FLOAT_REGISTER_NUMBER - 1)
 170
 171
 172 #define NDS32_IS_EXT_FPR_REGNUM(regno) \
 173   (((regno) >= NDS32_FIRST_FPR_REGNUM + 32) \
 174    && ((regno) < NDS32_FIRST_FPR_REGNUM + 64))
 175
 176 #define NDS32_IS_FPR_REGNUM(regno) \
 177   (((regno) >= NDS32_FIRST_FPR_REGNUM) \
 178    && ((regno) <= NDS32_LAST_FPR_REGNUM))
 179
 180 #define NDS32_FPR_REGNO_OK_FOR_SINGLE(regno) \
 181   ((regno) <= NDS32_LAST_FPR_REGNUM)
 182
 183 #define NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) \
 184   ((((regno) - NDS32_FIRST_FPR_REGNUM) & 1) == 0)
 185
 186 #define NDS32_IS_GPR_REGNUM(regno) \
 187   (((regno) <= NDS32_LAST_GPR_REGNUM))
 188
 189 /* Define double word alignment bits.  */
 190 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 191
 192 /* Define alignment checking macros for convenience.  */
 193 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 194 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 195 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 196
 197 /* Get alignment according to mode or type information.
 198    When 'type' is nonnull, there is no need to look at 'mode'.  */
 199 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
 200   (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
 201
 202 /* Round X up to the nearest double word.  */
 203 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 204
 205
 206 /* This macro is used to calculate the numbers of registers for
 207    containing 'size' bytes of the argument.
 208    The size of a register is a word in nds32 target.
 209    So we use UNITS_PER_WORD to do the calculation.  */
 210 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 211   ((mode == BLKmode)                                                     \
 212    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 213    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 214
 215 /* This macro is used to return the register number for passing argument.
 216    We need to obey the following rules:
 217      1. If it is required MORE THAN one register,
 218         we need to further check if it really needs to be
 219         aligned on double words.
 220           a) If double word alignment is necessary,
 221              the register number must be even value.
 222           b) Otherwise, the register number can be odd or even value.
 223      2. If it is required ONLY one register,
 224         the register number can be odd or even value.  */
 225 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
 226   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 227    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 228       ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 229       : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))               \
 230    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 231
 232 #define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \
 233   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                    \
 234    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)         \
 235       ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1)     \
 236       : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))               \
 237    : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
 238
 239 /* These two macros are to check if there are still available registers
 240    for passing argument, which must be entirely in registers.  */
 241 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type)   \
 242   ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 243     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 244    <= (NDS32_GPR_ARG_FIRST_REGNUM                               \
 245        + NDS32_MAX_GPR_REGS_FOR_ARGS))
 246
 247 #define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type)   \
 248   ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
 249     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 250    <= (NDS32_FPR_ARG_FIRST_REGNUM                               \
 251        + NDS32_MAX_FPR_REGS_FOR_ARGS))
 252
 253 /* These two macros are to check if there are still available registers
 254    for passing argument, either entirely in registers or partially
 255    in registers.  */
 256 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
 257   (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 258    < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
 259
 260 #define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \
 261   (NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
 262    < NDS32_FPR_ARG_FIRST_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS)
 263
 264 /* This macro is to check if the register is required to be saved on stack.
 265    If call_used_regs[regno] == 0, regno is the callee-saved register.
 266    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 267    As long as the register satisfies both criteria above,
 268    it is required to be saved.  */
 269 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 270   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 271
 272 /* This macro is to check if the push25/pop25 are available to be used
 273    for code generation.  Because pop25 also performs return behavior,
 274    the instructions may not be available for some cases.
 275    If we want to use push25/pop25, all the following conditions must
 276    be satisfied:
 277      1. TARGET_V3PUSH is set.
 278      2. Current function is not an ISR function.
 279      3. Current function is not a variadic function.*/
 280 #define NDS32_V3PUSH_AVAILABLE_P  \
 281   (TARGET_V3PUSH \
 282    && !nds32_isr_function_p (current_function_decl) \
 283    && (cfun->machine->va_args_size == 0))
 284
 285 /* ------------------------------------------------------------------------ */
 286
 287 /* A C structure for machine-specific, per-function data.
 288    This is added to the cfun structure.  */
 289 struct GTY(()) machine_function
 290 {
 291   /* Number of bytes allocated on the stack for variadic args
 292      if we want to push them into stack as pretend arguments by ourself.  */
 293   int va_args_size;
 294   /* Number of bytes reserved on the stack for
 295      local and temporary variables.  */
 296   int local_size;
 297   /* Number of bytes allocated on the stack for outgoing arguments.  */
 298   int out_args_size;
 299
 300   /* Number of bytes on the stack for saving $fp.  */
 301   int fp_size;
 302   /* Number of bytes on the stack for saving $gp.  */
 303   int gp_size;
 304   /* Number of bytes on the stack for saving $lp.  */
 305   int lp_size;
 306
 307   /* Number of bytes on the stack for saving general purpose
 308      callee-saved registers.  */
 309   int callee_saved_gpr_regs_size;
 310
 311   /* Number of bytes on the stack for saving floating-point
 312      callee-saved registers.  */
 313   int callee_saved_fpr_regs_size;
 314
 315   /* The padding bytes in callee-saved area may be required.  */
 316   int callee_saved_area_gpr_padding_bytes;
 317
 318   /* The first required general purpose callee-saved register.  */
 319   int callee_saved_first_gpr_regno;
 320   /* The last required general purpose callee-saved register.  */
 321   int callee_saved_last_gpr_regno;
 322
 323   /* The first required floating-point callee-saved register.  */
 324   int callee_saved_first_fpr_regno;
 325   /* The last required floating-point callee-saved register.  */
 326   int callee_saved_last_fpr_regno;
 327
 328   /* The padding bytes in varargs area may be required.  */
 329   int va_args_area_padding_bytes;
 330
 331   /* The first required register that should be saved on stack for va_args.  */
 332   int va_args_first_regno;
 333   /* The last required register that should be saved on stack for va_args.  */
 334   int va_args_last_regno;
 335
 336   /* Indicate that whether this function needs
 337      prologue/epilogue code generation.  */
 338   int naked_p;
 339   /* Indicate that whether this function
 340      uses fp_as_gp optimization.  */
 341   int fp_as_gp_p;
 342 };
 343
 344 /* A C structure that contains the arguments information.  */
 345 typedef struct
 346 {
 347   unsigned int gpr_offset;
 348   unsigned int fpr_offset;
 349 } nds32_cumulative_args;
 350
 351 /* ------------------------------------------------------------------------ */
 352
 353 /* The following we define C-ISR related stuff.
 354    In nds32 architecture, we have 73 vectors for interrupt/exception.
 355    For each vector (except for vector 0, which is used for reset behavior),
 356    we allow users to set its register saving scheme and interrupt level.  */
 357
 358 /* There are 73 vectors in nds32 architecture.
 359    0 for reset handler,
 360    1-8 for exception handler,
 361    and 9-72 for interrupt handler.
 362    We use an array, which is defined in nds32.c, to record
 363    essential information for each vector.  */
 364 #define NDS32_N_ISR_VECTORS 73
 365
 366 /* Define possible isr category.  */
 367 enum nds32_isr_category
 368 {
 369   NDS32_ISR_NONE,
 370   NDS32_ISR_INTERRUPT,
 371   NDS32_ISR_EXCEPTION,
 372   NDS32_ISR_RESET
 373 };
 374
 375 /* Define isr register saving scheme.  */
 376 enum nds32_isr_save_reg
 377 {
 378   NDS32_SAVE_ALL,
 379   NDS32_PARTIAL_SAVE
 380 };
 381
 382 /* Define isr nested type.  */
 383 enum nds32_isr_nested_type
 384 {
 385   NDS32_NESTED,
 386   NDS32_NOT_NESTED,
 387   NDS32_NESTED_READY
 388 };
 389
 390 /* Define structure to record isr information.
 391    The isr vector array 'isr_vectors[]' with this structure
 392    is defined in nds32.c.  */
 393 struct nds32_isr_info
 394 {
 395   /* The field to identify isr category.
 396      It should be set to NDS32_ISR_NONE by default.
 397      If user specifies a function as isr by using attribute,
 398      this field will be set accordingly.  */
 399   enum nds32_isr_category category;
 400
 401   /* A string for the applied function name.
 402      It should be set to empty string by default.  */
 403   char func_name[100];
 404
 405   /* The register saving scheme.
 406      It should be set to NDS32_PARTIAL_SAVE by default
 407      unless user specifies attribute to change it.  */
 408   enum nds32_isr_save_reg save_reg;
 409
 410   /* The nested type.
 411      It should be set to NDS32_NOT_NESTED by default
 412      unless user specifies attribute to change it.  */
 413   enum nds32_isr_nested_type nested_type;
 414
 415   /* Total vectors.
 416      The total vectors = interrupt + exception numbers + reset.
 417      It should be set to 0 by default.
 418      This field is ONLY used in NDS32_ISR_RESET category.  */
 419   unsigned int total_n_vectors;
 420
 421   /* A string for nmi handler name.
 422      It should be set to empty string by default.
 423      This field is ONLY used in NDS32_ISR_RESET category.  */
 424   char nmi_name[100];
 425
 426   /* A string for warm handler name.
 427      It should be set to empty string by default.
 428      This field is ONLY used in NDS32_ISR_RESET category.  */
 429   char warm_name[100];
 430 };
 431
 432 /* ------------------------------------------------------------------------ */
 433
 434 /* Define code for all nds32 builtins.  */
 435 enum nds32_builtins
 436 {
 437   NDS32_BUILTIN_ISYNC,
 438   NDS32_BUILTIN_ISB,
 439   NDS32_BUILTIN_DSB,
 440   NDS32_BUILTIN_MSYNC_ALL,
 441   NDS32_BUILTIN_MSYNC_STORE,
 442   NDS32_BUILTIN_MFSR,
 443   NDS32_BUILTIN_MFUSR,
 444   NDS32_BUILTIN_MTSR,
 445   NDS32_BUILTIN_MTSR_ISB,
 446   NDS32_BUILTIN_MTSR_DSB,
 447   NDS32_BUILTIN_MTUSR,
 448   NDS32_BUILTIN_SETGIE_EN,
 449   NDS32_BUILTIN_SETGIE_DIS,
 450   NDS32_BUILTIN_FMFCFG,
 451   NDS32_BUILTIN_FMFCSR,
 452   NDS32_BUILTIN_FMTCSR,
 453   NDS32_BUILTIN_FCPYNSS,
 454   NDS32_BUILTIN_FCPYSS,
 455   NDS32_BUILTIN_FCPYNSD,
 456   NDS32_BUILTIN_FCPYSD,
 457   NDS32_BUILTIN_FFB,
 458   NDS32_BUILTIN_FFMISM,
 459   NDS32_BUILTIN_FLMISM,
 460   NDS32_BUILTIN_LLW,
 461   NDS32_BUILTIN_LWUP,
 462   NDS32_BUILTIN_LBUP,
 463   NDS32_BUILTIN_SCW,
 464   NDS32_BUILTIN_SWUP,
 465   NDS32_BUILTIN_SBUP,
 466   NDS32_BUILTIN_CCTL_VA_LCK,
 467   NDS32_BUILTIN_CCTL_IDX_WBINVAL,
 468   NDS32_BUILTIN_CCTL_VA_WBINVAL_L1,
 469   NDS32_BUILTIN_CCTL_VA_WBINVAL_LA,
 470   NDS32_BUILTIN_CCTL_IDX_READ,
 471   NDS32_BUILTIN_CCTL_IDX_WRITE,
 472   NDS32_BUILTIN_CCTL_L1D_INVALALL,
 473   NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL,
 474   NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL,
 475   NDS32_BUILTIN_UALOAD_HW,
 476   NDS32_BUILTIN_UALOAD_W,
 477   NDS32_BUILTIN_UALOAD_DW,
 478   NDS32_BUILTIN_UASTORE_HW,
 479   NDS32_BUILTIN_UASTORE_W,
 480   NDS32_BUILTIN_UASTORE_DW,
 481   NDS32_BUILTIN_COUNT
 482 };
 483
 484 /* ------------------------------------------------------------------------ */
 485
 486 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 487
 488 #define TARGET_ISA_V3 \
 489   (nds32_arch_option == ARCH_V3 \
 490    || nds32_arch_option == ARCH_V3F \
 491    || nds32_arch_option == ARCH_V3S)
 492 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 493
 494 #define TARGET_CMODEL_SMALL \
 495    (nds32_cmodel_option == CMODEL_SMALL)
 496 #define TARGET_CMODEL_MEDIUM \
 497    (nds32_cmodel_option == CMODEL_MEDIUM)
 498 #define TARGET_CMODEL_LARGE \
 499    (nds32_cmodel_option == CMODEL_LARGE)
 500
 501 /* When -mcmodel=small or -mcmodel=medium,
 502    compiler may generate gp-base instruction directly.  */
 503 #define TARGET_GP_DIRECT \
 504    (nds32_cmodel_option == CMODEL_SMALL\
 505     || nds32_cmodel_option == CMODEL_MEDIUM)
 506
 507
 508 /* Run-time Target Specification.  */
 509 #define TARGET_SOFT_FLOAT (nds32_abi == NDS32_ABI_V2)
 510 /* Use hardware floating point calling convention.  */
 511 #define TARGET_HARD_FLOAT (nds32_abi == NDS32_ABI_V2_FP_PLUS)
 512
 513 /* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI,
 514    1 means  hard ABI and using full floating-point instruction,
 515    2 means hard ABI and only using single-precision floating-point
 516    instruction  */
 517 #if TARGET_ARCH_DEFAULT == 1
 518 #  define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
 519 #  define TARGET_DEFAULT_FPU_ISA MASK_FPU_DOUBLE | MASK_FPU_SINGLE
 520 #  define TARGET_DEFAULT_FPU_FMA 0
 521 #else
 522 #  if TARGET_ARCH_DEFAULT == 2
 523 #    define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
 524 #    define TARGET_DEFAULT_FPU_ISA MASK_FPU_SINGLE
 525 #    define TARGET_DEFAULT_FPU_FMA 0
 526 #  else
 527 #    define TARGET_DEFAULT_ABI NDS32_ABI_V2
 528 #    define TARGET_DEFAULT_FPU_ISA 0
 529 #    define TARGET_DEFAULT_FPU_FMA 0
 530 #  endif
 531 #endif
 532
 533 #define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2
 534 /* ------------------------------------------------------------------------ */
 535 \f
 536 /* Controlling the Compilation Driver.  */
 537
 538 #define OPTION_DEFAULT_SPECS \
 539   {"arch", " %{!march=*:-march=%(VALUE)}" \
 540            " %{march=v3f:%{!mfloat-abi=*:-mfloat-abi=hard}" \
 541            " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}" \
 542            " %{!mno-ext-fpu-dp:%{!mext-fpu-dp:-mext-fpu-dp}}}" \
 543            " %{march=v3s:%{!mfloat-abi=*:-mfloat-abi=hard}" \
 544            " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}}" }, \
 545   {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }
 546
 547 #define CC1_SPEC \
 548   ""
 549
 550 #define ASM_SPEC \
 551   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 552   " %{march=*:-march=%*}" \
 553   " %{mabi=*:-mabi=v%*}" \
 554   " %{mconfig-fpu=*:-mfpu-freg=%*}" \
 555   " %{mext-fpu-mac:-mmac}" \
 556   " %{mno-ext-fpu-mac:-mno-mac}" \
 557   " %{mext-fpu-sp:-mfpu-sp-ext}" \
 558   " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \
 559   " %{mext-fpu-dp:-mfpu-dp-ext}" \
 560   " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}"
 561
 562 /* If user issues -mrelax, we need to pass '--relax' to linker.  */
 563 #define LINK_SPEC \
 564   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 565   " %{mrelax:--relax}"
 566
 567 #define LIB_SPEC \
 568   " -lc -lgloss"
 569
 570 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 571    by applying different crt stuff.  In the convention, crt0.o is the
 572    startup file without constructor/destructor;
 573    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 574    startup files with constructor/destructor.
 575    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 576    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 577    currently provided by GCC for nds32 target.
 578
 579    For nds32 target so far:
 580    If -mno-ctor-dtor, we are going to link
 581    "crt0.o [user objects]".
 582    If general cases, we are going to link
 583    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 584 #define STARTFILE_SPEC \
 585   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 586   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 587 #define ENDFILE_SPEC \
 588   " %{!mno-ctor-dtor:crtend1.o%s}"
 589
 590 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
 591    configure gcc with --target=nds32be-* setting.
 592    Check gcc/config.gcc for more information.  */
 593 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 594 #  define NDS32_ENDIAN_DEFAULT "mbig-endian"
 595 #else
 596 #  define NDS32_ENDIAN_DEFAULT "mlittle-endian"
 597 #endif
 598
 599 /* Currently we only have elf toolchain,
 600    where -mcmodel=medium is always the default.  */
 601 #define NDS32_CMODEL_DEFAULT "mcmodel=medium"
 602
 603 #define MULTILIB_DEFAULTS \
 604   { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
 605
 606 \f
 607 /* Run-time Target Specification.  */
 608
 609 #define TARGET_CPU_CPP_BUILTINS() \
 610   nds32_cpu_cpp_builtins (pfile)
 611
 612 \f
 613 /* Defining Data Structures for Per-function Information.  */
 614
 615 /* This macro is called once per function,
 616    before generation of any RTL has begun.  */
 617 #define INIT_EXPANDERS  nds32_init_expanders ()
 618
 619 \f
 620 /* Storage Layout.  */
 621
 622 #define BITS_BIG_ENDIAN 0
 623
 624 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 625
 626 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 627
 628 #define UNITS_PER_WORD 4
 629
 630 #define PROMOTE_MODE(m, unsignedp, type)                                    \
 631   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
 632     {                                                                       \
 633       (m) = SImode;                                                         \
 634     }
 635
 636 #define PARM_BOUNDARY 32
 637
 638 #define STACK_BOUNDARY 64
 639
 640 #define FUNCTION_BOUNDARY 32
 641
 642 #define BIGGEST_ALIGNMENT 64
 643
 644 #define EMPTY_FIELD_BOUNDARY 32
 645
 646 #define STRUCTURE_SIZE_BOUNDARY 8
 647
 648 #define STRICT_ALIGNMENT 1
 649
 650 #define PCC_BITFIELD_TYPE_MATTERS 1
 651
 652 \f
 653 /* Layout of Source Language Data Types.  */
 654
 655 #define INT_TYPE_SIZE           32
 656 #define SHORT_TYPE_SIZE         16
 657 #define LONG_TYPE_SIZE          32
 658 #define LONG_LONG_TYPE_SIZE     64
 659
 660 #define FLOAT_TYPE_SIZE         32
 661 #define DOUBLE_TYPE_SIZE        64
 662 #define LONG_DOUBLE_TYPE_SIZE   64
 663
 664 #define DEFAULT_SIGNED_CHAR 1
 665
 666 #define SIZE_TYPE "long unsigned int"
 667 #define PTRDIFF_TYPE "long int"
 668 #define WCHAR_TYPE "unsigned int"
 669 #define WCHAR_TYPE_SIZE 32
 670
 671 \f
 672 /* Register Usage.  */
 673
 674 /* Number of actual hardware registers.
 675    The hardware registers are assigned numbers for the compiler
 676    from 0 to just below FIRST_PSEUDO_REGISTER.
 677    All registers that the compiler knows about must be given numbers,
 678    even those that are not normally considered general registers.  */
 679 #define FIRST_PSEUDO_REGISTER 101
 680
 681 /* An initializer that says which registers are used for fixed
 682    purposes all throughout the compiled code and are therefore
 683    not available for general allocation.
 684
 685    $r28 : $fp
 686    $r29 : $gp
 687    $r30 : $lp
 688    $r31 : $sp
 689
 690    caller-save registers: $r0 ~ $r5, $r16 ~ $r23, $fs0 ~ $fs5, $fs22 ~ $fs47
 691    callee-save registers: $r6 ~ $r10, $r11 ~ $r14, $fs6 ~ $fs21, $fs48 ~ $fs63
 692
 693    reserved for assembler : $r15
 694    reserved for other use : $r24, $r25, $r26, $r27 */
 695 #define FIXED_REGISTERS \
 696 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 697       0,   0,   0,   0,   0,   0,   0,   0,     \
 698   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 699       0,   0,   0,   0,   0,   0,   0,   1,     \
 700   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 701       0,   0,   0,   0,   0,   0,   0,   0,     \
 702   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 703       1,   1,   1,   1,   0,   1,   0,   1,     \
 704   /* AP   FP   fs0  fs1  fs2  fs3  fs4  fs5  */ \
 705       1,   1,   1,   1,   1,   1,   1,   1,     \
 706   /* fs6  fs7  fs8  fs9  fs10 fs11 fs12 fs13 */ \
 707       1,   1,   1,   1,   1,   1,   1,   1,     \
 708   /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
 709       1,   1,   1,   1,   1,   1,   1,   1,     \
 710   /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
 711       1,   1,   1,   1,   1,   1,   1,   1,     \
 712   /* fs30 fs31 fd16      fd17      fd18      */ \
 713       1,   1,   1,   1,   1,   1,   1,   1,     \
 714   /* fd19      fd20      fd21      fd22      */ \
 715       1,   1,   1,   1,   1,   1,   1,   1,     \
 716   /* fd23      fd24      fd25      fd26      */ \
 717       1,   1,   1,   1,   1,   1,   1,   1,     \
 718   /* fd27      fd28      fd29      fd30      */ \
 719       1,   1,   1,   1,   1,   1,   1,   1,     \
 720   /* fd31      Reserved..................... */ \
 721       1,   1,   1,   1,   1                     \
 722 }
 723
 724 /* Identifies the registers that are not available for
 725    general allocation of values that must live across
 726    function calls -- so they are caller-save registers.
 727
 728    0 : callee-save registers
 729    1 : caller-save registers */
 730 #define CALL_USED_REGISTERS \
 731 { /* r0   r1   r2   r3   r4   r5   r6   r7   */ \
 732       1,   1,   1,   1,   1,   1,   0,   0,     \
 733   /* r8   r9   r10  r11  r12  r13  r14  r15  */ \
 734       0,   0,   0,   0,   0,   0,   0,   1,     \
 735   /* r16  r17  r18  r19  r20  r21  r22  r23  */ \
 736       1,   1,   1,   1,   1,   1,   1,   1,     \
 737   /* r24  r25  r26  r27  r28  r29  r30  r31  */ \
 738       1,   1,   1,   1,   0,   1,   0,   1,     \
 739   /* AP   FP   fs0  fs1  fs2  fs3  fs4  fs5  */ \
 740       1,   1,   1,   1,   1,   1,   1,   1,     \
 741   /* fs6  fs7  fs8  fs9  fs10 fs11 fs12 fs13 */ \
 742       1,   1,   1,   1,   1,   1,   1,   1,     \
 743   /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
 744       1,   1,   1,   1,   1,   1,   1,   1,     \
 745   /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
 746       1,   1,   1,   1,   1,   1,   1,   1,     \
 747   /* fs30 fs31 fd16      fd17      fd18      */ \
 748       1,   1,   1,   1,   1,   1,   1,   1,     \
 749   /* fd19      fd20      fd21      fd22      */ \
 750       1,   1,   1,   1,   1,   1,   1,   1,     \
 751   /* fd23      fd24      fd25      fd26      */ \
 752       1,   1,   1,   1,   1,   1,   1,   1,     \
 753   /* fd27      fd28      fd29      fd30      */ \
 754       1,   1,   1,   1,   1,   1,   1,   1,     \
 755   /* fd31      Reserved..................... */ \
 756       1,   1,   1,   1,   1                     \
 757 }
 758
 759 /* In nds32 target, we have three levels of registers:
 760      LOW_COST_REGS    : $r0 ~ $r7
 761      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
 762      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
 763 #define REG_ALLOC_ORDER \
 764 {   0,   1,   2,   3,   4,   5,   6,   7, \
 765    16,  17,  18,  19,   9,  10,  11,  12, \
 766    13,  14,  8,   15,  20,  21,  22,  23, \
 767    24,  25,  26,  27,  28,  29,  30,  31, \
 768    32,  33,  34,  35,  36,  37,  38,  39, \
 769    40,  41,  42,  43,  44,  45,  46,  47, \
 770    48,  49,  50,  51,  52,  53,  54,  55, \
 771    56,  57,  58,  59,  60,  61,  62,  63, \
 772    64,  65,  66,  67,  68,  69,  70,  71, \
 773    72,  73,  74,  75,  76,  77,  78,  79, \
 774    80,  81,  82,  83,  84,  85,  86,  87, \
 775    88,  89,  90,  91,  92,  93,  94,  95, \
 776    96,  97,  98,  99, 100,                \
 777 }
 778
 779 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
 780    to be rearranged based on optimizing for speed or size.  */
 781 #define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order ()
 782
 783 /* Tell IRA to use the order we define rather than messing it up with its
 784    own cost calculations.  */
 785 #define HONOR_REG_ALLOC_ORDER optimize_size
 786
 787 \f
 788 /* Register Classes.  */
 789
 790 /* In nds32 target, we have three levels of registers:
 791      Low cost regsiters    : $r0 ~ $r7
 792      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
 793      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
 794
 795    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
 796    so that it provides more chance to use low cost registers.  */
 797 enum reg_class
 798 {
 799   NO_REGS,
 800   R5_REG,
 801   R8_REG,
 802   R15_TA_REG,
 803   STACK_REG,
 804   FRAME_POINTER_REG,
 805   LOW_REGS,
 806   MIDDLE_REGS,
 807   HIGH_REGS,
 808   GENERAL_REGS,
 809   FRAME_REGS,
 810   FP_REGS,
 811   ALL_REGS,
 812   LIM_REG_CLASSES
 813 };
 814
 815 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 816
 817 #define REG_CLASS_NAMES \
 818 {                       \
 819   "NO_REGS",            \
 820   "R5_REG",             \
 821   "R8_REG",             \
 822   "R15_TA_REG",         \
 823   "STACK_REG",          \
 824   "FRAME_POINTER_REG",  \
 825   "LOW_REGS",           \
 826   "MIDDLE_REGS",        \
 827   "HIGH_REGS",          \
 828   "GENERAL_REGS",       \
 829   "FRAME_REGS",         \
 830   "FP_REGS",            \
 831   "ALL_REGS"            \
 832 }
 833
 834 #define REG_CLASS_CONTENTS \
 835 { /* NO_REGS                                    */  \
 836   {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
 837   /* R5_REG              : 5                    */  \
 838   {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
 839   /* R8_REG              : 8                    */  \
 840   {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
 841   /* R15_TA_REG          : 15                   */  \
 842   {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
 843   /* STACK_REG           : 31                   */  \
 844   {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
 845   /* FRAME_POINTER_REG   : 28                   */  \
 846   {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
 847   /* LOW_REGS            : 0-7                  */  \
 848   {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
 849   /* MIDDLE_REGS         : 0-11, 16-19          */  \
 850   {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
 851   /* HIGH_REGS           : 12-14, 20-31         */  \
 852   {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
 853   /* GENERAL_REGS        : 0-31                 */  \
 854   {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
 855   /* FRAME_REGS          : 32, 33               */  \
 856   {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
 857   /* FP_REGS             : 34-98                */  \
 858   {0x00000000, 0xfffffffc, 0xffffffff, 0x00000003}, \
 859   /* ALL_REGS            : 0-100                */  \
 860   {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f}  \
 861 }
 862
 863 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
 864
 865 #define BASE_REG_CLASS GENERAL_REGS
 866 #define INDEX_REG_CLASS GENERAL_REGS
 867
 868 #define TEST_REGNO(R, TEST, VALUE) \
 869   ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
 870
 871 /* Return nonzero if it is suitable for use as a
 872    base register in operand addresses.
 873    So far, we return nonzero only if "num" is a hard reg
 874    of the suitable class or a pseudo register which is
 875    allocated to a suitable hard reg.  */
 876 #define REGNO_OK_FOR_BASE_P(num) \
 877   (TEST_REGNO (num, <, 32) \
 878    || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
 879    || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
 880
 881 /* Return nonzero if it is suitable for use as a
 882    index register in operand addresses.
 883    So far, we return nonzero only if "num" is a hard reg
 884    of the suitable class or a pseudo register which is
 885    allocated to a suitable hard reg.
 886    The difference between an index register and a base register is that
 887    the index register may be scaled.  */
 888 #define REGNO_OK_FOR_INDEX_P(num) \
 889   (TEST_REGNO (num, <, 32) \
 890    || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
 891    || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
 892
 893 \f
 894 /* Obsolete Macros for Defining Constraints.  */
 895
 896 \f
 897 /* Stack Layout and Calling Conventions.  */
 898
 899 #define STACK_GROWS_DOWNWARD 1
 900
 901 #define FRAME_GROWS_DOWNWARD 1
 902
 903 #define STACK_POINTER_OFFSET 0
 904
 905 #define FIRST_PARM_OFFSET(fundecl) \
 906   (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
 907
 908 #define RETURN_ADDR_RTX(count, frameaddr) \
 909   nds32_return_addr_rtx (count, frameaddr)
 910
 911 /* A C expression whose value is RTL representing the location
 912    of the incoming return address at the beginning of any function
 913    before the prologue.
 914    If this RTL is REG, you should also define
 915    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
 916 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
 917 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
 918
 919 #define DBX_REGISTER_NUMBER(REGNO) nds32_dbx_register_number (REGNO)
 920
 921 #define STACK_POINTER_REGNUM SP_REGNUM
 922
 923 #define FRAME_POINTER_REGNUM 33
 924
 925 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
 926
 927 #define ARG_POINTER_REGNUM 32
 928
 929 #define STATIC_CHAIN_REGNUM 16
 930
 931 #define ELIMINABLE_REGS                                \
 932 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
 933   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
 934   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
 935   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
 936
 937 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
 938   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
 939
 940 #define ACCUMULATE_OUTGOING_ARGS 1
 941
 942 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
 943
 944 #define CUMULATIVE_ARGS nds32_cumulative_args
 945
 946 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
 947   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
 948
 949 #define FUNCTION_ARG_REGNO_P(regno)                                           \
 950  (IN_RANGE ((regno), NDS32_FIRST_GPR_REGNUM, NDS32_MAX_GPR_REGS_FOR_ARGS - 1) \
 951   || ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)                                \
 952       && IN_RANGE ((regno), NDS32_FPR_ARG_FIRST_REGNUM,                       \
 953                    NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS - 1)))
 954
 955 #define DEFAULT_PCC_STRUCT_RETURN 0
 956
 957 /* EXIT_IGNORE_STACK should be nonzero if, when returning
 958    from a function, the stack pointer does not matter.
 959    The value is tested only in functions that have frame pointers.
 960    In nds32 target, the function epilogue recovers the
 961    stack pointer from the frame.  */
 962 #define EXIT_IGNORE_STACK 1
 963
 964 #define FUNCTION_PROFILER(file, labelno) \
 965   fprintf (file, "/* profiler %d */\n", (labelno))
 966
 967 #define PROFILE_HOOK(LABEL)                                             \
 968   {                                                                     \
 969     rtx fun, lp;                                                        \
 970     lp = get_hard_reg_initial_val (Pmode, LP_REGNUM);                   \
 971     fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount");                        \
 972     emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode);           \
 973   }
 974
 975 \f
 976 /* Implementing the Varargs Macros.  */
 977
 978 \f
 979 /* Trampolines for Nested Functions.  */
 980
 981 /* Giving A-function and B-function,
 982    if B-function wants to call A-function's nested function,
 983    we need to fill trampoline code into A-function's stack
 984    so that B-function can execute the code in stack to indirectly
 985    jump to (like 'trampoline' action) desired nested function.
 986
 987    The trampoline code for nds32 target must contains following parts:
 988
 989      1. instructions (4 * 4 = 16 bytes):
 990           get $pc first
 991           load chain_value to static chain register via $pc
 992           load nested function address to $r15 via $pc
 993           jump to desired nested function via $r15
 994      2. data (4 * 2 = 8 bytes):
 995           chain_value
 996           nested function address
 997
 998    Please check nds32.c implementation for more information.  */
 999 #define TRAMPOLINE_SIZE 24
1000
1001 /* Because all instructions/data in trampoline template are 4-byte size,
1002    we set trampoline alignment 8*4=32 bits.  */
1003 #define TRAMPOLINE_ALIGNMENT 32
1004
1005 \f
1006 /* Implicit Calls to Library Routines.  */
1007
1008 \f
1009 /* Addressing Modes.  */
1010
1011 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
1012 #define HAVE_POST_INCREMENT 1
1013 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
1014 #define HAVE_POST_DECREMENT 1
1015
1016 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
1017 #define HAVE_POST_MODIFY_DISP 1
1018 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
1019 #define HAVE_POST_MODIFY_REG  1
1020
1021 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
1022
1023 #define MAX_REGS_PER_ADDRESS 3
1024
1025 \f
1026 /* Anchored Addresses.  */
1027
1028 \f
1029 /* Condition Code Status.  */
1030
1031 \f
1032 /* Describing Relative Costs of Operations.  */
1033
1034 /* A C expression for the cost of a branch instruction.
1035    A value of 1 is the default;
1036    other values are interpreted relative to that.  */
1037 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1)
1038
1039 /* Override BRANCH_COST heuristic which empirically produces worse
1040    performance for removing short circuiting from the logical ops.  */
1041 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1042
1043 #define SLOW_BYTE_ACCESS 1
1044
1045 #define NO_FUNCTION_CSE 1
1046
1047 \f
1048 /* Adjusting the Instruction Scheduler.  */
1049
1050 \f
1051 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
1052
1053 #define TEXT_SECTION_ASM_OP     "\t.text"
1054 #define DATA_SECTION_ASM_OP     "\t.data"
1055
1056 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
1057    So we use '.section .bss' alternatively.  */
1058 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
1059
1060 /* Define this macro to be an expression with a nonzero value if jump tables
1061    (for tablejump insns) should be output in the text section,
1062    along with the assembler instructions.
1063    Otherwise, the readonly data section is used.  */
1064 #define JUMP_TABLES_IN_TEXT_SECTION 1
1065
1066 \f
1067 /* Position Independent Code.  */
1068
1069 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
1070
1071 \f
1072 /* Defining the Output Assembler Language.  */
1073
1074 #define ASM_COMMENT_START "!"
1075
1076 #define ASM_APP_ON "! #APP"
1077
1078 #define ASM_APP_OFF "! #NO_APP\n"
1079
1080 #define ASM_OUTPUT_LABELREF(stream, name) \
1081   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
1082
1083 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
1084   assemble_name (stream, XSTR (sym, 0))
1085
1086 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
1087   assemble_name (stream, buf)
1088
1089 #define LOCAL_LABEL_PREFIX "."
1090
1091 #define REGISTER_NAMES \
1092 { "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
1093   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
1094   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
1095   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
1096   "$AP",  "$SFP", "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", \
1097   "$fs6", "$fs7", "$fs8", "$fs9", "$fs10","$fs11","$fs12","$fs13",\
1098   "$fs14","$fs15","$fs16","$fs17","$fs18","$fs19","$fs20","$fs21",\
1099   "$fs22","$fs23","$fs24","$fs25","$fs26","$fs27","$fs28","$fs29",\
1100   "$fs30","$fs31","$fs32","$fs33","$fs34","$fs35","$fs36","$fs37",\
1101   "$fs38","$fs39","$fs40","$fs41","$fs42","$fs43","$fs44","$fs45",\
1102   "$fs46","$fs47","$fs48","$fs49","$fs50","$fs51","$fs52","$fs53",\
1103   "$fs54","$fs55","$fs56","$fs57","$fs58","$fs59","$fs60","$fs61",\
1104   "$fs62","$fs63",   "LB",   "LE",   "LC"                         \
1105 }
1106
1107 #define ADDITIONAL_REGISTER_NAMES                               \
1108 {                                                               \
1109   {"$r15", 15},                                                 \
1110   {"$r28", 28}, {"$r29", 29},   {"$r30", 30},   {"$r31", 31},   \
1111   {"$a0", 0},   {"$a1", 1},     {"$a2", 2},                     \
1112   {"$a3", 3},   {"$a4", 4},     {"$a5", 5},                     \
1113   {"$s0", 6},   {"$s1", 7},     {"$s2", 8},     {"$s3", 9},     \
1114   {"$s4", 10},  {"$s5", 11},    {"$s6", 12},    {"$s7", 13},    \
1115   {"$s8", 14},                                                  \
1116   {"$t0", 16},  {"$t1", 17},    {"$t2", 18},    {"$t3", 19},    \
1117   {"$t4", 20},  {"$t5", 21},    {"$t6", 22},    {"$t7", 23},    \
1118   {"$t8", 24},  {"$t9", 25},                                    \
1119   {"$p0", 26},  {"$p1", 27},                                    \
1120   {"$h0", 0},   {"$h1", 1},     {"$h2", 2},     {"$h3", 3},     \
1121   {"$h4", 4},   {"$h5", 5},     {"$h6", 6},     {"$h7", 7},     \
1122   {"$h8", 8},   {"$h9", 9},     {"$h10", 10},   {"$h11", 11},   \
1123   {"$h12", 16}, {"$h13", 17},   {"$h14", 18},   {"$h15", 19},   \
1124   {"$o0", 0},   {"$o1", 1},     {"$o2", 2},     {"$o3", 3},     \
1125   {"$o4", 4},   {"$o5", 5},     {"$o6", 6},     {"$o7", 7},     \
1126 }
1127
1128 #define OVERLAPPING_REGISTER_NAMES              \
1129 {                                               \
1130   {"$fd0",  NDS32_FIRST_FPR_REGNUM + 0,  2},    \
1131   {"$fd1",  NDS32_FIRST_FPR_REGNUM + 2,  2},    \
1132   {"$fd2",  NDS32_FIRST_FPR_REGNUM + 4,  2},    \
1133   {"$fd3",  NDS32_FIRST_FPR_REGNUM + 6,  2},    \
1134   {"$fd4",  NDS32_FIRST_FPR_REGNUM + 8,  2},    \
1135   {"$fd5",  NDS32_FIRST_FPR_REGNUM + 10, 2},    \
1136   {"$fd6",  NDS32_FIRST_FPR_REGNUM + 12, 2},    \
1137   {"$fd7",  NDS32_FIRST_FPR_REGNUM + 14, 2},    \
1138   {"$fd8",  NDS32_FIRST_FPR_REGNUM + 16, 2},    \
1139   {"$fd9",  NDS32_FIRST_FPR_REGNUM + 18, 2},    \
1140   {"$fd10", NDS32_FIRST_FPR_REGNUM + 20, 2},    \
1141   {"$fd11", NDS32_FIRST_FPR_REGNUM + 22, 2},    \
1142   {"$fd12", NDS32_FIRST_FPR_REGNUM + 24, 2},    \
1143   {"$fd13", NDS32_FIRST_FPR_REGNUM + 26, 2},    \
1144   {"$fd14", NDS32_FIRST_FPR_REGNUM + 28, 2},    \
1145   {"$fd15", NDS32_FIRST_FPR_REGNUM + 30, 2},    \
1146   {"$fd16", NDS32_FIRST_FPR_REGNUM + 32, 2},    \
1147   {"$fd17", NDS32_FIRST_FPR_REGNUM + 34, 2},    \
1148   {"$fd18", NDS32_FIRST_FPR_REGNUM + 36, 2},    \
1149   {"$fd19", NDS32_FIRST_FPR_REGNUM + 38, 2},    \
1150   {"$fd20", NDS32_FIRST_FPR_REGNUM + 40, 2},    \
1151   {"$fd21", NDS32_FIRST_FPR_REGNUM + 42, 2},    \
1152   {"$fd22", NDS32_FIRST_FPR_REGNUM + 44, 2},    \
1153   {"$fd23", NDS32_FIRST_FPR_REGNUM + 46, 2},    \
1154   {"$fd24", NDS32_FIRST_FPR_REGNUM + 48, 2},    \
1155   {"$fd25", NDS32_FIRST_FPR_REGNUM + 50, 2},    \
1156   {"$fd26", NDS32_FIRST_FPR_REGNUM + 52, 2},    \
1157   {"$fd27", NDS32_FIRST_FPR_REGNUM + 54, 2},    \
1158   {"$fd28", NDS32_FIRST_FPR_REGNUM + 56, 2},    \
1159   {"$fd29", NDS32_FIRST_FPR_REGNUM + 58, 2},    \
1160   {"$fd30", NDS32_FIRST_FPR_REGNUM + 60, 2},    \
1161   {"$fd31", NDS32_FIRST_FPR_REGNUM + 62, 2},    \
1162 }
1163
1164 /* Output normal jump table entry.  */
1165 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
1166   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
1167
1168 /* Output pc relative jump table entry.  */
1169 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
1170   do                                                                    \
1171     {                                                                   \
1172       switch (GET_MODE (body))                                          \
1173         {                                                               \
1174         case E_QImode:                                                    \
1175           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
1176           break;                                                        \
1177         case E_HImode:                                                    \
1178           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
1179           break;                                                        \
1180         case E_SImode:                                                    \
1181           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
1182           break;                                                        \
1183         default:                                                        \
1184           gcc_unreachable();                                            \
1185         }                                                               \
1186     } while (0)
1187
1188 /* We have to undef it first because elfos.h formerly define it
1189    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
1190 #undef  ASM_OUTPUT_CASE_LABEL
1191 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
1192   do                                                               \
1193     {                                                              \
1194       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
1195       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
1196     } while (0)
1197
1198 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
1199   do                                                   \
1200     {                                                  \
1201       /* Because our jump table is in text section,    \
1202          we need to make sure 2-byte alignment after   \
1203          the jump table for instructions fetch.  */    \
1204       if (GET_MODE (PATTERN (table)) == QImode)        \
1205         ASM_OUTPUT_ALIGN (stream, 1);                  \
1206       asm_fprintf (stream, "\t! Jump Table End\n");    \
1207     }  while (0)
1208
1209 /* This macro is not documented yet.
1210    But we do need it to make jump table vector aligned.  */
1211 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
1212
1213 #define DWARF2_UNWIND_INFO 1
1214
1215 #define JUMP_ALIGN(x) \
1216   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
1217
1218 #define LOOP_ALIGN(x) \
1219   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
1220
1221 #define LABEL_ALIGN(x) \
1222   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
1223
1224 #define ASM_OUTPUT_ALIGN(stream, power) \
1225   fprintf (stream, "\t.align\t%d\n", power)
1226
1227 \f
1228 /* Controlling Debugging Information Format.  */
1229
1230 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1231
1232 #define DWARF2_DEBUGGING_INFO 1
1233
1234 #define DWARF2_ASM_LINE_DEBUG_INFO 1
1235
1236 \f
1237 /* Cross Compilation and Floating Point.  */
1238
1239 \f
1240 /* Mode Switching Instructions.  */
1241
1242 \f
1243 /* Defining target-specific uses of __attribute__.  */
1244
1245 \f
1246 /* Emulating TLS.  */
1247
1248 \f
1249 /* Defining coprocessor specifics for MIPS targets.  */
1250
1251 \f
1252 /* Parameters for Precompiled Header Validity Checking.  */
1253
1254 \f
1255 /* C++ ABI parameters.  */
1256
1257 \f
1258 /* Adding support for named address spaces.  */
1259
1260 \f
1261 /* Miscellaneous Parameters.  */
1262
1263 /* This is the machine mode that elements of a jump-table should have.  */
1264 #define CASE_VECTOR_MODE Pmode
1265
1266 /* Return the preferred mode for and addr_diff_vec when the mininum
1267    and maximum offset are known.  */
1268 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
1269    ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
1270    : (max_offset >= 100) ? HImode                               \
1271    : QImode)
1272
1273 /* Generate pc relative jump table when -fpic or -Os.  */
1274 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1275
1276 /* Define this macro if operations between registers with integral mode
1277    smaller than a word are always performed on the entire register.  */
1278 #define WORD_REGISTER_OPERATIONS 1
1279
1280 /* A C expression indicating when insns that read memory in mem_mode,
1281    an integral mode narrower than a word, set the bits outside of mem_mode
1282    to be either the sign-extension or the zero-extension of the data read.  */
1283 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1284
1285 /* The maximum number of bytes that a single instruction can move quickly
1286    between memory and registers or between two memory locations.  */
1287 #define MOVE_MAX 4
1288
1289 /* A C expression that is nonzero if on this machine the number of bits
1290    actually used for the count of a shift operation is equal to the number
1291    of bits needed to represent the size of the object being shifted.  */
1292 #define SHIFT_COUNT_TRUNCATED 1
1293
1294 /* A C expression describing the value returned by a comparison operator with
1295    an integral mode and stored by a store-flag instruction ('cstoremode4')
1296    when the condition is true.  */
1297 #define STORE_FLAG_VALUE 1
1298
1299 /* A C expression that indicates whether the architecture defines a value for
1300    clz or ctz with a zero operand.  In nds32 clz for 0 result 32 is defined
1301    in ISA spec */
1302 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
1303
1304 /* An alias for the machine mode for pointers.  */
1305 #define Pmode SImode
1306
1307 /* An alias for the machine mode used for memory references to functions
1308    being called, in call RTL expressions.  */
1309 #define FUNCTION_MODE SImode
1310
1311 /* ------------------------------------------------------------------------ */