1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here cannot be reallocated by global.c if the hard
59 register is used as a spill register. So we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
70 #include "insn-attr.h"
74 /* Next quantity number available for allocation. */
78 /* In all the following vectors indexed by quantity number. */
80 /* Element Q is the hard reg number chosen for quantity Q,
81 or -1 if none was found. */
83 static short *qty_phys_reg
;
85 /* We maintain two hard register sets that indicate suggested hard registers
86 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
87 that are tied to the quantity by a simple copy. The second contains all
88 hard registers that are tied to the quantity via an arithmetic operation.
90 The former register set is given priority for allocation. This tends to
91 eliminate copy insns. */
93 /* Element Q is a set of hard registers that are suggested for quantity Q by
96 static HARD_REG_SET
*qty_phys_copy_sugg
;
98 /* Element Q is a set of hard registers that are suggested for quantity Q by
101 static HARD_REG_SET
*qty_phys_sugg
;
103 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
105 static short *qty_phys_num_copy_sugg
;
107 /* Element Q is the number of suggested registers in qty_phys_sugg. */
109 static short *qty_phys_num_sugg
;
111 /* Element Q is the number of refs to quantity Q. */
113 static int *qty_n_refs
;
115 /* Element Q is a reg class contained in (smaller than) the
116 preferred classes of all the pseudo regs that are tied in quantity Q.
117 This is the preferred class for allocating that quantity. */
119 static enum reg_class
*qty_min_class
;
121 /* Insn number (counting from head of basic block)
122 where quantity Q was born. -1 if birth has not been recorded. */
124 static int *qty_birth
;
126 /* Insn number (counting from head of basic block)
127 where quantity Q died. Due to the way tying is done,
128 and the fact that we consider in this pass only regs that die but once,
129 a quantity can die only once. Each quantity's life span
130 is a set of consecutive insns. -1 if death has not been recorded. */
132 static int *qty_death
;
134 /* Number of words needed to hold the data in quantity Q.
135 This depends on its machine mode. It is used for these purposes:
136 1. It is used in computing the relative importances of qtys,
137 which determines the order in which we look for regs for them.
138 2. It is used in rules that prevent tying several registers of
139 different sizes in a way that is geometrically impossible
140 (see combine_regs). */
142 static int *qty_size
;
144 /* This holds the mode of the registers that are tied to qty Q,
145 or VOIDmode if registers with differing modes are tied together. */
147 static enum machine_mode
*qty_mode
;
149 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
151 static int *qty_n_calls_crossed
;
153 /* Register class within which we allocate qty Q if we can't get
154 its preferred class. */
156 static enum reg_class
*qty_alternate_class
;
158 /* Element Q is the SCRATCH expression for which this quantity is being
159 allocated or 0 if this quantity is allocating registers. */
161 static rtx
*qty_scratch_rtx
;
163 /* Element Q is nonzero if this quantity has been used in a SUBREG
164 that changes its size. */
166 static char *qty_changes_size
;
168 /* Element Q is the register number of one pseudo register whose
169 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
170 register should be the head of the chain maintained in reg_next_in_qty. */
172 static int *qty_first_reg
;
174 /* If (REG N) has been assigned a quantity number, is a register number
175 of another register assigned the same quantity number, or -1 for the
176 end of the chain. qty_first_reg point to the head of this chain. */
178 static int *reg_next_in_qty
;
180 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
182 of -1 if this register cannot be allocated by local-alloc,
183 or -2 if not known yet.
185 Note that if we see a use or death of pseudo register N with
186 reg_qty[N] == -2, register N must be local to the current block. If
187 it were used in more than one block, we would have reg_qty[N] == -1.
188 This relies on the fact that if reg_basic_block[N] is >= 0, register N
189 will not appear in any other block. We save a considerable number of
190 tests by exploiting this.
192 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
197 /* The offset (in words) of register N within its quantity.
198 This can be nonzero if register N is SImode, and has been tied
199 to a subreg of a DImode register. */
201 static char *reg_offset
;
203 /* Vector of substitutions of register numbers,
204 used to map pseudo regs into hardware regs.
205 This is set up as a result of register allocation.
206 Element N is the hard reg assigned to pseudo reg N,
207 or is -1 if no hard reg was assigned.
208 If N is a hard reg number, element N is N. */
212 /* Set of hard registers live at the current point in the scan
213 of the instructions in a basic block. */
215 static HARD_REG_SET regs_live
;
217 /* Each set of hard registers indicates registers live at a particular
218 point in the basic block. For N even, regs_live_at[N] says which
219 hard registers are needed *after* insn N/2 (i.e., they may not
220 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
222 If an object is to conflict with the inputs of insn J but not the
223 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
224 if it is to conflict with the outputs of insn J but not the inputs of
225 insn J + 1, it is said to die at index J*2 + 1. */
227 static HARD_REG_SET
*regs_live_at
;
231 int scratch_list_length
;
232 static int scratch_index
;
234 /* Communicate local vars `insn_number' and `insn'
235 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
236 static int this_insn_number
;
237 static rtx this_insn
;
239 /* Used to communicate changes made by update_equiv_regs to
240 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
241 found or created, so that we can keep track of what memory accesses might
242 be created later, e.g. by reload. */
244 static rtx
*reg_equiv_replacement
;
246 static void alloc_qty
PROTO((int, enum machine_mode
, int, int));
247 static void alloc_qty_for_scratch
PROTO((rtx
, int, rtx
, int, int));
248 static void validate_equiv_mem_from_store
PROTO((rtx
, rtx
));
249 static int validate_equiv_mem
PROTO((rtx
, rtx
, rtx
));
250 static int contains_replace_regs
PROTO((rtx
, char *));
251 static int memref_referenced_p
PROTO((rtx
, rtx
));
252 static int memref_used_between_p
PROTO((rtx
, rtx
, rtx
));
253 static void update_equiv_regs
PROTO((void));
254 static void block_alloc
PROTO((int));
255 static int qty_sugg_compare
PROTO((int, int));
256 static int qty_sugg_compare_1
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
257 static int qty_compare
PROTO((int, int));
258 static int qty_compare_1
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
259 static int combine_regs
PROTO((rtx
, rtx
, int, int, rtx
, int));
260 static int reg_meets_class_p
PROTO((int, enum reg_class
));
261 static void update_qty_class
PROTO((int, int));
262 static void reg_is_set
PROTO((rtx
, rtx
));
263 static void reg_is_born
PROTO((rtx
, int));
264 static void wipe_dead_reg
PROTO((rtx
, int));
265 static int find_free_reg
PROTO((enum reg_class
, enum machine_mode
,
266 int, int, int, int, int));
267 static void mark_life
PROTO((int, enum machine_mode
, int));
268 static void post_mark_life
PROTO((int, enum machine_mode
, int, int, int));
269 static int no_conflict_p
PROTO((rtx
, rtx
, rtx
));
270 static int requires_inout
PROTO((char *));
272 /* Allocate a new quantity (new within current basic block)
273 for register number REGNO which is born at index BIRTH
274 within the block. MODE and SIZE are info on reg REGNO. */
277 alloc_qty (regno
, mode
, size
, birth
)
279 enum machine_mode mode
;
282 register int qty
= next_qty
++;
284 reg_qty
[regno
] = qty
;
285 reg_offset
[regno
] = 0;
286 reg_next_in_qty
[regno
] = -1;
288 qty_first_reg
[qty
] = regno
;
289 qty_size
[qty
] = size
;
290 qty_mode
[qty
] = mode
;
291 qty_birth
[qty
] = birth
;
292 qty_n_calls_crossed
[qty
] = REG_N_CALLS_CROSSED (regno
);
293 qty_min_class
[qty
] = reg_preferred_class (regno
);
294 qty_alternate_class
[qty
] = reg_alternate_class (regno
);
295 qty_n_refs
[qty
] = REG_N_REFS (regno
);
296 qty_changes_size
[qty
] = REG_CHANGES_SIZE (regno
);
299 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
300 used as operand N in INSN. We assume here that the SCRATCH is used in
304 alloc_qty_for_scratch (scratch
, n
, insn
, insn_code_num
, insn_number
)
308 int insn_code_num
, insn_number
;
311 enum reg_class
class;
315 #ifdef REGISTER_CONSTRAINTS
316 /* If we haven't yet computed which alternative will be used, do so now.
317 Then set P to the constraints for that alternative. */
318 if (which_alternative
== -1)
319 if (! constrain_operands (insn_code_num
, 0))
322 for (p
= insn_operand_constraint
[insn_code_num
][n
], i
= 0;
323 *p
&& i
< which_alternative
; p
++)
327 /* Compute the class required for this SCRATCH. If we don't need a
328 register, the class will remain NO_REGS. If we guessed the alternative
329 number incorrectly, reload will fix things up for us. */
332 while ((c
= *p
++) != '\0' && c
!= ',')
335 case '=': case '+': case '?':
336 case '#': case '&': case '!':
338 case '0': case '1': case '2': case '3': case '4':
339 case 'm': case '<': case '>': case 'V': case 'o':
340 case 'E': case 'F': case 'G': case 'H':
341 case 's': case 'i': case 'n':
342 case 'I': case 'J': case 'K': case 'L':
343 case 'M': case 'N': case 'O': case 'P':
344 #ifdef EXTRA_CONSTRAINT
345 case 'Q': case 'R': case 'S': case 'T': case 'U':
348 /* These don't say anything we care about. */
352 /* We don't need to allocate this SCRATCH. */
356 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
361 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER (c
)];
365 if (class == NO_REGS
)
368 #else /* REGISTER_CONSTRAINTS */
370 class = GENERAL_REGS
;
376 qty_first_reg
[qty
] = -1;
377 qty_scratch_rtx
[qty
] = scratch
;
378 qty_size
[qty
] = GET_MODE_SIZE (GET_MODE (scratch
));
379 qty_mode
[qty
] = GET_MODE (scratch
);
380 qty_birth
[qty
] = 2 * insn_number
- 1;
381 qty_death
[qty
] = 2 * insn_number
+ 1;
382 qty_n_calls_crossed
[qty
] = 0;
383 qty_min_class
[qty
] = class;
384 qty_alternate_class
[qty
] = NO_REGS
;
386 qty_changes_size
[qty
] = 0;
389 /* Main entry point of this file. */
397 /* Leaf functions and non-leaf functions have different needs.
398 If defined, let the machine say what kind of ordering we
400 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
401 ORDER_REGS_FOR_LOCAL_ALLOC
;
404 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
406 update_equiv_regs ();
408 /* This sets the maximum number of quantities we can have. Quantity
409 numbers start at zero and we can have one for each pseudo plus the
410 number of SCRATCHes in the largest block, in the worst case. */
411 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
) + max_scratch
;
413 /* Allocate vectors of temporary data.
414 See the declarations of these variables, above,
415 for what they mean. */
417 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
418 Instead of allocating this much memory from now until the end of
419 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
420 reload will allocate them. */
422 scratch_list_length
= max_qty
;
423 scratch_list
= (rtx
*) xmalloc (scratch_list_length
* sizeof (rtx
));
424 bzero ((char *) scratch_list
, scratch_list_length
* sizeof (rtx
));
425 scratch_block
= (int *) xmalloc (scratch_list_length
* sizeof (int));
426 bzero ((char *) scratch_block
, scratch_list_length
* sizeof (int));
429 qty_phys_reg
= (short *) alloca (max_qty
* sizeof (short));
431 = (HARD_REG_SET
*) alloca (max_qty
* sizeof (HARD_REG_SET
));
432 qty_phys_num_copy_sugg
= (short *) alloca (max_qty
* sizeof (short));
433 qty_phys_sugg
= (HARD_REG_SET
*) alloca (max_qty
* sizeof (HARD_REG_SET
));
434 qty_phys_num_sugg
= (short *) alloca (max_qty
* sizeof (short));
435 qty_birth
= (int *) alloca (max_qty
* sizeof (int));
436 qty_death
= (int *) alloca (max_qty
* sizeof (int));
437 qty_scratch_rtx
= (rtx
*) alloca (max_qty
* sizeof (rtx
));
438 qty_first_reg
= (int *) alloca (max_qty
* sizeof (int));
439 qty_size
= (int *) alloca (max_qty
* sizeof (int));
441 = (enum machine_mode
*) alloca (max_qty
* sizeof (enum machine_mode
));
442 qty_n_calls_crossed
= (int *) alloca (max_qty
* sizeof (int));
444 = (enum reg_class
*) alloca (max_qty
* sizeof (enum reg_class
));
446 = (enum reg_class
*) alloca (max_qty
* sizeof (enum reg_class
));
447 qty_n_refs
= (int *) alloca (max_qty
* sizeof (int));
448 qty_changes_size
= (char *) alloca (max_qty
* sizeof (char));
450 reg_qty
= (int *) alloca (max_regno
* sizeof (int));
451 reg_offset
= (char *) alloca (max_regno
* sizeof (char));
452 reg_next_in_qty
= (int *) alloca (max_regno
* sizeof (int));
454 /* Allocate the reg_renumber array */
455 allocate_reg_info (max_regno
, FALSE
, TRUE
);
457 /* Determine which pseudo-registers can be allocated by local-alloc.
458 In general, these are the registers used only in a single block and
459 which only die once. However, if a register's preferred class has only
460 a few entries, don't allocate this register here unless it is preferred
461 or nothing since retry_global_alloc won't be able to move it to
462 GENERAL_REGS if a reload register of this class is needed.
464 We need not be concerned with which block actually uses the register
465 since we will never see it outside that block. */
467 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
469 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1
470 && (reg_alternate_class (i
) == NO_REGS
471 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i
))))
477 /* Force loop below to initialize entire quantity array. */
480 /* Allocate each block's local registers, block by block. */
482 for (b
= 0; b
< n_basic_blocks
; b
++)
484 /* NEXT_QTY indicates which elements of the `qty_...'
485 vectors might need to be initialized because they were used
486 for the previous block; it is set to the entire array before
487 block 0. Initialize those, with explicit loop if there are few,
488 else with bzero and bcopy. Do not initialize vectors that are
489 explicit set by `alloc_qty'. */
493 for (i
= 0; i
< next_qty
; i
++)
495 qty_scratch_rtx
[i
] = 0;
496 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
497 qty_phys_num_copy_sugg
[i
] = 0;
498 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
499 qty_phys_num_sugg
[i
] = 0;
504 #define CLEAR(vector) \
505 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
507 CLEAR (qty_scratch_rtx
);
508 CLEAR (qty_phys_copy_sugg
);
509 CLEAR (qty_phys_num_copy_sugg
);
510 CLEAR (qty_phys_sugg
);
511 CLEAR (qty_phys_num_sugg
);
523 /* Depth of loops we are in while in update_equiv_regs. */
524 static int loop_depth
;
526 /* Used for communication between the following two functions: contains
527 a MEM that we wish to ensure remains unchanged. */
528 static rtx equiv_mem
;
530 /* Set nonzero if EQUIV_MEM is modified. */
531 static int equiv_mem_modified
;
533 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
534 Called via note_stores. */
537 validate_equiv_mem_from_store (dest
, set
)
541 if ((GET_CODE (dest
) == REG
542 && reg_overlap_mentioned_p (dest
, equiv_mem
))
543 || (GET_CODE (dest
) == MEM
544 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
545 equiv_mem_modified
= 1;
548 /* Verify that no store between START and the death of REG invalidates
549 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
550 by storing into an overlapping memory location, or with a non-const
553 Return 1 if MEMREF remains valid. */
556 validate_equiv_mem (start
, reg
, memref
)
565 equiv_mem_modified
= 0;
567 /* If the memory reference has side effects or is volatile, it isn't a
568 valid equivalence. */
569 if (side_effects_p (memref
))
572 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
574 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
577 if (find_reg_note (insn
, REG_DEAD
, reg
))
580 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
581 && ! CONST_CALL_P (insn
))
584 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
);
586 /* If a register mentioned in MEMREF is modified via an
587 auto-increment, we lose the equivalence. Do the same if one
588 dies; although we could extend the life, it doesn't seem worth
591 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
592 if ((REG_NOTE_KIND (note
) == REG_INC
593 || REG_NOTE_KIND (note
) == REG_DEAD
)
594 && GET_CODE (XEXP (note
, 0)) == REG
595 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
602 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
605 contains_replace_regs (x
, reg_equiv_replace
)
607 char *reg_equiv_replace
;
611 enum rtx_code code
= GET_CODE (x
);
627 return reg_equiv_replace
[REGNO (x
)];
633 fmt
= GET_RTX_FORMAT (code
);
634 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
638 if (contains_replace_regs (XEXP (x
, i
), reg_equiv_replace
))
642 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
643 if (contains_replace_regs (XVECEXP (x
, i
, j
), reg_equiv_replace
))
651 /* TRUE if X references a memory location that would be affected by a store
655 memref_referenced_p (memref
, x
)
661 enum rtx_code code
= GET_CODE (x
);
677 return (reg_equiv_replacement
[REGNO (x
)]
678 && memref_referenced_p (memref
,
679 reg_equiv_replacement
[REGNO (x
)]));
682 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
687 /* If we are setting a MEM, it doesn't count (its address does), but any
688 other SET_DEST that has a MEM in it is referencing the MEM. */
689 if (GET_CODE (SET_DEST (x
)) == MEM
)
691 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
694 else if (memref_referenced_p (memref
, SET_DEST (x
)))
697 return memref_referenced_p (memref
, SET_SRC (x
));
703 fmt
= GET_RTX_FORMAT (code
);
704 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
708 if (memref_referenced_p (memref
, XEXP (x
, i
)))
712 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
713 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
721 /* TRUE if some insn in the range (START, END] references a memory location
722 that would be affected by a store to MEMREF. */
725 memref_used_between_p (memref
, start
, end
)
732 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
733 insn
= NEXT_INSN (insn
))
734 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
735 && memref_referenced_p (memref
, PATTERN (insn
)))
741 /* Find registers that are equivalent to a single value throughout the
742 compilation (either because they can be referenced in memory or are set once
743 from a single constant). Lower their priority for a register.
745 If such a register is only referenced once, try substituting its value
746 into the using insn. If it succeeds, we can eliminate the register
752 rtx
*reg_equiv_init_insn
= (rtx
*) alloca (max_regno
* sizeof (rtx
*));
753 /* Set when an attempt should be made to replace a register with the
754 associated reg_equiv_replacement entry at the end of this function. */
755 char *reg_equiv_replace
756 = (char *) alloca (max_regno
* sizeof *reg_equiv_replace
);
760 reg_equiv_replacement
= (rtx
*) alloca (max_regno
* sizeof (rtx
*));
762 bzero ((char *) reg_equiv_init_insn
, max_regno
* sizeof (rtx
*));
763 bzero ((char *) reg_equiv_replacement
, max_regno
* sizeof (rtx
*));
764 bzero ((char *) reg_equiv_replace
, max_regno
* sizeof *reg_equiv_replace
);
766 init_alias_analysis ();
770 /* Scan the insns and find which registers have equivalences. Do this
771 in a separate scan of the insns because (due to -fcse-follow-jumps)
772 a register can be set below its use. */
773 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
776 rtx set
= single_set (insn
);
780 if (GET_CODE (insn
) == NOTE
)
782 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
784 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
788 /* If this insn contains more (or less) than a single SET, ignore it. */
792 dest
= SET_DEST (set
);
795 /* If this sets a MEM to the contents of a REG that is only used
796 in a single basic block, see if the register is always equivalent
797 to that memory location and if moving the store from INSN to the
798 insn that set REG is safe. If so, put a REG_EQUIV note on the
801 Don't add a REG_EQUIV note if the insn already has one. The existing
802 REG_EQUIV is likely more useful than the one we are adding.
804 If one of the regs in the address is marked as reg_equiv_replace,
805 then we can't add this REG_EQUIV note. The reg_equiv_replace
806 optimization may move the set of this register immediately before
807 insn, which puts it after reg_equiv_init_insn[regno], and hence
808 the mention in the REG_EQUIV note would be to an uninitialized
811 if (GET_CODE (dest
) == MEM
&& GET_CODE (SET_SRC (set
)) == REG
812 && (regno
= REGNO (SET_SRC (set
))) >= FIRST_PSEUDO_REGISTER
813 && REG_BASIC_BLOCK (regno
) >= 0
814 && reg_equiv_init_insn
[regno
] != 0
815 && ! find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)
816 && ! contains_replace_regs (XEXP (dest
, 0), reg_equiv_replace
)
817 && validate_equiv_mem (reg_equiv_init_insn
[regno
], SET_SRC (set
),
819 && ! memref_used_between_p (SET_DEST (set
),
820 reg_equiv_init_insn
[regno
], insn
))
821 REG_NOTES (reg_equiv_init_insn
[regno
])
822 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
,
823 REG_NOTES (reg_equiv_init_insn
[regno
]));
825 /* We only handle the case of a pseudo register being set
826 once and only if neither the source nor the destination are
827 in a register class that's likely to be spilled. */
828 if (GET_CODE (dest
) != REG
829 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
830 || REG_N_SETS (regno
) != 1
831 || CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (dest
)))
832 || (GET_CODE (src
) == REG
833 && REGNO (src
) >= FIRST_PSEUDO_REGISTER
834 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src
)))))
837 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
839 #ifdef DONT_RECORD_EQUIVALENCE
840 /* Allow the target to reject promotions of some REG_EQUAL notes to
843 In some cases this can improve register allocation if the existence
844 of the REG_EQUIV note is likely to increase the lifetime of a register
845 that is likely to be spilled.
847 It may also be necessary if the target can't handle certain constant
848 expressions appearing randomly in insns, but for whatever reason
849 those expressions must be considered legitimate constant expressions
850 to prevent them from being forced into memory. */
851 if (note
&& DONT_RECORD_EQUIVALENCE (note
))
855 /* Record this insn as initializing this register. */
856 reg_equiv_init_insn
[regno
] = insn
;
858 /* If this register is known to be equal to a constant, record that
859 it is always equivalent to the constant. */
860 if (note
&& CONSTANT_P (XEXP (note
, 0)))
861 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
863 /* If this insn introduces a "constant" register, decrease the priority
864 of that register. Record this insn if the register is only used once
865 more and the equivalence value is the same as our source.
867 The latter condition is checked for two reasons: First, it is an
868 indication that it may be more efficient to actually emit the insn
869 as written (if no registers are available, reload will substitute
870 the equivalence). Secondly, it avoids problems with any registers
871 dying in this insn whose death notes would be missed.
873 If we don't have a REG_EQUIV note, see if this insn is loading
874 a register used only in one basic block from a MEM. If so, and the
875 MEM remains unchanged for the life of the register, add a REG_EQUIV
878 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
880 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
881 && GET_CODE (SET_SRC (set
)) == MEM
882 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
883 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
888 int regno
= REGNO (dest
);
890 reg_equiv_replacement
[regno
] = XEXP (note
, 0);
892 /* Don't mess with things live during setjmp. */
893 if (REG_LIVE_LENGTH (regno
) >= 0)
895 /* Note that the statement below does not affect the priority
897 REG_LIVE_LENGTH (regno
) *= 2;
900 /* If the register is referenced exactly twice, meaning it is
901 set once and used once, indicate that the reference may be
902 replaced by the equivalence we computed above. If the
903 register is only used in one basic block, this can't succeed
904 or combine would have done it.
906 It would be nice to use "loop_depth * 2" in the compare
907 below. Unfortunately, LOOP_DEPTH need not be constant within
908 a basic block so this would be too complicated.
910 This case normally occurs when a parameter is read from
911 memory and then used exactly once, not in a loop. */
913 if (REG_N_REFS (regno
) == 2
914 && REG_BASIC_BLOCK (regno
) < 0
915 && rtx_equal_p (XEXP (note
, 0), SET_SRC (set
)))
916 reg_equiv_replace
[regno
] = 1;
921 /* Now scan all regs killed in an insn to see if any of them are
922 registers only used that once. If so, see if we can replace the
923 reference with the equivalent from. If we can, delete the
924 initializing reference and this register will go away. If we
925 can't replace the reference, and the instruction is not in a
926 loop, then move the register initialization just before the use,
927 so that they are in the same basic block. */
930 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
934 /* Keep track of which basic block we are in. */
935 if (block
+ 1 < n_basic_blocks
936 && basic_block_head
[block
+ 1] == insn
)
939 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
941 if (GET_CODE (insn
) == NOTE
)
943 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
945 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
956 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
958 if (REG_NOTE_KIND (link
) == REG_DEAD
959 /* Make sure this insn still refers to the register. */
960 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
962 int regno
= REGNO (XEXP (link
, 0));
965 if (! reg_equiv_replace
[regno
])
968 equiv_insn
= reg_equiv_init_insn
[regno
];
970 if (validate_replace_rtx (regno_reg_rtx
[regno
],
971 reg_equiv_replacement
[regno
], insn
))
973 remove_death (regno
, insn
);
974 REG_N_REFS (regno
) = 0;
975 PUT_CODE (equiv_insn
, NOTE
);
976 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
977 NOTE_SOURCE_FILE (equiv_insn
) = 0;
979 /* If we aren't in a loop, and there are no calls in
980 INSN or in the initialization of the register, then
981 move the initialization of the register to just
982 before INSN. Update the flow information. */
984 && GET_CODE (equiv_insn
) == INSN
985 && GET_CODE (insn
) == INSN
986 && REG_BASIC_BLOCK (regno
) < 0)
990 emit_insn_before (copy_rtx (PATTERN (equiv_insn
)), insn
);
991 REG_NOTES (PREV_INSN (insn
)) = REG_NOTES (equiv_insn
);
993 PUT_CODE (equiv_insn
, NOTE
);
994 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
995 NOTE_SOURCE_FILE (equiv_insn
) = 0;
996 REG_NOTES (equiv_insn
) = 0;
999 REG_BASIC_BLOCK (regno
) = 0;
1001 REG_BASIC_BLOCK (regno
) = block
;
1002 REG_N_CALLS_CROSSED (regno
) = 0;
1003 REG_LIVE_LENGTH (regno
) = 2;
1005 if (block
>= 0 && insn
== basic_block_head
[block
])
1006 basic_block_head
[block
] = PREV_INSN (insn
);
1008 for (l
= 0; l
< n_basic_blocks
; l
++)
1009 CLEAR_REGNO_REG_SET (basic_block_live_at_start
[l
], regno
);
1016 /* Allocate hard regs to the pseudo regs used only within block number B.
1017 Only the pseudos that die but once can be handled. */
1026 int insn_number
= 0;
1028 int max_uid
= get_max_uid ();
1030 int no_conflict_combined_regno
= -1;
1031 /* Counter to prevent allocating more SCRATCHes than can be stored
1033 int scratches_allocated
= scratch_index
;
1035 /* Count the instructions in the basic block. */
1037 insn
= basic_block_end
[b
];
1040 if (GET_CODE (insn
) != NOTE
)
1041 if (++insn_count
> max_uid
)
1043 if (insn
== basic_block_head
[b
])
1045 insn
= PREV_INSN (insn
);
1048 /* +2 to leave room for a post_mark_life at the last insn and for
1049 the birth of a CLOBBER in the first insn. */
1050 regs_live_at
= (HARD_REG_SET
*) alloca ((2 * insn_count
+ 2)
1051 * sizeof (HARD_REG_SET
));
1052 bzero ((char *) regs_live_at
, (2 * insn_count
+ 2) * sizeof (HARD_REG_SET
));
1054 /* Initialize table of hardware registers currently live. */
1056 REG_SET_TO_HARD_REG_SET (regs_live
, basic_block_live_at_start
[b
]);
1058 /* This loop scans the instructions of the basic block
1059 and assigns quantities to registers.
1060 It computes which registers to tie. */
1062 insn
= basic_block_head
[b
];
1065 register rtx body
= PATTERN (insn
);
1067 if (GET_CODE (insn
) != NOTE
)
1070 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1072 register rtx link
, set
;
1073 register int win
= 0;
1074 register rtx r0
, r1
;
1075 int combined_regno
= -1;
1077 int insn_code_number
= recog_memoized (insn
);
1079 this_insn_number
= insn_number
;
1082 if (insn_code_number
>= 0)
1083 insn_extract (insn
);
1084 which_alternative
= -1;
1086 /* Is this insn suitable for tying two registers?
1087 If so, try doing that.
1088 Suitable insns are those with at least two operands and where
1089 operand 0 is an output that is a register that is not
1092 We can tie operand 0 with some operand that dies in this insn.
1093 First look for operands that are required to be in the same
1094 register as operand 0. If we find such, only try tying that
1095 operand or one that can be put into that operand if the
1096 operation is commutative. If we don't find an operand
1097 that is required to be in the same register as operand 0,
1098 we can tie with any operand.
1100 Subregs in place of regs are also ok.
1102 If tying is done, WIN is set nonzero. */
1104 if (insn_code_number
>= 0
1105 #ifdef REGISTER_CONSTRAINTS
1106 && insn_n_operands
[insn_code_number
] > 1
1107 && insn_operand_constraint
[insn_code_number
][0][0] == '='
1108 && insn_operand_constraint
[insn_code_number
][0][1] != '&'
1110 && GET_CODE (PATTERN (insn
)) == SET
1111 && rtx_equal_p (SET_DEST (PATTERN (insn
)), recog_operand
[0])
1115 #ifdef REGISTER_CONSTRAINTS
1116 /* If non-negative, is an operand that must match operand 0. */
1117 int must_match_0
= -1;
1118 /* Counts number of alternatives that require a match with
1120 int n_matching_alts
= 0;
1122 for (i
= 1; i
< insn_n_operands
[insn_code_number
]; i
++)
1124 char *p
= insn_operand_constraint
[insn_code_number
][i
];
1125 int this_match
= (requires_inout (p
));
1127 n_matching_alts
+= this_match
;
1128 if (this_match
== insn_n_alternatives
[insn_code_number
])
1133 r0
= recog_operand
[0];
1134 for (i
= 1; i
< insn_n_operands
[insn_code_number
]; i
++)
1136 #ifdef REGISTER_CONSTRAINTS
1137 /* Skip this operand if we found an operand that
1138 must match operand 0 and this operand isn't it
1139 and can't be made to be it by commutativity. */
1141 if (must_match_0
>= 0 && i
!= must_match_0
1142 && ! (i
== must_match_0
+ 1
1143 && insn_operand_constraint
[insn_code_number
][i
-1][0] == '%')
1144 && ! (i
== must_match_0
- 1
1145 && insn_operand_constraint
[insn_code_number
][i
][0] == '%'))
1148 /* Likewise if each alternative has some operand that
1149 must match operand zero. In that case, skip any
1150 operand that doesn't list operand 0 since we know that
1151 the operand always conflicts with operand 0. We
1152 ignore commutatity in this case to keep things simple. */
1153 if (n_matching_alts
== insn_n_alternatives
[insn_code_number
]
1154 && (0 == requires_inout
1155 (insn_operand_constraint
[insn_code_number
][i
])))
1159 r1
= recog_operand
[i
];
1161 /* If the operand is an address, find a register in it.
1162 There may be more than one register, but we only try one
1165 #ifdef REGISTER_CONSTRAINTS
1166 insn_operand_constraint
[insn_code_number
][i
][0] == 'p'
1168 insn_operand_address_p
[insn_code_number
][i
]
1171 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1174 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1176 /* We have two priorities for hard register preferences.
1177 If we have a move insn or an insn whose first input
1178 can only be in the same register as the output, give
1179 priority to an equivalence found from that insn. */
1181 = ((SET_DEST (body
) == r0
&& SET_SRC (body
) == r1
)
1182 #ifdef REGISTER_CONSTRAINTS
1183 || (r1
== recog_operand
[i
] && must_match_0
>= 0)
1187 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1188 win
= combine_regs (r1
, r0
, may_save_copy
,
1189 insn_number
, insn
, 0);
1196 /* Recognize an insn sequence with an ultimate result
1197 which can safely overlap one of the inputs.
1198 The sequence begins with a CLOBBER of its result,
1199 and ends with an insn that copies the result to itself
1200 and has a REG_EQUAL note for an equivalent formula.
1201 That note indicates what the inputs are.
1202 The result and the input can overlap if each insn in
1203 the sequence either doesn't mention the input
1204 or has a REG_NO_CONFLICT note to inhibit the conflict.
1206 We do the combining test at the CLOBBER so that the
1207 destination register won't have had a quantity number
1208 assigned, since that would prevent combining. */
1210 if (GET_CODE (PATTERN (insn
)) == CLOBBER
1211 && (r0
= XEXP (PATTERN (insn
), 0),
1212 GET_CODE (r0
) == REG
)
1213 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1214 && XEXP (link
, 0) != 0
1215 && GET_CODE (XEXP (link
, 0)) == INSN
1216 && (set
= single_set (XEXP (link
, 0))) != 0
1217 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1218 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1221 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1222 /* Check that we have such a sequence. */
1223 && no_conflict_p (insn
, r0
, r1
))
1224 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1225 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1226 && (r1
= XEXP (XEXP (note
, 0), 0),
1227 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1228 && no_conflict_p (insn
, r0
, r1
))
1229 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1231 /* Here we care if the operation to be computed is
1233 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1234 || GET_CODE (XEXP (note
, 0)) == NE
1235 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1236 && (r1
= XEXP (XEXP (note
, 0), 1),
1237 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1238 && no_conflict_p (insn
, r0
, r1
))
1239 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1241 /* If we did combine something, show the register number
1242 in question so that we know to ignore its death. */
1244 no_conflict_combined_regno
= REGNO (r1
);
1247 /* If registers were just tied, set COMBINED_REGNO
1248 to the number of the register used in this insn
1249 that was tied to the register set in this insn.
1250 This register's qty should not be "killed". */
1254 while (GET_CODE (r1
) == SUBREG
)
1255 r1
= SUBREG_REG (r1
);
1256 combined_regno
= REGNO (r1
);
1259 /* Mark the death of everything that dies in this instruction,
1260 except for anything that was just combined. */
1262 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1263 if (REG_NOTE_KIND (link
) == REG_DEAD
1264 && GET_CODE (XEXP (link
, 0)) == REG
1265 && combined_regno
!= REGNO (XEXP (link
, 0))
1266 && (no_conflict_combined_regno
!= REGNO (XEXP (link
, 0))
1267 || ! find_reg_note (insn
, REG_NO_CONFLICT
, XEXP (link
, 0))))
1268 wipe_dead_reg (XEXP (link
, 0), 0);
1270 /* Allocate qty numbers for all registers local to this block
1271 that are born (set) in this instruction.
1272 A pseudo that already has a qty is not changed. */
1274 note_stores (PATTERN (insn
), reg_is_set
);
1276 /* If anything is set in this insn and then unused, mark it as dying
1277 after this insn, so it will conflict with our outputs. This
1278 can't match with something that combined, and it doesn't matter
1279 if it did. Do this after the calls to reg_is_set since these
1280 die after, not during, the current insn. */
1282 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1283 if (REG_NOTE_KIND (link
) == REG_UNUSED
1284 && GET_CODE (XEXP (link
, 0)) == REG
)
1285 wipe_dead_reg (XEXP (link
, 0), 1);
1287 /* Allocate quantities for any SCRATCH operands of this insn. */
1289 if (insn_code_number
>= 0)
1290 for (i
= 0; i
< insn_n_operands
[insn_code_number
]; i
++)
1291 if (GET_CODE (recog_operand
[i
]) == SCRATCH
1292 && scratches_allocated
++ < scratch_list_length
)
1293 alloc_qty_for_scratch (recog_operand
[i
], i
, insn
,
1294 insn_code_number
, insn_number
);
1296 /* If this is an insn that has a REG_RETVAL note pointing at a
1297 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1298 block, so clear any register number that combined within it. */
1299 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1300 && GET_CODE (XEXP (note
, 0)) == INSN
1301 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1302 no_conflict_combined_regno
= -1;
1305 /* Set the registers live after INSN_NUMBER. Note that we never
1306 record the registers live before the block's first insn, since no
1307 pseudos we care about are live before that insn. */
1309 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1310 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1312 if (insn
== basic_block_end
[b
])
1315 insn
= NEXT_INSN (insn
);
1318 /* Now every register that is local to this basic block
1319 should have been given a quantity, or else -1 meaning ignore it.
1320 Every quantity should have a known birth and death.
1322 Order the qtys so we assign them registers in order of the
1323 number of suggested registers they need so we allocate those with
1324 the most restrictive needs first. */
1326 qty_order
= (int *) alloca (next_qty
* sizeof (int));
1327 for (i
= 0; i
< next_qty
; i
++)
1330 #define EXCHANGE(I1, I2) \
1331 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1336 /* Make qty_order[2] be the one to allocate last. */
1337 if (qty_sugg_compare (0, 1) > 0)
1339 if (qty_sugg_compare (1, 2) > 0)
1342 /* ... Fall through ... */
1344 /* Put the best one to allocate in qty_order[0]. */
1345 if (qty_sugg_compare (0, 1) > 0)
1348 /* ... Fall through ... */
1352 /* Nothing to do here. */
1356 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1359 /* Try to put each quantity in a suggested physical register, if it has one.
1360 This may cause registers to be allocated that otherwise wouldn't be, but
1361 this seems acceptable in local allocation (unlike global allocation). */
1362 for (i
= 0; i
< next_qty
; i
++)
1365 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1366 qty_phys_reg
[q
] = find_free_reg (qty_min_class
[q
], qty_mode
[q
], q
,
1367 0, 1, qty_birth
[q
], qty_death
[q
]);
1369 qty_phys_reg
[q
] = -1;
1372 /* Order the qtys so we assign them registers in order of
1373 decreasing length of life. Normally call qsort, but if we
1374 have only a very small number of quantities, sort them ourselves. */
1376 for (i
= 0; i
< next_qty
; i
++)
1379 #define EXCHANGE(I1, I2) \
1380 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1385 /* Make qty_order[2] be the one to allocate last. */
1386 if (qty_compare (0, 1) > 0)
1388 if (qty_compare (1, 2) > 0)
1391 /* ... Fall through ... */
1393 /* Put the best one to allocate in qty_order[0]. */
1394 if (qty_compare (0, 1) > 0)
1397 /* ... Fall through ... */
1401 /* Nothing to do here. */
1405 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1408 /* Now for each qty that is not a hardware register,
1409 look for a hardware register to put it in.
1410 First try the register class that is cheapest for this qty,
1411 if there is more than one class. */
1413 for (i
= 0; i
< next_qty
; i
++)
1416 if (qty_phys_reg
[q
] < 0)
1418 #ifdef INSN_SCHEDULING
1419 /* These values represent the adjusted lifetime of a qty so
1420 that it conflicts with qtys which appear near the start/end
1421 of this qty's lifetime.
1423 The purpose behind extending the lifetime of this qty is to
1424 discourage the register allocator from creating false
1427 The adjustment by the value +-3 indicates precisely that
1428 this qty conflicts with qtys in the instructions immediately
1429 before and after the lifetime of this qty.
1431 Experiments have shown that higher values tend to hurt
1432 overall code performance.
1434 If allocation using the extended lifetime fails we will try
1435 again with the qty's unadjusted lifetime. */
1436 int fake_birth
= MAX (0, qty_birth
[q
] - 3);
1437 int fake_death
= MIN (insn_number
* 2 + 1, qty_death
[q
] + 3);
1440 if (N_REG_CLASSES
> 1)
1442 #ifdef INSN_SCHEDULING
1443 /* We try to avoid using hard registers allocated to qtys which
1444 are born immediately after this qty or die immediately before
1447 This optimization is only appropriate when we will run
1448 a scheduling pass after reload and we are not optimizing
1450 if (flag_schedule_insns_after_reload
&& !optimize_size
)
1453 qty_phys_reg
[q
] = find_free_reg (qty_min_class
[q
],
1454 qty_mode
[q
], q
, 0, 0,
1455 fake_birth
, fake_death
);
1456 if (qty_phys_reg
[q
] >= 0)
1460 qty_phys_reg
[q
] = find_free_reg (qty_min_class
[q
],
1461 qty_mode
[q
], q
, 0, 0,
1462 qty_birth
[q
], qty_death
[q
]);
1463 if (qty_phys_reg
[q
] >= 0)
1467 #ifdef INSN_SCHEDULING
1468 /* Similarly, avoid false dependencies. */
1469 if (flag_schedule_insns_after_reload
&& !optimize_size
1470 && qty_alternate_class
[q
] != NO_REGS
)
1471 qty_phys_reg
[q
] = find_free_reg (qty_alternate_class
[q
],
1472 qty_mode
[q
], q
, 0, 0,
1473 fake_birth
, fake_death
);
1475 if (qty_alternate_class
[q
] != NO_REGS
)
1476 qty_phys_reg
[q
] = find_free_reg (qty_alternate_class
[q
],
1477 qty_mode
[q
], q
, 0, 0,
1478 qty_birth
[q
], qty_death
[q
]);
1482 /* Now propagate the register assignments
1483 to the pseudo regs belonging to the qtys. */
1485 for (q
= 0; q
< next_qty
; q
++)
1486 if (qty_phys_reg
[q
] >= 0)
1488 for (i
= qty_first_reg
[q
]; i
>= 0; i
= reg_next_in_qty
[i
])
1489 reg_renumber
[i
] = qty_phys_reg
[q
] + reg_offset
[i
];
1490 if (qty_scratch_rtx
[q
])
1492 if (GET_CODE (qty_scratch_rtx
[q
]) == REG
)
1494 qty_scratch_rtx
[q
] = gen_rtx_REG (GET_MODE (qty_scratch_rtx
[q
]),
1496 scratch_block
[scratch_index
] = b
;
1497 scratch_list
[scratch_index
++] = qty_scratch_rtx
[q
];
1503 /* Compare two quantities' priority for getting real registers.
1504 We give shorter-lived quantities higher priority.
1505 Quantities with more references are also preferred, as are quantities that
1506 require multiple registers. This is the identical prioritization as
1507 done by global-alloc.
1509 We used to give preference to registers with *longer* lives, but using
1510 the same algorithm in both local- and global-alloc can speed up execution
1511 of some programs by as much as a factor of three! */
1513 /* Note that the quotient will never be bigger than
1514 the value of floor_log2 times the maximum number of
1515 times a register can occur in one insn (surely less than 100).
1516 Multiplying this by 10000 can't overflow.
1517 QTY_CMP_PRI is also used by qty_sugg_compare. */
1519 #define QTY_CMP_PRI(q) \
1520 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1521 / (qty_death[q] - qty_birth[q])) * 10000))
1524 qty_compare (q1
, q2
)
1527 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1531 qty_compare_1 (q1p
, q2p
)
1532 const GENERIC_PTR q1p
;
1533 const GENERIC_PTR q2p
;
1535 register int q1
= *(int *)q1p
, q2
= *(int *)q2p
;
1536 register int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1541 /* If qtys are equally good, sort by qty number,
1542 so that the results of qsort leave nothing to chance. */
1546 /* Compare two quantities' priority for getting real registers. This version
1547 is called for quantities that have suggested hard registers. First priority
1548 goes to quantities that have copy preferences, then to those that have
1549 normal preferences. Within those groups, quantities with the lower
1550 number of preferences have the highest priority. Of those, we use the same
1551 algorithm as above. */
1553 #define QTY_CMP_SUGG(q) \
1554 (qty_phys_num_copy_sugg[q] \
1555 ? qty_phys_num_copy_sugg[q] \
1556 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1559 qty_sugg_compare (q1
, q2
)
1562 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1567 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1571 qty_sugg_compare_1 (q1p
, q2p
)
1572 const GENERIC_PTR q1p
;
1573 const GENERIC_PTR q2p
;
1575 register int q1
= *(int *)q1p
, q2
= *(int *)q2p
;
1576 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1581 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1585 /* If qtys are equally good, sort by qty number,
1586 so that the results of qsort leave nothing to chance. */
1593 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1594 Returns 1 if have done so, or 0 if cannot.
1596 Combining registers means marking them as having the same quantity
1597 and adjusting the offsets within the quantity if either of
1600 We don't actually combine a hard reg with a pseudo; instead
1601 we just record the hard reg as the suggestion for the pseudo's quantity.
1602 If we really combined them, we could lose if the pseudo lives
1603 across an insn that clobbers the hard reg (eg, movstr).
1605 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1606 there is no REG_DEAD note on INSN. This occurs during the processing
1607 of REG_NO_CONFLICT blocks.
1609 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1610 SETREG or if the input and output must share a register.
1611 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1613 There are elaborate checks for the validity of combining. */
1617 combine_regs (usedreg
, setreg
, may_save_copy
, insn_number
, insn
, already_dead
)
1618 rtx usedreg
, setreg
;
1624 register int ureg
, sreg
;
1625 register int offset
= 0;
1629 /* Determine the numbers and sizes of registers being used. If a subreg
1630 is present that does not change the entire register, don't consider
1631 this a copy insn. */
1633 while (GET_CODE (usedreg
) == SUBREG
)
1635 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg
))) > UNITS_PER_WORD
)
1637 offset
+= SUBREG_WORD (usedreg
);
1638 usedreg
= SUBREG_REG (usedreg
);
1640 if (GET_CODE (usedreg
) != REG
)
1642 ureg
= REGNO (usedreg
);
1643 usize
= REG_SIZE (usedreg
);
1645 while (GET_CODE (setreg
) == SUBREG
)
1647 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg
))) > UNITS_PER_WORD
)
1649 offset
-= SUBREG_WORD (setreg
);
1650 setreg
= SUBREG_REG (setreg
);
1652 if (GET_CODE (setreg
) != REG
)
1654 sreg
= REGNO (setreg
);
1655 ssize
= REG_SIZE (setreg
);
1657 /* If UREG is a pseudo-register that hasn't already been assigned a
1658 quantity number, it means that it is not local to this block or dies
1659 more than once. In either event, we can't do anything with it. */
1660 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1661 /* Do not combine registers unless one fits within the other. */
1662 || (offset
> 0 && usize
+ offset
> ssize
)
1663 || (offset
< 0 && usize
+ offset
< ssize
)
1664 /* Do not combine with a smaller already-assigned object
1665 if that smaller object is already combined with something bigger. */
1666 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1667 && usize
< qty_size
[reg_qty
[ureg
]])
1668 /* Can't combine if SREG is not a register we can allocate. */
1669 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1670 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1671 These have already been taken care of. This probably wouldn't
1672 combine anyway, but don't take any chances. */
1673 || (ureg
>= FIRST_PSEUDO_REGISTER
1674 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1675 /* Don't tie something to itself. In most cases it would make no
1676 difference, but it would screw up if the reg being tied to itself
1677 also dies in this insn. */
1679 /* Don't try to connect two different hardware registers. */
1680 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1681 /* Don't connect two different machine modes if they have different
1682 implications as to which registers may be used. */
1683 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1686 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1687 qty_phys_sugg for the pseudo instead of tying them.
1689 Return "failure" so that the lifespan of UREG is terminated here;
1690 that way the two lifespans will be disjoint and nothing will prevent
1691 the pseudo reg from being given this hard reg. */
1693 if (ureg
< FIRST_PSEUDO_REGISTER
)
1695 /* Allocate a quantity number so we have a place to put our
1697 if (reg_qty
[sreg
] == -2)
1698 reg_is_born (setreg
, 2 * insn_number
);
1700 if (reg_qty
[sreg
] >= 0)
1703 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1705 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1706 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1708 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1710 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1711 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1717 /* Similarly for SREG a hard register and UREG a pseudo register. */
1719 if (sreg
< FIRST_PSEUDO_REGISTER
)
1722 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1724 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1725 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1727 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1729 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1730 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1735 /* At this point we know that SREG and UREG are both pseudos.
1736 Do nothing if SREG already has a quantity or is a register that we
1738 if (reg_qty
[sreg
] >= -1
1739 /* If we are not going to let any regs live across calls,
1740 don't tie a call-crossing reg to a non-call-crossing reg. */
1741 || (current_function_has_nonlocal_label
1742 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1743 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1746 /* We don't already know about SREG, so tie it to UREG
1747 if this is the last use of UREG, provided the classes they want
1750 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1751 && reg_meets_class_p (sreg
, qty_min_class
[reg_qty
[ureg
]]))
1753 /* Add SREG to UREG's quantity. */
1754 sqty
= reg_qty
[ureg
];
1755 reg_qty
[sreg
] = sqty
;
1756 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1757 reg_next_in_qty
[sreg
] = qty_first_reg
[sqty
];
1758 qty_first_reg
[sqty
] = sreg
;
1760 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1761 update_qty_class (sqty
, sreg
);
1763 /* Update info about quantity SQTY. */
1764 qty_n_calls_crossed
[sqty
] += REG_N_CALLS_CROSSED (sreg
);
1765 qty_n_refs
[sqty
] += REG_N_REFS (sreg
);
1770 for (i
= qty_first_reg
[sqty
]; i
>= 0; i
= reg_next_in_qty
[i
])
1771 reg_offset
[i
] -= offset
;
1773 qty_size
[sqty
] = ssize
;
1774 qty_mode
[sqty
] = GET_MODE (setreg
);
1783 /* Return 1 if the preferred class of REG allows it to be tied
1784 to a quantity or register whose class is CLASS.
1785 True if REG's reg class either contains or is contained in CLASS. */
1788 reg_meets_class_p (reg
, class)
1790 enum reg_class
class;
1792 register enum reg_class rclass
= reg_preferred_class (reg
);
1793 return (reg_class_subset_p (rclass
, class)
1794 || reg_class_subset_p (class, rclass
));
1797 /* Update the class of QTY assuming that REG is being tied to it. */
1800 update_qty_class (qty
, reg
)
1804 enum reg_class rclass
= reg_preferred_class (reg
);
1805 if (reg_class_subset_p (rclass
, qty_min_class
[qty
]))
1806 qty_min_class
[qty
] = rclass
;
1808 rclass
= reg_alternate_class (reg
);
1809 if (reg_class_subset_p (rclass
, qty_alternate_class
[qty
]))
1810 qty_alternate_class
[qty
] = rclass
;
1812 if (REG_CHANGES_SIZE (reg
))
1813 qty_changes_size
[qty
] = 1;
1816 /* Handle something which alters the value of an rtx REG.
1818 REG is whatever is set or clobbered. SETTER is the rtx that
1819 is modifying the register.
1821 If it is not really a register, we do nothing.
1822 The file-global variables `this_insn' and `this_insn_number'
1823 carry info from `block_alloc'. */
1826 reg_is_set (reg
, setter
)
1830 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1831 a hard register. These may actually not exist any more. */
1833 if (GET_CODE (reg
) != SUBREG
1834 && GET_CODE (reg
) != REG
)
1837 /* Mark this register as being born. If it is used in a CLOBBER, mark
1838 it as being born halfway between the previous insn and this insn so that
1839 it conflicts with our inputs but not the outputs of the previous insn. */
1841 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
1844 /* Handle beginning of the life of register REG.
1845 BIRTH is the index at which this is happening. */
1848 reg_is_born (reg
, birth
)
1854 if (GET_CODE (reg
) == SUBREG
)
1855 regno
= REGNO (SUBREG_REG (reg
)) + SUBREG_WORD (reg
);
1857 regno
= REGNO (reg
);
1859 if (regno
< FIRST_PSEUDO_REGISTER
)
1861 mark_life (regno
, GET_MODE (reg
), 1);
1863 /* If the register was to have been born earlier that the present
1864 insn, mark it as live where it is actually born. */
1865 if (birth
< 2 * this_insn_number
)
1866 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
1870 if (reg_qty
[regno
] == -2)
1871 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
1873 /* If this register has a quantity number, show that it isn't dead. */
1874 if (reg_qty
[regno
] >= 0)
1875 qty_death
[reg_qty
[regno
]] = -1;
1879 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1880 REG is an output that is dying (i.e., it is never used), otherwise it
1881 is an input (the normal case).
1882 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1885 wipe_dead_reg (reg
, output_p
)
1889 register int regno
= REGNO (reg
);
1891 /* If this insn has multiple results,
1892 and the dead reg is used in one of the results,
1893 extend its life to after this insn,
1894 so it won't get allocated together with any other result of this insn. */
1895 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
1896 && !single_set (this_insn
))
1899 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
1901 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
1902 if (GET_CODE (set
) == SET
1903 && GET_CODE (SET_DEST (set
)) != REG
1904 && !rtx_equal_p (reg
, SET_DEST (set
))
1905 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1910 /* If this register is used in an auto-increment address, then extend its
1911 life to after this insn, so that it won't get allocated together with
1912 the result of this insn. */
1913 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
1916 if (regno
< FIRST_PSEUDO_REGISTER
)
1918 mark_life (regno
, GET_MODE (reg
), 0);
1920 /* If a hard register is dying as an output, mark it as in use at
1921 the beginning of this insn (the above statement would cause this
1924 post_mark_life (regno
, GET_MODE (reg
), 1,
1925 2 * this_insn_number
, 2 * this_insn_number
+ 1);
1928 else if (reg_qty
[regno
] >= 0)
1929 qty_death
[reg_qty
[regno
]] = 2 * this_insn_number
+ output_p
;
1932 /* Find a block of SIZE words of hard regs in reg_class CLASS
1933 that can hold something of machine-mode MODE
1934 (but actually we test only the first of the block for holding MODE)
1935 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1936 and return the number of the first of them.
1937 Return -1 if such a block cannot be found.
1938 If QTY crosses calls, insist on a register preserved by calls,
1939 unless ACCEPT_CALL_CLOBBERED is nonzero.
1941 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1942 register is available. If not, return -1. */
1945 find_free_reg (class, mode
, qty
, accept_call_clobbered
, just_try_suggested
,
1946 born_index
, dead_index
)
1947 enum reg_class
class;
1948 enum machine_mode mode
;
1950 int accept_call_clobbered
;
1951 int just_try_suggested
;
1952 int born_index
, dead_index
;
1954 register int i
, ins
;
1956 register /* Declare it register if it's a scalar. */
1958 HARD_REG_SET used
, first_used
;
1959 #ifdef ELIMINABLE_REGS
1960 static struct {int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
1963 /* Validate our parameters. */
1964 if (born_index
< 0 || born_index
> dead_index
)
1967 /* Don't let a pseudo live in a reg across a function call
1968 if we might get a nonlocal goto. */
1969 if (current_function_has_nonlocal_label
1970 && qty_n_calls_crossed
[qty
] > 0)
1973 if (accept_call_clobbered
)
1974 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
1975 else if (qty_n_calls_crossed
[qty
] == 0)
1976 COPY_HARD_REG_SET (used
, fixed_reg_set
);
1978 COPY_HARD_REG_SET (used
, call_used_reg_set
);
1980 if (accept_call_clobbered
)
1981 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
1983 for (ins
= born_index
; ins
< dead_index
; ins
++)
1984 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
1986 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
1988 /* Don't use the frame pointer reg in local-alloc even if
1989 we may omit the frame pointer, because if we do that and then we
1990 need a frame pointer, reload won't know how to move the pseudo
1991 to another hard reg. It can move only regs made by global-alloc.
1993 This is true of any register that can be eliminated. */
1994 #ifdef ELIMINABLE_REGS
1995 for (i
= 0; i
< sizeof eliminables
/ sizeof eliminables
[0]; i
++)
1996 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
1997 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1998 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1999 that it might be eliminated into. */
2000 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
2003 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
2006 #ifdef CLASS_CANNOT_CHANGE_SIZE
2007 if (qty_changes_size
[qty
])
2008 IOR_HARD_REG_SET (used
,
2009 reg_class_contents
[(int) CLASS_CANNOT_CHANGE_SIZE
]);
2012 /* Normally, the registers that can be used for the first register in
2013 a multi-register quantity are the same as those that can be used for
2014 subsequent registers. However, if just trying suggested registers,
2015 restrict our consideration to them. If there are copy-suggested
2016 register, try them. Otherwise, try the arithmetic-suggested
2018 COPY_HARD_REG_SET (first_used
, used
);
2020 if (just_try_suggested
)
2022 if (qty_phys_num_copy_sugg
[qty
] != 0)
2023 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qty
]);
2025 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qty
]);
2028 /* If all registers are excluded, we can't do anything. */
2029 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2031 /* If at least one would be suitable, test each hard reg. */
2033 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2035 #ifdef REG_ALLOC_ORDER
2036 int regno
= reg_alloc_order
[i
];
2040 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2041 && HARD_REGNO_MODE_OK (regno
, mode
))
2044 register int size1
= HARD_REGNO_NREGS (regno
, mode
);
2045 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2048 /* Mark that this register is in use between its birth and death
2050 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2053 #ifndef REG_ALLOC_ORDER
2054 i
+= j
; /* Skip starting points we know will lose */
2061 /* If we are just trying suggested register, we have just tried copy-
2062 suggested registers, and there are arithmetic-suggested registers,
2065 /* If it would be profitable to allocate a call-clobbered register
2066 and save and restore it around calls, do that. */
2067 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qty
] != 0
2068 && qty_phys_num_sugg
[qty
] != 0)
2070 /* Don't try the copy-suggested regs again. */
2071 qty_phys_num_copy_sugg
[qty
] = 0;
2072 return find_free_reg (class, mode
, qty
, accept_call_clobbered
, 1,
2073 born_index
, dead_index
);
2076 /* We need not check to see if the current function has nonlocal
2077 labels because we don't put any pseudos that are live over calls in
2078 registers in that case. */
2080 if (! accept_call_clobbered
2081 && flag_caller_saves
2082 && ! just_try_suggested
2083 && qty_n_calls_crossed
[qty
] != 0
2084 && CALLER_SAVE_PROFITABLE (qty_n_refs
[qty
], qty_n_calls_crossed
[qty
]))
2086 i
= find_free_reg (class, mode
, qty
, 1, 0, born_index
, dead_index
);
2088 caller_save_needed
= 1;
2094 /* Mark that REGNO with machine-mode MODE is live starting from the current
2095 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2099 mark_life (regno
, mode
, life
)
2101 enum machine_mode mode
;
2104 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2107 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2110 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2113 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2114 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2115 to insn number DEATH (exclusive). */
2118 post_mark_life (regno
, mode
, life
, birth
, death
)
2120 enum machine_mode mode
;
2121 int life
, birth
, death
;
2123 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2125 register /* Declare it register if it's a scalar. */
2127 HARD_REG_SET this_reg
;
2129 CLEAR_HARD_REG_SET (this_reg
);
2131 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2134 while (birth
< death
)
2136 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2140 while (birth
< death
)
2142 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2147 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2148 is the register being clobbered, and R1 is a register being used in
2149 the equivalent expression.
2151 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2152 in which it is used, return 1.
2154 Otherwise, return 0. */
2157 no_conflict_p (insn
, r0
, r1
)
2161 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2164 /* If R1 is a hard register, return 0 since we handle this case
2165 when we scan the insns that actually use it. */
2168 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2169 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2170 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2173 last
= XEXP (note
, 0);
2175 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2176 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
2178 if (find_reg_note (p
, REG_DEAD
, r1
))
2181 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2182 some earlier optimization pass has inserted instructions into
2183 the sequence, and it is not safe to perform this optimization.
2184 Note that emit_no_conflict_block always ensures that this is
2185 true when these sequences are created. */
2186 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2193 #ifdef REGISTER_CONSTRAINTS
2195 /* Return the number of alternatives for which the constraint string P
2196 indicates that the operand must be equal to operand 0 and that no register
2205 int reg_allowed
= 0;
2206 int num_matching_alts
= 0;
2211 case '=': case '+': case '?':
2212 case '#': case '&': case '!':
2214 case '1': case '2': case '3': case '4':
2215 case 'm': case '<': case '>': case 'V': case 'o':
2216 case 'E': case 'F': case 'G': case 'H':
2217 case 's': case 'i': case 'n':
2218 case 'I': case 'J': case 'K': case 'L':
2219 case 'M': case 'N': case 'O': case 'P':
2220 #ifdef EXTRA_CONSTRAINT
2221 case 'Q': case 'R': case 'S': case 'T': case 'U':
2224 /* These don't say anything we care about. */
2228 if (found_zero
&& ! reg_allowed
)
2229 num_matching_alts
++;
2231 found_zero
= reg_allowed
= 0;
2245 if (found_zero
&& ! reg_allowed
)
2246 num_matching_alts
++;
2248 return num_matching_alts
;
2250 #endif /* REGISTER_CONSTRAINTS */
2253 dump_local_alloc (file
)
2257 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2258 if (reg_renumber
[i
] != -1)
2259 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);