| blob | ced6f9bf82948b3c3da022f360f03fd2268551d6 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
71 /* This file should be included last. */
74 /* Defined for convenience. */
75 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
77 /* Classifies an address.
79 ADDRESS_REG_IMM
80 A simple base register plus immediate offset.
82 ADDRESS_REG_WB
83 A base register indexed by immediate offset with writeback.
85 ADDRESS_REG_REG
86 A base register indexed by (optionally scaled) register.
88 ADDRESS_REG_UXTW
89 A base register indexed by (optionally scaled) zero-extended register.
91 ADDRESS_REG_SXTW
92 A base register indexed by (optionally scaled) sign-extended register.
94 ADDRESS_LO_SUM
95 A LO_SUM rtx with a base register and "LO12" symbol relocation.
97 ADDRESS_SYMBOLIC:
98 A constant symbolic address, in pc-relative literal pool. */
101 ADDRESS_REG_IMM,
102 ADDRESS_REG_WB,
103 ADDRESS_REG_REG,
104 ADDRESS_REG_UXTW,
105 ADDRESS_REG_SXTW,
106 ADDRESS_LO_SUM,
107 ADDRESS_SYMBOLIC
108 };
112 rtx base;
113 rtx offset;
116 };
118 struct simd_immediate_info
119 {
120 rtx value;
125 };
127 /* The current code model. */
130 #ifdef HAVE_AS_TLS
131 #undef TARGET_HAVE_TLS
132 #define TARGET_HAVE_TLS 1
133 #endif
137 const_tree,
148 const_tree type,
151 static machine_mode
154 /* Major revision number of the ARM Architecture implemented by the target. */
157 /* The processor for which instructions should be scheduled. */
160 /* Mask to specify which instruction scheduling options should be used. */
163 /* Global flag for PC relative loads. */
166 /* Support for command line parsing of boolean flags in the tuning
167 structures. */
168 struct aarch64_flag_desc
169 {
172 };
174 #define AARCH64_FUSION_PAIR(name, internal_name) \
175 { name, AARCH64_FUSE_##internal_name },
177 {
182 };
184 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
185 { name, AARCH64_EXTRA_TUNE_##internal_name },
187 {
192 };
194 /* Tuning parameters. */
197 {
198 {
203 },
210 };
213 {
214 {
219 },
226 };
229 {
230 {
235 },
242 };
245 {
246 {
251 },
258 };
261 {
263 /* Avoid the use of slow int<->fp moves for spilling by setting
264 their cost higher than memmov_cost. */
268 };
271 {
273 /* Avoid the use of slow int<->fp moves for spilling by setting
274 their cost higher than memmov_cost. */
278 };
281 {
283 /* Avoid the use of slow int<->fp moves for spilling by setting
284 their cost higher than memmov_cost. */
288 };
291 {
293 /* Avoid the use of slow int<->fp moves for spilling by setting
294 their cost higher than memmov_cost (actual, 4 and 9). */
298 };
301 {
306 };
309 {
311 /* Avoid the use of slow int<->fp moves for spilling by setting
312 their cost higher than memmov_cost. */
316 };
319 {
321 /* Avoid the use of int<->fp moves for spilling. */
325 };
328 {
330 /* Avoid the use of int<->fp moves for spilling. */
334 };
336 /* Generic costs for vector insn classes. */
338 {
354 };
356 /* ThunderX costs for vector insn classes. */
358 {
374 };
376 /* Generic costs for vector insn classes. */
378 {
394 };
397 {
413 };
415 /* Generic costs for vector insn classes. */
417 {
433 };
435 /* Costs for vector insn classes for Vulcan. */
437 {
453 };
455 /* Generic costs for branch instructions. */
457 {
460 };
462 /* Generic approximation modes. */
464 {
467 AARCH64_APPROX_NONE /* recip_sqrt */
468 };
470 /* Approximation modes for Exynos M1. */
472 {
475 AARCH64_APPROX_ALL /* recip_sqrt */
476 };
478 /* Approximation modes for X-Gene 1. */
480 {
483 AARCH64_APPROX_ALL /* recip_sqrt */
484 };
486 /* Generic prefetch settings (which disable prefetch). */
488 {
494 };
497 {
503 };
506 {
512 };
515 {
521 };
524 {
530 };
533 {
539 };
542 {
563 &generic_prefetch_tune
564 };
567 {
589 &generic_prefetch_tune
590 };
593 {
615 &generic_prefetch_tune
616 };
619 {
641 &generic_prefetch_tune
642 };
645 {
667 &generic_prefetch_tune
668 };
671 {
693 &generic_prefetch_tune
694 };
699 {
720 &exynosm1_prefetch_tune
721 };
724 {
745 &thunderxt88_prefetch_tune
746 };
749 {
769 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
771 &thunderx_prefetch_tune
772 };
775 {
796 &generic_prefetch_tune
797 };
800 {
822 &qdf24xx_prefetch_tune
823 };
826 {
848 &thunderx2t99_prefetch_tune
849 };
851 /* Support for fine-grained override of the tuning structures. */
852 struct aarch64_tuning_override_function
853 {
856 };
861 static const struct aarch64_tuning_override_function
862 aarch64_tuning_override_functions[] =
863 {
867 };
869 /* A processor implementing AArch64. */
870 struct processor
871 {
879 };
881 /* Architectures implementing AArch64. */
883 {
884 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
885 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
888 };
890 /* Processor cores implementing AArch64. */
892 {
893 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
894 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
895 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
896 FLAGS, &COSTS##_tunings},
901 };
904 /* Target specification. These are populated by the -march, -mtune, -mcpu
905 handling code or by target attributes. */
910 /* The current tuning set. */
913 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
915 /* An ISA extension in the co-processor and main instruction set space. */
916 struct aarch64_option_extension
917 {
921 };
924 {
928 }
929 aarch64_cc;
931 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
933 /* The condition codes of the processor, and the inverse function. */
935 {
938 };
940 /* Generate code to enable conditional branches in functions over 1 MiB. */
944 {
961 }
963 void
965 {
969 else
971 }
973 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
974 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
975 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
976 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
977 cost (in this case the best class is the lowest cost one). Using ALL_REGS
978 irrespectively of its cost results in bad allocations with many redundant
979 int<->FP moves which are expensive on various cores.
980 To avoid this we don't allow ALL_REGS as the allocno class, but force a
981 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
982 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
983 Otherwise set the allocno class depending on the mode.
984 The result of this is that it is no longer inefficient to have a higher
985 memory move cost than the register move cost.
986 */
988 static reg_class_t
990 reg_class_t best_class)
991 {
992 machine_mode mode;
1002 }
1004 static unsigned int
1006 {
1010 }
1012 static int
1014 machine_mode mode)
1015 {
1023 }
1025 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1026 unsigned
1028 {
1036 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1037 equivalent DWARF register. */
1039 }
1041 /* Return TRUE if MODE is any of the large INT modes. */
1042 static bool
1044 {
1046 }
1048 /* Return TRUE if MODE is any of the vector modes. */
1049 static bool
1051 {
1054 }
1056 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1057 static bool
1060 {
1068 }
1070 /* Implement HARD_REGNO_NREGS. */
1072 int
1074 {
1076 {
1082 }
1084 }
1086 /* Implement HARD_REGNO_MODE_OK. */
1088 int
1090 {
1095 /* The purpose of comparing with ptr_mode is to support the
1096 global register variable associated with the stack pointer
1097 register via the syntax of asm ("wsp") in ILP32. */
1107 {
1109 return
1111 else
1113 }
1116 }
1118 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1119 machine_mode
1121 machine_mode mode)
1122 {
1123 /* Handle modes that fit within single registers. */
1125 {
1128 else
1130 }
1131 /* Fall back to generic for multi-reg and very large modes. */
1132 else
1134 }
1136 /* Return true if calls to DECL should be treated as
1137 long-calls (ie called via a register). */
1138 static bool
1140 {
1142 }
1144 /* Return true if calls to symbol-ref SYM should be treated as
1145 long-calls (ie called via a register). */
1146 bool
1148 {
1150 }
1152 /* Return true if calls to symbol-ref SYM should not go through
1153 plt stubs. */
1155 bool
1157 {
1161 && decl
1162 && (!flag_plt
1168 }
1170 /* Return true if the offsets to a zero/sign-extract operation
1171 represent an expression that matches an extend operation. The
1172 operands represent the paramters from
1174 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1175 bool
1177 rtx extract_imm)
1178 {
1195 }
1197 /* Emit an insn that's a simple single-set. Both the operands must be
1198 known to be valid. */
1201 {
1203 }
1205 /* X and Y are two things to compare using CODE. Emit the compare insn and
1206 return the rtx for register 0 in the proper mode. */
1207 rtx
1209 {
1215 }
1217 /* Build the SYMBOL_REF for __tls_get_addr. */
1221 rtx
1223 {
1227 }
1229 /* Return the TLS model to use for ADDR. */
1231 static enum tls_model
1233 {
1238 {
1242 }
1247 }
1249 /* We'll allow lo_sum's in addresses in our legitimate addresses
1250 so that combine would take care of combining addresses where
1251 necessary, but for generation purposes, we'll generate the address
1252 as :
1253 RTL Absolute
1254 tmp = hi (symbol_ref); adrp x1, foo
1255 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1256 nop
1258 PIC TLS
1259 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1260 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1261 bl __tls_get_addr
1262 nop
1264 Load TLS symbol, depending on TLS mechanism and TLS access model.
1266 Global Dynamic - Traditional TLS:
1267 adrp tmp, :tlsgd:imm
1268 add dest, tmp, #:tlsgd_lo12:imm
1269 bl __tls_get_addr
1271 Global Dynamic - TLS Descriptors:
1272 adrp dest, :tlsdesc:imm
1273 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1274 add dest, dest, #:tlsdesc_lo12:imm
1275 blr tmp
1276 mrs tp, tpidr_el0
1277 add dest, dest, tp
1279 Initial Exec:
1280 mrs tp, tpidr_el0
1281 adrp tmp, :gottprel:imm
1282 ldr dest, [tmp, #:gottprel_lo12:imm]
1283 add dest, dest, tp
1285 Local Exec:
1286 mrs tp, tpidr_el0
1287 add t0, tp, #:tprel_hi12:imm, lsl #12
1288 add t0, t0, #:tprel_lo12_nc:imm
1289 */
1291 static void
1294 {
1296 {
1298 {
1299 /* In ILP32, the mode of dest can be either SImode or DImode. */
1311 }
1318 {
1321 rtx insn;
1322 rtx mem;
1324 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1325 here before rtl expand. Tree IVOPT will generate rtl pattern to
1326 decide rtx costs, in which case pic_offset_table_rtx is not
1327 initialized. For that case no need to generate the first adrp
1328 instruction as the final cost for global variable access is
1329 one instruction. */
1331 {
1332 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1333 using the page base as GOT base, the first page may be wasted,
1334 in the worst scenario, there is only 28K space for GOT).
1336 The generate instruction sequence for accessing global variable
1337 is:
1339 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1341 Only one instruction needed. But we must initialize
1342 pic_offset_table_rtx properly. We generate initialize insn for
1343 every global access, and allow CSE to remove all redundant.
1345 The final instruction sequences will look like the following
1346 for multiply global variables access.
1348 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1350 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1351 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1352 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1353 ... */
1362 }
1365 {
1368 else
1372 }
1373 else
1374 {
1379 }
1381 /* The operand is expected to be MEM. Whenever the related insn
1382 pattern changed, above code which calculate mem should be
1383 updated. */
1389 }
1392 {
1393 /* In ILP32, the mode of dest can be either SImode or DImode,
1394 while the got entry is always of SImode size. The mode of
1395 dest depends on how dest is used: if dest is assigned to a
1396 pointer (e.g. in the memory), it has SImode; it may have
1397 DImode if dest is dereferenced to access the memeory.
1398 This is why we have to handle three different ldr_got_small
1399 patterns here (two patterns for ILP32). */
1401 rtx insn;
1402 rtx mem;
1411 {
1414 else
1418 }
1419 else
1420 {
1425 }
1432 }
1435 {
1443 else
1451 }
1454 {
1457 rtx tp;
1461 /* In ILP32, the got entry is always of SImode size. Unlike
1462 small GOT, the dest is fixed at reg 0. */
1465 else
1475 }
1478 {
1479 /* In ILP32, the mode of dest can be either SImode or DImode,
1480 while the got entry is always of SImode size. The mode of
1481 dest depends on how dest is used: if dest is assigned to a
1482 pointer (e.g. in the memory), it has SImode; it may have
1483 DImode if dest is dereferenced to access the memeory.
1484 This is why we have to handle three different tlsie_small
1485 patterns here (two patterns for ILP32). */
1491 {
1494 else
1495 {
1498 }
1499 }
1500 else
1501 {
1504 }
1509 }
1515 {
1523 {
1546 }
1550 }
1557 {
1562 {
1565 else
1566 {
1569 }
1570 }
1571 else
1572 {
1575 }
1579 }
1583 }
1584 }
1586 /* Emit a move from SRC to DEST. Assume that the move expanders can
1587 handle all moves if !can_create_pseudo_p (). The distinction is
1588 important because, unlike emit_move_insn, the move expanders know
1589 how to force Pmode objects into the constant pool even when the
1590 constant pool address is not itself legitimate. */
1591 static rtx
1593 {
1597 }
1599 /* Split a 128-bit move operation into two 64-bit move operations,
1600 taking care to handle partial overlap of register to register
1601 copies. Special cases are needed when moving between GP regs and
1602 FP regs. SRC can be a register, constant or memory; DST a register
1603 or memory. If either operand is memory it must not have any side
1604 effects. */
1605 void
1607 {
1618 {
1622 /* Handle FP <-> GP regs. */
1624 {
1629 {
1632 }
1633 else
1634 {
1637 }
1639 }
1641 {
1646 {
1649 }
1650 else
1651 {
1654 }
1656 }
1657 }
1664 /* At most one pairing may overlap. */
1666 {
1669 }
1670 else
1671 {
1674 }
1675 }
1677 bool
1679 {
1682 }
1684 /* Split a complex SIMD combine. */
1686 void
1688 {
1700 {
1724 }
1728 }
1730 /* Split a complex SIMD move. */
1732 void
1734 {
1741 {
1747 {
1771 }
1775 }
1776 }
1778 bool
1781 {
1785 }
1788 static rtx
1790 {
1793 else
1794 {
1797 }
1798 }
1801 static rtx
1803 {
1805 {
1806 rtx high;
1807 /* Load the full offset into a register. This
1808 might be improvable in the future. */
1814 }
1816 }
1818 static int
1820 machine_mode mode)
1821 {
1830 {
1834 }
1836 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
1837 (with XXXX non-zero). In that case check to see if the move can be done in
1838 a smaller mode. */
1843 {
1847 /* Check if we have to emit a second instruction by checking to see
1848 if any of the upper 32 bits of the original DI mode value is set. */
1859 }
1862 {
1864 {
1869 else
1872 }
1874 }
1876 /* Remaining cases are all for DImode. */
1885 {
1886 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1887 For a 64-bit bitmask try whether changing 16 bits to all ones or
1888 zeroes creates a valid bitmask. To check any repeated bitmask,
1889 try using 16 bits from the other 32-bit half of val. */
1892 {
1903 }
1905 {
1907 {
1911 }
1913 }
1914 }
1916 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1917 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1918 otherwise skip zero bits. */
1930 {
1936 num_insns ++;
1937 }
1940 }
1943 void
1945 {
1950 /* Check on what type of symbol it is. */
1954 {
1958 /* If we have (const (plus symbol offset)), separate out the offset
1959 before we start classifying the symbol. */
1964 {
1968 {
1974 }
1979 /* If we aren't generating PC relative literals, then
1980 we need to expand the literal pool access carefully.
1981 This is something that needs to be done in a number
1982 of places, so could well live as a separate function. */
1984 {
1991 }
2008 {
2014 }
2015 /* FALLTHRU */
2028 }
2029 }
2032 {
2035 else
2036 {
2040 }
2043 }
2046 }
2048 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
2049 temporary value if necessary. FRAME_RELATED_P should be true if
2050 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
2051 to the generated instructions. If SCRATCHREG is known to hold
2052 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
2053 immediate again.
2055 Since this function may be used to adjust the stack pointer, we must
2056 ensure that it cannot cause transient stack deallocation (for example
2057 by first incrementing SP and then decrementing when adjusting by a
2058 large immediate). */
2060 static void
2064 {
2072 /* Single instruction adjustment. */
2074 {
2078 }
2080 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2081 Only do this if mdelta is not a 16-bit move as adjusting using a move
2082 is better. */
2084 {
2093 }
2095 /* Emit a move immediate if required and an addition/subtraction. */
2102 {
2106 }
2107 }
2111 HOST_WIDE_INT delta)
2112 {
2114 }
2118 {
2121 }
2125 {
2128 }
2130 static bool
2132 tree exp ATTRIBUTE_UNUSED)
2133 {
2134 /* Currently, always true. */
2136 }
2138 /* Implement TARGET_PASS_BY_REFERENCE. */
2140 static bool
2142 machine_mode mode,
2143 const_tree type,
2145 {
2146 HOST_WIDE_INT size;
2147 machine_mode dummymode;
2150 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2154 /* Aggregates are passed by reference based on their size. */
2156 {
2158 }
2160 /* Variable sized arguments are always returned by reference. */
2164 /* Can this be a candidate to be passed in fp/simd register(s)? */
2167 NULL))
2170 /* Arguments which are variable sized or larger than 2 registers are
2171 passed by reference unless they are a homogenous floating point
2172 aggregate. */
2174 }
2176 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2177 static bool
2179 {
2180 machine_mode dummy_mode;
2183 /* Never happens in little-endian mode. */
2187 /* Only composite types smaller than or equal to 16 bytes can
2188 be potentially returned in registers. */
2194 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2195 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2196 is always passed/returned in the least significant bits of fp/simd
2197 register(s). */
2203 }
2205 /* Implement TARGET_FUNCTION_VALUE.
2206 Define how to find the value returned by a function. */
2208 static rtx
2211 {
2212 machine_mode mode;
2215 machine_mode ag_mode;
2222 {
2226 {
2229 }
2230 }
2234 {
2236 {
2239 }
2240 else
2241 {
2243 rtx par;
2247 {
2252 }
2254 }
2255 }
2256 else
2258 }
2260 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2261 Return true if REGNO is the number of a hard register in which the values
2262 of called function may come back. */
2264 static bool
2266 {
2267 /* Maximum of 16 bytes can be returned in the general registers. Examples
2268 of 16-byte return values are: 128-bit integers and 16-byte small
2269 structures (excluding homogeneous floating-point aggregates). */
2273 /* Up to four fp/simd registers can return a function value, e.g. a
2274 homogeneous floating-point aggregate having four members. */
2279 }
2281 /* Implement TARGET_RETURN_IN_MEMORY.
2283 If the type T of the result of a function is such that
2284 void func (T arg)
2285 would require that arg be passed as a value in a register (or set of
2286 registers) according to the parameter passing rules, then the result
2287 is returned in the same registers as would be used for such an
2288 argument. */
2290 static bool
2292 {
2293 HOST_WIDE_INT size;
2294 machine_mode ag_mode;
2300 /* Simple scalar types always returned in registers. */
2304 type,
2307 NULL))
2310 /* Types larger than 2 registers returned in memory. */
2313 }
2315 static bool
2318 {
2321 type,
2323 nregs,
2324 NULL);
2325 }
2327 /* Given MODE and TYPE of a function argument, return the alignment in
2328 bits. The idea is to suppress any stronger alignment requested by
2329 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2330 This is a helper function for local use only. */
2332 static unsigned int
2334 {
2355 }
2357 /* Layout a function argument according to the AAPCS64 rules. The rule
2358 numbers refer to the rule numbers in the AAPCS64. */
2360 static void
2362 const_tree type,
2364 {
2368 HOST_WIDE_INT size;
2370 /* We need to do this once per argument. */
2376 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2377 size
2379 UNITS_PER_WORD);
2383 mode,
2384 type,
2387 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2388 The following code thus handles passing by SIMD/FP registers first. */
2392 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2393 and homogenous short-vector aggregates (HVA). */
2395 {
2400 {
2403 {
2406 }
2407 else
2408 {
2409 rtx par;
2413 {
2416 tmp = gen_rtx_EXPR_LIST
2420 }
2422 }
2424 }
2425 else
2426 {
2427 /* C.3 NSRN is set to 8. */
2430 }
2431 }
2436 /* C6 - C9. though the sign and zero extension semantics are
2437 handled elsewhere. This is the case where the argument fits
2438 entirely general registers. */
2440 {
2444 /* C.8 if the argument has an alignment of 16 then the NGRN is
2445 rounded up to the next even number. */
2448 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
2449 comparison is there because for > 16 * BITS_PER_UNIT
2450 alignment nregs should be > 2 and therefore it should be
2451 passed by reference rather than value. */
2453 {
2456 }
2458 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2459 A reg is still generated for it, but the caller should be smart
2460 enough not to use it. */
2463 else
2464 {
2465 rtx par;
2470 {
2475 }
2477 }
2481 }
2483 /* C.11 */
2486 /* The argument is passed on stack; record the needed number of words for
2487 this argument and align the total size if necessary. */
2488 on_stack:
2495 }
2497 /* Implement TARGET_FUNCTION_ARG. */
2499 static rtx
2502 {
2511 }
2513 void
2515 const_tree fntype ATTRIBUTE_UNUSED,
2516 rtx libname ATTRIBUTE_UNUSED,
2517 const_tree fndecl ATTRIBUTE_UNUSED,
2519 {
2533 {
2540 }
2542 }
2544 static void
2546 machine_mode mode,
2547 const_tree type,
2549 {
2552 {
2562 }
2563 }
2565 bool
2567 {
2570 }
2572 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2573 PARM_BOUNDARY bits of alignment, but will be given anything up
2574 to STACK_BOUNDARY bits if the type requires it. This makes sure
2575 that both before and after the layout of each argument, the Next
2576 Stacked Argument Address (NSAA) will have a minimum alignment of
2577 8 bytes. */
2579 static unsigned int
2581 {
2584 }
2586 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2588 Return true if an argument passed on the stack should be padded upwards,
2589 i.e. if the least-significant byte of the stack slot has useful data.
2591 Small aggregate types are placed in the lowest memory address.
2593 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2595 bool
2597 {
2598 /* On little-endian targets, the least significant byte of every stack
2599 argument is passed at the lowest byte address of the stack slot. */
2603 /* Otherwise, integral, floating-point and pointer types are padded downward:
2604 the least significant byte of a stack argument is passed at the highest
2605 byte address of the stack slot. */
2612 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2614 }
2616 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2618 It specifies padding for the last (may also be the only)
2619 element of a block move between registers and memory. If
2620 assuming the block is in the memory, padding upward means that
2621 the last element is padded after its highest significant byte,
2622 while in downward padding, the last element is padded at the
2623 its least significant byte side.
2625 Small aggregates and small complex types are always padded
2626 upwards.
2628 We don't need to worry about homogeneous floating-point or
2629 short-vector aggregates; their move is not affected by the
2630 padding direction determined here. Regardless of endianness,
2631 each element of such an aggregate is put in the least
2632 significant bits of a fp/simd register.
2634 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2635 register has useful data, and return the opposite if the most
2636 significant byte does. */
2638 bool
2641 {
2643 /* Small composite types are always padded upward. */
2645 {
2650 }
2652 /* Otherwise, use the default padding. */
2654 }
2656 static machine_mode
2658 {
2660 }
2662 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2664 /* We use the 12-bit shifted immediate arithmetic instructions so values
2665 must be multiple of (1 << 12), i.e. 4096. */
2666 #define ARITH_FACTOR 4096
2668 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2669 #error Cannot use simple address calculation for stack probing
2670 #endif
2672 /* The pair of scratch registers used for stack probing. */
2673 #define PROBE_STACK_FIRST_REG 9
2674 #define PROBE_STACK_SECOND_REG 10
2676 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2677 inclusive. These are offsets from the current stack pointer. */
2679 static void
2681 {
2684 /* See the same assertion on PROBE_INTERVAL above. */
2687 /* See if we have a constant small number of probes to generate. If so,
2688 that's the easy case. */
2690 {
2697 }
2699 /* The run-time loop is made up of 8 insns in the generic case while the
2700 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2702 {
2707 stack_pointer_rtx,
2711 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2712 it exceeds SIZE. If only two probes are needed, this will not
2713 generate any code. Then probe at FIRST + SIZE. */
2715 {
2719 }
2723 {
2728 }
2729 else
2731 }
2733 /* Otherwise, do the same as above, but in a loop. Note that we must be
2734 extra careful with variables wrapping around because we might be at
2735 the very top (or the very bottom) of the address space and we have
2736 to be able to handle this case properly; in particular, we use an
2737 equality test for the loop condition. */
2738 else
2739 {
2742 /* Step 1: round SIZE to the previous multiple of the interval. */
2747 /* Step 2: compute initial and final value of the loop counter. */
2749 /* TEST_ADDR = SP + FIRST. */
2753 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2756 {
2760 }
2761 else
2762 {
2765 }
2767 /* Step 3: the loop
2769 do
2770 {
2771 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2772 probe at TEST_ADDR
2773 }
2774 while (TEST_ADDR != LAST_ADDR)
2776 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2777 until it is equal to ROUNDED_SIZE. */
2782 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2783 that SIZE is equal to ROUNDED_SIZE. */
2786 {
2790 {
2795 }
2796 else
2798 }
2799 }
2801 /* Make sure nothing is scheduled before we are done. */
2803 }
2805 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2806 absolute addresses. */
2810 {
2817 /* Loop. */
2820 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2825 /* Probe at TEST_ADDR. */
2828 /* Test if TEST_ADDR == LAST_ADDR. */
2832 /* Branch. */
2838 }
2840 static bool
2842 {
2843 /* In aarch64_override_options_after_change
2844 flag_omit_leaf_frame_pointer turns off the frame pointer by
2845 default. Turn it back on now if we've not got a leaf
2846 function. */
2851 /* Force a frame pointer for EH returns so the return address is at FP+8. */
2856 }
2858 /* Mark the registers that need to be saved by the callee and calculate
2859 the size of the callee-saved registers area and frame record (both FP
2860 and LR may be omitted). */
2861 static void
2863 {
2870 #define SLOT_NOT_REQUIRED (-2)
2871 #define SLOT_REQUIRED (-1)
2876 /* First mark all the registers that really need to be saved... */
2883 /* ... that includes the eh data registers (if needed)... */
2889 /* ... and any callee saved register that dataflow says is live. */
2899 {
2902 }
2905 {
2906 /* FP and LR are placed in the linkage record. */
2912 }
2914 /* Now assign stack slots for them. */
2917 {
2924 }
2932 {
2933 /* If there is an alignment gap between integer and fp callee-saves,
2934 allocate the last fp register to it if possible. */
2936 {
2939 }
2948 }
2954 HOST_WIDE_INT varargs_and_saved_regs_size
2981 {
2982 /* Simple, small frame with no outgoing arguments:
2983 stp reg1, reg2, [sp, -frame_size]!
2984 stp reg3, reg4, [sp, 16] */
2986 }
2991 {
2992 /* Frame with small outgoing arguments:
2993 sub sp, sp, frame_size
2994 stp reg1, reg2, [sp, outgoing_args_size]
2995 stp reg3, reg4, [sp, outgoing_args_size + 16] */
2999 }
3001 {
3002 /* Frame with large outgoing arguments but a small local area:
3003 stp reg1, reg2, [sp, -hard_fp_offset]!
3004 stp reg3, reg4, [sp, 16]
3005 sub sp, sp, outgoing_args_size */
3009 }
3012 {
3013 /* Frame with large local area and outgoing arguments (this pushes the
3014 callee-saves first, followed by the locals and outgoing area):
3015 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
3016 stp reg3, reg4, [sp, 16]
3017 sub sp, sp, frame_size - varargs_and_saved_regs_size */
3023 }
3024 else
3025 {
3026 /* Frame with large local area and outgoing arguments using frame pointer:
3027 sub sp, sp, hard_fp_offset
3028 stp x29, x30, [sp, 0]
3029 add x29, sp, 0
3030 stp reg3, reg4, [sp, 16]
3031 sub sp, sp, outgoing_args_size */
3035 }
3038 }
3040 /* Return true if the register REGNO is saved on entry to
3041 the current function. */
3043 static bool
3045 {
3047 }
3049 /* Return the next register up from REGNO up to LIMIT for the callee
3050 to save. */
3052 static unsigned
3054 {
3056 regno ++;
3058 }
3060 /* Push the register number REGNO of mode MODE to the stack with write-back
3061 adjusting the stack by ADJUSTMENT. */
3063 static void
3065 HOST_WIDE_INT adjustment)
3066 {
3077 }
3079 /* Generate and return an instruction to store the pair of registers
3080 REG and REG2 of mode MODE to location BASE with write-back adjusting
3081 the stack location BASE by ADJUSTMENT. */
3083 static rtx
3085 HOST_WIDE_INT adjustment)
3086 {
3088 {
3099 }
3100 }
3102 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3103 stack pointer by ADJUSTMENT. */
3105 static void
3107 {
3122 }
3124 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3125 adjusting it by ADJUSTMENT afterwards. */
3127 static rtx
3129 HOST_WIDE_INT adjustment)
3130 {
3132 {
3141 }
3142 }
3144 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3145 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3146 into CFI_OPS. */
3148 static void
3151 {
3158 {
3162 }
3163 else
3164 {
3169 }
3170 }
3172 /* Generate and return a store pair instruction of mode MODE to store
3173 register REG1 to MEM1 and register REG2 to MEM2. */
3175 static rtx
3177 rtx reg2)
3178 {
3180 {
3189 }
3190 }
3192 /* Generate and regurn a load pair isntruction of mode MODE to load register
3193 REG1 from MEM1 and register REG2 from MEM2. */
3195 static rtx
3197 rtx mem2)
3198 {
3200 {
3209 }
3210 }
3212 /* Return TRUE if return address signing should be enabled for the current
3213 function, otherwise return FALSE. */
3215 bool
3217 {
3218 /* This function should only be called after frame laid out. */
3221 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3222 if it's LR is pushed onto stack. */
3226 }
3228 /* Emit code to save the callee-saved registers from register number START
3229 to LIMIT to the stack at the location starting at offset START_OFFSET,
3230 skipping any write-back candidates if SKIP_WB is true. */
3232 static void
3235 {
3243 {
3245 HOST_WIDE_INT offset;
3258 offset));
3267 {
3269 rtx mem2;
3273 offset));
3275 reg2));
3277 /* The first part of a frame-related parallel insn is
3278 always assumed to be relevant to the frame
3279 calculations; subsequent parts, are only
3280 frame-related if explicitly marked. */
3283 }
3284 else
3288 }
3289 }
3291 /* Emit code to restore the callee registers of mode MODE from register
3292 number START up to and including LIMIT. Restore from the stack offset
3293 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3294 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3296 static void
3300 {
3304 HOST_WIDE_INT offset;
3309 {
3330 {
3332 rtx mem2;
3340 }
3341 else
3344 }
3345 }
3349 HOST_WIDE_INT offset)
3350 {
3352 }
3356 {
3360 }
3362 bool
3364 {
3368 }
3370 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3372 static sbitmap
3374 {
3380 /* The registers we need saved to the frame. */
3383 {
3388 /* Check that we can access the stack slot of the register with one
3389 direct load with no adjustments needed. */
3392 }
3394 /* Don't mess with the hard frame pointer. */
3400 /* If aarch64_layout_frame has chosen registers to store/restore with
3401 writeback don't interfere with them to avoid having to output explicit
3402 stack adjustment instructions. */
3412 }
3414 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3416 static sbitmap
3418 {
3426 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3435 }
3437 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3438 Nothing to do for aarch64. */
3440 static void
3442 {
3443 }
3445 /* Return the next set bit in BMP from START onwards. Return the total number
3446 of bits in BMP if no set bit is found at or after START. */
3448 static unsigned int
3450 {
3461 }
3463 /* Do the work for aarch64_emit_prologue_components and
3464 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3465 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3466 for these components or the epilogue sequence. That is, it determines
3467 whether we should emit stores or loads and what kind of CFA notes to attach
3468 to the insns. Otherwise the logic for the two sequences is very
3469 similar. */
3471 static void
3473 {
3475 ? HARD_FRAME_POINTER_REGNUM
3483 {
3484 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3485 so DFmode for the vector registers is enough. */
3497 /* No more registers to handle after REGNO.
3498 Emit a single save/restore and exit. */
3500 {
3505 else
3508 }
3511 /* The next register is not of the same class or its offset is not
3512 mergeable with the current one into a pair. */
3517 {
3522 else
3527 }
3529 /* REGNO2 can be saved/restored in a pair with REGNO. */
3541 else
3546 {
3549 }
3550 else
3551 {
3554 }
3557 }
3558 }
3560 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3562 static void
3564 {
3566 }
3568 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3570 static void
3572 {
3574 }
3576 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3578 static void
3580 {
3584 }
3586 /* AArch64 stack frames generated by this compiler look like:
3588 +-------------------------------+
3589 | |
3590 | incoming stack arguments |
3591 | |
3592 +-------------------------------+
3593 | | <-- incoming stack pointer (aligned)
3594 | callee-allocated save area |
3595 | for register varargs |
3596 | |
3597 +-------------------------------+
3598 | local variables | <-- frame_pointer_rtx
3599 | |
3600 +-------------------------------+
3601 | padding0 | \
3602 +-------------------------------+ |
3603 | callee-saved registers | | frame.saved_regs_size
3604 +-------------------------------+ |
3605 | LR' | |
3606 +-------------------------------+ |
3607 | FP' | / <- hard_frame_pointer_rtx (aligned)
3608 +-------------------------------+
3609 | dynamic allocation |
3610 +-------------------------------+
3611 | padding |
3612 +-------------------------------+
3613 | outgoing stack arguments | <-- arg_pointer
3614 | |
3615 +-------------------------------+
3616 | | <-- stack_pointer_rtx (aligned)
3618 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3619 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3620 unchanged. */
3622 /* Generate the prologue instructions for entry into a function.
3623 Establish the stack frame by decreasing the stack pointer with a
3624 properly calculated size and, if necessary, create a frame record
3625 filled with the values of LR and previous frame pointer. The
3626 current FP is also set up if it is in use. */
3628 void
3630 {
3642 /* Sign return address for functions. */
3644 {
3648 }
3654 {
3656 {
3660 }
3663 }
3671 {
3676 stack_pointer_rtx,
3680 }
3687 }
3689 /* Return TRUE if we can use a simple_return insn.
3691 This function checks whether the callee saved stack is empty, which
3692 means no restore actions are need. The pro_and_epilogue will use
3693 this to check whether shrink-wrapping opt is feasible. */
3695 bool
3697 {
3707 }
3709 /* Generate the epilogue instructions for returning from a function.
3710 This is almost exactly the reverse of the prolog sequence, except
3711 that we need to insert barriers to avoid scheduling loads that read
3712 from a deallocated stack, and we optimize the unwind records by
3713 emitting them all together if possible. */
3714 void
3716 {
3728 /* We need to add memory barrier to prevent read from deallocated stack. */
3732 /* Emit a barrier to prevent loads from a deallocated stack. */
3735 {
3738 }
3740 /* Restore the stack pointer from the frame pointer if it may not
3741 be the same as the stack pointer. */
3743 {
3745 hard_frame_pointer_rtx,
3747 /* If writeback is used when restoring callee-saves, the CFA
3748 is restored on the instruction doing the writeback. */
3750 }
3751 else
3766 {
3767 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3773 }
3778 {
3779 /* Emit delayed restores and reset the CFA to be SP. */
3784 }
3786 /* We prefer to emit the combined return/authenticate instruction RETAA,
3787 however there are three cases in which we must instead emit an explicit
3788 authentication instruction.
3790 1) Sibcalls don't return in a normal way, so if we're about to call one
3791 we must authenticate.
3793 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3794 generating code for !TARGET_ARMV8_3 we can't use it and must
3795 explicitly authenticate.
3797 3) On an eh_return path we make extra stack adjustments to update the
3798 canonical frame address to be the exception handler's CFA. We want
3799 to authenticate using the CFA of the function which calls eh_return.
3800 */
3803 {
3807 }
3809 /* Stack adjustment for exception handler. */
3811 {
3812 /* We need to unwind the stack by the offset computed by
3813 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3814 to be SP; letting the CFA move during this adjustment
3815 is just as correct as retaining the CFA from the body
3816 of the function. Therefore, do nothing special. */
3818 }
3823 }
3825 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3826 normally or return to a previous frame after unwinding.
3828 An EH return uses a single shared return sequence. The epilogue is
3829 exactly like a normal epilogue except that it has an extra input
3830 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3831 that must be applied after the frame has been destroyed. An extra label
3832 is inserted before the epilogue which initializes this register to zero,
3833 and this is the entry point for a normal return.
3835 An actual EH return updates the return address, initializes the stack
3836 adjustment and jumps directly into the epilogue (bypassing the zeroing
3837 of the adjustment). Since the return address is typically saved on the
3838 stack when a function makes a call, the saved LR must be updated outside
3839 the epilogue.
3841 This poses problems as the store is generated well before the epilogue,
3842 so the offset of LR is not known yet. Also optimizations will remove the
3843 store as it appears dead, even after the epilogue is generated (as the
3844 base or offset for loading LR is different in many cases).
3846 To avoid these problems this implementation forces the frame pointer
3847 in eh_return functions so that the location of LR is fixed and known early.
3848 It also marks the store volatile, so no optimization is permitted to
3849 remove the store. */
3850 rtx
3852 {
3856 /* Mark the store volatile, so no optimization is permitted to remove it. */
3859 }
3861 /* Output code to add DELTA to the first argument, and then jump
3862 to FUNCTION. Used for C++ multiple inheritance. */
3863 static void
3865 HOST_WIDE_INT delta,
3866 HOST_WIDE_INT vcall_offset,
3867 tree function)
3868 {
3869 /* The this pointer is always in x0. Note that this differs from
3870 Arm where the this pointer maybe bumped to r1 if r0 is required
3871 to return a pointer to an aggregate. On AArch64 a result value
3872 pointer will be in x8. */
3882 else
3883 {
3892 {
3896 else
3898 }
3902 else
3909 else
3910 {
3912 Pmode);
3914 }
3918 else
3924 }
3926 /* Generate a tail call to the target function. */
3928 {
3931 }
3943 /* Stop pretending to be a post-reload pass. */
3945 }
3947 static bool
3949 {
3954 {
3958 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3959 TLS offsets, not real symbol references. */
3962 }
3964 }
3967 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3968 a left shift of 0 or 12 bits. */
3969 bool
3971 {
3974 );
3975 }
3978 /* Return true if val is an immediate that can be loaded into a
3979 register by a MOVZ instruction. */
3980 static bool
3982 {
3984 {
3988 }
3989 else
3990 {
3991 /* Ignore sign extension. */
3993 }
3996 }
3998 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
4001 {
4007 };
4010 /* Return true if val is a valid bitmask immediate. */
4012 bool
4014 {
4018 /* Check for a single sequence of one bits and return quickly if so.
4019 The special cases of all ones and all zeroes returns false. */
4026 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
4030 /* Invert if the immediate doesn't start with a zero bit - this means we
4031 only need to search for sequences of one bits. */
4035 /* Find the first set bit and set tmp to val with the first sequence of one
4036 bits removed. Return success if there is a single sequence of ones. */
4043 /* Find the next set bit and compute the difference in bit position. */
4048 /* Check the bit position difference is a power of 2, and that the first
4049 sequence of one bits fits within 'bits' bits. */
4053 /* Check the sequence of one bits is repeated 64/bits times. */
4055 }
4057 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4058 Assumed precondition: VAL_IN Is not zero. */
4060 unsigned HOST_WIDE_INT
4062 {
4069 }
4071 /* Create constant where bits outside of lowest bit set to highest bit set
4072 are set to 1. */
4074 unsigned HOST_WIDE_INT
4076 {
4078 }
4080 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4082 bool
4084 {
4094 }
4096 /* Return true if val is an immediate that can be loaded into a
4097 register in a single instruction. */
4098 bool
4100 {
4104 }
4106 static bool
4108 {
4116 {
4120 else
4121 /* Avoid generating a 64-bit relocation in ILP32; leave
4122 to aarch64_expand_mov_immediate to handle it properly. */
4124 }
4127 }
4129 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4130 The expansion for a table switch is quite expensive due to the number
4131 of instructions, the table lookup and hard to predict indirect jump.
4132 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4133 set, otherwise use tables for > 16 cases as a tradeoff between size and
4134 performance. When optimizing for size, use the default setting. */
4136 static unsigned int
4138 {
4139 /* Use the specified limit for the number of cases before using jump
4140 tables at higher optimization levels. */
4144 else
4146 }
4148 /* Return true if register REGNO is a valid index register.
4149 STRICT_P is true if REG_OK_STRICT is in effect. */
4151 bool
4153 {
4155 {
4163 }
4165 }
4167 /* Return true if register REGNO is a valid base register for mode MODE.
4168 STRICT_P is true if REG_OK_STRICT is in effect. */
4170 bool
4172 {
4174 {
4182 }
4184 /* The fake registers will be eliminated to either the stack or
4185 hard frame pointer, both of which are usually valid base registers.
4186 Reload deals with the cases where the eliminated form isn't valid. */
4191 }
4193 /* Return true if X is a valid base register for mode MODE.
4194 STRICT_P is true if REG_OK_STRICT is in effect. */
4196 static bool
4198 {
4203 }
4205 /* Return true if address offset is a valid index. If it is, fill in INFO
4206 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4208 static bool
4211 {
4213 rtx index;
4216 /* (reg:P) */
4219 {
4223 }
4224 /* (sign_extend:DI (reg:SI)) */
4229 {
4234 }
4235 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4242 {
4247 }
4248 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4255 {
4260 }
4261 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4268 {
4276 }
4277 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4278 (const_int 0xffffffff<<shift)) */
4285 {
4291 }
4292 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4299 {
4307 }
4308 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4309 (const_int 0xffffffff<<shift)) */
4316 {
4322 }
4323 /* (mult:P (reg:P) (const_int scale)) */
4328 {
4332 }
4333 /* (ashift:P (reg:P) (const_int shift)) */
4338 {
4342 }
4343 else
4354 {
4359 }
4362 }
4364 /* Return true if MODE is one of the modes for which we
4365 support LDP/STP operations. */
4367 static bool
4369 {
4374 }
4376 /* Return true if REGNO is a virtual pointer register, or an eliminable
4377 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4378 include stack_pointer or hard_frame_pointer. */
4379 static bool
4381 {
4386 }
4388 /* Return true if X is a valid address for machine mode MODE. If it is,
4389 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4390 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4392 static bool
4396 {
4400 /* On BE, we use load/store pair for all large int mode load/stores.
4401 TI/TFmode may also use a load/store pair. */
4405 || (BYTES_BIG_ENDIAN
4409 !load_store_pair_p
4413 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4414 REG addressing. */
4420 {
4436 {
4442 }
4447 {
4454 /* TImode and TFmode values are allowed in both pairs of X
4455 registers and individual Q registers. The available
4456 address modes are:
4457 X,X: 7-bit signed scaled offset
4458 Q: 9-bit signed offset
4459 We conservatively require an offset representable in either mode.
4460 When performing the check for pairs of X registers i.e. LDP/STP
4461 pass down DImode since that is the natural size of the LDP/STP
4462 instruction memory accesses. */
4468 /* A 7bit offset check because OImode will emit a ldp/stp
4469 instruction (only big endian will get here).
4470 For ldp/stp instructions, the offset is scaled for the size of a
4471 single element of the pair. */
4475 /* Three 9/12 bit offsets checks because CImode will emit three
4476 ldr/str instructions (only big endian will get here). */
4483 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4484 instructions (only big endian will get here). */
4493 else
4496 }
4499 {
4500 /* Look for base + (scaled/extended) index register. */
4503 {
4506 }
4509 {
4512 }
4513 }
4534 {
4535 HOST_WIDE_INT offset;
4539 /* TImode and TFmode values are allowed in both pairs of X
4540 registers and individual Q registers. The available
4541 address modes are:
4542 X,X: 7-bit signed scaled offset
4543 Q: 9-bit signed offset
4544 We conservatively require an offset representable in either mode.
4545 */
4553 else
4555 }
4561 /* load literal: pc-relative constant pool entry. Only supported
4562 for SI mode or larger. */
4566 {
4574 }
4583 {
4588 {
4589 /* The symbol and offset must be aligned to the access size. */
4596 {
4600 }
4606 else
4615 }
4616 }
4621 }
4622 }
4624 /* Return true if the address X is valid for a PRFM instruction.
4625 STRICT_P is true if we should do strict checking with
4626 aarch64_classify_address. */
4628 bool
4630 {
4633 /* PRFM accepts the same addresses as DImode... */
4638 /* ... except writeback forms. */
4640 }
4642 bool
4644 {
4645 rtx offset;
4649 }
4651 /* Classify the base of symbolic expression X. */
4653 enum aarch64_symbol_type
4655 {
4656 rtx offset;
4660 }
4663 /* Return TRUE if X is a legitimate address for accessing memory in
4664 mode MODE. */
4665 static bool
4667 {
4671 }
4673 /* Return TRUE if X is a legitimate address for accessing memory in
4674 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4675 pair operation. */
4676 bool
4679 {
4683 }
4685 /* Split an out-of-range address displacement into a base and offset.
4686 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4687 to increase opportunities for sharing the base address of different sizes.
4688 For unaligned accesses and TI/TF mode use the signed 9-bit range. */
4689 static bool
4691 {
4702 }
4704 /* Return the binary representation of floating point constant VALUE in INTVAL.
4705 If the value cannot be converted, return false without setting INTVAL.
4706 The conversion is done in the given MODE. */
4707 bool
4709 {
4711 /* We make a general exception for 0. */
4713 {
4716 }
4722 /* Only support up to DF mode. */
4734 {
4738 }
4739 else
4744 }
4746 /* Return TRUE if rtx X is an immediate constant that can be moved using a
4747 single MOV(+MOVK) followed by an FMOV. */
4748 bool
4750 {
4755 /* Determine whether it's cheaper to write float constants as
4756 mov/movk pairs over ldr/adrp pairs. */
4762 {
4767 }
4770 }
4772 /* Return TRUE if rtx X is immediate constant 0.0 */
4773 bool
4775 {
4782 }
4784 /* Return TRUE if rtx X is immediate constant that fits in a single
4785 MOVI immediate operation. */
4786 bool
4788 {
4797 {
4801 /* We make a general exception for 0. */
4806 }
4809 {
4812 }
4813 else
4816 /* use a 64 bit mode for everything except for DI/DF mode, where we use
4817 a 128 bit vector mode. */
4824 }
4827 /* Return the fixed registers used for condition codes. */
4829 static bool
4831 {
4835 }
4837 /* This function is used by the call expanders of the machine description.
4838 RESULT is the register in which the result is returned. It's NULL for
4839 "call" and "sibcall".
4840 MEM is the location of the function call.
4841 SIBCALL indicates whether this function call is normal call or sibling call.
4842 It will generate different pattern accordingly. */
4844 void
4846 {
4848 rtvec vec;
4849 machine_mode mode;
4856 /* Decide if we should generate indirect calls by loading the
4857 address of the callee into a register before performing
4858 the branch-and-link. */
4872 else
4879 }
4881 /* Emit call insn with PAT and do aarch64-specific handling. */
4883 void
4885 {
4891 }
4893 machine_mode
4895 {
4896 /* All floating point compares return CCFP if it is an equality
4897 comparison, and CCFPE otherwise. */
4899 {
4901 {
4922 }
4923 }
4925 /* Equality comparisons of short modes against zero can be performed
4926 using the TST instruction with the appropriate bitmask. */
4932 /* Similarly, comparisons of zero_extends from shorter modes can
4933 be performed using an ANDS with an immediate mask. */
4949 /* A compare with a shifted operand. Because of canonicalization,
4950 the comparison will have to be swapped when we emit the assembly
4951 code. */
4959 /* Similarly for a negated operand, but we can only do this for
4960 equalities. */
4967 /* A test for unsigned overflow. */
4974 /* For everything else, return CCmode. */
4976 }
4978 static int
4981 int
4983 {
4990 }
4992 static int
4994 {
4996 {
5000 {
5014 }
5019 {
5031 }
5036 {
5048 }
5053 {
5059 }
5064 {
5068 }
5073 {
5077 }
5082 }
5085 }
5087 bool
5089 HOST_WIDE_INT minval,
5090 HOST_WIDE_INT maxval)
5091 {
5092 HOST_WIDE_INT firstval;
5109 }
5111 bool
5113 {
5115 }
5118 /* N Z C V. */
5119 #define AARCH64_CC_V 1
5120 #define AARCH64_CC_C (1 << 1)
5121 #define AARCH64_CC_Z (1 << 2)
5122 #define AARCH64_CC_N (1 << 3)
5124 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
5126 {
5143 };
5145 /* Print operand X to file F in a target specific manner according to CODE.
5146 The acceptable formatting commands given by CODE are:
5147 'c': An integer or symbol address without a preceding #
5148 sign.
5149 'e': Print the sign/zero-extend size as a character 8->b,
5150 16->h, 32->w.
5151 'p': Prints N such that 2^N == X (X must be power of 2 and
5152 const int).
5153 'P': Print the number of non-zero bits in X (a const_int).
5154 'H': Print the higher numbered register of a pair (TImode)
5155 of regs.
5156 'm': Print a condition (eq, ne, etc).
5157 'M': Same as 'm', but invert condition.
5158 'b/h/s/d/q': Print a scalar FP/SIMD register name.
5159 'S/T/U/V': Print a FP/SIMD register name for a register list.
5160 The register printed is the FP/SIMD register name
5161 of X + 0/1/2/3 for S/T/U/V.
5162 'R': Print a scalar FP/SIMD register name + 1.
5163 'X': Print bottom 16 bits of integer constant in hex.
5164 'w/x': Print a general register name or the zero register
5165 (32-bit or 64-bit).
5166 '0': Print a normal operand, if it's a general register,
5167 then we assume DImode.
5168 'k': Print NZCV for conditional compare instructions.
5169 'A': Output address constant representing the first
5170 argument of X, specifying a relocation offset
5171 if appropriate.
5172 'L': Output constant address specified by X
5173 with a relocation offset if appropriate.
5174 'G': Prints address of X, specifying a PC relative
5175 relocation mode if appropriate. */
5177 static void
5179 {
5181 {
5184 {
5196 {
5199 }
5200 /* Fall through. */
5204 }
5208 {
5213 {
5216 }
5219 {
5232 }
5233 }
5237 {
5241 {
5244 }
5247 }
5252 {
5255 }
5262 {
5265 }
5272 {
5274 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5276 {
5280 }
5283 {
5286 }
5293 }
5302 {
5303 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5305 }
5314 {
5315 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5317 }
5323 {
5324 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5326 }
5332 {
5335 }
5343 {
5346 }
5349 {
5352 }
5355 {
5358 }
5360 /* Fall through */
5364 {
5367 }
5370 {
5377 /* Check all memory references are Pmode - even with ILP32. */
5393 {
5396 HOST_WIDE_INT_MIN,
5397 HOST_WIDE_INT_MAX));
5399 }
5401 {
5403 }
5404 else
5409 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5410 be getting CONST_DOUBLEs holding integers. */
5413 {
5416 }
5418 {
5419 #define buf_size 20
5427 #undef buf_size
5428 }
5434 }
5442 {
5469 }
5475 {
5510 }
5516 {
5522 }
5527 {
5528 HOST_WIDE_INT cond_code;
5531 {
5534 }
5539 }
5545 }
5546 }
5548 static void
5550 {
5555 {
5559 else
5568 else
5577 else
5586 else
5593 {
5620 }
5631 }
5634 }
5636 bool
5638 {
5645 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5646 referencing instruction, but they are constant offsets, not
5647 symbols. */
5653 {
5655 {
5661 }
5664 }
5667 }
5669 /* Implement REGNO_REG_CLASS. */
5671 enum reg_class
5673 {
5688 }
5690 static rtx
5692 {
5693 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5694 where mask is selected by alignment and size of the offset.
5695 We try to pick as large a range for the offset as possible to
5696 maximize the chance of a CSE. However, for aligned addresses
5697 we limit the range to 4k so that structures with different sized
5698 elements are likely to use the same base. We need to be careful
5699 not to split a CONST for some forms of address expression, otherwise
5700 it will generate sub-optimal code. */
5703 {
5709 {
5713 /* Force any scaling into a temp for CSE. */
5717 /* Let the pointer register be in op0. */
5721 /* If the pointer is virtual or frame related, then we know that
5722 virtual register instantiation or register elimination is going
5723 to apply a second constant. We want the two constants folded
5724 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5726 {
5730 }
5732 /* Otherwise, in order to encourage CSE (and thence loop strength
5733 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5737 }
5739 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5740 HOST_WIDE_INT base_offset;
5743 /* For offsets aren't a multiple of the access size, the limit is
5744 -256...255. */
5746 {
5749 /* BLKmode typically uses LDP of X-registers. */
5752 }
5753 /* Small negative offsets are supported. */
5758 /* Use 12-bit offset by access size. */
5759 else
5763 {
5767 }
5768 }
5771 }
5773 /* Return the reload icode required for a constant pool in mode. */
5774 static enum insn_code
5776 {
5778 {
5814 }
5817 }
5818 static reg_class_t
5820 reg_class_t rclass,
5821 machine_mode mode,
5823 {
5825 /* If we have to disable direct literal pool loads and stores because the
5826 function is too big, then we need a scratch register. */
5831 {
5834 }
5836 /* Without the TARGET_SIMD instructions we cannot move a Q register
5837 to a Q register directly. We need a scratch. */
5841 {
5847 }
5849 /* A TFmode or TImode memory access should be handled via an FP_REGS
5850 because AArch64 has richer addressing modes for LDR/STR instructions
5851 than LDP/STP instructions. */
5860 }
5862 static bool
5864 {
5865 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5866 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5869 {
5881 }
5882 else
5883 {
5884 /* If we decided that we didn't need a leaf frame pointer but then used
5885 LR in the function, then we'll want a frame pointer after all, so
5886 prevent this elimination to ensure a frame pointer is used. */
5888 && flag_omit_leaf_frame_pointer
5891 }
5894 }
5896 HOST_WIDE_INT
5898 {
5902 {
5909 }
5912 {
5916 }
5919 }
5921 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5922 previous frame. */
5924 rtx
5926 {
5930 }
5933 static void
5935 {
5937 {
5940 }
5941 else
5942 {
5945 }
5950 }
5952 static void
5954 {
5958 /* Don't need to copy the trailing D-words, we fill those in below. */
5970 /* XXX We should really define a "clear_cache" pattern and use
5971 gen_clear_cache(). */
5976 ptr_mode);
5977 }
5979 static unsigned char
5981 {
5983 {
5990 return
6002 }
6004 }
6006 static reg_class_t
6008 {
6013 {
6019 }
6021 /* Register eliminiation can result in a request for
6022 SP+constant->FP_REGS. We cannot support such operations which
6023 use SP as source and an FP_REG as destination, so reject out
6024 right now. */
6026 {
6029 /* Look through a possible SUBREG introduced by ILP32. */
6035 POINTER_REGS));
6037 }
6040 }
6042 void
6044 {
6046 }
6048 static void
6050 {
6053 else
6054 {
6056 /* While priority is known to be in range [0, 65535], so 18 bytes
6057 would be enough, the compiler might not know that. To avoid
6058 -Wformat-truncation false positive, use a larger size. */
6065 }
6066 }
6068 static void
6070 {
6073 else
6074 {
6076 /* While priority is known to be in range [0, 65535], so 18 bytes
6077 would be enough, the compiler might not know that. To avoid
6078 -Wformat-truncation false positive, use a larger size. */
6085 }
6086 }
6090 {
6096 {
6097 {
6100 },
6101 {
6104 },
6105 {
6108 },
6109 /* We assume that DImode is only generated when not optimizing and
6110 that we don't really need 64-bit address offsets. That would
6111 imply an object file with 8GB of code in a single function! */
6112 {
6115 }
6116 };
6124 /* Need to implement table size reduction, by chaning the code below. */
6134 }
6137 /* Return size in bits of an arithmetic operand which is shifted/scaled and
6138 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
6139 operator. */
6141 int
6143 {
6145 {
6148 {
6152 }
6153 }
6155 }
6157 /* Constant pools are per function only when PC relative
6158 literal loads are true or we are in the large memory
6159 model. */
6163 {
6166 }
6168 static bool
6170 {
6171 /* Fixme:: In an ideal world this would work similar
6172 to the logic in aarch64_select_rtx_section but this
6173 breaks bootstrap in gcc go. For now we workaround
6174 this by returning false here. */
6176 }
6178 /* Select appropriate section for constants depending
6179 on where we place literal pools. */
6183 rtx x,
6185 {
6190 }
6192 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
6193 void
6195 HOST_WIDE_INT offset)
6196 {
6197 /* When using per-function literal pools, we must ensure that any code
6198 section is aligned to the minimal instruction length, lest we get
6199 errors from the assembler re "unaligned instructions". */
6202 }
6204 /* Costs. */
6206 /* Helper function for rtx cost calculation. Strip a shift expression
6207 from X. Returns the inner operand if successful, or the original
6208 expression on failure. */
6209 static rtx
6211 {
6214 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
6215 we can convert both to ROR during final output. */
6230 }
6232 /* Helper function for rtx cost calculation. Strip an extend
6233 expression from X. Returns the inner operand if successful, or the
6234 original expression on failure. We deal with a number of possible
6235 canonicalization variations here. If STRIP_SHIFT is true, then
6236 we can strip off a shift also. */
6237 static rtx
6239 {
6242 /* Zero and sign extraction of a widened value. */
6250 /* It can also be represented (for zero-extend) as an AND with an
6251 immediate. */
6260 /* Now handle extended register, as this may also have an optional
6261 left shift by 1..4. */
6276 }
6278 /* Return true iff CODE is a shift supported in combination
6279 with arithmetic instructions. */
6281 static bool
6283 {
6285 }
6288 /* Return true iff X is a cheap shift without a sign extend. */
6290 static bool
6292 {
6318 }
6320 /* Helper function for rtx cost calculation. Calculate the cost of
6321 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6322 Return the calculated cost of the expression, recursing manually in to
6323 operands where needed. */
6325 static int
6327 {
6343 /* Integer multiply/fma. */
6345 {
6346 /* The multiply will be canonicalized as a shift, cost it as such. */
6350 {
6354 {
6356 {
6357 /* If the shift is considered cheap,
6358 then don't add any cost. */
6360 ;
6362 /* ARITH + shift-by-register. */
6365 /* ARITH + extended register. We don't have a cost field
6366 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6368 else
6369 /* ARITH + shift-by-immediate. */
6371 }
6372 else
6373 /* LSL (immediate). */
6376 }
6377 /* Strip extends as we will have costed them in the case above. */
6384 }
6386 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6387 compound and let the below cases handle it. After all, MNEG is a
6388 special-case alias of MSUB. */
6390 {
6393 }
6395 /* Integer multiplies or FMAs have zero/sign extending variants. */
6400 {
6405 {
6407 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6409 else
6410 /* MUL/SMULL/UMULL. */
6412 }
6415 }
6417 /* This is either an integer multiply or a MADD. In both cases
6418 we want to recurse and cost the operands. */
6423 {
6425 /* MADD/MSUB. */
6427 else
6428 /* MUL. */
6430 }
6433 }
6434 else
6435 {
6437 {
6438 /* Floating-point FMA/FMUL can also support negations of the
6439 operands, unless the rounding mode is upward or downward in
6440 which case FNMUL is different than FMUL with operand negation. */
6444 {
6449 }
6452 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6454 else
6455 /* FMUL/FNMUL. */
6457 }
6462 }
6463 }
6465 static int
6467 machine_mode mode,
6468 addr_space_t as ATTRIBUTE_UNUSED,
6470 {
6478 {
6480 {
6481 /* This is a CONST or SYMBOL ref which will be split
6482 in a different way depending on the code model in use.
6483 Cost it through the generic infrastructure. */
6485 /* Divide through by the cost of one instruction to
6486 bring it to the same units as the address costs. */
6488 /* The cost is then the cost of preparing the address,
6489 followed by an immediate (possibly 0) offset. */
6491 }
6492 else
6493 {
6494 /* This is most likely a jump table from a case
6495 statement. */
6497 }
6498 }
6501 {
6513 else
6532 }
6536 {
6537 /* For the sake of calculating the cost of the shifted register
6538 component, we can treat same sized modes in the same way. */
6540 {
6553 /* We can't tell, or this is a 128-bit vector. */
6557 }
6558 }
6561 }
6563 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6564 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6565 to be taken. */
6567 int
6569 {
6570 /* When optimizing for speed, use the cost of unpredictable branches. */
6576 else
6578 }
6580 /* Return true if the RTX X in mode MODE is a zero or sign extract
6581 usable in an ADD or SUB (extended register) instruction. */
6582 static bool
6584 {
6585 /* Catch add with a sign extract.
6586 This is add_<optab><mode>_multp2. */
6589 {
6600 op1))
6601 {
6603 }
6604 }
6605 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6606 No shift. */
6612 }
6614 static bool
6616 {
6618 {
6630 }
6631 }
6633 /* Return true iff X is an rtx that will match an extr instruction
6634 i.e. as described in the *extr<mode>5_insn family of patterns.
6635 OP0 and OP1 will be set to the operands of the shifts involved
6636 on success and will be NULL_RTX otherwise. */
6638 static bool
6640 {
6655 {
6656 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6668 {
6672 }
6673 }
6676 }
6678 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6679 storing it in *COST. Result is true if the total cost of the operation
6680 has now been calculated. */
6681 static bool
6683 {
6684 rtx inner;
6685 rtx comparator;
6689 {
6693 }
6694 else
6695 {
6699 }
6702 {
6703 /* Conditional branch. */
6706 else
6707 {
6709 {
6711 {
6712 /* TBZ/TBNZ/CBZ/CBNZ. */
6714 /* TBZ/TBNZ. */
6717 else
6718 /* CBZ/CBNZ. */
6722 }
6723 }
6725 {
6726 /* TBZ/TBNZ. */
6729 }
6730 }
6731 }
6733 {
6734 /* CCMP. */
6736 {
6737 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6741 {
6748 else
6750 }
6752 }
6754 /* It's a conditional operation based on the status flags,
6755 so it must be some flavor of CSEL. */
6757 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6763 {
6764 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6767 }
6772 }
6774 /* We don't know what this is, cost all operands. */
6776 }
6778 /* Check whether X is a bitfield operation of the form shift + extend that
6779 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6780 operand to which the bitfield operation is applied. Otherwise return
6781 NULL_RTX. */
6783 static rtx
6785 {
6799 {
6817 }
6820 }
6822 /* Return true if the mask and a shift amount from an RTX of the form
6823 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6824 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6826 bool
6828 {
6833 }
6835 /* Calculate the cost of calculating X, storing it in *COST. Result
6836 is true if the total cost of the operation has now been calculated. */
6837 static bool
6840 {
6846 /* By default, assume that everything has equivalent cost to the
6847 cheapest instruction. Any additional costs are applied as a delta
6848 above this default. */
6852 {
6854 /* The cost depends entirely on the operands to SET. */
6860 {
6863 {
6877 }
6886 /* Fall through. */
6888 /* The cost is one per vector-register copied. */
6890 {
6894 }
6895 /* const0_rtx is in general free, but we will use an
6896 instruction to set a register to 0. */
6898 {
6899 /* The cost is 1 per register copied. */
6903 }
6904 else
6905 /* Cost is just the cost of the RHS of the set. */
6911 /* Bit-field insertion. Strip any redundant widening of
6912 the RHS to meet the width of the target. */
6923 {
6924 /* MOV immediate is assumed to always be cheap. */
6926 }
6927 else
6928 {
6929 /* BFM. */
6933 }
6938 /* We can't make sense of this, assume default cost. */
6941 }
6945 /* If an instruction can incorporate a constant within the
6946 instruction, the instruction's expression avoids calling
6947 rtx_cost() on the constant. If rtx_cost() is called on a
6948 constant, then it is usually because the constant must be
6949 moved into a register by one or more instructions.
6951 The exception is constant 0, which can be expressed
6952 as XZR/WZR and is therefore free. The exception to this is
6953 if we have (set (reg) (const0_rtx)) in which case we must cost
6954 the move. However, we can catch that when we cost the SET, so
6955 we don't need to consider that here. */
6958 else
6959 {
6960 /* To an approximation, building any other constant is
6961 proportionally expensive to the number of instructions
6962 required to build that constant. This is true whether we
6963 are compiling for SPEED or otherwise. */
6966 }
6971 /* First determine number of instructions to do the move
6972 as an integer constant. */
6976 {
6987 }
6990 {
6991 /* mov[df,sf]_aarch64. */
6993 /* FMOV (scalar immediate). */
6996 {
6997 /* This will be a load from memory. */
7000 else
7002 }
7003 else
7004 /* Otherwise this is +0.0. We get this using MOVI d0, #0
7005 or MOV v0.s[0], wzr - neither of which are modeled by the
7006 cost tables. Just use the default cost. */
7007 {
7008 }
7009 }
7015 {
7016 /* For loads we want the base cost of a load, plus an
7017 approximation for the additional cost of the addressing
7018 mode. */
7032 }
7040 {
7042 {
7043 /* FNEG. */
7045 }
7047 }
7050 {
7053 {
7054 /* CSETM. */
7057 }
7059 /* Cost this as SUB wzr, X. */
7063 }
7066 {
7067 /* Support (neg(fma...)) as a single instruction only if
7068 sign of zeros is unimportant. This matches the decision
7069 making in aarch64.md. */
7071 {
7072 /* FNMADD. */
7075 }
7077 {
7078 /* FNMUL. */
7081 }
7083 /* FNEG. */
7086 }
7093 {
7096 else
7098 }
7108 {
7112 }
7115 {
7116 /* TODO: A write to the CC flags possibly costs extra, this
7117 needs encoding in the cost tables. */
7120 /* ANDS. */
7122 {
7125 }
7128 {
7129 /* ADDS (and CMN alias). */
7132 }
7135 {
7136 /* SUBS. */
7139 }
7144 {
7145 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
7146 Handle it here directly rather than going to cost_logic
7147 since we know the immediate generated for the TST is valid
7148 so we can avoid creating an intermediate rtx for it only
7149 for costing purposes. */
7156 }
7159 {
7160 /* CMN. */
7167 }
7169 /* CMP.
7171 Compare can freely swap the order of operands, and
7172 canonicalization puts the more complex operation first.
7173 But the integer MINUS logic expects the shift/extend
7174 operation in op1. */
7177 {
7180 }
7182 }
7185 {
7186 /* FCMP. */
7191 {
7193 /* FCMP supports constant 0.0 for no extra cost. */
7195 }
7197 }
7200 {
7201 /* Vector compare. */
7206 {
7207 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
7208 cost. */
7210 }
7212 }
7216 {
7220 cost_minus:
7223 /* Detect valid immediates. */
7229 {
7231 /* SUB(S) (immediate). */
7234 }
7236 /* Look for SUB (extended register). */
7238 {
7246 }
7250 /* Cost this as an FMA-alike operation. */
7254 {
7257 speed);
7259 }
7264 {
7266 {
7267 /* Vector SUB. */
7269 }
7271 {
7272 /* SUB(S). */
7274 }
7276 {
7277 /* FSUB. */
7279 }
7280 }
7282 }
7285 {
7286 rtx new_op0;
7291 cost_plus:
7294 {
7295 /* CSINC. */
7299 }
7304 {
7308 /* ADD (immediate). */
7311 }
7315 /* Look for ADD (extended register). */
7317 {
7325 }
7327 /* Strip any extend, leave shifts behind as we will
7328 cost them through mult_cost. */
7333 {
7335 speed);
7337 }
7342 {
7344 {
7345 /* Vector ADD. */
7347 }
7349 {
7350 /* ADD. */
7352 }
7354 {
7355 /* FADD. */
7357 }
7358 }
7360 }
7366 {
7369 else
7371 }
7376 {
7380 {
7383 else
7385 }
7387 }
7390 {
7397 }
7398 /* Fall through. */
7401 cost_logic:
7406 {
7410 }
7418 {
7419 /* This is a UBFM/SBFM. */
7424 }
7427 {
7429 {
7430 /* We have a mask + shift version of a UBFIZ
7431 i.e. the *andim_ashift<mode>_bfiz pattern. */
7435 {
7442 }
7444 {
7445 /* We possibly get the immediate for free, this is not
7446 modelled. */
7452 }
7453 }
7454 else
7455 {
7458 /* Handle ORN, EON, or BIC. */
7464 /* If we had a shift on op0 then this is a logical-shift-
7465 by-register/immediate operation. Otherwise, this is just
7466 a logical operation. */
7468 {
7470 {
7471 /* Shift by immediate. */
7474 else
7476 }
7477 else
7479 }
7481 /* In both cases we want to cost both operands. */
7486 }
7487 }
7495 {
7496 /* Vector NOT. */
7499 }
7501 /* MVN-shifted-reg. */
7503 {
7510 }
7511 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7512 Handle the second form here taking care that 'a' in the above can
7513 be a shift. */
7515 {
7524 {
7527 else
7529 }
7532 }
7533 /* MVN. */
7542 /* If a value is written in SI mode, then zero extended to DI
7543 mode, the operation will in general be free as a write to
7544 a 'w' register implicitly zeroes the upper bits of an 'x'
7545 register. However, if this is
7547 (set (reg) (zero_extend (reg)))
7549 we must cost the explicit register move. */
7553 {
7556 /* If OP_COST is non-zero, then the cost of the zero extend
7557 is effectively the cost of the inner operation. Otherwise
7558 we have a MOV instruction and we take the cost from the MOV
7559 itself. This is true independently of whether we are
7560 optimizing for space or time. */
7565 }
7567 {
7568 /* All loads can zero extend to any size for free. */
7571 }
7575 {
7580 }
7583 {
7585 {
7586 /* UMOV. */
7588 }
7589 else
7590 {
7591 /* We generate an AND instead of UXTB/UXTH. */
7593 }
7594 }
7599 {
7600 /* LDRSH. */
7602 {
7609 }
7611 }
7615 {
7620 }
7623 {
7626 else
7628 }
7636 {
7638 {
7640 {
7641 /* Vector shift (immediate). */
7643 }
7644 else
7645 {
7646 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7647 aliases. */
7649 }
7650 }
7652 /* We can incorporate zero/sign extend for free. */
7659 }
7660 else
7661 {
7663 {
7665 /* Vector shift (register). */
7667 }
7668 else
7669 {
7671 /* LSLV. */
7677 {
7679 /* We already demanded XEXP (op1, 0) to be REG_P, so
7680 don't recurse into it. */
7682 }
7683 }
7685 }
7695 {
7696 /* ASR (immediate) and friends. */
7698 {
7701 else
7703 }
7707 }
7708 else
7709 {
7711 {
7713 /* Vector shift (register). */
7715 }
7716 else
7717 {
7719 /* ASR (register) and friends. */
7725 {
7727 /* We already demanded XEXP (op1, 0) to be REG_P, so
7728 don't recurse into it. */
7730 }
7731 }
7733 }
7739 {
7740 /* LDR. */
7743 }
7746 {
7747 /* ADRP, followed by ADD. */
7751 }
7754 {
7755 /* ADR. */
7758 }
7761 {
7762 /* One extra load instruction, after accessing the GOT. */
7766 }
7771 /* ADRP/ADD (immediate). */
7778 /* UBFX/SBFX. */
7780 {
7783 else
7785 }
7787 /* We can trust that the immediates used will be correct (there
7788 are no by-register forms), so we need only cost op0. */
7794 /* aarch64_rtx_mult_cost always handles recursion to its
7795 operands. */
7799 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7800 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7801 an unconditional negate. This case should only ever be reached through
7802 the set_smod_pow2_cheap check in expmed.c. */
7806 {
7807 /* We expand to 4 instructions. Reset the baseline. */
7815 }
7817 /* Fall-through. */
7820 {
7821 /* Slighly prefer UMOD over SMOD. */
7828 }
7835 {
7839 /* There is no integer SQRT, so only DIV and UDIV can get
7840 here. */
7842 /* Slighly prefer UDIV over SDIV. */
7844 else
7846 }
7872 {
7875 else
7877 }
7879 /* FMSUB, FNMADD, and FNMSUB are free. */
7886 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7887 and the by-element operand as operand 0. */
7891 /* Catch vector-by-element operations. The by-element operand can
7892 either be (vec_duplicate (vec_select (x))) or just
7893 (vec_select (x)), depending on whether we are multiplying by
7894 a vector or a scalar.
7896 Canonicalization is not very good in these cases, FMA4 will put the
7897 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7908 /* If the remaining parameters are not registers,
7909 get the cost to put them into registers. */
7923 {
7925 {
7926 /*Vector truncate. */
7928 }
7929 else
7931 }
7936 {
7938 {
7939 /*Vector conversion. */
7941 }
7942 else
7944 }
7950 /* Strip the rounding part. They will all be implemented
7951 by the fcvt* family of instructions anyway. */
7953 {
7962 }
7965 {
7968 else
7970 }
7972 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7973 fixed-point fcvt. */
7978 {
7982 }
7989 {
7990 /* ABS (vector). */
7993 }
7995 {
7998 /* FABD, which is analogous to FADD. */
8000 {
8007 }
8008 /* Simple FABS is analogous to FNEG. */
8011 }
8012 else
8013 {
8014 /* Integer ABS will either be split to
8015 two arithmetic instructions, or will be an ABS
8016 (scalar), which we don't model. */
8020 }
8026 {
8029 else
8030 {
8031 /* FMAXNM/FMINNM/FMAX/FMIN.
8032 TODO: This may not be accurate for all implementations, but
8033 we do not model this in the cost tables. */
8035 }
8036 }
8040 /* The floating point round to integer frint* instructions. */
8042 {
8047 }
8050 {
8055 }
8060 /* Decompose <su>muldi3_highpart. */
8062 mode == DImode
8063 /* (lshiftrt:TI */
8066 /* (mult:TI */
8068 /* (ANY_EXTEND:TI (reg:DI))
8069 (ANY_EXTEND:TI (reg:DI))) */
8076 /* (const_int 64) */
8079 {
8080 /* UMULH/SMULH. */
8088 }
8090 /* Fall through. */
8093 }
8101 }
8103 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
8104 calculated for X. This cost is stored in *COST. Returns true
8105 if the total cost of X was calculated. */
8106 static bool
8109 {
8114 {
8119 }
8122 }
8124 static int
8127 {
8133 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
8140 /* Moving between GPR and stack cost is the same as GP2GP. */
8145 /* To/From the stack register, we move via the gprs. */
8151 {
8152 /* 128-bit operations on general registers require 2 instructions. */
8160 /* When AdvSIMD instructions are disabled it is not possible to move
8161 a 128-bit value directly between Q registers. This is handled in
8162 secondary reload. A general register is used as a scratch to move
8163 the upper DI value and the lower DI value is moved directly,
8164 hence the cost is the sum of three moves. */
8169 }
8179 }
8181 static int
8183 reg_class_t rclass ATTRIBUTE_UNUSED,
8185 {
8187 }
8189 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
8190 to optimize 1.0/sqrt. */
8192 static bool
8194 {
8196 && flag_unsafe_math_optimizations
8200 }
8202 /* Function to decide when to use the approximate reciprocal square root
8203 builtin. */
8205 static tree
8207 {
8213 }
8217 /* Select reciprocal square root initial estimate insn depending on machine
8218 mode. */
8220 static rsqrte_type
8222 {
8224 {
8231 }
8232 }
8236 /* Select reciprocal square root series step insn depending on machine mode. */
8238 static rsqrts_type
8240 {
8242 {
8249 }
8250 }
8252 /* Emit instruction sequence to compute either the approximate square root
8253 or its approximate reciprocal, depending on the flag RECP, and return
8254 whether the sequence was emitted or not. */
8256 bool
8258 {
8262 {
8265 }
8267 machine_mode mmsk
8271 {
8278 || flag_trapping_math
8279 || !flag_unsafe_math_optimizations
8282 }
8283 else
8284 /* Caller assumes we cannot fail. */
8290 /* When calculating the approximate square root, compare the
8291 argument with 0.0 and create a mask. */
8297 /* Estimate the approximate reciprocal square root. */
8301 /* Iterate over the series twice for SF and thrice for DF. */
8304 /* Optionally iterate over the series once less for faster performance
8305 while sacrificing the accuracy. */
8308 iterations--;
8310 /* Iterate over the series to calculate the approximate reciprocal square
8311 root. */
8314 {
8322 }
8325 {
8326 /* Qualify the approximate reciprocal square root when the argument is
8327 0.0 by squashing the intermediary result to 0.0. */
8333 /* Calculate the approximate square root. */
8335 }
8337 /* Finalize the approximation. */
8341 }
8345 /* Select reciprocal initial estimate insn depending on machine mode. */
8347 static recpe_type
8349 {
8351 {
8358 }
8359 }
8363 /* Select reciprocal series step insn depending on machine mode. */
8365 static recps_type
8367 {
8369 {
8376 }
8377 }
8379 /* Emit the instruction sequence to compute the approximation for the division
8380 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8382 bool
8384 {
8395 || flag_trapping_math
8396 || !flag_unsafe_math_optimizations
8401 /* Estimate the approximate reciprocal. */
8405 /* Iterate over the series twice for SF and thrice for DF. */
8408 /* Optionally iterate over the series once less for faster performance,
8409 while sacrificing the accuracy. */
8411 iterations--;
8413 /* Iterate over the series to calculate the approximate reciprocal. */
8416 {
8421 }
8424 {
8425 /* As the approximate reciprocal of DEN is already calculated, only
8426 calculate the approximate division when NUM is not 1.0. */
8429 }
8431 /* Finalize the approximation. */
8434 }
8436 /* Return the number of instructions that can be issued per cycle. */
8437 static int
8439 {
8441 }
8443 static int
8445 {
8449 }
8452 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8453 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8454 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8456 static int
8459 {
8461 }
8464 /* Vectorizer cost model target hooks. */
8466 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8467 static int
8469 tree vectype,
8471 {
8480 {
8529 }
8530 }
8532 /* Implement targetm.vectorize.add_stmt_cost. */
8533 static unsigned
8537 {
8542 {
8547 /* Statements in an inner loop relative to the loop being
8548 vectorized are weighted more heavily. The value here is
8549 arbitrary and could potentially be improved with analysis. */
8555 }
8558 }
8562 /* Parse the TO_PARSE string and put the architecture struct that it
8563 selects into RES and the architectural features into ISA_FLAGS.
8564 Return an aarch64_parse_opt_result describing the parse result.
8565 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8567 static enum aarch64_parse_opt_result
8570 {
8582 else
8589 /* Loop through the list of supported ARCHes to find a match. */
8591 {
8593 {
8597 {
8598 /* TO_PARSE string contains at least one extension. */
8599 enum aarch64_parse_opt_result ext_res
8604 }
8605 /* Extension parsing was successful. Confirm the result
8606 arch and ISA flags. */
8610 }
8611 }
8613 /* ARCH name not found in list. */
8615 }
8617 /* Parse the TO_PARSE string and put the result tuning in RES and the
8618 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8619 describing the parse result. If there is an error parsing, RES and
8620 ISA_FLAGS are left unchanged. */
8622 static enum aarch64_parse_opt_result
8625 {
8637 else
8644 /* Loop through the list of supported CPUs to find a match. */
8646 {
8648 {
8653 {
8654 /* TO_PARSE string contains at least one extension. */
8655 enum aarch64_parse_opt_result ext_res
8660 }
8661 /* Extension parsing was successfull. Confirm the result
8662 cpu and ISA flags. */
8666 }
8667 }
8669 /* CPU name not found in list. */
8671 }
8673 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8674 Return an aarch64_parse_opt_result describing the parse result.
8675 If the parsing fails the RES does not change. */
8677 static enum aarch64_parse_opt_result
8679 {
8685 /* Loop through the list of supported CPUs to find a match. */
8687 {
8689 {
8692 }
8693 }
8695 /* CPU name not found in list. */
8697 }
8699 /* Parse TOKEN, which has length LENGTH to see if it is an option
8700 described in FLAG. If it is, return the index bit for that fusion type.
8701 If not, error (printing OPTION_NAME) and return zero. */
8703 static unsigned int
8708 {
8710 {
8714 }
8718 }
8720 /* Parse OPTION which is a comma-separated list of flags to enable.
8721 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8722 default state we inherit from the CPU tuning structures. OPTION_NAME
8723 gives the top-level option we are parsing in the -moverride string,
8724 for use in error messages. */
8726 static unsigned int
8731 {
8738 {
8741 token_length,
8742 flags,
8743 option_name);
8744 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8745 in the token stream, reset the supported operations. So:
8747 adrp+add.cmp+branch.none.adrp+add
8749 would have the result of turning on only adrp+add fusion. */
8755 }
8757 /* We ended with a comma, print something. */
8759 {
8762 }
8764 /* We still have one more token to parse. */
8767 token_length,
8768 flags,
8769 option_name);
8775 }
8777 /* Support for overriding instruction fusion. */
8779 static void
8782 {
8784 aarch64_fusible_pairs,
8787 }
8789 /* Support for overriding other tuning flags. */
8791 static void
8794 {
8795 tune->extra_tuning_flags
8797 aarch64_tuning_flags,
8800 }
8802 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8803 we understand. If it is, extract the option string and handoff to
8804 the appropriate function. */
8806 void
8810 {
8816 {
8819 }
8821 /* Get the length of the option name. */
8823 /* Skip the '=' to get to the option string. */
8824 option_part++;
8827 {
8829 {
8832 }
8833 }
8837 }
8839 /* A checking mechanism for the implementation of the tls size. */
8841 static void
8843 {
8848 {
8850 /* Both the default and maximum TLS size allowed under tiny is 1M which
8851 needs two instructions to address, so we clamp the size to 24. */
8856 /* The maximum TLS size allowed under small is 4G. */
8861 /* The maximum TLS size allowed under large is 16E.
8862 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8868 }
8871 }
8873 /* Parse STRING looking for options in the format:
8874 string :: option:string
8875 option :: name=substring
8876 name :: {a-z}
8877 substring :: defined by option. */
8879 static void
8882 {
8893 {
8895 /* Make this substring look like a string. */
8899 }
8901 /* One last option to parse. */
8904 }
8907 static void
8909 {
8910 /* The logic here is that if we are disabling all frame pointer generation
8911 then we do not need to disable leaf frame pointer generation as a
8912 separate operation. But if we are *only* disabling leaf frame pointer
8913 generation then we set flag_omit_frame_pointer to true, but in
8914 aarch64_frame_pointer_required we return false only for leaf functions.
8916 PR 70044: We have to be careful about being called multiple times for the
8917 same function. Once we have decided to set flag_omit_frame_pointer just
8918 so that we can omit leaf frame pointers, we must then not interpret a
8919 second call as meaning that all frame pointer generation should be
8920 omitted. We do this by setting flag_omit_frame_pointer to a special,
8921 non-zero value. */
8930 /* If not optimizing for size, set the default
8931 alignment to what the target wants. */
8933 {
8940 }
8942 /* We default to no pc-relative literal loads. */
8946 /* If -mpc-relative-literal-loads is set on the command line, this
8947 implies that the user asked for PC relative literal loads. */
8951 /* This is PR70113. When building the Linux kernel with
8952 CONFIG_ARM64_ERRATUM_843419, support for relocations
8953 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8954 removed from the kernel to avoid loading objects with possibly
8955 offending sequences. Without -mpc-relative-literal-loads we would
8956 generate such relocations, preventing the kernel build from
8957 succeeding. */
8962 /* In the tiny memory model it makes no sense to disallow PC relative
8963 literal pool loads. */
8968 /* When enabling the lower precision Newton series for the square root, also
8969 enable it for the reciprocal square root, since the latter is an
8970 intermediary step for the former. */
8973 }
8975 /* 'Unpack' up the internal tuning structs and update the options
8976 in OPTS. The caller must have set up selected_tune and selected_arch
8977 as all the other target-specific codegen decisions are
8978 derived from them. */
8980 void
8982 {
8985 /* Make a copy of the tuning parameters attached to the core, which
8986 we may later overwrite. */
8994 /* This target defaults to strict volatile bitfields. */
9003 {
9015 }
9017 /* We don't mind passing in global_options_set here as we don't use
9018 the *options_set structs anyway. */
9020 queue_depth,
9024 /* Set up parameters to be used in prefetching algorithm. Do not
9025 override the defaults unless we are tuning for a core we have
9026 researched values for. */
9048 /* Enable sw prefetching at specified optimization level for
9049 CPUS that have prefetch. Lower optimization level threshold by 1
9050 when profiling is enabled. */
9058 }
9060 /* Print a hint with a suggestion for a core or architecture name that
9061 most closely resembles what the user passed in STR. ARCH is true if
9062 the user is asking for an architecture name. ARCH is false if the user
9063 is asking for a core name. */
9065 static void
9067 {
9078 }
9080 /* Print a hint with a suggestion for a core name that most closely resembles
9081 what the user passed in STR. */
9085 {
9087 }
9089 /* Print a hint with a suggestion for an architecture name that most closely
9090 resembles what the user passed in STR. */
9094 {
9096 }
9098 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
9099 specified in STR and throw errors if appropriate. Put the results if
9100 they are valid in RES and ISA_FLAGS. Return whether the option is
9101 valid. */
9103 static bool
9106 {
9107 enum aarch64_parse_opt_result parse_res
9114 {
9127 }
9130 }
9132 /* Validate a command-line -march option. Parse the arch and extensions
9133 (if any) specified in STR and throw errors if appropriate. Put the
9134 results, if they are valid, in RES and ISA_FLAGS. Return whether the
9135 option is valid. */
9137 static bool
9140 {
9141 enum aarch64_parse_opt_result parse_res
9148 {
9161 }
9164 }
9166 /* Validate a command-line -mtune option. Parse the cpu
9167 specified in STR and throw errors if appropriate. Put the
9168 result, if it is valid, in RES. Return whether the option is
9169 valid. */
9171 static bool
9173 {
9174 enum aarch64_parse_opt_result parse_res
9181 {
9191 }
9193 }
9195 /* Return the CPU corresponding to the enum CPU.
9196 If it doesn't specify a cpu, return the default. */
9200 {
9204 /* The & 0x3f is to extract the bottom 6 bits that encode the
9205 default cpu as selected by the --with-cpu GCC configure option
9206 in config.gcc.
9207 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
9208 flags mechanism should be reworked to make it more sane. */
9210 }
9212 /* Return the architecture corresponding to the enum ARCH.
9213 If it doesn't specify a valid architecture, return the default. */
9217 {
9224 }
9226 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
9227 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
9228 tuning structs. In particular it must set selected_tune and
9229 aarch64_isa_flags that define the available ISA features and tuning
9230 decisions. It must also set selected_arch as this will be used to
9231 output the .arch asm tags for each function. */
9233 static void
9235 {
9248 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
9249 If either of -march or -mtune is given, they override their
9250 respective component of -mcpu. */
9262 /* If the user did not specify a processor, choose the default
9263 one for them. This will be the CPU set during configuration using
9264 --with-cpu, otherwise it is "generic". */
9266 {
9268 {
9272 }
9273 else
9274 {
9275 /* Get default configure-time CPU. */
9278 }
9282 }
9283 /* If both -mcpu and -march are specified check that they are architecturally
9284 compatible, warn if they're not and prefer the -march ISA flags. */
9286 {
9288 {
9292 }
9297 }
9298 else
9299 {
9300 /* -mcpu but no -march. */
9307 }
9309 /* Set the arch as well as we will need it when outputing
9310 the .arch directive in assembly. */
9312 {
9315 }
9320 #ifndef HAVE_AS_MABI_OPTION
9321 /* The compiler may have been configured with 2.23.* binutils, which does
9322 not have support for ILP32. */
9325 #endif
9330 /* Make sure we properly set up the explicit options. */
9341 /* Save these options as the default ones in case we push and pop them later
9342 while processing functions with potential target attributes. */
9343 target_option_default_node = target_option_current_node
9345 }
9347 /* Implement targetm.override_options_after_change. */
9349 static void
9351 {
9353 }
9357 {
9361 }
9363 void
9365 {
9367 }
9369 /* A checking mechanism for the implementation of the various code models. */
9370 static void
9372 {
9374 {
9376 {
9381 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9383 ? AARCH64_CMODEL_SMALL_PIC
9385 #else
9387 #endif
9395 }
9396 }
9397 else
9399 }
9401 /* Implement TARGET_OPTION_SAVE. */
9403 static void
9405 {
9407 }
9409 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9410 using the information saved in PTR. */
9412 static void
9414 {
9422 }
9424 /* Implement TARGET_OPTION_PRINT. */
9426 static void
9428 {
9439 }
9443 void
9445 {
9447 }
9449 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9450 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9451 make sure optab availability predicates are recomputed when necessary. */
9453 void
9455 {
9460 else
9462 }
9464 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9465 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9466 of the function, if such exists. This function may be called multiple
9467 times on a single function so use aarch64_previous_fndecl to avoid
9468 setting up identical state. */
9470 static void
9472 {
9476 tree old_tree = (aarch64_previous_fndecl
9482 /* If current function has no attributes but the previous one did,
9483 use the default node. */
9487 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9488 the default have been handled by aarch64_save_restore_target_globals from
9489 aarch64_pragma_target_parse. */
9495 /* First set the target options. */
9499 }
9501 /* Enum describing the various ways we can handle attributes.
9502 In many cases we can reuse the generic option handling machinery. */
9504 enum aarch64_attr_opt_type
9505 {
9509 aarch64_attr_custom /* Attribute requires a custom handling function. */
9510 };
9512 /* All the information needed to handle a target attribute.
9513 NAME is the name of the attribute.
9514 ATTR_TYPE specifies the type of behavior of the attribute as described
9515 in the definition of enum aarch64_attr_opt_type.
9516 ALLOW_NEG is true if the attribute supports a "no-" form.
9517 HANDLER is the function that takes the attribute string and whether
9518 it is a pragma or attribute and handles the option. It is needed only
9519 when the ATTR_TYPE is aarch64_attr_custom.
9520 OPT_NUM is the enum specifying the option that the attribute modifies.
9521 This is needed for attributes that mirror the behavior of a command-line
9522 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9523 aarch64_attr_enum. */
9525 struct aarch64_attribute_info
9526 {
9532 };
9534 /* Handle the ARCH_STR argument to the arch= target attribute.
9535 PRAGMA_OR_ATTR is used in potential error messages. */
9537 static bool
9539 {
9541 enum aarch64_parse_opt_result parse_res
9545 {
9550 }
9553 {
9567 }
9570 }
9572 /* Handle the argument CPU_STR to the cpu= target attribute.
9573 PRAGMA_OR_ATTR is used in potential error messages. */
9575 static bool
9577 {
9579 enum aarch64_parse_opt_result parse_res
9583 {
9591 }
9594 {
9608 }
9611 }
9613 /* Handle the argument STR to the tune= target attribute.
9614 PRAGMA_OR_ATTR is used in potential error messages. */
9616 static bool
9618 {
9620 enum aarch64_parse_opt_result parse_res
9624 {
9629 }
9632 {
9639 }
9642 }
9644 /* Parse an architecture extensions target attribute string specified in STR.
9645 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9646 if successful. Update aarch64_isa_flags to reflect the ISA features
9647 modified.
9648 PRAGMA_OR_ATTR is used in potential error messages. */
9650 static bool
9652 {
9656 /* We allow "+nothing" in the beginning to clear out all architectural
9657 features if the user wants to handpick specific features. */
9659 {
9662 }
9667 {
9670 }
9673 {
9686 }
9689 }
9691 /* The target attributes that we support. On top of these we also support just
9692 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9693 handled explicitly in aarch64_process_one_target_attr. */
9696 {
9698 OPT_mgeneral_regs_only },
9700 OPT_mfix_cortex_a53_835769 },
9702 OPT_mfix_cortex_a53_843419 },
9706 OPT_momit_leaf_frame_pointer },
9709 OPT_march_ },
9712 OPT_mtune_ },
9714 OPT_msign_return_address_ },
9716 };
9718 /* Parse ARG_STR which contains the definition of one target attribute.
9719 Show appropriate errors if any or return true if the attribute is valid.
9720 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9721 we're processing a target attribute or pragma. */
9723 static bool
9725 {
9731 {
9734 }
9739 /* Skip leading whitespace. */
9741 str_to_check++;
9743 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9744 It is easier to detect and handle it explicitly here rather than going
9745 through the machinery for the rest of the target attributes in this
9746 function. */
9751 {
9754 }
9757 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9758 and point ARG to "foo". */
9760 {
9762 arg++;
9763 }
9767 {
9768 /* If the names don't match up, or the user has given an argument
9769 to an attribute that doesn't accept one, or didn't give an argument
9770 to an attribute that expects one, fail to match. */
9779 {
9783 }
9785 /* If the name matches but the attribute does not allow "no-" versions
9786 then we can't match. */
9788 {
9792 }
9795 {
9796 /* Has a custom handler registered.
9797 For example, cpu=, arch=, tune=. */
9804 /* Either set or unset a boolean option. */
9806 {
9814 }
9815 /* Set or unset a bit in the target_flags. aarch64_handle_option
9816 should know what mask to apply given the option number. */
9818 {
9820 /* We only need to specify the option number.
9821 aarch64_handle_option will know which mask to apply. */
9827 }
9828 /* Use the option setting machinery to set an option to an enum. */
9830 {
9837 {
9840 global_dc);
9841 }
9842 else
9843 {
9846 }
9848 }
9851 }
9852 }
9854 /* If we reached here we either have found an attribute and validated
9855 it or didn't match any. If we matched an attribute but its arguments
9856 were malformed we will have returned false already. */
9858 }
9860 /* Count how many times the character C appears in
9861 NULL-terminated string STR. */
9863 static unsigned int
9865 {
9868 {
9870 res++;
9872 str++;
9873 }
9876 }
9878 /* Parse the tree in ARGS that contains the target attribute information
9879 and update the global target options space. PRAGMA_OR_ATTR is a string
9880 to be used in error messages, specifying whether this is processing
9881 a target attribute or a target pragma. */
9883 bool
9885 {
9887 {
9888 do
9889 {
9892 {
9895 }
9900 }
9903 {
9906 }
9913 {
9916 }
9918 /* Used to catch empty spaces between commas i.e.
9919 attribute ((target ("attr1,,attr2"))). */
9922 /* Handle multiple target attributes separated by ','. */
9927 {
9928 num_attrs++;
9930 {
9933 }
9936 }
9939 {
9943 }
9946 }
9948 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9949 process attribute ((target ("..."))). */
9951 static bool
9953 {
9956 tree old_optimize;
9960 /* If what we're processing is the current pragma string then the
9961 target option node is already stored in target_option_current_node
9962 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9963 having to re-parse the string. This is especially useful to keep
9964 arm_neon.h compile times down since that header contains a lot
9965 of intrinsics enclosed in pragmas. */
9967 {
9970 }
9976 /* If the function changed the optimization levels as well as setting
9977 target options, start with the optimizations specified. */
9982 /* Save the current target options to restore at the end. */
9985 /* If fndecl already has some target attributes applied to it, unpack
9986 them so that we add this attribute on top of them, rather than
9987 overwriting them. */
9989 {
9995 }
9996 else
10003 /* Set up any additional state. */
10005 {
10007 /* Initialize SIMD builtins if we haven't already.
10008 Set current_target_pragma to NULL for the duration so that
10009 the builtin initialization code doesn't try to tag the functions
10010 being built with the attributes specified by any current pragma, thus
10011 going into an infinite recursion. */
10013 {
10018 }
10020 }
10021 else
10027 {
10032 }
10040 }
10042 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
10043 tri-bool options (yes, no, don't care) and the default value is
10044 DEF, determine whether to reject inlining. */
10046 static bool
10049 {
10050 /* If the callee doesn't care, always allow inlining. */
10054 /* If the caller doesn't care, always allow inlining. */
10058 /* Otherwise, allow inlining if either the callee and caller values
10059 agree, or if the callee is using the default value. */
10061 }
10063 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
10064 to inline CALLEE into CALLER based on target-specific info.
10065 Make sure that the caller and callee have compatible architectural
10066 features. Then go through the other possible target attributes
10067 and see if they can block inlining. Try not to reject always_inline
10068 callees unless they are incompatible architecturally. */
10070 static bool
10072 {
10076 /* If callee has no option attributes, then it is ok to inline. */
10087 /* Callee's ISA flags should be a subset of the caller's. */
10092 /* Allow non-strict aligned functions inlining into strict
10093 aligned ones. */
10103 /* If the architectural features match up and the callee is always_inline
10104 then the other attributes don't matter. */
10116 /* Honour explicit requests to workaround errata. */
10129 /* If the user explicitly specified -momit-leaf-frame-pointer for the
10130 caller and calle and they don't match up, reject inlining. */
10137 /* If the callee has specific tuning overrides, respect them. */
10142 /* If the user specified tuning override strings for the
10143 caller and callee and they don't match up, reject inlining.
10144 We just do a string compare here, we don't analyze the meaning
10145 of the string, as it would be too costly for little gain. */
10153 }
10155 /* Return true if SYMBOL_REF X binds locally. */
10157 static bool
10159 {
10163 }
10165 /* Return true if SYMBOL_REF X is thread local */
10166 static bool
10168 {
10176 }
10178 /* Classify a TLS symbol into one of the TLS kinds. */
10179 enum aarch64_symbol_type
10181 {
10185 {
10192 {
10198 }
10209 else
10218 }
10219 }
10221 /* Return the method that should be used to access SYMBOL_REF or
10222 LABEL_REF X. */
10224 enum aarch64_symbol_type
10226 {
10228 {
10230 {
10245 }
10246 }
10249 {
10254 {
10256 /* When we retrieve symbol + offset address, we have to make sure
10257 the offset does not cause overflow of the final address. But
10258 we have no way of knowing the address of symbol at compile time
10259 so we can't accurately say if the distance between the PC and
10260 symbol + offset is outside the addressible range of +/-1M in the
10261 TINY code model. So we rely on images not being greater than
10262 1M and cap the offset at 1M and anything beyond 1M will have to
10263 be loaded using an alternative mechanism. Furthermore if the
10264 symbol is a weak reference to something that isn't known to
10265 resolve to a symbol in this module, then force to memory. */
10273 /* Same reasoning as the tiny code model, but the offset cap here is
10274 4G. */
10295 /* This is alright even in PIC code as the constant
10296 pool reference is always PC relative and within
10297 the same translation unit. */
10300 else
10305 }
10306 }
10308 /* By default push everything into the constant pool. */
10310 }
10312 bool
10314 {
10316 }
10318 bool
10320 {
10328 }
10330 /* Return true if X holds either a quarter-precision or
10331 floating-point +0.0 constant. */
10332 static bool
10334 {
10338 /* This call determines which constants can be used in mov<mode>
10339 as integer moves instead of constant loads. */
10344 }
10346 static bool
10348 {
10349 /* Do not allow vector struct mode constants. We could support
10350 0 and -1 easily, but they need support in aarch64-simd.md. */
10354 /* For these cases we never want to use a literal load.
10355 As such we have to prevent the compiler from forcing these
10356 to memory. */
10369 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
10370 so spilling them is better than rematerialization. */
10375 }
10377 rtx
10379 {
10385 /* Can return in any reg. */
10388 }
10390 /* On AAPCS systems, this is the "struct __va_list". */
10393 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10394 Return the type to use as __builtin_va_list.
10396 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10398 struct __va_list
10399 {
10400 void *__stack;
10401 void *__gr_top;
10402 void *__vr_top;
10403 int __gr_offs;
10404 int __vr_offs;
10405 }; */
10407 static tree
10409 {
10410 tree va_list_name;
10413 /* Create the type. */
10415 /* Give it the required name. */
10417 TYPE_DECL,
10419 va_list_type);
10424 /* Create the fields. */
10427 ptr_type_node);
10430 ptr_type_node);
10433 ptr_type_node);
10436 integer_type_node);
10439 integer_type_node);
10441 /* Tell tree-stdarg pass about our internal offset fields.
10442 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10443 purpose to identify whether the code is updating va_list internal
10444 offset fields through irregular way. */
10466 /* Compute its layout. */
10470 }
10472 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10473 static void
10475 {
10479 tree t;
10493 {
10496 }
10505 NULL_TREE);
10507 NULL_TREE);
10509 NULL_TREE);
10511 NULL_TREE);
10513 NULL_TREE);
10515 /* Emit code to initialize STACK, which points to the next varargs stack
10516 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10517 by named arguments. STACK is 8-byte aligned. */
10524 /* Emit code to initialize GRTOP, the top of the GR save area.
10525 virtual_incoming_args_rtx should have been 16 byte aligned. */
10530 /* Emit code to initialize VRTOP, the top of the VR save area.
10531 This address is gr_save_area_bytes below GRTOP, rounded
10532 down to the next 16-byte boundary. */
10542 /* Emit code to initialize GROFF, the offset from GRTOP of the
10543 next GPR argument. */
10548 /* Likewise emit code to initialize VROFF, the offset from FTOP
10549 of the next VR argument. */
10553 }
10555 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10557 static tree
10560 {
10561 tree addr;
10567 machine_mode mode;
10594 type,
10598 {
10599 /* TYPE passed in fp/simd registers. */
10611 {
10614 }
10617 {
10619 }
10620 }
10621 else
10622 {
10623 /* TYPE passed in general registers. */
10636 {
10638 }
10639 }
10641 /* Get a local temporary for the field value. */
10644 /* Emit code to branch if off >= 0. */
10650 {
10651 /* Emit: offs = (offs + 15) & -16. */
10657 }
10658 else
10661 /* Update ap.__[g|v]r_offs */
10666 /* String up. */
10670 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10675 /* String up: make sure the assignment happens before the use. */
10679 /* Prepare the trees handling the argument that is passed on the stack;
10680 the top level node will store in ON_STACK. */
10683 {
10684 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10692 }
10693 else
10695 /* Advance ap.__stack */
10703 /* String up roundup and advance. */
10706 /* String up with arg */
10708 /* Big-endianness related address adjustment. */
10711 {
10715 }
10720 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10730 {
10731 /* type ha; // treat as "struct {ftype field[n];}"
10732 ... [computing offs]
10733 for (i = 0; i <nregs; ++i, offs += 16)
10734 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10735 return ha; */
10739 /* Declare a local variable. */
10743 /* Establish the base type. */
10745 {
10764 {
10768 }
10772 }
10774 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10782 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10784 {
10794 }
10798 }
10808 }
10810 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10812 static void
10816 {
10818 CUMULATIVE_ARGS local_cum;
10822 /* The caller has advanced CUM up to, but not beyond, the last named
10823 argument. Advance a local copy of CUM past the last "real" named
10824 argument, to find out how many registers are left over. */
10828 /* Found out how many registers we need to save.
10829 Honor tree-stdvar analysis results. */
10838 {
10841 }
10844 {
10846 {
10849 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10857 }
10859 {
10860 /* We can't use move_block_from_reg, because it will use
10861 the wrong mode, storing D regs only. */
10865 /* Set OFF to the offset from virtual_incoming_args_rtx of
10866 the first vector register. The VR save area lies below
10867 the GR one, and is aligned to 16 bytes. */
10874 {
10882 }
10883 }
10884 }
10886 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10887 any complication of having crtl->args.pretend_args_size changed. */
10892 }
10894 static void
10896 {
10899 {
10901 {
10904 }
10905 }
10906 }
10908 /* Walk down the type tree of TYPE counting consecutive base elements.
10909 If *MODEP is VOIDmode, then set it to the first valid floating point
10910 type. If a non-floating point type is found, or if a floating point
10911 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10912 otherwise return the count in the sub-tree. */
10913 static int
10915 {
10916 machine_mode mode;
10917 HOST_WIDE_INT size;
10920 {
10950 /* Use V2SImode and V4SImode as representatives of all 64-bit
10951 and 128-bit vector types. */
10954 {
10963 }
10968 /* Vector modes are considered to be opaque: two vectors are
10969 equivalent for the purposes of being homogeneous aggregates
10970 if they are the same size. */
10977 {
10981 /* Can't handle incomplete types nor sizes that are not
10982 fixed. */
10989 || !index
11000 /* There must be no padding. */
11005 }
11008 {
11011 tree field;
11013 /* Can't handle incomplete types nor sizes that are not
11014 fixed. */
11020 {
11028 }
11030 /* There must be no padding. */
11035 }
11039 {
11040 /* These aren't very interesting except in a degenerate case. */
11043 tree field;
11045 /* Can't handle incomplete types nor sizes that are not
11046 fixed. */
11052 {
11060 }
11062 /* There must be no padding. */
11067 }
11071 }
11074 }
11076 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
11077 type as described in AAPCS64 \S 4.1.2.
11079 See the comment above aarch64_composite_type_p for the notes on MODE. */
11081 static bool
11083 machine_mode mode)
11084 {
11094 }
11096 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
11097 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
11098 array types. The C99 floating-point complex types are also considered
11099 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
11100 types, which are GCC extensions and out of the scope of AAPCS64, are
11101 treated as composite types here as well.
11103 Note that MODE itself is not sufficient in determining whether a type
11104 is such a composite type or not. This is because
11105 stor-layout.c:compute_record_mode may have already changed the MODE
11106 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
11107 structure with only one field may have its MODE set to the mode of the
11108 field. Also an integer mode whose size matches the size of the
11109 RECORD_TYPE type may be used to substitute the original mode
11110 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
11111 solely relied on. */
11113 static bool
11115 machine_mode mode)
11116 {
11129 }
11131 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
11132 shall be passed or returned in simd/fp register(s) (providing these
11133 parameter passing registers are available).
11135 Upon successful return, *COUNT returns the number of needed registers,
11136 *BASE_MODE returns the mode of the individual register and when IS_HAF
11137 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
11138 floating-point aggregate or a homogeneous short-vector aggregate. */
11140 static bool
11142 const_tree type,
11146 {
11154 {
11157 }
11159 {
11163 }
11165 {
11169 {
11172 }
11173 else
11175 }
11176 else
11181 }
11183 /* Implement TARGET_STRUCT_VALUE_RTX. */
11185 static rtx
11188 {
11190 }
11192 /* Implements target hook vector_mode_supported_p. */
11193 static bool
11195 {
11207 }
11209 /* Return appropriate SIMD container
11210 for MODE within a vector of WIDTH bits. */
11211 static machine_mode
11213 {
11216 {
11219 {
11236 }
11237 else
11239 {
11252 }
11253 }
11255 }
11257 /* Return 128-bit container as the preferred SIMD mode for MODE. */
11258 static machine_mode
11260 {
11262 }
11264 /* Return the bitmask of possible vector sizes for the vectorizer
11265 to iterate over. */
11266 static unsigned int
11268 {
11270 }
11272 /* Implement TARGET_MANGLE_TYPE. */
11276 {
11277 /* The AArch64 ABI documents say that "__va_list" has to be
11278 managled as if it is in the "std" namespace. */
11282 /* Half-precision float. */
11286 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
11287 builtin types. */
11291 /* Use the default mangling. */
11293 }
11295 /* Find the first rtx_insn before insn that will generate an assembly
11296 instruction. */
11300 {
11304 do
11305 {
11307 }
11311 }
11313 static bool
11315 {
11317 /* A number of these may be AArch32 only. */
11322 };
11325 {
11328 }
11331 }
11333 /* Check if there is a register dependency between a load and the insn
11334 for which we hold recog_data. */
11336 static bool
11338 {
11339 rtx load_reg;
11349 {
11355 }
11357 }
11360 /* When working around the Cortex-A53 erratum 835769,
11361 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
11362 instruction and has a preceding memory instruction such that a NOP
11363 should be inserted between them. */
11365 bool
11367 {
11370 rtx body;
11383 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11384 Restore recog state to INSN to avoid state corruption. */
11392 /* If the previous insn is a memory op and there is no dependency between
11393 it and the DImode madd, emit a NOP between them. If body is NULL then we
11394 have a complex memory operation, probably a load/store pair.
11395 Be conservative for now and emit a NOP. */
11402 }
11405 /* Implement FINAL_PRESCAN_INSN. */
11407 void
11409 {
11412 }
11415 /* Return the equivalent letter for size. */
11416 static char
11418 {
11420 {
11426 }
11427 }
11429 /* Return true iff x is a uniform vector of floating-point
11430 constants, and the constant can be represented in
11431 quarter-precision form. Note, as aarch64_float_const_representable
11432 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11433 static bool
11435 {
11436 rtx elt;
11440 }
11442 /* Return true for valid and false for invalid. */
11443 bool
11446 {
11447 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11448 matches = 1; \
11449 for (i = 0; i < idx; i += (STRIDE)) \
11450 if (!(TEST)) \
11451 matches = 0; \
11452 if (matches) \
11453 { \
11454 immtype = (CLASS); \
11455 elsize = (ELSIZE); \
11456 eshift = (SHIFT); \
11457 emvn = (NEG); \
11458 break; \
11459 }
11469 {
11475 {
11480 }
11483 }
11485 /* Splat vector constant out into a byte vector. */
11487 {
11488 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11489 it must be laid out in the vector register in reverse order. */
11497 {
11500 }
11502 }
11504 /* Sanity check. */
11507 do
11508 {
11557 }
11564 {
11574 /* Un-invert bytes of recognized vector, if necessary. */
11580 {
11581 /* FIXME: Broken on 32-bit H_W_I hosts. */
11590 }
11591 else
11592 {
11596 /* Construct 'abcdefgh' because the assembler cannot handle
11597 generic constants. */
11602 }
11603 }
11606 #undef CHECK
11607 }
11609 /* Check of immediate shift constants are within range. */
11610 bool
11612 {
11616 else
11618 }
11620 /* Return true if X is a uniform vector where all elements
11621 are either the floating-point constant 0.0 or the
11622 integer constant 0. */
11623 bool
11625 {
11627 }
11630 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11631 operation of width WIDTH at bit position POS. */
11633 rtx
11635 {
11639 unsigned HOST_WIDE_INT mask
11642 }
11644 bool
11646 {
11659 }
11661 /* Return a const_int vector of VAL. */
11662 rtx
11664 {
11675 }
11677 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11679 bool
11681 {
11682 machine_mode vmode;
11688 }
11690 /* Construct and return a PARALLEL RTX vector with elements numbering the
11691 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11692 the vector - from the perspective of the architecture. This does not
11693 line up with GCC's perspective on lane numbers, so we end up with
11694 different masks depending on our target endian-ness. The diagram
11695 below may help. We must draw the distinction when building masks
11696 which select one half of the vector. An instruction selecting
11697 architectural low-lanes for a big-endian target, must be described using
11698 a mask selecting GCC high-lanes.
11700 Big-Endian Little-Endian
11702 GCC 0 1 2 3 3 2 1 0
11703 | x | x | x | x | | x | x | x | x |
11704 Architecture 3 2 1 0 3 2 1 0
11706 Low Mask: { 2, 3 } { 0, 1 }
11707 High Mask: { 0, 1 } { 2, 3 }
11708 */
11710 rtx
11712 {
11718 rtx t1;
11723 else
11731 }
11733 /* Check OP for validity as a PARALLEL RTX vector with elements
11734 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11735 from the perspective of the architecture. See the diagram above
11736 aarch64_simd_vect_par_cnst_half for more details. */
11738 bool
11741 {
11754 {
11761 }
11763 }
11765 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11766 HIGH (exclusive). */
11767 void
11769 const_tree exp)
11770 {
11771 HOST_WIDE_INT lane;
11776 {
11779 else
11781 }
11782 }
11784 /* Return TRUE if OP is a valid vector addressing mode. */
11785 bool
11787 {
11790 }
11792 /* Emit a register copy from operand to operand, taking care not to
11793 early-clobber source registers in the process.
11795 COUNT is the number of components into which the copy needs to be
11796 decomposed. */
11797 void
11800 {
11810 else
11814 }
11816 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11817 one of VSTRUCT modes: OI, CI, or XI. */
11818 int
11820 {
11822 }
11824 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11825 alignment of a vector to 128 bits. */
11826 static HOST_WIDE_INT
11828 {
11831 }
11833 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11834 static bool
11836 {
11840 /* We guarantee alignment for vectors up to 128-bits. */
11845 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11847 }
11849 /* Return true if the vector misalignment factor is supported by the
11850 target. */
11851 static bool
11855 {
11857 {
11858 /* Return if movmisalign pattern is not supported for this mode. */
11863 {
11864 /* Misalignment factor is unknown at compile time but we know
11865 it's word aligned. */
11867 {
11872 }
11874 }
11875 }
11877 is_packed);
11878 }
11880 /* If VALS is a vector constant that can be loaded into a register
11881 using DUP, generate instructions to do so and return an RTX to
11882 assign to the register. Otherwise return NULL_RTX. */
11883 static rtx
11885 {
11888 rtx x;
11893 /* We can load this constant by using DUP and a constant in a
11894 single ARM register. This will be cheaper than a vector
11895 load. */
11898 }
11901 /* Generate code to load VALS, which is a PARALLEL containing only
11902 constants (for vec_init) or CONST_VECTOR, efficiently into a
11903 register. Returns an RTX to copy into the register, or NULL_RTX
11904 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11905 static rtx
11907 {
11909 rtx const_dup;
11918 {
11919 /* A CONST_VECTOR must contain only CONST_INTs and
11920 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11921 Only store valid constants in a CONST_VECTOR. */
11923 {
11926 n_const++;
11927 }
11930 }
11931 else
11936 /* Load using MOVI/MVNI. */
11939 /* Loaded using DUP. */
11942 /* Load from constant pool. We can not take advantage of single-cycle
11943 LD1 because we need a PC-relative addressing mode. */
11945 else
11946 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11947 We can not construct an initializer. */
11949 }
11951 /* Expand a vector initialisation sequence, such that TARGET is
11952 initialised to contain VALS. */
11954 void
11956 {
11959 /* The number of vector elements. */
11961 /* The number of vector elements which are not constant. */
11964 /* The first element of vals. */
11968 /* Count the number of variable elements to initialise. */
11970 {
11974 else
11978 }
11980 /* No variable elements, hand off to aarch64_simd_make_constant which knows
11981 how best to handle this. */
11983 {
11986 {
11989 }
11990 }
11992 /* Splat a single non-constant element if we can. */
11994 {
11998 }
12003 /* If there are only variable elements, try to optimize
12004 the insertion using dup for the most common element
12005 followed by insertions. */
12007 /* The algorithm will fill matches[*][0] with the earliest matching element,
12008 and matches[X][1] with the count of duplicate elements (if X is the
12009 earliest element which has duplicates). */
12012 {
12015 {
12017 {
12019 {
12023 }
12024 }
12025 }
12030 {
12033 }
12035 /* Create a duplicate of the most common element. */
12039 /* Insert the rest. */
12041 {
12047 }
12049 }
12051 /* Initialise a vector which is part-variable. We want to first try
12052 to build those lanes which are constant in the most efficient way we
12053 can. */
12055 {
12058 /* Load constant part of vector. We really don't care what goes into the
12059 parts we will overwrite, but we're more likely to be able to load the
12060 constant efficiently if it has fewer, larger, repeating parts
12061 (see aarch64_simd_valid_immediate). */
12063 {
12069 {
12070 /* Look in the copied vector, as more elements are const. */
12073 {
12076 }
12077 }
12079 }
12081 }
12083 /* Insert the variable lanes directly. */
12085 {
12091 }
12092 }
12094 static unsigned HOST_WIDE_INT
12096 {
12097 return
12098 (!SHIFT_COUNT_TRUNCATED
12101 }
12103 /* Select a format to encode pointers in exception handling data. */
12104 int
12106 {
12109 {
12115 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
12116 for everything. */
12120 /* No assumptions here. 8-byte relocs required. */
12123 }
12125 }
12127 /* The last .arch and .tune assembly strings that we printed. */
12131 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
12132 by the function fndecl. */
12134 void
12136 tree fndecl)
12137 {
12143 else
12154 /* Only update the assembler .arch string if it is distinct from the last
12155 such string we printed. */
12158 {
12161 }
12163 /* Print the cpu name we're tuning for in the comments, might be
12164 useful to readers of the generated asm. Do it only when it changes
12165 from function to function and verbose assembly is requested. */
12170 {
12174 }
12176 /* Don't forget the type directive for ELF. */
12179 }
12181 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
12183 static void
12185 {
12202 }
12204 /* Emit load exclusive. */
12206 static void
12209 {
12213 {
12220 }
12223 }
12225 /* Emit store exclusive. */
12227 static void
12230 {
12234 {
12241 }
12244 }
12246 /* Mark the previous jump instruction as unlikely. */
12248 static void
12250 {
12253 }
12255 /* Expand a compare and swap pattern. */
12257 void
12259 {
12264 gen_cas_fn gen;
12266 {
12267 gen_aarch64_compare_and_swapqi,
12268 gen_aarch64_compare_and_swaphi,
12269 gen_aarch64_compare_and_swapsi,
12270 gen_aarch64_compare_and_swapdi
12271 };
12273 {
12274 gen_aarch64_compare_and_swapqi_lse,
12275 gen_aarch64_compare_and_swaphi_lse,
12276 gen_aarch64_compare_and_swapsi_lse,
12277 gen_aarch64_compare_and_swapdi_lse
12278 };
12291 /* Normally the succ memory model must be stronger than fail, but in the
12292 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
12293 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
12300 {
12303 /* For short modes, we're going to perform the comparison in SImode,
12304 so do the zero-extension now. */
12308 /* Fall through. */
12312 /* Force the value into a register if needed. */
12319 }
12322 {
12329 }
12332 else
12343 }
12345 /* Test whether the target supports using a atomic load-operate instruction.
12346 CODE is the operation and AFTER is TRUE if the data in memory after the
12347 operation should be returned and FALSE if the data before the operation
12348 should be returned. Returns FALSE if the operation isn't supported by the
12349 architecture. */
12351 bool
12353 {
12358 {
12368 }
12369 }
12371 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
12372 sequence implementing an atomic operation. */
12374 static void
12376 {
12383 {
12385 }
12386 }
12388 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
12389 for the data in memory. EXPECTED is the value expected to be in memory.
12390 DESIRED is the value to store to memory. MEM is the memory location. MODEL
12391 is the memory ordering to use. */
12393 void
12396 rtx model)
12397 {
12399 machine_mode mode;
12404 {
12411 }
12413 /* Move the expected value into the CAS destination register. */
12416 /* Emit the CAS. */
12419 /* Compare the expected value with the value loaded by the CAS, to establish
12420 whether the swap was made. */
12422 }
12424 /* Split a compare and swap pattern. */
12426 void
12428 {
12430 machine_mode mode;
12435 rtx model_rtx;
12447 /* When OLDVAL is zero and we want the strong version we can emit a tighter
12448 loop:
12449 .label1:
12450 LD[A]XR rval, [mem]
12451 CBNZ rval, .label2
12452 ST[L]XR scratch, newval, [mem]
12453 CBNZ scratch, .label1
12454 .label2:
12455 CMP rval, 0. */
12460 {
12463 }
12466 /* The initial load can be relaxed for a __sync operation since a final
12467 barrier will be emitted to stop code hoisting. */
12471 else
12475 {
12480 }
12481 else
12482 {
12488 }
12493 {
12498 }
12499 else
12500 {
12504 }
12507 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
12508 to set the condition flags. If this is not used it will be removed by
12509 later passes. */
12511 {
12515 }
12516 /* Emit any final barrier needed for a __sync operation. */
12519 }
12521 /* Emit a BIC instruction. */
12523 static void
12525 {
12530 {
12535 }
12538 }
12540 /* Emit an atomic swap. */
12542 static void
12545 {
12549 {
12556 }
12559 }
12561 /* Operations supported by aarch64_emit_atomic_load_op. */
12563 enum aarch64_atomic_load_op_code
12564 {
12568 AARCH64_LDOP_BIC /* A & ~B */
12569 };
12571 /* Emit an atomic load-operate. */
12573 static void
12577 {
12580 {
12581 gen_aarch64_atomic_loadaddqi,
12582 gen_aarch64_atomic_loadaddhi,
12583 gen_aarch64_atomic_loadaddsi,
12584 gen_aarch64_atomic_loadadddi
12585 };
12587 {
12588 gen_aarch64_atomic_loadeorqi,
12589 gen_aarch64_atomic_loadeorhi,
12590 gen_aarch64_atomic_loadeorsi,
12591 gen_aarch64_atomic_loadeordi
12592 };
12594 {
12595 gen_aarch64_atomic_loadsetqi,
12596 gen_aarch64_atomic_loadsethi,
12597 gen_aarch64_atomic_loadsetsi,
12598 gen_aarch64_atomic_loadsetdi
12599 };
12601 {
12602 gen_aarch64_atomic_loadclrqi,
12603 gen_aarch64_atomic_loadclrhi,
12604 gen_aarch64_atomic_loadclrsi,
12605 gen_aarch64_atomic_loadclrdi
12606 };
12607 aarch64_atomic_load_op_fn gen;
12611 {
12618 }
12621 {
12628 }
12631 }
12633 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12634 location to store the data read from memory. OUT_RESULT is the location to
12635 store the result of the operation. MEM is the memory location to read and
12636 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12637 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12638 be NULL. */
12640 void
12643 {
12647 aarch64_atomic_load_op_code ldop_code;
12648 rtx src;
12649 rtx x;
12657 /* Make sure the value is in a register, putting it into a destination
12658 register if it needs to be manipulated. */
12661 {
12664 }
12665 else
12669 /* Preprocess the data for the operation as necessary. If the operation is
12670 a SET then emit a swap instruction and finish. */
12672 {
12678 /* Negate the value and treat it as a PLUS. */
12679 {
12680 rtx neg_src;
12682 /* Resize the value if necessary. */
12691 }
12692 /* Fall-through. */
12706 {
12707 rtx not_src;
12709 /* Resize the value if necessary. */
12718 }
12723 /* The operation can't be done with atomic instructions. */
12725 }
12729 /* If necessary, calculate the data in memory after the update by redoing the
12730 operation from values in registers. */
12735 {
12739 }
12744 {
12760 }
12765 }
12767 /* Split an atomic operation. */
12769 void
12772 {
12778 rtx x;
12780 /* Split the atomic operation into a sequence. */
12788 else
12792 /* The initial load can be relaxed for a __sync operation since a final
12793 barrier will be emitted to stop code hoisting. */
12797 else
12801 {
12815 {
12818 }
12819 /* Fall through. */
12825 }
12835 /* Emit any final barrier needed for a __sync operation. */
12838 }
12840 static void
12842 {
12843 /* Half-precision float operations. The compiler handles all operations
12844 with NULL libfuncs by converting to SFmode. */
12846 /* Conversions. */
12850 /* Arithmetic. */
12857 /* Comparisons. */
12865 }
12867 /* Target hook for c_mode_for_suffix. */
12868 static machine_mode
12870 {
12875 }
12877 /* We can only represent floating point constants which will fit in
12878 "quarter-precision" values. These values are characterised by
12879 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12880 by:
12882 (-1)^s * (n/16) * 2^r
12884 Where:
12885 's' is the sign bit.
12886 'n' is an integer in the range 16 <= n <= 31.
12887 'r' is an integer in the range -3 <= r <= 4. */
12889 /* Return true iff X can be represented by a quarter-precision
12890 floating point immediate operand X. Note, we cannot represent 0.0. */
12891 bool
12893 {
12894 /* This represents our current view of how many bits
12895 make up the mantissa. */
12905 /* We don't support HFmode constants yet. */
12911 /* We cannot represent infinities, NaNs or +/-zero. We won't
12912 know if we have +zero until we analyse the mantissa, but we
12913 can reject the other invalid values. */
12918 /* Extract exponent. */
12922 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12923 highest (sign) bit, with a fixed binary point at bit point_pos.
12924 m1 holds the low part of the mantissa, m2 the high part.
12925 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12926 bits for the mantissa, this can fail (low bits will be lost). */
12930 /* If the low part of the mantissa has bits set we cannot represent
12931 the value. */
12934 /* We have rejected the lower HOST_WIDE_INT, so update our
12935 understanding of how many bits lie in the mantissa and
12936 look only at the high HOST_WIDE_INT. */
12940 /* We can only represent values with a mantissa of the form 1.xxxx. */
12945 /* Having filtered unrepresentable values, we may now remove all
12946 but the highest 5 bits. */
12949 /* We cannot represent the value 0.0, so reject it. This is handled
12950 elsewhere. */
12954 /* Then, as bit 4 is always set, we can mask it off, leaving
12955 the mantissa in the range [0, 15]. */
12959 /* GCC internally does not use IEEE754-like encoding (where normalized
12960 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12961 Our mantissa values are shifted 4 places to the left relative to
12962 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12963 by 5 places to correct for GCC's representation. */
12967 }
12971 machine_mode mode,
12973 {
12983 /* This will return true to show const_vector is legal for use as either
12984 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
12985 also update INFO to show how the immediate should be generated. */
12994 {
12996 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
12997 move immediate path. */
13000 else
13001 {
13010 else
13014 }
13015 }
13028 else
13032 }
13036 {
13038 /* If a floating point number was passed and we desire to use it in an
13039 integer mode do the conversion to integer. */
13041 {
13046 }
13048 machine_mode vmode;
13049 /* use a 64 bit mode for everything except for DI/DF mode, where we use
13050 a 128 bit vector mode. */
13057 }
13059 /* Split operands into moves from op[1] + op[2] into op[0]. */
13061 void
13063 {
13074 {
13075 /* No-op move. Can't split to nothing; emit something. */
13078 }
13080 /* Preserve register attributes for variable tracking. */
13085 /* Special case of reversed high/low parts. */
13088 {
13092 }
13094 {
13095 /* Try to avoid unnecessary moves if part of the result
13096 is in the right place already. */
13101 }
13102 else
13103 {
13108 }
13109 }
13111 /* vec_perm support. */
13113 #define MAX_VECT_LEN 16
13115 struct expand_vec_perm_d
13116 {
13119 machine_mode vmode;
13123 };
13125 /* Generate a variable permutation. */
13127 static void
13129 {
13140 {
13142 {
13143 /* Expand the argument to a V16QI mode by duplicating it. */
13147 }
13148 else
13149 {
13151 }
13152 }
13153 else
13154 {
13155 rtx pair;
13158 {
13162 }
13163 else
13164 {
13168 }
13169 }
13170 }
13172 void
13174 {
13178 rtx mask;
13180 /* The TBL instruction does not use a modulo index, so we must take care
13181 of that ourselves. */
13186 /* For big-endian, we also need to reverse the index within the vector
13187 (but not which vector). */
13189 {
13190 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
13195 }
13197 }
13199 /* Recognize patterns suitable for the TRN instructions. */
13200 static bool
13202 {
13211 /* Note that these are little-endian tests.
13212 We correct for big-endian later. */
13217 else
13222 {
13227 }
13229 /* Success! */
13236 {
13239 }
13243 {
13245 {
13260 }
13261 }
13262 else
13263 {
13265 {
13280 }
13281 }
13285 }
13287 /* Recognize patterns suitable for the UZP instructions. */
13288 static bool
13290 {
13299 /* Note that these are little-endian tests.
13300 We correct for big-endian later. */
13305 else
13310 {
13314 }
13316 /* Success! */
13323 {
13326 }
13330 {
13332 {
13347 }
13348 }
13349 else
13350 {
13352 {
13367 }
13368 }
13372 }
13374 /* Recognize patterns suitable for the ZIP instructions. */
13375 static bool
13377 {
13386 /* Note that these are little-endian tests.
13387 We correct for big-endian later. */
13390 /* Do Nothing. */
13391 ;
13394 else
13399 {
13406 }
13408 /* Success! */
13415 {
13418 }
13422 {
13424 {
13439 }
13440 }
13441 else
13442 {
13444 {
13459 }
13460 }
13464 }
13466 /* Recognize patterns for the EXT insn. */
13468 static bool
13470 {
13473 rtx offset;
13477 /* Check if the extracted indices are increasing by one. */
13479 {
13482 {
13483 /* We'll pass the same vector in twice, so allow indices to wrap. */
13485 }
13488 }
13491 {
13506 }
13508 /* Success! */
13512 /* The case where (location == 0) is a no-op for both big- and little-endian,
13513 and is removed by the mid-end at optimization levels -O1 and higher. */
13516 {
13517 /* After setup, we want the high elements of the first vector (stored
13518 at the LSB end of the register), and the low elements of the second
13519 vector (stored at the MSB end of the register). So swap. */
13521 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13523 }
13528 }
13530 /* Recognize patterns for the REV insns. */
13532 static bool
13534 {
13543 {
13546 {
13551 }
13555 {
13562 }
13566 {
13579 }
13583 }
13587 {
13588 /* This is guaranteed to be true as the value of diff
13589 is 7, 3, 1 and we should have enough elements in the
13590 queue to generate this. Getting a vector mask with a
13591 value of diff other than these values implies that
13592 something is wrong by the time we get here. */
13596 }
13598 /* Success! */
13604 }
13606 static bool
13608 {
13611 rtx in0;
13614 rtx lane;
13618 {
13621 }
13623 /* The generic preparation in aarch64_expand_vec_perm_const_1
13624 swaps the operand order and the permute indices if it finds
13625 d->perm[0] to be in the second operand. Thus, we can always
13626 use d->op0 and need not do any extra arithmetic to get the
13627 correct lane number. */
13632 {
13647 }
13651 }
13653 static bool
13655 {
13663 /* Generic code will try constant permutation twice. Once with the
13664 original mode and again with the elements lowered to QImode.
13665 So wait and don't do the selector expansion ourselves. */
13670 {
13673 /* If big-endian and two vectors we end up with a weird mixed-endian
13674 mode on NEON. Reverse the index within each word but not the word
13675 itself. */
13678 }
13684 }
13686 static bool
13688 {
13689 /* The pattern matching functions above are written to look for a small
13690 number to begin the sequence (0, 1, N/2). If we begin with an index
13691 from the second operand, we can swap the operands. */
13693 {
13701 }
13704 {
13718 }
13720 }
13722 /* Expand a vec_perm_const pattern. */
13724 bool
13726 {
13740 {
13745 }
13748 {
13757 /* The elements of PERM do not suggest that only the first operand
13758 is used, but both operands are identical. Allow easier matching
13759 of the permutation by folding the permutation into the single
13760 input vector. */
13761 /* Fall Through. */
13773 }
13776 }
13778 static bool
13781 {
13791 /* Calculate whether all elements are in one vector. */
13793 {
13797 }
13799 /* If all elements are from the second vector, reindex as if from the
13800 first vector. */
13805 /* Check whether the mask can be applied to a single vector. */
13818 }
13820 rtx
13822 {
13823 /* We have to reverse each vector because we dont have
13824 a permuted load that can reverse-load according to ABI rules. */
13825 rtx mask;
13839 }
13841 /* Implement MODES_TIEABLE_P. In principle we should always return true.
13842 However due to issues with register allocation it is preferable to avoid
13843 tieing integer scalar and FP scalar modes. Executing integer operations
13844 in general registers is better than treating them as scalar vector
13845 operations. This reduces latency and avoids redundant int<->FP moves.
13846 So tie modes if they are either the same class, or vector modes with
13847 other vector modes, vector structs or any scalar mode.
13848 */
13850 bool
13852 {
13856 /* We specifically want to allow elements of "structure" modes to
13857 be tieable to the structure. This more general condition allows
13858 other rarer situations too. */
13862 /* Also allow any scalar modes with vectors. */
13868 }
13870 /* Return a new RTX holding the result of moving POINTER forward by
13871 AMOUNT bytes. */
13873 static rtx
13875 {
13880 }
13882 /* Return a new RTX holding the result of moving POINTER forward by the
13883 size of the mode it points to. */
13885 static rtx
13887 {
13891 }
13893 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13894 MODE bytes. */
13896 static void
13898 machine_mode mode)
13899 {
13902 /* "Cast" the pointers to the correct mode. */
13905 /* Emit the memcpy. */
13908 /* Move the pointers forward. */
13911 }
13913 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13914 we succeed, otherwise return false. */
13916 bool
13918 {
13922 rtx base;
13925 /* When optimizing for size, give a better estimate of the length of a
13926 memcpy call, but use the default otherwise. */
13929 /* We can't do anything smart if the amount to copy is not constant. */
13935 /* Try to keep the number of instructions low. For cases below 16 bytes we
13936 need to make at most two moves. For cases above 16 bytes it will be one
13937 move for each 16 byte chunk, then at most two additional moves. */
13947 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13948 1-byte chunk. */
13950 {
13952 {
13955 }
13961 }
13963 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13964 4-byte chunk, partially overlapping with the previously copied chunk. */
13966 {
13970 {
13976 }
13978 }
13980 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13981 them, then (if applicable) an 8-byte chunk. */
13983 {
13985 {
13988 }
13989 else
13990 {
13993 }
13994 }
13996 /* Finish the final bytes of the copy. We can always do this in one
13997 instruction. We either copy the exact amount we need, or partially
13998 overlap with the previous chunk we copied and copy 8-bytes. */
14007 else
14008 {
14010 {
14014 }
14015 else
14016 {
14022 }
14023 }
14026 }
14028 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
14029 SImode stores. Handle the case when the constant has identical
14030 bottom and top halves. This is beneficial when the two stores can be
14031 merged into an STP and we avoid synthesising potentially expensive
14032 immediates twice. Return true if such a split is possible. */
14034 bool
14036 {
14045 unsigned int orig_cost
14047 unsigned int lo_cost
14050 /* We want to transform:
14051 MOV x1, 49370
14052 MOVK x1, 0x140, lsl 16
14053 MOVK x1, 0xc0da, lsl 32
14054 MOVK x1, 0x140, lsl 48
14055 STR x1, [x0]
14056 into:
14057 MOV w1, 49370
14058 MOVK w1, 0x140, lsl 16
14059 STP w1, w1, [x0]
14060 So we want to perform this only when we save two instructions
14061 or more. When optimizing for size, however, accept any code size
14062 savings we can. */
14077 /* Don't emit an explicit store pair as this may not be always profitable.
14078 Let the sched-fusion logic decide whether to merge them. */
14083 }
14085 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
14087 static unsigned HOST_WIDE_INT
14089 {
14091 }
14093 static bool
14098 {
14099 /* STORE_BY_PIECES can be used when copying a constant string, but
14100 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
14101 For now we always fail this and let the move_by_pieces code copy
14102 the string from read-only memory. */
14107 }
14109 static rtx
14112 {
14116 insn_code icode;
14127 {
14155 }
14160 {
14163 }
14172 {
14175 }
14181 }
14183 static rtx
14186 {
14190 insn_code icode;
14202 {
14230 }
14235 {
14238 }
14246 {
14251 }
14262 {
14265 }
14271 }
14273 #undef TARGET_GEN_CCMP_FIRST
14274 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
14276 #undef TARGET_GEN_CCMP_NEXT
14277 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
14279 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
14280 instruction fusion of some sort. */
14282 static bool
14284 {
14286 }
14289 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
14290 should be kept together during scheduling. */
14292 static bool
14294 {
14295 rtx set_dest;
14298 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
14305 {
14306 /* We are trying to match:
14307 prev (mov) == (set (reg r0) (const_int imm16))
14308 curr (movk) == (set (zero_extract (reg r0)
14309 (const_int 16)
14310 (const_int 16))
14311 (const_int imm16_1)) */
14323 {
14325 }
14326 }
14329 {
14331 /* We're trying to match:
14332 prev (adrp) == (set (reg r1)
14333 (high (symbol_ref ("SYM"))))
14334 curr (add) == (set (reg r0)
14335 (lo_sum (reg r1)
14336 (symbol_ref ("SYM"))))
14337 Note that r0 need not necessarily be the same as r1, especially
14338 during pre-regalloc scheduling. */
14342 {
14350 }
14351 }
14354 {
14356 /* We're trying to match:
14357 prev (movk) == (set (zero_extract (reg r0)
14358 (const_int 16)
14359 (const_int 32))
14360 (const_int imm16_1))
14361 curr (movk) == (set (zero_extract (reg r0)
14362 (const_int 16)
14363 (const_int 48))
14364 (const_int imm16_2)) */
14380 }
14382 {
14383 /* We're trying to match:
14384 prev (adrp) == (set (reg r0)
14385 (high (symbol_ref ("SYM"))))
14386 curr (ldr) == (set (reg r1)
14387 (mem (lo_sum (reg r0)
14388 (symbol_ref ("SYM")))))
14389 or
14390 curr (ldr) == (set (reg r1)
14391 (zero_extend (mem
14392 (lo_sum (reg r0)
14393 (symbol_ref ("SYM")))))) */
14396 {
14409 }
14410 }
14418 {
14422 rtx cc_reg_1;
14427 && prev
14429 {
14430 /* FIXME: this misses some which is considered simple arthematic
14431 instructions for ThunderX. Simple shifts are missed here. */
14437 }
14438 }
14441 && curr_set
14444 {
14445 /* We're trying to match:
14446 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
14447 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
14448 (const_int 0))
14449 (label_ref ("SYM"))
14450 (pc)) */
14457 {
14458 /* Fuse ALU operations followed by conditional branch instruction. */
14460 {
14481 }
14482 }
14483 }
14486 }
14488 /* Return true iff the instruction fusion described by OP is enabled. */
14490 bool
14492 {
14494 }
14496 /* If MEM is in the form of [base+offset], extract the two parts
14497 of address and set to BASE and OFFSET, otherwise return false
14498 after clearing BASE and OFFSET. */
14500 bool
14502 {
14503 rtx addr;
14510 {
14514 }
14518 {
14522 }
14528 }
14530 /* Types for scheduling fusion. */
14531 enum sched_fusion_type
14532 {
14534 SCHED_FUSION_LD_SIGN_EXTEND,
14535 SCHED_FUSION_LD_ZERO_EXTEND,
14536 SCHED_FUSION_LD,
14537 SCHED_FUSION_ST,
14538 SCHED_FUSION_NUM
14539 };
14541 /* If INSN is a load or store of address in the form of [base+offset],
14542 extract the two parts and set to BASE and OFFSET. Return scheduling
14543 fusion type this INSN is. */
14545 static enum sched_fusion_type
14547 {
14565 {
14570 }
14572 {
14577 }
14582 {
14585 }
14586 else
14593 }
14595 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14597 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14598 and PRI are only calculated for these instructions. For other instruction,
14599 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14600 type instruction fusion can be added by returning different priorities.
14602 It's important that irrelevant instructions get the largest FUSION_PRI. */
14604 static void
14607 {
14617 {
14621 }
14623 /* Set FUSION_PRI according to fusion type and base register. */
14626 /* Calculate PRI. */
14629 /* INSN with smaller offset goes first. */
14633 else
14638 }
14640 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14641 Adjust priority of sha1h instructions so they are scheduled before
14642 other SHA1 instructions. */
14644 static int
14646 {
14650 {
14655 }
14658 }
14660 /* Given OPERANDS of consecutive load/store, check if we can merge
14661 them into ldp/stp. LOAD is true if they are load instructions.
14662 MODE is the mode of memory operands. */
14664 bool
14666 machine_mode mode)
14667 {
14673 {
14681 }
14682 else
14683 {
14688 }
14690 /* The mems cannot be volatile. */
14694 /* If we have SImode and slow unaligned ldp,
14695 check the alignment to be at least 8 byte. */
14699 && !optimize_size
14703 /* Check if the addresses are in the form of [base+offset]. */
14711 /* Check if the bases are same. */
14718 /* Check if the offsets are consecutive. */
14722 /* Check if the addresses are clobbered by load. */
14724 {
14728 /* In increasing order, the last load can clobber the address. */
14731 }
14735 else
14740 else
14743 /* Check if the registers are of same class. */
14748 }
14750 /* Given OPERANDS of consecutive load/store, check if we can merge
14751 them into ldp/stp by adjusting the offset. LOAD is true if they
14752 are load instructions. MODE is the mode of memory operands.
14754 Given below consecutive stores:
14756 str w1, [xb, 0x100]
14757 str w1, [xb, 0x104]
14758 str w1, [xb, 0x108]
14759 str w1, [xb, 0x10c]
14761 Though the offsets are out of the range supported by stp, we can
14762 still pair them after adjusting the offset, like:
14764 add scratch, xb, 0x100
14765 stp w1, w1, [scratch]
14766 stp w1, w1, [scratch, 0x8]
14768 The peephole patterns detecting this opportunity should guarantee
14769 the scratch register is avaliable. */
14771 bool
14773 machine_mode mode)
14774 {
14781 {
14794 }
14795 else
14796 {
14805 }
14806 /* Skip if memory operand is by itslef valid for ldp/stp. */
14810 /* The mems cannot be volatile. */
14815 /* Check if the addresses are in the form of [base+offset]. */
14829 /* Check if the bases are same. */
14840 /* Check if the offsets are consecutive. */
14849 /* Check if the addresses are clobbered by load. */
14851 {
14857 /* In increasing order, the last load can clobber the address. */
14860 }
14862 /* If we have SImode and slow unaligned ldp,
14863 check the alignment to be at least 8 byte. */
14867 && !optimize_size
14873 else
14878 else
14883 else
14888 else
14891 /* Check if the registers are of same class. */
14896 }
14898 /* Given OPERANDS of consecutive load/store, this function pairs them
14899 into ldp/stp after adjusting the offset. It depends on the fact
14900 that addresses of load/store instructions are in increasing order.
14901 MODE is the mode of memory operands. CODE is the rtl operator
14902 which should be applied to all memory operands, it's SIGN_EXTEND,
14903 ZERO_EXTEND or UNKNOWN. */
14905 bool
14908 {
14914 {
14919 }
14920 else
14921 {
14927 }
14932 /* Adjust offset thus it can fit in ldp/stp instruction. */
14940 /* Further adjust to make sure all offsets are OK. */
14942 {
14945 }
14947 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14952 {
14955 }
14957 /* Create new memory references. */
14961 /* Check if the adjusted address is OK for ldp/stp. */
14980 {
14985 }
14987 {
14992 }
14995 {
15000 }
15001 else
15002 {
15007 }
15009 /* Emit adjusting instruction. */
15011 /* Emit ldp/stp instructions. */
15019 }
15021 /* Return 1 if pseudo register should be created and used to hold
15022 GOT address for PIC code. */
15024 bool
15026 {
15028 }
15030 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
15032 static int
15034 {
15036 {
15043 }
15046 }
15049 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
15050 return the log2 of that value. Otherwise return -1. */
15052 int
15054 {
15069 }
15071 /* If X is a vector of equal CONST_DOUBLE values and that value is
15072 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
15074 int
15076 {
15092 }
15094 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
15095 to float.
15097 __fp16 always promotes through this hook.
15098 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
15099 through the generic excess precision logic rather than here. */
15101 static tree
15103 {
15109 }
15111 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
15113 static bool
15115 optimization_type opt_type)
15116 {
15118 {
15124 }
15125 }
15127 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
15128 if MODE is HFmode, and punt to the generic implementation otherwise. */
15130 static bool
15132 {
15136 }
15138 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
15139 if MODE is HFmode, and punt to the generic implementation otherwise. */
15141 static bool
15143 {
15147 }
15149 /* Set the value of FLT_EVAL_METHOD.
15150 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
15152 0: evaluate all operations and constants, whose semantic type has at
15153 most the range and precision of type float, to the range and
15154 precision of float; evaluate all other operations and constants to
15155 the range and precision of the semantic type;
15157 N, where _FloatN is a supported interchange floating type
15158 evaluate all operations and constants, whose semantic type has at
15159 most the range and precision of _FloatN type, to the range and
15160 precision of the _FloatN type; evaluate all other operations and
15161 constants to the range and precision of the semantic type;
15163 If we have the ARMv8.2-A extensions then we support _Float16 in native
15164 precision, so we should set this to 16. Otherwise, we support the type,
15165 but want to evaluate expressions in float precision, so set this to
15166 0. */
15168 static enum flt_eval_method
15170 {
15172 {
15175 /* We can calculate either in 16-bit range and precision or
15176 32-bit range and precision. Make that decision based on whether
15177 we have native support for the ARMv8.2-A 16-bit floating-point
15178 instructions or not. */
15180 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
15186 }
15188 }
15190 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
15191 scheduled for speculative execution. Reject the long-running division
15192 and square-root instructions. */
15194 static bool
15196 {
15198 {
15216 }
15217 }
15219 /* Target-specific selftests. */
15221 #if CHECKING_P
15225 /* Selftest for the RTL loader.
15226 Verify that the RTL loader copes with a dump from
15227 print_rtx_function. This is essentially just a test that class
15228 function_reader can handle a real dump, but it also verifies
15229 that lookup_reg_by_dump_name correctly handles hard regs.
15230 The presence of hard reg names in the dump means that the test is
15231 target-specific, hence it is in this file. */
15233 static void
15235 {
15247 /* Verify crtl->return_rtx. */
15251 }
15253 /* Run all target-specific selftests. */
15255 static void
15257 {
15259 }
15265 #undef TARGET_ADDRESS_COST
15266 #define TARGET_ADDRESS_COST aarch64_address_cost
15268 /* This hook will determines whether unnamed bitfields affect the alignment
15269 of the containing structure. The hook returns true if the structure
15270 should inherit the alignment requirements of an unnamed bitfield's
15271 type. */
15272 #undef TARGET_ALIGN_ANON_BITFIELD
15273 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
15275 #undef TARGET_ASM_ALIGNED_DI_OP
15278 #undef TARGET_ASM_ALIGNED_HI_OP
15281 #undef TARGET_ASM_ALIGNED_SI_OP
15284 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
15285 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
15286 hook_bool_const_tree_hwi_hwi_const_tree_true
15288 #undef TARGET_ASM_FILE_START
15289 #define TARGET_ASM_FILE_START aarch64_start_file
15291 #undef TARGET_ASM_OUTPUT_MI_THUNK
15292 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
15294 #undef TARGET_ASM_SELECT_RTX_SECTION
15295 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
15297 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
15298 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
15300 #undef TARGET_BUILD_BUILTIN_VA_LIST
15301 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
15303 #undef TARGET_CALLEE_COPIES
15304 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
15306 #undef TARGET_CAN_ELIMINATE
15307 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
15309 #undef TARGET_CAN_INLINE_P
15310 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
15312 #undef TARGET_CANNOT_FORCE_CONST_MEM
15313 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
15315 #undef TARGET_CASE_VALUES_THRESHOLD
15316 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
15318 #undef TARGET_CONDITIONAL_REGISTER_USAGE
15319 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
15321 /* Only the least significant bit is used for initialization guard
15322 variables. */
15323 #undef TARGET_CXX_GUARD_MASK_BIT
15324 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
15326 #undef TARGET_C_MODE_FOR_SUFFIX
15327 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
15329 #ifdef TARGET_BIG_ENDIAN_DEFAULT
15330 #undef TARGET_DEFAULT_TARGET_FLAGS
15331 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
15332 #endif
15334 #undef TARGET_CLASS_MAX_NREGS
15335 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
15337 #undef TARGET_BUILTIN_DECL
15338 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
15340 #undef TARGET_BUILTIN_RECIPROCAL
15341 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
15343 #undef TARGET_C_EXCESS_PRECISION
15344 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
15346 #undef TARGET_EXPAND_BUILTIN
15347 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
15349 #undef TARGET_EXPAND_BUILTIN_VA_START
15350 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
15352 #undef TARGET_FOLD_BUILTIN
15353 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
15355 #undef TARGET_FUNCTION_ARG
15356 #define TARGET_FUNCTION_ARG aarch64_function_arg
15358 #undef TARGET_FUNCTION_ARG_ADVANCE
15359 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
15361 #undef TARGET_FUNCTION_ARG_BOUNDARY
15362 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
15364 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
15365 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
15367 #undef TARGET_FUNCTION_VALUE
15368 #define TARGET_FUNCTION_VALUE aarch64_function_value
15370 #undef TARGET_FUNCTION_VALUE_REGNO_P
15371 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
15373 #undef TARGET_FRAME_POINTER_REQUIRED
15374 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
15376 #undef TARGET_GIMPLE_FOLD_BUILTIN
15377 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
15379 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
15380 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
15382 #undef TARGET_INIT_BUILTINS
15383 #define TARGET_INIT_BUILTINS aarch64_init_builtins
15385 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
15386 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
15387 aarch64_ira_change_pseudo_allocno_class
15389 #undef TARGET_LEGITIMATE_ADDRESS_P
15390 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
15392 #undef TARGET_LEGITIMATE_CONSTANT_P
15393 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
15395 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
15396 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
15397 aarch64_legitimize_address_displacement
15399 #undef TARGET_LIBGCC_CMP_RETURN_MODE
15400 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
15402 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
15403 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
15404 aarch64_libgcc_floating_mode_supported_p
15406 #undef TARGET_MANGLE_TYPE
15407 #define TARGET_MANGLE_TYPE aarch64_mangle_type
15409 #undef TARGET_MEMORY_MOVE_COST
15410 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
15412 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
15413 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
15415 #undef TARGET_MUST_PASS_IN_STACK
15416 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
15418 /* This target hook should return true if accesses to volatile bitfields
15419 should use the narrowest mode possible. It should return false if these
15420 accesses should use the bitfield container type. */
15421 #undef TARGET_NARROW_VOLATILE_BITFIELD
15422 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
15424 #undef TARGET_OPTION_OVERRIDE
15425 #define TARGET_OPTION_OVERRIDE aarch64_override_options
15427 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
15428 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
15429 aarch64_override_options_after_change
15431 #undef TARGET_OPTION_SAVE
15432 #define TARGET_OPTION_SAVE aarch64_option_save
15434 #undef TARGET_OPTION_RESTORE
15435 #define TARGET_OPTION_RESTORE aarch64_option_restore
15437 #undef TARGET_OPTION_PRINT
15438 #define TARGET_OPTION_PRINT aarch64_option_print
15440 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
15441 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
15443 #undef TARGET_SET_CURRENT_FUNCTION
15444 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
15446 #undef TARGET_PASS_BY_REFERENCE
15447 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
15449 #undef TARGET_PREFERRED_RELOAD_CLASS
15450 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
15452 #undef TARGET_SCHED_REASSOCIATION_WIDTH
15453 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
15455 #undef TARGET_PROMOTED_TYPE
15456 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
15458 #undef TARGET_SECONDARY_RELOAD
15459 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
15461 #undef TARGET_SHIFT_TRUNCATION_MASK
15462 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
15464 #undef TARGET_SETUP_INCOMING_VARARGS
15465 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
15467 #undef TARGET_STRUCT_VALUE_RTX
15468 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
15470 #undef TARGET_REGISTER_MOVE_COST
15471 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
15473 #undef TARGET_RETURN_IN_MEMORY
15474 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
15476 #undef TARGET_RETURN_IN_MSB
15477 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
15479 #undef TARGET_RTX_COSTS
15480 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
15482 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15483 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
15485 #undef TARGET_SCHED_ISSUE_RATE
15486 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
15488 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15489 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15490 aarch64_sched_first_cycle_multipass_dfa_lookahead
15492 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
15493 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
15494 aarch64_first_cycle_multipass_dfa_lookahead_guard
15496 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
15497 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
15498 aarch64_get_separate_components
15500 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
15501 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
15502 aarch64_components_for_bb
15504 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
15505 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
15506 aarch64_disqualify_components
15508 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
15509 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
15510 aarch64_emit_prologue_components
15512 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
15513 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
15514 aarch64_emit_epilogue_components
15516 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
15517 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
15518 aarch64_set_handled_components
15520 #undef TARGET_TRAMPOLINE_INIT
15521 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
15523 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15524 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
15526 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15527 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
15529 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
15530 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
15531 aarch64_builtin_support_vector_misalignment
15533 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15534 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15536 #undef TARGET_VECTORIZE_ADD_STMT_COST
15537 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15539 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15540 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15541 aarch64_builtin_vectorization_cost
15543 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15544 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15546 #undef TARGET_VECTORIZE_BUILTINS
15547 #define TARGET_VECTORIZE_BUILTINS
15549 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15550 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15551 aarch64_builtin_vectorized_function
15553 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15554 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15555 aarch64_autovectorize_vector_sizes
15557 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15558 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15559 aarch64_atomic_assign_expand_fenv
15561 /* Section anchor support. */
15563 #undef TARGET_MIN_ANCHOR_OFFSET
15564 #define TARGET_MIN_ANCHOR_OFFSET -256
15566 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15567 byte offset; we can do much more for larger data types, but have no way
15568 to determine the size of the access. We assume accesses are aligned. */
15569 #undef TARGET_MAX_ANCHOR_OFFSET
15570 #define TARGET_MAX_ANCHOR_OFFSET 4095
15572 #undef TARGET_VECTOR_ALIGNMENT
15573 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15575 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15576 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15577 aarch64_simd_vector_alignment_reachable
15579 /* vec_perm support. */
15581 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15582 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15583 aarch64_vectorize_vec_perm_const_ok
15585 #undef TARGET_INIT_LIBFUNCS
15586 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15588 #undef TARGET_FIXED_CONDITION_CODE_REGS
15589 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15591 #undef TARGET_FLAGS_REGNUM
15592 #define TARGET_FLAGS_REGNUM CC_REGNUM
15594 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15595 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15597 #undef TARGET_ASAN_SHADOW_OFFSET
15598 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15600 #undef TARGET_LEGITIMIZE_ADDRESS
15601 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15603 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15604 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15605 aarch64_use_by_pieces_infrastructure_p
15607 #undef TARGET_SCHED_CAN_SPECULATE_INSN
15608 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
15610 #undef TARGET_CAN_USE_DOLOOP_P
15611 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15613 #undef TARGET_SCHED_ADJUST_PRIORITY
15614 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15616 #undef TARGET_SCHED_MACRO_FUSION_P
15617 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15619 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15620 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15622 #undef TARGET_SCHED_FUSION_PRIORITY
15623 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15625 #undef TARGET_UNSPEC_MAY_TRAP_P
15626 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15628 #undef TARGET_USE_PSEUDO_PIC_REG
15629 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15631 #undef TARGET_PRINT_OPERAND
15632 #define TARGET_PRINT_OPERAND aarch64_print_operand
15634 #undef TARGET_PRINT_OPERAND_ADDRESS
15635 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15637 #undef TARGET_OPTAB_SUPPORTED_P
15638 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15640 #undef TARGET_OMIT_STRUCT_RETURN_REG
15641 #define TARGET_OMIT_STRUCT_RETURN_REG true
15643 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15644 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15645 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15647 #if CHECKING_P
15648 #undef TARGET_RUN_TARGET_SELFTESTS
15649 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests