| blob | 5f297ccdc6923d73ea1967d74af3ce145dba160b |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; UNSPEC usage
27 ;;
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit
54 ])
56 ;;
57 ;; UNSPEC_VOLATILE usage
58 ;;
60 (define_constants
61 [(UNSPECV_BLOCK 0)
62 (UNSPECV_EH_RR 9) ; eh_reg_restore
63 ])
64 \f
65 ;; Define an insn type attribute. This is used in function unit delay
66 ;; computations.
67 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
68 (const_string "integer"))
70 ;; Length (in bytes).
71 ; '(pc)' in the following doesn't include the instruction itself; it is
72 ; calculated as if the instruction had zero size.
73 (define_attr "length" ""
74 (if_then_else (eq_attr "type" "branch")
75 (if_then_else (and (ge (minus (match_dup 0) (pc))
76 (const_int -32768))
77 (lt (minus (match_dup 0) (pc))
78 (const_int 32764)))
79 (const_int 4)
80 (const_int 8))
81 (const_int 4)))
83 ;; Processor type -- this attribute must exactly match the processor_type
84 ;; enumeration in rs6000.h.
86 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
87 (const (symbol_ref "rs6000_cpu_attr")))
89 (automata_option "ndfa")
91 (include "rios1.md")
92 (include "rios2.md")
93 (include "rs64.md")
94 (include "mpc.md")
95 (include "40x.md")
96 (include "440.md")
97 (include "603.md")
98 (include "6xx.md")
99 (include "7xx.md")
100 (include "7450.md")
101 (include "8540.md")
102 (include "power4.md")
103 (include "power5.md")
105 (include "predicates.md")
107 (include "darwin.md")
109 \f
110 ;; This mode macro allows :P to be used for patterns that operate on
111 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
112 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
114 ;; Start with fixed-point load and store insns. Here we put only the more
115 ;; complex forms. Basic data transfer is done later.
117 (define_expand "zero_extendqidi2"
118 [(set (match_operand:DI 0 "gpc_reg_operand" "")
119 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
120 "TARGET_POWERPC64"
121 "")
123 (define_insn ""
124 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
125 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
126 "TARGET_POWERPC64"
127 "@
128 lbz%U1%X1 %0,%1
129 rldicl %0,%1,0,56"
130 [(set_attr "type" "load,*")])
132 (define_insn ""
133 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
134 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
135 (const_int 0)))
136 (clobber (match_scratch:DI 2 "=r,r"))]
137 "TARGET_64BIT"
138 "@
139 rldicl. %2,%1,0,56
140 #"
141 [(set_attr "type" "compare")
142 (set_attr "length" "4,8")])
144 (define_split
145 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
146 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
147 (const_int 0)))
148 (clobber (match_scratch:DI 2 ""))]
149 "TARGET_POWERPC64 && reload_completed"
150 [(set (match_dup 2)
151 (zero_extend:DI (match_dup 1)))
152 (set (match_dup 0)
153 (compare:CC (match_dup 2)
154 (const_int 0)))]
155 "")
157 (define_insn ""
158 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
159 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
160 (const_int 0)))
161 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
162 (zero_extend:DI (match_dup 1)))]
163 "TARGET_64BIT"
164 "@
165 rldicl. %0,%1,0,56
166 #"
167 [(set_attr "type" "compare")
168 (set_attr "length" "4,8")])
170 (define_split
171 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
172 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
173 (const_int 0)))
174 (set (match_operand:DI 0 "gpc_reg_operand" "")
175 (zero_extend:DI (match_dup 1)))]
176 "TARGET_POWERPC64 && reload_completed"
177 [(set (match_dup 0)
178 (zero_extend:DI (match_dup 1)))
179 (set (match_dup 2)
180 (compare:CC (match_dup 0)
181 (const_int 0)))]
182 "")
184 (define_insn "extendqidi2"
185 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
186 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
187 "TARGET_POWERPC64"
188 "extsb %0,%1")
190 (define_insn ""
191 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
192 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
193 (const_int 0)))
194 (clobber (match_scratch:DI 2 "=r,r"))]
195 "TARGET_64BIT"
196 "@
197 extsb. %2,%1
198 #"
199 [(set_attr "type" "compare")
200 (set_attr "length" "4,8")])
202 (define_split
203 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
204 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
205 (const_int 0)))
206 (clobber (match_scratch:DI 2 ""))]
207 "TARGET_POWERPC64 && reload_completed"
208 [(set (match_dup 2)
209 (sign_extend:DI (match_dup 1)))
210 (set (match_dup 0)
211 (compare:CC (match_dup 2)
212 (const_int 0)))]
213 "")
215 (define_insn ""
216 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
217 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
218 (const_int 0)))
219 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
220 (sign_extend:DI (match_dup 1)))]
221 "TARGET_64BIT"
222 "@
223 extsb. %0,%1
224 #"
225 [(set_attr "type" "compare")
226 (set_attr "length" "4,8")])
228 (define_split
229 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
230 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
231 (const_int 0)))
232 (set (match_operand:DI 0 "gpc_reg_operand" "")
233 (sign_extend:DI (match_dup 1)))]
234 "TARGET_POWERPC64 && reload_completed"
235 [(set (match_dup 0)
236 (sign_extend:DI (match_dup 1)))
237 (set (match_dup 2)
238 (compare:CC (match_dup 0)
239 (const_int 0)))]
240 "")
242 (define_expand "zero_extendhidi2"
243 [(set (match_operand:DI 0 "gpc_reg_operand" "")
244 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
245 "TARGET_POWERPC64"
246 "")
248 (define_insn ""
249 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
250 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
251 "TARGET_POWERPC64"
252 "@
253 lhz%U1%X1 %0,%1
254 rldicl %0,%1,0,48"
255 [(set_attr "type" "load,*")])
257 (define_insn ""
258 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
259 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
260 (const_int 0)))
261 (clobber (match_scratch:DI 2 "=r,r"))]
262 "TARGET_64BIT"
263 "@
264 rldicl. %2,%1,0,48
265 #"
266 [(set_attr "type" "compare")
267 (set_attr "length" "4,8")])
269 (define_split
270 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
271 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
272 (const_int 0)))
273 (clobber (match_scratch:DI 2 ""))]
274 "TARGET_POWERPC64 && reload_completed"
275 [(set (match_dup 2)
276 (zero_extend:DI (match_dup 1)))
277 (set (match_dup 0)
278 (compare:CC (match_dup 2)
279 (const_int 0)))]
280 "")
282 (define_insn ""
283 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
284 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
285 (const_int 0)))
286 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287 (zero_extend:DI (match_dup 1)))]
288 "TARGET_64BIT"
289 "@
290 rldicl. %0,%1,0,48
291 #"
292 [(set_attr "type" "compare")
293 (set_attr "length" "4,8")])
295 (define_split
296 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
297 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
298 (const_int 0)))
299 (set (match_operand:DI 0 "gpc_reg_operand" "")
300 (zero_extend:DI (match_dup 1)))]
301 "TARGET_POWERPC64 && reload_completed"
302 [(set (match_dup 0)
303 (zero_extend:DI (match_dup 1)))
304 (set (match_dup 2)
305 (compare:CC (match_dup 0)
306 (const_int 0)))]
307 "")
309 (define_expand "extendhidi2"
310 [(set (match_operand:DI 0 "gpc_reg_operand" "")
311 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
312 "TARGET_POWERPC64"
313 "")
315 (define_insn ""
316 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
317 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
318 "TARGET_POWERPC64"
319 "@
320 lha%U1%X1 %0,%1
321 extsh %0,%1"
322 [(set_attr "type" "load_ext,*")])
324 (define_insn ""
325 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
326 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
327 (const_int 0)))
328 (clobber (match_scratch:DI 2 "=r,r"))]
329 "TARGET_64BIT"
330 "@
331 extsh. %2,%1
332 #"
333 [(set_attr "type" "compare")
334 (set_attr "length" "4,8")])
336 (define_split
337 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
338 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
339 (const_int 0)))
340 (clobber (match_scratch:DI 2 ""))]
341 "TARGET_POWERPC64 && reload_completed"
342 [(set (match_dup 2)
343 (sign_extend:DI (match_dup 1)))
344 (set (match_dup 0)
345 (compare:CC (match_dup 2)
346 (const_int 0)))]
347 "")
349 (define_insn ""
350 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
351 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
352 (const_int 0)))
353 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
354 (sign_extend:DI (match_dup 1)))]
355 "TARGET_64BIT"
356 "@
357 extsh. %0,%1
358 #"
359 [(set_attr "type" "compare")
360 (set_attr "length" "4,8")])
362 (define_split
363 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
364 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
365 (const_int 0)))
366 (set (match_operand:DI 0 "gpc_reg_operand" "")
367 (sign_extend:DI (match_dup 1)))]
368 "TARGET_POWERPC64 && reload_completed"
369 [(set (match_dup 0)
370 (sign_extend:DI (match_dup 1)))
371 (set (match_dup 2)
372 (compare:CC (match_dup 0)
373 (const_int 0)))]
374 "")
376 (define_expand "zero_extendsidi2"
377 [(set (match_operand:DI 0 "gpc_reg_operand" "")
378 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
379 "TARGET_POWERPC64"
380 "")
382 (define_insn ""
383 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
384 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
385 "TARGET_POWERPC64"
386 "@
387 lwz%U1%X1 %0,%1
388 rldicl %0,%1,0,32"
389 [(set_attr "type" "load,*")])
391 (define_insn ""
392 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
393 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
394 (const_int 0)))
395 (clobber (match_scratch:DI 2 "=r,r"))]
396 "TARGET_64BIT"
397 "@
398 rldicl. %2,%1,0,32
399 #"
400 [(set_attr "type" "compare")
401 (set_attr "length" "4,8")])
403 (define_split
404 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
405 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
406 (const_int 0)))
407 (clobber (match_scratch:DI 2 ""))]
408 "TARGET_POWERPC64 && reload_completed"
409 [(set (match_dup 2)
410 (zero_extend:DI (match_dup 1)))
411 (set (match_dup 0)
412 (compare:CC (match_dup 2)
413 (const_int 0)))]
414 "")
416 (define_insn ""
417 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
418 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
419 (const_int 0)))
420 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
421 (zero_extend:DI (match_dup 1)))]
422 "TARGET_64BIT"
423 "@
424 rldicl. %0,%1,0,32
425 #"
426 [(set_attr "type" "compare")
427 (set_attr "length" "4,8")])
429 (define_split
430 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
431 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
432 (const_int 0)))
433 (set (match_operand:DI 0 "gpc_reg_operand" "")
434 (zero_extend:DI (match_dup 1)))]
435 "TARGET_POWERPC64 && reload_completed"
436 [(set (match_dup 0)
437 (zero_extend:DI (match_dup 1)))
438 (set (match_dup 2)
439 (compare:CC (match_dup 0)
440 (const_int 0)))]
441 "")
443 (define_expand "extendsidi2"
444 [(set (match_operand:DI 0 "gpc_reg_operand" "")
445 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
446 "TARGET_POWERPC64"
447 "")
449 (define_insn ""
450 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
451 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
452 "TARGET_POWERPC64"
453 "@
454 lwa%U1%X1 %0,%1
455 extsw %0,%1"
456 [(set_attr "type" "load_ext,*")])
458 (define_insn ""
459 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
460 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
461 (const_int 0)))
462 (clobber (match_scratch:DI 2 "=r,r"))]
463 "TARGET_64BIT"
464 "@
465 extsw. %2,%1
466 #"
467 [(set_attr "type" "compare")
468 (set_attr "length" "4,8")])
470 (define_split
471 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
472 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
473 (const_int 0)))
474 (clobber (match_scratch:DI 2 ""))]
475 "TARGET_POWERPC64 && reload_completed"
476 [(set (match_dup 2)
477 (sign_extend:DI (match_dup 1)))
478 (set (match_dup 0)
479 (compare:CC (match_dup 2)
480 (const_int 0)))]
481 "")
483 (define_insn ""
484 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
485 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
486 (const_int 0)))
487 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
488 (sign_extend:DI (match_dup 1)))]
489 "TARGET_64BIT"
490 "@
491 extsw. %0,%1
492 #"
493 [(set_attr "type" "compare")
494 (set_attr "length" "4,8")])
496 (define_split
497 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
498 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
499 (const_int 0)))
500 (set (match_operand:DI 0 "gpc_reg_operand" "")
501 (sign_extend:DI (match_dup 1)))]
502 "TARGET_POWERPC64 && reload_completed"
503 [(set (match_dup 0)
504 (sign_extend:DI (match_dup 1)))
505 (set (match_dup 2)
506 (compare:CC (match_dup 0)
507 (const_int 0)))]
508 "")
510 (define_expand "zero_extendqisi2"
511 [(set (match_operand:SI 0 "gpc_reg_operand" "")
512 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
513 ""
514 "")
516 (define_insn ""
517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
518 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
519 ""
520 "@
521 lbz%U1%X1 %0,%1
522 {rlinm|rlwinm} %0,%1,0,0xff"
523 [(set_attr "type" "load,*")])
525 (define_insn ""
526 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
527 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
528 (const_int 0)))
529 (clobber (match_scratch:SI 2 "=r,r"))]
530 ""
531 "@
532 {andil.|andi.} %2,%1,0xff
533 #"
534 [(set_attr "type" "compare")
535 (set_attr "length" "4,8")])
537 (define_split
538 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
539 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
540 (const_int 0)))
541 (clobber (match_scratch:SI 2 ""))]
542 "reload_completed"
543 [(set (match_dup 2)
544 (zero_extend:SI (match_dup 1)))
545 (set (match_dup 0)
546 (compare:CC (match_dup 2)
547 (const_int 0)))]
548 "")
550 (define_insn ""
551 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
552 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
553 (const_int 0)))
554 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
555 (zero_extend:SI (match_dup 1)))]
556 ""
557 "@
558 {andil.|andi.} %0,%1,0xff
559 #"
560 [(set_attr "type" "compare")
561 (set_attr "length" "4,8")])
563 (define_split
564 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
565 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
566 (const_int 0)))
567 (set (match_operand:SI 0 "gpc_reg_operand" "")
568 (zero_extend:SI (match_dup 1)))]
569 "reload_completed"
570 [(set (match_dup 0)
571 (zero_extend:SI (match_dup 1)))
572 (set (match_dup 2)
573 (compare:CC (match_dup 0)
574 (const_int 0)))]
575 "")
577 (define_expand "extendqisi2"
578 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
579 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
580 ""
581 "
582 {
583 if (TARGET_POWERPC)
584 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
585 else if (TARGET_POWER)
586 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
587 else
588 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
589 DONE;
590 }")
592 (define_insn "extendqisi2_ppc"
593 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
594 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
595 "TARGET_POWERPC"
596 "extsb %0,%1")
598 (define_insn ""
599 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
600 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
601 (const_int 0)))
602 (clobber (match_scratch:SI 2 "=r,r"))]
603 "TARGET_POWERPC"
604 "@
605 extsb. %2,%1
606 #"
607 [(set_attr "type" "compare")
608 (set_attr "length" "4,8")])
610 (define_split
611 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
612 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
613 (const_int 0)))
614 (clobber (match_scratch:SI 2 ""))]
615 "TARGET_POWERPC && reload_completed"
616 [(set (match_dup 2)
617 (sign_extend:SI (match_dup 1)))
618 (set (match_dup 0)
619 (compare:CC (match_dup 2)
620 (const_int 0)))]
621 "")
623 (define_insn ""
624 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
625 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
626 (const_int 0)))
627 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
628 (sign_extend:SI (match_dup 1)))]
629 "TARGET_POWERPC"
630 "@
631 extsb. %0,%1
632 #"
633 [(set_attr "type" "compare")
634 (set_attr "length" "4,8")])
636 (define_split
637 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
638 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
639 (const_int 0)))
640 (set (match_operand:SI 0 "gpc_reg_operand" "")
641 (sign_extend:SI (match_dup 1)))]
642 "TARGET_POWERPC && reload_completed"
643 [(set (match_dup 0)
644 (sign_extend:SI (match_dup 1)))
645 (set (match_dup 2)
646 (compare:CC (match_dup 0)
647 (const_int 0)))]
648 "")
650 (define_expand "extendqisi2_power"
651 [(parallel [(set (match_dup 2)
652 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
653 (const_int 24)))
654 (clobber (scratch:SI))])
655 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
656 (ashiftrt:SI (match_dup 2)
657 (const_int 24)))
658 (clobber (scratch:SI))])]
659 "TARGET_POWER"
660 "
661 { operands[1] = gen_lowpart (SImode, operands[1]);
662 operands[2] = gen_reg_rtx (SImode); }")
664 (define_expand "extendqisi2_no_power"
665 [(set (match_dup 2)
666 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
667 (const_int 24)))
668 (set (match_operand:SI 0 "gpc_reg_operand" "")
669 (ashiftrt:SI (match_dup 2)
670 (const_int 24)))]
671 "! TARGET_POWER && ! TARGET_POWERPC"
672 "
673 { operands[1] = gen_lowpart (SImode, operands[1]);
674 operands[2] = gen_reg_rtx (SImode); }")
676 (define_expand "zero_extendqihi2"
677 [(set (match_operand:HI 0 "gpc_reg_operand" "")
678 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
679 ""
680 "")
682 (define_insn ""
683 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
684 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
685 ""
686 "@
687 lbz%U1%X1 %0,%1
688 {rlinm|rlwinm} %0,%1,0,0xff"
689 [(set_attr "type" "load,*")])
691 (define_insn ""
692 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
693 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
694 (const_int 0)))
695 (clobber (match_scratch:HI 2 "=r,r"))]
696 ""
697 "@
698 {andil.|andi.} %2,%1,0xff
699 #"
700 [(set_attr "type" "compare")
701 (set_attr "length" "4,8")])
703 (define_split
704 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
705 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
706 (const_int 0)))
707 (clobber (match_scratch:HI 2 ""))]
708 "reload_completed"
709 [(set (match_dup 2)
710 (zero_extend:HI (match_dup 1)))
711 (set (match_dup 0)
712 (compare:CC (match_dup 2)
713 (const_int 0)))]
714 "")
716 (define_insn ""
717 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
718 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
719 (const_int 0)))
720 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
721 (zero_extend:HI (match_dup 1)))]
722 ""
723 "@
724 {andil.|andi.} %0,%1,0xff
725 #"
726 [(set_attr "type" "compare")
727 (set_attr "length" "4,8")])
729 (define_split
730 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
731 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
732 (const_int 0)))
733 (set (match_operand:HI 0 "gpc_reg_operand" "")
734 (zero_extend:HI (match_dup 1)))]
735 "reload_completed"
736 [(set (match_dup 0)
737 (zero_extend:HI (match_dup 1)))
738 (set (match_dup 2)
739 (compare:CC (match_dup 0)
740 (const_int 0)))]
741 "")
743 (define_expand "extendqihi2"
744 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
745 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
746 ""
747 "
748 {
749 if (TARGET_POWERPC)
750 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
751 else if (TARGET_POWER)
752 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
753 else
754 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
755 DONE;
756 }")
758 (define_insn "extendqihi2_ppc"
759 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
760 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
761 "TARGET_POWERPC"
762 "extsb %0,%1")
764 (define_insn ""
765 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
766 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
767 (const_int 0)))
768 (clobber (match_scratch:HI 2 "=r,r"))]
769 "TARGET_POWERPC"
770 "@
771 extsb. %2,%1
772 #"
773 [(set_attr "type" "compare")
774 (set_attr "length" "4,8")])
776 (define_split
777 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
778 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
779 (const_int 0)))
780 (clobber (match_scratch:HI 2 ""))]
781 "TARGET_POWERPC && reload_completed"
782 [(set (match_dup 2)
783 (sign_extend:HI (match_dup 1)))
784 (set (match_dup 0)
785 (compare:CC (match_dup 2)
786 (const_int 0)))]
787 "")
789 (define_insn ""
790 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
791 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
792 (const_int 0)))
793 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
794 (sign_extend:HI (match_dup 1)))]
795 "TARGET_POWERPC"
796 "@
797 extsb. %0,%1
798 #"
799 [(set_attr "type" "compare")
800 (set_attr "length" "4,8")])
802 (define_split
803 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
804 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
805 (const_int 0)))
806 (set (match_operand:HI 0 "gpc_reg_operand" "")
807 (sign_extend:HI (match_dup 1)))]
808 "TARGET_POWERPC && reload_completed"
809 [(set (match_dup 0)
810 (sign_extend:HI (match_dup 1)))
811 (set (match_dup 2)
812 (compare:CC (match_dup 0)
813 (const_int 0)))]
814 "")
816 (define_expand "extendqihi2_power"
817 [(parallel [(set (match_dup 2)
818 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
819 (const_int 24)))
820 (clobber (scratch:SI))])
821 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
822 (ashiftrt:SI (match_dup 2)
823 (const_int 24)))
824 (clobber (scratch:SI))])]
825 "TARGET_POWER"
826 "
827 { operands[0] = gen_lowpart (SImode, operands[0]);
828 operands[1] = gen_lowpart (SImode, operands[1]);
829 operands[2] = gen_reg_rtx (SImode); }")
831 (define_expand "extendqihi2_no_power"
832 [(set (match_dup 2)
833 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
834 (const_int 24)))
835 (set (match_operand:HI 0 "gpc_reg_operand" "")
836 (ashiftrt:SI (match_dup 2)
837 (const_int 24)))]
838 "! TARGET_POWER && ! TARGET_POWERPC"
839 "
840 { operands[0] = gen_lowpart (SImode, operands[0]);
841 operands[1] = gen_lowpart (SImode, operands[1]);
842 operands[2] = gen_reg_rtx (SImode); }")
844 (define_expand "zero_extendhisi2"
845 [(set (match_operand:SI 0 "gpc_reg_operand" "")
846 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
847 ""
848 "")
850 (define_insn ""
851 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
852 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
853 ""
854 "@
855 lhz%U1%X1 %0,%1
856 {rlinm|rlwinm} %0,%1,0,0xffff"
857 [(set_attr "type" "load,*")])
859 (define_insn ""
860 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
861 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
862 (const_int 0)))
863 (clobber (match_scratch:SI 2 "=r,r"))]
864 ""
865 "@
866 {andil.|andi.} %2,%1,0xffff
867 #"
868 [(set_attr "type" "compare")
869 (set_attr "length" "4,8")])
871 (define_split
872 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
873 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
874 (const_int 0)))
875 (clobber (match_scratch:SI 2 ""))]
876 "reload_completed"
877 [(set (match_dup 2)
878 (zero_extend:SI (match_dup 1)))
879 (set (match_dup 0)
880 (compare:CC (match_dup 2)
881 (const_int 0)))]
882 "")
884 (define_insn ""
885 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
886 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
887 (const_int 0)))
888 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
889 (zero_extend:SI (match_dup 1)))]
890 ""
891 "@
892 {andil.|andi.} %0,%1,0xffff
893 #"
894 [(set_attr "type" "compare")
895 (set_attr "length" "4,8")])
897 (define_split
898 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
899 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
900 (const_int 0)))
901 (set (match_operand:SI 0 "gpc_reg_operand" "")
902 (zero_extend:SI (match_dup 1)))]
903 "reload_completed"
904 [(set (match_dup 0)
905 (zero_extend:SI (match_dup 1)))
906 (set (match_dup 2)
907 (compare:CC (match_dup 0)
908 (const_int 0)))]
909 "")
911 (define_expand "extendhisi2"
912 [(set (match_operand:SI 0 "gpc_reg_operand" "")
913 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
914 ""
915 "")
917 (define_insn ""
918 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
919 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
920 ""
921 "@
922 lha%U1%X1 %0,%1
923 {exts|extsh} %0,%1"
924 [(set_attr "type" "load_ext,*")])
926 (define_insn ""
927 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
928 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
929 (const_int 0)))
930 (clobber (match_scratch:SI 2 "=r,r"))]
931 ""
932 "@
933 {exts.|extsh.} %2,%1
934 #"
935 [(set_attr "type" "compare")
936 (set_attr "length" "4,8")])
938 (define_split
939 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
940 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
941 (const_int 0)))
942 (clobber (match_scratch:SI 2 ""))]
943 "reload_completed"
944 [(set (match_dup 2)
945 (sign_extend:SI (match_dup 1)))
946 (set (match_dup 0)
947 (compare:CC (match_dup 2)
948 (const_int 0)))]
949 "")
951 (define_insn ""
952 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
953 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
954 (const_int 0)))
955 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
956 (sign_extend:SI (match_dup 1)))]
957 ""
958 "@
959 {exts.|extsh.} %0,%1
960 #"
961 [(set_attr "type" "compare")
962 (set_attr "length" "4,8")])
963 \f
964 (define_split
965 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
966 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
967 (const_int 0)))
968 (set (match_operand:SI 0 "gpc_reg_operand" "")
969 (sign_extend:SI (match_dup 1)))]
970 "reload_completed"
971 [(set (match_dup 0)
972 (sign_extend:SI (match_dup 1)))
973 (set (match_dup 2)
974 (compare:CC (match_dup 0)
975 (const_int 0)))]
976 "")
978 ;; Fixed-point arithmetic insns.
980 ;; Discourage ai/addic because of carry but provide it in an alternative
981 ;; allowing register zero as source.
982 (define_expand "addsi3"
983 [(set (match_operand:SI 0 "gpc_reg_operand" "")
984 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
985 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
986 ""
987 "
988 {
989 if (GET_CODE (operands[2]) == CONST_INT
990 && ! add_operand (operands[2], SImode))
991 {
992 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
993 ? operands[0] : gen_reg_rtx (SImode));
995 HOST_WIDE_INT val = INTVAL (operands[2]);
996 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
997 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
999 /* The ordering here is important for the prolog expander.
1000 When space is allocated from the stack, adding 'low' first may
1001 produce a temporary deallocation (which would be bad). */
1002 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
1003 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1004 DONE;
1005 }
1006 }")
1008 (define_insn "*addsi3_internal1"
1009 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1010 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1011 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1012 ""
1013 "@
1014 {cax|add} %0,%1,%2
1015 {cal %0,%2(%1)|addi %0,%1,%2}
1016 {ai|addic} %0,%1,%2
1017 {cau|addis} %0,%1,%v2"
1018 [(set_attr "length" "4,4,4,4")])
1020 (define_insn "addsi3_high"
1021 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1022 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1023 (high:SI (match_operand 2 "" ""))))]
1024 "TARGET_MACHO && !TARGET_64BIT"
1025 "{cau|addis} %0,%1,ha16(%2)"
1026 [(set_attr "length" "4")])
1028 (define_insn "*addsi3_internal2"
1029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1030 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1031 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1032 (const_int 0)))
1033 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1034 "TARGET_32BIT"
1035 "@
1036 {cax.|add.} %3,%1,%2
1037 {ai.|addic.} %3,%1,%2
1038 #
1039 #"
1040 [(set_attr "type" "fast_compare,compare,compare,compare")
1041 (set_attr "length" "4,4,8,8")])
1043 (define_split
1044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1045 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1046 (match_operand:SI 2 "reg_or_short_operand" ""))
1047 (const_int 0)))
1048 (clobber (match_scratch:SI 3 ""))]
1049 "TARGET_32BIT && reload_completed"
1050 [(set (match_dup 3)
1051 (plus:SI (match_dup 1)
1052 (match_dup 2)))
1053 (set (match_dup 0)
1054 (compare:CC (match_dup 3)
1055 (const_int 0)))]
1056 "")
1058 (define_insn "*addsi3_internal3"
1059 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1060 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1061 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1062 (const_int 0)))
1063 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1064 (plus:SI (match_dup 1)
1065 (match_dup 2)))]
1066 "TARGET_32BIT"
1067 "@
1068 {cax.|add.} %0,%1,%2
1069 {ai.|addic.} %0,%1,%2
1070 #
1071 #"
1072 [(set_attr "type" "fast_compare,compare,compare,compare")
1073 (set_attr "length" "4,4,8,8")])
1075 (define_split
1076 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1077 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1078 (match_operand:SI 2 "reg_or_short_operand" ""))
1079 (const_int 0)))
1080 (set (match_operand:SI 0 "gpc_reg_operand" "")
1081 (plus:SI (match_dup 1) (match_dup 2)))]
1082 "TARGET_32BIT && reload_completed"
1083 [(set (match_dup 0)
1084 (plus:SI (match_dup 1)
1085 (match_dup 2)))
1086 (set (match_dup 3)
1087 (compare:CC (match_dup 0)
1088 (const_int 0)))]
1089 "")
1091 ;; Split an add that we can't do in one insn into two insns, each of which
1092 ;; does one 16-bit part. This is used by combine. Note that the low-order
1093 ;; add should be last in case the result gets used in an address.
1095 (define_split
1096 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1097 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1098 (match_operand:SI 2 "non_add_cint_operand" "")))]
1099 ""
1100 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1101 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1102 "
1103 {
1104 HOST_WIDE_INT val = INTVAL (operands[2]);
1105 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1106 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1108 operands[3] = GEN_INT (rest);
1109 operands[4] = GEN_INT (low);
1110 }")
1112 (define_insn "one_cmplsi2"
1113 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1114 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1115 ""
1116 "nor %0,%1,%1")
1118 (define_insn ""
1119 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1120 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1121 (const_int 0)))
1122 (clobber (match_scratch:SI 2 "=r,r"))]
1123 "TARGET_32BIT"
1124 "@
1125 nor. %2,%1,%1
1126 #"
1127 [(set_attr "type" "compare")
1128 (set_attr "length" "4,8")])
1130 (define_split
1131 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1132 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1133 (const_int 0)))
1134 (clobber (match_scratch:SI 2 ""))]
1135 "TARGET_32BIT && reload_completed"
1136 [(set (match_dup 2)
1137 (not:SI (match_dup 1)))
1138 (set (match_dup 0)
1139 (compare:CC (match_dup 2)
1140 (const_int 0)))]
1141 "")
1143 (define_insn ""
1144 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1145 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1146 (const_int 0)))
1147 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1148 (not:SI (match_dup 1)))]
1149 "TARGET_32BIT"
1150 "@
1151 nor. %0,%1,%1
1152 #"
1153 [(set_attr "type" "compare")
1154 (set_attr "length" "4,8")])
1156 (define_split
1157 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1158 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1159 (const_int 0)))
1160 (set (match_operand:SI 0 "gpc_reg_operand" "")
1161 (not:SI (match_dup 1)))]
1162 "TARGET_32BIT && reload_completed"
1163 [(set (match_dup 0)
1164 (not:SI (match_dup 1)))
1165 (set (match_dup 2)
1166 (compare:CC (match_dup 0)
1167 (const_int 0)))]
1168 "")
1170 (define_insn ""
1171 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1172 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1173 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1174 "! TARGET_POWERPC"
1175 "{sf%I1|subf%I1c} %0,%2,%1")
1177 (define_insn ""
1178 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1179 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1180 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1181 "TARGET_POWERPC"
1182 "@
1183 subf %0,%2,%1
1184 subfic %0,%2,%1")
1186 (define_insn ""
1187 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1188 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1189 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1190 (const_int 0)))
1191 (clobber (match_scratch:SI 3 "=r,r"))]
1192 "! TARGET_POWERPC"
1193 "@
1194 {sf.|subfc.} %3,%2,%1
1195 #"
1196 [(set_attr "type" "compare")
1197 (set_attr "length" "4,8")])
1199 (define_insn ""
1200 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1201 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1202 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1203 (const_int 0)))
1204 (clobber (match_scratch:SI 3 "=r,r"))]
1205 "TARGET_POWERPC && TARGET_32BIT"
1206 "@
1207 subf. %3,%2,%1
1208 #"
1209 [(set_attr "type" "fast_compare")
1210 (set_attr "length" "4,8")])
1212 (define_split
1213 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1214 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1215 (match_operand:SI 2 "gpc_reg_operand" ""))
1216 (const_int 0)))
1217 (clobber (match_scratch:SI 3 ""))]
1218 "TARGET_32BIT && reload_completed"
1219 [(set (match_dup 3)
1220 (minus:SI (match_dup 1)
1221 (match_dup 2)))
1222 (set (match_dup 0)
1223 (compare:CC (match_dup 3)
1224 (const_int 0)))]
1225 "")
1227 (define_insn ""
1228 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1229 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1230 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1231 (const_int 0)))
1232 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1233 (minus:SI (match_dup 1) (match_dup 2)))]
1234 "! TARGET_POWERPC"
1235 "@
1236 {sf.|subfc.} %0,%2,%1
1237 #"
1238 [(set_attr "type" "compare")
1239 (set_attr "length" "4,8")])
1241 (define_insn ""
1242 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1243 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1244 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1245 (const_int 0)))
1246 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1247 (minus:SI (match_dup 1)
1248 (match_dup 2)))]
1249 "TARGET_POWERPC && TARGET_32BIT"
1250 "@
1251 subf. %0,%2,%1
1252 #"
1253 [(set_attr "type" "fast_compare")
1254 (set_attr "length" "4,8")])
1256 (define_split
1257 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1258 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1259 (match_operand:SI 2 "gpc_reg_operand" ""))
1260 (const_int 0)))
1261 (set (match_operand:SI 0 "gpc_reg_operand" "")
1262 (minus:SI (match_dup 1)
1263 (match_dup 2)))]
1264 "TARGET_32BIT && reload_completed"
1265 [(set (match_dup 0)
1266 (minus:SI (match_dup 1)
1267 (match_dup 2)))
1268 (set (match_dup 3)
1269 (compare:CC (match_dup 0)
1270 (const_int 0)))]
1271 "")
1273 (define_expand "subsi3"
1274 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1275 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1276 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1277 ""
1278 "
1279 {
1280 if (GET_CODE (operands[2]) == CONST_INT)
1281 {
1282 emit_insn (gen_addsi3 (operands[0], operands[1],
1283 negate_rtx (SImode, operands[2])));
1284 DONE;
1285 }
1286 }")
1288 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1289 ;; instruction and some auxiliary computations. Then we just have a single
1290 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1291 ;; combine.
1293 (define_expand "sminsi3"
1294 [(set (match_dup 3)
1295 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1296 (match_operand:SI 2 "reg_or_short_operand" ""))
1297 (const_int 0)
1298 (minus:SI (match_dup 2) (match_dup 1))))
1299 (set (match_operand:SI 0 "gpc_reg_operand" "")
1300 (minus:SI (match_dup 2) (match_dup 3)))]
1301 "TARGET_POWER || TARGET_ISEL"
1302 "
1303 {
1304 if (TARGET_ISEL)
1305 {
1306 operands[2] = force_reg (SImode, operands[2]);
1307 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1308 DONE;
1309 }
1311 operands[3] = gen_reg_rtx (SImode);
1312 }")
1314 (define_split
1315 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1316 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1317 (match_operand:SI 2 "reg_or_short_operand" "")))
1318 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1319 "TARGET_POWER"
1320 [(set (match_dup 3)
1321 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1322 (const_int 0)
1323 (minus:SI (match_dup 2) (match_dup 1))))
1324 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1325 "")
1327 (define_expand "smaxsi3"
1328 [(set (match_dup 3)
1329 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1330 (match_operand:SI 2 "reg_or_short_operand" ""))
1331 (const_int 0)
1332 (minus:SI (match_dup 2) (match_dup 1))))
1333 (set (match_operand:SI 0 "gpc_reg_operand" "")
1334 (plus:SI (match_dup 3) (match_dup 1)))]
1335 "TARGET_POWER || TARGET_ISEL"
1336 "
1337 {
1338 if (TARGET_ISEL)
1339 {
1340 operands[2] = force_reg (SImode, operands[2]);
1341 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1342 DONE;
1343 }
1344 operands[3] = gen_reg_rtx (SImode);
1345 }")
1347 (define_split
1348 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1349 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1350 (match_operand:SI 2 "reg_or_short_operand" "")))
1351 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1352 "TARGET_POWER"
1353 [(set (match_dup 3)
1354 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1355 (const_int 0)
1356 (minus:SI (match_dup 2) (match_dup 1))))
1357 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1358 "")
1360 (define_expand "uminsi3"
1361 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1362 (match_dup 5)))
1363 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1364 (match_dup 5)))
1365 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1366 (const_int 0)
1367 (minus:SI (match_dup 4) (match_dup 3))))
1368 (set (match_operand:SI 0 "gpc_reg_operand" "")
1369 (minus:SI (match_dup 2) (match_dup 3)))]
1370 "TARGET_POWER || TARGET_ISEL"
1371 "
1372 {
1373 if (TARGET_ISEL)
1374 {
1375 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1376 DONE;
1377 }
1378 operands[3] = gen_reg_rtx (SImode);
1379 operands[4] = gen_reg_rtx (SImode);
1380 operands[5] = GEN_INT (-2147483647 - 1);
1381 }")
1383 (define_expand "umaxsi3"
1384 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1385 (match_dup 5)))
1386 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1387 (match_dup 5)))
1388 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1389 (const_int 0)
1390 (minus:SI (match_dup 4) (match_dup 3))))
1391 (set (match_operand:SI 0 "gpc_reg_operand" "")
1392 (plus:SI (match_dup 3) (match_dup 1)))]
1393 "TARGET_POWER || TARGET_ISEL"
1394 "
1395 {
1396 if (TARGET_ISEL)
1397 {
1398 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1399 DONE;
1400 }
1401 operands[3] = gen_reg_rtx (SImode);
1402 operands[4] = gen_reg_rtx (SImode);
1403 operands[5] = GEN_INT (-2147483647 - 1);
1404 }")
1406 (define_insn ""
1407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1408 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1409 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1410 (const_int 0)
1411 (minus:SI (match_dup 2) (match_dup 1))))]
1412 "TARGET_POWER"
1413 "doz%I2 %0,%1,%2")
1415 (define_insn ""
1416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1417 (compare:CC
1418 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1419 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1420 (const_int 0)
1421 (minus:SI (match_dup 2) (match_dup 1)))
1422 (const_int 0)))
1423 (clobber (match_scratch:SI 3 "=r,r"))]
1424 "TARGET_POWER"
1425 "@
1426 doz%I2. %3,%1,%2
1427 #"
1428 [(set_attr "type" "delayed_compare")
1429 (set_attr "length" "4,8")])
1431 (define_split
1432 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1433 (compare:CC
1434 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1435 (match_operand:SI 2 "reg_or_short_operand" ""))
1436 (const_int 0)
1437 (minus:SI (match_dup 2) (match_dup 1)))
1438 (const_int 0)))
1439 (clobber (match_scratch:SI 3 ""))]
1440 "TARGET_POWER && reload_completed"
1441 [(set (match_dup 3)
1442 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1443 (const_int 0)
1444 (minus:SI (match_dup 2) (match_dup 1))))
1445 (set (match_dup 0)
1446 (compare:CC (match_dup 3)
1447 (const_int 0)))]
1448 "")
1450 (define_insn ""
1451 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1452 (compare:CC
1453 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1454 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1455 (const_int 0)
1456 (minus:SI (match_dup 2) (match_dup 1)))
1457 (const_int 0)))
1458 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1459 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1460 (const_int 0)
1461 (minus:SI (match_dup 2) (match_dup 1))))]
1462 "TARGET_POWER"
1463 "@
1464 doz%I2. %0,%1,%2
1465 #"
1466 [(set_attr "type" "delayed_compare")
1467 (set_attr "length" "4,8")])
1469 (define_split
1470 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1471 (compare:CC
1472 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1473 (match_operand:SI 2 "reg_or_short_operand" ""))
1474 (const_int 0)
1475 (minus:SI (match_dup 2) (match_dup 1)))
1476 (const_int 0)))
1477 (set (match_operand:SI 0 "gpc_reg_operand" "")
1478 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1479 (const_int 0)
1480 (minus:SI (match_dup 2) (match_dup 1))))]
1481 "TARGET_POWER && reload_completed"
1482 [(set (match_dup 0)
1483 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1484 (const_int 0)
1485 (minus:SI (match_dup 2) (match_dup 1))))
1486 (set (match_dup 3)
1487 (compare:CC (match_dup 0)
1488 (const_int 0)))]
1489 "")
1491 ;; We don't need abs with condition code because such comparisons should
1492 ;; never be done.
1493 (define_expand "abssi2"
1494 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1495 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1496 ""
1497 "
1498 {
1499 if (TARGET_ISEL)
1500 {
1501 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1502 DONE;
1503 }
1504 else if (! TARGET_POWER)
1505 {
1506 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1507 DONE;
1508 }
1509 }")
1511 (define_insn "*abssi2_power"
1512 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1513 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1514 "TARGET_POWER"
1515 "abs %0,%1")
1517 (define_insn_and_split "abssi2_isel"
1518 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1519 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1520 (clobber (match_scratch:SI 2 "=&b"))
1521 (clobber (match_scratch:CC 3 "=y"))]
1522 "TARGET_ISEL"
1523 "#"
1524 "&& reload_completed"
1525 [(set (match_dup 2) (neg:SI (match_dup 1)))
1526 (set (match_dup 3)
1527 (compare:CC (match_dup 1)
1528 (const_int 0)))
1529 (set (match_dup 0)
1530 (if_then_else:SI (ge (match_dup 3)
1531 (const_int 0))
1532 (match_dup 1)
1533 (match_dup 2)))]
1534 "")
1536 (define_insn_and_split "abssi2_nopower"
1537 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1538 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1539 (clobber (match_scratch:SI 2 "=&r,&r"))]
1540 "! TARGET_POWER && ! TARGET_ISEL"
1541 "#"
1542 "&& reload_completed"
1543 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1544 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1545 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1546 "")
1548 (define_insn "*nabs_power"
1549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1550 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1551 "TARGET_POWER"
1552 "nabs %0,%1")
1554 (define_insn_and_split "*nabs_nopower"
1555 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1556 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1557 (clobber (match_scratch:SI 2 "=&r,&r"))]
1558 "! TARGET_POWER"
1559 "#"
1560 "&& reload_completed"
1561 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1562 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1563 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1564 "")
1566 (define_insn "negsi2"
1567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1568 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1569 ""
1570 "neg %0,%1")
1572 (define_insn ""
1573 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1574 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1575 (const_int 0)))
1576 (clobber (match_scratch:SI 2 "=r,r"))]
1577 "TARGET_32BIT"
1578 "@
1579 neg. %2,%1
1580 #"
1581 [(set_attr "type" "fast_compare")
1582 (set_attr "length" "4,8")])
1584 (define_split
1585 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1586 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1587 (const_int 0)))
1588 (clobber (match_scratch:SI 2 ""))]
1589 "TARGET_32BIT && reload_completed"
1590 [(set (match_dup 2)
1591 (neg:SI (match_dup 1)))
1592 (set (match_dup 0)
1593 (compare:CC (match_dup 2)
1594 (const_int 0)))]
1595 "")
1597 (define_insn ""
1598 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1599 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1600 (const_int 0)))
1601 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1602 (neg:SI (match_dup 1)))]
1603 "TARGET_32BIT"
1604 "@
1605 neg. %0,%1
1606 #"
1607 [(set_attr "type" "fast_compare")
1608 (set_attr "length" "4,8")])
1610 (define_split
1611 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1612 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1613 (const_int 0)))
1614 (set (match_operand:SI 0 "gpc_reg_operand" "")
1615 (neg:SI (match_dup 1)))]
1616 "TARGET_32BIT && reload_completed"
1617 [(set (match_dup 0)
1618 (neg:SI (match_dup 1)))
1619 (set (match_dup 2)
1620 (compare:CC (match_dup 0)
1621 (const_int 0)))]
1622 "")
1624 (define_insn "clzsi2"
1625 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1626 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1627 ""
1628 "{cntlz|cntlzw} %0,%1")
1630 (define_expand "ctzsi2"
1631 [(set (match_dup 2)
1632 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1633 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1634 (match_dup 2)))
1635 (clobber (scratch:CC))])
1636 (set (match_dup 4) (clz:SI (match_dup 3)))
1637 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1638 (minus:SI (const_int 31) (match_dup 4)))]
1639 ""
1640 {
1641 operands[2] = gen_reg_rtx (SImode);
1642 operands[3] = gen_reg_rtx (SImode);
1643 operands[4] = gen_reg_rtx (SImode);
1644 })
1646 (define_expand "ffssi2"
1647 [(set (match_dup 2)
1648 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1649 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1650 (match_dup 2)))
1651 (clobber (scratch:CC))])
1652 (set (match_dup 4) (clz:SI (match_dup 3)))
1653 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1654 (minus:SI (const_int 32) (match_dup 4)))]
1655 ""
1656 {
1657 operands[2] = gen_reg_rtx (SImode);
1658 operands[3] = gen_reg_rtx (SImode);
1659 operands[4] = gen_reg_rtx (SImode);
1660 })
1662 (define_expand "mulsi3"
1663 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1664 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1665 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1666 ""
1667 "
1668 {
1669 if (TARGET_POWER)
1670 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1671 else
1672 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1673 DONE;
1674 }")
1676 (define_insn "mulsi3_mq"
1677 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1678 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1679 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1680 (clobber (match_scratch:SI 3 "=q,q"))]
1681 "TARGET_POWER"
1682 "@
1683 {muls|mullw} %0,%1,%2
1684 {muli|mulli} %0,%1,%2"
1685 [(set (attr "type")
1686 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1687 (const_string "imul3")
1688 (match_operand:SI 2 "short_cint_operand" "")
1689 (const_string "imul2")]
1690 (const_string "imul")))])
1692 (define_insn "mulsi3_no_mq"
1693 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1694 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1695 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1696 "! TARGET_POWER"
1697 "@
1698 {muls|mullw} %0,%1,%2
1699 {muli|mulli} %0,%1,%2"
1700 [(set (attr "type")
1701 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1702 (const_string "imul3")
1703 (match_operand:SI 2 "short_cint_operand" "")
1704 (const_string "imul2")]
1705 (const_string "imul")))])
1707 (define_insn "*mulsi3_mq_internal1"
1708 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1709 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1710 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1711 (const_int 0)))
1712 (clobber (match_scratch:SI 3 "=r,r"))
1713 (clobber (match_scratch:SI 4 "=q,q"))]
1714 "TARGET_POWER"
1715 "@
1716 {muls.|mullw.} %3,%1,%2
1717 #"
1718 [(set_attr "type" "imul_compare")
1719 (set_attr "length" "4,8")])
1721 (define_split
1722 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1723 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1724 (match_operand:SI 2 "gpc_reg_operand" ""))
1725 (const_int 0)))
1726 (clobber (match_scratch:SI 3 ""))
1727 (clobber (match_scratch:SI 4 ""))]
1728 "TARGET_POWER && reload_completed"
1729 [(parallel [(set (match_dup 3)
1730 (mult:SI (match_dup 1) (match_dup 2)))
1731 (clobber (match_dup 4))])
1732 (set (match_dup 0)
1733 (compare:CC (match_dup 3)
1734 (const_int 0)))]
1735 "")
1737 (define_insn "*mulsi3_no_mq_internal1"
1738 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1739 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1740 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1741 (const_int 0)))
1742 (clobber (match_scratch:SI 3 "=r,r"))]
1743 "! TARGET_POWER"
1744 "@
1745 {muls.|mullw.} %3,%1,%2
1746 #"
1747 [(set_attr "type" "imul_compare")
1748 (set_attr "length" "4,8")])
1750 (define_split
1751 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1752 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1753 (match_operand:SI 2 "gpc_reg_operand" ""))
1754 (const_int 0)))
1755 (clobber (match_scratch:SI 3 ""))]
1756 "! TARGET_POWER && reload_completed"
1757 [(set (match_dup 3)
1758 (mult:SI (match_dup 1) (match_dup 2)))
1759 (set (match_dup 0)
1760 (compare:CC (match_dup 3)
1761 (const_int 0)))]
1762 "")
1764 (define_insn "*mulsi3_mq_internal2"
1765 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1766 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1767 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1768 (const_int 0)))
1769 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1770 (mult:SI (match_dup 1) (match_dup 2)))
1771 (clobber (match_scratch:SI 4 "=q,q"))]
1772 "TARGET_POWER"
1773 "@
1774 {muls.|mullw.} %0,%1,%2
1775 #"
1776 [(set_attr "type" "imul_compare")
1777 (set_attr "length" "4,8")])
1779 (define_split
1780 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1781 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1782 (match_operand:SI 2 "gpc_reg_operand" ""))
1783 (const_int 0)))
1784 (set (match_operand:SI 0 "gpc_reg_operand" "")
1785 (mult:SI (match_dup 1) (match_dup 2)))
1786 (clobber (match_scratch:SI 4 ""))]
1787 "TARGET_POWER && reload_completed"
1788 [(parallel [(set (match_dup 0)
1789 (mult:SI (match_dup 1) (match_dup 2)))
1790 (clobber (match_dup 4))])
1791 (set (match_dup 3)
1792 (compare:CC (match_dup 0)
1793 (const_int 0)))]
1794 "")
1796 (define_insn "*mulsi3_no_mq_internal2"
1797 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1798 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1799 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1800 (const_int 0)))
1801 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1802 (mult:SI (match_dup 1) (match_dup 2)))]
1803 "! TARGET_POWER"
1804 "@
1805 {muls.|mullw.} %0,%1,%2
1806 #"
1807 [(set_attr "type" "imul_compare")
1808 (set_attr "length" "4,8")])
1810 (define_split
1811 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1812 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1813 (match_operand:SI 2 "gpc_reg_operand" ""))
1814 (const_int 0)))
1815 (set (match_operand:SI 0 "gpc_reg_operand" "")
1816 (mult:SI (match_dup 1) (match_dup 2)))]
1817 "! TARGET_POWER && reload_completed"
1818 [(set (match_dup 0)
1819 (mult:SI (match_dup 1) (match_dup 2)))
1820 (set (match_dup 3)
1821 (compare:CC (match_dup 0)
1822 (const_int 0)))]
1823 "")
1825 ;; Operand 1 is divided by operand 2; quotient goes to operand
1826 ;; 0 and remainder to operand 3.
1827 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1829 (define_expand "divmodsi4"
1830 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1831 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1832 (match_operand:SI 2 "gpc_reg_operand" "")))
1833 (set (match_operand:SI 3 "register_operand" "")
1834 (mod:SI (match_dup 1) (match_dup 2)))])]
1835 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1836 "
1837 {
1838 if (! TARGET_POWER && ! TARGET_POWERPC)
1839 {
1840 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1841 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1842 emit_insn (gen_divss_call ());
1843 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1844 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1845 DONE;
1846 }
1847 }")
1849 (define_insn "*divmodsi4_internal"
1850 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1851 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1852 (match_operand:SI 2 "gpc_reg_operand" "r")))
1853 (set (match_operand:SI 3 "register_operand" "=q")
1854 (mod:SI (match_dup 1) (match_dup 2)))]
1855 "TARGET_POWER"
1856 "divs %0,%1,%2"
1857 [(set_attr "type" "idiv")])
1859 (define_expand "udivsi3"
1860 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1861 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1862 (match_operand:SI 2 "gpc_reg_operand" "")))]
1863 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1864 "
1865 {
1866 if (! TARGET_POWER && ! TARGET_POWERPC)
1867 {
1868 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1869 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1870 emit_insn (gen_quous_call ());
1871 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1872 DONE;
1873 }
1874 else if (TARGET_POWER)
1875 {
1876 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1877 DONE;
1878 }
1879 }")
1881 (define_insn "udivsi3_mq"
1882 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1883 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1884 (match_operand:SI 2 "gpc_reg_operand" "r")))
1885 (clobber (match_scratch:SI 3 "=q"))]
1886 "TARGET_POWERPC && TARGET_POWER"
1887 "divwu %0,%1,%2"
1888 [(set_attr "type" "idiv")])
1890 (define_insn "*udivsi3_no_mq"
1891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1892 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1893 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1894 "TARGET_POWERPC && ! TARGET_POWER"
1895 "divwu %0,%1,%2"
1896 [(set_attr "type" "idiv")])
1898 ;; For powers of two we can do srai/aze for divide and then adjust for
1899 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1900 ;; used; for PowerPC, force operands into register and do a normal divide;
1901 ;; for AIX common-mode, use quoss call on register operands.
1902 (define_expand "divsi3"
1903 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1904 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1905 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1906 ""
1907 "
1908 {
1909 if (GET_CODE (operands[2]) == CONST_INT
1910 && INTVAL (operands[2]) > 0
1911 && exact_log2 (INTVAL (operands[2])) >= 0)
1912 ;
1913 else if (TARGET_POWERPC)
1914 {
1915 operands[2] = force_reg (SImode, operands[2]);
1916 if (TARGET_POWER)
1917 {
1918 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1919 DONE;
1920 }
1921 }
1922 else if (TARGET_POWER)
1923 FAIL;
1924 else
1925 {
1926 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1927 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1928 emit_insn (gen_quoss_call ());
1929 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1930 DONE;
1931 }
1932 }")
1934 (define_insn "divsi3_mq"
1935 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1936 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1937 (match_operand:SI 2 "gpc_reg_operand" "r")))
1938 (clobber (match_scratch:SI 3 "=q"))]
1939 "TARGET_POWERPC && TARGET_POWER"
1940 "divw %0,%1,%2"
1941 [(set_attr "type" "idiv")])
1943 (define_insn "*divsi3_no_mq"
1944 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1945 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1946 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1947 "TARGET_POWERPC && ! TARGET_POWER"
1948 "divw %0,%1,%2"
1949 [(set_attr "type" "idiv")])
1951 (define_expand "modsi3"
1952 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1953 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1954 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1955 ""
1956 "
1957 {
1958 int i;
1959 rtx temp1;
1960 rtx temp2;
1962 if (GET_CODE (operands[2]) != CONST_INT
1963 || INTVAL (operands[2]) <= 0
1964 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1965 FAIL;
1967 temp1 = gen_reg_rtx (SImode);
1968 temp2 = gen_reg_rtx (SImode);
1970 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1971 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1972 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1973 DONE;
1974 }")
1976 (define_insn ""
1977 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1978 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1979 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1980 ""
1981 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1982 [(set_attr "type" "two")
1983 (set_attr "length" "8")])
1985 (define_insn ""
1986 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1987 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1988 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1989 (const_int 0)))
1990 (clobber (match_scratch:SI 3 "=r,r"))]
1991 ""
1992 "@
1993 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1994 #"
1995 [(set_attr "type" "compare")
1996 (set_attr "length" "8,12")])
1998 (define_split
1999 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2000 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2001 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2002 (const_int 0)))
2003 (clobber (match_scratch:SI 3 ""))]
2004 "reload_completed"
2005 [(set (match_dup 3)
2006 (div:SI (match_dup 1) (match_dup 2)))
2007 (set (match_dup 0)
2008 (compare:CC (match_dup 3)
2009 (const_int 0)))]
2010 "")
2012 (define_insn ""
2013 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2014 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2015 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2016 (const_int 0)))
2017 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2018 (div:SI (match_dup 1) (match_dup 2)))]
2019 ""
2020 "@
2021 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2022 #"
2023 [(set_attr "type" "compare")
2024 (set_attr "length" "8,12")])
2026 (define_split
2027 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2028 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2029 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2030 (const_int 0)))
2031 (set (match_operand:SI 0 "gpc_reg_operand" "")
2032 (div:SI (match_dup 1) (match_dup 2)))]
2033 "reload_completed"
2034 [(set (match_dup 0)
2035 (div:SI (match_dup 1) (match_dup 2)))
2036 (set (match_dup 3)
2037 (compare:CC (match_dup 0)
2038 (const_int 0)))]
2039 "")
2041 (define_insn ""
2042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2043 (udiv:SI
2044 (plus:DI (ashift:DI
2045 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2046 (const_int 32))
2047 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2048 (match_operand:SI 3 "gpc_reg_operand" "r")))
2049 (set (match_operand:SI 2 "register_operand" "=*q")
2050 (umod:SI
2051 (plus:DI (ashift:DI
2052 (zero_extend:DI (match_dup 1)) (const_int 32))
2053 (zero_extend:DI (match_dup 4)))
2054 (match_dup 3)))]
2055 "TARGET_POWER"
2056 "div %0,%1,%3"
2057 [(set_attr "type" "idiv")])
2059 ;; To do unsigned divide we handle the cases of the divisor looking like a
2060 ;; negative number. If it is a constant that is less than 2**31, we don't
2061 ;; have to worry about the branches. So make a few subroutines here.
2062 ;;
2063 ;; First comes the normal case.
2064 (define_expand "udivmodsi4_normal"
2065 [(set (match_dup 4) (const_int 0))
2066 (parallel [(set (match_operand:SI 0 "" "")
2067 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2068 (const_int 32))
2069 (zero_extend:DI (match_operand:SI 1 "" "")))
2070 (match_operand:SI 2 "" "")))
2071 (set (match_operand:SI 3 "" "")
2072 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2073 (const_int 32))
2074 (zero_extend:DI (match_dup 1)))
2075 (match_dup 2)))])]
2076 "TARGET_POWER"
2077 "
2078 { operands[4] = gen_reg_rtx (SImode); }")
2080 ;; This handles the branches.
2081 (define_expand "udivmodsi4_tests"
2082 [(set (match_operand:SI 0 "" "") (const_int 0))
2083 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2084 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2085 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2086 (label_ref (match_operand:SI 4 "" "")) (pc)))
2087 (set (match_dup 0) (const_int 1))
2088 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2089 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2090 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2091 (label_ref (match_dup 4)) (pc)))]
2092 "TARGET_POWER"
2093 "
2094 { operands[5] = gen_reg_rtx (CCUNSmode);
2095 operands[6] = gen_reg_rtx (CCmode);
2096 }")
2098 (define_expand "udivmodsi4"
2099 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2100 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2101 (match_operand:SI 2 "reg_or_cint_operand" "")))
2102 (set (match_operand:SI 3 "gpc_reg_operand" "")
2103 (umod:SI (match_dup 1) (match_dup 2)))])]
2104 ""
2105 "
2106 {
2107 rtx label = 0;
2109 if (! TARGET_POWER)
2110 {
2111 if (! TARGET_POWERPC)
2112 {
2113 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2114 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2115 emit_insn (gen_divus_call ());
2116 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2117 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2118 DONE;
2119 }
2120 else
2121 FAIL;
2122 }
2124 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2125 {
2126 operands[2] = force_reg (SImode, operands[2]);
2127 label = gen_label_rtx ();
2128 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2129 operands[3], label));
2130 }
2131 else
2132 operands[2] = force_reg (SImode, operands[2]);
2134 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2135 operands[3]));
2136 if (label)
2137 emit_label (label);
2139 DONE;
2140 }")
2142 ;; AIX architecture-independent common-mode multiply (DImode),
2143 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2144 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2145 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2146 ;; assumed unused if generating common-mode, so ignore.
2147 (define_insn "mulh_call"
2148 [(set (reg:SI 3)
2149 (truncate:SI
2150 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2151 (sign_extend:DI (reg:SI 4)))
2152 (const_int 32))))
2153 (clobber (match_scratch:SI 0 "=l"))]
2154 "! TARGET_POWER && ! TARGET_POWERPC"
2155 "bla __mulh"
2156 [(set_attr "type" "imul")])
2158 (define_insn "mull_call"
2159 [(set (reg:DI 3)
2160 (mult:DI (sign_extend:DI (reg:SI 3))
2161 (sign_extend:DI (reg:SI 4))))
2162 (clobber (match_scratch:SI 0 "=l"))
2163 (clobber (reg:SI 0))]
2164 "! TARGET_POWER && ! TARGET_POWERPC"
2165 "bla __mull"
2166 [(set_attr "type" "imul")])
2168 (define_insn "divss_call"
2169 [(set (reg:SI 3)
2170 (div:SI (reg:SI 3) (reg:SI 4)))
2171 (set (reg:SI 4)
2172 (mod:SI (reg:SI 3) (reg:SI 4)))
2173 (clobber (match_scratch:SI 0 "=l"))
2174 (clobber (reg:SI 0))]
2175 "! TARGET_POWER && ! TARGET_POWERPC"
2176 "bla __divss"
2177 [(set_attr "type" "idiv")])
2179 (define_insn "divus_call"
2180 [(set (reg:SI 3)
2181 (udiv:SI (reg:SI 3) (reg:SI 4)))
2182 (set (reg:SI 4)
2183 (umod:SI (reg:SI 3) (reg:SI 4)))
2184 (clobber (match_scratch:SI 0 "=l"))
2185 (clobber (reg:SI 0))
2186 (clobber (match_scratch:CC 1 "=x"))
2187 (clobber (reg:CC 69))]
2188 "! TARGET_POWER && ! TARGET_POWERPC"
2189 "bla __divus"
2190 [(set_attr "type" "idiv")])
2192 (define_insn "quoss_call"
2193 [(set (reg:SI 3)
2194 (div:SI (reg:SI 3) (reg:SI 4)))
2195 (clobber (match_scratch:SI 0 "=l"))]
2196 "! TARGET_POWER && ! TARGET_POWERPC"
2197 "bla __quoss"
2198 [(set_attr "type" "idiv")])
2200 (define_insn "quous_call"
2201 [(set (reg:SI 3)
2202 (udiv:SI (reg:SI 3) (reg:SI 4)))
2203 (clobber (match_scratch:SI 0 "=l"))
2204 (clobber (reg:SI 0))
2205 (clobber (match_scratch:CC 1 "=x"))
2206 (clobber (reg:CC 69))]
2207 "! TARGET_POWER && ! TARGET_POWERPC"
2208 "bla __quous"
2209 [(set_attr "type" "idiv")])
2210 \f
2211 ;; Logical instructions
2212 ;; The logical instructions are mostly combined by using match_operator,
2213 ;; but the plain AND insns are somewhat different because there is no
2214 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2215 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2217 (define_insn "andsi3"
2218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2219 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2220 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2221 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2222 ""
2223 "@
2224 and %0,%1,%2
2225 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2226 {andil.|andi.} %0,%1,%b2
2227 {andiu.|andis.} %0,%1,%u2"
2228 [(set_attr "type" "*,*,compare,compare")])
2230 ;; Note to set cr's other than cr0 we do the and immediate and then
2231 ;; the test again -- this avoids a mfcr which on the higher end
2232 ;; machines causes an execution serialization
2234 (define_insn "*andsi3_internal2"
2235 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2236 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2237 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2238 (const_int 0)))
2239 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2240 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2241 "TARGET_32BIT"
2242 "@
2243 and. %3,%1,%2
2244 {andil.|andi.} %3,%1,%b2
2245 {andiu.|andis.} %3,%1,%u2
2246 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2247 #
2248 #
2249 #
2250 #"
2251 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2252 (set_attr "length" "4,4,4,4,8,8,8,8")])
2254 (define_insn "*andsi3_internal3"
2255 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2256 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2257 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2258 (const_int 0)))
2259 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2260 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2261 "TARGET_64BIT"
2262 "@
2263 #
2264 {andil.|andi.} %3,%1,%b2
2265 {andiu.|andis.} %3,%1,%u2
2266 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2267 #
2268 #
2269 #
2270 #"
2271 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2272 (set_attr "length" "8,4,4,4,8,8,8,8")])
2274 (define_split
2275 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2276 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2277 (match_operand:SI 2 "and_operand" ""))
2278 (const_int 0)))
2279 (clobber (match_scratch:SI 3 ""))
2280 (clobber (match_scratch:CC 4 ""))]
2281 "reload_completed"
2282 [(parallel [(set (match_dup 3)
2283 (and:SI (match_dup 1)
2284 (match_dup 2)))
2285 (clobber (match_dup 4))])
2286 (set (match_dup 0)
2287 (compare:CC (match_dup 3)
2288 (const_int 0)))]
2289 "")
2291 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2292 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2294 (define_split
2295 [(set (match_operand:CC 0 "cc_reg_operand" "")
2296 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2297 (match_operand:SI 2 "gpc_reg_operand" ""))
2298 (const_int 0)))
2299 (clobber (match_scratch:SI 3 ""))
2300 (clobber (match_scratch:CC 4 ""))]
2301 "TARGET_POWERPC64 && reload_completed"
2302 [(parallel [(set (match_dup 3)
2303 (and:SI (match_dup 1)
2304 (match_dup 2)))
2305 (clobber (match_dup 4))])
2306 (set (match_dup 0)
2307 (compare:CC (match_dup 3)
2308 (const_int 0)))]
2309 "")
2311 (define_insn "*andsi3_internal4"
2312 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2313 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2314 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2315 (const_int 0)))
2316 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2317 (and:SI (match_dup 1)
2318 (match_dup 2)))
2319 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2320 "TARGET_32BIT"
2321 "@
2322 and. %0,%1,%2
2323 {andil.|andi.} %0,%1,%b2
2324 {andiu.|andis.} %0,%1,%u2
2325 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2326 #
2327 #
2328 #
2329 #"
2330 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2331 (set_attr "length" "4,4,4,4,8,8,8,8")])
2333 (define_insn "*andsi3_internal5"
2334 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2335 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2336 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2337 (const_int 0)))
2338 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2339 (and:SI (match_dup 1)
2340 (match_dup 2)))
2341 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2342 "TARGET_64BIT"
2343 "@
2344 #
2345 {andil.|andi.} %0,%1,%b2
2346 {andiu.|andis.} %0,%1,%u2
2347 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2348 #
2349 #
2350 #
2351 #"
2352 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2353 (set_attr "length" "8,4,4,4,8,8,8,8")])
2355 (define_split
2356 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2357 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2358 (match_operand:SI 2 "and_operand" ""))
2359 (const_int 0)))
2360 (set (match_operand:SI 0 "gpc_reg_operand" "")
2361 (and:SI (match_dup 1)
2362 (match_dup 2)))
2363 (clobber (match_scratch:CC 4 ""))]
2364 "reload_completed"
2365 [(parallel [(set (match_dup 0)
2366 (and:SI (match_dup 1)
2367 (match_dup 2)))
2368 (clobber (match_dup 4))])
2369 (set (match_dup 3)
2370 (compare:CC (match_dup 0)
2371 (const_int 0)))]
2372 "")
2374 (define_split
2375 [(set (match_operand:CC 3 "cc_reg_operand" "")
2376 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2377 (match_operand:SI 2 "gpc_reg_operand" ""))
2378 (const_int 0)))
2379 (set (match_operand:SI 0 "gpc_reg_operand" "")
2380 (and:SI (match_dup 1)
2381 (match_dup 2)))
2382 (clobber (match_scratch:CC 4 ""))]
2383 "TARGET_POWERPC64 && reload_completed"
2384 [(parallel [(set (match_dup 0)
2385 (and:SI (match_dup 1)
2386 (match_dup 2)))
2387 (clobber (match_dup 4))])
2388 (set (match_dup 3)
2389 (compare:CC (match_dup 0)
2390 (const_int 0)))]
2391 "")
2393 ;; Handle the PowerPC64 rlwinm corner case
2395 (define_insn_and_split "*andsi3_internal6"
2396 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2397 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2398 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2399 "TARGET_POWERPC64"
2400 "#"
2401 "TARGET_POWERPC64"
2402 [(set (match_dup 0)
2403 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2404 (match_dup 4)))
2405 (set (match_dup 0)
2406 (rotate:SI (match_dup 0) (match_dup 5)))]
2407 "
2408 {
2409 int mb = extract_MB (operands[2]);
2410 int me = extract_ME (operands[2]);
2411 operands[3] = GEN_INT (me + 1);
2412 operands[5] = GEN_INT (32 - (me + 1));
2413 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2414 }"
2415 [(set_attr "length" "8")])
2417 (define_expand "iorsi3"
2418 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2419 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2420 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2421 ""
2422 "
2423 {
2424 if (GET_CODE (operands[2]) == CONST_INT
2425 && ! logical_operand (operands[2], SImode))
2426 {
2427 HOST_WIDE_INT value = INTVAL (operands[2]);
2428 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2429 ? operands[0] : gen_reg_rtx (SImode));
2431 emit_insn (gen_iorsi3 (tmp, operands[1],
2432 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2433 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2434 DONE;
2435 }
2436 }")
2438 (define_expand "xorsi3"
2439 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2440 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2441 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2442 ""
2443 "
2444 {
2445 if (GET_CODE (operands[2]) == CONST_INT
2446 && ! logical_operand (operands[2], SImode))
2447 {
2448 HOST_WIDE_INT value = INTVAL (operands[2]);
2449 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2450 ? operands[0] : gen_reg_rtx (SImode));
2452 emit_insn (gen_xorsi3 (tmp, operands[1],
2453 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2454 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2455 DONE;
2456 }
2457 }")
2459 (define_insn "*boolsi3_internal1"
2460 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2461 (match_operator:SI 3 "boolean_or_operator"
2462 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2463 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2464 ""
2465 "@
2466 %q3 %0,%1,%2
2467 {%q3il|%q3i} %0,%1,%b2
2468 {%q3iu|%q3is} %0,%1,%u2")
2470 (define_insn "*boolsi3_internal2"
2471 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2472 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2473 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2474 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2475 (const_int 0)))
2476 (clobber (match_scratch:SI 3 "=r,r"))]
2477 "TARGET_32BIT"
2478 "@
2479 %q4. %3,%1,%2
2480 #"
2481 [(set_attr "type" "compare")
2482 (set_attr "length" "4,8")])
2484 (define_split
2485 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2486 (compare:CC (match_operator:SI 4 "boolean_operator"
2487 [(match_operand:SI 1 "gpc_reg_operand" "")
2488 (match_operand:SI 2 "gpc_reg_operand" "")])
2489 (const_int 0)))
2490 (clobber (match_scratch:SI 3 ""))]
2491 "TARGET_32BIT && reload_completed"
2492 [(set (match_dup 3) (match_dup 4))
2493 (set (match_dup 0)
2494 (compare:CC (match_dup 3)
2495 (const_int 0)))]
2496 "")
2498 (define_insn "*boolsi3_internal3"
2499 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2500 (compare:CC (match_operator:SI 4 "boolean_operator"
2501 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2502 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2503 (const_int 0)))
2504 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2505 (match_dup 4))]
2506 "TARGET_32BIT"
2507 "@
2508 %q4. %0,%1,%2
2509 #"
2510 [(set_attr "type" "compare")
2511 (set_attr "length" "4,8")])
2513 (define_split
2514 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2515 (compare:CC (match_operator:SI 4 "boolean_operator"
2516 [(match_operand:SI 1 "gpc_reg_operand" "")
2517 (match_operand:SI 2 "gpc_reg_operand" "")])
2518 (const_int 0)))
2519 (set (match_operand:SI 0 "gpc_reg_operand" "")
2520 (match_dup 4))]
2521 "TARGET_32BIT && reload_completed"
2522 [(set (match_dup 0) (match_dup 4))
2523 (set (match_dup 3)
2524 (compare:CC (match_dup 0)
2525 (const_int 0)))]
2526 "")
2528 ;; Split a logical operation that we can't do in one insn into two insns,
2529 ;; each of which does one 16-bit part. This is used by combine.
2531 (define_split
2532 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2533 (match_operator:SI 3 "boolean_or_operator"
2534 [(match_operand:SI 1 "gpc_reg_operand" "")
2535 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2536 ""
2537 [(set (match_dup 0) (match_dup 4))
2538 (set (match_dup 0) (match_dup 5))]
2539 "
2540 {
2541 rtx i;
2542 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2543 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2544 operands[1], i);
2545 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2546 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2547 operands[0], i);
2548 }")
2550 (define_insn "*boolcsi3_internal1"
2551 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2552 (match_operator:SI 3 "boolean_operator"
2553 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2554 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2555 ""
2556 "%q3 %0,%2,%1")
2558 (define_insn "*boolcsi3_internal2"
2559 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2560 (compare:CC (match_operator:SI 4 "boolean_operator"
2561 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2562 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2563 (const_int 0)))
2564 (clobber (match_scratch:SI 3 "=r,r"))]
2565 "TARGET_32BIT"
2566 "@
2567 %q4. %3,%2,%1
2568 #"
2569 [(set_attr "type" "compare")
2570 (set_attr "length" "4,8")])
2572 (define_split
2573 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2574 (compare:CC (match_operator:SI 4 "boolean_operator"
2575 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2576 (match_operand:SI 2 "gpc_reg_operand" "")])
2577 (const_int 0)))
2578 (clobber (match_scratch:SI 3 ""))]
2579 "TARGET_32BIT && reload_completed"
2580 [(set (match_dup 3) (match_dup 4))
2581 (set (match_dup 0)
2582 (compare:CC (match_dup 3)
2583 (const_int 0)))]
2584 "")
2586 (define_insn "*boolcsi3_internal3"
2587 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2588 (compare:CC (match_operator:SI 4 "boolean_operator"
2589 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2590 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2591 (const_int 0)))
2592 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2593 (match_dup 4))]
2594 "TARGET_32BIT"
2595 "@
2596 %q4. %0,%2,%1
2597 #"
2598 [(set_attr "type" "compare")
2599 (set_attr "length" "4,8")])
2601 (define_split
2602 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2603 (compare:CC (match_operator:SI 4 "boolean_operator"
2604 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2605 (match_operand:SI 2 "gpc_reg_operand" "")])
2606 (const_int 0)))
2607 (set (match_operand:SI 0 "gpc_reg_operand" "")
2608 (match_dup 4))]
2609 "TARGET_32BIT && reload_completed"
2610 [(set (match_dup 0) (match_dup 4))
2611 (set (match_dup 3)
2612 (compare:CC (match_dup 0)
2613 (const_int 0)))]
2614 "")
2616 (define_insn "*boolccsi3_internal1"
2617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2618 (match_operator:SI 3 "boolean_operator"
2619 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2620 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2621 ""
2622 "%q3 %0,%1,%2")
2624 (define_insn "*boolccsi3_internal2"
2625 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2626 (compare:CC (match_operator:SI 4 "boolean_operator"
2627 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2628 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2629 (const_int 0)))
2630 (clobber (match_scratch:SI 3 "=r,r"))]
2631 "TARGET_32BIT"
2632 "@
2633 %q4. %3,%1,%2
2634 #"
2635 [(set_attr "type" "compare")
2636 (set_attr "length" "4,8")])
2638 (define_split
2639 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2640 (compare:CC (match_operator:SI 4 "boolean_operator"
2641 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2642 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2643 (const_int 0)))
2644 (clobber (match_scratch:SI 3 ""))]
2645 "TARGET_32BIT && reload_completed"
2646 [(set (match_dup 3) (match_dup 4))
2647 (set (match_dup 0)
2648 (compare:CC (match_dup 3)
2649 (const_int 0)))]
2650 "")
2652 (define_insn "*boolccsi3_internal3"
2653 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2654 (compare:CC (match_operator:SI 4 "boolean_operator"
2655 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2656 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2657 (const_int 0)))
2658 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2659 (match_dup 4))]
2660 "TARGET_32BIT"
2661 "@
2662 %q4. %0,%1,%2
2663 #"
2664 [(set_attr "type" "compare")
2665 (set_attr "length" "4,8")])
2667 (define_split
2668 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2669 (compare:CC (match_operator:SI 4 "boolean_operator"
2670 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2671 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2672 (const_int 0)))
2673 (set (match_operand:SI 0 "gpc_reg_operand" "")
2674 (match_dup 4))]
2675 "TARGET_32BIT && reload_completed"
2676 [(set (match_dup 0) (match_dup 4))
2677 (set (match_dup 3)
2678 (compare:CC (match_dup 0)
2679 (const_int 0)))]
2680 "")
2682 ;; maskir insn. We need four forms because things might be in arbitrary
2683 ;; orders. Don't define forms that only set CR fields because these
2684 ;; would modify an input register.
2686 (define_insn "*maskir_internal1"
2687 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2688 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2689 (match_operand:SI 1 "gpc_reg_operand" "0"))
2690 (and:SI (match_dup 2)
2691 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2692 "TARGET_POWER"
2693 "maskir %0,%3,%2")
2695 (define_insn "*maskir_internal2"
2696 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2697 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2698 (match_operand:SI 1 "gpc_reg_operand" "0"))
2699 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2700 (match_dup 2))))]
2701 "TARGET_POWER"
2702 "maskir %0,%3,%2")
2704 (define_insn "*maskir_internal3"
2705 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2706 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2707 (match_operand:SI 3 "gpc_reg_operand" "r"))
2708 (and:SI (not:SI (match_dup 2))
2709 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2710 "TARGET_POWER"
2711 "maskir %0,%3,%2")
2713 (define_insn "*maskir_internal4"
2714 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2715 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2716 (match_operand:SI 2 "gpc_reg_operand" "r"))
2717 (and:SI (not:SI (match_dup 2))
2718 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2719 "TARGET_POWER"
2720 "maskir %0,%3,%2")
2722 (define_insn "*maskir_internal5"
2723 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2724 (compare:CC
2725 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2726 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2727 (and:SI (match_dup 2)
2728 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2729 (const_int 0)))
2730 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2731 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2732 (and:SI (match_dup 2) (match_dup 3))))]
2733 "TARGET_POWER"
2734 "@
2735 maskir. %0,%3,%2
2736 #"
2737 [(set_attr "type" "compare")
2738 (set_attr "length" "4,8")])
2740 (define_split
2741 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2742 (compare:CC
2743 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2744 (match_operand:SI 1 "gpc_reg_operand" ""))
2745 (and:SI (match_dup 2)
2746 (match_operand:SI 3 "gpc_reg_operand" "")))
2747 (const_int 0)))
2748 (set (match_operand:SI 0 "gpc_reg_operand" "")
2749 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2750 (and:SI (match_dup 2) (match_dup 3))))]
2751 "TARGET_POWER && reload_completed"
2752 [(set (match_dup 0)
2753 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2754 (and:SI (match_dup 2) (match_dup 3))))
2755 (set (match_dup 4)
2756 (compare:CC (match_dup 0)
2757 (const_int 0)))]
2758 "")
2760 (define_insn "*maskir_internal6"
2761 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2762 (compare:CC
2763 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2764 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2765 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2766 (match_dup 2)))
2767 (const_int 0)))
2768 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2769 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2770 (and:SI (match_dup 3) (match_dup 2))))]
2771 "TARGET_POWER"
2772 "@
2773 maskir. %0,%3,%2
2774 #"
2775 [(set_attr "type" "compare")
2776 (set_attr "length" "4,8")])
2778 (define_split
2779 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2780 (compare:CC
2781 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2782 (match_operand:SI 1 "gpc_reg_operand" ""))
2783 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2784 (match_dup 2)))
2785 (const_int 0)))
2786 (set (match_operand:SI 0 "gpc_reg_operand" "")
2787 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2788 (and:SI (match_dup 3) (match_dup 2))))]
2789 "TARGET_POWER && reload_completed"
2790 [(set (match_dup 0)
2791 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2792 (and:SI (match_dup 3) (match_dup 2))))
2793 (set (match_dup 4)
2794 (compare:CC (match_dup 0)
2795 (const_int 0)))]
2796 "")
2798 (define_insn "*maskir_internal7"
2799 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2800 (compare:CC
2801 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2802 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2803 (and:SI (not:SI (match_dup 2))
2804 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2805 (const_int 0)))
2806 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2807 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2808 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2809 "TARGET_POWER"
2810 "@
2811 maskir. %0,%3,%2
2812 #"
2813 [(set_attr "type" "compare")
2814 (set_attr "length" "4,8")])
2816 (define_split
2817 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2818 (compare:CC
2819 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2820 (match_operand:SI 3 "gpc_reg_operand" ""))
2821 (and:SI (not:SI (match_dup 2))
2822 (match_operand:SI 1 "gpc_reg_operand" "")))
2823 (const_int 0)))
2824 (set (match_operand:SI 0 "gpc_reg_operand" "")
2825 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2826 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2827 "TARGET_POWER && reload_completed"
2828 [(set (match_dup 0)
2829 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2830 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2831 (set (match_dup 4)
2832 (compare:CC (match_dup 0)
2833 (const_int 0)))]
2834 "")
2836 (define_insn "*maskir_internal8"
2837 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2838 (compare:CC
2839 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2840 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2841 (and:SI (not:SI (match_dup 2))
2842 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2843 (const_int 0)))
2844 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2845 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2846 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2847 "TARGET_POWER"
2848 "@
2849 maskir. %0,%3,%2
2850 #"
2851 [(set_attr "type" "compare")
2852 (set_attr "length" "4,8")])
2854 (define_split
2855 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2856 (compare:CC
2857 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2858 (match_operand:SI 2 "gpc_reg_operand" ""))
2859 (and:SI (not:SI (match_dup 2))
2860 (match_operand:SI 1 "gpc_reg_operand" "")))
2861 (const_int 0)))
2862 (set (match_operand:SI 0 "gpc_reg_operand" "")
2863 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2864 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2865 "TARGET_POWER && reload_completed"
2866 [(set (match_dup 0)
2867 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2868 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2869 (set (match_dup 4)
2870 (compare:CC (match_dup 0)
2871 (const_int 0)))]
2872 "")
2873 \f
2874 ;; Rotate and shift insns, in all their variants. These support shifts,
2875 ;; field inserts and extracts, and various combinations thereof.
2876 (define_expand "insv"
2877 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2878 (match_operand:SI 1 "const_int_operand" "")
2879 (match_operand:SI 2 "const_int_operand" ""))
2880 (match_operand 3 "gpc_reg_operand" ""))]
2881 ""
2882 "
2883 {
2884 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2885 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2886 compiler if the address of the structure is taken later. */
2887 if (GET_CODE (operands[0]) == SUBREG
2888 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2889 FAIL;
2891 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2892 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2893 else
2894 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2895 DONE;
2896 }")
2898 (define_insn "insvsi"
2899 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2900 (match_operand:SI 1 "const_int_operand" "i")
2901 (match_operand:SI 2 "const_int_operand" "i"))
2902 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2903 ""
2904 "*
2905 {
2906 int start = INTVAL (operands[2]) & 31;
2907 int size = INTVAL (operands[1]) & 31;
2909 operands[4] = GEN_INT (32 - start - size);
2910 operands[1] = GEN_INT (start + size - 1);
2911 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2912 }"
2913 [(set_attr "type" "insert_word")])
2915 (define_insn "*insvsi_internal1"
2916 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2917 (match_operand:SI 1 "const_int_operand" "i")
2918 (match_operand:SI 2 "const_int_operand" "i"))
2919 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2920 (match_operand:SI 4 "const_int_operand" "i")))]
2921 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2922 "*
2923 {
2924 int shift = INTVAL (operands[4]) & 31;
2925 int start = INTVAL (operands[2]) & 31;
2926 int size = INTVAL (operands[1]) & 31;
2928 operands[4] = GEN_INT (shift - start - size);
2929 operands[1] = GEN_INT (start + size - 1);
2930 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2931 }"
2932 [(set_attr "type" "insert_word")])
2934 (define_insn "*insvsi_internal2"
2935 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2936 (match_operand:SI 1 "const_int_operand" "i")
2937 (match_operand:SI 2 "const_int_operand" "i"))
2938 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2939 (match_operand:SI 4 "const_int_operand" "i")))]
2940 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2941 "*
2942 {
2943 int shift = INTVAL (operands[4]) & 31;
2944 int start = INTVAL (operands[2]) & 31;
2945 int size = INTVAL (operands[1]) & 31;
2947 operands[4] = GEN_INT (32 - shift - start - size);
2948 operands[1] = GEN_INT (start + size - 1);
2949 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2950 }"
2951 [(set_attr "type" "insert_word")])
2953 (define_insn "*insvsi_internal3"
2954 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2955 (match_operand:SI 1 "const_int_operand" "i")
2956 (match_operand:SI 2 "const_int_operand" "i"))
2957 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2958 (match_operand:SI 4 "const_int_operand" "i")))]
2959 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2960 "*
2961 {
2962 int shift = INTVAL (operands[4]) & 31;
2963 int start = INTVAL (operands[2]) & 31;
2964 int size = INTVAL (operands[1]) & 31;
2966 operands[4] = GEN_INT (32 - shift - start - size);
2967 operands[1] = GEN_INT (start + size - 1);
2968 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2969 }"
2970 [(set_attr "type" "insert_word")])
2972 (define_insn "*insvsi_internal4"
2973 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2974 (match_operand:SI 1 "const_int_operand" "i")
2975 (match_operand:SI 2 "const_int_operand" "i"))
2976 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2977 (match_operand:SI 4 "const_int_operand" "i")
2978 (match_operand:SI 5 "const_int_operand" "i")))]
2979 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2980 "*
2981 {
2982 int extract_start = INTVAL (operands[5]) & 31;
2983 int extract_size = INTVAL (operands[4]) & 31;
2984 int insert_start = INTVAL (operands[2]) & 31;
2985 int insert_size = INTVAL (operands[1]) & 31;
2987 /* Align extract field with insert field */
2988 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
2989 operands[1] = GEN_INT (insert_start + insert_size - 1);
2990 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2991 }"
2992 [(set_attr "type" "insert_word")])
2994 ;; combine patterns for rlwimi
2995 (define_insn "*insvsi_internal5"
2996 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2997 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2998 (match_operand:SI 1 "mask_operand" "i"))
2999 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3000 (match_operand:SI 2 "const_int_operand" "i"))
3001 (match_operand:SI 5 "mask_operand" "i"))))]
3002 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3003 "*
3004 {
3005 int me = extract_ME(operands[5]);
3006 int mb = extract_MB(operands[5]);
3007 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3008 operands[2] = GEN_INT(mb);
3009 operands[1] = GEN_INT(me);
3010 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3011 }"
3012 [(set_attr "type" "insert_word")])
3014 (define_insn "*insvsi_internal6"
3015 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3016 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3017 (match_operand:SI 2 "const_int_operand" "i"))
3018 (match_operand:SI 5 "mask_operand" "i"))
3019 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3020 (match_operand:SI 1 "mask_operand" "i"))))]
3021 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3022 "*
3023 {
3024 int me = extract_ME(operands[5]);
3025 int mb = extract_MB(operands[5]);
3026 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3027 operands[2] = GEN_INT(mb);
3028 operands[1] = GEN_INT(me);
3029 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3030 }"
3031 [(set_attr "type" "insert_word")])
3033 (define_insn "insvdi"
3034 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3035 (match_operand:SI 1 "const_int_operand" "i")
3036 (match_operand:SI 2 "const_int_operand" "i"))
3037 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3038 "TARGET_POWERPC64"
3039 "*
3040 {
3041 int start = INTVAL (operands[2]) & 63;
3042 int size = INTVAL (operands[1]) & 63;
3044 operands[1] = GEN_INT (64 - start - size);
3045 return \"rldimi %0,%3,%H1,%H2\";
3046 }")
3048 (define_insn "*insvdi_internal2"
3049 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3050 (match_operand:SI 1 "const_int_operand" "i")
3051 (match_operand:SI 2 "const_int_operand" "i"))
3052 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3053 (match_operand:SI 4 "const_int_operand" "i")))]
3054 "TARGET_POWERPC64
3055 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3056 "*
3057 {
3058 int shift = INTVAL (operands[4]) & 63;
3059 int start = (INTVAL (operands[2]) & 63) - 32;
3060 int size = INTVAL (operands[1]) & 63;
3062 operands[4] = GEN_INT (64 - shift - start - size);
3063 operands[2] = GEN_INT (start);
3064 operands[1] = GEN_INT (start + size - 1);
3065 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3066 }")
3068 (define_insn "*insvdi_internal3"
3069 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3070 (match_operand:SI 1 "const_int_operand" "i")
3071 (match_operand:SI 2 "const_int_operand" "i"))
3072 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3073 (match_operand:SI 4 "const_int_operand" "i")))]
3074 "TARGET_POWERPC64
3075 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3076 "*
3077 {
3078 int shift = INTVAL (operands[4]) & 63;
3079 int start = (INTVAL (operands[2]) & 63) - 32;
3080 int size = INTVAL (operands[1]) & 63;
3082 operands[4] = GEN_INT (64 - shift - start - size);
3083 operands[2] = GEN_INT (start);
3084 operands[1] = GEN_INT (start + size - 1);
3085 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3086 }")
3088 (define_expand "extzv"
3089 [(set (match_operand 0 "gpc_reg_operand" "")
3090 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3091 (match_operand:SI 2 "const_int_operand" "")
3092 (match_operand:SI 3 "const_int_operand" "")))]
3093 ""
3094 "
3095 {
3096 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3097 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3098 compiler if the address of the structure is taken later. */
3099 if (GET_CODE (operands[0]) == SUBREG
3100 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3101 FAIL;
3103 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3104 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3105 else
3106 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3107 DONE;
3108 }")
3110 (define_insn "extzvsi"
3111 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3112 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3113 (match_operand:SI 2 "const_int_operand" "i")
3114 (match_operand:SI 3 "const_int_operand" "i")))]
3115 ""
3116 "*
3117 {
3118 int start = INTVAL (operands[3]) & 31;
3119 int size = INTVAL (operands[2]) & 31;
3121 if (start + size >= 32)
3122 operands[3] = const0_rtx;
3123 else
3124 operands[3] = GEN_INT (start + size);
3125 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3126 }")
3128 (define_insn "*extzvsi_internal1"
3129 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3130 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3131 (match_operand:SI 2 "const_int_operand" "i,i")
3132 (match_operand:SI 3 "const_int_operand" "i,i"))
3133 (const_int 0)))
3134 (clobber (match_scratch:SI 4 "=r,r"))]
3135 ""
3136 "*
3137 {
3138 int start = INTVAL (operands[3]) & 31;
3139 int size = INTVAL (operands[2]) & 31;
3141 /* Force split for non-cc0 compare. */
3142 if (which_alternative == 1)
3143 return \"#\";
3145 /* If the bit-field being tested fits in the upper or lower half of a
3146 word, it is possible to use andiu. or andil. to test it. This is
3147 useful because the condition register set-use delay is smaller for
3148 andi[ul]. than for rlinm. This doesn't work when the starting bit
3149 position is 0 because the LT and GT bits may be set wrong. */
3151 if ((start > 0 && start + size <= 16) || start >= 16)
3152 {
3153 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3154 - (1 << (16 - (start & 15) - size))));
3155 if (start < 16)
3156 return \"{andiu.|andis.} %4,%1,%3\";
3157 else
3158 return \"{andil.|andi.} %4,%1,%3\";
3159 }
3161 if (start + size >= 32)
3162 operands[3] = const0_rtx;
3163 else
3164 operands[3] = GEN_INT (start + size);
3165 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3166 }"
3167 [(set_attr "type" "compare")
3168 (set_attr "length" "4,8")])
3170 (define_split
3171 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3172 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3173 (match_operand:SI 2 "const_int_operand" "")
3174 (match_operand:SI 3 "const_int_operand" ""))
3175 (const_int 0)))
3176 (clobber (match_scratch:SI 4 ""))]
3177 "reload_completed"
3178 [(set (match_dup 4)
3179 (zero_extract:SI (match_dup 1) (match_dup 2)
3180 (match_dup 3)))
3181 (set (match_dup 0)
3182 (compare:CC (match_dup 4)
3183 (const_int 0)))]
3184 "")
3186 (define_insn "*extzvsi_internal2"
3187 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3188 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3189 (match_operand:SI 2 "const_int_operand" "i,i")
3190 (match_operand:SI 3 "const_int_operand" "i,i"))
3191 (const_int 0)))
3192 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3193 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3194 ""
3195 "*
3196 {
3197 int start = INTVAL (operands[3]) & 31;
3198 int size = INTVAL (operands[2]) & 31;
3200 /* Force split for non-cc0 compare. */
3201 if (which_alternative == 1)
3202 return \"#\";
3204 /* Since we are using the output value, we can't ignore any need for
3205 a shift. The bit-field must end at the LSB. */
3206 if (start >= 16 && start + size == 32)
3207 {
3208 operands[3] = GEN_INT ((1 << size) - 1);
3209 return \"{andil.|andi.} %0,%1,%3\";
3210 }
3212 if (start + size >= 32)
3213 operands[3] = const0_rtx;
3214 else
3215 operands[3] = GEN_INT (start + size);
3216 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3217 }"
3218 [(set_attr "type" "compare")
3219 (set_attr "length" "4,8")])
3221 (define_split
3222 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3223 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3224 (match_operand:SI 2 "const_int_operand" "")
3225 (match_operand:SI 3 "const_int_operand" ""))
3226 (const_int 0)))
3227 (set (match_operand:SI 0 "gpc_reg_operand" "")
3228 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3229 "reload_completed"
3230 [(set (match_dup 0)
3231 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3232 (set (match_dup 4)
3233 (compare:CC (match_dup 0)
3234 (const_int 0)))]
3235 "")
3237 (define_insn "extzvdi"
3238 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3239 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3240 (match_operand:SI 2 "const_int_operand" "i")
3241 (match_operand:SI 3 "const_int_operand" "i")))]
3242 "TARGET_POWERPC64"
3243 "*
3244 {
3245 int start = INTVAL (operands[3]) & 63;
3246 int size = INTVAL (operands[2]) & 63;
3248 if (start + size >= 64)
3249 operands[3] = const0_rtx;
3250 else
3251 operands[3] = GEN_INT (start + size);
3252 operands[2] = GEN_INT (64 - size);
3253 return \"rldicl %0,%1,%3,%2\";
3254 }")
3256 (define_insn "*extzvdi_internal1"
3257 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3258 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3259 (match_operand:SI 2 "const_int_operand" "i")
3260 (match_operand:SI 3 "const_int_operand" "i"))
3261 (const_int 0)))
3262 (clobber (match_scratch:DI 4 "=r"))]
3263 "TARGET_64BIT"
3264 "*
3265 {
3266 int start = INTVAL (operands[3]) & 63;
3267 int size = INTVAL (operands[2]) & 63;
3269 if (start + size >= 64)
3270 operands[3] = const0_rtx;
3271 else
3272 operands[3] = GEN_INT (start + size);
3273 operands[2] = GEN_INT (64 - size);
3274 return \"rldicl. %4,%1,%3,%2\";
3275 }"
3276 [(set_attr "type" "compare")])
3278 (define_insn "*extzvdi_internal2"
3279 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3280 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3281 (match_operand:SI 2 "const_int_operand" "i")
3282 (match_operand:SI 3 "const_int_operand" "i"))
3283 (const_int 0)))
3284 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3285 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3286 "TARGET_64BIT"
3287 "*
3288 {
3289 int start = INTVAL (operands[3]) & 63;
3290 int size = INTVAL (operands[2]) & 63;
3292 if (start + size >= 64)
3293 operands[3] = const0_rtx;
3294 else
3295 operands[3] = GEN_INT (start + size);
3296 operands[2] = GEN_INT (64 - size);
3297 return \"rldicl. %0,%1,%3,%2\";
3298 }"
3299 [(set_attr "type" "compare")])
3301 (define_insn "rotlsi3"
3302 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3303 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3304 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3305 ""
3306 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3308 (define_insn "*rotlsi3_internal2"
3309 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3310 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3311 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3312 (const_int 0)))
3313 (clobber (match_scratch:SI 3 "=r,r"))]
3314 ""
3315 "@
3316 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3317 #"
3318 [(set_attr "type" "delayed_compare")
3319 (set_attr "length" "4,8")])
3321 (define_split
3322 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3323 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3324 (match_operand:SI 2 "reg_or_cint_operand" ""))
3325 (const_int 0)))
3326 (clobber (match_scratch:SI 3 ""))]
3327 "reload_completed"
3328 [(set (match_dup 3)
3329 (rotate:SI (match_dup 1) (match_dup 2)))
3330 (set (match_dup 0)
3331 (compare:CC (match_dup 3)
3332 (const_int 0)))]
3333 "")
3335 (define_insn "*rotlsi3_internal3"
3336 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3337 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3338 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3339 (const_int 0)))
3340 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3341 (rotate:SI (match_dup 1) (match_dup 2)))]
3342 ""
3343 "@
3344 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3345 #"
3346 [(set_attr "type" "delayed_compare")
3347 (set_attr "length" "4,8")])
3349 (define_split
3350 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3351 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3352 (match_operand:SI 2 "reg_or_cint_operand" ""))
3353 (const_int 0)))
3354 (set (match_operand:SI 0 "gpc_reg_operand" "")
3355 (rotate:SI (match_dup 1) (match_dup 2)))]
3356 "reload_completed"
3357 [(set (match_dup 0)
3358 (rotate:SI (match_dup 1) (match_dup 2)))
3359 (set (match_dup 3)
3360 (compare:CC (match_dup 0)
3361 (const_int 0)))]
3362 "")
3364 (define_insn "*rotlsi3_internal4"
3365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3366 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3367 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3368 (match_operand:SI 3 "mask_operand" "n")))]
3369 ""
3370 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3372 (define_insn "*rotlsi3_internal5"
3373 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3374 (compare:CC (and:SI
3375 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3376 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3377 (match_operand:SI 3 "mask_operand" "n,n"))
3378 (const_int 0)))
3379 (clobber (match_scratch:SI 4 "=r,r"))]
3380 ""
3381 "@
3382 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3383 #"
3384 [(set_attr "type" "delayed_compare")
3385 (set_attr "length" "4,8")])
3387 (define_split
3388 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3389 (compare:CC (and:SI
3390 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3391 (match_operand:SI 2 "reg_or_cint_operand" ""))
3392 (match_operand:SI 3 "mask_operand" ""))
3393 (const_int 0)))
3394 (clobber (match_scratch:SI 4 ""))]
3395 "reload_completed"
3396 [(set (match_dup 4)
3397 (and:SI (rotate:SI (match_dup 1)
3398 (match_dup 2))
3399 (match_dup 3)))
3400 (set (match_dup 0)
3401 (compare:CC (match_dup 4)
3402 (const_int 0)))]
3403 "")
3405 (define_insn "*rotlsi3_internal6"
3406 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3407 (compare:CC (and:SI
3408 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3409 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3410 (match_operand:SI 3 "mask_operand" "n,n"))
3411 (const_int 0)))
3412 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3413 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3414 ""
3415 "@
3416 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3417 #"
3418 [(set_attr "type" "delayed_compare")
3419 (set_attr "length" "4,8")])
3421 (define_split
3422 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3423 (compare:CC (and:SI
3424 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3425 (match_operand:SI 2 "reg_or_cint_operand" ""))
3426 (match_operand:SI 3 "mask_operand" ""))
3427 (const_int 0)))
3428 (set (match_operand:SI 0 "gpc_reg_operand" "")
3429 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3430 "reload_completed"
3431 [(set (match_dup 0)
3432 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3433 (set (match_dup 4)
3434 (compare:CC (match_dup 0)
3435 (const_int 0)))]
3436 "")
3438 (define_insn "*rotlsi3_internal7"
3439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3440 (zero_extend:SI
3441 (subreg:QI
3442 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3443 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3444 ""
3445 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3447 (define_insn "*rotlsi3_internal8"
3448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3449 (compare:CC (zero_extend:SI
3450 (subreg:QI
3451 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3452 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3453 (const_int 0)))
3454 (clobber (match_scratch:SI 3 "=r,r"))]
3455 ""
3456 "@
3457 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3458 #"
3459 [(set_attr "type" "delayed_compare")
3460 (set_attr "length" "4,8")])
3462 (define_split
3463 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3464 (compare:CC (zero_extend:SI
3465 (subreg:QI
3466 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3467 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3468 (const_int 0)))
3469 (clobber (match_scratch:SI 3 ""))]
3470 "reload_completed"
3471 [(set (match_dup 3)
3472 (zero_extend:SI (subreg:QI
3473 (rotate:SI (match_dup 1)
3474 (match_dup 2)) 0)))
3475 (set (match_dup 0)
3476 (compare:CC (match_dup 3)
3477 (const_int 0)))]
3478 "")
3480 (define_insn "*rotlsi3_internal9"
3481 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3482 (compare:CC (zero_extend:SI
3483 (subreg:QI
3484 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3485 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3486 (const_int 0)))
3487 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3488 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3489 ""
3490 "@
3491 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3492 #"
3493 [(set_attr "type" "delayed_compare")
3494 (set_attr "length" "4,8")])
3496 (define_split
3497 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3498 (compare:CC (zero_extend:SI
3499 (subreg:QI
3500 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3501 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3502 (const_int 0)))
3503 (set (match_operand:SI 0 "gpc_reg_operand" "")
3504 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3505 "reload_completed"
3506 [(set (match_dup 0)
3507 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3508 (set (match_dup 3)
3509 (compare:CC (match_dup 0)
3510 (const_int 0)))]
3511 "")
3513 (define_insn "*rotlsi3_internal10"
3514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3515 (zero_extend:SI
3516 (subreg:HI
3517 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3518 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3519 ""
3520 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3522 (define_insn "*rotlsi3_internal11"
3523 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3524 (compare:CC (zero_extend:SI
3525 (subreg:HI
3526 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3527 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3528 (const_int 0)))
3529 (clobber (match_scratch:SI 3 "=r,r"))]
3530 ""
3531 "@
3532 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3533 #"
3534 [(set_attr "type" "delayed_compare")
3535 (set_attr "length" "4,8")])
3537 (define_split
3538 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3539 (compare:CC (zero_extend:SI
3540 (subreg:HI
3541 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3542 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3543 (const_int 0)))
3544 (clobber (match_scratch:SI 3 ""))]
3545 "reload_completed"
3546 [(set (match_dup 3)
3547 (zero_extend:SI (subreg:HI
3548 (rotate:SI (match_dup 1)
3549 (match_dup 2)) 0)))
3550 (set (match_dup 0)
3551 (compare:CC (match_dup 3)
3552 (const_int 0)))]
3553 "")
3555 (define_insn "*rotlsi3_internal12"
3556 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3557 (compare:CC (zero_extend:SI
3558 (subreg:HI
3559 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3560 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3561 (const_int 0)))
3562 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3563 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3564 ""
3565 "@
3566 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3567 #"
3568 [(set_attr "type" "delayed_compare")
3569 (set_attr "length" "4,8")])
3571 (define_split
3572 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3573 (compare:CC (zero_extend:SI
3574 (subreg:HI
3575 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3576 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3577 (const_int 0)))
3578 (set (match_operand:SI 0 "gpc_reg_operand" "")
3579 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3580 "reload_completed"
3581 [(set (match_dup 0)
3582 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3583 (set (match_dup 3)
3584 (compare:CC (match_dup 0)
3585 (const_int 0)))]
3586 "")
3588 ;; Note that we use "sle." instead of "sl." so that we can set
3589 ;; SHIFT_COUNT_TRUNCATED.
3591 (define_expand "ashlsi3"
3592 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3593 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3594 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3595 ""
3596 "
3597 {
3598 if (TARGET_POWER)
3599 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3600 else
3601 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3602 DONE;
3603 }")
3605 (define_insn "ashlsi3_power"
3606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3607 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3608 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3609 (clobber (match_scratch:SI 3 "=q,X"))]
3610 "TARGET_POWER"
3611 "@
3612 sle %0,%1,%2
3613 {sli|slwi} %0,%1,%h2")
3615 (define_insn "ashlsi3_no_power"
3616 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3617 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3618 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3619 "! TARGET_POWER"
3620 "{sl|slw}%I2 %0,%1,%h2")
3622 (define_insn ""
3623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3624 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3625 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3626 (const_int 0)))
3627 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3628 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3629 "TARGET_POWER"
3630 "@
3631 sle. %3,%1,%2
3632 {sli.|slwi.} %3,%1,%h2
3633 #
3634 #"
3635 [(set_attr "type" "delayed_compare")
3636 (set_attr "length" "4,4,8,8")])
3638 (define_split
3639 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3640 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3641 (match_operand:SI 2 "reg_or_cint_operand" ""))
3642 (const_int 0)))
3643 (clobber (match_scratch:SI 3 ""))
3644 (clobber (match_scratch:SI 4 ""))]
3645 "TARGET_POWER && reload_completed"
3646 [(parallel [(set (match_dup 3)
3647 (ashift:SI (match_dup 1) (match_dup 2)))
3648 (clobber (match_dup 4))])
3649 (set (match_dup 0)
3650 (compare:CC (match_dup 3)
3651 (const_int 0)))]
3652 "")
3654 (define_insn ""
3655 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3656 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3657 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3658 (const_int 0)))
3659 (clobber (match_scratch:SI 3 "=r,r"))]
3660 "! TARGET_POWER && TARGET_32BIT"
3661 "@
3662 {sl|slw}%I2. %3,%1,%h2
3663 #"
3664 [(set_attr "type" "delayed_compare")
3665 (set_attr "length" "4,8")])
3667 (define_split
3668 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3669 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3670 (match_operand:SI 2 "reg_or_cint_operand" ""))
3671 (const_int 0)))
3672 (clobber (match_scratch:SI 3 ""))]
3673 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3674 [(set (match_dup 3)
3675 (ashift:SI (match_dup 1) (match_dup 2)))
3676 (set (match_dup 0)
3677 (compare:CC (match_dup 3)
3678 (const_int 0)))]
3679 "")
3681 (define_insn ""
3682 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3683 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3684 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3685 (const_int 0)))
3686 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3687 (ashift:SI (match_dup 1) (match_dup 2)))
3688 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3689 "TARGET_POWER"
3690 "@
3691 sle. %0,%1,%2
3692 {sli.|slwi.} %0,%1,%h2
3693 #
3694 #"
3695 [(set_attr "type" "delayed_compare")
3696 (set_attr "length" "4,4,8,8")])
3698 (define_split
3699 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3700 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3701 (match_operand:SI 2 "reg_or_cint_operand" ""))
3702 (const_int 0)))
3703 (set (match_operand:SI 0 "gpc_reg_operand" "")
3704 (ashift:SI (match_dup 1) (match_dup 2)))
3705 (clobber (match_scratch:SI 4 ""))]
3706 "TARGET_POWER && reload_completed"
3707 [(parallel [(set (match_dup 0)
3708 (ashift:SI (match_dup 1) (match_dup 2)))
3709 (clobber (match_dup 4))])
3710 (set (match_dup 3)
3711 (compare:CC (match_dup 0)
3712 (const_int 0)))]
3713 "")
3715 (define_insn ""
3716 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3717 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3718 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3719 (const_int 0)))
3720 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3721 (ashift:SI (match_dup 1) (match_dup 2)))]
3722 "! TARGET_POWER && TARGET_32BIT"
3723 "@
3724 {sl|slw}%I2. %0,%1,%h2
3725 #"
3726 [(set_attr "type" "delayed_compare")
3727 (set_attr "length" "4,8")])
3729 (define_split
3730 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3731 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3732 (match_operand:SI 2 "reg_or_cint_operand" ""))
3733 (const_int 0)))
3734 (set (match_operand:SI 0 "gpc_reg_operand" "")
3735 (ashift:SI (match_dup 1) (match_dup 2)))]
3736 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3737 [(set (match_dup 0)
3738 (ashift:SI (match_dup 1) (match_dup 2)))
3739 (set (match_dup 3)
3740 (compare:CC (match_dup 0)
3741 (const_int 0)))]
3742 "")
3744 (define_insn ""
3745 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3746 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3747 (match_operand:SI 2 "const_int_operand" "i"))
3748 (match_operand:SI 3 "mask_operand" "n")))]
3749 "includes_lshift_p (operands[2], operands[3])"
3750 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3752 (define_insn ""
3753 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3754 (compare:CC
3755 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3756 (match_operand:SI 2 "const_int_operand" "i,i"))
3757 (match_operand:SI 3 "mask_operand" "n,n"))
3758 (const_int 0)))
3759 (clobber (match_scratch:SI 4 "=r,r"))]
3760 "includes_lshift_p (operands[2], operands[3])"
3761 "@
3762 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3763 #"
3764 [(set_attr "type" "delayed_compare")
3765 (set_attr "length" "4,8")])
3767 (define_split
3768 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3769 (compare:CC
3770 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3771 (match_operand:SI 2 "const_int_operand" ""))
3772 (match_operand:SI 3 "mask_operand" ""))
3773 (const_int 0)))
3774 (clobber (match_scratch:SI 4 ""))]
3775 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3776 [(set (match_dup 4)
3777 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3778 (match_dup 3)))
3779 (set (match_dup 0)
3780 (compare:CC (match_dup 4)
3781 (const_int 0)))]
3782 "")
3784 (define_insn ""
3785 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3786 (compare:CC
3787 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3788 (match_operand:SI 2 "const_int_operand" "i,i"))
3789 (match_operand:SI 3 "mask_operand" "n,n"))
3790 (const_int 0)))
3791 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3792 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3793 "includes_lshift_p (operands[2], operands[3])"
3794 "@
3795 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3796 #"
3797 [(set_attr "type" "delayed_compare")
3798 (set_attr "length" "4,8")])
3800 (define_split
3801 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3802 (compare:CC
3803 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3804 (match_operand:SI 2 "const_int_operand" ""))
3805 (match_operand:SI 3 "mask_operand" ""))
3806 (const_int 0)))
3807 (set (match_operand:SI 0 "gpc_reg_operand" "")
3808 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3809 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3810 [(set (match_dup 0)
3811 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3812 (set (match_dup 4)
3813 (compare:CC (match_dup 0)
3814 (const_int 0)))]
3815 "")
3817 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3818 ;; "sli x,x,0".
3819 (define_expand "lshrsi3"
3820 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3821 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3822 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3823 ""
3824 "
3825 {
3826 if (TARGET_POWER)
3827 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3828 else
3829 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3830 DONE;
3831 }")
3833 (define_insn "lshrsi3_power"
3834 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3835 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3836 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3837 (clobber (match_scratch:SI 3 "=q,X,X"))]
3838 "TARGET_POWER"
3839 "@
3840 sre %0,%1,%2
3841 mr %0,%1
3842 {s%A2i|s%A2wi} %0,%1,%h2")
3844 (define_insn "lshrsi3_no_power"
3845 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3846 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3847 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3848 "! TARGET_POWER"
3849 "@
3850 mr %0,%1
3851 {sr|srw}%I2 %0,%1,%h2")
3853 (define_insn ""
3854 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3855 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3856 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3857 (const_int 0)))
3858 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3859 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3860 "TARGET_POWER"
3861 "@
3862 sre. %3,%1,%2
3863 mr. %1,%1
3864 {s%A2i.|s%A2wi.} %3,%1,%h2
3865 #
3866 #
3867 #"
3868 [(set_attr "type" "delayed_compare")
3869 (set_attr "length" "4,4,4,8,8,8")])
3871 (define_split
3872 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3873 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3874 (match_operand:SI 2 "reg_or_cint_operand" ""))
3875 (const_int 0)))
3876 (clobber (match_scratch:SI 3 ""))
3877 (clobber (match_scratch:SI 4 ""))]
3878 "TARGET_POWER && reload_completed"
3879 [(parallel [(set (match_dup 3)
3880 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3881 (clobber (match_dup 4))])
3882 (set (match_dup 0)
3883 (compare:CC (match_dup 3)
3884 (const_int 0)))]
3885 "")
3887 (define_insn ""
3888 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3889 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3890 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3891 (const_int 0)))
3892 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3893 "! TARGET_POWER && TARGET_32BIT"
3894 "@
3895 mr. %1,%1
3896 {sr|srw}%I2. %3,%1,%h2
3897 #
3898 #"
3899 [(set_attr "type" "delayed_compare")
3900 (set_attr "length" "4,4,8,8")])
3902 (define_split
3903 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3904 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3905 (match_operand:SI 2 "reg_or_cint_operand" ""))
3906 (const_int 0)))
3907 (clobber (match_scratch:SI 3 ""))]
3908 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3909 [(set (match_dup 3)
3910 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3911 (set (match_dup 0)
3912 (compare:CC (match_dup 3)
3913 (const_int 0)))]
3914 "")
3916 (define_insn ""
3917 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3918 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3919 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3920 (const_int 0)))
3921 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3922 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3923 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3924 "TARGET_POWER"
3925 "@
3926 sre. %0,%1,%2
3927 mr. %0,%1
3928 {s%A2i.|s%A2wi.} %0,%1,%h2
3929 #
3930 #
3931 #"
3932 [(set_attr "type" "delayed_compare")
3933 (set_attr "length" "4,4,4,8,8,8")])
3935 (define_split
3936 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3937 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3938 (match_operand:SI 2 "reg_or_cint_operand" ""))
3939 (const_int 0)))
3940 (set (match_operand:SI 0 "gpc_reg_operand" "")
3941 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3942 (clobber (match_scratch:SI 4 ""))]
3943 "TARGET_POWER && reload_completed"
3944 [(parallel [(set (match_dup 0)
3945 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3946 (clobber (match_dup 4))])
3947 (set (match_dup 3)
3948 (compare:CC (match_dup 0)
3949 (const_int 0)))]
3950 "")
3952 (define_insn ""
3953 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3954 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3955 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3956 (const_int 0)))
3957 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3958 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3959 "! TARGET_POWER && TARGET_32BIT"
3960 "@
3961 mr. %0,%1
3962 {sr|srw}%I2. %0,%1,%h2
3963 #
3964 #"
3965 [(set_attr "type" "delayed_compare")
3966 (set_attr "length" "4,4,8,8")])
3968 (define_split
3969 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3970 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3971 (match_operand:SI 2 "reg_or_cint_operand" ""))
3972 (const_int 0)))
3973 (set (match_operand:SI 0 "gpc_reg_operand" "")
3974 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3975 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3976 [(set (match_dup 0)
3977 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3978 (set (match_dup 3)
3979 (compare:CC (match_dup 0)
3980 (const_int 0)))]
3981 "")
3983 (define_insn ""
3984 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3985 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3986 (match_operand:SI 2 "const_int_operand" "i"))
3987 (match_operand:SI 3 "mask_operand" "n")))]
3988 "includes_rshift_p (operands[2], operands[3])"
3989 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3991 (define_insn ""
3992 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3993 (compare:CC
3994 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3995 (match_operand:SI 2 "const_int_operand" "i,i"))
3996 (match_operand:SI 3 "mask_operand" "n,n"))
3997 (const_int 0)))
3998 (clobber (match_scratch:SI 4 "=r,r"))]
3999 "includes_rshift_p (operands[2], operands[3])"
4000 "@
4001 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4002 #"
4003 [(set_attr "type" "delayed_compare")
4004 (set_attr "length" "4,8")])
4006 (define_split
4007 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4008 (compare:CC
4009 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4010 (match_operand:SI 2 "const_int_operand" ""))
4011 (match_operand:SI 3 "mask_operand" ""))
4012 (const_int 0)))
4013 (clobber (match_scratch:SI 4 ""))]
4014 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4015 [(set (match_dup 4)
4016 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4017 (match_dup 3)))
4018 (set (match_dup 0)
4019 (compare:CC (match_dup 4)
4020 (const_int 0)))]
4021 "")
4023 (define_insn ""
4024 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4025 (compare:CC
4026 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4027 (match_operand:SI 2 "const_int_operand" "i,i"))
4028 (match_operand:SI 3 "mask_operand" "n,n"))
4029 (const_int 0)))
4030 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4031 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4032 "includes_rshift_p (operands[2], operands[3])"
4033 "@
4034 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4035 #"
4036 [(set_attr "type" "delayed_compare")
4037 (set_attr "length" "4,8")])
4039 (define_split
4040 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4041 (compare:CC
4042 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4043 (match_operand:SI 2 "const_int_operand" ""))
4044 (match_operand:SI 3 "mask_operand" ""))
4045 (const_int 0)))
4046 (set (match_operand:SI 0 "gpc_reg_operand" "")
4047 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4048 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4049 [(set (match_dup 0)
4050 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4051 (set (match_dup 4)
4052 (compare:CC (match_dup 0)
4053 (const_int 0)))]
4054 "")
4056 (define_insn ""
4057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4058 (zero_extend:SI
4059 (subreg:QI
4060 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4061 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4062 "includes_rshift_p (operands[2], GEN_INT (255))"
4063 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4065 (define_insn ""
4066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4067 (compare:CC
4068 (zero_extend:SI
4069 (subreg:QI
4070 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4071 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4072 (const_int 0)))
4073 (clobber (match_scratch:SI 3 "=r,r"))]
4074 "includes_rshift_p (operands[2], GEN_INT (255))"
4075 "@
4076 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4077 #"
4078 [(set_attr "type" "delayed_compare")
4079 (set_attr "length" "4,8")])
4081 (define_split
4082 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4083 (compare:CC
4084 (zero_extend:SI
4085 (subreg:QI
4086 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4087 (match_operand:SI 2 "const_int_operand" "")) 0))
4088 (const_int 0)))
4089 (clobber (match_scratch:SI 3 ""))]
4090 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4091 [(set (match_dup 3)
4092 (zero_extend:SI (subreg:QI
4093 (lshiftrt:SI (match_dup 1)
4094 (match_dup 2)) 0)))
4095 (set (match_dup 0)
4096 (compare:CC (match_dup 3)
4097 (const_int 0)))]
4098 "")
4100 (define_insn ""
4101 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4102 (compare:CC
4103 (zero_extend:SI
4104 (subreg:QI
4105 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4106 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4107 (const_int 0)))
4108 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4109 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4110 "includes_rshift_p (operands[2], GEN_INT (255))"
4111 "@
4112 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4113 #"
4114 [(set_attr "type" "delayed_compare")
4115 (set_attr "length" "4,8")])
4117 (define_split
4118 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4119 (compare:CC
4120 (zero_extend:SI
4121 (subreg:QI
4122 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4123 (match_operand:SI 2 "const_int_operand" "")) 0))
4124 (const_int 0)))
4125 (set (match_operand:SI 0 "gpc_reg_operand" "")
4126 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4127 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4128 [(set (match_dup 0)
4129 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4130 (set (match_dup 3)
4131 (compare:CC (match_dup 0)
4132 (const_int 0)))]
4133 "")
4135 (define_insn ""
4136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4137 (zero_extend:SI
4138 (subreg:HI
4139 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4140 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4141 "includes_rshift_p (operands[2], GEN_INT (65535))"
4142 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4144 (define_insn ""
4145 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4146 (compare:CC
4147 (zero_extend:SI
4148 (subreg:HI
4149 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4150 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4151 (const_int 0)))
4152 (clobber (match_scratch:SI 3 "=r,r"))]
4153 "includes_rshift_p (operands[2], GEN_INT (65535))"
4154 "@
4155 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4156 #"
4157 [(set_attr "type" "delayed_compare")
4158 (set_attr "length" "4,8")])
4160 (define_split
4161 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4162 (compare:CC
4163 (zero_extend:SI
4164 (subreg:HI
4165 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4166 (match_operand:SI 2 "const_int_operand" "")) 0))
4167 (const_int 0)))
4168 (clobber (match_scratch:SI 3 ""))]
4169 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4170 [(set (match_dup 3)
4171 (zero_extend:SI (subreg:HI
4172 (lshiftrt:SI (match_dup 1)
4173 (match_dup 2)) 0)))
4174 (set (match_dup 0)
4175 (compare:CC (match_dup 3)
4176 (const_int 0)))]
4177 "")
4179 (define_insn ""
4180 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4181 (compare:CC
4182 (zero_extend:SI
4183 (subreg:HI
4184 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4185 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4186 (const_int 0)))
4187 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4188 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4189 "includes_rshift_p (operands[2], GEN_INT (65535))"
4190 "@
4191 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4192 #"
4193 [(set_attr "type" "delayed_compare")
4194 (set_attr "length" "4,8")])
4196 (define_split
4197 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4198 (compare:CC
4199 (zero_extend:SI
4200 (subreg:HI
4201 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4202 (match_operand:SI 2 "const_int_operand" "")) 0))
4203 (const_int 0)))
4204 (set (match_operand:SI 0 "gpc_reg_operand" "")
4205 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4206 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4207 [(set (match_dup 0)
4208 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4209 (set (match_dup 3)
4210 (compare:CC (match_dup 0)
4211 (const_int 0)))]
4212 "")
4214 (define_insn ""
4215 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4216 (const_int 1)
4217 (match_operand:SI 1 "gpc_reg_operand" "r"))
4218 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4219 (const_int 31)))]
4220 "TARGET_POWER"
4221 "rrib %0,%1,%2")
4223 (define_insn ""
4224 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4225 (const_int 1)
4226 (match_operand:SI 1 "gpc_reg_operand" "r"))
4227 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4228 (const_int 31)))]
4229 "TARGET_POWER"
4230 "rrib %0,%1,%2")
4232 (define_insn ""
4233 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4234 (const_int 1)
4235 (match_operand:SI 1 "gpc_reg_operand" "r"))
4236 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4237 (const_int 1)
4238 (const_int 0)))]
4239 "TARGET_POWER"
4240 "rrib %0,%1,%2")
4242 (define_expand "ashrsi3"
4243 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4244 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4245 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4246 ""
4247 "
4248 {
4249 if (TARGET_POWER)
4250 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4251 else
4252 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4253 DONE;
4254 }")
4256 (define_insn "ashrsi3_power"
4257 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4258 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4259 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4260 (clobber (match_scratch:SI 3 "=q,X"))]
4261 "TARGET_POWER"
4262 "@
4263 srea %0,%1,%2
4264 {srai|srawi} %0,%1,%h2")
4266 (define_insn "ashrsi3_no_power"
4267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4268 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4269 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4270 "! TARGET_POWER"
4271 "{sra|sraw}%I2 %0,%1,%h2")
4273 (define_insn ""
4274 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4275 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4276 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4277 (const_int 0)))
4278 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4279 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4280 "TARGET_POWER"
4281 "@
4282 srea. %3,%1,%2
4283 {srai.|srawi.} %3,%1,%h2
4284 #
4285 #"
4286 [(set_attr "type" "delayed_compare")
4287 (set_attr "length" "4,4,8,8")])
4289 (define_split
4290 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4291 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4292 (match_operand:SI 2 "reg_or_cint_operand" ""))
4293 (const_int 0)))
4294 (clobber (match_scratch:SI 3 ""))
4295 (clobber (match_scratch:SI 4 ""))]
4296 "TARGET_POWER && reload_completed"
4297 [(parallel [(set (match_dup 3)
4298 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4299 (clobber (match_dup 4))])
4300 (set (match_dup 0)
4301 (compare:CC (match_dup 3)
4302 (const_int 0)))]
4303 "")
4305 (define_insn ""
4306 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4307 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4308 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4309 (const_int 0)))
4310 (clobber (match_scratch:SI 3 "=r,r"))]
4311 "! TARGET_POWER"
4312 "@
4313 {sra|sraw}%I2. %3,%1,%h2
4314 #"
4315 [(set_attr "type" "delayed_compare")
4316 (set_attr "length" "4,8")])
4318 (define_split
4319 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4320 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4321 (match_operand:SI 2 "reg_or_cint_operand" ""))
4322 (const_int 0)))
4323 (clobber (match_scratch:SI 3 ""))]
4324 "! TARGET_POWER && reload_completed"
4325 [(set (match_dup 3)
4326 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4327 (set (match_dup 0)
4328 (compare:CC (match_dup 3)
4329 (const_int 0)))]
4330 "")
4332 (define_insn ""
4333 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4334 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4335 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4336 (const_int 0)))
4337 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4338 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4339 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4340 "TARGET_POWER"
4341 "@
4342 srea. %0,%1,%2
4343 {srai.|srawi.} %0,%1,%h2
4344 #
4345 #"
4346 [(set_attr "type" "delayed_compare")
4347 (set_attr "length" "4,4,8,8")])
4349 (define_split
4350 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4351 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4352 (match_operand:SI 2 "reg_or_cint_operand" ""))
4353 (const_int 0)))
4354 (set (match_operand:SI 0 "gpc_reg_operand" "")
4355 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4356 (clobber (match_scratch:SI 4 ""))]
4357 "TARGET_POWER && reload_completed"
4358 [(parallel [(set (match_dup 0)
4359 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4360 (clobber (match_dup 4))])
4361 (set (match_dup 3)
4362 (compare:CC (match_dup 0)
4363 (const_int 0)))]
4364 "")
4366 (define_insn ""
4367 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4368 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4369 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4370 (const_int 0)))
4371 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4372 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4373 "! TARGET_POWER"
4374 "@
4375 {sra|sraw}%I2. %0,%1,%h2
4376 #"
4377 [(set_attr "type" "delayed_compare")
4378 (set_attr "length" "4,8")])
4379 \f
4380 (define_split
4381 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4382 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4383 (match_operand:SI 2 "reg_or_cint_operand" ""))
4384 (const_int 0)))
4385 (set (match_operand:SI 0 "gpc_reg_operand" "")
4386 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4387 "! TARGET_POWER && reload_completed"
4388 [(set (match_dup 0)
4389 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4390 (set (match_dup 3)
4391 (compare:CC (match_dup 0)
4392 (const_int 0)))]
4393 "")
4395 ;; Floating-point insns, excluding normal data motion.
4396 ;;
4397 ;; PowerPC has a full set of single-precision floating point instructions.
4398 ;;
4399 ;; For the POWER architecture, we pretend that we have both SFmode and
4400 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4401 ;; The only conversions we will do will be when storing to memory. In that
4402 ;; case, we will use the "frsp" instruction before storing.
4403 ;;
4404 ;; Note that when we store into a single-precision memory location, we need to
4405 ;; use the frsp insn first. If the register being stored isn't dead, we
4406 ;; need a scratch register for the frsp. But this is difficult when the store
4407 ;; is done by reload. It is not incorrect to do the frsp on the register in
4408 ;; this case, we just lose precision that we would have otherwise gotten but
4409 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4411 (define_expand "extendsfdf2"
4412 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4413 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))]
4414 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4415 "")
4417 (define_insn_and_split "*extendsfdf2_fpr"
4418 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
4419 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))]
4420 "TARGET_HARD_FLOAT && TARGET_FPRS"
4421 "@
4422 #
4423 fmr %0,%1"
4424 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
4425 [(const_int 0)]
4426 {
4427 emit_note (NOTE_INSN_DELETED);
4428 DONE;
4429 }
4430 [(set_attr "type" "fp")])
4432 (define_expand "truncdfsf2"
4433 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4434 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4435 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4436 "")
4438 (define_insn "*truncdfsf2_fpr"
4439 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4440 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4441 "TARGET_HARD_FLOAT && TARGET_FPRS"
4442 "frsp %0,%1"
4443 [(set_attr "type" "fp")])
4445 (define_insn "aux_truncdfsf2"
4446 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4447 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4448 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4449 "frsp %0,%1"
4450 [(set_attr "type" "fp")])
4452 (define_expand "negsf2"
4453 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4454 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4455 "TARGET_HARD_FLOAT"
4456 "")
4458 (define_insn "*negsf2"
4459 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4460 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4461 "TARGET_HARD_FLOAT && TARGET_FPRS"
4462 "fneg %0,%1"
4463 [(set_attr "type" "fp")])
4465 (define_expand "abssf2"
4466 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4467 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4468 "TARGET_HARD_FLOAT"
4469 "")
4471 (define_insn "*abssf2"
4472 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4473 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4474 "TARGET_HARD_FLOAT && TARGET_FPRS"
4475 "fabs %0,%1"
4476 [(set_attr "type" "fp")])
4478 (define_insn ""
4479 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4480 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4481 "TARGET_HARD_FLOAT && TARGET_FPRS"
4482 "fnabs %0,%1"
4483 [(set_attr "type" "fp")])
4485 (define_expand "addsf3"
4486 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4487 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4488 (match_operand:SF 2 "gpc_reg_operand" "")))]
4489 "TARGET_HARD_FLOAT"
4490 "")
4492 (define_insn ""
4493 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4494 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4495 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4496 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4497 "fadds %0,%1,%2"
4498 [(set_attr "type" "fp")])
4500 (define_insn ""
4501 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4502 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4503 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4504 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4505 "{fa|fadd} %0,%1,%2"
4506 [(set_attr "type" "fp")])
4508 (define_expand "subsf3"
4509 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4510 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4511 (match_operand:SF 2 "gpc_reg_operand" "")))]
4512 "TARGET_HARD_FLOAT"
4513 "")
4515 (define_insn ""
4516 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4517 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4518 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4519 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4520 "fsubs %0,%1,%2"
4521 [(set_attr "type" "fp")])
4523 (define_insn ""
4524 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4525 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4526 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4527 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4528 "{fs|fsub} %0,%1,%2"
4529 [(set_attr "type" "fp")])
4531 (define_expand "mulsf3"
4532 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4533 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4534 (match_operand:SF 2 "gpc_reg_operand" "")))]
4535 "TARGET_HARD_FLOAT"
4536 "")
4538 (define_insn ""
4539 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4540 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4541 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4542 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4543 "fmuls %0,%1,%2"
4544 [(set_attr "type" "fp")])
4546 (define_insn ""
4547 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4548 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4549 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4550 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4551 "{fm|fmul} %0,%1,%2"
4552 [(set_attr "type" "dmul")])
4554 (define_expand "divsf3"
4555 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4556 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4557 (match_operand:SF 2 "gpc_reg_operand" "")))]
4558 "TARGET_HARD_FLOAT"
4559 "")
4561 (define_insn ""
4562 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4563 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4564 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4565 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4566 "fdivs %0,%1,%2"
4567 [(set_attr "type" "sdiv")])
4569 (define_insn ""
4570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4571 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4572 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4573 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4574 "{fd|fdiv} %0,%1,%2"
4575 [(set_attr "type" "ddiv")])
4577 (define_insn ""
4578 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4579 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4580 (match_operand:SF 2 "gpc_reg_operand" "f"))
4581 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4582 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4583 "fmadds %0,%1,%2,%3"
4584 [(set_attr "type" "fp")])
4586 (define_insn ""
4587 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4588 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4589 (match_operand:SF 2 "gpc_reg_operand" "f"))
4590 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4591 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4592 "{fma|fmadd} %0,%1,%2,%3"
4593 [(set_attr "type" "dmul")])
4595 (define_insn ""
4596 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4597 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4598 (match_operand:SF 2 "gpc_reg_operand" "f"))
4599 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4600 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4601 "fmsubs %0,%1,%2,%3"
4602 [(set_attr "type" "fp")])
4604 (define_insn ""
4605 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4606 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4607 (match_operand:SF 2 "gpc_reg_operand" "f"))
4608 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4609 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4610 "{fms|fmsub} %0,%1,%2,%3"
4611 [(set_attr "type" "dmul")])
4613 (define_insn ""
4614 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4615 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4616 (match_operand:SF 2 "gpc_reg_operand" "f"))
4617 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4618 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4619 && HONOR_SIGNED_ZEROS (SFmode)"
4620 "fnmadds %0,%1,%2,%3"
4621 [(set_attr "type" "fp")])
4623 (define_insn ""
4624 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4625 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4626 (match_operand:SF 2 "gpc_reg_operand" "f"))
4627 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4628 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4629 && ! HONOR_SIGNED_ZEROS (SFmode)"
4630 "fnmadds %0,%1,%2,%3"
4631 [(set_attr "type" "fp")])
4633 (define_insn ""
4634 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4635 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4636 (match_operand:SF 2 "gpc_reg_operand" "f"))
4637 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4638 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4639 "{fnma|fnmadd} %0,%1,%2,%3"
4640 [(set_attr "type" "dmul")])
4642 (define_insn ""
4643 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4644 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4645 (match_operand:SF 2 "gpc_reg_operand" "f"))
4646 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4647 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4648 && ! HONOR_SIGNED_ZEROS (SFmode)"
4649 "{fnma|fnmadd} %0,%1,%2,%3"
4650 [(set_attr "type" "dmul")])
4652 (define_insn ""
4653 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4654 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4655 (match_operand:SF 2 "gpc_reg_operand" "f"))
4656 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4657 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4658 && HONOR_SIGNED_ZEROS (SFmode)"
4659 "fnmsubs %0,%1,%2,%3"
4660 [(set_attr "type" "fp")])
4662 (define_insn ""
4663 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4664 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4665 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4666 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4667 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4668 && ! HONOR_SIGNED_ZEROS (SFmode)"
4669 "fnmsubs %0,%1,%2,%3"
4670 [(set_attr "type" "fp")])
4672 (define_insn ""
4673 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4674 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4675 (match_operand:SF 2 "gpc_reg_operand" "f"))
4676 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4677 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4678 "{fnms|fnmsub} %0,%1,%2,%3"
4679 [(set_attr "type" "dmul")])
4681 (define_insn ""
4682 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4683 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4684 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4685 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4686 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4687 && ! HONOR_SIGNED_ZEROS (SFmode)"
4688 "{fnms|fnmsub} %0,%1,%2,%3"
4689 [(set_attr "type" "fp")])
4691 (define_expand "sqrtsf2"
4692 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4693 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4694 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4695 "")
4697 (define_insn ""
4698 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4699 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4700 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4701 "fsqrts %0,%1"
4702 [(set_attr "type" "ssqrt")])
4704 (define_insn ""
4705 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4706 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4707 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4708 "fsqrt %0,%1"
4709 [(set_attr "type" "dsqrt")])
4711 (define_expand "copysignsf3"
4712 [(set (match_dup 3)
4713 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4714 (set (match_dup 4)
4715 (neg:SF (abs:SF (match_dup 1))))
4716 (set (match_operand:SF 0 "gpc_reg_operand" "")
4717 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4718 (match_dup 5))
4719 (match_dup 3)
4720 (match_dup 4)))]
4721 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4722 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4723 {
4724 operands[3] = gen_reg_rtx (SFmode);
4725 operands[4] = gen_reg_rtx (SFmode);
4726 operands[5] = CONST0_RTX (SFmode);
4727 })
4729 (define_expand "copysigndf3"
4730 [(set (match_dup 3)
4731 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4732 (set (match_dup 4)
4733 (neg:DF (abs:DF (match_dup 1))))
4734 (set (match_operand:DF 0 "gpc_reg_operand" "")
4735 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4736 (match_dup 5))
4737 (match_dup 3)
4738 (match_dup 4)))]
4739 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4740 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4741 {
4742 operands[3] = gen_reg_rtx (DFmode);
4743 operands[4] = gen_reg_rtx (DFmode);
4744 operands[5] = CONST0_RTX (DFmode);
4745 })
4747 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4748 ;; fsel instruction and some auxiliary computations. Then we just have a
4749 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4750 ;; combine.
4751 (define_expand "smaxsf3"
4752 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4753 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4754 (match_operand:SF 2 "gpc_reg_operand" ""))
4755 (match_dup 1)
4756 (match_dup 2)))]
4757 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4758 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4760 (define_expand "sminsf3"
4761 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4762 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4763 (match_operand:SF 2 "gpc_reg_operand" ""))
4764 (match_dup 2)
4765 (match_dup 1)))]
4766 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4767 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4769 (define_split
4770 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4771 (match_operator:SF 3 "min_max_operator"
4772 [(match_operand:SF 1 "gpc_reg_operand" "")
4773 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4774 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4775 [(const_int 0)]
4776 "
4777 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4778 operands[1], operands[2]);
4779 DONE;
4780 }")
4782 (define_expand "movsicc"
4783 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4784 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4785 (match_operand:SI 2 "gpc_reg_operand" "")
4786 (match_operand:SI 3 "gpc_reg_operand" "")))]
4787 "TARGET_ISEL"
4788 "
4789 {
4790 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4791 DONE;
4792 else
4793 FAIL;
4794 }")
4796 ;; We use the BASE_REGS for the isel input operands because, if rA is
4797 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4798 ;; because we may switch the operands and rB may end up being rA.
4799 ;;
4800 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4801 ;; leave out the mode in operand 4 and use one pattern, but reload can
4802 ;; change the mode underneath our feet and then gets confused trying
4803 ;; to reload the value.
4804 (define_insn "isel_signed"
4805 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4806 (if_then_else:SI
4807 (match_operator 1 "comparison_operator"
4808 [(match_operand:CC 4 "cc_reg_operand" "y")
4809 (const_int 0)])
4810 (match_operand:SI 2 "gpc_reg_operand" "b")
4811 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4812 "TARGET_ISEL"
4813 "*
4814 { return output_isel (operands); }"
4815 [(set_attr "length" "4")])
4817 (define_insn "isel_unsigned"
4818 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4819 (if_then_else:SI
4820 (match_operator 1 "comparison_operator"
4821 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4822 (const_int 0)])
4823 (match_operand:SI 2 "gpc_reg_operand" "b")
4824 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4825 "TARGET_ISEL"
4826 "*
4827 { return output_isel (operands); }"
4828 [(set_attr "length" "4")])
4830 (define_expand "movsfcc"
4831 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4832 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4833 (match_operand:SF 2 "gpc_reg_operand" "")
4834 (match_operand:SF 3 "gpc_reg_operand" "")))]
4835 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4836 "
4837 {
4838 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4839 DONE;
4840 else
4841 FAIL;
4842 }")
4844 (define_insn "*fselsfsf4"
4845 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4846 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4847 (match_operand:SF 4 "zero_fp_constant" "F"))
4848 (match_operand:SF 2 "gpc_reg_operand" "f")
4849 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4850 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4851 "fsel %0,%1,%2,%3"
4852 [(set_attr "type" "fp")])
4854 (define_insn "*fseldfsf4"
4855 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4856 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4857 (match_operand:DF 4 "zero_fp_constant" "F"))
4858 (match_operand:SF 2 "gpc_reg_operand" "f")
4859 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4860 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4861 "fsel %0,%1,%2,%3"
4862 [(set_attr "type" "fp")])
4864 (define_expand "negdf2"
4865 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4866 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4867 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4868 "")
4870 (define_insn "*negdf2_fpr"
4871 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4872 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4873 "TARGET_HARD_FLOAT && TARGET_FPRS"
4874 "fneg %0,%1"
4875 [(set_attr "type" "fp")])
4877 (define_expand "absdf2"
4878 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4879 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4880 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4881 "")
4883 (define_insn "*absdf2_fpr"
4884 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4885 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4886 "TARGET_HARD_FLOAT && TARGET_FPRS"
4887 "fabs %0,%1"
4888 [(set_attr "type" "fp")])
4890 (define_insn "*nabsdf2_fpr"
4891 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4892 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4893 "TARGET_HARD_FLOAT && TARGET_FPRS"
4894 "fnabs %0,%1"
4895 [(set_attr "type" "fp")])
4897 (define_expand "adddf3"
4898 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4899 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4900 (match_operand:DF 2 "gpc_reg_operand" "")))]
4901 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4902 "")
4904 (define_insn "*adddf3_fpr"
4905 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4906 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4907 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4908 "TARGET_HARD_FLOAT && TARGET_FPRS"
4909 "{fa|fadd} %0,%1,%2"
4910 [(set_attr "type" "fp")])
4912 (define_expand "subdf3"
4913 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4914 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4915 (match_operand:DF 2 "gpc_reg_operand" "")))]
4916 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4917 "")
4919 (define_insn "*subdf3_fpr"
4920 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4921 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4922 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4923 "TARGET_HARD_FLOAT && TARGET_FPRS"
4924 "{fs|fsub} %0,%1,%2"
4925 [(set_attr "type" "fp")])
4927 (define_expand "muldf3"
4928 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4929 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4930 (match_operand:DF 2 "gpc_reg_operand" "")))]
4931 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4932 "")
4934 (define_insn "*muldf3_fpr"
4935 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4936 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4937 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4938 "TARGET_HARD_FLOAT && TARGET_FPRS"
4939 "{fm|fmul} %0,%1,%2"
4940 [(set_attr "type" "dmul")])
4942 (define_expand "divdf3"
4943 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4944 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4945 (match_operand:DF 2 "gpc_reg_operand" "")))]
4946 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4947 "")
4949 (define_insn "*divdf3_fpr"
4950 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4951 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4952 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4953 "TARGET_HARD_FLOAT && TARGET_FPRS"
4954 "{fd|fdiv} %0,%1,%2"
4955 [(set_attr "type" "ddiv")])
4957 (define_insn ""
4958 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4959 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4960 (match_operand:DF 2 "gpc_reg_operand" "f"))
4961 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4962 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4963 "{fma|fmadd} %0,%1,%2,%3"
4964 [(set_attr "type" "dmul")])
4966 (define_insn ""
4967 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4968 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4969 (match_operand:DF 2 "gpc_reg_operand" "f"))
4970 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4971 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4972 "{fms|fmsub} %0,%1,%2,%3"
4973 [(set_attr "type" "dmul")])
4975 (define_insn ""
4976 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4977 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4978 (match_operand:DF 2 "gpc_reg_operand" "f"))
4979 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4980 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4981 && HONOR_SIGNED_ZEROS (DFmode)"
4982 "{fnma|fnmadd} %0,%1,%2,%3"
4983 [(set_attr "type" "dmul")])
4985 (define_insn ""
4986 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4987 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4988 (match_operand:DF 2 "gpc_reg_operand" "f"))
4989 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4990 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4991 && ! HONOR_SIGNED_ZEROS (DFmode)"
4992 "{fnma|fnmadd} %0,%1,%2,%3"
4993 [(set_attr "type" "dmul")])
4995 (define_insn ""
4996 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4997 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4998 (match_operand:DF 2 "gpc_reg_operand" "f"))
4999 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5000 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5001 && HONOR_SIGNED_ZEROS (DFmode)"
5002 "{fnms|fnmsub} %0,%1,%2,%3"
5003 [(set_attr "type" "dmul")])
5005 (define_insn ""
5006 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5007 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5008 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5009 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5010 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5011 && ! HONOR_SIGNED_ZEROS (DFmode)"
5012 "{fnms|fnmsub} %0,%1,%2,%3"
5013 [(set_attr "type" "dmul")])
5015 (define_insn "sqrtdf2"
5016 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5017 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5018 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5019 "fsqrt %0,%1"
5020 [(set_attr "type" "dsqrt")])
5022 ;; The conditional move instructions allow us to perform max and min
5023 ;; operations even when
5025 (define_expand "smaxdf3"
5026 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5027 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5028 (match_operand:DF 2 "gpc_reg_operand" ""))
5029 (match_dup 1)
5030 (match_dup 2)))]
5031 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5032 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5034 (define_expand "smindf3"
5035 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5036 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5037 (match_operand:DF 2 "gpc_reg_operand" ""))
5038 (match_dup 2)
5039 (match_dup 1)))]
5040 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5041 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5043 (define_split
5044 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5045 (match_operator:DF 3 "min_max_operator"
5046 [(match_operand:DF 1 "gpc_reg_operand" "")
5047 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5048 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5049 [(const_int 0)]
5050 "
5051 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5052 operands[1], operands[2]);
5053 DONE;
5054 }")
5056 (define_expand "movdfcc"
5057 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5058 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5059 (match_operand:DF 2 "gpc_reg_operand" "")
5060 (match_operand:DF 3 "gpc_reg_operand" "")))]
5061 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5062 "
5063 {
5064 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5065 DONE;
5066 else
5067 FAIL;
5068 }")
5070 (define_insn "*fseldfdf4"
5071 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5072 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5073 (match_operand:DF 4 "zero_fp_constant" "F"))
5074 (match_operand:DF 2 "gpc_reg_operand" "f")
5075 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5076 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5077 "fsel %0,%1,%2,%3"
5078 [(set_attr "type" "fp")])
5080 (define_insn "*fselsfdf4"
5081 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5082 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5083 (match_operand:SF 4 "zero_fp_constant" "F"))
5084 (match_operand:DF 2 "gpc_reg_operand" "f")
5085 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5086 "TARGET_PPC_GFXOPT"
5087 "fsel %0,%1,%2,%3"
5088 [(set_attr "type" "fp")])
5089 \f
5090 ;; Conversions to and from floating-point.
5092 (define_expand "fixuns_truncsfsi2"
5093 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5094 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5095 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5096 "")
5098 (define_expand "fix_truncsfsi2"
5099 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5100 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5101 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5102 "")
5104 ; For each of these conversions, there is a define_expand, a define_insn
5105 ; with a '#' template, and a define_split (with C code). The idea is
5106 ; to allow constant folding with the template of the define_insn,
5107 ; then to have the insns split later (between sched1 and final).
5109 (define_expand "floatsidf2"
5110 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5111 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5112 (use (match_dup 2))
5113 (use (match_dup 3))
5114 (clobber (match_dup 4))
5115 (clobber (match_dup 5))
5116 (clobber (match_dup 6))])]
5117 "TARGET_HARD_FLOAT && TARGET_FPRS"
5118 "
5119 {
5120 if (TARGET_E500_DOUBLE)
5121 {
5122 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5123 DONE;
5124 }
5125 if (TARGET_POWERPC64)
5126 {
5127 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5128 rtx t1 = gen_reg_rtx (DImode);
5129 rtx t2 = gen_reg_rtx (DImode);
5130 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5131 DONE;
5132 }
5134 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5135 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5136 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5137 operands[5] = gen_reg_rtx (DFmode);
5138 operands[6] = gen_reg_rtx (SImode);
5139 }")
5141 (define_insn "*floatsidf2_internal"
5142 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5143 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5144 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5145 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5146 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5147 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5148 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5149 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5150 "#"
5151 [(set_attr "length" "24")])
5153 (define_split
5154 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5155 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5156 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5157 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5158 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5159 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5160 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5161 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5162 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5163 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5164 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5165 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5166 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5167 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5168 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5169 "
5170 {
5171 rtx lowword, highword;
5172 if (GET_CODE (operands[4]) != MEM)
5173 abort();
5174 highword = XEXP (operands[4], 0);
5175 lowword = plus_constant (highword, 4);
5176 if (! WORDS_BIG_ENDIAN)
5177 {
5178 rtx tmp;
5179 tmp = highword; highword = lowword; lowword = tmp;
5180 }
5182 emit_insn (gen_xorsi3 (operands[6], operands[1],
5183 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5184 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5185 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5186 emit_move_insn (operands[5], operands[4]);
5187 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5188 DONE;
5189 }")
5191 (define_expand "floatunssisf2"
5192 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5193 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5194 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5195 "")
5197 (define_expand "floatunssidf2"
5198 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5199 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5200 (use (match_dup 2))
5201 (use (match_dup 3))
5202 (clobber (match_dup 4))
5203 (clobber (match_dup 5))])]
5204 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5205 "
5206 {
5207 if (TARGET_E500_DOUBLE)
5208 {
5209 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5210 DONE;
5211 }
5212 if (TARGET_POWERPC64)
5213 {
5214 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5215 rtx t1 = gen_reg_rtx (DImode);
5216 rtx t2 = gen_reg_rtx (DImode);
5217 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5218 t1, t2));
5219 DONE;
5220 }
5222 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5223 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5224 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5225 operands[5] = gen_reg_rtx (DFmode);
5226 }")
5228 (define_insn "*floatunssidf2_internal"
5229 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5230 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5231 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5232 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5233 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5234 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5235 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5236 "#"
5237 [(set_attr "length" "20")])
5239 (define_split
5240 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5241 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5242 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5243 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5244 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5245 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5246 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5247 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5248 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5249 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5250 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5251 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5252 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5253 "
5254 {
5255 rtx lowword, highword;
5256 if (GET_CODE (operands[4]) != MEM)
5257 abort();
5258 highword = XEXP (operands[4], 0);
5259 lowword = plus_constant (highword, 4);
5260 if (! WORDS_BIG_ENDIAN)
5261 {
5262 rtx tmp;
5263 tmp = highword; highword = lowword; lowword = tmp;
5264 }
5266 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5267 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5268 emit_move_insn (operands[5], operands[4]);
5269 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5270 DONE;
5271 }")
5273 (define_expand "fix_truncdfsi2"
5274 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5275 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5276 (clobber (match_dup 2))
5277 (clobber (match_dup 3))])]
5278 "(TARGET_POWER2 || TARGET_POWERPC)
5279 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5280 "
5281 {
5282 if (TARGET_E500_DOUBLE)
5283 {
5284 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5285 DONE;
5286 }
5287 operands[2] = gen_reg_rtx (DImode);
5288 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5289 }")
5291 (define_insn "*fix_truncdfsi2_internal"
5292 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5293 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5294 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5295 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5296 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5297 "#"
5298 [(set_attr "length" "16")])
5300 (define_split
5301 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5302 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5303 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5304 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5305 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5306 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5307 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5308 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5309 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5310 "
5311 {
5312 rtx lowword;
5313 if (GET_CODE (operands[3]) != MEM)
5314 abort();
5315 lowword = XEXP (operands[3], 0);
5316 if (WORDS_BIG_ENDIAN)
5317 lowword = plus_constant (lowword, 4);
5319 emit_insn (gen_fctiwz (operands[2], operands[1]));
5320 emit_move_insn (operands[3], operands[2]);
5321 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5322 DONE;
5323 }")
5325 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5326 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5327 ; because the first makes it clear that operand 0 is not live
5328 ; before the instruction.
5329 (define_insn "fctiwz"
5330 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5331 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5332 UNSPEC_FCTIWZ))]
5333 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5334 "{fcirz|fctiwz} %0,%1"
5335 [(set_attr "type" "fp")])
5337 (define_expand "floatsisf2"
5338 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5339 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5340 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5341 "")
5343 (define_insn "floatdidf2"
5344 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5345 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5346 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5347 "fcfid %0,%1"
5348 [(set_attr "type" "fp")])
5350 (define_insn_and_split "floatsidf_ppc64"
5351 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5352 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5353 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5354 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5355 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5356 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5357 "#"
5358 "&& 1"
5359 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5360 (set (match_dup 2) (match_dup 3))
5361 (set (match_dup 4) (match_dup 2))
5362 (set (match_dup 0) (float:DF (match_dup 4)))]
5363 "")
5365 (define_insn_and_split "floatunssidf_ppc64"
5366 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5367 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5368 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5369 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5370 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5371 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5372 "#"
5373 "&& 1"
5374 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5375 (set (match_dup 2) (match_dup 3))
5376 (set (match_dup 4) (match_dup 2))
5377 (set (match_dup 0) (float:DF (match_dup 4)))]
5378 "")
5380 (define_insn "fix_truncdfdi2"
5381 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5382 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5383 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5384 "fctidz %0,%1"
5385 [(set_attr "type" "fp")])
5387 (define_expand "floatdisf2"
5388 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5389 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5390 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5391 "
5392 {
5393 rtx val = operands[1];
5394 if (!flag_unsafe_math_optimizations)
5395 {
5396 rtx label = gen_label_rtx ();
5397 val = gen_reg_rtx (DImode);
5398 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5399 emit_label (label);
5400 }
5401 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5402 DONE;
5403 }")
5405 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5406 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5407 ;; from double rounding.
5408 (define_insn_and_split "floatdisf2_internal1"
5409 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5410 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5411 (clobber (match_scratch:DF 2 "=f"))]
5412 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5413 "#"
5414 "&& reload_completed"
5415 [(set (match_dup 2)
5416 (float:DF (match_dup 1)))
5417 (set (match_dup 0)
5418 (float_truncate:SF (match_dup 2)))]
5419 "")
5421 ;; Twiddles bits to avoid double rounding.
5422 ;; Bits that might be truncated when converting to DFmode are replaced
5423 ;; by a bit that won't be lost at that stage, but is below the SFmode
5424 ;; rounding position.
5425 (define_expand "floatdisf2_internal2"
5426 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5427 (const_int 53)))
5428 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5429 (const_int 2047)))
5430 (clobber (scratch:CC))])
5431 (set (match_dup 3) (plus:DI (match_dup 3)
5432 (const_int 1)))
5433 (set (match_dup 0) (plus:DI (match_dup 0)
5434 (const_int 2047)))
5435 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5436 (const_int 3)))
5437 (set (match_dup 0) (ior:DI (match_dup 0)
5438 (match_dup 1)))
5439 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5440 (const_int -2048)))
5441 (clobber (scratch:CC))])
5442 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5443 (label_ref (match_operand:DI 2 "" ""))
5444 (pc)))
5445 (set (match_dup 0) (match_dup 1))]
5446 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5447 "
5448 {
5449 operands[3] = gen_reg_rtx (DImode);
5450 operands[4] = gen_reg_rtx (CCUNSmode);
5451 }")
5452 \f
5453 ;; Define the DImode operations that can be done in a small number
5454 ;; of instructions. The & constraints are to prevent the register
5455 ;; allocator from allocating registers that overlap with the inputs
5456 ;; (for example, having an input in 7,8 and an output in 6,7). We
5457 ;; also allow for the output being the same as one of the inputs.
5459 (define_insn "*adddi3_noppc64"
5460 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5461 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5462 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5463 "! TARGET_POWERPC64"
5464 "*
5465 {
5466 if (WORDS_BIG_ENDIAN)
5467 return (GET_CODE (operands[2])) != CONST_INT
5468 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5469 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5470 else
5471 return (GET_CODE (operands[2])) != CONST_INT
5472 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5473 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5474 }"
5475 [(set_attr "type" "two")
5476 (set_attr "length" "8")])
5478 (define_insn "*subdi3_noppc64"
5479 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5480 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5481 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5482 "! TARGET_POWERPC64"
5483 "*
5484 {
5485 if (WORDS_BIG_ENDIAN)
5486 return (GET_CODE (operands[1]) != CONST_INT)
5487 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5488 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5489 else
5490 return (GET_CODE (operands[1]) != CONST_INT)
5491 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5492 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5493 }"
5494 [(set_attr "type" "two")
5495 (set_attr "length" "8")])
5497 (define_insn "*negdi2_noppc64"
5498 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5499 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5500 "! TARGET_POWERPC64"
5501 "*
5502 {
5503 return (WORDS_BIG_ENDIAN)
5504 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5505 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5506 }"
5507 [(set_attr "type" "two")
5508 (set_attr "length" "8")])
5510 (define_expand "mulsidi3"
5511 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5512 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5513 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5514 "! TARGET_POWERPC64"
5515 "
5516 {
5517 if (! TARGET_POWER && ! TARGET_POWERPC)
5518 {
5519 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5520 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5521 emit_insn (gen_mull_call ());
5522 if (WORDS_BIG_ENDIAN)
5523 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5524 else
5525 {
5526 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5527 gen_rtx_REG (SImode, 3));
5528 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5529 gen_rtx_REG (SImode, 4));
5530 }
5531 DONE;
5532 }
5533 else if (TARGET_POWER)
5534 {
5535 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5536 DONE;
5537 }
5538 }")
5540 (define_insn "mulsidi3_mq"
5541 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5542 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5543 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5544 (clobber (match_scratch:SI 3 "=q"))]
5545 "TARGET_POWER"
5546 "mul %0,%1,%2\;mfmq %L0"
5547 [(set_attr "type" "imul")
5548 (set_attr "length" "8")])
5550 (define_insn "*mulsidi3_no_mq"
5551 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5552 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5553 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5554 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5555 "*
5556 {
5557 return (WORDS_BIG_ENDIAN)
5558 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5559 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5560 }"
5561 [(set_attr "type" "imul")
5562 (set_attr "length" "8")])
5564 (define_split
5565 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5566 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5567 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5568 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5569 [(set (match_dup 3)
5570 (truncate:SI
5571 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5572 (sign_extend:DI (match_dup 2)))
5573 (const_int 32))))
5574 (set (match_dup 4)
5575 (mult:SI (match_dup 1)
5576 (match_dup 2)))]
5577 "
5578 {
5579 int endian = (WORDS_BIG_ENDIAN == 0);
5580 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5581 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5582 }")
5584 (define_expand "umulsidi3"
5585 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5586 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5587 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5588 "TARGET_POWERPC && ! TARGET_POWERPC64"
5589 "
5590 {
5591 if (TARGET_POWER)
5592 {
5593 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5594 DONE;
5595 }
5596 }")
5598 (define_insn "umulsidi3_mq"
5599 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5600 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5601 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5602 (clobber (match_scratch:SI 3 "=q"))]
5603 "TARGET_POWERPC && TARGET_POWER"
5604 "*
5605 {
5606 return (WORDS_BIG_ENDIAN)
5607 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5608 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5609 }"
5610 [(set_attr "type" "imul")
5611 (set_attr "length" "8")])
5613 (define_insn "*umulsidi3_no_mq"
5614 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5615 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5616 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5617 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5618 "*
5619 {
5620 return (WORDS_BIG_ENDIAN)
5621 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5622 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5623 }"
5624 [(set_attr "type" "imul")
5625 (set_attr "length" "8")])
5627 (define_split
5628 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5629 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5630 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5631 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5632 [(set (match_dup 3)
5633 (truncate:SI
5634 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5635 (zero_extend:DI (match_dup 2)))
5636 (const_int 32))))
5637 (set (match_dup 4)
5638 (mult:SI (match_dup 1)
5639 (match_dup 2)))]
5640 "
5641 {
5642 int endian = (WORDS_BIG_ENDIAN == 0);
5643 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5644 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5645 }")
5647 (define_expand "smulsi3_highpart"
5648 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5649 (truncate:SI
5650 (lshiftrt:DI (mult:DI (sign_extend:DI
5651 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5652 (sign_extend:DI
5653 (match_operand:SI 2 "gpc_reg_operand" "r")))
5654 (const_int 32))))]
5655 ""
5656 "
5657 {
5658 if (! TARGET_POWER && ! TARGET_POWERPC)
5659 {
5660 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5661 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5662 emit_insn (gen_mulh_call ());
5663 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5664 DONE;
5665 }
5666 else if (TARGET_POWER)
5667 {
5668 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5669 DONE;
5670 }
5671 }")
5673 (define_insn "smulsi3_highpart_mq"
5674 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5675 (truncate:SI
5676 (lshiftrt:DI (mult:DI (sign_extend:DI
5677 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5678 (sign_extend:DI
5679 (match_operand:SI 2 "gpc_reg_operand" "r")))
5680 (const_int 32))))
5681 (clobber (match_scratch:SI 3 "=q"))]
5682 "TARGET_POWER"
5683 "mul %0,%1,%2"
5684 [(set_attr "type" "imul")])
5686 (define_insn "*smulsi3_highpart_no_mq"
5687 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5688 (truncate:SI
5689 (lshiftrt:DI (mult:DI (sign_extend:DI
5690 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5691 (sign_extend:DI
5692 (match_operand:SI 2 "gpc_reg_operand" "r")))
5693 (const_int 32))))]
5694 "TARGET_POWERPC && ! TARGET_POWER"
5695 "mulhw %0,%1,%2"
5696 [(set_attr "type" "imul")])
5698 (define_expand "umulsi3_highpart"
5699 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5700 (truncate:SI
5701 (lshiftrt:DI (mult:DI (zero_extend:DI
5702 (match_operand:SI 1 "gpc_reg_operand" ""))
5703 (zero_extend:DI
5704 (match_operand:SI 2 "gpc_reg_operand" "")))
5705 (const_int 32))))]
5706 "TARGET_POWERPC"
5707 "
5708 {
5709 if (TARGET_POWER)
5710 {
5711 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5712 DONE;
5713 }
5714 }")
5716 (define_insn "umulsi3_highpart_mq"
5717 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5718 (truncate:SI
5719 (lshiftrt:DI (mult:DI (zero_extend:DI
5720 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5721 (zero_extend:DI
5722 (match_operand:SI 2 "gpc_reg_operand" "r")))
5723 (const_int 32))))
5724 (clobber (match_scratch:SI 3 "=q"))]
5725 "TARGET_POWERPC && TARGET_POWER"
5726 "mulhwu %0,%1,%2"
5727 [(set_attr "type" "imul")])
5729 (define_insn "*umulsi3_highpart_no_mq"
5730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5731 (truncate:SI
5732 (lshiftrt:DI (mult:DI (zero_extend:DI
5733 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5734 (zero_extend:DI
5735 (match_operand:SI 2 "gpc_reg_operand" "r")))
5736 (const_int 32))))]
5737 "TARGET_POWERPC && ! TARGET_POWER"
5738 "mulhwu %0,%1,%2"
5739 [(set_attr "type" "imul")])
5741 ;; If operands 0 and 2 are in the same register, we have a problem. But
5742 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5743 ;; why we have the strange constraints below.
5744 (define_insn "ashldi3_power"
5745 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5746 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5747 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5748 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5749 "TARGET_POWER"
5750 "@
5751 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5752 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5753 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5754 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5755 [(set_attr "length" "8")])
5757 (define_insn "lshrdi3_power"
5758 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5759 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5760 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5761 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5762 "TARGET_POWER"
5763 "@
5764 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5765 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5766 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5767 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5768 [(set_attr "length" "8")])
5770 ;; Shift by a variable amount is too complex to be worth open-coding. We
5771 ;; just handle shifts by constants.
5772 (define_insn "ashrdi3_power"
5773 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5774 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5775 (match_operand:SI 2 "const_int_operand" "M,i")))
5776 (clobber (match_scratch:SI 3 "=X,q"))]
5777 "TARGET_POWER"
5778 "@
5779 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5780 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5781 [(set_attr "length" "8")])
5783 (define_insn "ashrdi3_no_power"
5784 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5785 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5786 (match_operand:SI 2 "const_int_operand" "M,i")))]
5787 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5788 "@
5789 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5790 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5791 [(set_attr "type" "two,three")
5792 (set_attr "length" "8,12")])
5794 (define_insn "*ashrdisi3_noppc64"
5795 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5796 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5797 (const_int 32)) 4))]
5798 "TARGET_32BIT && !TARGET_POWERPC64"
5799 "*
5800 {
5801 if (REGNO (operands[0]) == REGNO (operands[1]))
5802 return \"\";
5803 else
5804 return \"mr %0,%1\";
5805 }"
5806 [(set_attr "length" "4")])
5808 \f
5809 ;; PowerPC64 DImode operations.
5811 (define_expand "adddi3"
5812 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5813 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5814 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5815 ""
5816 "
5817 {
5818 if (! TARGET_POWERPC64)
5819 {
5820 if (non_short_cint_operand (operands[2], DImode))
5821 FAIL;
5822 }
5823 else
5824 if (GET_CODE (operands[2]) == CONST_INT
5825 && ! add_operand (operands[2], DImode))
5826 {
5827 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5828 ? operands[0] : gen_reg_rtx (DImode));
5830 HOST_WIDE_INT val = INTVAL (operands[2]);
5831 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5832 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5834 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5835 FAIL;
5837 /* The ordering here is important for the prolog expander.
5838 When space is allocated from the stack, adding 'low' first may
5839 produce a temporary deallocation (which would be bad). */
5840 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5841 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5842 DONE;
5843 }
5844 }")
5846 ;; Discourage ai/addic because of carry but provide it in an alternative
5847 ;; allowing register zero as source.
5849 (define_insn "*adddi3_internal1"
5850 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5851 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5852 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5853 "TARGET_POWERPC64"
5854 "@
5855 add %0,%1,%2
5856 addi %0,%1,%2
5857 addic %0,%1,%2
5858 addis %0,%1,%v2")
5860 (define_insn "*adddi3_internal2"
5861 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5862 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5863 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5864 (const_int 0)))
5865 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5866 "TARGET_64BIT"
5867 "@
5868 add. %3,%1,%2
5869 addic. %3,%1,%2
5870 #
5871 #"
5872 [(set_attr "type" "fast_compare,compare,compare,compare")
5873 (set_attr "length" "4,4,8,8")])
5875 (define_split
5876 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5877 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5878 (match_operand:DI 2 "reg_or_short_operand" ""))
5879 (const_int 0)))
5880 (clobber (match_scratch:DI 3 ""))]
5881 "TARGET_POWERPC64 && reload_completed"
5882 [(set (match_dup 3)
5883 (plus:DI (match_dup 1) (match_dup 2)))
5884 (set (match_dup 0)
5885 (compare:CC (match_dup 3)
5886 (const_int 0)))]
5887 "")
5889 (define_insn "*adddi3_internal3"
5890 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5891 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5892 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5893 (const_int 0)))
5894 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5895 (plus:DI (match_dup 1) (match_dup 2)))]
5896 "TARGET_64BIT"
5897 "@
5898 add. %0,%1,%2
5899 addic. %0,%1,%2
5900 #
5901 #"
5902 [(set_attr "type" "fast_compare,compare,compare,compare")
5903 (set_attr "length" "4,4,8,8")])
5905 (define_split
5906 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5907 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5908 (match_operand:DI 2 "reg_or_short_operand" ""))
5909 (const_int 0)))
5910 (set (match_operand:DI 0 "gpc_reg_operand" "")
5911 (plus:DI (match_dup 1) (match_dup 2)))]
5912 "TARGET_POWERPC64 && reload_completed"
5913 [(set (match_dup 0)
5914 (plus:DI (match_dup 1) (match_dup 2)))
5915 (set (match_dup 3)
5916 (compare:CC (match_dup 0)
5917 (const_int 0)))]
5918 "")
5920 ;; Split an add that we can't do in one insn into two insns, each of which
5921 ;; does one 16-bit part. This is used by combine. Note that the low-order
5922 ;; add should be last in case the result gets used in an address.
5924 (define_split
5925 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5926 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5927 (match_operand:DI 2 "non_add_cint_operand" "")))]
5928 "TARGET_POWERPC64"
5929 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5930 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5931 "
5932 {
5933 HOST_WIDE_INT val = INTVAL (operands[2]);
5934 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5935 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5937 operands[4] = GEN_INT (low);
5938 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5939 operands[3] = GEN_INT (rest);
5940 else if (! no_new_pseudos)
5941 {
5942 operands[3] = gen_reg_rtx (DImode);
5943 emit_move_insn (operands[3], operands[2]);
5944 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5945 DONE;
5946 }
5947 else
5948 FAIL;
5949 }")
5951 (define_insn "one_cmpldi2"
5952 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5953 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5954 "TARGET_POWERPC64"
5955 "nor %0,%1,%1")
5957 (define_insn ""
5958 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5959 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5960 (const_int 0)))
5961 (clobber (match_scratch:DI 2 "=r,r"))]
5962 "TARGET_64BIT"
5963 "@
5964 nor. %2,%1,%1
5965 #"
5966 [(set_attr "type" "compare")
5967 (set_attr "length" "4,8")])
5969 (define_split
5970 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5971 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5972 (const_int 0)))
5973 (clobber (match_scratch:DI 2 ""))]
5974 "TARGET_POWERPC64 && reload_completed"
5975 [(set (match_dup 2)
5976 (not:DI (match_dup 1)))
5977 (set (match_dup 0)
5978 (compare:CC (match_dup 2)
5979 (const_int 0)))]
5980 "")
5982 (define_insn ""
5983 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5984 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5985 (const_int 0)))
5986 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5987 (not:DI (match_dup 1)))]
5988 "TARGET_64BIT"
5989 "@
5990 nor. %0,%1,%1
5991 #"
5992 [(set_attr "type" "compare")
5993 (set_attr "length" "4,8")])
5995 (define_split
5996 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5997 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5998 (const_int 0)))
5999 (set (match_operand:DI 0 "gpc_reg_operand" "")
6000 (not:DI (match_dup 1)))]
6001 "TARGET_POWERPC64 && reload_completed"
6002 [(set (match_dup 0)
6003 (not:DI (match_dup 1)))
6004 (set (match_dup 2)
6005 (compare:CC (match_dup 0)
6006 (const_int 0)))]
6007 "")
6009 (define_insn ""
6010 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6011 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
6012 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
6013 "TARGET_POWERPC64"
6014 "@
6015 subf %0,%2,%1
6016 subfic %0,%2,%1")
6018 (define_insn ""
6019 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6020 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6021 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6022 (const_int 0)))
6023 (clobber (match_scratch:DI 3 "=r,r"))]
6024 "TARGET_64BIT"
6025 "@
6026 subf. %3,%2,%1
6027 #"
6028 [(set_attr "type" "fast_compare")
6029 (set_attr "length" "4,8")])
6031 (define_split
6032 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6033 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6034 (match_operand:DI 2 "gpc_reg_operand" ""))
6035 (const_int 0)))
6036 (clobber (match_scratch:DI 3 ""))]
6037 "TARGET_POWERPC64 && reload_completed"
6038 [(set (match_dup 3)
6039 (minus:DI (match_dup 1) (match_dup 2)))
6040 (set (match_dup 0)
6041 (compare:CC (match_dup 3)
6042 (const_int 0)))]
6043 "")
6045 (define_insn ""
6046 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6047 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6048 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6049 (const_int 0)))
6050 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6051 (minus:DI (match_dup 1) (match_dup 2)))]
6052 "TARGET_64BIT"
6053 "@
6054 subf. %0,%2,%1
6055 #"
6056 [(set_attr "type" "fast_compare")
6057 (set_attr "length" "4,8")])
6059 (define_split
6060 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6061 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6062 (match_operand:DI 2 "gpc_reg_operand" ""))
6063 (const_int 0)))
6064 (set (match_operand:DI 0 "gpc_reg_operand" "")
6065 (minus:DI (match_dup 1) (match_dup 2)))]
6066 "TARGET_POWERPC64 && reload_completed"
6067 [(set (match_dup 0)
6068 (minus:DI (match_dup 1) (match_dup 2)))
6069 (set (match_dup 3)
6070 (compare:CC (match_dup 0)
6071 (const_int 0)))]
6072 "")
6074 (define_expand "subdi3"
6075 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6076 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
6077 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
6078 ""
6079 "
6080 {
6081 if (GET_CODE (operands[2]) == CONST_INT)
6082 {
6083 emit_insn (gen_adddi3 (operands[0], operands[1],
6084 negate_rtx (DImode, operands[2])));
6085 DONE;
6086 }
6087 }")
6089 (define_insn_and_split "absdi2"
6090 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6091 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6092 (clobber (match_scratch:DI 2 "=&r,&r"))]
6093 "TARGET_POWERPC64"
6094 "#"
6095 "&& reload_completed"
6096 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6097 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6098 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6099 "")
6101 (define_insn_and_split "*nabsdi2"
6102 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6103 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6104 (clobber (match_scratch:DI 2 "=&r,&r"))]
6105 "TARGET_POWERPC64"
6106 "#"
6107 "&& reload_completed"
6108 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6109 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6110 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6111 "")
6113 (define_expand "negdi2"
6114 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6115 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
6116 ""
6117 "")
6119 (define_insn ""
6120 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6121 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6122 "TARGET_POWERPC64"
6123 "neg %0,%1")
6125 (define_insn ""
6126 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6127 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6128 (const_int 0)))
6129 (clobber (match_scratch:DI 2 "=r,r"))]
6130 "TARGET_64BIT"
6131 "@
6132 neg. %2,%1
6133 #"
6134 [(set_attr "type" "fast_compare")
6135 (set_attr "length" "4,8")])
6137 (define_split
6138 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6139 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6140 (const_int 0)))
6141 (clobber (match_scratch:DI 2 ""))]
6142 "TARGET_POWERPC64 && reload_completed"
6143 [(set (match_dup 2)
6144 (neg:DI (match_dup 1)))
6145 (set (match_dup 0)
6146 (compare:CC (match_dup 2)
6147 (const_int 0)))]
6148 "")
6150 (define_insn ""
6151 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6152 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6153 (const_int 0)))
6154 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6155 (neg:DI (match_dup 1)))]
6156 "TARGET_64BIT"
6157 "@
6158 neg. %0,%1
6159 #"
6160 [(set_attr "type" "fast_compare")
6161 (set_attr "length" "4,8")])
6163 (define_split
6164 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6165 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6166 (const_int 0)))
6167 (set (match_operand:DI 0 "gpc_reg_operand" "")
6168 (neg:DI (match_dup 1)))]
6169 "TARGET_POWERPC64 && reload_completed"
6170 [(set (match_dup 0)
6171 (neg:DI (match_dup 1)))
6172 (set (match_dup 2)
6173 (compare:CC (match_dup 0)
6174 (const_int 0)))]
6175 "")
6177 (define_insn "clzdi2"
6178 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6179 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6180 "TARGET_POWERPC64"
6181 "cntlzd %0,%1")
6183 (define_expand "ctzdi2"
6184 [(set (match_dup 2)
6185 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6186 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6187 (match_dup 2)))
6188 (clobber (scratch:CC))])
6189 (set (match_dup 4) (clz:DI (match_dup 3)))
6190 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6191 (minus:DI (const_int 63) (match_dup 4)))]
6192 "TARGET_POWERPC64"
6193 {
6194 operands[2] = gen_reg_rtx (DImode);
6195 operands[3] = gen_reg_rtx (DImode);
6196 operands[4] = gen_reg_rtx (DImode);
6197 })
6199 (define_expand "ffsdi2"
6200 [(set (match_dup 2)
6201 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6202 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6203 (match_dup 2)))
6204 (clobber (scratch:CC))])
6205 (set (match_dup 4) (clz:DI (match_dup 3)))
6206 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6207 (minus:DI (const_int 64) (match_dup 4)))]
6208 "TARGET_POWERPC64"
6209 {
6210 operands[2] = gen_reg_rtx (DImode);
6211 operands[3] = gen_reg_rtx (DImode);
6212 operands[4] = gen_reg_rtx (DImode);
6213 })
6215 (define_insn "muldi3"
6216 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6217 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6218 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6219 "TARGET_POWERPC64"
6220 "mulld %0,%1,%2"
6221 [(set_attr "type" "lmul")])
6223 (define_insn "*muldi3_internal1"
6224 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6225 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6226 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6227 (const_int 0)))
6228 (clobber (match_scratch:DI 3 "=r,r"))]
6229 "TARGET_POWERPC64"
6230 "@
6231 mulld. %3,%1,%2
6232 #"
6233 [(set_attr "type" "lmul_compare")
6234 (set_attr "length" "4,8")])
6236 (define_split
6237 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6238 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6239 (match_operand:DI 2 "gpc_reg_operand" ""))
6240 (const_int 0)))
6241 (clobber (match_scratch:DI 3 ""))]
6242 "TARGET_POWERPC64 && reload_completed"
6243 [(set (match_dup 3)
6244 (mult:DI (match_dup 1) (match_dup 2)))
6245 (set (match_dup 0)
6246 (compare:CC (match_dup 3)
6247 (const_int 0)))]
6248 "")
6250 (define_insn "*muldi3_internal2"
6251 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6252 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6253 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6254 (const_int 0)))
6255 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6256 (mult:DI (match_dup 1) (match_dup 2)))]
6257 "TARGET_POWERPC64"
6258 "@
6259 mulld. %0,%1,%2
6260 #"
6261 [(set_attr "type" "lmul_compare")
6262 (set_attr "length" "4,8")])
6264 (define_split
6265 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6266 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6267 (match_operand:DI 2 "gpc_reg_operand" ""))
6268 (const_int 0)))
6269 (set (match_operand:DI 0 "gpc_reg_operand" "")
6270 (mult:DI (match_dup 1) (match_dup 2)))]
6271 "TARGET_POWERPC64 && reload_completed"
6272 [(set (match_dup 0)
6273 (mult:DI (match_dup 1) (match_dup 2)))
6274 (set (match_dup 3)
6275 (compare:CC (match_dup 0)
6276 (const_int 0)))]
6277 "")
6279 (define_insn "smuldi3_highpart"
6280 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6281 (truncate:DI
6282 (lshiftrt:TI (mult:TI (sign_extend:TI
6283 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6284 (sign_extend:TI
6285 (match_operand:DI 2 "gpc_reg_operand" "r")))
6286 (const_int 64))))]
6287 "TARGET_POWERPC64"
6288 "mulhd %0,%1,%2"
6289 [(set_attr "type" "lmul")])
6291 (define_insn "umuldi3_highpart"
6292 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6293 (truncate:DI
6294 (lshiftrt:TI (mult:TI (zero_extend:TI
6295 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6296 (zero_extend:TI
6297 (match_operand:DI 2 "gpc_reg_operand" "r")))
6298 (const_int 64))))]
6299 "TARGET_POWERPC64"
6300 "mulhdu %0,%1,%2"
6301 [(set_attr "type" "lmul")])
6303 (define_expand "divdi3"
6304 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6305 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6306 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6307 "TARGET_POWERPC64"
6308 "
6309 {
6310 if (GET_CODE (operands[2]) == CONST_INT
6311 && INTVAL (operands[2]) > 0
6312 && exact_log2 (INTVAL (operands[2])) >= 0)
6313 ;
6314 else
6315 operands[2] = force_reg (DImode, operands[2]);
6316 }")
6318 (define_expand "moddi3"
6319 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6320 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6321 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6322 "TARGET_POWERPC64"
6323 "
6324 {
6325 int i;
6326 rtx temp1;
6327 rtx temp2;
6329 if (GET_CODE (operands[2]) != CONST_INT
6330 || INTVAL (operands[2]) <= 0
6331 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6332 FAIL;
6334 temp1 = gen_reg_rtx (DImode);
6335 temp2 = gen_reg_rtx (DImode);
6337 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6338 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6339 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6340 DONE;
6341 }")
6343 (define_insn ""
6344 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6345 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6346 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6347 "TARGET_POWERPC64"
6348 "sradi %0,%1,%p2\;addze %0,%0"
6349 [(set_attr "type" "two")
6350 (set_attr "length" "8")])
6352 (define_insn ""
6353 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6354 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6355 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6356 (const_int 0)))
6357 (clobber (match_scratch:DI 3 "=r,r"))]
6358 "TARGET_64BIT"
6359 "@
6360 sradi %3,%1,%p2\;addze. %3,%3
6361 #"
6362 [(set_attr "type" "compare")
6363 (set_attr "length" "8,12")])
6365 (define_split
6366 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6367 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6368 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6369 (const_int 0)))
6370 (clobber (match_scratch:DI 3 ""))]
6371 "TARGET_POWERPC64 && reload_completed"
6372 [(set (match_dup 3)
6373 (div:DI (match_dup 1) (match_dup 2)))
6374 (set (match_dup 0)
6375 (compare:CC (match_dup 3)
6376 (const_int 0)))]
6377 "")
6379 (define_insn ""
6380 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6381 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6382 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6383 (const_int 0)))
6384 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6385 (div:DI (match_dup 1) (match_dup 2)))]
6386 "TARGET_64BIT"
6387 "@
6388 sradi %0,%1,%p2\;addze. %0,%0
6389 #"
6390 [(set_attr "type" "compare")
6391 (set_attr "length" "8,12")])
6393 (define_split
6394 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6395 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6396 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6397 (const_int 0)))
6398 (set (match_operand:DI 0 "gpc_reg_operand" "")
6399 (div:DI (match_dup 1) (match_dup 2)))]
6400 "TARGET_POWERPC64 && reload_completed"
6401 [(set (match_dup 0)
6402 (div:DI (match_dup 1) (match_dup 2)))
6403 (set (match_dup 3)
6404 (compare:CC (match_dup 0)
6405 (const_int 0)))]
6406 "")
6408 (define_insn ""
6409 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6410 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6411 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6412 "TARGET_POWERPC64"
6413 "divd %0,%1,%2"
6414 [(set_attr "type" "ldiv")])
6416 (define_insn "udivdi3"
6417 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6418 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6419 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6420 "TARGET_POWERPC64"
6421 "divdu %0,%1,%2"
6422 [(set_attr "type" "ldiv")])
6424 (define_insn "rotldi3"
6425 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6426 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6427 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6428 "TARGET_POWERPC64"
6429 "rld%I2cl %0,%1,%H2,0")
6431 (define_insn "*rotldi3_internal2"
6432 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6433 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6434 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6435 (const_int 0)))
6436 (clobber (match_scratch:DI 3 "=r,r"))]
6437 "TARGET_64BIT"
6438 "@
6439 rld%I2cl. %3,%1,%H2,0
6440 #"
6441 [(set_attr "type" "delayed_compare")
6442 (set_attr "length" "4,8")])
6444 (define_split
6445 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6446 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6447 (match_operand:DI 2 "reg_or_cint_operand" ""))
6448 (const_int 0)))
6449 (clobber (match_scratch:DI 3 ""))]
6450 "TARGET_POWERPC64 && reload_completed"
6451 [(set (match_dup 3)
6452 (rotate:DI (match_dup 1) (match_dup 2)))
6453 (set (match_dup 0)
6454 (compare:CC (match_dup 3)
6455 (const_int 0)))]
6456 "")
6458 (define_insn "*rotldi3_internal3"
6459 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6460 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6461 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6462 (const_int 0)))
6463 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6464 (rotate:DI (match_dup 1) (match_dup 2)))]
6465 "TARGET_64BIT"
6466 "@
6467 rld%I2cl. %0,%1,%H2,0
6468 #"
6469 [(set_attr "type" "delayed_compare")
6470 (set_attr "length" "4,8")])
6472 (define_split
6473 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6474 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6475 (match_operand:DI 2 "reg_or_cint_operand" ""))
6476 (const_int 0)))
6477 (set (match_operand:DI 0 "gpc_reg_operand" "")
6478 (rotate:DI (match_dup 1) (match_dup 2)))]
6479 "TARGET_POWERPC64 && reload_completed"
6480 [(set (match_dup 0)
6481 (rotate:DI (match_dup 1) (match_dup 2)))
6482 (set (match_dup 3)
6483 (compare:CC (match_dup 0)
6484 (const_int 0)))]
6485 "")
6487 (define_insn "*rotldi3_internal4"
6488 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6489 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6490 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6491 (match_operand:DI 3 "mask64_operand" "n")))]
6492 "TARGET_POWERPC64"
6493 "rld%I2c%B3 %0,%1,%H2,%S3")
6495 (define_insn "*rotldi3_internal5"
6496 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6497 (compare:CC (and:DI
6498 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6499 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6500 (match_operand:DI 3 "mask64_operand" "n,n"))
6501 (const_int 0)))
6502 (clobber (match_scratch:DI 4 "=r,r"))]
6503 "TARGET_64BIT"
6504 "@
6505 rld%I2c%B3. %4,%1,%H2,%S3
6506 #"
6507 [(set_attr "type" "delayed_compare")
6508 (set_attr "length" "4,8")])
6510 (define_split
6511 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6512 (compare:CC (and:DI
6513 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6514 (match_operand:DI 2 "reg_or_cint_operand" ""))
6515 (match_operand:DI 3 "mask64_operand" ""))
6516 (const_int 0)))
6517 (clobber (match_scratch:DI 4 ""))]
6518 "TARGET_POWERPC64 && reload_completed"
6519 [(set (match_dup 4)
6520 (and:DI (rotate:DI (match_dup 1)
6521 (match_dup 2))
6522 (match_dup 3)))
6523 (set (match_dup 0)
6524 (compare:CC (match_dup 4)
6525 (const_int 0)))]
6526 "")
6528 (define_insn "*rotldi3_internal6"
6529 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6530 (compare:CC (and:DI
6531 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6532 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6533 (match_operand:DI 3 "mask64_operand" "n,n"))
6534 (const_int 0)))
6535 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6536 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6537 "TARGET_64BIT"
6538 "@
6539 rld%I2c%B3. %0,%1,%H2,%S3
6540 #"
6541 [(set_attr "type" "delayed_compare")
6542 (set_attr "length" "4,8")])
6544 (define_split
6545 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6546 (compare:CC (and:DI
6547 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6548 (match_operand:DI 2 "reg_or_cint_operand" ""))
6549 (match_operand:DI 3 "mask64_operand" ""))
6550 (const_int 0)))
6551 (set (match_operand:DI 0 "gpc_reg_operand" "")
6552 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6553 "TARGET_POWERPC64 && reload_completed"
6554 [(set (match_dup 0)
6555 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6556 (set (match_dup 4)
6557 (compare:CC (match_dup 0)
6558 (const_int 0)))]
6559 "")
6561 (define_insn "*rotldi3_internal7"
6562 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6563 (zero_extend:DI
6564 (subreg:QI
6565 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6566 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6567 "TARGET_POWERPC64"
6568 "rld%I2cl %0,%1,%H2,56")
6570 (define_insn "*rotldi3_internal8"
6571 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6572 (compare:CC (zero_extend:DI
6573 (subreg:QI
6574 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6575 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6576 (const_int 0)))
6577 (clobber (match_scratch:DI 3 "=r,r"))]
6578 "TARGET_64BIT"
6579 "@
6580 rld%I2cl. %3,%1,%H2,56
6581 #"
6582 [(set_attr "type" "delayed_compare")
6583 (set_attr "length" "4,8")])
6585 (define_split
6586 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6587 (compare:CC (zero_extend:DI
6588 (subreg:QI
6589 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6590 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6591 (const_int 0)))
6592 (clobber (match_scratch:DI 3 ""))]
6593 "TARGET_POWERPC64 && reload_completed"
6594 [(set (match_dup 3)
6595 (zero_extend:DI (subreg:QI
6596 (rotate:DI (match_dup 1)
6597 (match_dup 2)) 0)))
6598 (set (match_dup 0)
6599 (compare:CC (match_dup 3)
6600 (const_int 0)))]
6601 "")
6603 (define_insn "*rotldi3_internal9"
6604 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6605 (compare:CC (zero_extend:DI
6606 (subreg:QI
6607 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6608 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6609 (const_int 0)))
6610 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6611 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6612 "TARGET_64BIT"
6613 "@
6614 rld%I2cl. %0,%1,%H2,56
6615 #"
6616 [(set_attr "type" "delayed_compare")
6617 (set_attr "length" "4,8")])
6619 (define_split
6620 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6621 (compare:CC (zero_extend:DI
6622 (subreg:QI
6623 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6624 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6625 (const_int 0)))
6626 (set (match_operand:DI 0 "gpc_reg_operand" "")
6627 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6628 "TARGET_POWERPC64 && reload_completed"
6629 [(set (match_dup 0)
6630 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6631 (set (match_dup 3)
6632 (compare:CC (match_dup 0)
6633 (const_int 0)))]
6634 "")
6636 (define_insn "*rotldi3_internal10"
6637 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6638 (zero_extend:DI
6639 (subreg:HI
6640 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6641 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6642 "TARGET_POWERPC64"
6643 "rld%I2cl %0,%1,%H2,48")
6645 (define_insn "*rotldi3_internal11"
6646 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6647 (compare:CC (zero_extend:DI
6648 (subreg:HI
6649 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6650 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6651 (const_int 0)))
6652 (clobber (match_scratch:DI 3 "=r,r"))]
6653 "TARGET_64BIT"
6654 "@
6655 rld%I2cl. %3,%1,%H2,48
6656 #"
6657 [(set_attr "type" "delayed_compare")
6658 (set_attr "length" "4,8")])
6660 (define_split
6661 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6662 (compare:CC (zero_extend:DI
6663 (subreg:HI
6664 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6665 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6666 (const_int 0)))
6667 (clobber (match_scratch:DI 3 ""))]
6668 "TARGET_POWERPC64 && reload_completed"
6669 [(set (match_dup 3)
6670 (zero_extend:DI (subreg:HI
6671 (rotate:DI (match_dup 1)
6672 (match_dup 2)) 0)))
6673 (set (match_dup 0)
6674 (compare:CC (match_dup 3)
6675 (const_int 0)))]
6676 "")
6678 (define_insn "*rotldi3_internal12"
6679 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6680 (compare:CC (zero_extend:DI
6681 (subreg:HI
6682 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6683 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6684 (const_int 0)))
6685 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6686 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6687 "TARGET_64BIT"
6688 "@
6689 rld%I2cl. %0,%1,%H2,48
6690 #"
6691 [(set_attr "type" "delayed_compare")
6692 (set_attr "length" "4,8")])
6694 (define_split
6695 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6696 (compare:CC (zero_extend:DI
6697 (subreg:HI
6698 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6699 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6700 (const_int 0)))
6701 (set (match_operand:DI 0 "gpc_reg_operand" "")
6702 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6703 "TARGET_POWERPC64 && reload_completed"
6704 [(set (match_dup 0)
6705 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6706 (set (match_dup 3)
6707 (compare:CC (match_dup 0)
6708 (const_int 0)))]
6709 "")
6711 (define_insn "*rotldi3_internal13"
6712 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6713 (zero_extend:DI
6714 (subreg:SI
6715 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6716 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6717 "TARGET_POWERPC64"
6718 "rld%I2cl %0,%1,%H2,32")
6720 (define_insn "*rotldi3_internal14"
6721 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6722 (compare:CC (zero_extend:DI
6723 (subreg:SI
6724 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6725 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6726 (const_int 0)))
6727 (clobber (match_scratch:DI 3 "=r,r"))]
6728 "TARGET_64BIT"
6729 "@
6730 rld%I2cl. %3,%1,%H2,32
6731 #"
6732 [(set_attr "type" "delayed_compare")
6733 (set_attr "length" "4,8")])
6735 (define_split
6736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6737 (compare:CC (zero_extend:DI
6738 (subreg:SI
6739 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6740 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6741 (const_int 0)))
6742 (clobber (match_scratch:DI 3 ""))]
6743 "TARGET_POWERPC64 && reload_completed"
6744 [(set (match_dup 3)
6745 (zero_extend:DI (subreg:SI
6746 (rotate:DI (match_dup 1)
6747 (match_dup 2)) 0)))
6748 (set (match_dup 0)
6749 (compare:CC (match_dup 3)
6750 (const_int 0)))]
6751 "")
6753 (define_insn "*rotldi3_internal15"
6754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6755 (compare:CC (zero_extend:DI
6756 (subreg:SI
6757 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6758 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6759 (const_int 0)))
6760 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6761 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6762 "TARGET_64BIT"
6763 "@
6764 rld%I2cl. %0,%1,%H2,32
6765 #"
6766 [(set_attr "type" "delayed_compare")
6767 (set_attr "length" "4,8")])
6769 (define_split
6770 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6771 (compare:CC (zero_extend:DI
6772 (subreg:SI
6773 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6774 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6775 (const_int 0)))
6776 (set (match_operand:DI 0 "gpc_reg_operand" "")
6777 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6778 "TARGET_POWERPC64 && reload_completed"
6779 [(set (match_dup 0)
6780 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6781 (set (match_dup 3)
6782 (compare:CC (match_dup 0)
6783 (const_int 0)))]
6784 "")
6786 (define_expand "ashldi3"
6787 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6788 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6789 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6790 "TARGET_POWERPC64 || TARGET_POWER"
6791 "
6792 {
6793 if (TARGET_POWERPC64)
6794 ;
6795 else if (TARGET_POWER)
6796 {
6797 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6798 DONE;
6799 }
6800 else
6801 FAIL;
6802 }")
6804 (define_insn "*ashldi3_internal1"
6805 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6806 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6807 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6808 "TARGET_POWERPC64"
6809 "sld%I2 %0,%1,%H2")
6811 (define_insn "*ashldi3_internal2"
6812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6813 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6814 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6815 (const_int 0)))
6816 (clobber (match_scratch:DI 3 "=r,r"))]
6817 "TARGET_64BIT"
6818 "@
6819 sld%I2. %3,%1,%H2
6820 #"
6821 [(set_attr "type" "delayed_compare")
6822 (set_attr "length" "4,8")])
6824 (define_split
6825 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6826 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6827 (match_operand:SI 2 "reg_or_cint_operand" ""))
6828 (const_int 0)))
6829 (clobber (match_scratch:DI 3 ""))]
6830 "TARGET_POWERPC64 && reload_completed"
6831 [(set (match_dup 3)
6832 (ashift:DI (match_dup 1) (match_dup 2)))
6833 (set (match_dup 0)
6834 (compare:CC (match_dup 3)
6835 (const_int 0)))]
6836 "")
6838 (define_insn "*ashldi3_internal3"
6839 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6840 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6841 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6842 (const_int 0)))
6843 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6844 (ashift:DI (match_dup 1) (match_dup 2)))]
6845 "TARGET_64BIT"
6846 "@
6847 sld%I2. %0,%1,%H2
6848 #"
6849 [(set_attr "type" "delayed_compare")
6850 (set_attr "length" "4,8")])
6852 (define_split
6853 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6854 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6855 (match_operand:SI 2 "reg_or_cint_operand" ""))
6856 (const_int 0)))
6857 (set (match_operand:DI 0 "gpc_reg_operand" "")
6858 (ashift:DI (match_dup 1) (match_dup 2)))]
6859 "TARGET_POWERPC64 && reload_completed"
6860 [(set (match_dup 0)
6861 (ashift:DI (match_dup 1) (match_dup 2)))
6862 (set (match_dup 3)
6863 (compare:CC (match_dup 0)
6864 (const_int 0)))]
6865 "")
6867 (define_insn "*ashldi3_internal4"
6868 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6869 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6870 (match_operand:SI 2 "const_int_operand" "i"))
6871 (match_operand:DI 3 "const_int_operand" "n")))]
6872 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6873 "rldic %0,%1,%H2,%W3")
6875 (define_insn "ashldi3_internal5"
6876 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6877 (compare:CC
6878 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6879 (match_operand:SI 2 "const_int_operand" "i,i"))
6880 (match_operand:DI 3 "const_int_operand" "n,n"))
6881 (const_int 0)))
6882 (clobber (match_scratch:DI 4 "=r,r"))]
6883 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6884 "@
6885 rldic. %4,%1,%H2,%W3
6886 #"
6887 [(set_attr "type" "delayed_compare")
6888 (set_attr "length" "4,8")])
6890 (define_split
6891 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6892 (compare:CC
6893 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6894 (match_operand:SI 2 "const_int_operand" ""))
6895 (match_operand:DI 3 "const_int_operand" ""))
6896 (const_int 0)))
6897 (clobber (match_scratch:DI 4 ""))]
6898 "TARGET_POWERPC64 && reload_completed
6899 && includes_rldic_lshift_p (operands[2], operands[3])"
6900 [(set (match_dup 4)
6901 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6902 (match_dup 3)))
6903 (set (match_dup 0)
6904 (compare:CC (match_dup 4)
6905 (const_int 0)))]
6906 "")
6908 (define_insn "*ashldi3_internal6"
6909 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6910 (compare:CC
6911 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6912 (match_operand:SI 2 "const_int_operand" "i,i"))
6913 (match_operand:DI 3 "const_int_operand" "n,n"))
6914 (const_int 0)))
6915 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6916 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6917 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6918 "@
6919 rldic. %0,%1,%H2,%W3
6920 #"
6921 [(set_attr "type" "delayed_compare")
6922 (set_attr "length" "4,8")])
6924 (define_split
6925 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6926 (compare:CC
6927 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6928 (match_operand:SI 2 "const_int_operand" ""))
6929 (match_operand:DI 3 "const_int_operand" ""))
6930 (const_int 0)))
6931 (set (match_operand:DI 0 "gpc_reg_operand" "")
6932 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6933 "TARGET_POWERPC64 && reload_completed
6934 && includes_rldic_lshift_p (operands[2], operands[3])"
6935 [(set (match_dup 0)
6936 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6937 (match_dup 3)))
6938 (set (match_dup 4)
6939 (compare:CC (match_dup 0)
6940 (const_int 0)))]
6941 "")
6943 (define_insn "*ashldi3_internal7"
6944 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6945 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6946 (match_operand:SI 2 "const_int_operand" "i"))
6947 (match_operand:DI 3 "mask64_operand" "n")))]
6948 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6949 "rldicr %0,%1,%H2,%S3")
6951 (define_insn "ashldi3_internal8"
6952 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6953 (compare:CC
6954 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6955 (match_operand:SI 2 "const_int_operand" "i,i"))
6956 (match_operand:DI 3 "mask64_operand" "n,n"))
6957 (const_int 0)))
6958 (clobber (match_scratch:DI 4 "=r,r"))]
6959 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6960 "@
6961 rldicr. %4,%1,%H2,%S3
6962 #"
6963 [(set_attr "type" "delayed_compare")
6964 (set_attr "length" "4,8")])
6966 (define_split
6967 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6968 (compare:CC
6969 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6970 (match_operand:SI 2 "const_int_operand" ""))
6971 (match_operand:DI 3 "mask64_operand" ""))
6972 (const_int 0)))
6973 (clobber (match_scratch:DI 4 ""))]
6974 "TARGET_POWERPC64 && reload_completed
6975 && includes_rldicr_lshift_p (operands[2], operands[3])"
6976 [(set (match_dup 4)
6977 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6978 (match_dup 3)))
6979 (set (match_dup 0)
6980 (compare:CC (match_dup 4)
6981 (const_int 0)))]
6982 "")
6984 (define_insn "*ashldi3_internal9"
6985 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6986 (compare:CC
6987 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6988 (match_operand:SI 2 "const_int_operand" "i,i"))
6989 (match_operand:DI 3 "mask64_operand" "n,n"))
6990 (const_int 0)))
6991 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6992 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6993 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6994 "@
6995 rldicr. %0,%1,%H2,%S3
6996 #"
6997 [(set_attr "type" "delayed_compare")
6998 (set_attr "length" "4,8")])
7000 (define_split
7001 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7002 (compare:CC
7003 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7004 (match_operand:SI 2 "const_int_operand" ""))
7005 (match_operand:DI 3 "mask64_operand" ""))
7006 (const_int 0)))
7007 (set (match_operand:DI 0 "gpc_reg_operand" "")
7008 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7009 "TARGET_POWERPC64 && reload_completed
7010 && includes_rldicr_lshift_p (operands[2], operands[3])"
7011 [(set (match_dup 0)
7012 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7013 (match_dup 3)))
7014 (set (match_dup 4)
7015 (compare:CC (match_dup 0)
7016 (const_int 0)))]
7017 "")
7019 (define_expand "lshrdi3"
7020 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7021 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7022 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7023 "TARGET_POWERPC64 || TARGET_POWER"
7024 "
7025 {
7026 if (TARGET_POWERPC64)
7027 ;
7028 else if (TARGET_POWER)
7029 {
7030 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7031 DONE;
7032 }
7033 else
7034 FAIL;
7035 }")
7037 (define_insn "*lshrdi3_internal1"
7038 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7039 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7040 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7041 "TARGET_POWERPC64"
7042 "srd%I2 %0,%1,%H2")
7044 (define_insn "*lshrdi3_internal2"
7045 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7046 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7047 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7048 (const_int 0)))
7049 (clobber (match_scratch:DI 3 "=r,r"))]
7050 "TARGET_64BIT "
7051 "@
7052 srd%I2. %3,%1,%H2
7053 #"
7054 [(set_attr "type" "delayed_compare")
7055 (set_attr "length" "4,8")])
7057 (define_split
7058 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7059 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7060 (match_operand:SI 2 "reg_or_cint_operand" ""))
7061 (const_int 0)))
7062 (clobber (match_scratch:DI 3 ""))]
7063 "TARGET_POWERPC64 && reload_completed"
7064 [(set (match_dup 3)
7065 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7066 (set (match_dup 0)
7067 (compare:CC (match_dup 3)
7068 (const_int 0)))]
7069 "")
7071 (define_insn "*lshrdi3_internal3"
7072 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7073 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7074 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7075 (const_int 0)))
7076 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7077 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7078 "TARGET_64BIT"
7079 "@
7080 srd%I2. %0,%1,%H2
7081 #"
7082 [(set_attr "type" "delayed_compare")
7083 (set_attr "length" "4,8")])
7085 (define_split
7086 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7087 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7088 (match_operand:SI 2 "reg_or_cint_operand" ""))
7089 (const_int 0)))
7090 (set (match_operand:DI 0 "gpc_reg_operand" "")
7091 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7092 "TARGET_POWERPC64 && reload_completed"
7093 [(set (match_dup 0)
7094 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7095 (set (match_dup 3)
7096 (compare:CC (match_dup 0)
7097 (const_int 0)))]
7098 "")
7100 (define_expand "ashrdi3"
7101 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7102 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7103 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7104 "WORDS_BIG_ENDIAN"
7105 "
7106 {
7107 if (TARGET_POWERPC64)
7108 ;
7109 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7110 {
7111 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7112 DONE;
7113 }
7114 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7115 && WORDS_BIG_ENDIAN)
7116 {
7117 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7118 DONE;
7119 }
7120 else
7121 FAIL;
7122 }")
7124 (define_insn "*ashrdi3_internal1"
7125 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7126 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7127 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7128 "TARGET_POWERPC64"
7129 "srad%I2 %0,%1,%H2")
7131 (define_insn "*ashrdi3_internal2"
7132 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7133 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7134 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7135 (const_int 0)))
7136 (clobber (match_scratch:DI 3 "=r,r"))]
7137 "TARGET_64BIT"
7138 "@
7139 srad%I2. %3,%1,%H2
7140 #"
7141 [(set_attr "type" "delayed_compare")
7142 (set_attr "length" "4,8")])
7144 (define_split
7145 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7146 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7147 (match_operand:SI 2 "reg_or_cint_operand" ""))
7148 (const_int 0)))
7149 (clobber (match_scratch:DI 3 ""))]
7150 "TARGET_POWERPC64 && reload_completed"
7151 [(set (match_dup 3)
7152 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7153 (set (match_dup 0)
7154 (compare:CC (match_dup 3)
7155 (const_int 0)))]
7156 "")
7158 (define_insn "*ashrdi3_internal3"
7159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7160 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7161 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7162 (const_int 0)))
7163 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7164 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7165 "TARGET_64BIT"
7166 "@
7167 srad%I2. %0,%1,%H2
7168 #"
7169 [(set_attr "type" "delayed_compare")
7170 (set_attr "length" "4,8")])
7172 (define_split
7173 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7174 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7175 (match_operand:SI 2 "reg_or_cint_operand" ""))
7176 (const_int 0)))
7177 (set (match_operand:DI 0 "gpc_reg_operand" "")
7178 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7179 "TARGET_POWERPC64 && reload_completed"
7180 [(set (match_dup 0)
7181 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7182 (set (match_dup 3)
7183 (compare:CC (match_dup 0)
7184 (const_int 0)))]
7185 "")
7187 (define_insn "anddi3"
7188 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7189 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7190 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7191 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7192 "TARGET_POWERPC64"
7193 "@
7194 and %0,%1,%2
7195 rldic%B2 %0,%1,0,%S2
7196 rlwinm %0,%1,0,%m2,%M2
7197 andi. %0,%1,%b2
7198 andis. %0,%1,%u2
7199 #"
7200 [(set_attr "type" "*,*,*,compare,compare,*")
7201 (set_attr "length" "4,4,4,4,4,8")])
7203 (define_split
7204 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7205 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7206 (match_operand:DI 2 "mask64_2_operand" "")))
7207 (clobber (match_scratch:CC 3 ""))]
7208 "TARGET_POWERPC64
7209 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7210 && !mask64_operand (operands[2], DImode)"
7211 [(set (match_dup 0)
7212 (and:DI (rotate:DI (match_dup 1)
7213 (match_dup 4))
7214 (match_dup 5)))
7215 (set (match_dup 0)
7216 (and:DI (rotate:DI (match_dup 0)
7217 (match_dup 6))
7218 (match_dup 7)))]
7219 {
7220 build_mask64_2_operands (operands[2], &operands[4]);
7221 })
7223 (define_insn "*anddi3_internal2"
7224 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7225 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7226 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7227 (const_int 0)))
7228 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7229 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7230 "TARGET_64BIT"
7231 "@
7232 and. %3,%1,%2
7233 rldic%B2. %3,%1,0,%S2
7234 andi. %3,%1,%b2
7235 andis. %3,%1,%u2
7236 #
7237 #
7238 #
7239 #
7240 #
7241 #"
7242 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7243 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7245 (define_split
7246 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7247 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7248 (match_operand:DI 2 "and64_operand" ""))
7249 (const_int 0)))
7250 (clobber (match_scratch:DI 3 ""))
7251 (clobber (match_scratch:CC 4 ""))]
7252 "TARGET_POWERPC64 && reload_completed"
7253 [(parallel [(set (match_dup 3)
7254 (and:DI (match_dup 1)
7255 (match_dup 2)))
7256 (clobber (match_dup 4))])
7257 (set (match_dup 0)
7258 (compare:CC (match_dup 3)
7259 (const_int 0)))]
7260 "")
7262 (define_split
7263 [(set (match_operand:CC 0 "cc_reg_operand" "")
7264 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7265 (match_operand:DI 2 "mask64_2_operand" ""))
7266 (const_int 0)))
7267 (clobber (match_scratch:DI 3 ""))
7268 (clobber (match_scratch:CC 4 ""))]
7269 "TARGET_POWERPC64 && reload_completed
7270 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7271 && !mask64_operand (operands[2], DImode)"
7272 [(set (match_dup 3)
7273 (and:DI (rotate:DI (match_dup 1)
7274 (match_dup 5))
7275 (match_dup 6)))
7276 (parallel [(set (match_dup 0)
7277 (compare:CC (and:DI (rotate:DI (match_dup 3)
7278 (match_dup 7))
7279 (match_dup 8))
7280 (const_int 0)))
7281 (clobber (match_dup 3))])]
7282 "
7283 {
7284 build_mask64_2_operands (operands[2], &operands[5]);
7285 }")
7287 (define_insn "*anddi3_internal3"
7288 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7289 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7290 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7291 (const_int 0)))
7292 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7293 (and:DI (match_dup 1) (match_dup 2)))
7294 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7295 "TARGET_64BIT"
7296 "@
7297 and. %0,%1,%2
7298 rldic%B2. %0,%1,0,%S2
7299 andi. %0,%1,%b2
7300 andis. %0,%1,%u2
7301 #
7302 #
7303 #
7304 #
7305 #
7306 #"
7307 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7308 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7310 (define_split
7311 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7312 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7313 (match_operand:DI 2 "and64_operand" ""))
7314 (const_int 0)))
7315 (set (match_operand:DI 0 "gpc_reg_operand" "")
7316 (and:DI (match_dup 1) (match_dup 2)))
7317 (clobber (match_scratch:CC 4 ""))]
7318 "TARGET_POWERPC64 && reload_completed"
7319 [(parallel [(set (match_dup 0)
7320 (and:DI (match_dup 1) (match_dup 2)))
7321 (clobber (match_dup 4))])
7322 (set (match_dup 3)
7323 (compare:CC (match_dup 0)
7324 (const_int 0)))]
7325 "")
7327 (define_split
7328 [(set (match_operand:CC 3 "cc_reg_operand" "")
7329 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7330 (match_operand:DI 2 "mask64_2_operand" ""))
7331 (const_int 0)))
7332 (set (match_operand:DI 0 "gpc_reg_operand" "")
7333 (and:DI (match_dup 1) (match_dup 2)))
7334 (clobber (match_scratch:CC 4 ""))]
7335 "TARGET_POWERPC64 && reload_completed
7336 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7337 && !mask64_operand (operands[2], DImode)"
7338 [(set (match_dup 0)
7339 (and:DI (rotate:DI (match_dup 1)
7340 (match_dup 5))
7341 (match_dup 6)))
7342 (parallel [(set (match_dup 3)
7343 (compare:CC (and:DI (rotate:DI (match_dup 0)
7344 (match_dup 7))
7345 (match_dup 8))
7346 (const_int 0)))
7347 (set (match_dup 0)
7348 (and:DI (rotate:DI (match_dup 0)
7349 (match_dup 7))
7350 (match_dup 8)))])]
7351 "
7352 {
7353 build_mask64_2_operands (operands[2], &operands[5]);
7354 }")
7356 (define_expand "iordi3"
7357 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7358 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7359 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7360 "TARGET_POWERPC64"
7361 "
7362 {
7363 if (non_logical_cint_operand (operands[2], DImode))
7364 {
7365 HOST_WIDE_INT value;
7366 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7367 ? operands[0] : gen_reg_rtx (DImode));
7369 if (GET_CODE (operands[2]) == CONST_INT)
7370 {
7371 value = INTVAL (operands[2]);
7372 emit_insn (gen_iordi3 (tmp, operands[1],
7373 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7374 }
7375 else
7376 {
7377 value = CONST_DOUBLE_LOW (operands[2]);
7378 emit_insn (gen_iordi3 (tmp, operands[1],
7379 immed_double_const (value
7380 & (~ (HOST_WIDE_INT) 0xffff),
7381 0, DImode)));
7382 }
7384 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7385 DONE;
7386 }
7387 }")
7389 (define_expand "xordi3"
7390 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7391 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7392 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7393 "TARGET_POWERPC64"
7394 "
7395 {
7396 if (non_logical_cint_operand (operands[2], DImode))
7397 {
7398 HOST_WIDE_INT value;
7399 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7400 ? operands[0] : gen_reg_rtx (DImode));
7402 if (GET_CODE (operands[2]) == CONST_INT)
7403 {
7404 value = INTVAL (operands[2]);
7405 emit_insn (gen_xordi3 (tmp, operands[1],
7406 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7407 }
7408 else
7409 {
7410 value = CONST_DOUBLE_LOW (operands[2]);
7411 emit_insn (gen_xordi3 (tmp, operands[1],
7412 immed_double_const (value
7413 & (~ (HOST_WIDE_INT) 0xffff),
7414 0, DImode)));
7415 }
7417 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7418 DONE;
7419 }
7420 }")
7422 (define_insn "*booldi3_internal1"
7423 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7424 (match_operator:DI 3 "boolean_or_operator"
7425 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7426 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7427 "TARGET_POWERPC64"
7428 "@
7429 %q3 %0,%1,%2
7430 %q3i %0,%1,%b2
7431 %q3is %0,%1,%u2")
7433 (define_insn "*booldi3_internal2"
7434 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7435 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7436 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7437 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7438 (const_int 0)))
7439 (clobber (match_scratch:DI 3 "=r,r"))]
7440 "TARGET_64BIT"
7441 "@
7442 %q4. %3,%1,%2
7443 #"
7444 [(set_attr "type" "compare")
7445 (set_attr "length" "4,8")])
7447 (define_split
7448 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7449 (compare:CC (match_operator:DI 4 "boolean_operator"
7450 [(match_operand:DI 1 "gpc_reg_operand" "")
7451 (match_operand:DI 2 "gpc_reg_operand" "")])
7452 (const_int 0)))
7453 (clobber (match_scratch:DI 3 ""))]
7454 "TARGET_POWERPC64 && reload_completed"
7455 [(set (match_dup 3) (match_dup 4))
7456 (set (match_dup 0)
7457 (compare:CC (match_dup 3)
7458 (const_int 0)))]
7459 "")
7461 (define_insn "*booldi3_internal3"
7462 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7463 (compare:CC (match_operator:DI 4 "boolean_operator"
7464 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7465 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7466 (const_int 0)))
7467 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7468 (match_dup 4))]
7469 "TARGET_64BIT"
7470 "@
7471 %q4. %0,%1,%2
7472 #"
7473 [(set_attr "type" "compare")
7474 (set_attr "length" "4,8")])
7476 (define_split
7477 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7478 (compare:CC (match_operator:DI 4 "boolean_operator"
7479 [(match_operand:DI 1 "gpc_reg_operand" "")
7480 (match_operand:DI 2 "gpc_reg_operand" "")])
7481 (const_int 0)))
7482 (set (match_operand:DI 0 "gpc_reg_operand" "")
7483 (match_dup 4))]
7484 "TARGET_POWERPC64 && reload_completed"
7485 [(set (match_dup 0) (match_dup 4))
7486 (set (match_dup 3)
7487 (compare:CC (match_dup 0)
7488 (const_int 0)))]
7489 "")
7491 ;; Split a logical operation that we can't do in one insn into two insns,
7492 ;; each of which does one 16-bit part. This is used by combine.
7494 (define_split
7495 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7496 (match_operator:DI 3 "boolean_or_operator"
7497 [(match_operand:DI 1 "gpc_reg_operand" "")
7498 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7499 "TARGET_POWERPC64"
7500 [(set (match_dup 0) (match_dup 4))
7501 (set (match_dup 0) (match_dup 5))]
7502 "
7503 {
7504 rtx i3,i4;
7506 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7507 {
7508 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7509 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7510 0, DImode);
7511 i4 = GEN_INT (value & 0xffff);
7512 }
7513 else
7514 {
7515 i3 = GEN_INT (INTVAL (operands[2])
7516 & (~ (HOST_WIDE_INT) 0xffff));
7517 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7518 }
7519 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7520 operands[1], i3);
7521 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7522 operands[0], i4);
7523 }")
7525 (define_insn "*boolcdi3_internal1"
7526 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7527 (match_operator:DI 3 "boolean_operator"
7528 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7529 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7530 "TARGET_POWERPC64"
7531 "%q3 %0,%2,%1")
7533 (define_insn "*boolcdi3_internal2"
7534 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7535 (compare:CC (match_operator:DI 4 "boolean_operator"
7536 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7537 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7538 (const_int 0)))
7539 (clobber (match_scratch:DI 3 "=r,r"))]
7540 "TARGET_64BIT"
7541 "@
7542 %q4. %3,%2,%1
7543 #"
7544 [(set_attr "type" "compare")
7545 (set_attr "length" "4,8")])
7547 (define_split
7548 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7549 (compare:CC (match_operator:DI 4 "boolean_operator"
7550 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7551 (match_operand:DI 2 "gpc_reg_operand" "")])
7552 (const_int 0)))
7553 (clobber (match_scratch:DI 3 ""))]
7554 "TARGET_POWERPC64 && reload_completed"
7555 [(set (match_dup 3) (match_dup 4))
7556 (set (match_dup 0)
7557 (compare:CC (match_dup 3)
7558 (const_int 0)))]
7559 "")
7561 (define_insn "*boolcdi3_internal3"
7562 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7563 (compare:CC (match_operator:DI 4 "boolean_operator"
7564 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7565 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7566 (const_int 0)))
7567 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7568 (match_dup 4))]
7569 "TARGET_64BIT"
7570 "@
7571 %q4. %0,%2,%1
7572 #"
7573 [(set_attr "type" "compare")
7574 (set_attr "length" "4,8")])
7576 (define_split
7577 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7578 (compare:CC (match_operator:DI 4 "boolean_operator"
7579 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7580 (match_operand:DI 2 "gpc_reg_operand" "")])
7581 (const_int 0)))
7582 (set (match_operand:DI 0 "gpc_reg_operand" "")
7583 (match_dup 4))]
7584 "TARGET_POWERPC64 && reload_completed"
7585 [(set (match_dup 0) (match_dup 4))
7586 (set (match_dup 3)
7587 (compare:CC (match_dup 0)
7588 (const_int 0)))]
7589 "")
7591 (define_insn "*boolccdi3_internal1"
7592 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7593 (match_operator:DI 3 "boolean_operator"
7594 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7595 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7596 "TARGET_POWERPC64"
7597 "%q3 %0,%1,%2")
7599 (define_insn "*boolccdi3_internal2"
7600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7601 (compare:CC (match_operator:DI 4 "boolean_operator"
7602 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7603 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7604 (const_int 0)))
7605 (clobber (match_scratch:DI 3 "=r,r"))]
7606 "TARGET_64BIT"
7607 "@
7608 %q4. %3,%1,%2
7609 #"
7610 [(set_attr "type" "compare")
7611 (set_attr "length" "4,8")])
7613 (define_split
7614 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7615 (compare:CC (match_operator:DI 4 "boolean_operator"
7616 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7617 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7618 (const_int 0)))
7619 (clobber (match_scratch:DI 3 ""))]
7620 "TARGET_POWERPC64 && reload_completed"
7621 [(set (match_dup 3) (match_dup 4))
7622 (set (match_dup 0)
7623 (compare:CC (match_dup 3)
7624 (const_int 0)))]
7625 "")
7627 (define_insn "*boolccdi3_internal3"
7628 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7629 (compare:CC (match_operator:DI 4 "boolean_operator"
7630 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7631 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7632 (const_int 0)))
7633 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7634 (match_dup 4))]
7635 "TARGET_64BIT"
7636 "@
7637 %q4. %0,%1,%2
7638 #"
7639 [(set_attr "type" "compare")
7640 (set_attr "length" "4,8")])
7642 (define_split
7643 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7644 (compare:CC (match_operator:DI 4 "boolean_operator"
7645 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7646 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7647 (const_int 0)))
7648 (set (match_operand:DI 0 "gpc_reg_operand" "")
7649 (match_dup 4))]
7650 "TARGET_POWERPC64 && reload_completed"
7651 [(set (match_dup 0) (match_dup 4))
7652 (set (match_dup 3)
7653 (compare:CC (match_dup 0)
7654 (const_int 0)))]
7655 "")
7656 \f
7657 ;; Now define ways of moving data around.
7659 ;; Elf specific ways of loading addresses for non-PIC code.
7660 ;; The output of this could be r0, but we make a very strong
7661 ;; preference for a base register because it will usually
7662 ;; be needed there.
7663 (define_insn "elf_high"
7664 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7665 (high:SI (match_operand 1 "" "")))]
7666 "TARGET_ELF && ! TARGET_64BIT"
7667 "{liu|lis} %0,%1@ha")
7669 (define_insn "elf_low"
7670 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7671 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7672 (match_operand 2 "" "")))]
7673 "TARGET_ELF && ! TARGET_64BIT"
7674 "@
7675 {cal|la} %0,%2@l(%1)
7676 {ai|addic} %0,%1,%K2")
7679 ;; Set up a register with a value from the GOT table
7681 (define_expand "movsi_got"
7682 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7683 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7684 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7685 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7686 "
7687 {
7688 if (GET_CODE (operands[1]) == CONST)
7689 {
7690 rtx offset = const0_rtx;
7691 HOST_WIDE_INT value;
7693 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7694 value = INTVAL (offset);
7695 if (value != 0)
7696 {
7697 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7698 emit_insn (gen_movsi_got (tmp, operands[1]));
7699 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7700 DONE;
7701 }
7702 }
7704 operands[2] = rs6000_got_register (operands[1]);
7705 }")
7707 (define_insn "*movsi_got_internal"
7708 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7709 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7710 (match_operand:SI 2 "gpc_reg_operand" "b")]
7711 UNSPEC_MOVSI_GOT))]
7712 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7713 "{l|lwz} %0,%a1@got(%2)"
7714 [(set_attr "type" "load")])
7716 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7717 ;; didn't get allocated to a hard register.
7718 (define_split
7719 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7720 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7721 (match_operand:SI 2 "memory_operand" "")]
7722 UNSPEC_MOVSI_GOT))]
7723 "DEFAULT_ABI == ABI_V4
7724 && flag_pic == 1
7725 && (reload_in_progress || reload_completed)"
7726 [(set (match_dup 0) (match_dup 2))
7727 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7728 UNSPEC_MOVSI_GOT))]
7729 "")
7731 ;; For SI, we special-case integers that can't be loaded in one insn. We
7732 ;; do the load 16-bits at a time. We could do this by loading from memory,
7733 ;; and this is even supposed to be faster, but it is simpler not to get
7734 ;; integers in the TOC.
7735 (define_expand "movsi"
7736 [(set (match_operand:SI 0 "general_operand" "")
7737 (match_operand:SI 1 "any_operand" ""))]
7738 ""
7739 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7741 (define_insn "movsi_low"
7742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7743 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7744 (match_operand 2 "" ""))))]
7745 "TARGET_MACHO && ! TARGET_64BIT"
7746 "{l|lwz} %0,lo16(%2)(%1)"
7747 [(set_attr "type" "load")
7748 (set_attr "length" "4")])
7750 (define_insn "*movsi_internal1"
7751 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7752 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7753 "gpc_reg_operand (operands[0], SImode)
7754 || gpc_reg_operand (operands[1], SImode)"
7755 "@
7756 mr %0,%1
7757 {cal|la} %0,%a1
7758 {l%U1%X1|lwz%U1%X1} %0,%1
7759 {st%U0%X0|stw%U0%X0} %1,%0
7760 {lil|li} %0,%1
7761 {liu|lis} %0,%v1
7762 #
7763 {cal|la} %0,%a1
7764 mf%1 %0
7765 mt%0 %1
7766 mt%0 %1
7767 mt%0 %1
7768 {cror 0,0,0|nop}"
7769 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7770 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7772 ;; Split a load of a large constant into the appropriate two-insn
7773 ;; sequence.
7775 (define_split
7776 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7777 (match_operand:SI 1 "const_int_operand" ""))]
7778 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7779 && (INTVAL (operands[1]) & 0xffff) != 0"
7780 [(set (match_dup 0)
7781 (match_dup 2))
7782 (set (match_dup 0)
7783 (ior:SI (match_dup 0)
7784 (match_dup 3)))]
7785 "
7786 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7788 if (tem == operands[0])
7789 DONE;
7790 else
7791 FAIL;
7792 }")
7794 (define_insn "*movsi_internal2"
7795 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7796 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7797 (const_int 0)))
7798 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7799 "TARGET_32BIT"
7800 "@
7801 {cmpi|cmpwi} %2,%0,0
7802 mr. %0,%1
7803 #"
7804 [(set_attr "type" "cmp,compare,cmp")
7805 (set_attr "length" "4,4,8")])
7807 (define_split
7808 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7809 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7810 (const_int 0)))
7811 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7812 "TARGET_32BIT && reload_completed"
7813 [(set (match_dup 0) (match_dup 1))
7814 (set (match_dup 2)
7815 (compare:CC (match_dup 0)
7816 (const_int 0)))]
7817 "")
7818 \f
7819 (define_expand "movhi"
7820 [(set (match_operand:HI 0 "general_operand" "")
7821 (match_operand:HI 1 "any_operand" ""))]
7822 ""
7823 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7825 (define_insn "*movhi_internal"
7826 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7827 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7828 "gpc_reg_operand (operands[0], HImode)
7829 || gpc_reg_operand (operands[1], HImode)"
7830 "@
7831 mr %0,%1
7832 lhz%U1%X1 %0,%1
7833 sth%U0%X0 %1,%0
7834 {lil|li} %0,%w1
7835 mf%1 %0
7836 mt%0 %1
7837 mt%0 %1
7838 {cror 0,0,0|nop}"
7839 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7841 (define_expand "movqi"
7842 [(set (match_operand:QI 0 "general_operand" "")
7843 (match_operand:QI 1 "any_operand" ""))]
7844 ""
7845 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7847 (define_insn "*movqi_internal"
7848 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7849 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7850 "gpc_reg_operand (operands[0], QImode)
7851 || gpc_reg_operand (operands[1], QImode)"
7852 "@
7853 mr %0,%1
7854 lbz%U1%X1 %0,%1
7855 stb%U0%X0 %1,%0
7856 {lil|li} %0,%1
7857 mf%1 %0
7858 mt%0 %1
7859 mt%0 %1
7860 {cror 0,0,0|nop}"
7861 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7862 \f
7863 ;; Here is how to move condition codes around. When we store CC data in
7864 ;; an integer register or memory, we store just the high-order 4 bits.
7865 ;; This lets us not shift in the most common case of CR0.
7866 (define_expand "movcc"
7867 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7868 (match_operand:CC 1 "nonimmediate_operand" ""))]
7869 ""
7870 "")
7872 (define_insn "*movcc_internal1"
7873 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7874 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7875 "register_operand (operands[0], CCmode)
7876 || register_operand (operands[1], CCmode)"
7877 "@
7878 mcrf %0,%1
7879 mtcrf 128,%1
7880 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7881 mfcr %0%Q1
7882 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7883 mr %0,%1
7884 mf%1 %0
7885 mt%0 %1
7886 mt%0 %1
7887 {l%U1%X1|lwz%U1%X1} %0,%1
7888 {st%U0%U1|stw%U0%U1} %1,%0"
7889 [(set (attr "type")
7890 (cond [(eq_attr "alternative" "0")
7891 (const_string "cr_logical")
7892 (eq_attr "alternative" "1,2")
7893 (const_string "mtcr")
7894 (eq_attr "alternative" "5,7")
7895 (const_string "integer")
7896 (eq_attr "alternative" "6")
7897 (const_string "mfjmpr")
7898 (eq_attr "alternative" "8")
7899 (const_string "mtjmpr")
7900 (eq_attr "alternative" "9")
7901 (const_string "load")
7902 (eq_attr "alternative" "10")
7903 (const_string "store")
7904 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7905 (const_string "mfcrf")
7906 ]
7907 (const_string "mfcr")))
7908 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7909 \f
7910 ;; For floating-point, we normally deal with the floating-point registers
7911 ;; unless -msoft-float is used. The sole exception is that parameter passing
7912 ;; can produce floating-point values in fixed-point registers. Unless the
7913 ;; value is a simple constant or already in memory, we deal with this by
7914 ;; allocating memory and copying the value explicitly via that memory location.
7915 (define_expand "movsf"
7916 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7917 (match_operand:SF 1 "any_operand" ""))]
7918 ""
7919 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7921 (define_split
7922 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7923 (match_operand:SF 1 "const_double_operand" ""))]
7924 "reload_completed
7925 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7926 || (GET_CODE (operands[0]) == SUBREG
7927 && GET_CODE (SUBREG_REG (operands[0])) == REG
7928 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7929 [(set (match_dup 2) (match_dup 3))]
7930 "
7931 {
7932 long l;
7933 REAL_VALUE_TYPE rv;
7935 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7936 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7938 if (! TARGET_POWERPC64)
7939 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7940 else
7941 operands[2] = gen_lowpart (SImode, operands[0]);
7943 operands[3] = gen_int_mode (l, SImode);
7944 }")
7946 (define_insn "*movsf_hardfloat"
7947 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7948 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7949 "(gpc_reg_operand (operands[0], SFmode)
7950 || gpc_reg_operand (operands[1], SFmode))
7951 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7952 "@
7953 mr %0,%1
7954 {l%U1%X1|lwz%U1%X1} %0,%1
7955 {st%U0%X0|stw%U0%X0} %1,%0
7956 fmr %0,%1
7957 lfs%U1%X1 %0,%1
7958 stfs%U0%X0 %1,%0
7959 mt%0 %1
7960 mt%0 %1
7961 mf%1 %0
7962 {cror 0,0,0|nop}
7963 #
7964 #"
7965 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7966 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7968 (define_insn "*movsf_softfloat"
7969 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7970 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7971 "(gpc_reg_operand (operands[0], SFmode)
7972 || gpc_reg_operand (operands[1], SFmode))
7973 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7974 "@
7975 mr %0,%1
7976 mt%0 %1
7977 mt%0 %1
7978 mf%1 %0
7979 {l%U1%X1|lwz%U1%X1} %0,%1
7980 {st%U0%X0|stw%U0%X0} %1,%0
7981 {lil|li} %0,%1
7982 {liu|lis} %0,%v1
7983 {cal|la} %0,%a1
7984 #
7985 #
7986 {cror 0,0,0|nop}"
7987 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7988 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7990 \f
7991 (define_expand "movdf"
7992 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7993 (match_operand:DF 1 "any_operand" ""))]
7994 ""
7995 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7997 (define_split
7998 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7999 (match_operand:DF 1 "const_int_operand" ""))]
8000 "! TARGET_POWERPC64 && reload_completed
8001 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8002 || (GET_CODE (operands[0]) == SUBREG
8003 && GET_CODE (SUBREG_REG (operands[0])) == REG
8004 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8005 [(set (match_dup 2) (match_dup 4))
8006 (set (match_dup 3) (match_dup 1))]
8007 "
8008 {
8009 int endian = (WORDS_BIG_ENDIAN == 0);
8010 HOST_WIDE_INT value = INTVAL (operands[1]);
8012 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8013 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8014 #if HOST_BITS_PER_WIDE_INT == 32
8015 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8016 #else
8017 operands[4] = GEN_INT (value >> 32);
8018 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8019 #endif
8020 }")
8022 (define_split
8023 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8024 (match_operand:DF 1 "const_double_operand" ""))]
8025 "! TARGET_POWERPC64 && reload_completed
8026 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8027 || (GET_CODE (operands[0]) == SUBREG
8028 && GET_CODE (SUBREG_REG (operands[0])) == REG
8029 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8030 [(set (match_dup 2) (match_dup 4))
8031 (set (match_dup 3) (match_dup 5))]
8032 "
8033 {
8034 int endian = (WORDS_BIG_ENDIAN == 0);
8035 long l[2];
8036 REAL_VALUE_TYPE rv;
8038 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8039 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8041 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8042 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8043 operands[4] = gen_int_mode (l[endian], SImode);
8044 operands[5] = gen_int_mode (l[1 - endian], SImode);
8045 }")
8047 (define_split
8048 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8049 (match_operand:DF 1 "easy_fp_constant" ""))]
8050 "TARGET_POWERPC64 && reload_completed
8051 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8052 || (GET_CODE (operands[0]) == SUBREG
8053 && GET_CODE (SUBREG_REG (operands[0])) == REG
8054 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8055 [(set (match_dup 2) (match_dup 3))]
8056 "
8057 {
8058 int endian = (WORDS_BIG_ENDIAN == 0);
8059 long l[2];
8060 REAL_VALUE_TYPE rv;
8061 #if HOST_BITS_PER_WIDE_INT >= 64
8062 HOST_WIDE_INT val;
8063 #endif
8065 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8066 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8068 operands[2] = gen_lowpart (DImode, operands[0]);
8069 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8070 #if HOST_BITS_PER_WIDE_INT >= 64
8071 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8072 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8074 operands[3] = gen_int_mode (val, DImode);
8075 #else
8076 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8077 #endif
8078 }")
8080 ;; Don't have reload use general registers to load a constant. First,
8081 ;; it might not work if the output operand is the equivalent of
8082 ;; a non-offsettable memref, but also it is less efficient than loading
8083 ;; the constant into an FP register, since it will probably be used there.
8084 ;; The "??" is a kludge until we can figure out a more reasonable way
8085 ;; of handling these non-offsettable values.
8086 (define_insn "*movdf_hardfloat32"
8087 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8088 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8089 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8090 && (gpc_reg_operand (operands[0], DFmode)
8091 || gpc_reg_operand (operands[1], DFmode))"
8092 "*
8093 {
8094 switch (which_alternative)
8095 {
8096 default:
8097 abort ();
8098 case 0:
8099 /* We normally copy the low-numbered register first. However, if
8100 the first register operand 0 is the same as the second register
8101 of operand 1, we must copy in the opposite order. */
8102 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8103 return \"mr %L0,%L1\;mr %0,%1\";
8104 else
8105 return \"mr %0,%1\;mr %L0,%L1\";
8106 case 1:
8107 if (GET_CODE (operands[1]) == MEM
8108 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
8109 reload_completed || reload_in_progress)
8110 || GET_CODE (XEXP (operands[1], 0)) == REG
8111 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8112 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8113 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
8114 {
8115 /* If the low-address word is used in the address, we must load
8116 it last. Otherwise, load it first. Note that we cannot have
8117 auto-increment in that case since the address register is
8118 known to be dead. */
8119 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8120 operands[1], 0))
8121 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8122 else
8123 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8124 }
8125 else
8126 {
8127 rtx addreg;
8129 addreg = find_addr_reg (XEXP (operands[1], 0));
8130 if (refers_to_regno_p (REGNO (operands[0]),
8131 REGNO (operands[0]) + 1,
8132 operands[1], 0))
8133 {
8134 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8135 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8136 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8137 return \"{lx|lwzx} %0,%1\";
8138 }
8139 else
8140 {
8141 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8142 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8143 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8144 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8145 return \"\";
8146 }
8147 }
8148 case 2:
8149 if (GET_CODE (operands[0]) == MEM
8150 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
8151 reload_completed || reload_in_progress)
8152 || GET_CODE (XEXP (operands[0], 0)) == REG
8153 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8154 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8155 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
8156 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8157 else
8158 {
8159 rtx addreg;
8161 addreg = find_addr_reg (XEXP (operands[0], 0));
8162 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8163 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8164 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8165 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8166 return \"\";
8167 }
8168 case 3:
8169 return \"fmr %0,%1\";
8170 case 4:
8171 return \"lfd%U1%X1 %0,%1\";
8172 case 5:
8173 return \"stfd%U0%X0 %1,%0\";
8174 case 6:
8175 case 7:
8176 case 8:
8177 return \"#\";
8178 }
8179 }"
8180 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8181 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8183 (define_insn "*movdf_softfloat32"
8184 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8185 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8186 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8187 && (gpc_reg_operand (operands[0], DFmode)
8188 || gpc_reg_operand (operands[1], DFmode))"
8189 "*
8190 {
8191 switch (which_alternative)
8192 {
8193 default:
8194 abort ();
8195 case 0:
8196 /* We normally copy the low-numbered register first. However, if
8197 the first register operand 0 is the same as the second register of
8198 operand 1, we must copy in the opposite order. */
8199 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8200 return \"mr %L0,%L1\;mr %0,%1\";
8201 else
8202 return \"mr %0,%1\;mr %L0,%L1\";
8203 case 1:
8204 /* If the low-address word is used in the address, we must load
8205 it last. Otherwise, load it first. Note that we cannot have
8206 auto-increment in that case since the address register is
8207 known to be dead. */
8208 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8209 operands[1], 0))
8210 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8211 else
8212 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8213 case 2:
8214 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8215 case 3:
8216 case 4:
8217 case 5:
8218 return \"#\";
8219 }
8220 }"
8221 [(set_attr "type" "two,load,store,*,*,*")
8222 (set_attr "length" "8,8,8,8,12,16")])
8224 ; ld/std require word-aligned displacements -> 'Y' constraint.
8225 ; List Y->r and r->Y before r->r for reload.
8226 (define_insn "*movdf_hardfloat64"
8227 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
8228 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8229 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8230 && (gpc_reg_operand (operands[0], DFmode)
8231 || gpc_reg_operand (operands[1], DFmode))"
8232 "@
8233 std%U0%X0 %1,%0
8234 ld%U1%X1 %0,%1
8235 mr %0,%1
8236 fmr %0,%1
8237 lfd%U1%X1 %0,%1
8238 stfd%U0%X0 %1,%0
8239 mt%0 %1
8240 mf%1 %0
8241 {cror 0,0,0|nop}
8242 #
8243 #
8244 #"
8245 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
8246 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8248 (define_insn "*movdf_softfloat64"
8249 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8250 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8251 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8252 && (gpc_reg_operand (operands[0], DFmode)
8253 || gpc_reg_operand (operands[1], DFmode))"
8254 "@
8255 ld%U1%X1 %0,%1
8256 std%U0%X0 %1,%0
8257 mr %0,%1
8258 mt%0 %1
8259 mf%1 %0
8260 #
8261 #
8262 #
8263 {cror 0,0,0|nop}"
8264 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
8265 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8266 \f
8267 (define_expand "movtf"
8268 [(set (match_operand:TF 0 "general_operand" "")
8269 (match_operand:TF 1 "any_operand" ""))]
8270 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8271 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8272 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8274 ; It's important to list the o->f and f->o moves before f->f because
8275 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8276 ; which doesn't make progress. Likewise r->Y must be before r->r.
8277 (define_insn_and_split "*movtf_internal"
8278 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8279 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8280 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8281 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8282 && (gpc_reg_operand (operands[0], TFmode)
8283 || gpc_reg_operand (operands[1], TFmode))"
8284 "#"
8285 "&& reload_completed"
8286 [(pc)]
8287 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8288 [(set_attr "length" "8,8,8,20,20,16")])
8290 (define_expand "extenddftf2"
8291 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8292 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8293 (use (match_dup 2))])]
8294 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8295 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8296 {
8297 operands[2] = CONST0_RTX (DFmode);
8298 })
8300 (define_insn_and_split "*extenddftf2_internal"
8301 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8302 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8303 (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))]
8304 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8305 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8306 "#"
8307 "&& reload_completed"
8308 [(pc)]
8309 {
8310 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8311 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8312 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8313 operands[1]);
8314 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8315 operands[2]);
8316 DONE;
8317 })
8319 (define_expand "extendsftf2"
8320 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8321 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8322 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8323 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8324 {
8325 rtx tmp = gen_reg_rtx (DFmode);
8326 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8327 emit_insn (gen_extenddftf2 (operands[0], tmp));
8328 DONE;
8329 })
8331 (define_expand "trunctfdf2"
8332 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8333 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8334 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8335 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8336 "")
8338 (define_insn_and_split "trunctfdf2_internal1"
8339 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8340 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8341 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
8342 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8343 "@
8344 #
8345 fmr %0,%1"
8346 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8347 [(const_int 0)]
8348 {
8349 emit_note (NOTE_INSN_DELETED);
8350 DONE;
8351 }
8352 [(set_attr "type" "fp")])
8354 (define_insn "trunctfdf2_internal2"
8355 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8356 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8357 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
8358 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8359 "fadd %0,%1,%L1"
8360 [(set_attr "type" "fp")])
8362 (define_insn_and_split "trunctfsf2"
8363 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8364 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8365 (clobber (match_scratch:DF 2 "=f"))]
8366 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8367 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8368 "#"
8369 "&& reload_completed"
8370 [(set (match_dup 2)
8371 (float_truncate:DF (match_dup 1)))
8372 (set (match_dup 0)
8373 (float_truncate:SF (match_dup 2)))]
8374 "")
8376 (define_expand "floatsitf2"
8377 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8378 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8379 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8380 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8381 {
8382 rtx tmp = gen_reg_rtx (DFmode);
8383 expand_float (tmp, operands[1], false);
8384 emit_insn (gen_extenddftf2 (operands[0], tmp));
8385 DONE;
8386 })
8388 ; fadd, but rounding towards zero.
8389 ; This is probably not the optimal code sequence.
8390 (define_insn "fix_trunc_helper"
8391 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8392 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8393 UNSPEC_FIX_TRUNC_TF))
8394 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8395 "TARGET_HARD_FLOAT && TARGET_FPRS"
8396 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8397 [(set_attr "type" "fp")
8398 (set_attr "length" "20")])
8400 (define_expand "fix_trunctfsi2"
8401 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8402 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8403 (clobber (match_dup 2))
8404 (clobber (match_dup 3))
8405 (clobber (match_dup 4))
8406 (clobber (match_dup 5))])]
8407 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8408 && (TARGET_POWER2 || TARGET_POWERPC)
8409 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8410 {
8411 operands[2] = gen_reg_rtx (DFmode);
8412 operands[3] = gen_reg_rtx (DFmode);
8413 operands[4] = gen_reg_rtx (DImode);
8414 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8415 })
8417 (define_insn_and_split "*fix_trunctfsi2_internal"
8418 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8419 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8420 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8421 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8422 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8423 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8424 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8425 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8426 "#"
8427 "&& reload_completed"
8428 [(pc)]
8429 {
8430 rtx lowword;
8431 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8433 if (GET_CODE (operands[5]) != MEM)
8434 abort();
8435 lowword = XEXP (operands[5], 0);
8436 if (WORDS_BIG_ENDIAN)
8437 lowword = plus_constant (lowword, 4);
8439 emit_insn (gen_fctiwz (operands[4], operands[2]));
8440 emit_move_insn (operands[5], operands[4]);
8441 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
8442 DONE;
8443 })
8445 (define_insn "negtf2"
8446 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8447 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8448 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8449 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8450 "*
8451 {
8452 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8453 return \"fneg %L0,%L1\;fneg %0,%1\";
8454 else
8455 return \"fneg %0,%1\;fneg %L0,%L1\";
8456 }"
8457 [(set_attr "type" "fp")
8458 (set_attr "length" "8")])
8460 (define_expand "abstf2"
8461 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8462 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8463 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8464 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8465 "
8466 {
8467 rtx label = gen_label_rtx ();
8468 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8469 emit_label (label);
8470 DONE;
8471 }")
8473 (define_expand "abstf2_internal"
8474 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8475 (match_operand:TF 1 "gpc_reg_operand" "f"))
8476 (set (match_dup 3) (match_dup 5))
8477 (set (match_dup 5) (abs:DF (match_dup 5)))
8478 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8479 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8480 (label_ref (match_operand 2 "" ""))
8481 (pc)))
8482 (set (match_dup 6) (neg:DF (match_dup 6)))]
8483 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8484 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8485 "
8486 {
8487 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8488 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8489 operands[3] = gen_reg_rtx (DFmode);
8490 operands[4] = gen_reg_rtx (CCFPmode);
8491 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8492 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8493 }")
8495 (define_expand "copysigntf3"
8496 [(match_operand:TF 0 "general_operand" "")
8497 (match_operand:TF 1 "general_operand" "")
8498 (match_operand:TF 2 "general_operand" "")]
8499 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8500 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8501 {
8502 rtx target, op0, op1, temp;
8503 bool op0_is_abs = false;
8505 target = operands[0];
8506 op0 = operands[1];
8507 op1 = operands[2];
8509 if (GET_CODE (op0) == CONST_DOUBLE)
8510 {
8511 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
8512 op0 = simplify_unary_operation (ABS, TFmode, op0, TFmode);
8513 op0_is_abs = true;
8514 }
8516 temp = expand_copysign_absneg (TFmode, op0, op1, target, 127, op0_is_abs);
8517 if (temp != target)
8518 emit_move_insn (target, temp);
8519 DONE;
8520 })
8521 \f
8522 ;; Next come the multi-word integer load and store and the load and store
8523 ;; multiple insns.
8524 (define_expand "movdi"
8525 [(set (match_operand:DI 0 "general_operand" "")
8526 (match_operand:DI 1 "any_operand" ""))]
8527 ""
8528 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8530 ; List r->r after r->"o<>", otherwise reload will try to reload a
8531 ; non-offsettable address by using r->r which won't make progress.
8532 (define_insn "*movdi_internal32"
8533 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8534 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8535 "! TARGET_POWERPC64
8536 && (gpc_reg_operand (operands[0], DImode)
8537 || gpc_reg_operand (operands[1], DImode))"
8538 "@
8539 #
8540 #
8541 #
8542 fmr %0,%1
8543 lfd%U1%X1 %0,%1
8544 stfd%U0%X0 %1,%0
8545 #"
8546 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8548 (define_split
8549 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8550 (match_operand:DI 1 "const_int_operand" ""))]
8551 "! TARGET_POWERPC64 && reload_completed"
8552 [(set (match_dup 2) (match_dup 4))
8553 (set (match_dup 3) (match_dup 1))]
8554 "
8555 {
8556 HOST_WIDE_INT value = INTVAL (operands[1]);
8557 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8558 DImode);
8559 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8560 DImode);
8561 #if HOST_BITS_PER_WIDE_INT == 32
8562 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8563 #else
8564 operands[4] = GEN_INT (value >> 32);
8565 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8566 #endif
8567 }")
8569 (define_split
8570 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8571 (match_operand:DI 1 "input_operand" ""))]
8572 "reload_completed && !TARGET_POWERPC64
8573 && gpr_or_gpr_p (operands[0], operands[1])"
8574 [(pc)]
8575 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8577 (define_insn "*movdi_internal64"
8578 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8579 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8580 "TARGET_POWERPC64
8581 && (gpc_reg_operand (operands[0], DImode)
8582 || gpc_reg_operand (operands[1], DImode))"
8583 "@
8584 mr %0,%1
8585 ld%U1%X1 %0,%1
8586 std%U0%X0 %1,%0
8587 li %0,%1
8588 lis %0,%v1
8589 #
8590 {cal|la} %0,%a1
8591 fmr %0,%1
8592 lfd%U1%X1 %0,%1
8593 stfd%U0%X0 %1,%0
8594 mf%1 %0
8595 mt%0 %1
8596 {cror 0,0,0|nop}"
8597 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8598 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8600 ;; immediate value valid for a single instruction hiding in a const_double
8601 (define_insn ""
8602 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8603 (match_operand:DI 1 "const_double_operand" "F"))]
8604 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8605 && GET_CODE (operands[1]) == CONST_DOUBLE
8606 && num_insns_constant (operands[1], DImode) == 1"
8607 "*
8608 {
8609 return ((unsigned HOST_WIDE_INT)
8610 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8611 ? \"li %0,%1\" : \"lis %0,%v1\";
8612 }")
8614 ;; Generate all one-bits and clear left or right.
8615 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8616 (define_split
8617 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8618 (match_operand:DI 1 "mask64_operand" ""))]
8619 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8620 [(set (match_dup 0) (const_int -1))
8621 (set (match_dup 0)
8622 (and:DI (rotate:DI (match_dup 0)
8623 (const_int 0))
8624 (match_dup 1)))]
8625 "")
8627 ;; Split a load of a large constant into the appropriate five-instruction
8628 ;; sequence. Handle anything in a constant number of insns.
8629 ;; When non-easy constants can go in the TOC, this should use
8630 ;; easy_fp_constant predicate.
8631 (define_split
8632 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8633 (match_operand:DI 1 "const_int_operand" ""))]
8634 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8635 [(set (match_dup 0) (match_dup 2))
8636 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8637 "
8638 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8640 if (tem == operands[0])
8641 DONE;
8642 else
8643 FAIL;
8644 }")
8646 (define_split
8647 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8648 (match_operand:DI 1 "const_double_operand" ""))]
8649 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8650 [(set (match_dup 0) (match_dup 2))
8651 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8652 "
8653 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8655 if (tem == operands[0])
8656 DONE;
8657 else
8658 FAIL;
8659 }")
8661 (define_insn "*movdi_internal2"
8662 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8663 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8664 (const_int 0)))
8665 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8666 "TARGET_64BIT"
8667 "@
8668 cmpdi %2,%0,0
8669 mr. %0,%1
8670 #"
8671 [(set_attr "type" "cmp,compare,cmp")
8672 (set_attr "length" "4,4,8")])
8674 (define_split
8675 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8676 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8677 (const_int 0)))
8678 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8679 "TARGET_POWERPC64 && reload_completed"
8680 [(set (match_dup 0) (match_dup 1))
8681 (set (match_dup 2)
8682 (compare:CC (match_dup 0)
8683 (const_int 0)))]
8684 "")
8685 \f
8686 ;; TImode is similar, except that we usually want to compute the address into
8687 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8688 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8689 (define_expand "movti"
8690 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8691 (match_operand:TI 1 "general_operand" ""))
8692 (clobber (scratch:SI))])]
8693 ""
8694 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8696 ;; We say that MQ is clobbered in the last alternative because the first
8697 ;; alternative would never get used otherwise since it would need a reload
8698 ;; while the 2nd alternative would not. We put memory cases first so they
8699 ;; are preferred. Otherwise, we'd try to reload the output instead of
8700 ;; giving the SCRATCH mq.
8702 (define_insn "*movti_power"
8703 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8704 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8705 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8706 "TARGET_POWER && ! TARGET_POWERPC64
8707 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8708 "*
8709 {
8710 switch (which_alternative)
8711 {
8712 default:
8713 abort ();
8715 case 0:
8716 if (TARGET_STRING)
8717 return \"{stsi|stswi} %1,%P0,16\";
8718 case 1:
8719 case 2:
8720 return \"#\";
8721 case 3:
8722 /* If the address is not used in the output, we can use lsi. Otherwise,
8723 fall through to generating four loads. */
8724 if (TARGET_STRING
8725 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8726 return \"{lsi|lswi} %0,%P1,16\";
8727 /* ... fall through ... */
8728 case 4:
8729 case 5:
8730 return \"#\";
8731 }
8732 }"
8733 [(set_attr "type" "store,store,*,load,load,*")])
8735 (define_insn "*movti_string"
8736 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8737 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8738 "! TARGET_POWER && ! TARGET_POWERPC64
8739 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8740 "*
8741 {
8742 switch (which_alternative)
8743 {
8744 default:
8745 abort ();
8746 case 0:
8747 if (TARGET_STRING)
8748 return \"{stsi|stswi} %1,%P0,16\";
8749 case 1:
8750 case 2:
8751 return \"#\";
8752 case 3:
8753 /* If the address is not used in the output, we can use lsi. Otherwise,
8754 fall through to generating four loads. */
8755 if (TARGET_STRING
8756 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8757 return \"{lsi|lswi} %0,%P1,16\";
8758 /* ... fall through ... */
8759 case 4:
8760 case 5:
8761 return \"#\";
8762 }
8763 }"
8764 [(set_attr "type" "store,store,*,load,load,*")])
8766 (define_insn "*movti_ppc64"
8767 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8768 (match_operand:TI 1 "input_operand" "r,r,m"))]
8769 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8770 || gpc_reg_operand (operands[1], TImode))"
8771 "#"
8772 [(set_attr "type" "*,load,store")])
8774 (define_split
8775 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8776 (match_operand:TI 1 "const_double_operand" ""))]
8777 "TARGET_POWERPC64"
8778 [(set (match_dup 2) (match_dup 4))
8779 (set (match_dup 3) (match_dup 5))]
8780 "
8781 {
8782 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8783 TImode);
8784 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8785 TImode);
8786 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8787 {
8788 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8789 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8790 }
8791 else if (GET_CODE (operands[1]) == CONST_INT)
8792 {
8793 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8794 operands[5] = operands[1];
8795 }
8796 else
8797 FAIL;
8798 }")
8800 (define_split
8801 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8802 (match_operand:TI 1 "input_operand" ""))]
8803 "reload_completed
8804 && gpr_or_gpr_p (operands[0], operands[1])"
8805 [(pc)]
8806 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8807 \f
8808 (define_expand "load_multiple"
8809 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8810 (match_operand:SI 1 "" ""))
8811 (use (match_operand:SI 2 "" ""))])]
8812 "TARGET_STRING && !TARGET_POWERPC64"
8813 "
8814 {
8815 int regno;
8816 int count;
8817 rtx op1;
8818 int i;
8820 /* Support only loading a constant number of fixed-point registers from
8821 memory and only bother with this if more than two; the machine
8822 doesn't support more than eight. */
8823 if (GET_CODE (operands[2]) != CONST_INT
8824 || INTVAL (operands[2]) <= 2
8825 || INTVAL (operands[2]) > 8
8826 || GET_CODE (operands[1]) != MEM
8827 || GET_CODE (operands[0]) != REG
8828 || REGNO (operands[0]) >= 32)
8829 FAIL;
8831 count = INTVAL (operands[2]);
8832 regno = REGNO (operands[0]);
8834 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8835 op1 = replace_equiv_address (operands[1],
8836 force_reg (SImode, XEXP (operands[1], 0)));
8838 for (i = 0; i < count; i++)
8839 XVECEXP (operands[3], 0, i)
8840 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8841 adjust_address_nv (op1, SImode, i * 4));
8842 }")
8844 (define_insn "*ldmsi8"
8845 [(match_parallel 0 "load_multiple_operation"
8846 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8847 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8848 (set (match_operand:SI 3 "gpc_reg_operand" "")
8849 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8850 (set (match_operand:SI 4 "gpc_reg_operand" "")
8851 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8852 (set (match_operand:SI 5 "gpc_reg_operand" "")
8853 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8854 (set (match_operand:SI 6 "gpc_reg_operand" "")
8855 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8856 (set (match_operand:SI 7 "gpc_reg_operand" "")
8857 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8858 (set (match_operand:SI 8 "gpc_reg_operand" "")
8859 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8860 (set (match_operand:SI 9 "gpc_reg_operand" "")
8861 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8862 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8863 "*
8864 { return rs6000_output_load_multiple (operands); }"
8865 [(set_attr "type" "load")
8866 (set_attr "length" "32")])
8868 (define_insn "*ldmsi7"
8869 [(match_parallel 0 "load_multiple_operation"
8870 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8871 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8872 (set (match_operand:SI 3 "gpc_reg_operand" "")
8873 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8874 (set (match_operand:SI 4 "gpc_reg_operand" "")
8875 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8876 (set (match_operand:SI 5 "gpc_reg_operand" "")
8877 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8878 (set (match_operand:SI 6 "gpc_reg_operand" "")
8879 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8880 (set (match_operand:SI 7 "gpc_reg_operand" "")
8881 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8882 (set (match_operand:SI 8 "gpc_reg_operand" "")
8883 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8884 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8885 "*
8886 { return rs6000_output_load_multiple (operands); }"
8887 [(set_attr "type" "load")
8888 (set_attr "length" "32")])
8890 (define_insn "*ldmsi6"
8891 [(match_parallel 0 "load_multiple_operation"
8892 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8893 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8894 (set (match_operand:SI 3 "gpc_reg_operand" "")
8895 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8896 (set (match_operand:SI 4 "gpc_reg_operand" "")
8897 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8898 (set (match_operand:SI 5 "gpc_reg_operand" "")
8899 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8900 (set (match_operand:SI 6 "gpc_reg_operand" "")
8901 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8902 (set (match_operand:SI 7 "gpc_reg_operand" "")
8903 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8904 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8905 "*
8906 { return rs6000_output_load_multiple (operands); }"
8907 [(set_attr "type" "load")
8908 (set_attr "length" "32")])
8910 (define_insn "*ldmsi5"
8911 [(match_parallel 0 "load_multiple_operation"
8912 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8913 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8914 (set (match_operand:SI 3 "gpc_reg_operand" "")
8915 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8916 (set (match_operand:SI 4 "gpc_reg_operand" "")
8917 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8918 (set (match_operand:SI 5 "gpc_reg_operand" "")
8919 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8920 (set (match_operand:SI 6 "gpc_reg_operand" "")
8921 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8922 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8923 "*
8924 { return rs6000_output_load_multiple (operands); }"
8925 [(set_attr "type" "load")
8926 (set_attr "length" "32")])
8928 (define_insn "*ldmsi4"
8929 [(match_parallel 0 "load_multiple_operation"
8930 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8931 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8932 (set (match_operand:SI 3 "gpc_reg_operand" "")
8933 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8934 (set (match_operand:SI 4 "gpc_reg_operand" "")
8935 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8936 (set (match_operand:SI 5 "gpc_reg_operand" "")
8937 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8938 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8939 "*
8940 { return rs6000_output_load_multiple (operands); }"
8941 [(set_attr "type" "load")
8942 (set_attr "length" "32")])
8944 (define_insn "*ldmsi3"
8945 [(match_parallel 0 "load_multiple_operation"
8946 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8947 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8948 (set (match_operand:SI 3 "gpc_reg_operand" "")
8949 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8950 (set (match_operand:SI 4 "gpc_reg_operand" "")
8951 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8952 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8953 "*
8954 { return rs6000_output_load_multiple (operands); }"
8955 [(set_attr "type" "load")
8956 (set_attr "length" "32")])
8958 (define_expand "store_multiple"
8959 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8960 (match_operand:SI 1 "" ""))
8961 (clobber (scratch:SI))
8962 (use (match_operand:SI 2 "" ""))])]
8963 "TARGET_STRING && !TARGET_POWERPC64"
8964 "
8965 {
8966 int regno;
8967 int count;
8968 rtx to;
8969 rtx op0;
8970 int i;
8972 /* Support only storing a constant number of fixed-point registers to
8973 memory and only bother with this if more than two; the machine
8974 doesn't support more than eight. */
8975 if (GET_CODE (operands[2]) != CONST_INT
8976 || INTVAL (operands[2]) <= 2
8977 || INTVAL (operands[2]) > 8
8978 || GET_CODE (operands[0]) != MEM
8979 || GET_CODE (operands[1]) != REG
8980 || REGNO (operands[1]) >= 32)
8981 FAIL;
8983 count = INTVAL (operands[2]);
8984 regno = REGNO (operands[1]);
8986 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8987 to = force_reg (SImode, XEXP (operands[0], 0));
8988 op0 = replace_equiv_address (operands[0], to);
8990 XVECEXP (operands[3], 0, 0)
8991 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8992 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8993 gen_rtx_SCRATCH (SImode));
8995 for (i = 1; i < count; i++)
8996 XVECEXP (operands[3], 0, i + 1)
8997 = gen_rtx_SET (VOIDmode,
8998 adjust_address_nv (op0, SImode, i * 4),
8999 gen_rtx_REG (SImode, regno + i));
9000 }")
9002 (define_insn "*store_multiple_power"
9003 [(match_parallel 0 "store_multiple_operation"
9004 [(set (match_operand:SI 1 "indirect_operand" "=Q")
9005 (match_operand:SI 2 "gpc_reg_operand" "r"))
9006 (clobber (match_scratch:SI 3 "=q"))])]
9007 "TARGET_STRING && TARGET_POWER"
9008 "{stsi|stswi} %2,%P1,%O0"
9009 [(set_attr "type" "store")])
9011 (define_insn "*stmsi8"
9012 [(match_parallel 0 "store_multiple_operation"
9013 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9014 (match_operand:SI 2 "gpc_reg_operand" "r"))
9015 (clobber (match_scratch:SI 3 "X"))
9016 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9017 (match_operand:SI 4 "gpc_reg_operand" "r"))
9018 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9019 (match_operand:SI 5 "gpc_reg_operand" "r"))
9020 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9021 (match_operand:SI 6 "gpc_reg_operand" "r"))
9022 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9023 (match_operand:SI 7 "gpc_reg_operand" "r"))
9024 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9025 (match_operand:SI 8 "gpc_reg_operand" "r"))
9026 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9027 (match_operand:SI 9 "gpc_reg_operand" "r"))
9028 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9029 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9030 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9031 "{stsi|stswi} %2,%1,%O0"
9032 [(set_attr "type" "store")])
9034 (define_insn "*stmsi7"
9035 [(match_parallel 0 "store_multiple_operation"
9036 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9037 (match_operand:SI 2 "gpc_reg_operand" "r"))
9038 (clobber (match_scratch:SI 3 "X"))
9039 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9040 (match_operand:SI 4 "gpc_reg_operand" "r"))
9041 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9042 (match_operand:SI 5 "gpc_reg_operand" "r"))
9043 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9044 (match_operand:SI 6 "gpc_reg_operand" "r"))
9045 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9046 (match_operand:SI 7 "gpc_reg_operand" "r"))
9047 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9048 (match_operand:SI 8 "gpc_reg_operand" "r"))
9049 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9050 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9051 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9052 "{stsi|stswi} %2,%1,%O0"
9053 [(set_attr "type" "store")])
9055 (define_insn "*stmsi6"
9056 [(match_parallel 0 "store_multiple_operation"
9057 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9058 (match_operand:SI 2 "gpc_reg_operand" "r"))
9059 (clobber (match_scratch:SI 3 "X"))
9060 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9061 (match_operand:SI 4 "gpc_reg_operand" "r"))
9062 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9063 (match_operand:SI 5 "gpc_reg_operand" "r"))
9064 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9065 (match_operand:SI 6 "gpc_reg_operand" "r"))
9066 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9067 (match_operand:SI 7 "gpc_reg_operand" "r"))
9068 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9069 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9070 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9071 "{stsi|stswi} %2,%1,%O0"
9072 [(set_attr "type" "store")])
9074 (define_insn "*stmsi5"
9075 [(match_parallel 0 "store_multiple_operation"
9076 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9077 (match_operand:SI 2 "gpc_reg_operand" "r"))
9078 (clobber (match_scratch:SI 3 "X"))
9079 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9080 (match_operand:SI 4 "gpc_reg_operand" "r"))
9081 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9082 (match_operand:SI 5 "gpc_reg_operand" "r"))
9083 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9084 (match_operand:SI 6 "gpc_reg_operand" "r"))
9085 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9086 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9087 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9088 "{stsi|stswi} %2,%1,%O0"
9089 [(set_attr "type" "store")])
9091 (define_insn "*stmsi4"
9092 [(match_parallel 0 "store_multiple_operation"
9093 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9094 (match_operand:SI 2 "gpc_reg_operand" "r"))
9095 (clobber (match_scratch:SI 3 "X"))
9096 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9097 (match_operand:SI 4 "gpc_reg_operand" "r"))
9098 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9099 (match_operand:SI 5 "gpc_reg_operand" "r"))
9100 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9101 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9102 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9103 "{stsi|stswi} %2,%1,%O0"
9104 [(set_attr "type" "store")])
9106 (define_insn "*stmsi3"
9107 [(match_parallel 0 "store_multiple_operation"
9108 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9109 (match_operand:SI 2 "gpc_reg_operand" "r"))
9110 (clobber (match_scratch:SI 3 "X"))
9111 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9112 (match_operand:SI 4 "gpc_reg_operand" "r"))
9113 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9114 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9115 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9116 "{stsi|stswi} %2,%1,%O0"
9117 [(set_attr "type" "store")])
9118 \f
9119 (define_expand "clrmemsi"
9120 [(parallel [(set (match_operand:BLK 0 "" "")
9121 (const_int 0))
9122 (use (match_operand:SI 1 "" ""))
9123 (use (match_operand:SI 2 "" ""))])]
9124 ""
9125 "
9126 {
9127 if (expand_block_clear (operands))
9128 DONE;
9129 else
9130 FAIL;
9131 }")
9133 ;; String/block move insn.
9134 ;; Argument 0 is the destination
9135 ;; Argument 1 is the source
9136 ;; Argument 2 is the length
9137 ;; Argument 3 is the alignment
9139 (define_expand "movmemsi"
9140 [(parallel [(set (match_operand:BLK 0 "" "")
9141 (match_operand:BLK 1 "" ""))
9142 (use (match_operand:SI 2 "" ""))
9143 (use (match_operand:SI 3 "" ""))])]
9144 ""
9145 "
9146 {
9147 if (expand_block_move (operands))
9148 DONE;
9149 else
9150 FAIL;
9151 }")
9153 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9154 ;; register allocator doesn't have a clue about allocating 8 word registers.
9155 ;; rD/rS = r5 is preferred, efficient form.
9156 (define_expand "movmemsi_8reg"
9157 [(parallel [(set (match_operand 0 "" "")
9158 (match_operand 1 "" ""))
9159 (use (match_operand 2 "" ""))
9160 (use (match_operand 3 "" ""))
9161 (clobber (reg:SI 5))
9162 (clobber (reg:SI 6))
9163 (clobber (reg:SI 7))
9164 (clobber (reg:SI 8))
9165 (clobber (reg:SI 9))
9166 (clobber (reg:SI 10))
9167 (clobber (reg:SI 11))
9168 (clobber (reg:SI 12))
9169 (clobber (match_scratch:SI 4 ""))])]
9170 "TARGET_STRING"
9171 "")
9173 (define_insn ""
9174 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9175 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9176 (use (match_operand:SI 2 "immediate_operand" "i"))
9177 (use (match_operand:SI 3 "immediate_operand" "i"))
9178 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9179 (clobber (reg:SI 6))
9180 (clobber (reg:SI 7))
9181 (clobber (reg:SI 8))
9182 (clobber (reg:SI 9))
9183 (clobber (reg:SI 10))
9184 (clobber (reg:SI 11))
9185 (clobber (reg:SI 12))
9186 (clobber (match_scratch:SI 5 "=q"))]
9187 "TARGET_STRING && TARGET_POWER
9188 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9189 || INTVAL (operands[2]) == 0)
9190 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9191 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9192 && REGNO (operands[4]) == 5"
9193 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9194 [(set_attr "type" "load")
9195 (set_attr "length" "8")])
9197 (define_insn ""
9198 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9199 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9200 (use (match_operand:SI 2 "immediate_operand" "i"))
9201 (use (match_operand:SI 3 "immediate_operand" "i"))
9202 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9203 (clobber (reg:SI 6))
9204 (clobber (reg:SI 7))
9205 (clobber (reg:SI 8))
9206 (clobber (reg:SI 9))
9207 (clobber (reg:SI 10))
9208 (clobber (reg:SI 11))
9209 (clobber (reg:SI 12))
9210 (clobber (match_scratch:SI 5 "X"))]
9211 "TARGET_STRING && ! TARGET_POWER
9212 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9213 || INTVAL (operands[2]) == 0)
9214 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9215 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9216 && REGNO (operands[4]) == 5"
9217 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9218 [(set_attr "type" "load")
9219 (set_attr "length" "8")])
9221 (define_insn ""
9222 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9223 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9224 (use (match_operand:SI 2 "immediate_operand" "i"))
9225 (use (match_operand:SI 3 "immediate_operand" "i"))
9226 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9227 (clobber (reg:SI 6))
9228 (clobber (reg:SI 7))
9229 (clobber (reg:SI 8))
9230 (clobber (reg:SI 9))
9231 (clobber (reg:SI 10))
9232 (clobber (reg:SI 11))
9233 (clobber (reg:SI 12))
9234 (clobber (match_scratch:SI 5 "X"))]
9235 "TARGET_STRING && TARGET_POWERPC64
9236 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9237 || INTVAL (operands[2]) == 0)
9238 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9239 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9240 && REGNO (operands[4]) == 5"
9241 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9242 [(set_attr "type" "load")
9243 (set_attr "length" "8")])
9245 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9246 ;; register allocator doesn't have a clue about allocating 6 word registers.
9247 ;; rD/rS = r5 is preferred, efficient form.
9248 (define_expand "movmemsi_6reg"
9249 [(parallel [(set (match_operand 0 "" "")
9250 (match_operand 1 "" ""))
9251 (use (match_operand 2 "" ""))
9252 (use (match_operand 3 "" ""))
9253 (clobber (reg:SI 5))
9254 (clobber (reg:SI 6))
9255 (clobber (reg:SI 7))
9256 (clobber (reg:SI 8))
9257 (clobber (reg:SI 9))
9258 (clobber (reg:SI 10))
9259 (clobber (match_scratch:SI 4 ""))])]
9260 "TARGET_STRING"
9261 "")
9263 (define_insn ""
9264 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9265 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9266 (use (match_operand:SI 2 "immediate_operand" "i"))
9267 (use (match_operand:SI 3 "immediate_operand" "i"))
9268 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9269 (clobber (reg:SI 6))
9270 (clobber (reg:SI 7))
9271 (clobber (reg:SI 8))
9272 (clobber (reg:SI 9))
9273 (clobber (reg:SI 10))
9274 (clobber (match_scratch:SI 5 "=q"))]
9275 "TARGET_STRING && TARGET_POWER
9276 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9277 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9278 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9279 && REGNO (operands[4]) == 5"
9280 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9281 [(set_attr "type" "load")
9282 (set_attr "length" "8")])
9284 (define_insn ""
9285 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9286 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9287 (use (match_operand:SI 2 "immediate_operand" "i"))
9288 (use (match_operand:SI 3 "immediate_operand" "i"))
9289 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9290 (clobber (reg:SI 6))
9291 (clobber (reg:SI 7))
9292 (clobber (reg:SI 8))
9293 (clobber (reg:SI 9))
9294 (clobber (reg:SI 10))
9295 (clobber (match_scratch:SI 5 "X"))]
9296 "TARGET_STRING && ! TARGET_POWER
9297 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9298 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9299 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9300 && REGNO (operands[4]) == 5"
9301 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9302 [(set_attr "type" "load")
9303 (set_attr "length" "8")])
9305 (define_insn ""
9306 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9307 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9308 (use (match_operand:SI 2 "immediate_operand" "i"))
9309 (use (match_operand:SI 3 "immediate_operand" "i"))
9310 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9311 (clobber (reg:SI 6))
9312 (clobber (reg:SI 7))
9313 (clobber (reg:SI 8))
9314 (clobber (reg:SI 9))
9315 (clobber (reg:SI 10))
9316 (clobber (match_scratch:SI 5 "X"))]
9317 "TARGET_STRING && TARGET_POWERPC64
9318 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9319 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9320 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9321 && REGNO (operands[4]) == 5"
9322 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9323 [(set_attr "type" "load")
9324 (set_attr "length" "8")])
9326 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9327 ;; problems with TImode.
9328 ;; rD/rS = r5 is preferred, efficient form.
9329 (define_expand "movmemsi_4reg"
9330 [(parallel [(set (match_operand 0 "" "")
9331 (match_operand 1 "" ""))
9332 (use (match_operand 2 "" ""))
9333 (use (match_operand 3 "" ""))
9334 (clobber (reg:SI 5))
9335 (clobber (reg:SI 6))
9336 (clobber (reg:SI 7))
9337 (clobber (reg:SI 8))
9338 (clobber (match_scratch:SI 4 ""))])]
9339 "TARGET_STRING"
9340 "")
9342 (define_insn ""
9343 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9344 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9345 (use (match_operand:SI 2 "immediate_operand" "i"))
9346 (use (match_operand:SI 3 "immediate_operand" "i"))
9347 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9348 (clobber (reg:SI 6))
9349 (clobber (reg:SI 7))
9350 (clobber (reg:SI 8))
9351 (clobber (match_scratch:SI 5 "=q"))]
9352 "TARGET_STRING && TARGET_POWER
9353 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9354 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9355 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9356 && REGNO (operands[4]) == 5"
9357 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9358 [(set_attr "type" "load")
9359 (set_attr "length" "8")])
9361 (define_insn ""
9362 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9363 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9364 (use (match_operand:SI 2 "immediate_operand" "i"))
9365 (use (match_operand:SI 3 "immediate_operand" "i"))
9366 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9367 (clobber (reg:SI 6))
9368 (clobber (reg:SI 7))
9369 (clobber (reg:SI 8))
9370 (clobber (match_scratch:SI 5 "X"))]
9371 "TARGET_STRING && ! TARGET_POWER
9372 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9373 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9374 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9375 && REGNO (operands[4]) == 5"
9376 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9377 [(set_attr "type" "load")
9378 (set_attr "length" "8")])
9380 (define_insn ""
9381 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9382 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9383 (use (match_operand:SI 2 "immediate_operand" "i"))
9384 (use (match_operand:SI 3 "immediate_operand" "i"))
9385 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9386 (clobber (reg:SI 6))
9387 (clobber (reg:SI 7))
9388 (clobber (reg:SI 8))
9389 (clobber (match_scratch:SI 5 "X"))]
9390 "TARGET_STRING && TARGET_POWERPC64
9391 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9392 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9393 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9394 && REGNO (operands[4]) == 5"
9395 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9396 [(set_attr "type" "load")
9397 (set_attr "length" "8")])
9399 ;; Move up to 8 bytes at a time.
9400 (define_expand "movmemsi_2reg"
9401 [(parallel [(set (match_operand 0 "" "")
9402 (match_operand 1 "" ""))
9403 (use (match_operand 2 "" ""))
9404 (use (match_operand 3 "" ""))
9405 (clobber (match_scratch:DI 4 ""))
9406 (clobber (match_scratch:SI 5 ""))])]
9407 "TARGET_STRING && ! TARGET_POWERPC64"
9408 "")
9410 (define_insn ""
9411 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9412 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9413 (use (match_operand:SI 2 "immediate_operand" "i"))
9414 (use (match_operand:SI 3 "immediate_operand" "i"))
9415 (clobber (match_scratch:DI 4 "=&r"))
9416 (clobber (match_scratch:SI 5 "=q"))]
9417 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9418 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9419 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9420 [(set_attr "type" "load")
9421 (set_attr "length" "8")])
9423 (define_insn ""
9424 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9425 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9426 (use (match_operand:SI 2 "immediate_operand" "i"))
9427 (use (match_operand:SI 3 "immediate_operand" "i"))
9428 (clobber (match_scratch:DI 4 "=&r"))
9429 (clobber (match_scratch:SI 5 "X"))]
9430 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9431 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9432 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9433 [(set_attr "type" "load")
9434 (set_attr "length" "8")])
9436 ;; Move up to 4 bytes at a time.
9437 (define_expand "movmemsi_1reg"
9438 [(parallel [(set (match_operand 0 "" "")
9439 (match_operand 1 "" ""))
9440 (use (match_operand 2 "" ""))
9441 (use (match_operand 3 "" ""))
9442 (clobber (match_scratch:SI 4 ""))
9443 (clobber (match_scratch:SI 5 ""))])]
9444 "TARGET_STRING"
9445 "")
9447 (define_insn ""
9448 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9449 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9450 (use (match_operand:SI 2 "immediate_operand" "i"))
9451 (use (match_operand:SI 3 "immediate_operand" "i"))
9452 (clobber (match_scratch:SI 4 "=&r"))
9453 (clobber (match_scratch:SI 5 "=q"))]
9454 "TARGET_STRING && TARGET_POWER
9455 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9456 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9457 [(set_attr "type" "load")
9458 (set_attr "length" "8")])
9460 (define_insn ""
9461 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9462 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9463 (use (match_operand:SI 2 "immediate_operand" "i"))
9464 (use (match_operand:SI 3 "immediate_operand" "i"))
9465 (clobber (match_scratch:SI 4 "=&r"))
9466 (clobber (match_scratch:SI 5 "X"))]
9467 "TARGET_STRING && ! TARGET_POWER
9468 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9469 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9470 [(set_attr "type" "load")
9471 (set_attr "length" "8")])
9473 (define_insn ""
9474 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9475 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9476 (use (match_operand:SI 2 "immediate_operand" "i"))
9477 (use (match_operand:SI 3 "immediate_operand" "i"))
9478 (clobber (match_scratch:SI 4 "=&r"))
9479 (clobber (match_scratch:SI 5 "X"))]
9480 "TARGET_STRING && TARGET_POWERPC64
9481 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9482 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9483 [(set_attr "type" "load")
9484 (set_attr "length" "8")])
9486 \f
9487 ;; Define insns that do load or store with update. Some of these we can
9488 ;; get by using pre-decrement or pre-increment, but the hardware can also
9489 ;; do cases where the increment is not the size of the object.
9490 ;;
9491 ;; In all these cases, we use operands 0 and 1 for the register being
9492 ;; incremented because those are the operands that local-alloc will
9493 ;; tie and these are the pair most likely to be tieable (and the ones
9494 ;; that will benefit the most).
9496 (define_insn "*movdi_update1"
9497 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9498 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9499 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9500 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9501 (plus:DI (match_dup 1) (match_dup 2)))]
9502 "TARGET_POWERPC64 && TARGET_UPDATE"
9503 "@
9504 ldux %3,%0,%2
9505 ldu %3,%2(%0)"
9506 [(set_attr "type" "load_ux,load_u")])
9508 (define_insn "movdi_<mode>_update"
9509 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9510 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9511 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9512 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9513 (plus:P (match_dup 1) (match_dup 2)))]
9514 "TARGET_POWERPC64 && TARGET_UPDATE"
9515 "@
9516 stdux %3,%0,%2
9517 stdu %3,%2(%0)"
9518 [(set_attr "type" "store_ux,store_u")])
9520 (define_insn "*movsi_update1"
9521 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9522 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9523 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9524 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9525 (plus:SI (match_dup 1) (match_dup 2)))]
9526 "TARGET_UPDATE"
9527 "@
9528 {lux|lwzux} %3,%0,%2
9529 {lu|lwzu} %3,%2(%0)"
9530 [(set_attr "type" "load_ux,load_u")])
9532 (define_insn "*movsi_update2"
9533 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9534 (sign_extend:DI
9535 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9536 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9537 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9538 (plus:DI (match_dup 1) (match_dup 2)))]
9539 "TARGET_POWERPC64"
9540 "lwaux %3,%0,%2"
9541 [(set_attr "type" "load_ext_ux")])
9543 (define_insn "movsi_update"
9544 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9545 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9546 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9547 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9548 (plus:SI (match_dup 1) (match_dup 2)))]
9549 "TARGET_UPDATE"
9550 "@
9551 {stux|stwux} %3,%0,%2
9552 {stu|stwu} %3,%2(%0)"
9553 [(set_attr "type" "store_ux,store_u")])
9555 (define_insn "*movhi_update1"
9556 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9557 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9558 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9559 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9560 (plus:SI (match_dup 1) (match_dup 2)))]
9561 "TARGET_UPDATE"
9562 "@
9563 lhzux %3,%0,%2
9564 lhzu %3,%2(%0)"
9565 [(set_attr "type" "load_ux,load_u")])
9567 (define_insn "*movhi_update2"
9568 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9569 (zero_extend:SI
9570 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9571 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9572 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9573 (plus:SI (match_dup 1) (match_dup 2)))]
9574 "TARGET_UPDATE"
9575 "@
9576 lhzux %3,%0,%2
9577 lhzu %3,%2(%0)"
9578 [(set_attr "type" "load_ux,load_u")])
9580 (define_insn "*movhi_update3"
9581 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9582 (sign_extend:SI
9583 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9584 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9585 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9586 (plus:SI (match_dup 1) (match_dup 2)))]
9587 "TARGET_UPDATE"
9588 "@
9589 lhaux %3,%0,%2
9590 lhau %3,%2(%0)"
9591 [(set_attr "type" "load_ext_ux,load_ext_u")])
9593 (define_insn "*movhi_update4"
9594 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9595 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9596 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9597 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9598 (plus:SI (match_dup 1) (match_dup 2)))]
9599 "TARGET_UPDATE"
9600 "@
9601 sthux %3,%0,%2
9602 sthu %3,%2(%0)"
9603 [(set_attr "type" "store_ux,store_u")])
9605 (define_insn "*movqi_update1"
9606 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9607 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9608 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9609 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9610 (plus:SI (match_dup 1) (match_dup 2)))]
9611 "TARGET_UPDATE"
9612 "@
9613 lbzux %3,%0,%2
9614 lbzu %3,%2(%0)"
9615 [(set_attr "type" "load_ux,load_u")])
9617 (define_insn "*movqi_update2"
9618 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9619 (zero_extend:SI
9620 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9621 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9622 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9623 (plus:SI (match_dup 1) (match_dup 2)))]
9624 "TARGET_UPDATE"
9625 "@
9626 lbzux %3,%0,%2
9627 lbzu %3,%2(%0)"
9628 [(set_attr "type" "load_ux,load_u")])
9630 (define_insn "*movqi_update3"
9631 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9632 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9633 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9634 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9635 (plus:SI (match_dup 1) (match_dup 2)))]
9636 "TARGET_UPDATE"
9637 "@
9638 stbux %3,%0,%2
9639 stbu %3,%2(%0)"
9640 [(set_attr "type" "store_ux,store_u")])
9642 (define_insn "*movsf_update1"
9643 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9644 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9645 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9646 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9647 (plus:SI (match_dup 1) (match_dup 2)))]
9648 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9649 "@
9650 lfsux %3,%0,%2
9651 lfsu %3,%2(%0)"
9652 [(set_attr "type" "fpload_ux,fpload_u")])
9654 (define_insn "*movsf_update2"
9655 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9656 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9657 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9658 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9659 (plus:SI (match_dup 1) (match_dup 2)))]
9660 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9661 "@
9662 stfsux %3,%0,%2
9663 stfsu %3,%2(%0)"
9664 [(set_attr "type" "fpstore_ux,fpstore_u")])
9666 (define_insn "*movsf_update3"
9667 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9668 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9669 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9670 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9671 (plus:SI (match_dup 1) (match_dup 2)))]
9672 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9673 "@
9674 {lux|lwzux} %3,%0,%2
9675 {lu|lwzu} %3,%2(%0)"
9676 [(set_attr "type" "load_ux,load_u")])
9678 (define_insn "*movsf_update4"
9679 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9680 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9681 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9682 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9683 (plus:SI (match_dup 1) (match_dup 2)))]
9684 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9685 "@
9686 {stux|stwux} %3,%0,%2
9687 {stu|stwu} %3,%2(%0)"
9688 [(set_attr "type" "store_ux,store_u")])
9690 (define_insn "*movdf_update1"
9691 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9692 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9693 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9694 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9695 (plus:SI (match_dup 1) (match_dup 2)))]
9696 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9697 "@
9698 lfdux %3,%0,%2
9699 lfdu %3,%2(%0)"
9700 [(set_attr "type" "fpload_ux,fpload_u")])
9702 (define_insn "*movdf_update2"
9703 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9704 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9705 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9706 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9707 (plus:SI (match_dup 1) (match_dup 2)))]
9708 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9709 "@
9710 stfdux %3,%0,%2
9711 stfdu %3,%2(%0)"
9712 [(set_attr "type" "fpstore_ux,fpstore_u")])
9714 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9716 (define_insn "*lfq_power2"
9717 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9718 (match_operand:TF 1 "memory_operand" ""))]
9719 "TARGET_POWER2
9720 && TARGET_HARD_FLOAT && TARGET_FPRS"
9721 "lfq%U1%X1 %0,%1")
9723 (define_peephole2
9724 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9725 (match_operand:DF 1 "memory_operand" ""))
9726 (set (match_operand:DF 2 "gpc_reg_operand" "")
9727 (match_operand:DF 3 "memory_operand" ""))]
9728 "TARGET_POWER2
9729 && TARGET_HARD_FLOAT && TARGET_FPRS
9730 && registers_ok_for_quad_peep (operands[0], operands[2])
9731 && mems_ok_for_quad_peep (operands[1], operands[3])"
9732 [(set (match_dup 0)
9733 (match_dup 1))]
9734 "operands[1] = widen_memory_access (operands[1], TFmode, 0);
9735 operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
9737 (define_insn "*stfq_power2"
9738 [(set (match_operand:TF 0 "memory_operand" "")
9739 (match_operand:TF 1 "gpc_reg_operand" "f"))]
9740 "TARGET_POWER2
9741 && TARGET_HARD_FLOAT && TARGET_FPRS"
9742 "stfq%U0%X0 %1,%0")
9745 (define_peephole2
9746 [(set (match_operand:DF 0 "memory_operand" "")
9747 (match_operand:DF 1 "gpc_reg_operand" ""))
9748 (set (match_operand:DF 2 "memory_operand" "")
9749 (match_operand:DF 3 "gpc_reg_operand" ""))]
9750 "TARGET_POWER2
9751 && TARGET_HARD_FLOAT && TARGET_FPRS
9752 && registers_ok_for_quad_peep (operands[1], operands[3])
9753 && mems_ok_for_quad_peep (operands[0], operands[2])"
9754 [(set (match_dup 0)
9755 (match_dup 1))]
9756 "operands[0] = widen_memory_access (operands[0], TFmode, 0);
9757 operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
9759 ;; after inserting conditional returns we can sometimes have
9760 ;; unnecessary register moves. Unfortunately we cannot have a
9761 ;; modeless peephole here, because some single SImode sets have early
9762 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9763 ;; sequences, using get_attr_length here will smash the operands
9764 ;; array. Neither is there an early_cobbler_p predicate.
9765 (define_peephole2
9766 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9767 (match_operand:DF 1 "any_operand" ""))
9768 (set (match_operand:DF 2 "gpc_reg_operand" "")
9769 (match_dup 0))]
9770 "peep2_reg_dead_p (2, operands[0])"
9771 [(set (match_dup 2) (match_dup 1))])
9773 (define_peephole2
9774 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9775 (match_operand:SF 1 "any_operand" ""))
9776 (set (match_operand:SF 2 "gpc_reg_operand" "")
9777 (match_dup 0))]
9778 "peep2_reg_dead_p (2, operands[0])"
9779 [(set (match_dup 2) (match_dup 1))])
9781 \f
9782 ;; TLS support.
9784 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9785 (define_insn "tls_gd_32"
9786 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9787 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9788 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9789 UNSPEC_TLSGD))]
9790 "HAVE_AS_TLS && !TARGET_64BIT"
9791 "addi %0,%1,%2@got@tlsgd")
9793 (define_insn "tls_gd_64"
9794 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9795 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9796 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9797 UNSPEC_TLSGD))]
9798 "HAVE_AS_TLS && TARGET_64BIT"
9799 "addi %0,%1,%2@got@tlsgd")
9801 (define_insn "tls_ld_32"
9802 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9803 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9804 UNSPEC_TLSLD))]
9805 "HAVE_AS_TLS && !TARGET_64BIT"
9806 "addi %0,%1,%&@got@tlsld")
9808 (define_insn "tls_ld_64"
9809 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9810 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9811 UNSPEC_TLSLD))]
9812 "HAVE_AS_TLS && TARGET_64BIT"
9813 "addi %0,%1,%&@got@tlsld")
9815 (define_insn "tls_dtprel_32"
9816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9817 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9818 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9819 UNSPEC_TLSDTPREL))]
9820 "HAVE_AS_TLS && !TARGET_64BIT"
9821 "addi %0,%1,%2@dtprel")
9823 (define_insn "tls_dtprel_64"
9824 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9825 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9826 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9827 UNSPEC_TLSDTPREL))]
9828 "HAVE_AS_TLS && TARGET_64BIT"
9829 "addi %0,%1,%2@dtprel")
9831 (define_insn "tls_dtprel_ha_32"
9832 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9833 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9834 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9835 UNSPEC_TLSDTPRELHA))]
9836 "HAVE_AS_TLS && !TARGET_64BIT"
9837 "addis %0,%1,%2@dtprel@ha")
9839 (define_insn "tls_dtprel_ha_64"
9840 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9841 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9842 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9843 UNSPEC_TLSDTPRELHA))]
9844 "HAVE_AS_TLS && TARGET_64BIT"
9845 "addis %0,%1,%2@dtprel@ha")
9847 (define_insn "tls_dtprel_lo_32"
9848 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9849 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9850 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9851 UNSPEC_TLSDTPRELLO))]
9852 "HAVE_AS_TLS && !TARGET_64BIT"
9853 "addi %0,%1,%2@dtprel@l")
9855 (define_insn "tls_dtprel_lo_64"
9856 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9857 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9858 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9859 UNSPEC_TLSDTPRELLO))]
9860 "HAVE_AS_TLS && TARGET_64BIT"
9861 "addi %0,%1,%2@dtprel@l")
9863 (define_insn "tls_got_dtprel_32"
9864 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9865 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9866 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9867 UNSPEC_TLSGOTDTPREL))]
9868 "HAVE_AS_TLS && !TARGET_64BIT"
9869 "lwz %0,%2@got@dtprel(%1)")
9871 (define_insn "tls_got_dtprel_64"
9872 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9873 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9874 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9875 UNSPEC_TLSGOTDTPREL))]
9876 "HAVE_AS_TLS && TARGET_64BIT"
9877 "ld %0,%2@got@dtprel(%1)")
9879 (define_insn "tls_tprel_32"
9880 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9881 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9882 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9883 UNSPEC_TLSTPREL))]
9884 "HAVE_AS_TLS && !TARGET_64BIT"
9885 "addi %0,%1,%2@tprel")
9887 (define_insn "tls_tprel_64"
9888 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9889 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9890 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9891 UNSPEC_TLSTPREL))]
9892 "HAVE_AS_TLS && TARGET_64BIT"
9893 "addi %0,%1,%2@tprel")
9895 (define_insn "tls_tprel_ha_32"
9896 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9897 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9898 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9899 UNSPEC_TLSTPRELHA))]
9900 "HAVE_AS_TLS && !TARGET_64BIT"
9901 "addis %0,%1,%2@tprel@ha")
9903 (define_insn "tls_tprel_ha_64"
9904 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9905 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9906 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9907 UNSPEC_TLSTPRELHA))]
9908 "HAVE_AS_TLS && TARGET_64BIT"
9909 "addis %0,%1,%2@tprel@ha")
9911 (define_insn "tls_tprel_lo_32"
9912 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9913 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9914 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9915 UNSPEC_TLSTPRELLO))]
9916 "HAVE_AS_TLS && !TARGET_64BIT"
9917 "addi %0,%1,%2@tprel@l")
9919 (define_insn "tls_tprel_lo_64"
9920 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9921 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9922 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9923 UNSPEC_TLSTPRELLO))]
9924 "HAVE_AS_TLS && TARGET_64BIT"
9925 "addi %0,%1,%2@tprel@l")
9927 ;; "b" output constraint here and on tls_tls input to support linker tls
9928 ;; optimization. The linker may edit the instructions emitted by a
9929 ;; tls_got_tprel/tls_tls pair to addis,addi.
9930 (define_insn "tls_got_tprel_32"
9931 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9932 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9933 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9934 UNSPEC_TLSGOTTPREL))]
9935 "HAVE_AS_TLS && !TARGET_64BIT"
9936 "lwz %0,%2@got@tprel(%1)")
9938 (define_insn "tls_got_tprel_64"
9939 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9940 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9941 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9942 UNSPEC_TLSGOTTPREL))]
9943 "HAVE_AS_TLS && TARGET_64BIT"
9944 "ld %0,%2@got@tprel(%1)")
9946 (define_insn "tls_tls_32"
9947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9948 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9949 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9950 UNSPEC_TLSTLS))]
9951 "HAVE_AS_TLS && !TARGET_64BIT"
9952 "add %0,%1,%2@tls")
9954 (define_insn "tls_tls_64"
9955 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9956 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9957 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9958 UNSPEC_TLSTLS))]
9959 "HAVE_AS_TLS && TARGET_64BIT"
9960 "add %0,%1,%2@tls")
9961 \f
9962 ;; Next come insns related to the calling sequence.
9963 ;;
9964 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9965 ;; We move the back-chain and decrement the stack pointer.
9967 (define_expand "allocate_stack"
9968 [(set (match_operand 0 "gpc_reg_operand" "=r")
9969 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9970 (set (reg 1)
9971 (minus (reg 1) (match_dup 1)))]
9972 ""
9973 "
9974 { rtx chain = gen_reg_rtx (Pmode);
9975 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9976 rtx neg_op0;
9978 emit_move_insn (chain, stack_bot);
9980 /* Check stack bounds if necessary. */
9981 if (current_function_limit_stack)
9982 {
9983 rtx available;
9984 available = expand_binop (Pmode, sub_optab,
9985 stack_pointer_rtx, stack_limit_rtx,
9986 NULL_RTX, 1, OPTAB_WIDEN);
9987 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9988 }
9990 if (GET_CODE (operands[1]) != CONST_INT
9991 || INTVAL (operands[1]) < -32767
9992 || INTVAL (operands[1]) > 32768)
9993 {
9994 neg_op0 = gen_reg_rtx (Pmode);
9995 if (TARGET_32BIT)
9996 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9997 else
9998 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9999 }
10000 else
10001 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10003 if (TARGET_UPDATE)
10004 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10005 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10007 else
10008 {
10009 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10010 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10011 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10012 }
10014 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10015 DONE;
10016 }")
10018 ;; These patterns say how to save and restore the stack pointer. We need not
10019 ;; save the stack pointer at function level since we are careful to
10020 ;; preserve the backchain. At block level, we have to restore the backchain
10021 ;; when we restore the stack pointer.
10022 ;;
10023 ;; For nonlocal gotos, we must save both the stack pointer and its
10024 ;; backchain and restore both. Note that in the nonlocal case, the
10025 ;; save area is a memory location.
10027 (define_expand "save_stack_function"
10028 [(match_operand 0 "any_operand" "")
10029 (match_operand 1 "any_operand" "")]
10030 ""
10031 "DONE;")
10033 (define_expand "restore_stack_function"
10034 [(match_operand 0 "any_operand" "")
10035 (match_operand 1 "any_operand" "")]
10036 ""
10037 "DONE;")
10039 (define_expand "restore_stack_block"
10040 [(use (match_operand 0 "register_operand" ""))
10041 (set (match_dup 2) (match_dup 3))
10042 (set (match_dup 0) (match_operand 1 "register_operand" ""))
10043 (set (match_dup 3) (match_dup 2))]
10044 ""
10045 "
10046 {
10047 operands[2] = gen_reg_rtx (Pmode);
10048 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
10049 }")
10051 (define_expand "save_stack_nonlocal"
10052 [(match_operand 0 "memory_operand" "")
10053 (match_operand 1 "register_operand" "")]
10054 ""
10055 "
10056 {
10057 rtx temp = gen_reg_rtx (Pmode);
10058 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10060 /* Copy the backchain to the first word, sp to the second. */
10061 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
10062 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
10063 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
10064 operands[1]);
10065 DONE;
10066 }")
10068 (define_expand "restore_stack_nonlocal"
10069 [(match_operand 0 "register_operand" "")
10070 (match_operand 1 "memory_operand" "")]
10071 ""
10072 "
10073 {
10074 rtx temp = gen_reg_rtx (Pmode);
10075 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10077 /* Restore the backchain from the first word, sp from the second. */
10078 emit_move_insn (temp,
10079 adjust_address_nv (operands[1], Pmode, 0));
10080 emit_move_insn (operands[0],
10081 adjust_address_nv (operands[1], Pmode, units_per_word));
10082 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
10083 DONE;
10084 }")
10085 \f
10086 ;; TOC register handling.
10088 ;; Code to initialize the TOC register...
10090 (define_insn "load_toc_aix_si"
10091 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10092 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10093 (use (reg:SI 2))])]
10094 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10095 "*
10096 {
10097 char buf[30];
10098 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10099 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10100 operands[2] = gen_rtx_REG (Pmode, 2);
10101 return \"{l|lwz} %0,%1(%2)\";
10102 }"
10103 [(set_attr "type" "load")])
10105 (define_insn "load_toc_aix_di"
10106 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10107 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10108 (use (reg:DI 2))])]
10109 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10110 "*
10111 {
10112 char buf[30];
10113 #ifdef TARGET_RELOCATABLE
10114 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10115 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10116 #else
10117 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10118 #endif
10119 if (TARGET_ELF)
10120 strcat (buf, \"@toc\");
10121 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10122 operands[2] = gen_rtx_REG (Pmode, 2);
10123 return \"ld %0,%1(%2)\";
10124 }"
10125 [(set_attr "type" "load")])
10127 (define_insn "load_toc_v4_pic_si"
10128 [(set (match_operand:SI 0 "register_operand" "=l")
10129 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10130 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10131 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10132 [(set_attr "type" "branch")
10133 (set_attr "length" "4")])
10135 (define_insn "load_toc_v4_PIC_1"
10136 [(set (match_operand:SI 0 "register_operand" "=l")
10137 (match_operand:SI 1 "immediate_operand" "s"))
10138 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10139 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10140 "bcl 20,31,%1\\n%1:"
10141 [(set_attr "type" "branch")
10142 (set_attr "length" "4")])
10144 (define_insn "load_toc_v4_PIC_1b"
10145 [(set (match_operand:SI 0 "register_operand" "=l")
10146 (match_operand:SI 1 "immediate_operand" "s"))
10147 (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
10148 UNSPEC_TOCPTR))]
10149 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10150 "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1"
10151 [(set_attr "type" "branch")
10152 (set_attr "length" "8")])
10154 (define_insn "load_toc_v4_PIC_2"
10155 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10156 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10157 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10158 (match_operand:SI 3 "immediate_operand" "s")))))]
10159 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10160 "{l|lwz} %0,%2-%3(%1)"
10161 [(set_attr "type" "load")])
10164 ;; If the TOC is shared over a translation unit, as happens with all
10165 ;; the kinds of PIC that we support, we need to restore the TOC
10166 ;; pointer only when jumping over units of translation.
10167 ;; On Darwin, we need to reload the picbase.
10169 (define_expand "builtin_setjmp_receiver"
10170 [(use (label_ref (match_operand 0 "" "")))]
10171 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10172 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10173 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10174 "
10175 {
10176 #if TARGET_MACHO
10177 if (DEFAULT_ABI == ABI_DARWIN)
10178 {
10179 const char *picbase = machopic_function_base_name ();
10180 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10181 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10182 rtx tmplabrtx;
10183 char tmplab[20];
10185 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10186 CODE_LABEL_NUMBER (operands[0]));
10187 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10189 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10190 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10191 }
10192 else
10193 #endif
10194 rs6000_emit_load_toc_table (FALSE);
10195 DONE;
10196 }")
10197 \f
10198 ;; A function pointer under AIX is a pointer to a data area whose first word
10199 ;; contains the actual address of the function, whose second word contains a
10200 ;; pointer to its TOC, and whose third word contains a value to place in the
10201 ;; static chain register (r11). Note that if we load the static chain, our
10202 ;; "trampoline" need not have any executable code.
10204 (define_expand "call_indirect_aix32"
10205 [(set (match_dup 2)
10206 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10207 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10208 (reg:SI 2))
10209 (set (reg:SI 2)
10210 (mem:SI (plus:SI (match_dup 0)
10211 (const_int 4))))
10212 (set (reg:SI 11)
10213 (mem:SI (plus:SI (match_dup 0)
10214 (const_int 8))))
10215 (parallel [(call (mem:SI (match_dup 2))
10216 (match_operand 1 "" ""))
10217 (use (reg:SI 2))
10218 (use (reg:SI 11))
10219 (set (reg:SI 2)
10220 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10221 (clobber (scratch:SI))])]
10222 "TARGET_32BIT"
10223 "
10224 { operands[2] = gen_reg_rtx (SImode); }")
10226 (define_expand "call_indirect_aix64"
10227 [(set (match_dup 2)
10228 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10229 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10230 (reg:DI 2))
10231 (set (reg:DI 2)
10232 (mem:DI (plus:DI (match_dup 0)
10233 (const_int 8))))
10234 (set (reg:DI 11)
10235 (mem:DI (plus:DI (match_dup 0)
10236 (const_int 16))))
10237 (parallel [(call (mem:SI (match_dup 2))
10238 (match_operand 1 "" ""))
10239 (use (reg:DI 2))
10240 (use (reg:DI 11))
10241 (set (reg:DI 2)
10242 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10243 (clobber (scratch:SI))])]
10244 "TARGET_64BIT"
10245 "
10246 { operands[2] = gen_reg_rtx (DImode); }")
10248 (define_expand "call_value_indirect_aix32"
10249 [(set (match_dup 3)
10250 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10251 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10252 (reg:SI 2))
10253 (set (reg:SI 2)
10254 (mem:SI (plus:SI (match_dup 1)
10255 (const_int 4))))
10256 (set (reg:SI 11)
10257 (mem:SI (plus:SI (match_dup 1)
10258 (const_int 8))))
10259 (parallel [(set (match_operand 0 "" "")
10260 (call (mem:SI (match_dup 3))
10261 (match_operand 2 "" "")))
10262 (use (reg:SI 2))
10263 (use (reg:SI 11))
10264 (set (reg:SI 2)
10265 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10266 (clobber (scratch:SI))])]
10267 "TARGET_32BIT"
10268 "
10269 { operands[3] = gen_reg_rtx (SImode); }")
10271 (define_expand "call_value_indirect_aix64"
10272 [(set (match_dup 3)
10273 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10274 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10275 (reg:DI 2))
10276 (set (reg:DI 2)
10277 (mem:DI (plus:DI (match_dup 1)
10278 (const_int 8))))
10279 (set (reg:DI 11)
10280 (mem:DI (plus:DI (match_dup 1)
10281 (const_int 16))))
10282 (parallel [(set (match_operand 0 "" "")
10283 (call (mem:SI (match_dup 3))
10284 (match_operand 2 "" "")))
10285 (use (reg:DI 2))
10286 (use (reg:DI 11))
10287 (set (reg:DI 2)
10288 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10289 (clobber (scratch:SI))])]
10290 "TARGET_64BIT"
10291 "
10292 { operands[3] = gen_reg_rtx (DImode); }")
10294 ;; Now the definitions for the call and call_value insns
10295 (define_expand "call"
10296 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10297 (match_operand 1 "" ""))
10298 (use (match_operand 2 "" ""))
10299 (clobber (scratch:SI))])]
10300 ""
10301 "
10302 {
10303 #if TARGET_MACHO
10304 if (MACHOPIC_INDIRECT)
10305 operands[0] = machopic_indirect_call_target (operands[0]);
10306 #endif
10308 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10309 abort ();
10311 operands[0] = XEXP (operands[0], 0);
10313 if (GET_CODE (operands[0]) != SYMBOL_REF
10314 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10315 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10316 {
10317 if (INTVAL (operands[2]) & CALL_LONG)
10318 operands[0] = rs6000_longcall_ref (operands[0]);
10320 if (DEFAULT_ABI == ABI_V4
10321 || DEFAULT_ABI == ABI_DARWIN)
10322 operands[0] = force_reg (Pmode, operands[0]);
10324 else if (DEFAULT_ABI == ABI_AIX)
10325 {
10326 /* AIX function pointers are really pointers to a three word
10327 area. */
10328 emit_call_insn (TARGET_32BIT
10329 ? gen_call_indirect_aix32 (force_reg (SImode,
10330 operands[0]),
10331 operands[1])
10332 : gen_call_indirect_aix64 (force_reg (DImode,
10333 operands[0]),
10334 operands[1]));
10335 DONE;
10336 }
10337 else
10338 abort ();
10339 }
10340 }")
10342 (define_expand "call_value"
10343 [(parallel [(set (match_operand 0 "" "")
10344 (call (mem:SI (match_operand 1 "address_operand" ""))
10345 (match_operand 2 "" "")))
10346 (use (match_operand 3 "" ""))
10347 (clobber (scratch:SI))])]
10348 ""
10349 "
10350 {
10351 #if TARGET_MACHO
10352 if (MACHOPIC_INDIRECT)
10353 operands[1] = machopic_indirect_call_target (operands[1]);
10354 #endif
10356 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10357 abort ();
10359 operands[1] = XEXP (operands[1], 0);
10361 if (GET_CODE (operands[1]) != SYMBOL_REF
10362 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10363 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10364 {
10365 if (INTVAL (operands[3]) & CALL_LONG)
10366 operands[1] = rs6000_longcall_ref (operands[1]);
10368 if (DEFAULT_ABI == ABI_V4
10369 || DEFAULT_ABI == ABI_DARWIN)
10370 operands[1] = force_reg (Pmode, operands[1]);
10372 else if (DEFAULT_ABI == ABI_AIX)
10373 {
10374 /* AIX function pointers are really pointers to a three word
10375 area. */
10376 emit_call_insn (TARGET_32BIT
10377 ? gen_call_value_indirect_aix32 (operands[0],
10378 force_reg (SImode,
10379 operands[1]),
10380 operands[2])
10381 : gen_call_value_indirect_aix64 (operands[0],
10382 force_reg (DImode,
10383 operands[1]),
10384 operands[2]));
10385 DONE;
10386 }
10387 else
10388 abort ();
10389 }
10390 }")
10392 ;; Call to function in current module. No TOC pointer reload needed.
10393 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10394 ;; either the function was not prototyped, or it was prototyped as a
10395 ;; variable argument function. It is > 0 if FP registers were passed
10396 ;; and < 0 if they were not.
10398 (define_insn "*call_local32"
10399 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10400 (match_operand 1 "" "g,g"))
10401 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10402 (clobber (match_scratch:SI 3 "=l,l"))]
10403 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10404 "*
10405 {
10406 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10407 output_asm_insn (\"crxor 6,6,6\", operands);
10409 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10410 output_asm_insn (\"creqv 6,6,6\", operands);
10412 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10413 }"
10414 [(set_attr "type" "branch")
10415 (set_attr "length" "4,8")])
10417 (define_insn "*call_local64"
10418 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10419 (match_operand 1 "" "g,g"))
10420 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10421 (clobber (match_scratch:SI 3 "=l,l"))]
10422 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10423 "*
10424 {
10425 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10426 output_asm_insn (\"crxor 6,6,6\", operands);
10428 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10429 output_asm_insn (\"creqv 6,6,6\", operands);
10431 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10432 }"
10433 [(set_attr "type" "branch")
10434 (set_attr "length" "4,8")])
10436 (define_insn "*call_value_local32"
10437 [(set (match_operand 0 "" "")
10438 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10439 (match_operand 2 "" "g,g")))
10440 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10441 (clobber (match_scratch:SI 4 "=l,l"))]
10442 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10443 "*
10444 {
10445 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10446 output_asm_insn (\"crxor 6,6,6\", operands);
10448 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10449 output_asm_insn (\"creqv 6,6,6\", operands);
10451 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10452 }"
10453 [(set_attr "type" "branch")
10454 (set_attr "length" "4,8")])
10457 (define_insn "*call_value_local64"
10458 [(set (match_operand 0 "" "")
10459 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10460 (match_operand 2 "" "g,g")))
10461 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10462 (clobber (match_scratch:SI 4 "=l,l"))]
10463 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10464 "*
10465 {
10466 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10467 output_asm_insn (\"crxor 6,6,6\", operands);
10469 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10470 output_asm_insn (\"creqv 6,6,6\", operands);
10472 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10473 }"
10474 [(set_attr "type" "branch")
10475 (set_attr "length" "4,8")])
10477 ;; Call to function which may be in another module. Restore the TOC
10478 ;; pointer (r2) after the call unless this is System V.
10479 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10480 ;; either the function was not prototyped, or it was prototyped as a
10481 ;; variable argument function. It is > 0 if FP registers were passed
10482 ;; and < 0 if they were not.
10484 (define_insn "*call_indirect_nonlocal_aix32"
10485 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10486 (match_operand 1 "" "g"))
10487 (use (reg:SI 2))
10488 (use (reg:SI 11))
10489 (set (reg:SI 2)
10490 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10491 (clobber (match_scratch:SI 2 "=l"))]
10492 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10493 "b%T0l\;{l|lwz} 2,20(1)"
10494 [(set_attr "type" "jmpreg")
10495 (set_attr "length" "8")])
10497 (define_insn "*call_nonlocal_aix32"
10498 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10499 (match_operand 1 "" "g"))
10500 (use (match_operand:SI 2 "immediate_operand" "O"))
10501 (clobber (match_scratch:SI 3 "=l"))]
10502 "TARGET_32BIT
10503 && DEFAULT_ABI == ABI_AIX
10504 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10505 "bl %z0\;%."
10506 [(set_attr "type" "branch")
10507 (set_attr "length" "8")])
10509 (define_insn "*call_indirect_nonlocal_aix64"
10510 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10511 (match_operand 1 "" "g"))
10512 (use (reg:DI 2))
10513 (use (reg:DI 11))
10514 (set (reg:DI 2)
10515 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10516 (clobber (match_scratch:SI 2 "=l"))]
10517 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10518 "b%T0l\;ld 2,40(1)"
10519 [(set_attr "type" "jmpreg")
10520 (set_attr "length" "8")])
10522 (define_insn "*call_nonlocal_aix64"
10523 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10524 (match_operand 1 "" "g"))
10525 (use (match_operand:SI 2 "immediate_operand" "O"))
10526 (clobber (match_scratch:SI 3 "=l"))]
10527 "TARGET_64BIT
10528 && DEFAULT_ABI == ABI_AIX
10529 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10530 "bl %z0\;%."
10531 [(set_attr "type" "branch")
10532 (set_attr "length" "8")])
10534 (define_insn "*call_value_indirect_nonlocal_aix32"
10535 [(set (match_operand 0 "" "")
10536 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10537 (match_operand 2 "" "g")))
10538 (use (reg:SI 2))
10539 (use (reg:SI 11))
10540 (set (reg:SI 2)
10541 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10542 (clobber (match_scratch:SI 3 "=l"))]
10543 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10544 "b%T1l\;{l|lwz} 2,20(1)"
10545 [(set_attr "type" "jmpreg")
10546 (set_attr "length" "8")])
10548 (define_insn "*call_value_nonlocal_aix32"
10549 [(set (match_operand 0 "" "")
10550 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10551 (match_operand 2 "" "g")))
10552 (use (match_operand:SI 3 "immediate_operand" "O"))
10553 (clobber (match_scratch:SI 4 "=l"))]
10554 "TARGET_32BIT
10555 && DEFAULT_ABI == ABI_AIX
10556 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10557 "bl %z1\;%."
10558 [(set_attr "type" "branch")
10559 (set_attr "length" "8")])
10561 (define_insn "*call_value_indirect_nonlocal_aix64"
10562 [(set (match_operand 0 "" "")
10563 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10564 (match_operand 2 "" "g")))
10565 (use (reg:DI 2))
10566 (use (reg:DI 11))
10567 (set (reg:DI 2)
10568 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10569 (clobber (match_scratch:SI 3 "=l"))]
10570 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10571 "b%T1l\;ld 2,40(1)"
10572 [(set_attr "type" "jmpreg")
10573 (set_attr "length" "8")])
10575 (define_insn "*call_value_nonlocal_aix64"
10576 [(set (match_operand 0 "" "")
10577 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10578 (match_operand 2 "" "g")))
10579 (use (match_operand:SI 3 "immediate_operand" "O"))
10580 (clobber (match_scratch:SI 4 "=l"))]
10581 "TARGET_64BIT
10582 && DEFAULT_ABI == ABI_AIX
10583 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10584 "bl %z1\;%."
10585 [(set_attr "type" "branch")
10586 (set_attr "length" "8")])
10588 ;; A function pointer under System V is just a normal pointer
10589 ;; operands[0] is the function pointer
10590 ;; operands[1] is the stack size to clean up
10591 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10592 ;; which indicates how to set cr1
10594 (define_insn "*call_indirect_nonlocal_sysv"
10595 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10596 (match_operand 1 "" "g,g"))
10597 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10598 (clobber (match_scratch:SI 3 "=l,l"))]
10599 "DEFAULT_ABI == ABI_V4
10600 || DEFAULT_ABI == ABI_DARWIN"
10601 {
10602 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10603 output_asm_insn ("crxor 6,6,6", operands);
10605 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10606 output_asm_insn ("creqv 6,6,6", operands);
10608 return "b%T0l";
10609 }
10610 [(set_attr "type" "jmpreg,jmpreg")
10611 (set_attr "length" "4,8")])
10613 (define_insn "*call_nonlocal_sysv"
10614 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10615 (match_operand 1 "" "g,g"))
10616 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10617 (clobber (match_scratch:SI 3 "=l,l"))]
10618 "(DEFAULT_ABI == ABI_DARWIN
10619 || (DEFAULT_ABI == ABI_V4
10620 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10621 {
10622 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10623 output_asm_insn ("crxor 6,6,6", operands);
10625 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10626 output_asm_insn ("creqv 6,6,6", operands);
10628 #if TARGET_MACHO
10629 return output_call(insn, operands, 0, 2);
10630 #else
10631 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10632 #endif
10633 }
10634 [(set_attr "type" "branch,branch")
10635 (set_attr "length" "4,8")])
10637 (define_insn "*call_value_indirect_nonlocal_sysv"
10638 [(set (match_operand 0 "" "")
10639 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10640 (match_operand 2 "" "g,g")))
10641 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10642 (clobber (match_scratch:SI 4 "=l,l"))]
10643 "DEFAULT_ABI == ABI_V4
10644 || DEFAULT_ABI == ABI_DARWIN"
10645 {
10646 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10647 output_asm_insn ("crxor 6,6,6", operands);
10649 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10650 output_asm_insn ("creqv 6,6,6", operands);
10652 return "b%T1l";
10653 }
10654 [(set_attr "type" "jmpreg,jmpreg")
10655 (set_attr "length" "4,8")])
10657 (define_insn "*call_value_nonlocal_sysv"
10658 [(set (match_operand 0 "" "")
10659 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10660 (match_operand 2 "" "g,g")))
10661 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10662 (clobber (match_scratch:SI 4 "=l,l"))]
10663 "(DEFAULT_ABI == ABI_DARWIN
10664 || (DEFAULT_ABI == ABI_V4
10665 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10666 {
10667 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10668 output_asm_insn ("crxor 6,6,6", operands);
10670 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10671 output_asm_insn ("creqv 6,6,6", operands);
10673 #if TARGET_MACHO
10674 return output_call(insn, operands, 1, 3);
10675 #else
10676 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10677 #endif
10678 }
10679 [(set_attr "type" "branch,branch")
10680 (set_attr "length" "4,8")])
10682 ;; Call subroutine returning any type.
10683 (define_expand "untyped_call"
10684 [(parallel [(call (match_operand 0 "" "")
10685 (const_int 0))
10686 (match_operand 1 "" "")
10687 (match_operand 2 "" "")])]
10688 ""
10689 "
10690 {
10691 int i;
10693 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10695 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10696 {
10697 rtx set = XVECEXP (operands[2], 0, i);
10698 emit_move_insn (SET_DEST (set), SET_SRC (set));
10699 }
10701 /* The optimizer does not know that the call sets the function value
10702 registers we stored in the result block. We avoid problems by
10703 claiming that all hard registers are used and clobbered at this
10704 point. */
10705 emit_insn (gen_blockage ());
10707 DONE;
10708 }")
10710 ;; sibling call patterns
10711 (define_expand "sibcall"
10712 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10713 (match_operand 1 "" ""))
10714 (use (match_operand 2 "" ""))
10715 (use (match_operand 3 "" ""))
10716 (return)])]
10717 ""
10718 "
10719 {
10720 #if TARGET_MACHO
10721 if (MACHOPIC_INDIRECT)
10722 operands[0] = machopic_indirect_call_target (operands[0]);
10723 #endif
10725 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10726 abort ();
10728 operands[0] = XEXP (operands[0], 0);
10729 operands[3] = gen_reg_rtx (SImode);
10731 }")
10733 ;; this and similar patterns must be marked as using LR, otherwise
10734 ;; dataflow will try to delete the store into it. This is true
10735 ;; even when the actual reg to jump to is in CTR, when LR was
10736 ;; saved and restored around the PIC-setting BCL.
10737 (define_insn "*sibcall_local32"
10738 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10739 (match_operand 1 "" "g,g"))
10740 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10741 (use (match_operand:SI 3 "register_operand" "l,l"))
10742 (return)]
10743 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10744 "*
10745 {
10746 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10747 output_asm_insn (\"crxor 6,6,6\", operands);
10749 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10750 output_asm_insn (\"creqv 6,6,6\", operands);
10752 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10753 }"
10754 [(set_attr "type" "branch")
10755 (set_attr "length" "4,8")])
10757 (define_insn "*sibcall_local64"
10758 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10759 (match_operand 1 "" "g,g"))
10760 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10761 (use (match_operand:SI 3 "register_operand" "l,l"))
10762 (return)]
10763 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10764 "*
10765 {
10766 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10767 output_asm_insn (\"crxor 6,6,6\", operands);
10769 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10770 output_asm_insn (\"creqv 6,6,6\", operands);
10772 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10773 }"
10774 [(set_attr "type" "branch")
10775 (set_attr "length" "4,8")])
10777 (define_insn "*sibcall_value_local32"
10778 [(set (match_operand 0 "" "")
10779 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10780 (match_operand 2 "" "g,g")))
10781 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10782 (use (match_operand:SI 4 "register_operand" "l,l"))
10783 (return)]
10784 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10785 "*
10786 {
10787 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10788 output_asm_insn (\"crxor 6,6,6\", operands);
10790 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10791 output_asm_insn (\"creqv 6,6,6\", operands);
10793 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10794 }"
10795 [(set_attr "type" "branch")
10796 (set_attr "length" "4,8")])
10799 (define_insn "*sibcall_value_local64"
10800 [(set (match_operand 0 "" "")
10801 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10802 (match_operand 2 "" "g,g")))
10803 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10804 (use (match_operand:SI 4 "register_operand" "l,l"))
10805 (return)]
10806 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10807 "*
10808 {
10809 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10810 output_asm_insn (\"crxor 6,6,6\", operands);
10812 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10813 output_asm_insn (\"creqv 6,6,6\", operands);
10815 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10816 }"
10817 [(set_attr "type" "branch")
10818 (set_attr "length" "4,8")])
10820 (define_insn "*sibcall_nonlocal_aix32"
10821 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10822 (match_operand 1 "" "g"))
10823 (use (match_operand:SI 2 "immediate_operand" "O"))
10824 (use (match_operand:SI 3 "register_operand" "l"))
10825 (return)]
10826 "TARGET_32BIT
10827 && DEFAULT_ABI == ABI_AIX
10828 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10829 "b %z0"
10830 [(set_attr "type" "branch")
10831 (set_attr "length" "4")])
10833 (define_insn "*sibcall_nonlocal_aix64"
10834 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10835 (match_operand 1 "" "g"))
10836 (use (match_operand:SI 2 "immediate_operand" "O"))
10837 (use (match_operand:SI 3 "register_operand" "l"))
10838 (return)]
10839 "TARGET_64BIT
10840 && DEFAULT_ABI == ABI_AIX
10841 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10842 "b %z0"
10843 [(set_attr "type" "branch")
10844 (set_attr "length" "4")])
10846 (define_insn "*sibcall_value_nonlocal_aix32"
10847 [(set (match_operand 0 "" "")
10848 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10849 (match_operand 2 "" "g")))
10850 (use (match_operand:SI 3 "immediate_operand" "O"))
10851 (use (match_operand:SI 4 "register_operand" "l"))
10852 (return)]
10853 "TARGET_32BIT
10854 && DEFAULT_ABI == ABI_AIX
10855 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10856 "b %z1"
10857 [(set_attr "type" "branch")
10858 (set_attr "length" "4")])
10860 (define_insn "*sibcall_value_nonlocal_aix64"
10861 [(set (match_operand 0 "" "")
10862 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10863 (match_operand 2 "" "g")))
10864 (use (match_operand:SI 3 "immediate_operand" "O"))
10865 (use (match_operand:SI 4 "register_operand" "l"))
10866 (return)]
10867 "TARGET_64BIT
10868 && DEFAULT_ABI == ABI_AIX
10869 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10870 "b %z1"
10871 [(set_attr "type" "branch")
10872 (set_attr "length" "4")])
10874 (define_insn "*sibcall_nonlocal_sysv"
10875 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10876 (match_operand 1 "" ""))
10877 (use (match_operand 2 "immediate_operand" "O,n"))
10878 (use (match_operand:SI 3 "register_operand" "l,l"))
10879 (return)]
10880 "(DEFAULT_ABI == ABI_DARWIN
10881 || DEFAULT_ABI == ABI_V4)
10882 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10883 "*
10884 {
10885 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10886 output_asm_insn (\"crxor 6,6,6\", operands);
10888 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10889 output_asm_insn (\"creqv 6,6,6\", operands);
10891 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10892 }"
10893 [(set_attr "type" "branch,branch")
10894 (set_attr "length" "4,8")])
10896 (define_expand "sibcall_value"
10897 [(parallel [(set (match_operand 0 "register_operand" "")
10898 (call (mem:SI (match_operand 1 "address_operand" ""))
10899 (match_operand 2 "" "")))
10900 (use (match_operand 3 "" ""))
10901 (use (match_operand 4 "" ""))
10902 (return)])]
10903 ""
10904 "
10905 {
10906 #if TARGET_MACHO
10907 if (MACHOPIC_INDIRECT)
10908 operands[1] = machopic_indirect_call_target (operands[1]);
10909 #endif
10911 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10912 abort ();
10914 operands[1] = XEXP (operands[1], 0);
10915 operands[4] = gen_reg_rtx (SImode);
10917 }")
10919 (define_insn "*sibcall_value_nonlocal_sysv"
10920 [(set (match_operand 0 "" "")
10921 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10922 (match_operand 2 "" "")))
10923 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10924 (use (match_operand:SI 4 "register_operand" "l,l"))
10925 (return)]
10926 "(DEFAULT_ABI == ABI_DARWIN
10927 || DEFAULT_ABI == ABI_V4)
10928 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10929 "*
10930 {
10931 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10932 output_asm_insn (\"crxor 6,6,6\", operands);
10934 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10935 output_asm_insn (\"creqv 6,6,6\", operands);
10937 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10938 }"
10939 [(set_attr "type" "branch,branch")
10940 (set_attr "length" "4,8")])
10942 (define_expand "sibcall_epilogue"
10943 [(use (const_int 0))]
10944 "TARGET_SCHED_PROLOG"
10945 "
10946 {
10947 rs6000_emit_epilogue (TRUE);
10948 DONE;
10949 }")
10951 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10952 ;; all of memory. This blocks insns from being moved across this point.
10954 (define_insn "blockage"
10955 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10956 ""
10957 "")
10958 \f
10959 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10960 ;; signed & unsigned, and one type of branch.
10961 ;;
10962 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10963 ;; insns, and branches. We store the operands of compares until we see
10964 ;; how it is used.
10965 (define_expand "cmpsi"
10966 [(set (cc0)
10967 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10968 (match_operand:SI 1 "reg_or_short_operand" "")))]
10969 ""
10970 "
10971 {
10972 /* Take care of the possibility that operands[1] might be negative but
10973 this might be a logical operation. That insn doesn't exist. */
10974 if (GET_CODE (operands[1]) == CONST_INT
10975 && INTVAL (operands[1]) < 0)
10976 operands[1] = force_reg (SImode, operands[1]);
10978 rs6000_compare_op0 = operands[0];
10979 rs6000_compare_op1 = operands[1];
10980 rs6000_compare_fp_p = 0;
10981 DONE;
10982 }")
10984 (define_expand "cmpdi"
10985 [(set (cc0)
10986 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10987 (match_operand:DI 1 "reg_or_short_operand" "")))]
10988 "TARGET_POWERPC64"
10989 "
10990 {
10991 /* Take care of the possibility that operands[1] might be negative but
10992 this might be a logical operation. That insn doesn't exist. */
10993 if (GET_CODE (operands[1]) == CONST_INT
10994 && INTVAL (operands[1]) < 0)
10995 operands[1] = force_reg (DImode, operands[1]);
10997 rs6000_compare_op0 = operands[0];
10998 rs6000_compare_op1 = operands[1];
10999 rs6000_compare_fp_p = 0;
11000 DONE;
11001 }")
11003 (define_expand "cmpsf"
11004 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
11005 (match_operand:SF 1 "gpc_reg_operand" "")))]
11006 "TARGET_HARD_FLOAT"
11007 "
11008 {
11009 rs6000_compare_op0 = operands[0];
11010 rs6000_compare_op1 = operands[1];
11011 rs6000_compare_fp_p = 1;
11012 DONE;
11013 }")
11015 (define_expand "cmpdf"
11016 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
11017 (match_operand:DF 1 "gpc_reg_operand" "")))]
11018 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
11019 "
11020 {
11021 rs6000_compare_op0 = operands[0];
11022 rs6000_compare_op1 = operands[1];
11023 rs6000_compare_fp_p = 1;
11024 DONE;
11025 }")
11027 (define_expand "cmptf"
11028 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
11029 (match_operand:TF 1 "gpc_reg_operand" "")))]
11030 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11031 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11032 "
11033 {
11034 rs6000_compare_op0 = operands[0];
11035 rs6000_compare_op1 = operands[1];
11036 rs6000_compare_fp_p = 1;
11037 DONE;
11038 }")
11040 (define_expand "beq"
11041 [(use (match_operand 0 "" ""))]
11042 ""
11043 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11045 (define_expand "bne"
11046 [(use (match_operand 0 "" ""))]
11047 ""
11048 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11050 (define_expand "bge"
11051 [(use (match_operand 0 "" ""))]
11052 ""
11053 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11055 (define_expand "bgt"
11056 [(use (match_operand 0 "" ""))]
11057 ""
11058 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11060 (define_expand "ble"
11061 [(use (match_operand 0 "" ""))]
11062 ""
11063 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11065 (define_expand "blt"
11066 [(use (match_operand 0 "" ""))]
11067 ""
11068 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11070 (define_expand "bgeu"
11071 [(use (match_operand 0 "" ""))]
11072 ""
11073 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11075 (define_expand "bgtu"
11076 [(use (match_operand 0 "" ""))]
11077 ""
11078 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11080 (define_expand "bleu"
11081 [(use (match_operand 0 "" ""))]
11082 ""
11083 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11085 (define_expand "bltu"
11086 [(use (match_operand 0 "" ""))]
11087 ""
11088 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11090 (define_expand "bunordered"
11091 [(use (match_operand 0 "" ""))]
11092 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11093 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11095 (define_expand "bordered"
11096 [(use (match_operand 0 "" ""))]
11097 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11098 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11100 (define_expand "buneq"
11101 [(use (match_operand 0 "" ""))]
11102 ""
11103 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11105 (define_expand "bunge"
11106 [(use (match_operand 0 "" ""))]
11107 ""
11108 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11110 (define_expand "bungt"
11111 [(use (match_operand 0 "" ""))]
11112 ""
11113 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11115 (define_expand "bunle"
11116 [(use (match_operand 0 "" ""))]
11117 ""
11118 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11120 (define_expand "bunlt"
11121 [(use (match_operand 0 "" ""))]
11122 ""
11123 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11125 (define_expand "bltgt"
11126 [(use (match_operand 0 "" ""))]
11127 ""
11128 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11130 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11131 ;; For SEQ, likewise, except that comparisons with zero should be done
11132 ;; with an scc insns. However, due to the order that combine see the
11133 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11134 ;; the cases we don't want to handle.
11135 (define_expand "seq"
11136 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11137 ""
11138 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11140 (define_expand "sne"
11141 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11142 ""
11143 "
11144 {
11145 if (! rs6000_compare_fp_p)
11146 FAIL;
11148 rs6000_emit_sCOND (NE, operands[0]);
11149 DONE;
11150 }")
11152 ;; A >= 0 is best done the portable way for A an integer.
11153 (define_expand "sge"
11154 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11155 ""
11156 "
11157 {
11158 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11159 FAIL;
11161 rs6000_emit_sCOND (GE, operands[0]);
11162 DONE;
11163 }")
11165 ;; A > 0 is best done using the portable sequence, so fail in that case.
11166 (define_expand "sgt"
11167 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11168 ""
11169 "
11170 {
11171 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11172 FAIL;
11174 rs6000_emit_sCOND (GT, operands[0]);
11175 DONE;
11176 }")
11178 ;; A <= 0 is best done the portable way for A an integer.
11179 (define_expand "sle"
11180 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11181 ""
11182 "
11183 {
11184 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11185 FAIL;
11187 rs6000_emit_sCOND (LE, operands[0]);
11188 DONE;
11189 }")
11191 ;; A < 0 is best done in the portable way for A an integer.
11192 (define_expand "slt"
11193 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11194 ""
11195 "
11196 {
11197 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11198 FAIL;
11200 rs6000_emit_sCOND (LT, operands[0]);
11201 DONE;
11202 }")
11204 (define_expand "sgeu"
11205 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11206 ""
11207 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11209 (define_expand "sgtu"
11210 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11211 ""
11212 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11214 (define_expand "sleu"
11215 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11216 ""
11217 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11219 (define_expand "sltu"
11220 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11221 ""
11222 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11224 (define_expand "sunordered"
11225 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11226 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11227 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11229 (define_expand "sordered"
11230 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11231 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11232 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11234 (define_expand "suneq"
11235 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11236 ""
11237 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11239 (define_expand "sunge"
11240 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11241 ""
11242 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11244 (define_expand "sungt"
11245 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11246 ""
11247 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11249 (define_expand "sunle"
11250 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11251 ""
11252 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11254 (define_expand "sunlt"
11255 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11256 ""
11257 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11259 (define_expand "sltgt"
11260 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11261 ""
11262 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11264 \f
11265 ;; Here are the actual compare insns.
11266 (define_insn "*cmpsi_internal1"
11267 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11268 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11269 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11270 ""
11271 "{cmp%I2|cmpw%I2} %0,%1,%2"
11272 [(set_attr "type" "cmp")])
11274 (define_insn "*cmpdi_internal1"
11275 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11276 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11277 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11278 "TARGET_POWERPC64"
11279 "cmpd%I2 %0,%1,%2"
11280 [(set_attr "type" "cmp")])
11282 ;; If we are comparing a register for equality with a large constant,
11283 ;; we can do this with an XOR followed by a compare. But we need a scratch
11284 ;; register for the result of the XOR.
11286 (define_split
11287 [(set (match_operand:CC 0 "cc_reg_operand" "")
11288 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11289 (match_operand:SI 2 "non_short_cint_operand" "")))
11290 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11291 "find_single_use (operands[0], insn, 0)
11292 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11293 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11294 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11295 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11296 "
11297 {
11298 /* Get the constant we are comparing against, C, and see what it looks like
11299 sign-extended to 16 bits. Then see what constant could be XOR'ed
11300 with C to get the sign-extended value. */
11302 HOST_WIDE_INT c = INTVAL (operands[2]);
11303 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11304 HOST_WIDE_INT xorv = c ^ sextc;
11306 operands[4] = GEN_INT (xorv);
11307 operands[5] = GEN_INT (sextc);
11308 }")
11310 (define_insn "*cmpsi_internal2"
11311 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11312 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11313 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11314 ""
11315 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11316 [(set_attr "type" "cmp")])
11318 (define_insn "*cmpdi_internal2"
11319 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11320 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11321 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11322 ""
11323 "cmpld%I2 %0,%1,%b2"
11324 [(set_attr "type" "cmp")])
11326 ;; The following two insns don't exist as single insns, but if we provide
11327 ;; them, we can swap an add and compare, which will enable us to overlap more
11328 ;; of the required delay between a compare and branch. We generate code for
11329 ;; them by splitting.
11331 (define_insn ""
11332 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11333 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11334 (match_operand:SI 2 "short_cint_operand" "i")))
11335 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11336 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11337 ""
11338 "#"
11339 [(set_attr "length" "8")])
11341 (define_insn ""
11342 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11343 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11344 (match_operand:SI 2 "u_short_cint_operand" "i")))
11345 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11346 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11347 ""
11348 "#"
11349 [(set_attr "length" "8")])
11351 (define_split
11352 [(set (match_operand:CC 3 "cc_reg_operand" "")
11353 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11354 (match_operand:SI 2 "short_cint_operand" "")))
11355 (set (match_operand:SI 0 "gpc_reg_operand" "")
11356 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11357 ""
11358 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11359 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11361 (define_split
11362 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11363 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11364 (match_operand:SI 2 "u_short_cint_operand" "")))
11365 (set (match_operand:SI 0 "gpc_reg_operand" "")
11366 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11367 ""
11368 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11369 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11371 (define_insn "*cmpsf_internal1"
11372 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11373 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11374 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11375 "TARGET_HARD_FLOAT && TARGET_FPRS"
11376 "fcmpu %0,%1,%2"
11377 [(set_attr "type" "fpcompare")])
11379 (define_insn "*cmpdf_internal1"
11380 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11381 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11382 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11383 "TARGET_HARD_FLOAT && TARGET_FPRS"
11384 "fcmpu %0,%1,%2"
11385 [(set_attr "type" "fpcompare")])
11387 ;; Only need to compare second words if first words equal
11388 (define_insn "*cmptf_internal1"
11389 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11390 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11391 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11392 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
11393 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11394 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11395 [(set_attr "type" "fpcompare")
11396 (set_attr "length" "12")])
11398 (define_insn_and_split "*cmptf_internal2"
11399 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11400 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11401 (match_operand:TF 2 "gpc_reg_operand" "f")))
11402 (clobber (match_scratch:DF 3 "=f"))
11403 (clobber (match_scratch:DF 4 "=f"))
11404 (clobber (match_scratch:DF 5 "=f"))
11405 (clobber (match_scratch:DF 6 "=f"))
11406 (clobber (match_scratch:DF 7 "=f"))
11407 (clobber (match_scratch:DF 8 "=f"))
11408 (clobber (match_scratch:DF 9 "=f"))
11409 (clobber (match_scratch:DF 10 "=f"))]
11410 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
11411 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11412 "#"
11413 "&& reload_completed"
11414 [(set (match_dup 3) (match_dup 13))
11415 (set (match_dup 4) (match_dup 14))
11416 (set (match_dup 9) (abs:DF (match_dup 5)))
11417 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11418 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11419 (label_ref (match_dup 11))
11420 (pc)))
11421 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11422 (set (pc) (label_ref (match_dup 12)))
11423 (match_dup 11)
11424 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11425 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11426 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11427 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11428 (match_dup 12)]
11429 {
11430 REAL_VALUE_TYPE rv;
11431 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11432 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11434 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11435 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11436 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11437 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11438 operands[11] = gen_label_rtx ();
11439 operands[12] = gen_label_rtx ();
11440 real_inf (&rv);
11441 operands[13] = force_const_mem (DFmode,
11442 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11443 operands[14] = force_const_mem (DFmode,
11444 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11445 DFmode));
11446 if (TARGET_TOC)
11447 {
11448 operands[13] = gen_const_mem (DFmode,
11449 create_TOC_reference (XEXP (operands[13], 0)));
11450 operands[14] = gen_const_mem (DFmode,
11451 create_TOC_reference (XEXP (operands[14], 0)));
11452 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11453 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11454 }
11455 })
11456 \f
11457 ;; Now we have the scc insns. We can do some combinations because of the
11458 ;; way the machine works.
11459 ;;
11460 ;; Note that this is probably faster if we can put an insn between the
11461 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11462 ;; cases the insns below which don't use an intermediate CR field will
11463 ;; be used instead.
11464 (define_insn ""
11465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11466 (match_operator:SI 1 "scc_comparison_operator"
11467 [(match_operand 2 "cc_reg_operand" "y")
11468 (const_int 0)]))]
11469 ""
11470 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11471 [(set (attr "type")
11472 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11473 (const_string "mfcrf")
11474 ]
11475 (const_string "mfcr")))
11476 (set_attr "length" "8")])
11478 ;; Same as above, but get the GT bit.
11479 (define_insn "move_from_CR_eq_bit"
11480 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11481 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))]
11482 "TARGET_E500"
11483 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
11484 [(set_attr "type" "mfcr")
11485 (set_attr "length" "8")])
11487 ;; Same as above, but get the OV/ORDERED bit.
11488 (define_insn "move_from_CR_ov_bit"
11489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11490 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11491 "TARGET_ISEL"
11492 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11493 [(set_attr "type" "mfcr")
11494 (set_attr "length" "8")])
11496 (define_insn ""
11497 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11498 (match_operator:DI 1 "scc_comparison_operator"
11499 [(match_operand 2 "cc_reg_operand" "y")
11500 (const_int 0)]))]
11501 "TARGET_POWERPC64"
11502 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11503 [(set (attr "type")
11504 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11505 (const_string "mfcrf")
11506 ]
11507 (const_string "mfcr")))
11508 (set_attr "length" "8")])
11510 (define_insn ""
11511 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11512 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11513 [(match_operand 2 "cc_reg_operand" "y,y")
11514 (const_int 0)])
11515 (const_int 0)))
11516 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11517 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11518 "TARGET_32BIT"
11519 "@
11520 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11521 #"
11522 [(set_attr "type" "delayed_compare")
11523 (set_attr "length" "8,16")])
11525 (define_split
11526 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11527 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11528 [(match_operand 2 "cc_reg_operand" "")
11529 (const_int 0)])
11530 (const_int 0)))
11531 (set (match_operand:SI 3 "gpc_reg_operand" "")
11532 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11533 "TARGET_32BIT && reload_completed"
11534 [(set (match_dup 3)
11535 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11536 (set (match_dup 0)
11537 (compare:CC (match_dup 3)
11538 (const_int 0)))]
11539 "")
11541 (define_insn ""
11542 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11543 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11544 [(match_operand 2 "cc_reg_operand" "y")
11545 (const_int 0)])
11546 (match_operand:SI 3 "const_int_operand" "n")))]
11547 ""
11548 "*
11549 {
11550 int is_bit = ccr_bit (operands[1], 1);
11551 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11552 int count;
11554 if (is_bit >= put_bit)
11555 count = is_bit - put_bit;
11556 else
11557 count = 32 - (put_bit - is_bit);
11559 operands[4] = GEN_INT (count);
11560 operands[5] = GEN_INT (put_bit);
11562 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11563 }"
11564 [(set (attr "type")
11565 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11566 (const_string "mfcrf")
11567 ]
11568 (const_string "mfcr")))
11569 (set_attr "length" "8")])
11571 (define_insn ""
11572 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11573 (compare:CC
11574 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11575 [(match_operand 2 "cc_reg_operand" "y,y")
11576 (const_int 0)])
11577 (match_operand:SI 3 "const_int_operand" "n,n"))
11578 (const_int 0)))
11579 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11580 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11581 (match_dup 3)))]
11582 ""
11583 "*
11584 {
11585 int is_bit = ccr_bit (operands[1], 1);
11586 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11587 int count;
11589 /* Force split for non-cc0 compare. */
11590 if (which_alternative == 1)
11591 return \"#\";
11593 if (is_bit >= put_bit)
11594 count = is_bit - put_bit;
11595 else
11596 count = 32 - (put_bit - is_bit);
11598 operands[5] = GEN_INT (count);
11599 operands[6] = GEN_INT (put_bit);
11601 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11602 }"
11603 [(set_attr "type" "delayed_compare")
11604 (set_attr "length" "8,16")])
11606 (define_split
11607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11608 (compare:CC
11609 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11610 [(match_operand 2 "cc_reg_operand" "")
11611 (const_int 0)])
11612 (match_operand:SI 3 "const_int_operand" ""))
11613 (const_int 0)))
11614 (set (match_operand:SI 4 "gpc_reg_operand" "")
11615 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11616 (match_dup 3)))]
11617 "reload_completed"
11618 [(set (match_dup 4)
11619 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11620 (match_dup 3)))
11621 (set (match_dup 0)
11622 (compare:CC (match_dup 4)
11623 (const_int 0)))]
11624 "")
11626 ;; There is a 3 cycle delay between consecutive mfcr instructions
11627 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11629 (define_peephole
11630 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11631 (match_operator:SI 1 "scc_comparison_operator"
11632 [(match_operand 2 "cc_reg_operand" "y")
11633 (const_int 0)]))
11634 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11635 (match_operator:SI 4 "scc_comparison_operator"
11636 [(match_operand 5 "cc_reg_operand" "y")
11637 (const_int 0)]))]
11638 "REGNO (operands[2]) != REGNO (operands[5])"
11639 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11640 [(set_attr "type" "mfcr")
11641 (set_attr "length" "12")])
11643 (define_peephole
11644 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11645 (match_operator:DI 1 "scc_comparison_operator"
11646 [(match_operand 2 "cc_reg_operand" "y")
11647 (const_int 0)]))
11648 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11649 (match_operator:DI 4 "scc_comparison_operator"
11650 [(match_operand 5 "cc_reg_operand" "y")
11651 (const_int 0)]))]
11652 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11653 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11654 [(set_attr "type" "mfcr")
11655 (set_attr "length" "12")])
11657 ;; There are some scc insns that can be done directly, without a compare.
11658 ;; These are faster because they don't involve the communications between
11659 ;; the FXU and branch units. In fact, we will be replacing all of the
11660 ;; integer scc insns here or in the portable methods in emit_store_flag.
11661 ;;
11662 ;; Also support (neg (scc ..)) since that construct is used to replace
11663 ;; branches, (plus (scc ..) ..) since that construct is common and
11664 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11665 ;; cases where it is no more expensive than (neg (scc ..)).
11667 ;; Have reload force a constant into a register for the simple insns that
11668 ;; otherwise won't accept constants. We do this because it is faster than
11669 ;; the cmp/mfcr sequence we would otherwise generate.
11671 (define_insn ""
11672 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11673 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11674 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11675 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11676 "TARGET_32BIT"
11677 "@
11678 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11679 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11680 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11681 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11682 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11683 [(set_attr "type" "three,two,three,three,three")
11684 (set_attr "length" "12,8,12,12,12")])
11686 (define_insn ""
11687 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11688 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11689 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11690 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11691 "TARGET_64BIT"
11692 "@
11693 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11694 subfic %3,%1,0\;adde %0,%3,%1
11695 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11696 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11697 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11698 [(set_attr "type" "three,two,three,three,three")
11699 (set_attr "length" "12,8,12,12,12")])
11701 (define_insn ""
11702 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11703 (compare:CC
11704 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11705 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11706 (const_int 0)))
11707 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11708 (eq:SI (match_dup 1) (match_dup 2)))
11709 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11710 "TARGET_32BIT"
11711 "@
11712 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11713 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11714 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11715 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11716 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11717 #
11718 #
11719 #
11720 #
11721 #"
11722 [(set_attr "type" "compare")
11723 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11725 (define_split
11726 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11727 (compare:CC
11728 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11729 (match_operand:SI 2 "reg_or_cint_operand" ""))
11730 (const_int 0)))
11731 (set (match_operand:SI 0 "gpc_reg_operand" "")
11732 (eq:SI (match_dup 1) (match_dup 2)))
11733 (clobber (match_scratch:SI 3 ""))]
11734 "TARGET_32BIT && reload_completed"
11735 [(parallel [(set (match_dup 0)
11736 (eq:SI (match_dup 1) (match_dup 2)))
11737 (clobber (match_dup 3))])
11738 (set (match_dup 4)
11739 (compare:CC (match_dup 0)
11740 (const_int 0)))]
11741 "")
11743 (define_insn ""
11744 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11745 (compare:CC
11746 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11747 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11748 (const_int 0)))
11749 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11750 (eq:DI (match_dup 1) (match_dup 2)))
11751 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11752 "TARGET_64BIT"
11753 "@
11754 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11755 subfic %3,%1,0\;adde. %0,%3,%1
11756 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11757 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11758 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11759 #
11760 #
11761 #
11762 #
11763 #"
11764 [(set_attr "type" "compare")
11765 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11767 (define_split
11768 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11769 (compare:CC
11770 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11771 (match_operand:DI 2 "reg_or_cint_operand" ""))
11772 (const_int 0)))
11773 (set (match_operand:DI 0 "gpc_reg_operand" "")
11774 (eq:DI (match_dup 1) (match_dup 2)))
11775 (clobber (match_scratch:DI 3 ""))]
11776 "TARGET_64BIT && reload_completed"
11777 [(parallel [(set (match_dup 0)
11778 (eq:DI (match_dup 1) (match_dup 2)))
11779 (clobber (match_dup 3))])
11780 (set (match_dup 4)
11781 (compare:CC (match_dup 0)
11782 (const_int 0)))]
11783 "")
11785 ;; We have insns of the form shown by the first define_insn below. If
11786 ;; there is something inside the comparison operation, we must split it.
11787 (define_split
11788 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11789 (plus:SI (match_operator 1 "comparison_operator"
11790 [(match_operand:SI 2 "" "")
11791 (match_operand:SI 3
11792 "reg_or_cint_operand" "")])
11793 (match_operand:SI 4 "gpc_reg_operand" "")))
11794 (clobber (match_operand:SI 5 "register_operand" ""))]
11795 "! gpc_reg_operand (operands[2], SImode)"
11796 [(set (match_dup 5) (match_dup 2))
11797 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11798 (match_dup 4)))])
11800 (define_insn ""
11801 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11802 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11803 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11804 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11805 "TARGET_32BIT"
11806 "@
11807 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11808 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11809 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11810 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11811 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11812 [(set_attr "type" "three,two,three,three,three")
11813 (set_attr "length" "12,8,12,12,12")])
11815 (define_insn ""
11816 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11817 (compare:CC
11818 (plus:SI
11819 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11820 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11821 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11822 (const_int 0)))
11823 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11824 "TARGET_32BIT"
11825 "@
11826 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11827 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11828 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11829 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11830 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11831 #
11832 #
11833 #
11834 #
11835 #"
11836 [(set_attr "type" "compare")
11837 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11839 (define_split
11840 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11841 (compare:CC
11842 (plus:SI
11843 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11844 (match_operand:SI 2 "reg_or_cint_operand" ""))
11845 (match_operand:SI 3 "gpc_reg_operand" ""))
11846 (const_int 0)))
11847 (clobber (match_scratch:SI 4 ""))]
11848 "TARGET_32BIT && reload_completed"
11849 [(set (match_dup 4)
11850 (plus:SI (eq:SI (match_dup 1)
11851 (match_dup 2))
11852 (match_dup 3)))
11853 (set (match_dup 0)
11854 (compare:CC (match_dup 4)
11855 (const_int 0)))]
11856 "")
11858 (define_insn ""
11859 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11860 (compare:CC
11861 (plus:SI
11862 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11863 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11864 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11865 (const_int 0)))
11866 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11867 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11868 "TARGET_32BIT"
11869 "@
11870 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11871 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11872 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11873 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11874 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11875 #
11876 #
11877 #
11878 #
11879 #"
11880 [(set_attr "type" "compare")
11881 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11883 (define_split
11884 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11885 (compare:CC
11886 (plus:SI
11887 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11888 (match_operand:SI 2 "reg_or_cint_operand" ""))
11889 (match_operand:SI 3 "gpc_reg_operand" ""))
11890 (const_int 0)))
11891 (set (match_operand:SI 0 "gpc_reg_operand" "")
11892 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11893 "TARGET_32BIT && reload_completed"
11894 [(set (match_dup 0)
11895 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11896 (set (match_dup 4)
11897 (compare:CC (match_dup 0)
11898 (const_int 0)))]
11899 "")
11901 (define_insn ""
11902 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11903 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11904 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11905 "TARGET_32BIT"
11906 "@
11907 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11908 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11909 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11910 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11911 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11912 [(set_attr "type" "three,two,three,three,three")
11913 (set_attr "length" "12,8,12,12,12")])
11915 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11916 ;; since it nabs/sr is just as fast.
11917 (define_insn "*ne0"
11918 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11919 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11920 (const_int 31)))
11921 (clobber (match_scratch:SI 2 "=&r"))]
11922 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11923 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11924 [(set_attr "type" "two")
11925 (set_attr "length" "8")])
11927 (define_insn ""
11928 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11929 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11930 (const_int 63)))
11931 (clobber (match_scratch:DI 2 "=&r"))]
11932 "TARGET_64BIT"
11933 "addic %2,%1,-1\;subfe %0,%2,%1"
11934 [(set_attr "type" "two")
11935 (set_attr "length" "8")])
11937 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11938 (define_insn ""
11939 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11940 (plus:SI (lshiftrt:SI
11941 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11942 (const_int 31))
11943 (match_operand:SI 2 "gpc_reg_operand" "r")))
11944 (clobber (match_scratch:SI 3 "=&r"))]
11945 "TARGET_32BIT"
11946 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11947 [(set_attr "type" "two")
11948 (set_attr "length" "8")])
11950 (define_insn ""
11951 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11952 (plus:DI (lshiftrt:DI
11953 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11954 (const_int 63))
11955 (match_operand:DI 2 "gpc_reg_operand" "r")))
11956 (clobber (match_scratch:DI 3 "=&r"))]
11957 "TARGET_64BIT"
11958 "addic %3,%1,-1\;addze %0,%2"
11959 [(set_attr "type" "two")
11960 (set_attr "length" "8")])
11962 (define_insn ""
11963 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11964 (compare:CC
11965 (plus:SI (lshiftrt:SI
11966 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11967 (const_int 31))
11968 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11969 (const_int 0)))
11970 (clobber (match_scratch:SI 3 "=&r,&r"))
11971 (clobber (match_scratch:SI 4 "=X,&r"))]
11972 "TARGET_32BIT"
11973 "@
11974 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11975 #"
11976 [(set_attr "type" "compare")
11977 (set_attr "length" "8,12")])
11979 (define_split
11980 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11981 (compare:CC
11982 (plus:SI (lshiftrt:SI
11983 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11984 (const_int 31))
11985 (match_operand:SI 2 "gpc_reg_operand" ""))
11986 (const_int 0)))
11987 (clobber (match_scratch:SI 3 ""))
11988 (clobber (match_scratch:SI 4 ""))]
11989 "TARGET_32BIT && reload_completed"
11990 [(parallel [(set (match_dup 3)
11991 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11992 (const_int 31))
11993 (match_dup 2)))
11994 (clobber (match_dup 4))])
11995 (set (match_dup 0)
11996 (compare:CC (match_dup 3)
11997 (const_int 0)))]
11998 "")
12000 (define_insn ""
12001 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12002 (compare:CC
12003 (plus:DI (lshiftrt:DI
12004 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12005 (const_int 63))
12006 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12007 (const_int 0)))
12008 (clobber (match_scratch:DI 3 "=&r,&r"))]
12009 "TARGET_64BIT"
12010 "@
12011 addic %3,%1,-1\;addze. %3,%2
12012 #"
12013 [(set_attr "type" "compare")
12014 (set_attr "length" "8,12")])
12016 (define_split
12017 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12018 (compare:CC
12019 (plus:DI (lshiftrt:DI
12020 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12021 (const_int 63))
12022 (match_operand:DI 2 "gpc_reg_operand" ""))
12023 (const_int 0)))
12024 (clobber (match_scratch:DI 3 ""))]
12025 "TARGET_64BIT && reload_completed"
12026 [(set (match_dup 3)
12027 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12028 (const_int 63))
12029 (match_dup 2)))
12030 (set (match_dup 0)
12031 (compare:CC (match_dup 3)
12032 (const_int 0)))]
12033 "")
12035 (define_insn ""
12036 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12037 (compare:CC
12038 (plus:SI (lshiftrt:SI
12039 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12040 (const_int 31))
12041 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12042 (const_int 0)))
12043 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12044 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12045 (match_dup 2)))
12046 (clobber (match_scratch:SI 3 "=&r,&r"))]
12047 "TARGET_32BIT"
12048 "@
12049 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12050 #"
12051 [(set_attr "type" "compare")
12052 (set_attr "length" "8,12")])
12054 (define_split
12055 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12056 (compare:CC
12057 (plus:SI (lshiftrt:SI
12058 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12059 (const_int 31))
12060 (match_operand:SI 2 "gpc_reg_operand" ""))
12061 (const_int 0)))
12062 (set (match_operand:SI 0 "gpc_reg_operand" "")
12063 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12064 (match_dup 2)))
12065 (clobber (match_scratch:SI 3 ""))]
12066 "TARGET_32BIT && reload_completed"
12067 [(parallel [(set (match_dup 0)
12068 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12069 (match_dup 2)))
12070 (clobber (match_dup 3))])
12071 (set (match_dup 4)
12072 (compare:CC (match_dup 0)
12073 (const_int 0)))]
12074 "")
12076 (define_insn ""
12077 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12078 (compare:CC
12079 (plus:DI (lshiftrt:DI
12080 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12081 (const_int 63))
12082 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12083 (const_int 0)))
12084 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12085 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12086 (match_dup 2)))
12087 (clobber (match_scratch:DI 3 "=&r,&r"))]
12088 "TARGET_64BIT"
12089 "@
12090 addic %3,%1,-1\;addze. %0,%2
12091 #"
12092 [(set_attr "type" "compare")
12093 (set_attr "length" "8,12")])
12095 (define_split
12096 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12097 (compare:CC
12098 (plus:DI (lshiftrt:DI
12099 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12100 (const_int 63))
12101 (match_operand:DI 2 "gpc_reg_operand" ""))
12102 (const_int 0)))
12103 (set (match_operand:DI 0 "gpc_reg_operand" "")
12104 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12105 (match_dup 2)))
12106 (clobber (match_scratch:DI 3 ""))]
12107 "TARGET_64BIT && reload_completed"
12108 [(parallel [(set (match_dup 0)
12109 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12110 (match_dup 2)))
12111 (clobber (match_dup 3))])
12112 (set (match_dup 4)
12113 (compare:CC (match_dup 0)
12114 (const_int 0)))]
12115 "")
12117 (define_insn ""
12118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12119 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12120 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12121 (clobber (match_scratch:SI 3 "=r,X"))]
12122 "TARGET_POWER"
12123 "@
12124 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12125 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12126 [(set_attr "length" "12")])
12128 (define_insn ""
12129 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12130 (compare:CC
12131 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12132 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12133 (const_int 0)))
12134 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12135 (le:SI (match_dup 1) (match_dup 2)))
12136 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12137 "TARGET_POWER"
12138 "@
12139 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12140 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12141 #
12142 #"
12143 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12144 (set_attr "length" "12,12,16,16")])
12146 (define_split
12147 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12148 (compare:CC
12149 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12150 (match_operand:SI 2 "reg_or_short_operand" ""))
12151 (const_int 0)))
12152 (set (match_operand:SI 0 "gpc_reg_operand" "")
12153 (le:SI (match_dup 1) (match_dup 2)))
12154 (clobber (match_scratch:SI 3 ""))]
12155 "TARGET_POWER && reload_completed"
12156 [(parallel [(set (match_dup 0)
12157 (le:SI (match_dup 1) (match_dup 2)))
12158 (clobber (match_dup 3))])
12159 (set (match_dup 4)
12160 (compare:CC (match_dup 0)
12161 (const_int 0)))]
12162 "")
12164 (define_insn ""
12165 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12166 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12167 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12168 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12169 "TARGET_POWER"
12170 "@
12171 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12172 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12173 [(set_attr "length" "12")])
12175 (define_insn ""
12176 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12177 (compare:CC
12178 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12179 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12180 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12181 (const_int 0)))
12182 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12183 "TARGET_POWER"
12184 "@
12185 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12186 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12187 #
12188 #"
12189 [(set_attr "type" "compare")
12190 (set_attr "length" "12,12,16,16")])
12192 (define_split
12193 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12194 (compare:CC
12195 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12196 (match_operand:SI 2 "reg_or_short_operand" ""))
12197 (match_operand:SI 3 "gpc_reg_operand" ""))
12198 (const_int 0)))
12199 (clobber (match_scratch:SI 4 ""))]
12200 "TARGET_POWER && reload_completed"
12201 [(set (match_dup 4)
12202 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12203 (match_dup 3)))
12204 (set (match_dup 0)
12205 (compare:CC (match_dup 4)
12206 (const_int 0)))]
12207 "")
12209 (define_insn ""
12210 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12211 (compare:CC
12212 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12213 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12214 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12215 (const_int 0)))
12216 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12217 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12218 "TARGET_POWER"
12219 "@
12220 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12221 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12222 #
12223 #"
12224 [(set_attr "type" "compare")
12225 (set_attr "length" "12,12,16,16")])
12227 (define_split
12228 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12229 (compare:CC
12230 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12231 (match_operand:SI 2 "reg_or_short_operand" ""))
12232 (match_operand:SI 3 "gpc_reg_operand" ""))
12233 (const_int 0)))
12234 (set (match_operand:SI 0 "gpc_reg_operand" "")
12235 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12236 "TARGET_POWER && reload_completed"
12237 [(set (match_dup 0)
12238 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12239 (set (match_dup 4)
12240 (compare:CC (match_dup 0)
12241 (const_int 0)))]
12242 "")
12244 (define_insn ""
12245 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12246 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12247 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12248 "TARGET_POWER"
12249 "@
12250 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12251 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12252 [(set_attr "length" "12")])
12254 (define_insn ""
12255 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12256 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12257 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12258 "TARGET_32BIT"
12259 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12260 [(set_attr "type" "three")
12261 (set_attr "length" "12")])
12263 (define_insn ""
12264 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12265 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12266 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12267 "TARGET_64BIT"
12268 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12269 [(set_attr "type" "three")
12270 (set_attr "length" "12")])
12272 (define_insn ""
12273 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12274 (compare:CC
12275 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12276 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12277 (const_int 0)))
12278 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12279 (leu:DI (match_dup 1) (match_dup 2)))]
12280 "TARGET_64BIT"
12281 "@
12282 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12283 #"
12284 [(set_attr "type" "compare")
12285 (set_attr "length" "12,16")])
12287 (define_split
12288 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12289 (compare:CC
12290 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12291 (match_operand:DI 2 "reg_or_short_operand" ""))
12292 (const_int 0)))
12293 (set (match_operand:DI 0 "gpc_reg_operand" "")
12294 (leu:DI (match_dup 1) (match_dup 2)))]
12295 "TARGET_64BIT && reload_completed"
12296 [(set (match_dup 0)
12297 (leu:DI (match_dup 1) (match_dup 2)))
12298 (set (match_dup 3)
12299 (compare:CC (match_dup 0)
12300 (const_int 0)))]
12301 "")
12303 (define_insn ""
12304 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12305 (compare:CC
12306 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12307 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12308 (const_int 0)))
12309 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12310 (leu:SI (match_dup 1) (match_dup 2)))]
12311 "TARGET_32BIT"
12312 "@
12313 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12314 #"
12315 [(set_attr "type" "compare")
12316 (set_attr "length" "12,16")])
12318 (define_split
12319 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12320 (compare:CC
12321 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12322 (match_operand:SI 2 "reg_or_short_operand" ""))
12323 (const_int 0)))
12324 (set (match_operand:SI 0 "gpc_reg_operand" "")
12325 (leu:SI (match_dup 1) (match_dup 2)))]
12326 "TARGET_32BIT && reload_completed"
12327 [(set (match_dup 0)
12328 (leu:SI (match_dup 1) (match_dup 2)))
12329 (set (match_dup 3)
12330 (compare:CC (match_dup 0)
12331 (const_int 0)))]
12332 "")
12334 (define_insn ""
12335 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12336 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12337 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12338 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12339 "TARGET_32BIT"
12340 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12341 [(set_attr "type" "two")
12342 (set_attr "length" "8")])
12344 (define_insn ""
12345 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12346 (compare:CC
12347 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12348 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12349 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12350 (const_int 0)))
12351 (clobber (match_scratch:SI 4 "=&r,&r"))]
12352 "TARGET_32BIT"
12353 "@
12354 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12355 #"
12356 [(set_attr "type" "compare")
12357 (set_attr "length" "8,12")])
12359 (define_split
12360 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12361 (compare:CC
12362 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12363 (match_operand:SI 2 "reg_or_short_operand" ""))
12364 (match_operand:SI 3 "gpc_reg_operand" ""))
12365 (const_int 0)))
12366 (clobber (match_scratch:SI 4 ""))]
12367 "TARGET_32BIT && reload_completed"
12368 [(set (match_dup 4)
12369 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12370 (match_dup 3)))
12371 (set (match_dup 0)
12372 (compare:CC (match_dup 4)
12373 (const_int 0)))]
12374 "")
12376 (define_insn ""
12377 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12378 (compare:CC
12379 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12380 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12381 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12382 (const_int 0)))
12383 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12384 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12385 "TARGET_32BIT"
12386 "@
12387 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12388 #"
12389 [(set_attr "type" "compare")
12390 (set_attr "length" "8,12")])
12392 (define_split
12393 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12394 (compare:CC
12395 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12396 (match_operand:SI 2 "reg_or_short_operand" ""))
12397 (match_operand:SI 3 "gpc_reg_operand" ""))
12398 (const_int 0)))
12399 (set (match_operand:SI 0 "gpc_reg_operand" "")
12400 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12401 "TARGET_32BIT && reload_completed"
12402 [(set (match_dup 0)
12403 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12404 (set (match_dup 4)
12405 (compare:CC (match_dup 0)
12406 (const_int 0)))]
12407 "")
12409 (define_insn ""
12410 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12411 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12412 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12413 "TARGET_32BIT"
12414 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12415 [(set_attr "type" "three")
12416 (set_attr "length" "12")])
12418 (define_insn ""
12419 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12420 (and:SI (neg:SI
12421 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12422 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12423 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12424 "TARGET_32BIT"
12425 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12426 [(set_attr "type" "three")
12427 (set_attr "length" "12")])
12429 (define_insn ""
12430 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12431 (compare:CC
12432 (and:SI (neg:SI
12433 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12434 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12435 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12436 (const_int 0)))
12437 (clobber (match_scratch:SI 4 "=&r,&r"))]
12438 "TARGET_32BIT"
12439 "@
12440 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12441 #"
12442 [(set_attr "type" "compare")
12443 (set_attr "length" "12,16")])
12445 (define_split
12446 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12447 (compare:CC
12448 (and:SI (neg:SI
12449 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12450 (match_operand:SI 2 "reg_or_short_operand" "")))
12451 (match_operand:SI 3 "gpc_reg_operand" ""))
12452 (const_int 0)))
12453 (clobber (match_scratch:SI 4 ""))]
12454 "TARGET_32BIT && reload_completed"
12455 [(set (match_dup 4)
12456 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12457 (match_dup 3)))
12458 (set (match_dup 0)
12459 (compare:CC (match_dup 4)
12460 (const_int 0)))]
12461 "")
12463 (define_insn ""
12464 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12465 (compare:CC
12466 (and:SI (neg:SI
12467 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12468 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12469 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12470 (const_int 0)))
12471 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12472 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12473 "TARGET_32BIT"
12474 "@
12475 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12476 #"
12477 [(set_attr "type" "compare")
12478 (set_attr "length" "12,16")])
12480 (define_split
12481 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12482 (compare:CC
12483 (and:SI (neg:SI
12484 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12485 (match_operand:SI 2 "reg_or_short_operand" "")))
12486 (match_operand:SI 3 "gpc_reg_operand" ""))
12487 (const_int 0)))
12488 (set (match_operand:SI 0 "gpc_reg_operand" "")
12489 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12490 "TARGET_32BIT && reload_completed"
12491 [(set (match_dup 0)
12492 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12493 (match_dup 3)))
12494 (set (match_dup 4)
12495 (compare:CC (match_dup 0)
12496 (const_int 0)))]
12497 "")
12499 (define_insn ""
12500 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12501 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12502 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12503 "TARGET_POWER"
12504 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12505 [(set_attr "length" "12")])
12507 (define_insn ""
12508 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12509 (compare:CC
12510 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12511 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12512 (const_int 0)))
12513 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12514 (lt:SI (match_dup 1) (match_dup 2)))]
12515 "TARGET_POWER"
12516 "@
12517 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12518 #"
12519 [(set_attr "type" "delayed_compare")
12520 (set_attr "length" "12,16")])
12522 (define_split
12523 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12524 (compare:CC
12525 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12526 (match_operand:SI 2 "reg_or_short_operand" ""))
12527 (const_int 0)))
12528 (set (match_operand:SI 0 "gpc_reg_operand" "")
12529 (lt:SI (match_dup 1) (match_dup 2)))]
12530 "TARGET_POWER && reload_completed"
12531 [(set (match_dup 0)
12532 (lt:SI (match_dup 1) (match_dup 2)))
12533 (set (match_dup 3)
12534 (compare:CC (match_dup 0)
12535 (const_int 0)))]
12536 "")
12538 (define_insn ""
12539 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12540 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12541 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12542 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12543 "TARGET_POWER"
12544 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12545 [(set_attr "length" "12")])
12547 (define_insn ""
12548 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12549 (compare:CC
12550 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12551 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12552 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12553 (const_int 0)))
12554 (clobber (match_scratch:SI 4 "=&r,&r"))]
12555 "TARGET_POWER"
12556 "@
12557 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12558 #"
12559 [(set_attr "type" "compare")
12560 (set_attr "length" "12,16")])
12562 (define_split
12563 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12564 (compare:CC
12565 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12566 (match_operand:SI 2 "reg_or_short_operand" ""))
12567 (match_operand:SI 3 "gpc_reg_operand" ""))
12568 (const_int 0)))
12569 (clobber (match_scratch:SI 4 ""))]
12570 "TARGET_POWER && reload_completed"
12571 [(set (match_dup 4)
12572 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12573 (match_dup 3)))
12574 (set (match_dup 0)
12575 (compare:CC (match_dup 4)
12576 (const_int 0)))]
12577 "")
12579 (define_insn ""
12580 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12581 (compare:CC
12582 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12583 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12584 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12585 (const_int 0)))
12586 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12587 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12588 "TARGET_POWER"
12589 "@
12590 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12591 #"
12592 [(set_attr "type" "compare")
12593 (set_attr "length" "12,16")])
12595 (define_split
12596 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12597 (compare:CC
12598 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12599 (match_operand:SI 2 "reg_or_short_operand" ""))
12600 (match_operand:SI 3 "gpc_reg_operand" ""))
12601 (const_int 0)))
12602 (set (match_operand:SI 0 "gpc_reg_operand" "")
12603 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12604 "TARGET_POWER && reload_completed"
12605 [(set (match_dup 0)
12606 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12607 (set (match_dup 4)
12608 (compare:CC (match_dup 0)
12609 (const_int 0)))]
12610 "")
12612 (define_insn ""
12613 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12614 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12615 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12616 "TARGET_POWER"
12617 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12618 [(set_attr "length" "12")])
12620 (define_insn_and_split ""
12621 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12622 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12623 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12624 "TARGET_32BIT"
12625 "#"
12626 "TARGET_32BIT"
12627 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12628 (set (match_dup 0) (neg:SI (match_dup 0)))]
12629 "")
12631 (define_insn_and_split ""
12632 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12633 (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12634 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12635 "TARGET_64BIT"
12636 "#"
12637 "TARGET_64BIT"
12638 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12639 (set (match_dup 0) (neg:DI (match_dup 0)))]
12640 "")
12642 (define_insn ""
12643 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12644 (compare:CC
12645 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12646 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12647 (const_int 0)))
12648 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12649 (ltu:SI (match_dup 1) (match_dup 2)))]
12650 "TARGET_32BIT"
12651 "@
12652 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12653 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12654 #
12655 #"
12656 [(set_attr "type" "compare")
12657 (set_attr "length" "12,12,16,16")])
12659 (define_split
12660 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12661 (compare:CC
12662 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12663 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12664 (const_int 0)))
12665 (set (match_operand:SI 0 "gpc_reg_operand" "")
12666 (ltu:SI (match_dup 1) (match_dup 2)))]
12667 "TARGET_32BIT && reload_completed"
12668 [(set (match_dup 0)
12669 (ltu:SI (match_dup 1) (match_dup 2)))
12670 (set (match_dup 3)
12671 (compare:CC (match_dup 0)
12672 (const_int 0)))]
12673 "")
12675 (define_insn_and_split ""
12676 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
12677 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12678 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12679 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12680 "TARGET_32BIT"
12681 "#"
12682 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12683 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12684 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
12685 "")
12687 (define_insn_and_split ""
12688 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
12689 (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12690 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
12691 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
12692 "TARGET_64BIT"
12693 "#"
12694 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12695 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12696 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
12697 "")
12699 (define_insn ""
12700 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12701 (compare:CC
12702 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12703 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12704 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12705 (const_int 0)))
12706 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12707 "TARGET_32BIT"
12708 "@
12709 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12710 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12711 #
12712 #"
12713 [(set_attr "type" "compare")
12714 (set_attr "length" "12,12,16,16")])
12716 (define_split
12717 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12718 (compare:CC
12719 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12720 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12721 (match_operand:SI 3 "gpc_reg_operand" ""))
12722 (const_int 0)))
12723 (clobber (match_scratch:SI 4 ""))]
12724 "TARGET_32BIT && reload_completed"
12725 [(set (match_dup 4)
12726 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12727 (match_dup 3)))
12728 (set (match_dup 0)
12729 (compare:CC (match_dup 4)
12730 (const_int 0)))]
12731 "")
12733 (define_insn ""
12734 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12735 (compare:CC
12736 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12737 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12738 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12739 (const_int 0)))
12740 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12741 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12742 "TARGET_32BIT"
12743 "@
12744 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12745 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12746 #
12747 #"
12748 [(set_attr "type" "compare")
12749 (set_attr "length" "12,12,16,16")])
12751 (define_split
12752 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12753 (compare:CC
12754 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12755 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12756 (match_operand:SI 3 "gpc_reg_operand" ""))
12757 (const_int 0)))
12758 (set (match_operand:SI 0 "gpc_reg_operand" "")
12759 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12760 "TARGET_32BIT && reload_completed"
12761 [(set (match_dup 0)
12762 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12763 (set (match_dup 4)
12764 (compare:CC (match_dup 0)
12765 (const_int 0)))]
12766 "")
12768 (define_insn ""
12769 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12770 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12771 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12772 "TARGET_32BIT"
12773 "@
12774 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12775 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12776 [(set_attr "type" "two")
12777 (set_attr "length" "8")])
12779 (define_insn ""
12780 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12781 (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12782 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
12783 "TARGET_64BIT"
12784 "@
12785 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12786 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12787 [(set_attr "type" "two")
12788 (set_attr "length" "8")])
12790 (define_insn ""
12791 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12792 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12793 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12794 (clobber (match_scratch:SI 3 "=r"))]
12795 "TARGET_POWER"
12796 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12797 [(set_attr "length" "12")])
12799 (define_insn ""
12800 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12801 (compare:CC
12802 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12803 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12804 (const_int 0)))
12805 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12806 (ge:SI (match_dup 1) (match_dup 2)))
12807 (clobber (match_scratch:SI 3 "=r,r"))]
12808 "TARGET_POWER"
12809 "@
12810 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12811 #"
12812 [(set_attr "type" "compare")
12813 (set_attr "length" "12,16")])
12815 (define_split
12816 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12817 (compare:CC
12818 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12819 (match_operand:SI 2 "reg_or_short_operand" ""))
12820 (const_int 0)))
12821 (set (match_operand:SI 0 "gpc_reg_operand" "")
12822 (ge:SI (match_dup 1) (match_dup 2)))
12823 (clobber (match_scratch:SI 3 ""))]
12824 "TARGET_POWER && reload_completed"
12825 [(parallel [(set (match_dup 0)
12826 (ge:SI (match_dup 1) (match_dup 2)))
12827 (clobber (match_dup 3))])
12828 (set (match_dup 4)
12829 (compare:CC (match_dup 0)
12830 (const_int 0)))]
12831 "")
12833 (define_insn ""
12834 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12835 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12836 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12837 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12838 "TARGET_POWER"
12839 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12840 [(set_attr "length" "12")])
12842 (define_insn ""
12843 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12844 (compare:CC
12845 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12846 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12847 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12848 (const_int 0)))
12849 (clobber (match_scratch:SI 4 "=&r,&r"))]
12850 "TARGET_POWER"
12851 "@
12852 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12853 #"
12854 [(set_attr "type" "compare")
12855 (set_attr "length" "12,16")])
12857 (define_split
12858 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12859 (compare:CC
12860 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12861 (match_operand:SI 2 "reg_or_short_operand" ""))
12862 (match_operand:SI 3 "gpc_reg_operand" ""))
12863 (const_int 0)))
12864 (clobber (match_scratch:SI 4 ""))]
12865 "TARGET_POWER && reload_completed"
12866 [(set (match_dup 4)
12867 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12868 (match_dup 3)))
12869 (set (match_dup 0)
12870 (compare:CC (match_dup 4)
12871 (const_int 0)))]
12872 "")
12874 (define_insn ""
12875 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12876 (compare:CC
12877 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12878 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12879 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12880 (const_int 0)))
12881 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12882 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12883 "TARGET_POWER"
12884 "@
12885 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12886 #"
12887 [(set_attr "type" "compare")
12888 (set_attr "length" "12,16")])
12890 (define_split
12891 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12892 (compare:CC
12893 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12894 (match_operand:SI 2 "reg_or_short_operand" ""))
12895 (match_operand:SI 3 "gpc_reg_operand" ""))
12896 (const_int 0)))
12897 (set (match_operand:SI 0 "gpc_reg_operand" "")
12898 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12899 "TARGET_POWER && reload_completed"
12900 [(set (match_dup 0)
12901 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12902 (set (match_dup 4)
12903 (compare:CC (match_dup 0)
12904 (const_int 0)))]
12905 "")
12907 (define_insn ""
12908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12909 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12910 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12911 "TARGET_POWER"
12912 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12913 [(set_attr "length" "12")])
12915 (define_insn ""
12916 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12917 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12918 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12919 "TARGET_32BIT"
12920 "@
12921 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12922 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12923 [(set_attr "type" "three")
12924 (set_attr "length" "12")])
12926 (define_insn ""
12927 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12928 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12929 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12930 "TARGET_64BIT"
12931 "@
12932 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12933 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12934 [(set_attr "type" "three")
12935 (set_attr "length" "12")])
12937 (define_insn ""
12938 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12939 (compare:CC
12940 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12941 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12942 (const_int 0)))
12943 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12944 (geu:SI (match_dup 1) (match_dup 2)))]
12945 "TARGET_32BIT"
12946 "@
12947 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12948 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12949 #
12950 #"
12951 [(set_attr "type" "compare")
12952 (set_attr "length" "12,12,16,16")])
12954 (define_split
12955 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12956 (compare:CC
12957 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12958 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12959 (const_int 0)))
12960 (set (match_operand:SI 0 "gpc_reg_operand" "")
12961 (geu:SI (match_dup 1) (match_dup 2)))]
12962 "TARGET_32BIT && reload_completed"
12963 [(set (match_dup 0)
12964 (geu:SI (match_dup 1) (match_dup 2)))
12965 (set (match_dup 3)
12966 (compare:CC (match_dup 0)
12967 (const_int 0)))]
12968 "")
12970 (define_insn ""
12971 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12972 (compare:CC
12973 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12974 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12975 (const_int 0)))
12976 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12977 (geu:DI (match_dup 1) (match_dup 2)))]
12978 "TARGET_64BIT"
12979 "@
12980 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12981 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12982 #
12983 #"
12984 [(set_attr "type" "compare")
12985 (set_attr "length" "12,12,16,16")])
12987 (define_split
12988 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12989 (compare:CC
12990 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12991 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12992 (const_int 0)))
12993 (set (match_operand:DI 0 "gpc_reg_operand" "")
12994 (geu:DI (match_dup 1) (match_dup 2)))]
12995 "TARGET_64BIT && reload_completed"
12996 [(set (match_dup 0)
12997 (geu:DI (match_dup 1) (match_dup 2)))
12998 (set (match_dup 3)
12999 (compare:CC (match_dup 0)
13000 (const_int 0)))]
13001 "")
13003 (define_insn ""
13004 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13005 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13006 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
13007 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13008 "TARGET_32BIT"
13009 "@
13010 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13011 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13012 [(set_attr "type" "two")
13013 (set_attr "length" "8")])
13015 (define_insn ""
13016 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13017 (compare:CC
13018 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13019 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13020 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13021 (const_int 0)))
13022 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13023 "TARGET_32BIT"
13024 "@
13025 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13026 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13027 #
13028 #"
13029 [(set_attr "type" "compare")
13030 (set_attr "length" "8,8,12,12")])
13032 (define_split
13033 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13034 (compare:CC
13035 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13036 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13037 (match_operand:SI 3 "gpc_reg_operand" ""))
13038 (const_int 0)))
13039 (clobber (match_scratch:SI 4 ""))]
13040 "TARGET_32BIT && reload_completed"
13041 [(set (match_dup 4)
13042 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13043 (match_dup 3)))
13044 (set (match_dup 0)
13045 (compare:CC (match_dup 4)
13046 (const_int 0)))]
13047 "")
13049 (define_insn ""
13050 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13051 (compare:CC
13052 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13053 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13054 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13055 (const_int 0)))
13056 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13057 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13058 "TARGET_32BIT"
13059 "@
13060 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13061 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13062 #
13063 #"
13064 [(set_attr "type" "compare")
13065 (set_attr "length" "8,8,12,12")])
13067 (define_split
13068 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13069 (compare:CC
13070 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13071 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13072 (match_operand:SI 3 "gpc_reg_operand" ""))
13073 (const_int 0)))
13074 (set (match_operand:SI 0 "gpc_reg_operand" "")
13075 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13076 "TARGET_32BIT && reload_completed"
13077 [(set (match_dup 0)
13078 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13079 (set (match_dup 4)
13080 (compare:CC (match_dup 0)
13081 (const_int 0)))]
13082 "")
13084 (define_insn ""
13085 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13086 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13087 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
13088 "TARGET_32BIT"
13089 "@
13090 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13091 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13092 [(set_attr "type" "three")
13093 (set_attr "length" "12")])
13095 (define_insn ""
13096 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13097 (and:SI (neg:SI
13098 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13099 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
13100 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13101 "TARGET_32BIT"
13102 "@
13103 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13104 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13105 [(set_attr "type" "three")
13106 (set_attr "length" "12")])
13108 (define_insn ""
13109 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13110 (compare:CC
13111 (and:SI (neg:SI
13112 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13113 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13114 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13115 (const_int 0)))
13116 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13117 "TARGET_32BIT"
13118 "@
13119 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13120 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13121 #
13122 #"
13123 [(set_attr "type" "compare")
13124 (set_attr "length" "12,12,16,16")])
13126 (define_split
13127 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13128 (compare:CC
13129 (and:SI (neg:SI
13130 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13131 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13132 (match_operand:SI 3 "gpc_reg_operand" ""))
13133 (const_int 0)))
13134 (clobber (match_scratch:SI 4 ""))]
13135 "TARGET_32BIT && reload_completed"
13136 [(set (match_dup 4)
13137 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13138 (match_dup 3)))
13139 (set (match_dup 0)
13140 (compare:CC (match_dup 4)
13141 (const_int 0)))]
13142 "")
13144 (define_insn ""
13145 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13146 (compare:CC
13147 (and:SI (neg:SI
13148 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13149 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13150 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13151 (const_int 0)))
13152 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13153 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13154 "TARGET_32BIT"
13155 "@
13156 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13157 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13158 #
13159 #"
13160 [(set_attr "type" "compare")
13161 (set_attr "length" "12,12,16,16")])
13163 (define_split
13164 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13165 (compare:CC
13166 (and:SI (neg:SI
13167 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13168 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13169 (match_operand:SI 3 "gpc_reg_operand" ""))
13170 (const_int 0)))
13171 (set (match_operand:SI 0 "gpc_reg_operand" "")
13172 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13173 "TARGET_32BIT && reload_completed"
13174 [(set (match_dup 0)
13175 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13176 (set (match_dup 4)
13177 (compare:CC (match_dup 0)
13178 (const_int 0)))]
13179 "")
13181 (define_insn ""
13182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13183 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13184 (const_int 0)))]
13185 "TARGET_32BIT"
13186 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
13187 [(set_attr "type" "three")
13188 (set_attr "length" "12")])
13190 (define_insn ""
13191 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13192 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13193 (const_int 0)))]
13194 "TARGET_64BIT"
13195 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
13196 [(set_attr "type" "three")
13197 (set_attr "length" "12")])
13199 (define_insn ""
13200 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13201 (compare:CC
13202 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13203 (const_int 0))
13204 (const_int 0)))
13205 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13206 (gt:SI (match_dup 1) (const_int 0)))]
13207 "TARGET_32BIT"
13208 "@
13209 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
13210 #"
13211 [(set_attr "type" "delayed_compare")
13212 (set_attr "length" "12,16")])
13214 (define_split
13215 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13216 (compare:CC
13217 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13218 (const_int 0))
13219 (const_int 0)))
13220 (set (match_operand:SI 0 "gpc_reg_operand" "")
13221 (gt:SI (match_dup 1) (const_int 0)))]
13222 "TARGET_32BIT && reload_completed"
13223 [(set (match_dup 0)
13224 (gt:SI (match_dup 1) (const_int 0)))
13225 (set (match_dup 2)
13226 (compare:CC (match_dup 0)
13227 (const_int 0)))]
13228 "")
13230 (define_insn ""
13231 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13232 (compare:CC
13233 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13234 (const_int 0))
13235 (const_int 0)))
13236 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13237 (gt:DI (match_dup 1) (const_int 0)))]
13238 "TARGET_64BIT"
13239 "@
13240 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13241 #"
13242 [(set_attr "type" "delayed_compare")
13243 (set_attr "length" "12,16")])
13245 (define_split
13246 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13247 (compare:CC
13248 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13249 (const_int 0))
13250 (const_int 0)))
13251 (set (match_operand:DI 0 "gpc_reg_operand" "")
13252 (gt:DI (match_dup 1) (const_int 0)))]
13253 "TARGET_64BIT && reload_completed"
13254 [(set (match_dup 0)
13255 (gt:DI (match_dup 1) (const_int 0)))
13256 (set (match_dup 2)
13257 (compare:CC (match_dup 0)
13258 (const_int 0)))]
13259 "")
13261 (define_insn ""
13262 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13263 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13264 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13265 "TARGET_POWER"
13266 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13267 [(set_attr "length" "12")])
13269 (define_insn ""
13270 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13271 (compare:CC
13272 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13273 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13274 (const_int 0)))
13275 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13276 (gt:SI (match_dup 1) (match_dup 2)))]
13277 "TARGET_POWER"
13278 "@
13279 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13280 #"
13281 [(set_attr "type" "delayed_compare")
13282 (set_attr "length" "12,16")])
13284 (define_split
13285 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13286 (compare:CC
13287 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13288 (match_operand:SI 2 "reg_or_short_operand" ""))
13289 (const_int 0)))
13290 (set (match_operand:SI 0 "gpc_reg_operand" "")
13291 (gt:SI (match_dup 1) (match_dup 2)))]
13292 "TARGET_POWER && reload_completed"
13293 [(set (match_dup 0)
13294 (gt:SI (match_dup 1) (match_dup 2)))
13295 (set (match_dup 3)
13296 (compare:CC (match_dup 0)
13297 (const_int 0)))]
13298 "")
13300 (define_insn ""
13301 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13302 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13303 (const_int 0))
13304 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13305 "TARGET_32BIT"
13306 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13307 [(set_attr "type" "three")
13308 (set_attr "length" "12")])
13310 (define_insn ""
13311 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13312 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13313 (const_int 0))
13314 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13315 "TARGET_64BIT"
13316 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13317 [(set_attr "type" "three")
13318 (set_attr "length" "12")])
13320 (define_insn ""
13321 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13322 (compare:CC
13323 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13324 (const_int 0))
13325 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13326 (const_int 0)))
13327 (clobber (match_scratch:SI 3 "=&r,&r"))]
13328 "TARGET_32BIT"
13329 "@
13330 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13331 #"
13332 [(set_attr "type" "compare")
13333 (set_attr "length" "12,16")])
13335 (define_split
13336 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13337 (compare:CC
13338 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13339 (const_int 0))
13340 (match_operand:SI 2 "gpc_reg_operand" ""))
13341 (const_int 0)))
13342 (clobber (match_scratch:SI 3 ""))]
13343 "TARGET_32BIT && reload_completed"
13344 [(set (match_dup 3)
13345 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13346 (match_dup 2)))
13347 (set (match_dup 0)
13348 (compare:CC (match_dup 3)
13349 (const_int 0)))]
13350 "")
13352 (define_insn ""
13353 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13354 (compare:CC
13355 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13356 (const_int 0))
13357 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13358 (const_int 0)))
13359 (clobber (match_scratch:DI 3 "=&r,&r"))]
13360 "TARGET_64BIT"
13361 "@
13362 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13363 #"
13364 [(set_attr "type" "compare")
13365 (set_attr "length" "12,16")])
13367 (define_split
13368 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13369 (compare:CC
13370 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13371 (const_int 0))
13372 (match_operand:DI 2 "gpc_reg_operand" ""))
13373 (const_int 0)))
13374 (clobber (match_scratch:DI 3 ""))]
13375 "TARGET_64BIT && reload_completed"
13376 [(set (match_dup 3)
13377 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13378 (match_dup 2)))
13379 (set (match_dup 0)
13380 (compare:CC (match_dup 3)
13381 (const_int 0)))]
13382 "")
13384 (define_insn ""
13385 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13386 (compare:CC
13387 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13388 (const_int 0))
13389 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13390 (const_int 0)))
13391 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13392 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13393 "TARGET_32BIT"
13394 "@
13395 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13396 #"
13397 [(set_attr "type" "compare")
13398 (set_attr "length" "12,16")])
13400 (define_split
13401 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13402 (compare:CC
13403 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13404 (const_int 0))
13405 (match_operand:SI 2 "gpc_reg_operand" ""))
13406 (const_int 0)))
13407 (set (match_operand:SI 0 "gpc_reg_operand" "")
13408 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13409 "TARGET_32BIT && reload_completed"
13410 [(set (match_dup 0)
13411 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13412 (set (match_dup 3)
13413 (compare:CC (match_dup 0)
13414 (const_int 0)))]
13415 "")
13417 (define_insn ""
13418 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13419 (compare:CC
13420 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13421 (const_int 0))
13422 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13423 (const_int 0)))
13424 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13425 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13426 "TARGET_64BIT"
13427 "@
13428 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13429 #"
13430 [(set_attr "type" "compare")
13431 (set_attr "length" "12,16")])
13433 (define_split
13434 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13435 (compare:CC
13436 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13437 (const_int 0))
13438 (match_operand:DI 2 "gpc_reg_operand" ""))
13439 (const_int 0)))
13440 (set (match_operand:DI 0 "gpc_reg_operand" "")
13441 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13442 "TARGET_64BIT && reload_completed"
13443 [(set (match_dup 0)
13444 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13445 (set (match_dup 3)
13446 (compare:CC (match_dup 0)
13447 (const_int 0)))]
13448 "")
13450 (define_insn ""
13451 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13452 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13453 (match_operand:SI 2 "reg_or_short_operand" "r"))
13454 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13455 "TARGET_POWER"
13456 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13457 [(set_attr "length" "12")])
13459 (define_insn ""
13460 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13461 (compare:CC
13462 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13463 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13464 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13465 (const_int 0)))
13466 (clobber (match_scratch:SI 4 "=&r,&r"))]
13467 "TARGET_POWER"
13468 "@
13469 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13470 #"
13471 [(set_attr "type" "compare")
13472 (set_attr "length" "12,16")])
13474 (define_split
13475 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13476 (compare:CC
13477 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13478 (match_operand:SI 2 "reg_or_short_operand" ""))
13479 (match_operand:SI 3 "gpc_reg_operand" ""))
13480 (const_int 0)))
13481 (clobber (match_scratch:SI 4 ""))]
13482 "TARGET_POWER && reload_completed"
13483 [(set (match_dup 4)
13484 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13485 (set (match_dup 0)
13486 (compare:CC (match_dup 4)
13487 (const_int 0)))]
13488 "")
13490 (define_insn ""
13491 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13492 (compare:CC
13493 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13494 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13495 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13496 (const_int 0)))
13497 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13498 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13499 "TARGET_POWER"
13500 "@
13501 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13502 #"
13503 [(set_attr "type" "compare")
13504 (set_attr "length" "12,16")])
13506 (define_split
13507 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13508 (compare:CC
13509 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13510 (match_operand:SI 2 "reg_or_short_operand" ""))
13511 (match_operand:SI 3 "gpc_reg_operand" ""))
13512 (const_int 0)))
13513 (set (match_operand:SI 0 "gpc_reg_operand" "")
13514 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13515 "TARGET_POWER && reload_completed"
13516 [(set (match_dup 0)
13517 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13518 (set (match_dup 4)
13519 (compare:CC (match_dup 0)
13520 (const_int 0)))]
13521 "")
13523 (define_insn ""
13524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13525 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13526 (const_int 0))))]
13527 "TARGET_32BIT"
13528 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13529 [(set_attr "type" "three")
13530 (set_attr "length" "12")])
13532 (define_insn ""
13533 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13534 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13535 (const_int 0))))]
13536 "TARGET_64BIT"
13537 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13538 [(set_attr "type" "three")
13539 (set_attr "length" "12")])
13541 (define_insn ""
13542 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13543 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13544 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13545 "TARGET_POWER"
13546 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13547 [(set_attr "length" "12")])
13549 (define_insn_and_split ""
13550 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13551 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13552 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13553 "TARGET_32BIT"
13554 "#"
13555 "TARGET_32BIT"
13556 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13557 (set (match_dup 0) (neg:SI (match_dup 0)))]
13558 "")
13560 (define_insn_and_split ""
13561 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13562 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13563 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13564 "TARGET_64BIT"
13565 "#"
13566 "TARGET_64BIT"
13567 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13568 (set (match_dup 0) (neg:DI (match_dup 0)))]
13569 "")
13571 (define_insn ""
13572 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13573 (compare:CC
13574 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13575 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13576 (const_int 0)))
13577 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13578 (gtu:SI (match_dup 1) (match_dup 2)))]
13579 "TARGET_32BIT"
13580 "@
13581 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13582 #"
13583 [(set_attr "type" "compare")
13584 (set_attr "length" "12,16")])
13586 (define_split
13587 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13588 (compare:CC
13589 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13590 (match_operand:SI 2 "reg_or_short_operand" ""))
13591 (const_int 0)))
13592 (set (match_operand:SI 0 "gpc_reg_operand" "")
13593 (gtu:SI (match_dup 1) (match_dup 2)))]
13594 "TARGET_32BIT && reload_completed"
13595 [(set (match_dup 0)
13596 (gtu:SI (match_dup 1) (match_dup 2)))
13597 (set (match_dup 3)
13598 (compare:CC (match_dup 0)
13599 (const_int 0)))]
13600 "")
13602 (define_insn ""
13603 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13604 (compare:CC
13605 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13606 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13607 (const_int 0)))
13608 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13609 (gtu:DI (match_dup 1) (match_dup 2)))]
13610 "TARGET_64BIT"
13611 "@
13612 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13613 #"
13614 [(set_attr "type" "compare")
13615 (set_attr "length" "12,16")])
13617 (define_split
13618 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13619 (compare:CC
13620 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13621 (match_operand:DI 2 "reg_or_short_operand" ""))
13622 (const_int 0)))
13623 (set (match_operand:DI 0 "gpc_reg_operand" "")
13624 (gtu:DI (match_dup 1) (match_dup 2)))]
13625 "TARGET_64BIT && reload_completed"
13626 [(set (match_dup 0)
13627 (gtu:DI (match_dup 1) (match_dup 2)))
13628 (set (match_dup 3)
13629 (compare:CC (match_dup 0)
13630 (const_int 0)))]
13631 "")
13633 (define_insn_and_split ""
13634 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13635 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13636 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13637 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
13638 "TARGET_32BIT"
13639 "#"
13640 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13641 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13642 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
13643 "")
13645 (define_insn_and_split ""
13646 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13647 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13648 (match_operand:DI 2 "reg_or_short_operand" "rI"))
13649 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
13650 "TARGET_64BIT"
13651 "#"
13652 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13653 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13654 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
13655 "")
13657 (define_insn ""
13658 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13659 (compare:CC
13660 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13661 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13662 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13663 (const_int 0)))
13664 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13665 "TARGET_32BIT"
13666 "@
13667 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13668 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
13669 #
13670 #"
13671 [(set_attr "type" "compare")
13672 (set_attr "length" "8,12,12,16")])
13674 (define_split
13675 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13676 (compare:CC
13677 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13678 (match_operand:SI 2 "reg_or_short_operand" ""))
13679 (match_operand:SI 3 "gpc_reg_operand" ""))
13680 (const_int 0)))
13681 (clobber (match_scratch:SI 4 ""))]
13682 "TARGET_32BIT && reload_completed"
13683 [(set (match_dup 4)
13684 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13685 (match_dup 3)))
13686 (set (match_dup 0)
13687 (compare:CC (match_dup 4)
13688 (const_int 0)))]
13689 "")
13691 (define_insn ""
13692 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13693 (compare:CC
13694 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13695 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13696 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13697 (const_int 0)))
13698 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13699 "TARGET_64BIT"
13700 "@
13701 addic %4,%1,%k2\;addze. %4,%3
13702 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
13703 #
13704 #"
13705 [(set_attr "type" "compare")
13706 (set_attr "length" "8,12,12,16")])
13708 (define_split
13709 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13710 (compare:CC
13711 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13712 (match_operand:DI 2 "reg_or_short_operand" ""))
13713 (match_operand:DI 3 "gpc_reg_operand" ""))
13714 (const_int 0)))
13715 (clobber (match_scratch:DI 4 ""))]
13716 "TARGET_64BIT && reload_completed"
13717 [(set (match_dup 4)
13718 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13719 (match_dup 3)))
13720 (set (match_dup 0)
13721 (compare:CC (match_dup 4)
13722 (const_int 0)))]
13723 "")
13725 (define_insn ""
13726 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13727 (compare:CC
13728 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13729 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13730 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13731 (const_int 0)))
13732 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13733 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13734 "TARGET_32BIT"
13735 "@
13736 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13737 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
13738 #
13739 #"
13740 [(set_attr "type" "compare")
13741 (set_attr "length" "8,12,12,16")])
13743 (define_split
13744 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13745 (compare:CC
13746 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13747 (match_operand:SI 2 "reg_or_short_operand" ""))
13748 (match_operand:SI 3 "gpc_reg_operand" ""))
13749 (const_int 0)))
13750 (set (match_operand:SI 0 "gpc_reg_operand" "")
13751 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13752 "TARGET_32BIT && reload_completed"
13753 [(set (match_dup 0)
13754 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13755 (set (match_dup 4)
13756 (compare:CC (match_dup 0)
13757 (const_int 0)))]
13758 "")
13760 (define_insn ""
13761 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13762 (compare:CC
13763 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13764 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13765 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13766 (const_int 0)))
13767 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13768 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13769 "TARGET_64BIT"
13770 "@
13771 addic %0,%1,%k2\;addze. %0,%3
13772 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
13773 #
13774 #"
13775 [(set_attr "type" "compare")
13776 (set_attr "length" "8,12,12,16")])
13778 (define_split
13779 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13780 (compare:CC
13781 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13782 (match_operand:DI 2 "reg_or_short_operand" ""))
13783 (match_operand:DI 3 "gpc_reg_operand" ""))
13784 (const_int 0)))
13785 (set (match_operand:DI 0 "gpc_reg_operand" "")
13786 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13787 "TARGET_64BIT && reload_completed"
13788 [(set (match_dup 0)
13789 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13790 (set (match_dup 4)
13791 (compare:CC (match_dup 0)
13792 (const_int 0)))]
13793 "")
13795 (define_insn ""
13796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13797 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13798 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13799 "TARGET_32BIT"
13800 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13801 [(set_attr "type" "two")
13802 (set_attr "length" "8")])
13804 (define_insn ""
13805 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13806 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13807 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13808 "TARGET_64BIT"
13809 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13810 [(set_attr "type" "two")
13811 (set_attr "length" "8")])
13812 \f
13813 ;; Define both directions of branch and return. If we need a reload
13814 ;; register, we'd rather use CR0 since it is much easier to copy a
13815 ;; register CC value to there.
13817 (define_insn ""
13818 [(set (pc)
13819 (if_then_else (match_operator 1 "branch_comparison_operator"
13820 [(match_operand 2
13821 "cc_reg_operand" "y")
13822 (const_int 0)])
13823 (label_ref (match_operand 0 "" ""))
13824 (pc)))]
13825 ""
13826 "*
13827 {
13828 return output_cbranch (operands[1], \"%l0\", 0, insn);
13829 }"
13830 [(set_attr "type" "branch")])
13832 (define_insn ""
13833 [(set (pc)
13834 (if_then_else (match_operator 0 "branch_comparison_operator"
13835 [(match_operand 1
13836 "cc_reg_operand" "y")
13837 (const_int 0)])
13838 (return)
13839 (pc)))]
13840 "direct_return ()"
13841 "*
13842 {
13843 return output_cbranch (operands[0], NULL, 0, insn);
13844 }"
13845 [(set_attr "type" "branch")
13846 (set_attr "length" "4")])
13848 (define_insn ""
13849 [(set (pc)
13850 (if_then_else (match_operator 1 "branch_comparison_operator"
13851 [(match_operand 2
13852 "cc_reg_operand" "y")
13853 (const_int 0)])
13854 (pc)
13855 (label_ref (match_operand 0 "" ""))))]
13856 ""
13857 "*
13858 {
13859 return output_cbranch (operands[1], \"%l0\", 1, insn);
13860 }"
13861 [(set_attr "type" "branch")])
13863 (define_insn ""
13864 [(set (pc)
13865 (if_then_else (match_operator 0 "branch_comparison_operator"
13866 [(match_operand 1
13867 "cc_reg_operand" "y")
13868 (const_int 0)])
13869 (pc)
13870 (return)))]
13871 "direct_return ()"
13872 "*
13873 {
13874 return output_cbranch (operands[0], NULL, 1, insn);
13875 }"
13876 [(set_attr "type" "branch")
13877 (set_attr "length" "4")])
13879 ;; Logic on condition register values.
13881 ; This pattern matches things like
13882 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13883 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13884 ; (const_int 1)))
13885 ; which are generated by the branch logic.
13886 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13888 (define_insn "*cceq_ior_compare"
13889 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13890 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13891 [(match_operator:SI 2
13892 "branch_positive_comparison_operator"
13893 [(match_operand 3
13894 "cc_reg_operand" "y,y")
13895 (const_int 0)])
13896 (match_operator:SI 4
13897 "branch_positive_comparison_operator"
13898 [(match_operand 5
13899 "cc_reg_operand" "0,y")
13900 (const_int 0)])])
13901 (const_int 1)))]
13902 ""
13903 "cr%q1 %E0,%j2,%j4"
13904 [(set_attr "type" "cr_logical,delayed_cr")])
13906 ; Why is the constant -1 here, but 1 in the previous pattern?
13907 ; Because ~1 has all but the low bit set.
13908 (define_insn ""
13909 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13910 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13911 [(not:SI (match_operator:SI 2
13912 "branch_positive_comparison_operator"
13913 [(match_operand 3
13914 "cc_reg_operand" "y,y")
13915 (const_int 0)]))
13916 (match_operator:SI 4
13917 "branch_positive_comparison_operator"
13918 [(match_operand 5
13919 "cc_reg_operand" "0,y")
13920 (const_int 0)])])
13921 (const_int -1)))]
13922 ""
13923 "cr%q1 %E0,%j2,%j4"
13924 [(set_attr "type" "cr_logical,delayed_cr")])
13926 (define_insn "*cceq_rev_compare"
13927 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13928 (compare:CCEQ (match_operator:SI 1
13929 "branch_positive_comparison_operator"
13930 [(match_operand 2
13931 "cc_reg_operand" "0,y")
13932 (const_int 0)])
13933 (const_int 0)))]
13934 ""
13935 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13936 [(set_attr "type" "cr_logical,delayed_cr")])
13938 ;; If we are comparing the result of two comparisons, this can be done
13939 ;; using creqv or crxor.
13941 (define_insn_and_split ""
13942 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13943 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13944 [(match_operand 2 "cc_reg_operand" "y")
13945 (const_int 0)])
13946 (match_operator 3 "branch_comparison_operator"
13947 [(match_operand 4 "cc_reg_operand" "y")
13948 (const_int 0)])))]
13949 ""
13950 "#"
13951 ""
13952 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13953 (match_dup 5)))]
13954 "
13955 {
13956 int positive_1, positive_2;
13958 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13959 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13961 if (! positive_1)
13962 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13963 GET_CODE (operands[1])),
13964 SImode,
13965 operands[2], const0_rtx);
13966 else if (GET_MODE (operands[1]) != SImode)
13967 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13968 operands[2], const0_rtx);
13970 if (! positive_2)
13971 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13972 GET_CODE (operands[3])),
13973 SImode,
13974 operands[4], const0_rtx);
13975 else if (GET_MODE (operands[3]) != SImode)
13976 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13977 operands[4], const0_rtx);
13979 if (positive_1 == positive_2)
13980 {
13981 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13982 operands[5] = constm1_rtx;
13983 }
13984 else
13985 {
13986 operands[5] = const1_rtx;
13987 }
13988 }")
13990 ;; Unconditional branch and return.
13992 (define_insn "jump"
13993 [(set (pc)
13994 (label_ref (match_operand 0 "" "")))]
13995 ""
13996 "b %l0"
13997 [(set_attr "type" "branch")])
13999 (define_insn "return"
14000 [(return)]
14001 "direct_return ()"
14002 "{br|blr}"
14003 [(set_attr "type" "jmpreg")])
14005 (define_expand "indirect_jump"
14006 [(set (pc) (match_operand 0 "register_operand" ""))]
14007 ""
14008 "
14009 {
14010 if (TARGET_32BIT)
14011 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
14012 else
14013 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
14014 DONE;
14015 }")
14017 (define_insn "indirect_jumpsi"
14018 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
14019 "TARGET_32BIT"
14020 "@
14021 bctr
14022 {br|blr}"
14023 [(set_attr "type" "jmpreg")])
14025 (define_insn "indirect_jumpdi"
14026 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
14027 "TARGET_64BIT"
14028 "@
14029 bctr
14030 blr"
14031 [(set_attr "type" "jmpreg")])
14033 ;; Table jump for switch statements:
14034 (define_expand "tablejump"
14035 [(use (match_operand 0 "" ""))
14036 (use (label_ref (match_operand 1 "" "")))]
14037 ""
14038 "
14039 {
14040 if (TARGET_32BIT)
14041 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14042 else
14043 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14044 DONE;
14045 }")
14047 (define_expand "tablejumpsi"
14048 [(set (match_dup 3)
14049 (plus:SI (match_operand:SI 0 "" "")
14050 (match_dup 2)))
14051 (parallel [(set (pc) (match_dup 3))
14052 (use (label_ref (match_operand 1 "" "")))])]
14053 "TARGET_32BIT"
14054 "
14055 { operands[0] = force_reg (SImode, operands[0]);
14056 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14057 operands[3] = gen_reg_rtx (SImode);
14058 }")
14060 (define_expand "tablejumpdi"
14061 [(set (match_dup 4)
14062 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
14063 (set (match_dup 3)
14064 (plus:DI (match_dup 4)
14065 (match_dup 2)))
14066 (parallel [(set (pc) (match_dup 3))
14067 (use (label_ref (match_operand 1 "" "")))])]
14068 "TARGET_64BIT"
14069 "
14070 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14071 operands[3] = gen_reg_rtx (DImode);
14072 operands[4] = gen_reg_rtx (DImode);
14073 }")
14075 (define_insn ""
14076 [(set (pc)
14077 (match_operand:SI 0 "register_operand" "c,*l"))
14078 (use (label_ref (match_operand 1 "" "")))]
14079 "TARGET_32BIT"
14080 "@
14081 bctr
14082 {br|blr}"
14083 [(set_attr "type" "jmpreg")])
14085 (define_insn ""
14086 [(set (pc)
14087 (match_operand:DI 0 "register_operand" "c,*l"))
14088 (use (label_ref (match_operand 1 "" "")))]
14089 "TARGET_64BIT"
14090 "@
14091 bctr
14092 blr"
14093 [(set_attr "type" "jmpreg")])
14095 (define_insn "nop"
14096 [(const_int 0)]
14097 ""
14098 "{cror 0,0,0|nop}")
14099 \f
14100 ;; Define the subtract-one-and-jump insns, starting with the template
14101 ;; so loop.c knows what to generate.
14103 (define_expand "doloop_end"
14104 [(use (match_operand 0 "" "")) ; loop pseudo
14105 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14106 (use (match_operand 2 "" "")) ; max iterations
14107 (use (match_operand 3 "" "")) ; loop level
14108 (use (match_operand 4 "" ""))] ; label
14109 ""
14110 "
14111 {
14112 /* Only use this on innermost loops. */
14113 if (INTVAL (operands[3]) > 1)
14114 FAIL;
14115 if (TARGET_64BIT)
14116 {
14117 if (GET_MODE (operands[0]) != DImode)
14118 FAIL;
14119 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14120 }
14121 else
14122 {
14123 if (GET_MODE (operands[0]) != SImode)
14124 FAIL;
14125 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14126 }
14127 DONE;
14128 }")
14130 (define_expand "ctrsi"
14131 [(parallel [(set (pc)
14132 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
14133 (const_int 1))
14134 (label_ref (match_operand 1 "" ""))
14135 (pc)))
14136 (set (match_dup 0)
14137 (plus:SI (match_dup 0)
14138 (const_int -1)))
14139 (clobber (match_scratch:CC 2 ""))
14140 (clobber (match_scratch:SI 3 ""))])]
14141 "TARGET_32BIT"
14142 "")
14144 (define_expand "ctrdi"
14145 [(parallel [(set (pc)
14146 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
14147 (const_int 1))
14148 (label_ref (match_operand 1 "" ""))
14149 (pc)))
14150 (set (match_dup 0)
14151 (plus:DI (match_dup 0)
14152 (const_int -1)))
14153 (clobber (match_scratch:CC 2 ""))
14154 (clobber (match_scratch:DI 3 ""))])]
14155 "TARGET_64BIT"
14156 "")
14158 ;; We need to be able to do this for any operand, including MEM, or we
14159 ;; will cause reload to blow up since we don't allow output reloads on
14160 ;; JUMP_INSNs.
14161 ;; For the length attribute to be calculated correctly, the
14162 ;; label MUST be operand 0.
14164 (define_insn "*ctrsi_internal1"
14165 [(set (pc)
14166 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14167 (const_int 1))
14168 (label_ref (match_operand 0 "" ""))
14169 (pc)))
14170 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14171 (plus:SI (match_dup 1)
14172 (const_int -1)))
14173 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14174 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14175 "TARGET_32BIT"
14176 "*
14177 {
14178 if (which_alternative != 0)
14179 return \"#\";
14180 else if (get_attr_length (insn) == 4)
14181 return \"{bdn|bdnz} %l0\";
14182 else
14183 return \"bdz $+8\;b %l0\";
14184 }"
14185 [(set_attr "type" "branch")
14186 (set_attr "length" "*,12,16,16")])
14188 (define_insn "*ctrsi_internal2"
14189 [(set (pc)
14190 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14191 (const_int 1))
14192 (pc)
14193 (label_ref (match_operand 0 "" ""))))
14194 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14195 (plus:SI (match_dup 1)
14196 (const_int -1)))
14197 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14198 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14199 "TARGET_32BIT"
14200 "*
14201 {
14202 if (which_alternative != 0)
14203 return \"#\";
14204 else if (get_attr_length (insn) == 4)
14205 return \"bdz %l0\";
14206 else
14207 return \"{bdn|bdnz} $+8\;b %l0\";
14208 }"
14209 [(set_attr "type" "branch")
14210 (set_attr "length" "*,12,16,16")])
14212 (define_insn "*ctrdi_internal1"
14213 [(set (pc)
14214 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14215 (const_int 1))
14216 (label_ref (match_operand 0 "" ""))
14217 (pc)))
14218 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14219 (plus:DI (match_dup 1)
14220 (const_int -1)))
14221 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14222 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14223 "TARGET_64BIT"
14224 "*
14225 {
14226 if (which_alternative != 0)
14227 return \"#\";
14228 else if (get_attr_length (insn) == 4)
14229 return \"{bdn|bdnz} %l0\";
14230 else
14231 return \"bdz $+8\;b %l0\";
14232 }"
14233 [(set_attr "type" "branch")
14234 (set_attr "length" "*,12,16,16")])
14236 (define_insn "*ctrdi_internal2"
14237 [(set (pc)
14238 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14239 (const_int 1))
14240 (pc)
14241 (label_ref (match_operand 0 "" ""))))
14242 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14243 (plus:DI (match_dup 1)
14244 (const_int -1)))
14245 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14246 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14247 "TARGET_64BIT"
14248 "*
14249 {
14250 if (which_alternative != 0)
14251 return \"#\";
14252 else if (get_attr_length (insn) == 4)
14253 return \"bdz %l0\";
14254 else
14255 return \"{bdn|bdnz} $+8\;b %l0\";
14256 }"
14257 [(set_attr "type" "branch")
14258 (set_attr "length" "*,12,16,16")])
14260 ;; Similar but use EQ
14262 (define_insn "*ctrsi_internal5"
14263 [(set (pc)
14264 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14265 (const_int 1))
14266 (label_ref (match_operand 0 "" ""))
14267 (pc)))
14268 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14269 (plus:SI (match_dup 1)
14270 (const_int -1)))
14271 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14272 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14273 "TARGET_32BIT"
14274 "*
14275 {
14276 if (which_alternative != 0)
14277 return \"#\";
14278 else if (get_attr_length (insn) == 4)
14279 return \"bdz %l0\";
14280 else
14281 return \"{bdn|bdnz} $+8\;b %l0\";
14282 }"
14283 [(set_attr "type" "branch")
14284 (set_attr "length" "*,12,16,16")])
14286 (define_insn "*ctrsi_internal6"
14287 [(set (pc)
14288 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14289 (const_int 1))
14290 (pc)
14291 (label_ref (match_operand 0 "" ""))))
14292 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14293 (plus:SI (match_dup 1)
14294 (const_int -1)))
14295 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14296 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14297 "TARGET_32BIT"
14298 "*
14299 {
14300 if (which_alternative != 0)
14301 return \"#\";
14302 else if (get_attr_length (insn) == 4)
14303 return \"{bdn|bdnz} %l0\";
14304 else
14305 return \"bdz $+8\;b %l0\";
14306 }"
14307 [(set_attr "type" "branch")
14308 (set_attr "length" "*,12,16,16")])
14310 (define_insn "*ctrdi_internal5"
14311 [(set (pc)
14312 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14313 (const_int 1))
14314 (label_ref (match_operand 0 "" ""))
14315 (pc)))
14316 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14317 (plus:DI (match_dup 1)
14318 (const_int -1)))
14319 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14320 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14321 "TARGET_64BIT"
14322 "*
14323 {
14324 if (which_alternative != 0)
14325 return \"#\";
14326 else if (get_attr_length (insn) == 4)
14327 return \"bdz %l0\";
14328 else
14329 return \"{bdn|bdnz} $+8\;b %l0\";
14330 }"
14331 [(set_attr "type" "branch")
14332 (set_attr "length" "*,12,16,16")])
14334 (define_insn "*ctrdi_internal6"
14335 [(set (pc)
14336 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14337 (const_int 1))
14338 (pc)
14339 (label_ref (match_operand 0 "" ""))))
14340 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14341 (plus:DI (match_dup 1)
14342 (const_int -1)))
14343 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14344 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14345 "TARGET_64BIT"
14346 "*
14347 {
14348 if (which_alternative != 0)
14349 return \"#\";
14350 else if (get_attr_length (insn) == 4)
14351 return \"{bdn|bdnz} %l0\";
14352 else
14353 return \"bdz $+8\;b %l0\";
14354 }"
14355 [(set_attr "type" "branch")
14356 (set_attr "length" "*,12,16,16")])
14358 ;; Now the splitters if we could not allocate the CTR register
14360 (define_split
14361 [(set (pc)
14362 (if_then_else (match_operator 2 "comparison_operator"
14363 [(match_operand:SI 1 "gpc_reg_operand" "")
14364 (const_int 1)])
14365 (match_operand 5 "" "")
14366 (match_operand 6 "" "")))
14367 (set (match_operand:SI 0 "gpc_reg_operand" "")
14368 (plus:SI (match_dup 1)
14369 (const_int -1)))
14370 (clobber (match_scratch:CC 3 ""))
14371 (clobber (match_scratch:SI 4 ""))]
14372 "TARGET_32BIT && reload_completed"
14373 [(parallel [(set (match_dup 3)
14374 (compare:CC (plus:SI (match_dup 1)
14375 (const_int -1))
14376 (const_int 0)))
14377 (set (match_dup 0)
14378 (plus:SI (match_dup 1)
14379 (const_int -1)))])
14380 (set (pc) (if_then_else (match_dup 7)
14381 (match_dup 5)
14382 (match_dup 6)))]
14383 "
14384 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14385 operands[3], const0_rtx); }")
14387 (define_split
14388 [(set (pc)
14389 (if_then_else (match_operator 2 "comparison_operator"
14390 [(match_operand:SI 1 "gpc_reg_operand" "")
14391 (const_int 1)])
14392 (match_operand 5 "" "")
14393 (match_operand 6 "" "")))
14394 (set (match_operand:SI 0 "nonimmediate_operand" "")
14395 (plus:SI (match_dup 1) (const_int -1)))
14396 (clobber (match_scratch:CC 3 ""))
14397 (clobber (match_scratch:SI 4 ""))]
14398 "TARGET_32BIT && reload_completed
14399 && ! gpc_reg_operand (operands[0], SImode)"
14400 [(parallel [(set (match_dup 3)
14401 (compare:CC (plus:SI (match_dup 1)
14402 (const_int -1))
14403 (const_int 0)))
14404 (set (match_dup 4)
14405 (plus:SI (match_dup 1)
14406 (const_int -1)))])
14407 (set (match_dup 0)
14408 (match_dup 4))
14409 (set (pc) (if_then_else (match_dup 7)
14410 (match_dup 5)
14411 (match_dup 6)))]
14412 "
14413 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14414 operands[3], const0_rtx); }")
14415 (define_split
14416 [(set (pc)
14417 (if_then_else (match_operator 2 "comparison_operator"
14418 [(match_operand:DI 1 "gpc_reg_operand" "")
14419 (const_int 1)])
14420 (match_operand 5 "" "")
14421 (match_operand 6 "" "")))
14422 (set (match_operand:DI 0 "gpc_reg_operand" "")
14423 (plus:DI (match_dup 1)
14424 (const_int -1)))
14425 (clobber (match_scratch:CC 3 ""))
14426 (clobber (match_scratch:DI 4 ""))]
14427 "TARGET_64BIT && reload_completed"
14428 [(parallel [(set (match_dup 3)
14429 (compare:CC (plus:DI (match_dup 1)
14430 (const_int -1))
14431 (const_int 0)))
14432 (set (match_dup 0)
14433 (plus:DI (match_dup 1)
14434 (const_int -1)))])
14435 (set (pc) (if_then_else (match_dup 7)
14436 (match_dup 5)
14437 (match_dup 6)))]
14438 "
14439 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14440 operands[3], const0_rtx); }")
14442 (define_split
14443 [(set (pc)
14444 (if_then_else (match_operator 2 "comparison_operator"
14445 [(match_operand:DI 1 "gpc_reg_operand" "")
14446 (const_int 1)])
14447 (match_operand 5 "" "")
14448 (match_operand 6 "" "")))
14449 (set (match_operand:DI 0 "nonimmediate_operand" "")
14450 (plus:DI (match_dup 1) (const_int -1)))
14451 (clobber (match_scratch:CC 3 ""))
14452 (clobber (match_scratch:DI 4 ""))]
14453 "TARGET_64BIT && reload_completed
14454 && ! gpc_reg_operand (operands[0], DImode)"
14455 [(parallel [(set (match_dup 3)
14456 (compare:CC (plus:DI (match_dup 1)
14457 (const_int -1))
14458 (const_int 0)))
14459 (set (match_dup 4)
14460 (plus:DI (match_dup 1)
14461 (const_int -1)))])
14462 (set (match_dup 0)
14463 (match_dup 4))
14464 (set (pc) (if_then_else (match_dup 7)
14465 (match_dup 5)
14466 (match_dup 6)))]
14467 "
14468 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14469 operands[3], const0_rtx); }")
14470 \f
14471 (define_insn "trap"
14472 [(trap_if (const_int 1) (const_int 0))]
14473 ""
14474 "{t 31,0,0|trap}")
14476 (define_expand "conditional_trap"
14477 [(trap_if (match_operator 0 "trap_comparison_operator"
14478 [(match_dup 2) (match_dup 3)])
14479 (match_operand 1 "const_int_operand" ""))]
14480 ""
14481 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14482 operands[2] = rs6000_compare_op0;
14483 operands[3] = rs6000_compare_op1;")
14485 (define_insn ""
14486 [(trap_if (match_operator 0 "trap_comparison_operator"
14487 [(match_operand:SI 1 "register_operand" "r")
14488 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14489 (const_int 0))]
14490 ""
14491 "{t|tw}%V0%I2 %1,%2")
14493 (define_insn ""
14494 [(trap_if (match_operator 0 "trap_comparison_operator"
14495 [(match_operand:DI 1 "register_operand" "r")
14496 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14497 (const_int 0))]
14498 "TARGET_POWERPC64"
14499 "td%V0%I2 %1,%2")
14500 \f
14501 ;; Insns related to generating the function prologue and epilogue.
14503 (define_expand "prologue"
14504 [(use (const_int 0))]
14505 "TARGET_SCHED_PROLOG"
14506 "
14507 {
14508 rs6000_emit_prologue ();
14509 DONE;
14510 }")
14512 (define_insn "*movesi_from_cr_one"
14513 [(match_parallel 0 "mfcr_operation"
14514 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14515 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14516 (match_operand 3 "immediate_operand" "n")]
14517 UNSPEC_MOVESI_FROM_CR))])]
14518 "TARGET_MFCRF"
14519 "*
14520 {
14521 int mask = 0;
14522 int i;
14523 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14524 {
14525 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14526 operands[4] = GEN_INT (mask);
14527 output_asm_insn (\"mfcr %1,%4\", operands);
14528 }
14529 return \"\";
14530 }"
14531 [(set_attr "type" "mfcrf")])
14533 (define_insn "movesi_from_cr"
14534 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14535 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14536 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14537 UNSPEC_MOVESI_FROM_CR))]
14538 ""
14539 "mfcr %0"
14540 [(set_attr "type" "mfcr")])
14542 (define_insn "*stmw"
14543 [(match_parallel 0 "stmw_operation"
14544 [(set (match_operand:SI 1 "memory_operand" "=m")
14545 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14546 "TARGET_MULTIPLE"
14547 "{stm|stmw} %2,%1")
14549 (define_insn "*save_fpregs_si"
14550 [(match_parallel 0 "any_parallel_operand"
14551 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14552 (use (match_operand:SI 2 "call_operand" "s"))
14553 (set (match_operand:DF 3 "memory_operand" "=m")
14554 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14555 "TARGET_32BIT"
14556 "bl %z2"
14557 [(set_attr "type" "branch")
14558 (set_attr "length" "4")])
14560 (define_insn "*save_fpregs_di"
14561 [(match_parallel 0 "any_parallel_operand"
14562 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14563 (use (match_operand:DI 2 "call_operand" "s"))
14564 (set (match_operand:DF 3 "memory_operand" "=m")
14565 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14566 "TARGET_64BIT"
14567 "bl %z2"
14568 [(set_attr "type" "branch")
14569 (set_attr "length" "4")])
14571 ; These are to explain that changes to the stack pointer should
14572 ; not be moved over stores to stack memory.
14573 (define_insn "stack_tie"
14574 [(set (match_operand:BLK 0 "memory_operand" "+m")
14575 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14576 ""
14577 ""
14578 [(set_attr "length" "0")])
14581 (define_expand "epilogue"
14582 [(use (const_int 0))]
14583 "TARGET_SCHED_PROLOG"
14584 "
14585 {
14586 rs6000_emit_epilogue (FALSE);
14587 DONE;
14588 }")
14590 ; On some processors, doing the mtcrf one CC register at a time is
14591 ; faster (like on the 604e). On others, doing them all at once is
14592 ; faster; for instance, on the 601 and 750.
14594 (define_expand "movsi_to_cr_one"
14595 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14596 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14597 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14598 ""
14599 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14601 (define_insn "*movsi_to_cr"
14602 [(match_parallel 0 "mtcrf_operation"
14603 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14604 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14605 (match_operand 3 "immediate_operand" "n")]
14606 UNSPEC_MOVESI_TO_CR))])]
14607 ""
14608 "*
14609 {
14610 int mask = 0;
14611 int i;
14612 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14613 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14614 operands[4] = GEN_INT (mask);
14615 return \"mtcrf %4,%2\";
14616 }"
14617 [(set_attr "type" "mtcr")])
14619 (define_insn "*mtcrfsi"
14620 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14621 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14622 (match_operand 2 "immediate_operand" "n")]
14623 UNSPEC_MOVESI_TO_CR))]
14624 "GET_CODE (operands[0]) == REG
14625 && CR_REGNO_P (REGNO (operands[0]))
14626 && GET_CODE (operands[2]) == CONST_INT
14627 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14628 "mtcrf %R0,%1"
14629 [(set_attr "type" "mtcr")])
14631 ; The load-multiple instructions have similar properties.
14632 ; Note that "load_multiple" is a name known to the machine-independent
14633 ; code that actually corresponds to the powerpc load-string.
14635 (define_insn "*lmw"
14636 [(match_parallel 0 "lmw_operation"
14637 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14638 (match_operand:SI 2 "memory_operand" "m"))])]
14639 "TARGET_MULTIPLE"
14640 "{lm|lmw} %1,%2")
14642 (define_insn "*return_internal_si"
14643 [(return)
14644 (use (match_operand:SI 0 "register_operand" "lc"))]
14645 "TARGET_32BIT"
14646 "b%T0"
14647 [(set_attr "type" "jmpreg")])
14649 (define_insn "*return_internal_di"
14650 [(return)
14651 (use (match_operand:DI 0 "register_operand" "lc"))]
14652 "TARGET_64BIT"
14653 "b%T0"
14654 [(set_attr "type" "jmpreg")])
14656 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14657 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14659 (define_insn "*return_and_restore_fpregs_si"
14660 [(match_parallel 0 "any_parallel_operand"
14661 [(return)
14662 (use (match_operand:SI 1 "register_operand" "l"))
14663 (use (match_operand:SI 2 "call_operand" "s"))
14664 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14665 (match_operand:DF 4 "memory_operand" "m"))])]
14666 "TARGET_32BIT"
14667 "b %z2")
14669 (define_insn "*return_and_restore_fpregs_di"
14670 [(match_parallel 0 "any_parallel_operand"
14671 [(return)
14672 (use (match_operand:DI 1 "register_operand" "l"))
14673 (use (match_operand:DI 2 "call_operand" "s"))
14674 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14675 (match_operand:DF 4 "memory_operand" "m"))])]
14676 "TARGET_64BIT"
14677 "b %z2")
14679 ; This is used in compiling the unwind routines.
14680 (define_expand "eh_return"
14681 [(use (match_operand 0 "general_operand" ""))]
14682 ""
14683 "
14684 {
14685 if (TARGET_32BIT)
14686 emit_insn (gen_eh_set_lr_si (operands[0]));
14687 else
14688 emit_insn (gen_eh_set_lr_di (operands[0]));
14689 DONE;
14690 }")
14692 ; We can't expand this before we know where the link register is stored.
14693 (define_insn "eh_set_lr_si"
14694 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14695 UNSPECV_EH_RR)
14696 (clobber (match_scratch:SI 1 "=&b"))]
14697 "TARGET_32BIT"
14698 "#")
14700 (define_insn "eh_set_lr_di"
14701 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14702 UNSPECV_EH_RR)
14703 (clobber (match_scratch:DI 1 "=&b"))]
14704 "TARGET_64BIT"
14705 "#")
14707 (define_split
14708 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14709 (clobber (match_scratch 1 ""))]
14710 "reload_completed"
14711 [(const_int 0)]
14712 "
14713 {
14714 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14715 DONE;
14716 }")
14718 (define_insn "prefetch"
14719 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14720 (match_operand:SI 1 "const_int_operand" "n")
14721 (match_operand:SI 2 "const_int_operand" "n"))]
14722 "TARGET_POWERPC"
14723 "*
14724 {
14725 if (GET_CODE (operands[0]) == REG)
14726 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14727 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14728 }"
14729 [(set_attr "type" "load")])
14731 (include "altivec.md")
14732 (include "spe.md")