1 ;; Scheduling description for IBM RS64 processors.
2 ;; Copyright (C) 2003-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 3, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_automaton "rs64,rs64fp")
21 (define_cpu_unit "iu_rs64" "rs64")
22 (define_cpu_unit "mciu_rs64" "rs64")
23 (define_cpu_unit "fpu_rs64" "rs64fp")
24 (define_cpu_unit "lsu_rs64,bpu_rs64" "rs64")
26 ;; RS64a 64-bit IU, LSU, FPU, BPU
28 (define_insn_reservation "rs64a-load" 2
29 (and (eq_attr "type" "load")
30 (eq_attr "cpu" "rs64a"))
33 (define_insn_reservation "rs64a-store" 2
34 (and (eq_attr "type" "store,fpstore")
35 (eq_attr "cpu" "rs64a"))
38 (define_insn_reservation "rs64a-fpload" 3
39 (and (eq_attr "type" "fpload")
40 (eq_attr "cpu" "rs64a"))
43 (define_insn_reservation "rs64a-llsc" 2
44 (and (eq_attr "type" "load_l,store_c")
45 (eq_attr "cpu" "rs64a"))
48 (define_insn_reservation "rs64a-integer" 1
49 (and (eq_attr "type" "integer,insert,shift,trap,\
50 var_shift_rotate,cntlz,exts,isel")
51 (eq_attr "cpu" "rs64a"))
54 (define_insn_reservation "rs64a-two" 1
55 (and (eq_attr "type" "two")
56 (eq_attr "cpu" "rs64a"))
59 (define_insn_reservation "rs64a-three" 1
60 (and (eq_attr "type" "three")
61 (eq_attr "cpu" "rs64a"))
62 "iu_rs64,iu_rs64,iu_rs64")
64 (define_insn_reservation "rs64a-imul" 20
65 (and (eq_attr "type" "mul")
67 (eq_attr "cpu" "rs64a"))
70 (define_insn_reservation "rs64a-imul2" 12
71 (and (eq_attr "type" "mul")
73 (eq_attr "cpu" "rs64a"))
76 (define_insn_reservation "rs64a-imul3" 8
77 (and (eq_attr "type" "mul")
79 (eq_attr "cpu" "rs64a"))
82 (define_insn_reservation "rs64a-lmul" 34
83 (and (eq_attr "type" "mul")
85 (eq_attr "cpu" "rs64a"))
88 (define_insn_reservation "rs64a-idiv" 66
89 (and (eq_attr "type" "div")
91 (eq_attr "cpu" "rs64a"))
94 (define_insn_reservation "rs64a-ldiv" 66
95 (and (eq_attr "type" "div")
97 (eq_attr "cpu" "rs64a"))
100 (define_insn_reservation "rs64a-compare" 3
101 (and (eq_attr "type" "cmp,fast_compare,compare,\
102 delayed_compare,var_delayed_compare")
103 (eq_attr "cpu" "rs64a"))
104 "iu_rs64,nothing,bpu_rs64")
106 (define_insn_reservation "rs64a-fpcompare" 5
107 (and (eq_attr "type" "fpcompare")
108 (eq_attr "cpu" "rs64a"))
109 "mciu_rs64,fpu_rs64,bpu_rs64")
111 (define_insn_reservation "rs64a-fp" 4
112 (and (eq_attr "type" "fp,dmul")
113 (eq_attr "cpu" "rs64a"))
114 "mciu_rs64,fpu_rs64")
116 (define_insn_reservation "rs64a-sdiv" 31
117 (and (eq_attr "type" "sdiv,ddiv")
118 (eq_attr "cpu" "rs64a"))
119 "mciu_rs64,fpu_rs64*31")
121 (define_insn_reservation "rs64a-sqrt" 49
122 (and (eq_attr "type" "ssqrt,dsqrt")
123 (eq_attr "cpu" "rs64a"))
124 "mciu_rs64,fpu_rs64*49")
126 (define_insn_reservation "rs64a-mfcr" 2
127 (and (eq_attr "type" "mfcr")
128 (eq_attr "cpu" "rs64a"))
131 (define_insn_reservation "rs64a-mtcr" 3
132 (and (eq_attr "type" "mtcr")
133 (eq_attr "cpu" "rs64a"))
136 (define_insn_reservation "rs64a-mtjmpr" 3
137 (and (eq_attr "type" "mtjmpr")
138 (eq_attr "cpu" "rs64a"))
141 (define_insn_reservation "rs64a-mfjmpr" 2
142 (and (eq_attr "type" "mfjmpr")
143 (eq_attr "cpu" "rs64a"))
146 (define_insn_reservation "rs64a-jmpreg" 1
147 (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr")
148 (eq_attr "cpu" "rs64a"))
151 (define_insn_reservation "rs64a-isync" 6
152 (and (eq_attr "type" "isync")
153 (eq_attr "cpu" "rs64a"))
156 (define_insn_reservation "rs64a-sync" 1
157 (and (eq_attr "type" "sync")
158 (eq_attr "cpu" "rs64a"))