1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (match_operand 0 "register_operand")
38 if (GET_CODE (op) == SUBREG)
44 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
47 return ALTIVEC_REGNO_P (REGNO (op));
50 ;; Return 1 if op is a VSX register.
51 (define_predicate "vsx_register_operand"
52 (match_operand 0 "register_operand")
54 if (GET_CODE (op) == SUBREG)
60 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
63 return VSX_REGNO_P (REGNO (op));
66 ;; Return 1 if op is a vector register that operates on floating point vectors
67 ;; (either altivec or VSX).
68 (define_predicate "vfloat_operand"
69 (match_operand 0 "register_operand")
71 if (GET_CODE (op) == SUBREG)
77 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
80 return VFLOAT_REGNO_P (REGNO (op));
83 ;; Return 1 if op is a vector register that operates on integer vectors
84 ;; (only altivec, VSX doesn't support integer vectors)
85 (define_predicate "vint_operand"
86 (match_operand 0 "register_operand")
88 if (GET_CODE (op) == SUBREG)
94 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
97 return VINT_REGNO_P (REGNO (op));
100 ;; Return 1 if op is a vector register to do logical operations on (and, or,
102 (define_predicate "vlogical_operand"
103 (match_operand 0 "register_operand")
105 if (GET_CODE (op) == SUBREG)
106 op = SUBREG_REG (op);
111 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
114 return VLOGICAL_REGNO_P (REGNO (op));
117 ;; Return 1 if op is the carry register.
118 (define_predicate "ca_operand"
119 (and (match_code "reg")
120 (match_test "CA_REGNO_P (REGNO (op))")))
122 ;; Return 1 if op is a signed 5-bit constant integer.
123 (define_predicate "s5bit_cint_operand"
124 (and (match_code "const_int")
125 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
127 ;; Return 1 if op is a unsigned 3-bit constant integer.
128 (define_predicate "u3bit_cint_operand"
129 (and (match_code "const_int")
130 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
132 ;; Return 1 if op is a unsigned 5-bit constant integer.
133 (define_predicate "u5bit_cint_operand"
134 (and (match_code "const_int")
135 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
137 ;; Return 1 if op is a signed 8-bit constant integer.
138 ;; Integer multiplication complete more quickly
139 (define_predicate "s8bit_cint_operand"
140 (and (match_code "const_int")
141 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
143 ;; Return 1 if op is a unsigned 10-bit constant integer.
144 (define_predicate "u10bit_cint_operand"
145 (and (match_code "const_int")
146 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
148 ;; Return 1 if op is a constant integer that can fit in a D field.
149 (define_predicate "short_cint_operand"
150 (and (match_code "const_int")
151 (match_test "satisfies_constraint_I (op)")))
153 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
154 (define_predicate "u_short_cint_operand"
155 (and (match_code "const_int")
156 (match_test "satisfies_constraint_K (op)")))
158 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
159 (define_predicate "non_short_cint_operand"
160 (and (match_code "const_int")
161 (match_test "(unsigned HOST_WIDE_INT)
162 (INTVAL (op) + 0x8000) >= 0x10000")))
164 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
165 (define_predicate "exact_log2_cint_operand"
166 (and (match_code "const_int")
167 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
169 ;; Match op = 0 or op = 1.
170 (define_predicate "const_0_to_1_operand"
171 (and (match_code "const_int")
172 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
175 (define_predicate "const_0_to_3_operand"
176 (and (match_code "const_int")
177 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
179 ;; Match op = 2 or op = 3.
180 (define_predicate "const_2_to_3_operand"
181 (and (match_code "const_int")
182 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
185 (define_predicate "const_0_to_15_operand"
186 (and (match_code "const_int")
187 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
189 ;; Return 1 if op is a register that is not special.
190 (define_predicate "gpc_reg_operand"
191 (match_operand 0 "register_operand")
193 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
196 if (GET_CODE (op) == SUBREG)
197 op = SUBREG_REG (op);
202 if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op)))
205 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
208 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
211 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
212 ;; allow floating point or vector registers.
213 (define_predicate "int_reg_operand"
214 (match_operand 0 "register_operand")
216 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
219 if (GET_CODE (op) == SUBREG)
220 op = SUBREG_REG (op);
225 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
228 return INT_REGNO_P (REGNO (op));
231 ;; Like int_reg_operand, but only return true for base registers
232 (define_predicate "base_reg_operand"
233 (match_operand 0 "int_reg_operand")
235 if (GET_CODE (op) == SUBREG)
236 op = SUBREG_REG (op);
241 return (REGNO (op) != FIRST_GPR_REGNO);
244 ;; Return 1 if op is a HTM specific SPR register.
245 (define_predicate "htm_spr_reg_operand"
246 (match_operand 0 "register_operand")
251 if (GET_CODE (op) == SUBREG)
252 op = SUBREG_REG (op);
271 ;; Return 1 if op is a general purpose register that is an even register
272 ;; which suitable for a load/store quad operation
273 (define_predicate "quad_int_reg_operand"
274 (match_operand 0 "register_operand")
278 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
281 if (GET_CODE (op) == SUBREG)
282 op = SUBREG_REG (op);
288 if (r >= FIRST_PSEUDO_REGISTER)
291 return (INT_REGNO_P (r) && ((r & 1) == 0));
294 ;; Return 1 if op is a register that is a condition register field.
295 (define_predicate "cc_reg_operand"
296 (match_operand 0 "register_operand")
298 if (GET_CODE (op) == SUBREG)
299 op = SUBREG_REG (op);
304 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
307 return CR_REGNO_P (REGNO (op));
310 ;; Return 1 if op is a register that is a condition register field not cr0.
311 (define_predicate "cc_reg_not_cr0_operand"
312 (match_operand 0 "register_operand")
314 if (GET_CODE (op) == SUBREG)
315 op = SUBREG_REG (op);
320 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
323 return CR_REGNO_NOT_CR0_P (REGNO (op));
326 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
327 (define_predicate "cc_reg_not_micro_cr0_operand"
328 (match_operand 0 "register_operand")
330 if (GET_CODE (op) == SUBREG)
331 op = SUBREG_REG (op);
336 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
339 if (rs6000_gen_cell_microcode)
340 return CR_REGNO_NOT_CR0_P (REGNO (op));
342 return CR_REGNO_P (REGNO (op));
345 ;; Return 1 if op is a constant integer valid for D field
346 ;; or non-special register register.
347 (define_predicate "reg_or_short_operand"
348 (if_then_else (match_code "const_int")
349 (match_operand 0 "short_cint_operand")
350 (match_operand 0 "gpc_reg_operand")))
352 ;; Return 1 if op is a constant integer valid whose negation is valid for
353 ;; D field or non-special register register.
354 ;; Do not allow a constant zero because all patterns that call this
355 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
356 ;; or equal to const, which does not work for zero.
357 (define_predicate "reg_or_neg_short_operand"
358 (if_then_else (match_code "const_int")
359 (match_test "satisfies_constraint_P (op)
360 && INTVAL (op) != 0")
361 (match_operand 0 "gpc_reg_operand")))
363 ;; Return 1 if op is a constant integer valid for DS field
364 ;; or non-special register.
365 (define_predicate "reg_or_aligned_short_operand"
366 (if_then_else (match_code "const_int")
367 (and (match_operand 0 "short_cint_operand")
368 (match_test "!(INTVAL (op) & 3)"))
369 (match_operand 0 "gpc_reg_operand")))
371 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
372 ;; or non-special register.
373 (define_predicate "reg_or_u_short_operand"
374 (if_then_else (match_code "const_int")
375 (match_operand 0 "u_short_cint_operand")
376 (match_operand 0 "gpc_reg_operand")))
378 ;; Return 1 if op is any constant integer
379 ;; or non-special register.
380 (define_predicate "reg_or_cint_operand"
381 (ior (match_code "const_int")
382 (match_operand 0 "gpc_reg_operand")))
384 ;; Return 1 if op is a constant integer valid for addition with addis, addi.
385 (define_predicate "add_cint_operand"
386 (and (match_code "const_int")
387 (match_test "(unsigned HOST_WIDE_INT)
388 (INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
389 < (unsigned HOST_WIDE_INT) 0x100000000ll")))
391 ;; Return 1 if op is a constant integer valid for addition
392 ;; or non-special register.
393 (define_predicate "reg_or_add_cint_operand"
394 (if_then_else (match_code "const_int")
395 (match_operand 0 "add_cint_operand")
396 (match_operand 0 "gpc_reg_operand")))
398 ;; Return 1 if op is a constant integer valid for subtraction
399 ;; or non-special register.
400 (define_predicate "reg_or_sub_cint_operand"
401 (if_then_else (match_code "const_int")
402 (match_test "(unsigned HOST_WIDE_INT)
403 (- INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
404 < (unsigned HOST_WIDE_INT) 0x100000000ll")
405 (match_operand 0 "gpc_reg_operand")))
407 ;; Return 1 if op is any 32-bit unsigned constant integer
408 ;; or non-special register.
409 (define_predicate "reg_or_logical_cint_operand"
410 (if_then_else (match_code "const_int")
411 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
413 || ((INTVAL (op) & GET_MODE_MASK (mode)
414 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
415 (match_operand 0 "gpc_reg_operand")))
417 ;; Like reg_or_logical_cint_operand, but allow vsx registers
418 (define_predicate "vsx_reg_or_cint_operand"
419 (ior (match_operand 0 "vsx_register_operand")
420 (match_operand 0 "reg_or_logical_cint_operand")))
422 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
423 ;; with no more than one instruction per word.
424 (define_predicate "easy_fp_constant"
425 (match_code "const_double")
430 if (GET_MODE (op) != mode
431 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
434 /* Consider all constants with -msoft-float to be easy. */
435 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
436 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
440 /* The constant 0.0 is easy under VSX. */
441 if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode)
442 && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode))
445 if (DECIMAL_FLOAT_MODE_P (mode))
448 /* If we are using V.4 style PIC, consider all constants to be hard. */
449 if (flag_pic && DEFAULT_ABI == ABI_V4)
452 #ifdef TARGET_RELOCATABLE
453 /* Similarly if we are using -mrelocatable, consider all constants
455 if (TARGET_RELOCATABLE)
462 if (TARGET_E500_DOUBLE)
465 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
466 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
468 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
469 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
470 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
471 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
474 /* The constant 0.f is easy under VSX. */
475 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode))
478 /* Force constants to memory before reload to utilize
479 compress_float_constant.
480 Avoid this when flag_unsafe_math_optimizations is enabled
481 because RDIV division to reciprocal optimization is not able
482 to regenerate the division. */
483 if (TARGET_E500_DOUBLE
484 || (!reload_in_progress && !reload_completed
485 && !flag_unsafe_math_optimizations))
488 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
489 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
491 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
492 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
495 /* The constant 0.f is easy. */
496 if (op == CONST0_RTX (SFmode))
499 /* Force constants to memory before reload to utilize
500 compress_float_constant.
501 Avoid this when flag_unsafe_math_optimizations is enabled
502 because RDIV division to reciprocal optimization is not able
503 to regenerate the division. */
504 if (!reload_in_progress && !reload_completed
505 && !flag_unsafe_math_optimizations)
508 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
509 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
511 return num_insns_constant_wide (k[0]) == 1;
514 return (num_insns_constant (op, DImode) <= 2);
524 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
525 ;; vector register without using memory.
526 (define_predicate "easy_vector_constant"
527 (match_code "const_vector")
529 /* As the paired vectors are actually FPRs it seems that there is
530 no easy way to load a CONST_VECTOR without using memory. */
531 if (TARGET_PAIRED_FLOAT)
534 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
536 if (zero_constant (op, mode))
539 return easy_altivec_constant (op, mode);
542 if (SPE_VECTOR_MODE (mode))
545 if (zero_constant (op, mode))
547 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
550 /* Limit SPE vectors to 15 bits signed. These we can generate with:
555 I don't know how efficient it would be to allow bigger constants,
556 considering we'll have an extra 'ori' for every 'li'. I doubt 5
557 instructions is better than a 64-bit memory load, but I don't
558 have the e500 timing specs. */
559 if (mode == V2SImode)
561 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
562 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
563 return cst >= -0x7fff && cst <= 0x7fff
564 && cst2 >= -0x7fff && cst2 <= 0x7fff;
571 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
572 (define_predicate "easy_vector_constant_add_self"
573 (and (match_code "const_vector")
574 (and (match_test "TARGET_ALTIVEC")
575 (match_test "easy_altivec_constant (op, mode)")))
579 if (mode == V2DImode || mode == V2DFmode)
581 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
582 val = const_vector_elt_as_int (op, elt);
583 val = ((val & 0xff) ^ 0x80) - 0x80;
584 return EASY_VECTOR_15_ADD_SELF (val);
587 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
588 (define_predicate "easy_vector_constant_msb"
589 (and (match_code "const_vector")
590 (and (match_test "TARGET_ALTIVEC")
591 (match_test "easy_altivec_constant (op, mode)")))
595 if (mode == V2DImode || mode == V2DFmode)
597 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
598 val = const_vector_elt_as_int (op, elt);
599 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
602 ;; Return 1 if operand is constant zero (scalars and vectors).
603 (define_predicate "zero_constant"
604 (and (match_code "const_int,const_double,const_wide_int,const_vector")
605 (match_test "op == CONST0_RTX (mode)")))
607 ;; Return 1 if operand is 0.0.
608 (define_predicate "zero_fp_constant"
609 (and (match_code "const_double")
610 (match_test "SCALAR_FLOAT_MODE_P (mode)
611 && op == CONST0_RTX (mode)")))
613 ;; Return 1 if the operand is in volatile memory. Note that during the
614 ;; RTL generation phase, memory_operand does not return TRUE for volatile
615 ;; memory references. So this function allows us to recognize volatile
616 ;; references where it's safe.
617 (define_predicate "volatile_mem_operand"
618 (and (and (match_code "mem")
619 (match_test "MEM_VOLATILE_P (op)"))
620 (if_then_else (match_test "reload_completed")
621 (match_operand 0 "memory_operand")
622 (if_then_else (match_test "reload_in_progress")
623 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
624 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
626 ;; Return 1 if the operand is an offsettable memory operand.
627 (define_predicate "offsettable_mem_operand"
628 (and (match_operand 0 "memory_operand")
629 (match_test "offsettable_nonstrict_memref_p (op)")))
631 ;; Return 1 if the operand is suitable for load/store quad memory.
632 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
633 (define_predicate "quad_memory_operand"
639 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
642 else if (!memory_operand (op, mode))
645 else if (GET_MODE_SIZE (GET_MODE (op)) != 16)
648 else if (MEM_ALIGN (op) < 128)
654 if (int_reg_operand (addr, Pmode))
657 else if (GET_CODE (addr) != PLUS)
662 op0 = XEXP (addr, 0);
663 op1 = XEXP (addr, 1);
664 ret = (int_reg_operand (op0, Pmode)
665 && GET_CODE (op1) == CONST_INT
666 && IN_RANGE (INTVAL (op1), -32768, 32767)
667 && (INTVAL (op1) & 15) == 0);
671 if (TARGET_DEBUG_ADDR)
673 fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false");
680 ;; Return 1 if the operand is an indexed or indirect memory operand.
681 (define_predicate "indexed_or_indirect_operand"
685 if (VECTOR_MEM_ALTIVEC_P (mode)
686 && GET_CODE (op) == AND
687 && GET_CODE (XEXP (op, 1)) == CONST_INT
688 && INTVAL (XEXP (op, 1)) == -16)
691 return indexed_or_indirect_address (op, mode);
694 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
695 ;; moves are supported.
696 (define_predicate "reg_or_indexed_operand"
697 (match_code "mem,reg")
700 return indexed_or_indirect_operand (op, mode);
701 else if (TARGET_DIRECT_MOVE)
702 return register_operand (op, mode);
707 ;; Return 1 if the operand is an indexed or indirect memory operand with an
708 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
709 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
710 ;; while VSX uses the full address and traps)
711 (define_predicate "altivec_indexed_or_indirect_operand"
715 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
716 && GET_CODE (op) == AND
717 && GET_CODE (XEXP (op, 1)) == CONST_INT
718 && INTVAL (XEXP (op, 1)) == -16)
719 return indexed_or_indirect_address (XEXP (op, 0), mode);
724 ;; Return 1 if the operand is an indexed or indirect address.
725 (define_special_predicate "indexed_or_indirect_address"
726 (and (match_test "REG_P (op)
727 || (GET_CODE (op) == PLUS
728 /* Omit testing REG_P (XEXP (op, 0)). */
729 && REG_P (XEXP (op, 1)))")
730 (match_operand 0 "address_operand")))
732 ;; Return 1 if the operand is an index-form address.
733 (define_special_predicate "indexed_address"
734 (match_test "(GET_CODE (op) == PLUS
735 && REG_P (XEXP (op, 0))
736 && REG_P (XEXP (op, 1)))"))
738 ;; Return 1 if the operand is a MEM with an update-form address. This may
739 ;; also include update-indexed form.
740 (define_special_predicate "update_address_mem"
741 (match_test "(MEM_P (op)
742 && (GET_CODE (XEXP (op, 0)) == PRE_INC
743 || GET_CODE (XEXP (op, 0)) == PRE_DEC
744 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
746 ;; Return 1 if the operand is a MEM with an indexed-form address.
747 (define_special_predicate "indexed_address_mem"
748 (match_test "(MEM_P (op)
749 && (indexed_address (XEXP (op, 0), mode)
750 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY
751 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))"))
753 ;; Used for the destination of the fix_truncdfsi2 expander.
754 ;; If stfiwx will be used, the result goes to memory; otherwise,
755 ;; we're going to emit a store and a load of a subreg, so the dest is a
757 (define_predicate "fix_trunc_dest_operand"
758 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
759 (match_operand 0 "memory_operand")
760 (match_operand 0 "gpc_reg_operand")))
762 ;; Return 1 if the operand is either a non-special register or can be used
763 ;; as the operand of a `mode' add insn.
764 (define_predicate "add_operand"
765 (if_then_else (match_code "const_int")
766 (match_test "satisfies_constraint_I (op)
767 || satisfies_constraint_L (op)")
768 (match_operand 0 "gpc_reg_operand")))
770 ;; Return 1 if OP is a constant but not a valid add_operand.
771 (define_predicate "non_add_cint_operand"
772 (and (match_code "const_int")
773 (match_test "!satisfies_constraint_I (op)
774 && !satisfies_constraint_L (op)")))
776 ;; Return 1 if the operand is a constant that can be used as the operand
778 (define_predicate "logical_const_operand"
779 (match_code "const_int")
783 opl = INTVAL (op) & GET_MODE_MASK (mode);
785 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
786 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
789 ;; Return 1 if the operand is a non-special register or a constant that
790 ;; can be used as the operand of an OR or XOR.
791 (define_predicate "logical_operand"
792 (ior (match_operand 0 "gpc_reg_operand")
793 (match_operand 0 "logical_const_operand")))
795 ;; Return 1 if op is a constant that is not a logical operand, but could
796 ;; be split into one.
797 (define_predicate "non_logical_cint_operand"
798 (and (match_code "const_int,const_wide_int")
799 (and (not (match_operand 0 "logical_operand"))
800 (match_operand 0 "reg_or_logical_cint_operand"))))
802 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
803 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
804 ;; transitions). Reject all ones and all zeros, since these should have
805 ;; been optimized away and confuse the making of MB and ME.
806 (define_predicate "mask_operand"
807 (match_code "const_int")
809 HOST_WIDE_INT c, lsb;
813 if (TARGET_POWERPC64)
815 /* Fail if the mask is not 32-bit. */
816 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
819 /* Fail if the mask wraps around because the upper 32-bits of the
820 mask will all be 1s, contrary to GCC's internal view. */
821 if ((c & 0x80000001) == 0x80000001)
825 /* We don't change the number of transitions by inverting,
826 so make sure we start with the LS bit zero. */
830 /* Reject all zeros or all ones. */
834 /* Find the first transition. */
837 /* Invert to look for a second transition. */
840 /* Erase first transition. */
843 /* Find the second transition (if any). */
846 /* Match if all the bits above are 1's (or c is zero). */
850 ;; Return 1 for the PowerPC64 rlwinm corner case.
851 (define_predicate "mask_operand_wrap"
852 (match_code "const_int")
854 HOST_WIDE_INT c, lsb;
858 if ((c & 0x80000001) != 0x80000001)
872 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
873 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
874 ;; transition). Reject all zeros, since zero should have been
875 ;; optimized away and confuses the making of MB and ME.
876 (define_predicate "mask64_operand"
877 (match_code "const_int")
879 HOST_WIDE_INT c, lsb;
883 /* Reject all zeros. */
887 /* We don't change the number of transitions by inverting,
888 so make sure we start with the LS bit zero. */
892 /* Find the first transition. */
895 /* Match if all the bits above are 1's (or c is zero). */
899 ;; Like mask64_operand, but allow up to three transitions. This
900 ;; predicate is used by insn patterns that generate two rldicl or
901 ;; rldicr machine insns.
902 (define_predicate "mask64_2_operand"
903 (match_code "const_int")
905 HOST_WIDE_INT c, lsb;
909 /* Disallow all zeros. */
913 /* We don't change the number of transitions by inverting,
914 so make sure we start with the LS bit zero. */
918 /* Find the first transition. */
921 /* Invert to look for a second transition. */
924 /* Erase first transition. */
927 /* Find the second transition. */
930 /* Invert to look for a third transition. */
933 /* Erase second transition. */
936 /* Find the third transition (if any). */
939 /* Match if all the bits above are 1's (or c is zero). */
943 ;; Like and_operand, but also match constants that can be implemented
944 ;; with two rldicl or rldicr insns.
945 (define_predicate "and64_2_operand"
946 (ior (match_operand 0 "mask64_2_operand")
947 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
948 (match_operand 0 "gpc_reg_operand")
949 (match_operand 0 "logical_operand"))))
951 ;; Return 1 if the operand is either a non-special register or a
952 ;; constant that can be used as the operand of a logical AND.
953 (define_predicate "and_operand"
954 (ior (match_operand 0 "mask_operand")
955 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
956 (match_operand 0 "mask64_operand"))
957 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
958 (match_operand 0 "gpc_reg_operand")
959 (match_operand 0 "logical_operand")))))
961 ;; Return 1 if the operand is either a logical operand or a short cint operand.
962 (define_predicate "scc_eq_operand"
963 (ior (match_operand 0 "logical_operand")
964 (match_operand 0 "short_cint_operand")))
966 ;; Return 1 if the operand is a general non-special register or memory operand.
967 (define_predicate "reg_or_mem_operand"
968 (ior (match_operand 0 "memory_operand")
969 (ior (and (match_code "mem")
970 (match_test "macho_lo_sum_memory_operand (op, mode)"))
971 (ior (match_operand 0 "volatile_mem_operand")
972 (match_operand 0 "gpc_reg_operand")))))
974 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
975 (define_predicate "reg_or_none500mem_operand"
976 (if_then_else (match_code "mem")
977 (and (match_test "!TARGET_E500_DOUBLE")
978 (ior (match_operand 0 "memory_operand")
979 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
980 (match_operand 0 "volatile_mem_operand"))))
981 (match_operand 0 "gpc_reg_operand")))
983 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
984 (define_predicate "zero_reg_mem_operand"
985 (ior (match_operand 0 "zero_fp_constant")
986 (match_operand 0 "reg_or_mem_operand")))
988 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
989 ;; data types inside of a vector that scalar instructions operate on
990 (define_predicate "vsx_scalar_64bit"
991 (match_code "const_int")
993 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
996 ;; Return 1 if the operand is a general register or memory operand without
997 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
999 (define_predicate "lwa_operand"
1000 (match_code "reg,subreg,mem")
1002 rtx inner, addr, offset;
1005 if (reload_completed && GET_CODE (inner) == SUBREG)
1006 inner = SUBREG_REG (inner);
1008 if (gpc_reg_operand (inner, mode))
1010 if (!memory_operand (inner, mode))
1012 addr = XEXP (inner, 0);
1013 if (GET_CODE (addr) == PRE_INC
1014 || GET_CODE (addr) == PRE_DEC
1015 || (GET_CODE (addr) == PRE_MODIFY
1016 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
1018 if (GET_CODE (addr) == LO_SUM
1019 && GET_CODE (XEXP (addr, 0)) == REG
1020 && GET_CODE (XEXP (addr, 1)) == CONST)
1021 addr = XEXP (XEXP (addr, 1), 0);
1022 if (GET_CODE (addr) != PLUS)
1024 offset = XEXP (addr, 1);
1025 if (GET_CODE (offset) != CONST_INT)
1027 return INTVAL (offset) % 4 == 0;
1030 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
1031 (define_predicate "symbol_ref_operand"
1032 (and (match_code "symbol_ref")
1033 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
1034 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
1036 ;; Return 1 if op is an operand that can be loaded via the GOT.
1037 ;; or non-special register register field no cr0
1038 (define_predicate "got_operand"
1039 (match_code "symbol_ref,const,label_ref"))
1041 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
1042 ;; excluding labels involving addition.
1043 (define_predicate "got_no_const_operand"
1044 (match_code "symbol_ref,label_ref"))
1046 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
1047 (define_predicate "rs6000_tls_symbol_ref"
1048 (and (match_code "symbol_ref")
1049 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
1051 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1052 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
1053 (define_predicate "call_operand"
1054 (if_then_else (match_code "reg")
1055 (match_test "REGNO (op) == LR_REGNO
1056 || REGNO (op) == CTR_REGNO
1057 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
1058 (match_code "symbol_ref")))
1060 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1062 (define_predicate "current_file_function_operand"
1063 (and (match_code "symbol_ref")
1064 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1065 && ((SYMBOL_REF_LOCAL_P (op)
1066 && ((DEFAULT_ABI != ABI_AIX
1067 && DEFAULT_ABI != ABI_ELFv2)
1068 || !SYMBOL_REF_EXTERNAL_P (op)))
1069 || (op == XEXP (DECL_RTL (current_function_decl),
1072 ;; Return 1 if this operand is a valid input for a move insn.
1073 (define_predicate "input_operand"
1074 (match_code "symbol_ref,const,reg,subreg,mem,
1075 const_double,const_wide_int,const_vector,const_int")
1077 /* Memory is always valid. */
1078 if (memory_operand (op, mode))
1081 /* For floating-point, easy constants are valid. */
1082 if (SCALAR_FLOAT_MODE_P (mode)
1083 && easy_fp_constant (op, mode))
1086 /* Allow any integer constant. */
1087 if (GET_MODE_CLASS (mode) == MODE_INT
1088 && CONST_SCALAR_INT_P (op))
1091 /* Allow easy vector constants. */
1092 if (GET_CODE (op) == CONST_VECTOR
1093 && easy_vector_constant (op, mode))
1096 /* Do not allow invalid E500 subregs. */
1097 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1098 && GET_CODE (op) == SUBREG
1099 && invalid_e500_subreg (op, mode))
1102 /* For floating-point or multi-word mode, the only remaining valid type
1104 if (SCALAR_FLOAT_MODE_P (mode)
1105 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1106 return register_operand (op, mode);
1108 /* The only cases left are integral modes one word or smaller (we
1109 do not get called for MODE_CC values). These can be in any
1111 if (register_operand (op, mode))
1114 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1116 if (DEFAULT_ABI == ABI_V4
1117 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1118 && small_data_operand (op, Pmode))
1124 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1125 (define_predicate "splat_input_operand"
1126 (match_code "symbol_ref,const,reg,subreg,mem,
1127 const_double,const_wide_int,const_vector,const_int")
1131 if (! volatile_ok && MEM_VOLATILE_P (op))
1135 else if (mode == DImode)
1139 return memory_address_addr_space_p (mode, XEXP (op, 0),
1140 MEM_ADDR_SPACE (op));
1142 return input_operand (op, mode);
1145 ;; Return true if OP is a non-immediate operand and not an invalid
1146 ;; SUBREG operation on the e500.
1147 (define_predicate "rs6000_nonimmediate_operand"
1148 (match_code "reg,subreg,mem")
1150 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1151 && GET_CODE (op) == SUBREG
1152 && invalid_e500_subreg (op, mode))
1155 return nonimmediate_operand (op, mode);
1158 ;; Return true if operand is boolean operator.
1159 (define_predicate "boolean_operator"
1160 (match_code "and,ior,xor"))
1162 ;; Return true if operand is OR-form of boolean operator.
1163 (define_predicate "boolean_or_operator"
1164 (match_code "ior,xor"))
1166 ;; Return true if operand is an equality operator.
1167 (define_special_predicate "equality_operator"
1168 (match_code "eq,ne"))
1170 ;; Return true if operand is MIN or MAX operator.
1171 (define_predicate "min_max_operator"
1172 (match_code "smin,smax,umin,umax"))
1174 ;; Return 1 if OP is a comparison operation that is valid for a branch
1175 ;; instruction. We check the opcode against the mode of the CC value.
1176 ;; validate_condition_mode is an assertion.
1177 (define_predicate "branch_comparison_operator"
1178 (and (match_operand 0 "comparison_operator")
1179 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1180 (match_test "validate_condition_mode (GET_CODE (op),
1181 GET_MODE (XEXP (op, 0))),
1184 ;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
1185 ;; If we're assuming that FP operations cannot generate user-visible traps,
1186 ;; then on e500 we can use the ordered-signaling instructions to implement
1187 ;; the unordered-quiet FP comparison predicates modulo a reversal.
1188 (define_predicate "rs6000_cbranch_operator"
1189 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
1190 (if_then_else (match_test "flag_trapping_math")
1191 (match_operand 0 "ordered_comparison_operator")
1192 (ior (match_operand 0 "ordered_comparison_operator")
1193 (match_code ("unlt,unle,ungt,unge"))))
1194 (match_operand 0 "comparison_operator")))
1196 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1197 ;; it must be a positive comparison.
1198 (define_predicate "scc_comparison_operator"
1199 (and (match_operand 0 "branch_comparison_operator")
1200 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1202 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1204 (define_predicate "scc_rev_comparison_operator"
1205 (and (match_operand 0 "branch_comparison_operator")
1206 (match_code "ne,le,ge,leu,geu,ordered")))
1208 ;; Return 1 if OP is a comparison operation that is valid for a branch
1209 ;; insn, which is true if the corresponding bit in the CC register is set.
1210 (define_predicate "branch_positive_comparison_operator"
1211 (and (match_operand 0 "branch_comparison_operator")
1212 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1214 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1215 (define_predicate "load_multiple_operation"
1216 (match_code "parallel")
1218 int count = XVECLEN (op, 0);
1219 unsigned int dest_regno;
1223 /* Perform a quick check so we don't blow up below. */
1225 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1226 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1227 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1230 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1231 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1233 for (i = 1; i < count; i++)
1235 rtx elt = XVECEXP (op, 0, i);
1237 if (GET_CODE (elt) != SET
1238 || GET_CODE (SET_DEST (elt)) != REG
1239 || GET_MODE (SET_DEST (elt)) != SImode
1240 || REGNO (SET_DEST (elt)) != dest_regno + i
1241 || GET_CODE (SET_SRC (elt)) != MEM
1242 || GET_MODE (SET_SRC (elt)) != SImode
1243 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1244 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1245 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1246 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1253 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1254 ;; The second vector element is a CLOBBER.
1255 (define_predicate "store_multiple_operation"
1256 (match_code "parallel")
1258 int count = XVECLEN (op, 0) - 1;
1259 unsigned int src_regno;
1263 /* Perform a quick check so we don't blow up below. */
1265 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1266 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1267 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1270 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1271 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1273 for (i = 1; i < count; i++)
1275 rtx elt = XVECEXP (op, 0, i + 1);
1277 if (GET_CODE (elt) != SET
1278 || GET_CODE (SET_SRC (elt)) != REG
1279 || GET_MODE (SET_SRC (elt)) != SImode
1280 || REGNO (SET_SRC (elt)) != src_regno + i
1281 || GET_CODE (SET_DEST (elt)) != MEM
1282 || GET_MODE (SET_DEST (elt)) != SImode
1283 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1284 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1285 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1286 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1293 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1295 (define_predicate "save_world_operation"
1296 (match_code "parallel")
1301 int count = XVECLEN (op, 0);
1307 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1308 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1311 for (i=1; i <= 18; i++)
1313 elt = XVECEXP (op, 0, index++);
1314 if (GET_CODE (elt) != SET
1315 || GET_CODE (SET_DEST (elt)) != MEM
1316 || ! memory_operand (SET_DEST (elt), DFmode)
1317 || GET_CODE (SET_SRC (elt)) != REG
1318 || GET_MODE (SET_SRC (elt)) != DFmode)
1322 for (i=1; i <= 12; i++)
1324 elt = XVECEXP (op, 0, index++);
1325 if (GET_CODE (elt) != SET
1326 || GET_CODE (SET_DEST (elt)) != MEM
1327 || GET_CODE (SET_SRC (elt)) != REG
1328 || GET_MODE (SET_SRC (elt)) != V4SImode)
1332 for (i=1; i <= 19; i++)
1334 elt = XVECEXP (op, 0, index++);
1335 if (GET_CODE (elt) != SET
1336 || GET_CODE (SET_DEST (elt)) != MEM
1337 || ! memory_operand (SET_DEST (elt), Pmode)
1338 || GET_CODE (SET_SRC (elt)) != REG
1339 || GET_MODE (SET_SRC (elt)) != Pmode)
1343 elt = XVECEXP (op, 0, index++);
1344 if (GET_CODE (elt) != SET
1345 || GET_CODE (SET_DEST (elt)) != MEM
1346 || ! memory_operand (SET_DEST (elt), Pmode)
1347 || GET_CODE (SET_SRC (elt)) != REG
1348 || REGNO (SET_SRC (elt)) != CR2_REGNO
1349 || GET_MODE (SET_SRC (elt)) != Pmode)
1352 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1353 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1358 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1360 (define_predicate "restore_world_operation"
1361 (match_code "parallel")
1366 int count = XVECLEN (op, 0);
1372 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1373 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1374 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1375 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1378 elt = XVECEXP (op, 0, index++);
1379 if (GET_CODE (elt) != SET
1380 || GET_CODE (SET_SRC (elt)) != MEM
1381 || ! memory_operand (SET_SRC (elt), Pmode)
1382 || GET_CODE (SET_DEST (elt)) != REG
1383 || REGNO (SET_DEST (elt)) != CR2_REGNO
1384 || GET_MODE (SET_DEST (elt)) != Pmode)
1387 for (i=1; i <= 19; i++)
1389 elt = XVECEXP (op, 0, index++);
1390 if (GET_CODE (elt) != SET
1391 || GET_CODE (SET_SRC (elt)) != MEM
1392 || ! memory_operand (SET_SRC (elt), Pmode)
1393 || GET_CODE (SET_DEST (elt)) != REG
1394 || GET_MODE (SET_DEST (elt)) != Pmode)
1398 for (i=1; i <= 12; i++)
1400 elt = XVECEXP (op, 0, index++);
1401 if (GET_CODE (elt) != SET
1402 || GET_CODE (SET_SRC (elt)) != MEM
1403 || GET_CODE (SET_DEST (elt)) != REG
1404 || GET_MODE (SET_DEST (elt)) != V4SImode)
1408 for (i=1; i <= 18; i++)
1410 elt = XVECEXP (op, 0, index++);
1411 if (GET_CODE (elt) != SET
1412 || GET_CODE (SET_SRC (elt)) != MEM
1413 || ! memory_operand (SET_SRC (elt), DFmode)
1414 || GET_CODE (SET_DEST (elt)) != REG
1415 || GET_MODE (SET_DEST (elt)) != DFmode)
1419 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1420 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1421 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1422 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1423 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1428 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1429 (define_predicate "vrsave_operation"
1430 (match_code "parallel")
1432 int count = XVECLEN (op, 0);
1433 unsigned int dest_regno, src_regno;
1437 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1438 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1439 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1440 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1443 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1444 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1446 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1449 for (i = 1; i < count; i++)
1451 rtx elt = XVECEXP (op, 0, i);
1453 if (GET_CODE (elt) != CLOBBER
1454 && GET_CODE (elt) != SET)
1461 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1462 (define_predicate "mfcr_operation"
1463 (match_code "parallel")
1465 int count = XVECLEN (op, 0);
1468 /* Perform a quick check so we don't blow up below. */
1470 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1471 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1472 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1475 for (i = 0; i < count; i++)
1477 rtx exp = XVECEXP (op, 0, i);
1482 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1484 if (GET_CODE (src_reg) != REG
1485 || GET_MODE (src_reg) != CCmode
1486 || ! CR_REGNO_P (REGNO (src_reg)))
1489 if (GET_CODE (exp) != SET
1490 || GET_CODE (SET_DEST (exp)) != REG
1491 || GET_MODE (SET_DEST (exp)) != SImode
1492 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1494 unspec = SET_SRC (exp);
1495 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1497 if (GET_CODE (unspec) != UNSPEC
1498 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1499 || XVECLEN (unspec, 0) != 2
1500 || XVECEXP (unspec, 0, 0) != src_reg
1501 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1502 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1508 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1509 (define_predicate "mtcrf_operation"
1510 (match_code "parallel")
1512 int count = XVECLEN (op, 0);
1516 /* Perform a quick check so we don't blow up below. */
1518 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1519 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1520 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1522 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1524 if (GET_CODE (src_reg) != REG
1525 || GET_MODE (src_reg) != SImode
1526 || ! INT_REGNO_P (REGNO (src_reg)))
1529 for (i = 0; i < count; i++)
1531 rtx exp = XVECEXP (op, 0, i);
1535 if (GET_CODE (exp) != SET
1536 || GET_CODE (SET_DEST (exp)) != REG
1537 || GET_MODE (SET_DEST (exp)) != CCmode
1538 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1540 unspec = SET_SRC (exp);
1541 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1543 if (GET_CODE (unspec) != UNSPEC
1544 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1545 || XVECLEN (unspec, 0) != 2
1546 || XVECEXP (unspec, 0, 0) != src_reg
1547 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1548 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1554 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1555 (define_predicate "crsave_operation"
1556 (match_code "parallel")
1558 int count = XVECLEN (op, 0);
1561 for (i = 1; i < count; i++)
1563 rtx exp = XVECEXP (op, 0, i);
1565 if (GET_CODE (exp) != USE
1566 || GET_CODE (XEXP (exp, 0)) != REG
1567 || GET_MODE (XEXP (exp, 0)) != CCmode
1568 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1574 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1575 (define_predicate "lmw_operation"
1576 (match_code "parallel")
1578 int count = XVECLEN (op, 0);
1579 unsigned int dest_regno;
1581 unsigned int base_regno;
1582 HOST_WIDE_INT offset;
1585 /* Perform a quick check so we don't blow up below. */
1587 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1588 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1589 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1592 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1593 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1596 || count != 32 - (int) dest_regno)
1599 if (legitimate_indirect_address_p (src_addr, 0))
1602 base_regno = REGNO (src_addr);
1603 if (base_regno == 0)
1606 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1608 offset = INTVAL (XEXP (src_addr, 1));
1609 base_regno = REGNO (XEXP (src_addr, 0));
1614 for (i = 0; i < count; i++)
1616 rtx elt = XVECEXP (op, 0, i);
1619 HOST_WIDE_INT newoffset;
1621 if (GET_CODE (elt) != SET
1622 || GET_CODE (SET_DEST (elt)) != REG
1623 || GET_MODE (SET_DEST (elt)) != SImode
1624 || REGNO (SET_DEST (elt)) != dest_regno + i
1625 || GET_CODE (SET_SRC (elt)) != MEM
1626 || GET_MODE (SET_SRC (elt)) != SImode)
1628 newaddr = XEXP (SET_SRC (elt), 0);
1629 if (legitimate_indirect_address_p (newaddr, 0))
1634 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1636 addr_reg = XEXP (newaddr, 0);
1637 newoffset = INTVAL (XEXP (newaddr, 1));
1641 if (REGNO (addr_reg) != base_regno
1642 || newoffset != offset + 4 * i)
1649 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1650 (define_predicate "stmw_operation"
1651 (match_code "parallel")
1653 int count = XVECLEN (op, 0);
1654 unsigned int src_regno;
1656 unsigned int base_regno;
1657 HOST_WIDE_INT offset;
1660 /* Perform a quick check so we don't blow up below. */
1662 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1663 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1664 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1667 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1668 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1671 || count != 32 - (int) src_regno)
1674 if (legitimate_indirect_address_p (dest_addr, 0))
1677 base_regno = REGNO (dest_addr);
1678 if (base_regno == 0)
1681 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1683 offset = INTVAL (XEXP (dest_addr, 1));
1684 base_regno = REGNO (XEXP (dest_addr, 0));
1689 for (i = 0; i < count; i++)
1691 rtx elt = XVECEXP (op, 0, i);
1694 HOST_WIDE_INT newoffset;
1696 if (GET_CODE (elt) != SET
1697 || GET_CODE (SET_SRC (elt)) != REG
1698 || GET_MODE (SET_SRC (elt)) != SImode
1699 || REGNO (SET_SRC (elt)) != src_regno + i
1700 || GET_CODE (SET_DEST (elt)) != MEM
1701 || GET_MODE (SET_DEST (elt)) != SImode)
1703 newaddr = XEXP (SET_DEST (elt), 0);
1704 if (legitimate_indirect_address_p (newaddr, 0))
1709 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1711 addr_reg = XEXP (newaddr, 0);
1712 newoffset = INTVAL (XEXP (newaddr, 1));
1716 if (REGNO (addr_reg) != base_regno
1717 || newoffset != offset + 4 * i)
1724 ;; Return 1 if OP is a stack tie operand.
1725 (define_predicate "tie_operand"
1726 (match_code "parallel")
1728 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1729 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1730 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1731 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1734 ;; Match a small code model toc reference (or medium and large
1735 ;; model toc references before reload).
1736 (define_predicate "small_toc_ref"
1737 (match_code "unspec,plus")
1739 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1742 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1745 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1746 ;; GPR registers on power8.
1747 (define_predicate "fusion_gpr_addis"
1748 (match_code "const_int,high,plus")
1750 HOST_WIDE_INT value;
1753 if (GET_CODE (op) == HIGH)
1756 if (CONST_INT_P (op))
1759 else if (GET_CODE (op) == PLUS
1760 && base_reg_operand (XEXP (op, 0), Pmode)
1761 && CONST_INT_P (XEXP (op, 1)))
1762 int_const = XEXP (op, 1);
1767 /* Power8 currently will only do the fusion if the top 11 bits of the addis
1768 value are all 1's or 0's. */
1769 value = INTVAL (int_const);
1770 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1773 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1776 return (IN_RANGE (value >> 16, -32, 31));
1779 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1780 ;; and loads to GPR registers on power8.
1781 (define_predicate "fusion_gpr_mem_load"
1782 (match_code "mem,sign_extend,zero_extend")
1786 /* Handle sign/zero extend. */
1787 if (GET_CODE (op) == ZERO_EXTEND
1788 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1791 mode = GET_MODE (op);
1805 if (!TARGET_POWERPC64)
1813 addr = XEXP (op, 0);
1814 if (GET_CODE (addr) == PLUS)
1816 rtx base = XEXP (addr, 0);
1817 rtx offset = XEXP (addr, 1);
1819 return (base_reg_operand (base, GET_MODE (base))
1820 && satisfies_constraint_I (offset));
1823 else if (GET_CODE (addr) == LO_SUM)
1825 rtx base = XEXP (addr, 0);
1826 rtx offset = XEXP (addr, 1);
1828 if (!base_reg_operand (base, GET_MODE (base)))
1831 else if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1832 return small_toc_ref (offset, GET_MODE (offset));
1834 else if (TARGET_ELF && !TARGET_POWERPC64)
1835 return CONSTANT_P (offset);