1 ;; Pipeline description for Freescale PowerPC e5500 core.
2 ;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
22 ;; Max issue 3 insns/clock cycle (includes 1 branch)
24 (define_automaton "e5500_most,e5500_long")
25 (define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most")
28 (define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most")
31 (define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most")
33 ;; Non-pipelined division.
34 (define_cpu_unit "e5500_cfx_div" "e5500_long")
37 (define_cpu_unit "e5500_lsu" "e5500_most")
40 (define_cpu_unit "e5500_fpu" "e5500_long")
43 (define_cpu_unit "e5500_bu" "e5500_most")
45 ;; The following units are used to make the automata deterministic.
46 (define_cpu_unit "present_e5500_decode_0" "e5500_most")
47 (define_cpu_unit "present_e5500_sfx_0" "e5500_most")
48 (presence_set "present_e5500_decode_0" "e5500_decode_0")
49 (presence_set "present_e5500_sfx_0" "e5500_sfx_0")
51 ;; Some useful abbreviations.
52 (define_reservation "e5500_decode"
53 "e5500_decode_0|e5500_decode_1+present_e5500_decode_0")
54 (define_reservation "e5500_sfx"
55 "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0")
58 (define_insn_reservation "e5500_sfx" 1
59 (and (eq_attr "type" "integer,insert,delayed_compare,\
61 (eq_attr "cpu" "ppce5500"))
62 "e5500_decode,e5500_sfx")
64 (define_insn_reservation "e5500_sfx2" 2
65 (and (eq_attr "type" "cmp,compare,fast_compare,trap")
66 (eq_attr "cpu" "ppce5500"))
67 "e5500_decode,e5500_sfx")
69 (define_insn_reservation "e5500_delayed" 2
70 (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
71 (eq_attr "cpu" "ppce5500"))
72 "e5500_decode,e5500_sfx*2")
74 (define_insn_reservation "e5500_two" 2
75 (and (eq_attr "type" "two")
76 (eq_attr "cpu" "ppce5500"))
77 "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx")
79 (define_insn_reservation "e5500_three" 3
80 (and (eq_attr "type" "three")
81 (eq_attr "cpu" "ppce5500"))
82 "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx")
85 (define_insn_reservation "e5500_mfcr" 4
86 (and (eq_attr "type" "mfcr")
87 (eq_attr "cpu" "ppce5500"))
88 "e5500_decode,e5500_sfx_0*4")
91 (define_insn_reservation "e5500_mtcrf" 1
92 (and (eq_attr "type" "mtcr")
93 (eq_attr "cpu" "ppce5500"))
94 "e5500_decode,e5500_sfx_0")
97 (define_insn_reservation "e5500_mtjmpr" 1
98 (and (eq_attr "type" "mtjmpr,mfjmpr")
99 (eq_attr "cpu" "ppce5500"))
100 "e5500_decode,e5500_sfx")
103 (define_insn_reservation "e5500_multiply" 4
104 (and (eq_attr "type" "mul")
106 (eq_attr "size" "32")
107 (eq_attr "cpu" "ppce5500"))
108 "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
110 (define_insn_reservation "e5500_multiply_i" 5
111 (and (eq_attr "type" "mul")
112 (ior (eq_attr "dot" "yes")
113 (eq_attr "size" "8,16"))
114 (eq_attr "cpu" "ppce5500"))
115 "e5500_decode,e5500_cfx_stage0,\
116 e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
119 (define_insn_reservation "e5500_divide" 16
120 (and (eq_attr "type" "div")
121 (eq_attr "size" "32")
122 (eq_attr "cpu" "ppce5500"))
123 "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
126 (define_insn_reservation "e5500_divide_d" 26
127 (and (eq_attr "type" "div")
128 (eq_attr "size" "64")
129 (eq_attr "cpu" "ppce5500"))
130 "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
134 (define_insn_reservation "e5500_load" 3
135 (and (eq_attr "type" "load,load_l,sync")
136 (eq_attr "cpu" "ppce5500"))
137 "e5500_decode,e5500_lsu")
139 (define_insn_reservation "e5500_fpload" 4
140 (and (eq_attr "type" "fpload")
141 (eq_attr "cpu" "ppce5500"))
142 "e5500_decode,e5500_lsu")
145 (define_insn_reservation "e5500_store" 3
146 (and (eq_attr "type" "store,store_c")
147 (eq_attr "cpu" "ppce5500"))
148 "e5500_decode,e5500_lsu")
150 (define_insn_reservation "e5500_fpstore" 3
151 (and (eq_attr "type" "fpstore")
152 (eq_attr "cpu" "ppce5500"))
153 "e5500_decode,e5500_lsu")
156 (define_insn_reservation "e5500_float" 7
157 (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
158 (eq_attr "cpu" "ppce5500"))
159 "e5500_decode,e5500_fpu")
161 (define_insn_reservation "e5500_sdiv" 20
162 (and (eq_attr "type" "sdiv")
163 (eq_attr "cpu" "ppce5500"))
164 "e5500_decode,e5500_fpu*20")
166 (define_insn_reservation "e5500_ddiv" 35
167 (and (eq_attr "type" "ddiv")
168 (eq_attr "cpu" "ppce5500"))
169 "e5500_decode,e5500_fpu*35")
172 (define_insn_reservation "e5500_branch" 1
173 (and (eq_attr "type" "jmpreg,branch,isync")
174 (eq_attr "cpu" "ppce5500"))
175 "e5500_decode,e5500_bu")
178 (define_insn_reservation "e5500_cr_logical" 1
179 (and (eq_attr "type" "cr_logical,delayed_cr")
180 (eq_attr "cpu" "ppce5500"))
181 "e5500_decode,e5500_bu")