| blob | b687867652fc8dc722909e8ffff034dafda3da66 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
96 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
106 #ifndef LOAD_EXTEND_OP
107 #define LOAD_EXTEND_OP(M) UNKNOWN
108 #endif
110 /* Number of attempts to combine instructions in this function. */
114 /* Number of attempts that got as far as substitution in this function. */
118 /* Number of instructions combined with added SETs in this function. */
122 /* Number of instructions combined in this function. */
126 /* Totals over entire compilation. */
130 /* combine_instructions may try to replace the right hand side of the
131 second instruction with the value of an associated REG_EQUAL note
132 before throwing it at try_combine. That is problematic when there
133 is a REG_DEAD note for a register used in the old right hand side
134 and can cause distribute_notes to do wrong things. This is the
135 second instruction if it has been so modified, null otherwise. */
139 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
143 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
146 \f
148 /* Record last point of death of (hard or pseudo) register n. */
151 /* Record last point of modification of (hard or pseudo) register n. */
154 /* The next group of fields allows the recording of the last value assigned
155 to (hard or pseudo) register n. We use this information to see if an
156 operation being processed is redundant given a prior operation performed
157 on the register. For example, an `and' with a constant is redundant if
158 all the zero bits are already known to be turned off.
160 We use an approach similar to that used by cse, but change it in the
161 following ways:
163 (1) We do not want to reinitialize at each label.
164 (2) It is useful, but not critical, to know the actual value assigned
165 to a register. Often just its form is helpful.
167 Therefore, we maintain the following fields:
169 last_set_value the last value assigned
170 last_set_label records the value of label_tick when the
171 register was assigned
172 last_set_table_tick records the value of label_tick when a
173 value using the register is assigned
174 last_set_invalid set to nonzero when it is not valid
175 to use the value of this register in some
176 register's value
178 To understand the usage of these tables, it is important to understand
179 the distinction between the value in last_set_value being valid and
180 the register being validly contained in some other expression in the
181 table.
183 (The next two parameters are out of date).
185 reg_stat[i].last_set_value is valid if it is nonzero, and either
186 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
188 Register I may validly appear in any expression returned for the value
189 of another register if reg_n_sets[i] is 1. It may also appear in the
190 value for register J if reg_stat[j].last_set_invalid is zero, or
191 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
193 If an expression is found in the table containing a register which may
194 not validly appear in an expression, the register is replaced by
195 something that won't match, (clobber (const_int 0)). */
197 /* Record last value assigned to (hard or pseudo) register n. */
199 rtx last_set_value;
201 /* Record the value of label_tick when an expression involving register n
202 is placed in last_set_value. */
206 /* Record the value of label_tick when the value for register n is placed in
207 last_set_value. */
211 /* These fields are maintained in parallel with last_set_value and are
212 used to store the mode in which the register was last set, the bits
213 that were known to be zero when it was last set, and the number of
214 sign bits copies it was known to have when it was last set. */
220 /* Set nonzero if references to register n in expressions should not be
221 used. last_set_invalid is set nonzero when this register is being
222 assigned to and last_set_table_tick == label_tick. */
226 /* Some registers that are set more than once and used in more than one
227 basic block are nevertheless always set in similar ways. For example,
228 a QImode register may be loaded from memory in two places on a machine
229 where byte loads zero extend.
231 We record in the following fields if a register has some leading bits
232 that are always equal to the sign bit, and what we know about the
233 nonzero bits of a register, specifically which bits are known to be
234 zero.
236 If an entry is zero, it means that we don't know anything special. */
242 /* Record the value of the label_tick when the last truncation
243 happened. The field truncated_to_mode is only valid if
244 truncation_label == label_tick. */
248 /* Record the last truncation seen for this register. If truncation
249 is not a nop to this mode we might be able to save an explicit
250 truncation if we know that value already contains a truncated
251 value. */
254 };
259 /* One plus the highest pseudo for which we track REG_N_SETS.
260 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
261 but during combine_split_insns new pseudos can be created. As we don't have
262 updated DF information in that case, it is hard to initialize the array
263 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
264 so instead of growing the arrays, just assume all newly created pseudos
265 during combine might be set multiple times. */
269 /* Record the luid of the last insn that invalidated memory
270 (anything that writes memory, and subroutine calls, but not pushes). */
274 /* Record the luid of the last CALL_INSN
275 so we can tell whether a potential combination crosses any calls. */
279 /* When `subst' is called, this is the insn that is being modified
280 (by combining in a previous insn). The PATTERN of this insn
281 is still the old pattern partially modified and it should not be
282 looked at, but this may be used to examine the successors of the insn
283 to judge whether a simplification is valid. */
287 /* This is the lowest LUID that `subst' is currently dealing with.
288 get_last_value will not return a value if the register was set at or
289 after this LUID. If not for this mechanism, we could get confused if
290 I2 or I1 in try_combine were an insn that used the old value of a register
291 to obtain a new value. In that case, we might erroneously get the
292 new value of the register when we wanted the old one. */
296 /* This contains any hard registers that are used in newpat; reg_dead_at_p
297 must consider all these registers to be always live. */
301 /* This is an insn to which a LOG_LINKS entry has been added. If this
302 insn is the earlier than I2 or I3, combine should rescan starting at
303 that location. */
307 /* Basic block in which we are performing combines. */
311 \f
312 /* Length of the currently allocated uid_insn_cost array. */
316 /* The following array records the insn_rtx_cost for every insn
317 in the instruction stream. */
321 /* The following array records the LOG_LINKS for every insn in the
322 instruction stream as struct insn_link pointers. */
328 };
332 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
333 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
335 #define FOR_EACH_LOG_LINK(L, INSN) \
336 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
338 /* Links for LOG_LINKS are allocated from this obstack. */
342 /* Allocate a link. */
346 {
354 }
356 /* Incremented for each basic block. */
360 /* Reset to label_tick for each extended basic block in scanning order. */
364 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
365 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
369 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
370 be safely used. It is zero while computing them and after combine has
371 completed. This former test prevents propagating values based on
372 previously set values, which can be incorrect if a variable is modified
373 in a loop. */
377 \f
378 /* Record one modification to rtl structure
379 to be undone by storing old_contents into *where. */
383 struct undo
384 {
389 };
391 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
392 num_undo says how many are currently recorded.
394 other_insn is nonzero if we have modified some other insn in the process
395 of working on subst_insn. It must be verified too. */
397 struct undobuf
398 {
402 };
406 /* Number of times the pseudo being substituted for
407 was found and replaced. */
412 machine_mode,
416 machine_mode,
488 \f
490 /* It is not safe to use ordinary gen_lowpart in combine.
491 See comments in gen_lowpart_for_combine. */
492 #undef RTL_HOOKS_GEN_LOWPART
493 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
495 /* Our implementation of gen_lowpart never emits a new pseudo. */
496 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
497 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
499 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
500 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
502 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
503 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
505 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
506 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
510 \f
511 /* Convenience wrapper for the canonicalize_comparison target hook.
512 Target hooks cannot use enum rtx_code. */
516 {
520 }
522 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
523 PATTERN can not be split. Otherwise, it returns an insn sequence.
524 This is a wrapper around split_insns which ensures that the
525 reg_stat vector is made larger if the splitter creates a new
526 register. */
530 {
539 }
541 /* This is used by find_single_use to locate an rtx in LOC that
542 contains exactly one use of DEST, which is typically either a REG
543 or CC0. It returns a pointer to the innermost rtx expression
544 containing DEST. Appearances of DEST that are being used to
545 totally replace it are not counted. */
549 {
558 {
562 CASE_CONST_ANY:
567 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
568 of a REG that occupies all of the REG, the insn uses DEST if
569 it is mentioned in the destination or the source. Otherwise, we
570 need just check the source. */
590 }
592 /* If it wasn't one of the common cases above, check each expression and
593 vector of this code. Look for a unique usage of DEST. */
597 {
599 {
604 else
610 /* Duplicate usage. */
612 }
614 {
618 {
624 else
631 }
632 }
633 }
636 }
639 /* See if DEST, produced in INSN, is used only a single time in the
640 sequel. If so, return a pointer to the innermost rtx expression in which
641 it is used.
643 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
645 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
646 care about REG_DEAD notes or LOG_LINKS.
648 Otherwise, we find the single use by finding an insn that has a
649 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
650 only referenced once in that insn, we know that it must be the first
651 and last insn referencing DEST. */
655 {
656 basic_block bb;
662 {
672 }
682 {
688 {
693 }
694 }
697 }
698 \f
699 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
700 insn. The substitution can be undone by undo_all. If INTO is already
701 set to NEWVAL, do not record this change. Because computing NEWVAL might
702 also call SUBST, we have to compute it before we put anything into
703 the undo table. */
705 static void
707 {
714 /* We'd like to catch as many invalid transformations here as
715 possible. Unfortunately, there are way too many mode changes
716 that are perfectly valid, so we'd waste too much effort for
717 little gain doing the checks here. Focus on catching invalid
718 transformations involving integer constants. */
721 {
722 /* Sanity check that we're replacing oldval with a CONST_INT
723 that is a valid sign-extension for the original mode. */
727 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
728 CONST_INT is not valid, because after the replacement, the
729 original mode would be gone. Unfortunately, we can't tell
730 when do_SUBST is called to replace the operand thereof, so we
731 perform this test on oldval instead, checking whether an
732 invalid replacement took place before we got here. */
737 }
741 else
750 }
752 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
754 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
755 for the value of a HOST_WIDE_INT value (including CONST_INT) is
756 not safe. */
758 static void
760 {
769 else
778 }
780 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
782 /* Similar to SUBST, but just substitute the mode. This is used when
783 changing the mode of a pseudo-register, so that any other
784 references to the entry in the regno_reg_rtx array will change as
785 well. */
787 static void
789 {
798 else
807 }
809 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
811 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
813 static void
815 {
824 else
833 }
835 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
836 \f
837 /* Subroutine of try_combine. Determine whether the replacement patterns
838 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
839 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
840 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
841 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
842 of all the instructions can be estimated and the replacements are more
843 expensive than the original sequence. */
845 static bool
848 {
853 /* Lookup the original insn_rtx_costs. */
858 {
861 {
865 }
866 else
867 {
871 }
872 }
873 else
874 {
877 }
879 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
880 correct that. */
885 /* Calculate the replacement insn_rtx_costs. */
888 {
892 }
893 else
894 {
897 }
900 {
906 {
909 }
910 else
912 }
914 /* Disallow this combination if both new_cost and old_cost are greater than
915 zero, and new_cost is greater than old cost. */
919 {
938 else
940 }
945 /* Update the uid_insn_cost array with the replacement costs. */
949 {
953 }
956 }
959 /* Delete any insns that copy a register to itself. */
961 static void
963 {
965 basic_block bb;
968 {
970 {
973 {
978 }
979 }
980 }
981 }
983 \f
984 /* Return false if we do not want to (or cannot) combine DEF. */
985 static bool
987 {
988 /* Do not consider if it is pre/post modification in MEM. */
994 /* Do not combine frame pointer adjustments. */
997 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1005 }
1007 /* Return false if we do not want to (or cannot) combine USE. */
1008 static bool
1010 {
1011 /* Do not consider the usage of the stack pointer by function call. */
1016 }
1018 /* Fill in log links field for all insns. */
1020 static void
1022 {
1023 basic_block bb;
1030 /* Pass through each block from the end, recording the uses of each
1031 register and establishing log links when def is encountered.
1032 Note that we do not clear next_use array in order to save time,
1033 so we have to test whether the use is in the same basic block as def.
1035 There are a few cases below when we do not consider the definition or
1036 usage -- these are taken from original flow.c did. Don't ask me why it is
1037 done this way; I don't know and if it works, I don't want to know. */
1040 {
1042 {
1046 /* Log links are created only once. */
1050 {
1066 /* flow.c claimed:
1068 We don't build a LOG_LINK for hard registers contained
1069 in ASM_OPERANDs. If these registers get replaced,
1070 we might wind up changing the semantics of the insn,
1071 even if reload can make what appear to be valid
1072 assignments later. */
1077 /* Don't add duplicate links between instructions. */
1086 }
1091 }
1092 }
1095 }
1097 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1098 true if we found a LOG_LINK that proves that A feeds B. This only works
1099 if there are no instructions between A and B which could have a link
1100 depending on A, since in that case we would not record a link for B.
1101 We also check the implicit dependency created by a cc0 setter/user
1102 pair. */
1104 static bool
1106 {
1114 }
1115 \f
1116 /* Main entry point for combiner. F is the first insn of the function.
1117 NREGS is the first unused pseudo-reg number.
1119 Return nonzero if the combiner has turned an indirect jump
1120 instruction into a direct jump. */
1121 static int
1123 {
1128 basic_block last_bb;
1148 /* Allocate array for insn info. */
1156 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1157 problems when, for example, we have j <<= 1 in a loop. */
1162 /* Scan all SETs and see if we can deduce anything about what
1163 bits are known to be zero for some registers and how many copies
1164 of the sign bit are known to exist for those registers.
1166 Also set any known values so that we can use it while searching
1167 for what bits are known to be set. */
1170 /* Allow the entry block and the first block to fall into the same EBB.
1171 Conceptually the incoming promotions are assigned to the entry block. */
1176 {
1181 label_tick++;
1189 {
1190 rtx links;
1196 insn);
1203 insn);
1205 /* Record the current insn_rtx_cost of this instruction. */
1208 optimize_this_for_speed_p);
1212 }
1213 }
1217 /* Now scan all the insns in forward order. */
1225 {
1231 label_tick++;
1241 {
1255 /* See if we know about function return values before this
1256 insn based upon SUBREG flags. */
1259 /* See if we can find hardregs and subreg of pseudos in
1260 narrower modes. This could help turning TRUNCATEs
1261 into SUBREGs. */
1264 /* Try this insn with each insn it links back to. */
1270 {
1273 }
1275 /* Try each sequence of three linked insns ending with this one. */
1279 {
1282 /* If the linked insn has been replaced by a note, then there
1283 is no point in pursuing this chain any further. */
1291 {
1294 }
1295 }
1297 /* Try to combine a jump insn that uses CC0
1298 with a preceding insn that sets CC0, and maybe with its
1299 logical predecessor as well.
1300 This is how we make decrement-and-branch insns.
1301 We need this special code because data flow connections
1302 via CC0 do not get entered in LOG_LINKS. */
1309 {
1320 }
1322 /* Do the same for an insn that explicitly references CC0. */
1329 {
1340 }
1342 /* Finally, see if any of the insns that this insn links to
1343 explicitly references CC0. If so, try this insn, that insn,
1344 and its predecessor if it sets CC0. */
1346 {
1358 }
1360 /* Try combining an insn with two different insns whose results it
1361 uses. */
1371 {
1374 }
1376 /* Try four-instruction combinations. */
1379 {
1383 /* If the linked insn has been replaced by a note, then there
1384 is no point in pursuing this chain any further. */
1389 {
1393 /* I0 -> I1 -> I2 -> I3. */
1399 {
1402 }
1403 /* I0, I1 -> I2, I2 -> I3. */
1410 {
1413 }
1414 }
1417 {
1421 /* I0 -> I2; I1, I2 -> I3. */
1427 {
1430 }
1431 /* I0 -> I1; I1, I2 -> I3. */
1437 {
1440 }
1441 }
1442 }
1444 /* Try this insn with each REG_EQUAL note it links back to. */
1446 {
1452 /* Avoid using a register that may already been marked
1453 dead by an earlier instruction. */
1461 {
1462 /* Temporarily replace the set's source with the
1463 contents of the REG_EQUAL note. The insn will
1464 be deleted or recognized by try_combine. */
1475 last_combined_insn);
1478 {
1481 }
1484 }
1485 }
1490 retry:
1491 ;
1492 }
1493 }
1500 /* Clean up. */
1506 {
1509 {
1512 }
1514 }
1524 /* Make recognizer allow volatile MEMs again. */
1528 }
1530 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1532 static void
1534 {
1540 }
1541 \f
1542 /* Set up any promoted values for incoming argument registers. */
1544 static void
1546 {
1547 tree arg;
1552 {
1557 /* Only continue if the incoming argument is in a register. */
1561 /* Determine, if possible, whether all call sites of the current
1562 function lie within the current compilation unit. (This does
1563 take into account the exporting of a function via taking its
1564 address, and so forth.) */
1567 /* The mode and signedness of the argument before any promotions happen
1568 (equal to the mode of the pseudo holding it at that stage). */
1572 /* The mode and signedness of the argument after any source language and
1573 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1577 /* The mode and signedness of the argument as it is actually passed,
1578 see assign_parm_setup_reg in function.c. */
1582 /* The mode of the register in which the argument is being passed. */
1585 /* Eliminate sign extensions in the callee when:
1586 (a) A mode promotion has occurred; */
1589 /* (b) The mode of the register is the same as the mode of
1590 the argument as it is passed; */
1593 /* (c) There's no language level extension; */
1595 ;
1596 /* (c.1) All callers are from the current compilation unit. If that's
1597 the case we don't have to rely on an ABI, we only have to know
1598 what we're generating right now, and we know that we will do the
1599 mode1 to mode2 promotion with the given sign. */
1602 /* (c.2) The combination of the two promotions is useful. This is
1603 true when the signs match, or if the first promotion is unsigned.
1604 In the later case, (sign_extend (zero_extend x)) is the same as
1605 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1611 /* Record that the value was promoted from mode1 to mode3,
1612 so that any sign extension at the head of the current
1613 function may be eliminated. */
1617 }
1618 }
1620 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1621 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1622 because some machines (maybe most) will actually do the sign-extension and
1623 this is the conservative approach.
1625 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1626 kludge. */
1628 static rtx
1630 {
1638 }
1640 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1641 and SET. */
1643 static void
1645 rtx x)
1646 {
1656 {
1660 }
1662 /* Don't call nonzero_bits if it cannot change anything. */
1664 {
1669 }
1671 /* Don't call num_sign_bit_copies if it cannot change anything. */
1673 {
1676 {
1680 }
1683 }
1684 }
1686 /* Called via note_stores. If X is a pseudo that is narrower than
1687 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1689 If we are setting only a portion of X and we can't figure out what
1690 portion, assume all bits will be used since we don't know what will
1691 be happening.
1693 Similarly, set how many bits of X are known to be copies of the sign bit
1694 at all locations in the function. This is the smallest number implied
1695 by any set of X. */
1697 static void
1699 {
1704 /* If this register is undefined at the start of the file, we can't
1705 say what its contents were. */
1706 && ! REGNO_REG_SET_P
1709 {
1713 {
1717 }
1719 /* If this register is being initialized using itself, and the
1720 register is uninitialized in this basic block, and there are
1721 no LOG_LINKS which set the register, then part of the
1722 register is uninitialized. In that case we can't assume
1723 anything about the number of nonzero bits.
1725 ??? We could do better if we checked this in
1726 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1727 could avoid making assumptions about the insn which initially
1728 sets the register, while still using the information in other
1729 insns. We would have to be careful to check every insn
1730 involved in the combination. */
1736 {
1743 {
1747 }
1748 }
1750 /* If this is a complex assignment, see if we can convert it into a
1751 simple assignment. */
1754 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1755 set what we know about X. */
1761 else
1762 {
1765 }
1766 }
1767 }
1768 \f
1769 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1770 optionally insns that were previously combined into I3 or that will be
1771 combined into the merger of INSN and I3. The order is PRED, PRED2,
1772 INSN, SUCC, SUCC2, I3.
1774 Return 0 if the combination is not allowed for any reason.
1776 If the combination is allowed, *PDEST will be set to the single
1777 destination of INSN and *PSRC to the single source, and this function
1778 will return 1. */
1780 static int
1784 {
1789 rtx link;
1794 {
1796 {
1801 }
1806 }
1810 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1811 or a PARALLEL consisting of such a SET and CLOBBERs.
1813 If INSN has CLOBBER parallel parts, ignore them for our processing.
1814 By definition, these happen during the execution of the insn. When it
1815 is merged with another insn, all bets are off. If they are, in fact,
1816 needed and aren't also supplied in I3, they may be added by
1817 recog_for_combine. Otherwise, it won't match.
1819 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1820 note.
1822 Get the source and destination of INSN. If more than one, can't
1823 combine. */
1829 {
1831 {
1835 {
1836 /* This is important to combine floating point insns
1837 for the SH4 port. */
1839 /* Combining an isolated USE doesn't make sense.
1840 We depend here on combinable_i3pat to reject them. */
1841 /* The code below this loop only verifies that the inputs of
1842 the SET in INSN do not change. We call reg_set_between_p
1843 to verify that the REG in the USE does not change between
1844 I3 and INSN.
1845 If the USE in INSN was for a pseudo register, the matching
1846 insn pattern will likely match any register; combining this
1847 with any other USE would only be safe if we knew that the
1848 used registers have identical values, or if there was
1849 something to tell them apart, e.g. different modes. For
1850 now, we forgo such complicated tests and simply disallow
1851 combining of USES of pseudo registers with any other USE. */
1854 {
1859 do
1860 {
1870 }
1872 }
1875 /* We can ignore CLOBBERs. */
1880 /* Ignore SETs whose result isn't used but not those that
1881 have side-effects. */
1887 /* If we have already found a SET, this is a second one and
1888 so we cannot combine with this insn. */
1896 /* Anything else means we can't combine. */
1898 }
1899 }
1902 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1903 so don't do anything with it. */
1906 }
1907 else
1913 /* The simplification in expand_field_assignment may call back to
1914 get_last_value, so set safe guard here. */
1920 /* Do not eliminate user-specified register if it is in an
1921 asm input because we may break the register asm usage defined
1922 in GCC manual if allow to do so.
1923 Be aware that this may cover more cases than we expect but this
1924 should be harmless. */
1929 /* Don't eliminate a store in the stack pointer. */
1931 /* Don't combine with an insn that sets a register to itself if it has
1932 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1934 /* Can't merge an ASM_OPERANDS. */
1936 /* Can't merge a function call. */
1938 /* Don't eliminate a function call argument. */
1944 /* Don't substitute into an incremented register. */
1948 /* Don't substitute into a non-local goto, this confuses CFG. */
1950 /* Make sure that DEST is not used after SUCC but before I3. */
1951 || (!all_adjacent
1952 && ((succ2
1956 /* Make sure that the value that is to be substituted for the register
1957 does not use any registers whose values alter in between. However,
1958 If the insns are adjacent, a use can't cross a set even though we
1959 think it might (this can happen for a sequence of insns each setting
1960 the same destination; last_set of that register might point to
1961 a NOTE). If INSN has a REG_EQUIV note, the register is always
1962 equivalent to the memory so the substitution is valid even if there
1963 are intervening stores. Also, don't move a volatile asm or
1964 UNSPEC_VOLATILE across any other insns. */
1965 || (! all_adjacent
1971 /* Don't combine across a CALL_INSN, because that would possibly
1972 change whether the life span of some REGs crosses calls or not,
1973 and it is a pain to update that information.
1974 Exception: if source is a constant, moving it later can't hurt.
1975 Accept that as a special case. */
1979 /* DEST must either be a REG or CC0. */
1981 {
1982 /* If register alignment is being enforced for multi-word items in all
1983 cases except for parameters, it is possible to have a register copy
1984 insn referencing a hard register that is not allowed to contain the
1985 mode being copied and which would not be valid as an operand of most
1986 insns. Eliminate this problem by not combining with such an insn.
1988 Also, on some machines we don't want to extend the life of a hard
1989 register. */
1994 /* Don't extend the life of a hard register unless it is
1995 user variable (if we have few registers) or it can't
1996 fit into the desired register (meaning something special
1997 is going on).
1998 Also avoid substituting a return register into I3, because
1999 reload can't handle a conflict with constraints of other
2000 inputs. */
2004 }
2012 {
2015 /* If the clobber represents an earlyclobber operand, we must not
2016 substitute an expression containing the clobbered register.
2017 As we do not analyze the constraint strings here, we have to
2018 make the conservative assumption. However, if the register is
2019 a fixed hard reg, the clobber cannot represent any operand;
2020 we leave it up to the machine description to either accept or
2021 reject use-and-clobber patterns. */
2027 }
2029 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2030 or not), reject, unless nothing volatile comes between it and I3 */
2033 {
2034 /* Make sure neither succ nor succ2 contains a volatile reference. */
2039 /* We'll check insns between INSN and I3 below. */
2040 }
2042 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2043 to be an explicit register variable, and was chosen for a reason. */
2049 /* If INSN contains volatile references (specifically volatile MEMs),
2050 we cannot combine across any other volatile references.
2051 Even if INSN doesn't contain volatile references, any intervening
2052 volatile insn might affect machine state. */
2055 ? volatile_refs_p
2062 /* If INSN contains an autoincrement or autodecrement, make sure that
2063 register is not used between there and I3, and not already used in
2064 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2065 Also insist that I3 not be a jump; if it were one
2066 and the incremented register were spilled, we would lose. */
2084 /* Don't combine an insn that follows a CC0-setting insn.
2085 An insn that uses CC0 must not be separated from the one that sets it.
2086 We do, however, allow I2 to follow a CC0-setting insn if that insn
2087 is passed as I1; in that case it will be deleted also.
2088 We also allow combining in this case if all the insns are adjacent
2089 because that would leave the two CC0 insns adjacent as well.
2090 It would be more logical to test whether CC0 occurs inside I1 or I2,
2091 but that would be much slower, and this ought to be equivalent. */
2094 {
2099 }
2101 /* If we get here, we have passed all the tests and the combination is
2102 to be allowed. */
2108 }
2109 \f
2110 /* LOC is the location within I3 that contains its pattern or the component
2111 of a PARALLEL of the pattern. We validate that it is valid for combining.
2113 One problem is if I3 modifies its output, as opposed to replacing it
2114 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2115 doing so would produce an insn that is not equivalent to the original insns.
2117 Consider:
2119 (set (reg:DI 101) (reg:DI 100))
2120 (set (subreg:SI (reg:DI 101) 0) <foo>)
2122 This is NOT equivalent to:
2124 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2125 (set (reg:DI 101) (reg:DI 100))])
2127 Not only does this modify 100 (in which case it might still be valid
2128 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2130 We can also run into a problem if I2 sets a register that I1
2131 uses and I1 gets directly substituted into I3 (not via I2). In that
2132 case, we would be getting the wrong value of I2DEST into I3, so we
2133 must reject the combination. This case occurs when I2 and I1 both
2134 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2135 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2136 of a SET must prevent combination from occurring. The same situation
2137 can occur for I0, in which case I0_NOT_IN_SRC is set.
2139 Before doing the above check, we first try to expand a field assignment
2140 into a set of logical operations.
2142 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2143 we place a register that is both set and used within I3. If more than one
2144 such register is detected, we fail.
2146 Return 1 if the combination is valid, zero otherwise. */
2148 static int
2151 {
2155 {
2160 rtx subdest;
2167 /* Check for the case where I3 modifies its output, as discussed
2168 above. We don't want to prevent pseudos from being combined
2169 into the address of a MEM, so only prevent the combination if
2170 i1 or i2 set the same MEM. */
2180 /* This is the same test done in can_combine_p except we can't test
2181 all_adjacent; we don't have to, since this instruction will stay
2182 in place, thus we are not considering increasing the lifetime of
2183 INNER_DEST.
2185 Also, if this insn sets a function argument, combining it with
2186 something that might need a spill could clobber a previous
2187 function argument; the all_adjacent test in can_combine_p also
2188 checks this; here, we do a more specific test for this case. */
2198 /* If DEST is used in I3, it is being killed in this insn, so
2199 record that for later. We have to consider paradoxical
2200 subregs here, since they kill the whole register, but we
2201 ignore partial subregs, STRICT_LOW_PART, etc.
2202 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2203 STACK_POINTER_REGNUM, since these are always considered to be
2204 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2214 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2220 {
2225 }
2226 }
2229 {
2236 }
2239 }
2240 \f
2241 /* Return 1 if X is an arithmetic expression that contains a multiplication
2242 and division. We don't count multiplications by powers of two here. */
2244 static int
2246 {
2248 {
2264 }
2265 }
2266 \f
2267 /* Determine whether INSN can be used in a combination. Return nonzero if
2268 not. This is used in try_combine to detect early some cases where we
2269 can't perform combinations. */
2271 static int
2273 {
2274 rtx set;
2277 /* If this isn't really an insn, we can't do anything.
2278 This can occur when flow deletes an insn that it has merged into an
2279 auto-increment address. */
2283 /* Never combine loads and stores involving hard regs that are likely
2284 to be spilled. The register allocator can usually handle such
2285 reg-reg moves by tying. If we allow the combiner to make
2286 substitutions of likely-spilled regs, reload might die.
2287 As an exception, we allow combinations involving fixed regs; these are
2288 not available to the register allocator so there's no risk involved. */
2309 }
2311 struct likely_spilled_retval_info
2312 {
2315 };
2317 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2318 hard registers that are known to be written to / clobbered in full. */
2319 static void
2321 {
2338 else
2341 }
2343 /* Return nonzero iff part of the return value is live during INSN, and
2344 it is likely spilled. This can happen when more than one insn is needed
2345 to copy the return value, e.g. when we consider to combine into the
2346 second copy insn for a complex value. */
2348 static int
2350 {
2352 rtx reg;
2355 /* We assume here that no machine mode needs more than
2356 32 hard registers when the value overlaps with a register
2357 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2372 /* Disregard parts of the return value that are set later. */
2381 /* Check if any of the (probably) live return value registers is
2382 likely spilled. */
2383 nregs --;
2384 do
2385 {
2391 }
2393 /* Adjust INSN after we made a change to its destination.
2395 Changing the destination can invalidate notes that say something about
2396 the results of the insn and a LOG_LINK pointing to the insn. */
2398 static void
2400 {
2401 /* For notes, be conservative and simply remove them. */
2404 /* The new insn will have a destination that was previously the destination
2405 of an insn just above it. Call distribute_links to make a LOG_LINK from
2406 the next use of that destination. */
2422 }
2424 /* Return TRUE if combine can reuse reg X in mode MODE.
2425 ADDED_SETS is nonzero if the original set is still required. */
2426 static bool
2428 {
2435 /* Allow hard registers if the new mode is legal, and occupies no more
2436 registers than the old mode. */
2441 /* Or a pseudo that is only used once. */
2444 && !added_sets
2446 }
2449 /* Check whether X, the destination of a set, refers to part of
2450 the register specified by REG. */
2452 static bool
2454 {
2455 /* Check that reg is an integer mode register. */
2466 }
2468 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2469 Note that the INSN should be deleted *after* removing dead edges, so
2470 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2471 but not for a (set (pc) (label_ref FOO)). */
2473 static void
2475 {
2483 {
2488 /* Remove barriers from the footer if there are any. */
2491 {
2494 else
2498 }
2501 }
2502 }
2504 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2505 by an arbitrary number of CLOBBERs. */
2506 static bool
2508 {
2527 }
2529 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2530 CLOBBERs), can be split into individual SETs in that order, without
2531 changing semantics. */
2532 static bool
2534 {
2542 {
2551 }
2554 }
2556 /* Try to combine the insns I0, I1 and I2 into I3.
2557 Here I0, I1 and I2 appear earlier than I3.
2558 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2559 I3.
2561 If we are combining more than two insns and the resulting insn is not
2562 recognized, try splitting it into two insns. If that happens, I2 and I3
2563 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2564 Otherwise, I0, I1 and I2 are pseudo-deleted.
2566 Return 0 if the combination does not work. Then nothing is changed.
2567 If we did the combination, return the insn at which combine should
2568 resume scanning.
2570 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2571 new direct jump instruction.
2573 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2574 been I3 passed to an earlier try_combine within the same basic
2575 block. */
2580 {
2581 /* New patterns for I3 and I2, respectively. */
2585 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2586 dead. */
2588 /* Total number of SETs to put into I3. */
2590 /* Nonzero if I2's or I1's body now appears in I3. */
2592 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2594 /* Contains I3 if the destination of I3 is used in its source, which means
2595 that the old life of I3 is being killed. If that usage is placed into
2596 I2 and not in I3, a REG_DEAD note must be made. */
2598 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2600 /* Copy of SET_SRC of I1 and I0, if needed. */
2602 /* Set if I2DEST was reused as a scratch register. */
2604 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2606 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2611 /* Notes that must be added to REG_NOTES in I3 and I2. */
2613 /* Notes that we substituted I3 into I2 instead of the normal case. */
2615 /* Notes that I1, I2 or I3 is a MULT operation. */
2622 rtx temp_expr;
2625 rtx new_other_notes;
2628 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2629 never be). */
2633 /* Only try four-insn combinations when there's high likelihood of
2634 success. Look for simple insns, such as loads of constants or
2635 binary operations involving a constant. */
2637 {
2647 {
2650 rtx src;
2655 {
2658 }
2660 ngood++;
2663 nshift++;
2664 }
2666 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2667 are likely manipulating its value. Ideally we'll be able to combine
2668 all four insns into a bitfield insertion of some kind.
2670 Note the source in I0 might be inside a sign/zero extension and the
2671 memory modes in I0 and I3 might be different. So extract the address
2672 from the destination of I3 and search for it in the source of I0.
2674 In the event that there's a match but the source/dest do not actually
2675 refer to the same memory, the worst that happens is we try some
2676 combinations that we wouldn't have otherwise. */
2678 /* Ensure the source of SET0 is a MEM, possibly buried inside
2679 an extension. */
2685 /* Ensure the destination of SET3 is a MEM. */
2687 /* Would it be better to extract the base address for the MEM
2688 in SET3 and look for that? I don't have cases where it matters
2689 but I could envision such cases. */
2695 }
2697 /* Exit early if one of the insns involved can't be used for
2698 combinations. */
2709 combine_attempts++;
2712 /* Reset the hard register usage information. */
2716 {
2723 else
2726 }
2728 /* If multiple insns feed into one of I2 or I3, they can be in any
2729 order. To simplify the code below, reorder them in sequence. */
2739 /* First check for one important special case that the code below will
2740 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2741 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2742 we may be able to replace that destination with the destination of I3.
2743 This occurs in the common code where we compute both a quotient and
2744 remainder into a structure, in which case we want to do the computation
2745 directly into the structure to avoid register-register copies.
2747 Note that this case handles both multiple sets in I2 and also cases
2748 where I2 has a number of CLOBBERs inside the PARALLEL.
2750 We make very conservative checks below and only try to handle the
2751 most common cases of this. For example, we only handle the case
2752 where I2 and I3 are adjacent to avoid making difficult register
2753 usage tests. */
2761 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2762 below would need to check what is inside (and reg_overlap_mentioned_p
2763 doesn't support those codes anyway). Don't allow those destinations;
2764 the resulting insn isn't likely to be recognized anyway. */
2770 {
2773 /* Make sure that the destination of I3,
2774 which we are going to substitute into one output of I2,
2775 is not used within another output of I2. We must avoid making this:
2776 (parallel [(set (mem (reg 69)) ...)
2777 (set (reg 69) ...)])
2778 which is not well-defined as to order of actions.
2779 (Besides, reload can't handle output reloads for this.)
2781 The problem can also happen if the dest of I3 is a memory ref,
2782 if another dest in I2 is an indirect memory ref. */
2790 /* Make sure this PARALLEL is not an asm. We do not allow combining
2791 that usually (see can_combine_p), so do not here either. */
2801 {
2802 combine_merges++;
2812 /* Replace the dest in I2 with our dest and make the resulting
2813 insn the new pattern for I3. Then skip to where we validate
2814 the pattern. Everything was set up above. */
2819 }
2820 }
2822 /* If I2 is setting a pseudo to a constant and I3 is setting some
2823 sub-part of it to another constant, merge them by making a new
2824 constant. */
2831 {
2837 {
2840 {
2846 }
2847 }
2848 else
2849 {
2854 }
2857 {
2858 /* If this is the low part, we're done. */
2860 ;
2861 /* Handle the case where inner is twice the size of outer. */
2865 /* Otherwise give up for now. */
2866 else
2868 }
2871 {
2875 wide_int o
2880 combine_merges++;
2887 /* Replace the source in I2 with the new constant and make the
2888 resulting insn the new pattern for I3. Then skip to where we
2889 validate the pattern. Everything was set up above. */
2895 /* The dest of I3 has been replaced with the dest of I2. */
2898 }
2899 }
2901 /* If we have no I1 and I2 looks like:
2902 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2903 (set Y OP)])
2904 make up a dummy I1 that is
2905 (set Y OP)
2906 and change I2 to be
2907 (set (reg:CC X) (compare:CC Y (const_int 0)))
2909 (We can ignore any trailing CLOBBERs.)
2911 This undoes a previous combination and allows us to match a branch-and-
2912 decrement insn. */
2924 {
2925 /* We make I1 with the same INSN_UID as I2. This gives it
2926 the same DF_INSN_LUID for value tracking. Our fake I1 will
2927 never appear in the insn stream so giving it the same INSN_UID
2928 as I2 will not cause a problem. */
2941 }
2943 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2944 make those two SETs separate I1 and I2 insns, and make an I0 that is
2945 the original I1. */
2951 {
2952 /* If there is no I1, there is no I0 either. */
2955 /* We make I1 with the same INSN_UID as I2. This gives it
2956 the same DF_INSN_LUID for value tracking. Our fake I1 will
2957 never appear in the insn stream so giving it the same INSN_UID
2958 as I2 will not cause a problem. */
2966 }
2968 /* Verify that I2 and I1 are valid for combining. */
2974 {
2977 }
2979 /* Record whether I2DEST is used in I2SRC and similarly for the other
2980 cases. Knowing this will help in register status updating below. */
2991 /* For the earlier insns, determine which of the subsequent ones they
2992 feed. */
2999 /* Ensure that I3's pattern can be the destination of combines. */
3005 {
3008 }
3010 /* See if any of the insns is a MULT operation. Unless one is, we will
3011 reject a combination that is, since it must be slower. Be conservative
3012 here. */
3020 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3021 We used to do this EXCEPT in one case: I3 has a post-inc in an
3022 output operand. However, that exception can give rise to insns like
3023 mov r3,(r3)+
3024 which is a famous insn on the PDP-11 where the value of r3 used as the
3025 source was model-dependent. Avoid this sort of thing. */
3027 #if 0
3033 /* It's not the exception. */
3034 #endif
3036 {
3037 rtx link;
3043 {
3046 }
3047 }
3049 /* See if the SETs in I1 or I2 need to be kept around in the merged
3050 instruction: whenever the value set there is still needed past I3.
3051 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3053 For the SET in I1, we have two cases: if I1 and I2 independently feed
3054 into I3, the set in I1 needs to be kept around unless I1DEST dies
3055 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3056 in I1 needs to be kept around unless I1DEST dies or is set in either
3057 I2 or I3. The same considerations apply to I0. */
3064 else
3072 else
3075 /* We are about to copy insns for the case where they need to be kept
3076 around. Check that they can be copied in the merged instruction. */
3082 {
3085 }
3087 /* If the set in I2 needs to be kept around, we must make a copy of
3088 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3089 PATTERN (I2), we are only substituting for the original I1DEST, not into
3090 an already-substituted copy. This also prevents making self-referential
3091 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3092 I2DEST. */
3095 {
3098 else
3100 }
3103 {
3106 else
3108 }
3111 {
3114 else
3116 }
3118 combine_merges++;
3120 /* Substitute in the latest insn for the regs set by the earlier ones. */
3126 /* Many machines that don't use CC0 have insns that can both perform an
3127 arithmetic operation and set the condition code. These operations will
3128 be represented as a PARALLEL with the first element of the vector
3129 being a COMPARE of an arithmetic operation with the constant zero.
3130 The second element of the vector will set some pseudo to the result
3131 of the same arithmetic operation. If we simplify the COMPARE, we won't
3132 match such a pattern and so will generate an extra insn. Here we test
3133 for this case, where both the comparison and the operation result are
3134 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3135 I2SRC. Later we will make the PARALLEL that contains I2. */
3141 {
3142 rtx newpat_dest;
3156 {
3161 }
3163 /* Do the rest only if op1 is const0_rtx, which may be the
3164 result of simplification. */
3166 {
3167 /* If a single use of the CC is found, prepare to modify it
3168 when SELECT_CC_MODE returns a new CC-class mode, or when
3169 the above simplify_compare_const() returned a new comparison
3170 operator. undobuf.other_insn is assigned the CC use insn
3171 when modifying it. */
3173 {
3174 #ifdef SELECT_CC_MODE
3175 machine_mode new_mode
3180 {
3185 else
3186 {
3189 }
3190 }
3191 #endif
3192 /* Cases for modifying the CC-using comparison. */
3194 /* ??? Do we need to verify the zero rtx? */
3196 {
3197 /* Replace cc_use_loc with entire new RTX. */
3202 }
3204 {
3205 /* Just replace the CC reg with a new mode. */
3208 }
3209 }
3211 /* Now we modify the current newpat:
3212 First, SET_DEST(newpat) is updated if the CC mode has been
3213 altered. For targets without SELECT_CC_MODE, this should be
3214 optimized away. */
3217 /* This is always done to propagate i2src into newpat. */
3220 /* Create new version of i2pat if needed; the below PARALLEL
3221 creation needs this to work correctly. */
3225 }
3226 }
3229 {
3230 /* It is possible that the source of I2 or I1 may be performing
3231 an unneeded operation, such as a ZERO_EXTEND of something
3232 that is known to have the high part zero. Handle that case
3233 by letting subst look at the inner insns.
3235 Another way to do this would be to have a function that tries
3236 to simplify a single insn instead of merging two or more
3237 insns. We don't do this because of the potential of infinite
3238 loops and because of the potential extra memory required.
3239 However, doing it the way we are is a bit of a kludge and
3240 doesn't catch all cases.
3242 But only do this if -fexpensive-optimizations since it slows
3243 things down and doesn't usually win.
3245 This is not done in the COMPARE case above because the
3246 unmodified I2PAT is used in the PARALLEL and so a pattern
3247 with a modified I2SRC would not match. */
3250 {
3251 /* Pass pc_rtx so no substitutions are done, just
3252 simplifications. */
3254 {
3257 }
3261 }
3266 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3267 copy of I2SRC each time we substitute it, in order to avoid creating
3268 self-referential RTL when we will be substituting I1SRC for I1DEST
3269 later. Likewise if I0 feeds into I2, either directly or indirectly
3270 through I1, and I0DEST is in I0SRC. */
3277 /* Record whether I2's body now appears within I3's body. */
3279 }
3281 /* If we already got a failure, don't try to do more. Otherwise, try to
3282 substitute I1 if we have it. */
3285 {
3286 /* Check that an autoincrement side-effect on I1 has not been lost.
3287 This happens if I1DEST is mentioned in I2 and dies there, and
3288 has disappeared from the new pattern. */
3290 && i1_feeds_i2_n
3293 /* Before we can do this substitution, we must redo the test done
3294 above (see detailed comments there) that ensures I1DEST isn't
3295 mentioned in any SETs in NEWPAT that are field assignments. */
3298 {
3301 }
3306 /* If the following substitution will modify I1SRC, make a copy of it
3307 for the case where it is substituted for I1DEST in I2PAT later. */
3311 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3312 copy of I1SRC each time we substitute it, in order to avoid creating
3313 self-referential RTL when we will be substituting I0SRC for I0DEST
3314 later. */
3319 /* Record whether I1's body now appears within I3's body. */
3321 }
3323 /* Likewise for I0 if we have it. */
3326 {
3333 {
3336 }
3338 /* If the following substitution will modify I0SRC, make a copy of it
3339 for the case where it is substituted for I0DEST in I1PAT later. */
3342 /* And a copy for I0DEST in I2PAT substitution. */
3351 }
3353 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3354 to count all the ways that I2SRC and I1SRC can be used. */
3365 /* Fail if we tried to make a new register. */
3367 /* Fail if we couldn't do something and have a CLOBBER. */
3369 /* Fail if this new pattern is a MULT and we didn't have one before
3370 at the outer level. */
3373 {
3376 }
3378 /* If the actions of the earlier insns must be kept
3379 in addition to substituting them into the latest one,
3380 we must make a new PARALLEL for the latest insn
3381 to hold additional the SETs. */
3384 {
3386 combine_extras++;
3389 {
3395 }
3396 else
3397 {
3402 }
3408 {
3414 }
3416 {
3425 }
3426 }
3428 validate_replacement:
3430 /* Note which hard regs this insn has as inputs. */
3433 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3434 consider splitting this pattern, we might need these clobbers. */
3437 {
3443 }
3445 /* We have recognized nothing yet. */
3448 /* See if this is a PARALLEL of two SETs where one SET's destination is
3449 a register that is unused and this isn't marked as an instruction that
3450 might trap in an EH region. In that case, we just need the other SET.
3451 We prefer this over the PARALLEL.
3453 This can occur when simplifying a divmod insn. We *must* test for this
3454 case here because the code below that splits two independent SETs doesn't
3455 handle this case correctly when it updates the register status.
3457 It's pointless doing this if we originally had two sets, one from
3458 i3, and one from i2. Combining then splitting the parallel results
3459 in the original i2 again plus an invalid insn (which we delete).
3460 The net effect is only to move instructions around, which makes
3461 debug info less accurate. */
3466 {
3477 {
3480 }
3489 {
3495 }
3499 }
3501 /* Is the result of combination a valid instruction? */
3505 /* If we were combining three insns and the result is a simple SET
3506 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3507 insns. There are two ways to do this. It can be split using a
3508 machine-specific method (like when you have an addition of a large
3509 constant) or by combine in the function find_split_point. */
3513 {
3517 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3518 use I2DEST as a scratch register will help. In the latter case,
3519 convert I2DEST to the mode of the source of NEWPAT if we can. */
3523 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3524 inputs of NEWPAT. */
3526 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3527 possible to try that as a scratch reg. This would require adding
3528 more code to make it work though. */
3531 {
3534 /* First try to split using the original register as a
3535 scratch register. */
3539 i2dest)));
3542 /* If that didn't work, try changing the mode of I2DEST if
3543 we can. */
3548 {
3550 rtx ni2dest;
3554 else
3555 {
3558 }
3560 parallel = (gen_rtx_PARALLEL
3564 ni2dest))));
3569 {
3577 }
3578 }
3581 }
3583 /* If recog_for_combine has discarded clobbers, try to use them
3584 again for the split. */
3586 {
3589 }
3592 {
3597 }
3601 {
3611 /* If I2 or I3 has multiple SETs, we won't know how to track
3612 register status, so don't use these insns. If I2's destination
3613 is used between I2 and I3, we also can't use these insns. */
3623 /* It is possible that both insns now set the destination of I3.
3624 If so, we must show an extra use of it. */
3627 {
3646 }
3647 }
3649 /* If we can split it and use I2DEST, go ahead and see if that
3650 helps things be recognized. Verify that none of the registers
3651 are set between I2 and I3. */
3655 /* We need I2DEST in the proper mode. If it is a hard register
3656 or the only use of a pseudo, we can change its mode.
3657 Make sure we don't change a hard register to have a mode that
3658 isn't valid for it, or change the number of registers. */
3665 /* We can't overwrite I2DEST if its value is still used by
3666 NEWPAT. */
3668 {
3677 /* *SPLIT may be part of I2SRC, so make sure we have the
3678 original expression around for later debug processing.
3679 We should not need I2SRC any more in other cases. */
3682 else
3685 /* Get NEWDEST as a register in the proper mode. We have already
3686 validated that we can do this. */
3688 {
3691 else
3692 {
3695 }
3696 }
3698 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3699 an ASHIFT. This can occur if it was inside a PLUS and hence
3700 appeared to be a memory address. This is a kludge. */
3705 {
3708 /* Update split_code because we may not have a multiply
3709 anymore. */
3711 }
3713 /* Similarly for (plus (mult FOO (const_int pow2))). */
3719 {
3723 /* Update split_code because we may not have a multiply
3724 anymore. */
3726 }
3728 #ifdef INSN_SCHEDULING
3729 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3730 be written as a ZERO_EXTEND. */
3732 {
3733 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3734 what it really is. */
3739 else
3742 }
3743 #endif
3745 /* Attempt to split binary operators using arithmetic identities. */
3749 {
3756 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3758 {
3763 }
3764 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3771 {
3777 /* Split both "((X op Y) op X) op Y" and
3778 "((X op Y) op Y) op X" as "T op T" where T is
3779 "X op Y". */
3782 {
3787 }
3788 /* Split "((X op X) op Y) op Y)" as "T op T" where
3789 T is "X op Y". */
3791 {
3797 }
3798 }
3799 }
3802 {
3805 }
3809 /* recog_for_combine might have added CLOBBERs to newi2pat.
3810 Make sure NEWPAT does not depend on the clobbered regs. */
3814 {
3817 {
3820 }
3821 }
3823 /* If the split point was a MULT and we didn't have one before,
3824 don't use one now. */
3827 }
3828 }
3830 /* Check for a case where we loaded from memory in a narrow mode and
3831 then sign extended it, but we need both registers. In that case,
3832 we have a PARALLEL with both loads from the same memory location.
3833 We can split this into a load from memory followed by a register-register
3834 copy. This saves at least one insn, more if register allocation can
3835 eliminate the copy.
3837 We cannot do this if the destination of the first assignment is a
3838 condition code register or cc0. We eliminate this case by making sure
3839 the SET_DEST and SET_SRC have the same mode.
3841 We cannot do this if the destination of the second assignment is
3842 a register that we have already assumed is zero-extended. Similarly
3843 for a SUBREG of such a register. */
3878 {
3879 rtx ni2dest;
3893 }
3895 /* Similarly, check for a case where we have a PARALLEL of two independent
3896 SETs but we started with three insns. In this case, we can do the sets
3897 as two separate insns. This case occurs when some SET allows two
3898 other insns to combine, but the destination of that SET is still live.
3900 Also do this if we started with two insns and (at least) one of the
3901 resulting sets is a noop; this noop will be deleted later. */
3920 {
3924 /* Normally, it doesn't matter which of the two is done first,
3925 but the one that references cc0 can't be the second, and
3926 one which uses any regs/memory set in between i2 and i3 can't
3927 be first. The PARALLEL might also have been pre-existing in i3,
3928 so we need to make sure that we won't wrongly hoist a SET to i2
3929 that would conflict with a death note present in there. */
3937 /* If I3 is a jump, ensure that set0 is a jump so that
3938 we do not create invalid RTL. */
3940 )
3941 {
3944 }
3952 /* If I3 is a jump, ensure that set1 is a jump so that
3953 we do not create invalid RTL. */
3955 )
3956 {
3959 }
3960 else
3961 {
3964 }
3969 {
3970 /* recog_for_combine might have added CLOBBERs to newi2pat.
3971 Make sure NEWPAT does not depend on the clobbered regs. */
3973 {
3976 {
3979 {
3982 }
3983 }
3984 }
3987 }
3988 }
3990 /* If it still isn't recognized, fail and change things back the way they
3991 were. */
3993 /* Is the result a reasonable ASM_OPERANDS? */
3995 {
3998 }
4000 /* If we had to change another insn, make sure it is valid also. */
4002 {
4010 {
4013 }
4014 }
4016 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4017 they are adjacent to each other or not. */
4019 {
4023 {
4026 }
4027 }
4029 /* Only allow this combination if insn_rtx_costs reports that the
4030 replacement instructions are cheaper than the originals. */
4032 {
4035 }
4038 {
4043 {
4048 /* Temporarily revert mode back. */
4052 {
4053 /* If we used i2dest as a scratch register with a
4054 different mode, substitute it for the original
4055 i2src while its original mode is temporarily
4056 restored, and then clear i2scratch so that we don't
4057 do it again later. */
4059 this_basic_block);
4061 /* Put back the new mode. */
4063 }
4064 else
4065 {
4070 {
4073 }
4074 else
4075 {
4082 }
4084 /* We're dealing with a reg that changed mode but not
4085 meaning, so we want to turn it into a subreg for
4086 the new mode. However, because of REG sharing and
4087 because its mode had already changed, we have to do
4088 it in two steps. First, replace any debug uses of
4089 reg, with its original mode temporarily restored,
4090 with this copy we have created; then, replace the
4091 copy with the SUBREG of the original shared reg,
4092 once again changed to the new mode. */
4094 this_basic_block);
4098 this_basic_block);
4099 }
4100 }
4101 }
4103 /* If we will be able to accept this, we have made a
4104 change to the destination of I3. This requires us to
4105 do a few adjustments. */
4108 {
4111 }
4113 /* We now know that we can do this combination. Merge the insns and
4114 update the status of registers and LOG_LINKS. */
4117 {
4122 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4123 ensure that they are still valid. Then add any non-duplicate
4124 notes added by recog_for_combine. */
4126 {
4136 }
4140 NULL_RTX);
4141 }
4144 {
4147 rtx ni2dest;
4149 /* I3 now uses what used to be its destination and which is now
4150 I2's destination. This requires us to do a few adjustments. */
4154 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4155 so we still will.
4157 However, some later insn might be using I2's dest and have
4158 a LOG_LINK pointing at I3. We must remove this link.
4159 The simplest way to remove the link is to point it at I1,
4160 which we know will be a NOTE. */
4162 /* newi2pat is usually a SET here; however, recog_for_combine might
4163 have added some clobbers. */
4166 else
4173 {
4175 {
4181 }
4182 }
4183 }
4185 {
4190 /* Compute which registers we expect to eliminate. newi2pat may be setting
4191 either i3dest or i2dest, so we must check it. */
4194 || !i2dest_killed
4196 /* For i1, we need to compute both local elimination and global
4197 elimination information with respect to newi2pat because i1dest
4198 may be the same as i3dest, in which case newi2pat may be setting
4199 i1dest. Global information is used when distributing REG_DEAD
4200 note for i2 and i3, in which case it does matter if newi2pat sets
4201 i1dest or not.
4203 Local information is used when distributing REG_DEAD note for i1,
4204 in which case it doesn't matter if newi2pat sets i1dest or not.
4205 See PR62151, if we have four insns combination:
4206 i0: r0 <- i0src
4207 i1: r1 <- i1src (using r0)
4208 REG_DEAD (r0)
4209 i2: r0 <- i2src (using r1)
4210 i3: r3 <- i3src (using r0)
4211 ix: using r0
4212 From i1's point of view, r0 is eliminated, no matter if it is set
4213 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4214 should be discarded.
4216 Note local information only affects cases in forms like "I1->I2->I3",
4217 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4218 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4219 i0dest anyway. */
4221 || !i1dest_killed
4226 /* Same case as i1. */
4233 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4234 clear them. */
4242 /* Ensure that we do not have something that should not be shared but
4243 occurs multiple times in the new insns. Check this by first
4244 resetting all the `used' flags and then copying anything is shared. */
4268 {
4275 {
4276 /* I2SRC must still be meaningful at this point. Some splitting
4277 operations can invalidate I2SRC, but those operations do not
4278 apply to calls. */
4281 }
4289 }
4294 /* We had one special case above where I2 had more than one set and
4295 we replaced a destination of one of those sets with the destination
4296 of I3. In that case, we have to update LOG_LINKS of insns later
4297 in this basic block. Note that this (expensive) case is rare.
4299 Also, in this case, we must pretend that all REG_NOTEs for I2
4300 actually came from I3, so that REG_UNUSED notes from I2 will be
4301 properly handled. */
4304 {
4313 temp_insn
4323 {
4328 }
4329 else
4332 }
4340 {
4343 this_basic_block);
4346 }
4347 else
4348 {
4351 this_basic_block);
4353 }
4356 {
4361 this_basic_block);
4363 }
4366 {
4371 this_basic_block);
4373 }
4375 /* Get death notes for everything that is now used in either I3 or
4376 I2 and used to die in a previous insn. If we built two new
4377 patterns, move from I1 to I2 then I2 to I3 so that we get the
4378 proper movement on registers that I2 modifies. */
4384 else
4390 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4407 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4408 know these are REG_UNUSED and want them to go to the desired insn,
4409 so we always pass it as i3. */
4413 NULL_RTX);
4417 NULL_RTX);
4419 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4420 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4421 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4422 in that case, it might delete I2. Similarly for I2 and I1.
4423 Show an additional death due to the REG_DEAD note we make here. If
4424 we discard it in distribute_notes, we will decrement it again. */
4427 {
4432 else
4435 }
4438 {
4443 else
4446 }
4449 {
4454 else
4457 }
4460 {
4465 else
4468 }
4476 {
4481 /* The insn that used to set this register doesn't exist, and
4482 this life of the register may not exist either. See if one of
4483 I3's links points to an insn that sets I2DEST. If it does,
4484 that is now the last known value for I2DEST. If we don't update
4485 this and I2 set the register to a value that depended on its old
4486 contents, we will get confused. If this insn is used, thing
4487 will be set correctly in combine_instructions. */
4495 /* If the reg formerly set in I2 died only once and that was in I3,
4496 zero its use count so it won't make `reload' do any work. */
4499 && ! i2dest_in_i2src
4502 }
4505 {
4518 && ! i1dest_in_i1src
4521 }
4524 {
4537 && ! i0dest_in_i0src
4540 }
4542 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4543 been made to this insn. The order is important, because newi2pat
4544 can affect nonzero_bits of newpat. */
4548 }
4551 {
4553 {
4556 }
4558 }
4561 {
4563 {
4566 }
4568 }
4571 {
4573 {
4576 }
4578 }
4581 {
4583 {
4586 }
4588 }
4591 {
4593 {
4596 }
4598 }
4600 /* Set new_direct_jump_p if a new return or simple jump instruction
4601 has been created. Adjust the CFG accordingly. */
4603 {
4607 }
4612 {
4615 }
4617 /* A noop might also need cleaning up of CFG, if it comes from the
4618 simplification of a jump. */
4623 {
4626 }
4633 {
4636 }
4638 combine_successes++;
4645 else
4647 }
4648 \f
4649 /* Get a marker for undoing to the current state. */
4653 {
4655 }
4657 /* Undo the modifications up to the marker. */
4659 static void
4661 {
4665 {
4670 {
4685 }
4689 }
4692 }
4694 /* Undo all the modifications recorded in undobuf. */
4696 static void
4698 {
4700 }
4702 /* We've committed to accepting the changes we made. Move all
4703 of the undos to the free list. */
4705 static void
4707 {
4711 {
4715 }
4717 }
4718 \f
4719 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4720 where we have an arithmetic expression and return that point. LOC will
4721 be inside INSN.
4723 try_combine will call this function to see if an insn can be split into
4724 two insns. */
4728 {
4737 /* First special-case some codes. */
4739 {
4741 #ifdef INSN_SCHEDULING
4742 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4743 point. */
4746 #endif
4750 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4751 using LO_SUM and HIGH. */
4754 {
4762 }
4764 /* If we have a PLUS whose second operand is a constant and the
4765 address is not valid, perhaps will can split it up using
4766 the machine-specific way to split large constants. We use
4767 the first pseudo-reg (one of the virtual regs) as a placeholder;
4768 it will not remain in the result. */
4773 {
4776 subst_insn);
4778 /* This should have produced two insns, each of which sets our
4779 placeholder. If the source of the second is a valid address,
4780 we can make put both sources together and make a split point
4781 in the middle. */
4794 && memory_address_addr_space_p
4797 {
4801 /* Replace the placeholder in SRC2 with SRC1. If we can
4802 find where in SRC2 it was placed, that can become our
4803 split point and we can replace this address with SRC2.
4804 Just try two obvious places. */
4815 {
4818 }
4819 }
4821 /* If that didn't work, perhaps the first operand is complex and
4822 needs to be computed separately, so make a split point there.
4823 This will occur on machines that just support REG + CONST
4824 and have a constant moved through some previous computation. */
4830 }
4832 /* If we have a PLUS whose first operand is complex, try computing it
4833 separately by making a split there. */
4844 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4845 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4846 we need to put the operand into a register. So split at that
4847 point. */
4857 /* See if we can split SET_SRC as it stands. */
4862 /* See if we can split SET_DEST as it stands. */
4867 /* See if this is a bitfield assignment with everything constant. If
4868 so, this is an IOR of an AND, so split it into that. */
4878 {
4884 unsigned HOST_WIDE_INT mask
4886 rtx or_mask;
4895 else
4896 {
4902 or_mask));
4903 }
4910 }
4912 /* Otherwise, see if this is an operation that we can split into two.
4913 If so, try to split that. */
4917 {
4919 /* If we are AND'ing with a large constant that is only a single
4920 bit and the result is only being used in a context where we
4921 need to know if it is zero or nonzero, replace it with a bit
4922 extraction. This will avoid the large constant, which might
4923 have taken more than one insn to make. If the constant were
4924 not a valid argument to the AND but took only one insn to make,
4925 this is no worse, but if it took more than one insn, it will
4926 be better. */
4936 {
4941 {
4944 }
4945 }
4949 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4950 is known to be on, this can be converted into a NEG of a shift. */
4956 {
4968 }
4974 /* We can't optimize if either mode is a partial integer
4975 mode as we don't know how many bits are significant
4976 in those modes. */
4990 {
4998 }
5003 }
5007 {
5010 /* For unsigned, we have a choice of a shift followed by an
5011 AND or two shifts. Use two shifts for field sizes where the
5012 constant might be too large. We assume here that we can
5013 always at least get 8-bit constants in an AND insn, which is
5014 true for every current RISC. */
5017 {
5018 unsigned HOST_WIDE_INT mask
5022 gen_rtx_LSHIFTRT
5030 }
5031 else
5032 {
5034 gen_rtx_fmt_ee
5045 }
5046 }
5048 /* See if this is a simple operation with a constant as the second
5049 operand. It might be that this constant is out of range and hence
5050 could be used as a split point. */
5058 /* Finally, see if this is a simple operation with its first operand
5059 not in a register. The operation might require this operand in a
5060 register, so return it as a split point. We can always do this
5061 because if the first operand were another operation, we would have
5062 already found it as a split point. */
5071 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5072 it is better to write this as (not (ior A B)) so we can split it.
5073 Similarly for IOR. */
5075 {
5083 }
5085 /* Many RISC machines have a large set of logical insns. If the
5086 second operand is a NOT, put it first so we will try to split the
5087 other operand first. */
5089 {
5093 }
5098 /* Canonicalization can produce (minus A (mult B C)), where C is a
5099 constant. It may be better to try splitting (plus (mult B -C) A)
5100 instead if this isn't a multiply by a power of two. */
5104 {
5112 mode)),
5115 }
5117 /* Split at a multiply-accumulate instruction. However if this is
5118 the SET_SRC, we likely do not have such an instruction and it's
5119 worthless to try this split. */
5128 }
5130 /* Otherwise, select our actions depending on our rtx class. */
5132 {
5138 /* ... fall through ... */
5146 /* ... fall through ... */
5148 /* Some machines have (and (shift ...) ...) insns. If X is not
5149 an AND, but XEXP (X, 0) is, use it as our split point. */
5159 /* Otherwise, we don't have a split point. */
5161 }
5162 }
5163 \f
5164 /* Throughout X, replace FROM with TO, and return the result.
5165 The result is TO if X is FROM;
5166 otherwise the result is X, but its contents may have been modified.
5167 If they were modified, a record was made in undobuf so that
5168 undo_all will (among other things) return X to its original state.
5170 If the number of changes necessary is too much to record to undo,
5171 the excess changes are not made, so the result is invalid.
5172 The changes already made can still be undone.
5173 undobuf.num_undo is incremented for such changes, so by testing that
5174 the caller can tell whether the result is valid.
5176 `n_occurrences' is incremented each time FROM is replaced.
5178 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5180 IN_COND is nonzero if we are at the top level of a condition.
5182 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5183 by copying if `n_occurrences' is nonzero. */
5185 static rtx
5187 {
5192 rtx new_rtx;
5194 /* Two expressions are equal if they are identical copies of a shared
5195 RTX or if they are both registers with the same register number
5196 and mode. */
5198 #define COMBINE_RTX_EQUAL_P(X,Y) \
5199 ((X) == (Y) \
5200 || (REG_P (X) && REG_P (Y) \
5201 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5203 /* Do not substitute into clobbers of regs -- this will never result in
5204 valid RTL. */
5209 {
5210 n_occurrences++;
5212 }
5214 /* If X and FROM are the same register but different modes, they
5215 will not have been seen as equal above. However, the log links code
5216 will make a LOG_LINKS entry for that case. If we do nothing, we
5217 will try to rerecognize our original insn and, when it succeeds,
5218 we will delete the feeding insn, which is incorrect.
5220 So force this insn not to match in this (rare) case. */
5225 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5226 of which may contain things that can be combined. */
5230 /* It is possible to have a subexpression appear twice in the insn.
5231 Suppose that FROM is a register that appears within TO.
5232 Then, after that subexpression has been scanned once by `subst',
5233 the second time it is scanned, TO may be found. If we were
5234 to scan TO here, we would find FROM within it and create a
5235 self-referent rtl structure which is completely wrong. */
5239 /* Parallel asm_operands need special attention because all of the
5240 inputs are shared across the arms. Furthermore, unsharing the
5241 rtl results in recognition failures. Failure to handle this case
5242 specially can result in circular rtl.
5244 Solve this by doing a normal pass across the first entry of the
5245 parallel, and only processing the SET_DESTs of the subsequent
5246 entries. Ug. */
5251 {
5254 /* If this substitution failed, this whole thing fails. */
5262 {
5268 {
5271 /* If this substitution failed, this whole thing fails. */
5277 }
5278 }
5279 }
5280 else
5281 {
5285 /* We don't need to process a SET_DEST that is a register, CC0,
5286 or PC, so set up to skip this common case. All other cases
5287 where we want to suppress replacing something inside a
5288 SET_SRC are handled via the IN_DEST operand. */
5295 /* Trying to simplify the operands of a widening MULT is not likely
5296 to create RTL matching a machine insn. */
5308 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5309 constant. */
5314 {
5316 {
5319 {
5321 {
5324 n_occurrences++;
5325 }
5326 else
5327 {
5329 unique_copy);
5331 /* If this substitution failed, this whole thing
5332 fails. */
5336 }
5339 }
5340 }
5342 {
5343 /* If this is a register being set, ignore it. */
5350 ;
5353 {
5354 /* In general, don't install a subreg involving two
5355 modes not tieable. It can worsen register
5356 allocation, and can even make invalid reload
5357 insns, since the reg inside may need to be copied
5358 from in the outside mode, and that may be invalid
5359 if it is an fp reg copied in integer mode.
5361 We allow two exceptions to this: It is valid if
5362 it is inside another SUBREG and the mode of that
5363 SUBREG and the mode of the inside of TO is
5364 tieable and it is valid if X is a SET that copies
5365 FROM to CC0. */
5373 && (!HAVE_cc0
5388 n_occurrences++;
5389 }
5390 else
5391 /* If we are in a SET_DEST, suppress most cases unless we
5392 have gone inside a MEM, in which case we want to
5393 simplify the address. We assume here that things that
5394 are actually part of the destination have their inner
5395 parts in the first expression. This is true for SUBREG,
5396 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5397 things aside from REG and MEM that should appear in a
5398 SET_DEST. */
5400 (((in_dest
5406 unique_copy);
5408 /* If we found that we will have to reject this combination,
5409 indicate that by returning the CLOBBER ourselves, rather than
5410 an expression containing it. This will speed things up as
5411 well as prevent accidents where two CLOBBERs are considered
5412 to be equal, thus producing an incorrect simplification. */
5418 {
5426 }
5429 {
5433 }
5434 else
5436 }
5437 }
5438 }
5440 /* Check if we are loading something from the constant pool via float
5441 extension; in this case we would undo compress_float_constant
5442 optimization and degenerate constant load to an immediate value. */
5446 {
5450 }
5452 /* Try to simplify X. If the simplification changed the code, it is likely
5453 that further simplification will help, so loop, but limit the number
5454 of repetitions that will be performed. */
5457 {
5458 /* If X is sufficiently simple, don't bother trying to do anything
5459 with it. */
5468 /* We no longer know the original mode of operand 0 since we
5469 have changed the form of X) */
5471 }
5474 }
5475 \f
5476 /* Simplify X, a piece of RTL. We just operate on the expression at the
5477 outer level; call `subst' to simplify recursively. Return the new
5478 expression.
5480 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5481 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5482 of a condition. */
5484 static rtx
5487 {
5490 rtx temp;
5493 /* If this is a commutative operation, put a constant last and a complex
5494 expression first. We don't need to do this for comparisons here. */
5497 {
5501 }
5503 /* Try to fold this expression in case we have constants that weren't
5504 present before. */
5507 {
5515 {
5518 {
5522 }
5525 }
5538 }
5541 {
5546 }
5548 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5549 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5550 things. Check for cases where both arms are testing the same
5551 condition.
5553 Don't do anything if all operands are very simple. */
5566 {
5571 /* If everything is a comparison, what we have is highly unlikely
5572 to be simpler, so don't use it. */
5575 {
5582 /* Simplify the alternative arms; this may collapse the true and
5583 false arms to store-flag values. Be careful to use copy_rtx
5584 here since true_rtx or false_rtx might share RTL with x as a
5585 result of the if_then_else_cond call above. */
5589 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5590 is unlikely to be simpler. */
5593 {
5596 /* Restarting if we generate a store-flag expression will cause
5597 us to loop. Just drop through in this case. */
5599 /* If the result values are STORE_FLAG_VALUE and zero, we can
5600 just make the comparison operation. */
5611 /* Likewise, we can make the negate of a comparison operation
5612 if the result values are - STORE_FLAG_VALUE and zero. */
5620 mode);
5631 mode);
5632 else
5635 mode,
5636 VOIDmode,
5637 cond,
5638 cop1),
5643 }
5644 }
5645 }
5647 /* First see if we can apply the inverse distributive law. */
5650 {
5654 }
5656 /* If CODE is an associative operation not otherwise handled, see if we
5657 can associate some operands. This can win if they are constants or
5658 if they are logically related (i.e. (a & b) & a). */
5664 {
5666 {
5670 rtx inner;
5672 /* Make sure we pass the constant operand if any as the second
5673 one if this is a commutative operation. */
5681 /* For commutative operations, try the other pair if that one
5682 didn't simplify. */
5684 {
5689 }
5693 }
5694 }
5696 /* A little bit of algebraic simplification here. */
5698 {
5700 /* Ensure that our address has any ASHIFTs converted to MULT in case
5701 address-recognizing predicates are called later. */
5710 /* See if this can be moved to simplify_subreg. */
5713 /* Don't call gen_lowpart if the inner mode
5714 is VOIDmode and we cannot simplify it, as SUBREG without
5715 inner mode is invalid. */
5722 {
5723 rtx temp;
5729 /* If op is known to have all lower bits zero, the result is zero. */
5739 }
5741 /* Don't change the mode of the MEM if that would change the meaning
5742 of the address. */
5749 /* Note that we cannot do any narrowing for non-constants since
5750 we might have been counting on using the fact that some bits were
5751 zero. We now do this in the SET. */
5758 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5759 replaced by (lshiftrt X C). This will convert
5760 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5768 /* If X has only a single bit that might be nonzero, say, bit I, convert
5769 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5770 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5771 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5772 or a SUBREG of one since we'd be making the expression more
5773 complex if it was just a register. */
5779 {
5780 rtx temp1 = simplify_shift_const
5786 /* If all we did was surround TEMP with the two shifts, we
5787 haven't improved anything, so don't use it. Otherwise,
5788 we are better off with TEMP1. */
5793 }
5797 /* We can't handle truncation to a partial integer mode here
5798 because we don't know the real bitsize of the partial
5799 integer mode. */
5808 /* We can truncate a constant value and return it. */
5812 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5813 whose value is a comparison can be replaced with a subreg if
5814 STORE_FLAG_VALUE permits. */
5823 /* (const (const X)) can become (const X). Do it this way rather than
5824 returning the inner CONST since CONST can be shared with a
5825 REG_EQUAL note. */
5831 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5832 can add in an offset. find_split_point will split this address up
5833 again if it doesn't match. */
5840 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5841 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5842 bit-field and can be replaced by either a sign_extend or a
5843 sign_extract. The `and' may be a zero_extend and the two
5844 <c>, -<c> constants may be reversed. */
5859 return simplify_shift_const
5866 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5867 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5868 the bitsize of the mode - 1. This allows simplification of
5869 "a = (b & 8) == 0;" */
5881 /* If we are adding two things that have no bits in common, convert
5882 the addition into an IOR. This will often be further simplified,
5883 for example in cases like ((a & 1) + (a & 2)), which can
5884 become a & 3. */
5889 {
5890 /* Try to simplify the expression further. */
5894 /* If we could, great. If not, do not go ahead with the IOR
5895 replacement, since PLUS appears in many special purpose
5896 address arithmetic instructions. */
5904 }
5906 /* Canonicalize x + x into x << 1. */
5915 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5916 (and <foo> (const_int pow2-1)) */
5926 /* If we have (mult (plus A B) C), apply the distributive law and then
5927 the inverse distributive law to see if things simplify. This
5928 occurs mostly in addresses, often when unrolling loops. */
5931 {
5935 }
5937 /* Try simplify a*(b/c) as (a*b)/c. */
5940 {
5946 }
5950 /* If this is a divide by a power of two, treat it as a shift if
5951 its first operand is a shift. */
5969 /* If the first operand is a condition code, we can't do anything
5970 with it. */
5974 {
5982 /* Simplify our comparison, if possible. */
5985 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5986 if only the low-order bit is possibly nonzero in X (such as when
5987 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5988 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5989 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5990 (plus X 1).
5992 Remove any ZERO_EXTRACT we made when thinking this was a
5993 comparison. It may now be simpler to use, e.g., an AND. If a
5994 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5995 the call to make_compound_operation in the SET case.
5997 Don't apply these optimizations if the caller would
5998 prefer a comparison rather than a value.
5999 E.g., for the condition in an IF_THEN_ELSE most targets need
6000 an explicit comparison. */
6003 ;
6019 {
6023 mode);
6024 }
6031 {
6035 const1_rtx);
6036 }
6044 {
6047 }
6049 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6050 those above. */
6052 ;
6068 {
6072 mode);
6073 }
6081 {
6085 mode);
6086 }
6088 /* If X is 0/1, (eq X 0) is X-1. */
6094 {
6097 }
6099 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6100 one bit that might be nonzero, we can convert (ne x 0) to
6101 (ashift x c) where C puts the bit in the sign bit. Remove any
6102 AND with STORE_FLAG_VALUE when we are done, since we are only
6103 going to test the sign bit. */
6110 {
6116 else
6118 }
6120 /* If the code changed, return a whole new comparison.
6121 We also need to avoid using SUBST in cases where
6122 simplify_comparison has widened a comparison with a CONST_INT,
6123 since in that case the wider CONST_INT may fail the sanity
6124 checks in do_SUBST. */
6131 /* Otherwise, keep this operation, but maybe change its operands.
6132 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6135 }
6145 /* If we are processing SET_DEST, we are done. */
6163 /* If this is a shift by a constant amount, simplify it. */
6171 (HOST_WIDE_INT_1U
6179 }
6182 }
6183 \f
6184 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6186 static rtx
6188 {
6195 rtx temp;
6198 rtx reversed;
6200 /* Simplify storing of the truth value. */
6205 /* Also when the truth value has to be reversed. */
6211 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6212 in it is being compared against certain values. Get the true and false
6213 comparisons and see if that says anything about the value of each arm. */
6219 {
6220 HOST_WIDE_INT nzb;
6226 /* If FALSE_CODE is EQ, swap the codes and arms. */
6229 {
6232 }
6234 /* If we are comparing against zero and the expression being tested has
6235 only a single bit that might be nonzero, that is its value when it is
6236 not equal to zero. Similarly if it is known to be -1 or 0. */
6240 {
6243 }
6247 {
6250 }
6252 /* Now simplify an arm if we know the value of the register in the
6253 branch and it is used in the arm. Be careful due to the potential
6254 of locally-shared RTL. */
6271 }
6273 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6274 reversed, do so to avoid needing two sets of patterns for
6275 subtract-and-branch insns. Similarly if we have a constant in the true
6276 arm, the false arm is the same as the first operand of the comparison, or
6277 the false arm is more complicated than the true arm. */
6290 {
6299 /* It is possible that the conditional has been simplified out. */
6302 }
6304 /* If the two arms are identical, we don't need the comparison. */
6309 /* Convert a == b ? b : a to "a". */
6321 /* Look for cases where we have (abs x) or (neg (abs X)). */
6324 && comparison_p
6331 {
6337 return
6340 mode);
6343 }
6345 /* Look for MIN or MAX. */
6348 && comparison_p
6353 {
6368 }
6370 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6371 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6372 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6373 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6374 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6375 neither 1 or -1, but it isn't worth checking for. */
6378 && comparison_p
6381 {
6397 /* If an identity-zero op is commutative, check whether there
6398 would be a match if we swapped the operands. */
6418 {
6422 }
6434 {
6438 }
6454 {
6458 }
6470 {
6474 }
6477 {
6483 const_true_rtx));
6491 }
6492 }
6494 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6495 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6496 negation of a single bit, we can convert this operation to a shift. We
6497 can actually do this more generally, but it doesn't seem worth it. */
6506 return
6510 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6520 }
6521 \f
6522 /* Simplify X, a SET expression. Return the new expression. */
6524 static rtx
6526 {
6529 machine_mode mode
6534 /* (set (pc) (return)) gets written as (return). */
6538 /* Now that we know for sure which bits of SRC we are using, see if we can
6539 simplify the expression for the object knowing that we only need the
6540 low-order bits. */
6543 {
6546 }
6548 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6549 the comparison result and try to simplify it unless we already have used
6550 undobuf.other_insn. */
6558 {
6567 {
6570 {
6573 }
6574 }
6575 else
6583 {
6587 }
6588 else
6589 {
6594 /* Attempt to simplify CC user. */
6596 {
6600 }
6602 /* Convert X into a no-op move. */
6606 }
6608 /* Simplify our comparison, if possible. */
6611 #ifdef SELECT_CC_MODE
6612 /* If this machine has CC modes other than CCmode, check to see if we
6613 need to use a different CC mode here. */
6622 else
6625 /* If the mode changed, we have to change SET_DEST, the mode in the
6626 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6627 a hard register, just build new versions with the proper mode. If it
6628 is a pseudo, we lose unless it is only time we set the pseudo, in
6629 which case we can safely change its mode. */
6631 {
6633 {
6635 rtx new_dest;
6639 else
6640 {
6643 }
6650 }
6651 }
6654 /* If the code changed, we have to build a new comparison in
6655 undobuf.other_insn. */
6657 {
6666 /* If the only change we made was to change an EQ into an NE or
6667 vice versa, OP0 has only one bit that might be nonzero, and OP1
6668 is zero, check if changing the user of the condition code will
6669 produce a valid insn. If it won't, we can keep the original code
6670 in that insn by surrounding our operation with an XOR. */
6677 {
6682 {
6689 }
6690 }
6691 }
6696 /* Don't generate a compare of a CC with 0, just use that CC. */
6698 {
6701 }
6702 /* Otherwise, if we didn't previously have the same COMPARE we
6703 want, create it from scratch. */
6706 {
6709 }
6710 }
6711 else
6712 {
6713 /* Get SET_SRC in a form where we have placed back any
6714 compound expressions. Then do the checks below. */
6717 }
6719 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6720 and X being a REG or (subreg (reg)), we may be able to convert this to
6721 (set (subreg:m2 x) (op)).
6723 We can always do this if M1 is narrower than M2 because that means that
6724 we only care about the low bits of the result.
6726 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6727 perform a narrower operation than requested since the high-order bits will
6728 be undefined. On machine where it is defined, this transformation is safe
6729 as long as M1 and M2 have the same number of words. */
6737 && (WORD_REGISTER_OPERATIONS
6740 #ifdef CANNOT_CHANGE_MODE_CLASS
6745 #endif
6749 {
6752 dest));
6756 }
6758 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6759 in SRC. */
6765 {
6769 /* Here we make sure that we don't have a sign bit on. */
6772 {
6775 }
6776 }
6778 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6779 would require a paradoxical subreg. Replace the subreg with a
6780 zero_extend to avoid the reload that would otherwise be required. */
6788 {
6794 }
6796 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6797 are comparing an item known to be 0 or -1 against 0, use a logical
6798 operation instead. Check for one of the arms being an IOR of the other
6799 arm with some value. We compute three terms to be IOR'ed together. In
6800 practice, at most two will be nonzero. Then we do the IOR's. */
6808 && (!HAVE_conditional_move
6814 {
6840 false_rtx);
6846 term3));
6849 }
6851 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6852 whole thing fail. */
6857 else
6858 /* Convert this into a field assignment operation, if possible. */
6860 }
6861 \f
6862 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6863 result. */
6865 static rtx
6867 {
6873 {
6875 /* We can call simplify_and_const_int only if we don't lose
6876 any (sign) bits when converting INTVAL (op1) to
6877 "unsigned HOST_WIDE_INT". */
6881 {
6888 }
6890 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6891 apply the distributive law and then the inverse distributive
6892 law to see if things simplify. */
6894 {
6898 }
6900 {
6904 }
6908 /* If we have (ior (and A B) C), apply the distributive law and then
6909 the inverse distributive law to see if things simplify. */
6912 {
6916 }
6919 {
6923 }
6928 }
6931 }
6932 \f
6933 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6934 operations" because they can be replaced with two more basic operations.
6935 ZERO_EXTEND is also considered "compound" because it can be replaced with
6936 an AND operation, which is simpler, though only one operation.
6938 The function expand_compound_operation is called with an rtx expression
6939 and will convert it to the appropriate shifts and AND operations,
6940 simplifying at each stage.
6942 The function make_compound_operation is called to convert an expression
6943 consisting of shifts and ANDs into the equivalent compound expression.
6944 It is the inverse of this function, loosely speaking. */
6946 static rtx
6948 {
6952 rtx tem;
6955 {
6959 /* We can't necessarily use a const_int for a multiword mode;
6960 it depends on implicitly extending the value.
6961 Since we don't know the right way to extend it,
6962 we can't tell whether the implicit way is right.
6964 Even for a mode that is no wider than a const_int,
6965 we can't win, because we need to sign extend one of its bits through
6966 the rest of it, and we don't know which bit. */
6970 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6971 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6972 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6973 reloaded. If not for that, MEM's would very rarely be safe.
6975 Reject MODEs bigger than a word, because we might not be able
6976 to reference a two-register group starting with an arbitrary register
6977 (and currently gen_lowpart might crash for a SUBREG). */
6982 /* Reject MODEs that aren't scalar integers because turning vector
6983 or complex modes into shifts causes problems. */
6989 /* If the inner object has VOIDmode (the only way this can happen
6990 is if it is an ASM_OPERANDS), we can't do anything since we don't
6991 know how much masking to do. */
7000 /* ... fall through ... */
7003 /* If the operand is a CLOBBER, just return it. */
7012 /* Reject MODEs that aren't scalar integers because turning vector
7013 or complex modes into shifts causes problems. */
7021 /* This should stay within the object being extracted, fail otherwise. */
7032 }
7033 /* Convert sign extension to zero extension, if we know that the high
7034 bit is not set, as this is easier to optimize. It will be converted
7035 back to cheaper alternative in make_extraction. */
7043 {
7048 /* Make sure this is a profitable operation. */
7055 else
7057 }
7059 /* We can optimize some special cases of ZERO_EXTEND. */
7061 {
7062 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7063 know that the last value didn't have any inappropriate bits
7064 set. */
7072 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7081 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7082 is a comparison and STORE_FLAG_VALUE permits. This is like
7083 the first case, but it works even when GET_MODE (x) is larger
7084 than HOST_WIDE_INT. */
7093 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7103 }
7105 /* If we reach here, we want to return a pair of shifts. The inner
7106 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7107 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7108 logical depending on the value of UNSIGNEDP.
7110 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7111 converted into an AND of a shift.
7113 We must check for the case where the left shift would have a negative
7114 count. This can happen in a case like (x >> 31) & 255 on machines
7115 that can't shift by a constant. On those machines, we would first
7116 combine the shift with the AND to produce a variable-position
7117 extraction. Then the constant of 31 would be substituted in
7118 to produce such a position. */
7122 {
7131 }
7138 else
7139 /* Any other cases we can't handle. */
7142 /* If we couldn't do this for some reason, return the original
7143 expression. */
7148 }
7149 \f
7150 /* X is a SET which contains an assignment of one object into
7151 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7152 or certain SUBREGS). If possible, convert it into a series of
7153 logical operations.
7155 We half-heartedly support variable positions, but do not at all
7156 support variable lengths. */
7158 static const_rtx
7160 {
7161 rtx inner;
7165 machine_mode compute_mode;
7167 /* Loop until we find something we can't simplify. */
7169 {
7172 {
7176 }
7179 {
7184 /* A constant position should stay within the width of INNER. */
7190 {
7198 /* If position is ADJUST - X, new position is X. */
7200 else
7201 {
7206 pos);
7207 }
7208 }
7209 }
7211 /* A SUBREG between two modes that occupy the same numbers of words
7212 can be done by moving the SUBREG to the source. */
7214 /* We need SUBREGs to compute nonzero_bits properly. */
7215 && nonzero_sign_valid
7220 {
7222 gen_lowpart
7226 }
7227 else
7235 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7237 {
7238 machine_mode imode;
7240 /* Don't do anything for vector or complex integral types. */
7244 /* Try to find an integral mode to pun with. */
7251 }
7253 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7257 /* Don't try to compute in too wide unsupported modes. */
7261 /* Now compute the equivalent expression. Make a copy of INNER
7262 for the SET_DEST in case it is a MEM into which we will substitute;
7263 we don't want shared RTL in that case. */
7265 compute_mode);
7269 compute_mode,
7271 compute_mode),
7272 inner);
7277 mask),
7278 pos);
7283 }
7286 }
7287 \f
7288 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7289 it is an RTX that represents the (variable) starting position; otherwise,
7290 POS is the (constant) starting bit position. Both are counted from the LSB.
7292 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7294 IN_DEST is nonzero if this is a reference in the destination of a SET.
7295 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7296 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7297 be used.
7299 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7300 ZERO_EXTRACT should be built even for bits starting at bit 0.
7302 MODE is the desired mode of the result (if IN_DEST == 0).
7304 The result is an RTX for the extraction or NULL_RTX if the target
7305 can't handle it. */
7307 static rtx
7311 {
7312 /* This mode describes the size of the storage area
7313 to fetch the overall value from. Within that, we
7314 ignore the POS lowest bits, etc. */
7316 machine_mode inner_mode;
7317 machine_mode wanted_inner_mode;
7324 HOST_WIDE_INT orig_pos;
7330 {
7331 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7332 consider just the QI as the memory to extract from.
7333 The subreg adds or removes high bits; its mode is
7334 irrelevant to the meaning of this extraction,
7335 since POS and LEN count from the lsb. */
7339 }
7344 {
7345 /* We're extracting the least significant bits of an rtx
7346 (ashift X (const_int C)), where LEN > C. Extract the
7347 least significant (LEN - C) bits of X, giving an rtx
7348 whose mode is MODE, then shift it left C times. */
7354 }
7360 /* See if this can be done without an extraction. We never can if the
7361 width of the field is not the same as that of some integer mode. For
7362 registers, we can only avoid the extraction if the position is at the
7363 low-order bit and this is either not in the destination or we have the
7364 appropriate STRICT_LOW_PART operation available.
7366 For MEM, we can avoid an extract if the field starts on an appropriate
7367 boundary and we can change the mode of the memory reference. */
7376 && (! in_dest
7380 && (pos
7383 /* We can't do this if we are widening INNER_MODE (it
7384 may not be aligned, for one thing). */
7390 {
7391 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7392 field. If the original and current mode are the same, we need not
7393 adjust the offset. Otherwise, we do if bytes big endian.
7395 If INNER is not a MEM, get a piece consisting of just the field
7396 of interest (in this case POS % BITS_PER_WORD must be 0). */
7399 {
7400 HOST_WIDE_INT offset;
7402 /* POS counts from lsb, but make OFFSET count in memory order. */
7405 else
7409 }
7411 {
7413 {
7414 /* We can't call gen_lowpart in a DEST since we
7415 always want a SUBREG (see below) and it would sometimes
7416 return a new hard register. */
7418 {
7433 /* Avoid creating invalid subregs, for example when
7434 simplifying (x>>32)&255. */
7439 }
7440 else
7442 }
7443 else
7445 }
7446 else
7448 len >= HOST_BITS_PER_WIDE_INT
7449 ? HOST_WIDE_INT_M1U
7453 /* If this extraction is going into the destination of a SET,
7454 make a STRICT_LOW_PART unless we made a MEM. */
7469 /* If we know that no extraneous bits are set, and that the high
7470 bit is not set, convert the extraction to the cheaper of
7471 sign and zero extension, that are equivalent in these cases. */
7477 {
7481 /* Prefer ZERO_EXTENSION, since it gives more information to
7482 backends. */
7487 }
7489 /* Otherwise, sign- or zero-extend unless we already are in the
7490 proper mode. */
7494 }
7496 /* Unless this is a COMPARE or we have a funny memory reference,
7497 don't do anything with zero-extending field extracts starting at
7498 the low-order bit since they are simple AND operations. */
7503 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7504 if the position is not a constant and the length is not 1. In all
7505 other cases, we would only be going outside our object in cases when
7506 an original shift would have been undefined. */
7515 /* If INNER is not from memory, we want it to have the mode of a register
7516 extraction pattern's structure operand, or word_mode if there is no
7517 such pattern. The same applies to extraction_mode and pos_mode
7518 and their respective operands.
7520 For memory, assume that the desired extraction_mode and pos_mode
7521 are the same as for a register operation, since at present we don't
7522 have named patterns for aligned memory structures. */
7526 {
7530 }
7532 /* Never narrow an object, since that might not be safe. */
7540 else
7541 {
7542 /* Be careful not to go beyond the extracted object and maintain the
7543 natural alignment of the memory. */
7547 {
7550 }
7551 }
7556 {
7557 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7558 BITS_BIG_ENDIAN style. If position is constant, compute new
7559 position. Otherwise, build subtraction.
7560 Note that POS is relative to the mode of the original argument.
7561 If it's a MEM we need to recompute POS relative to that.
7562 However, if we're extracting from (or inserting into) a register,
7563 we want to recompute POS relative to wanted_inner_mode. */
7570 else
7571 pos_rtx
7574 pos_rtx);
7575 /* POS may be less than 0 now, but we check for that below.
7576 Note that it can only be less than 0 if !MEM_P (inner). */
7577 }
7579 /* If INNER has a wider mode, and this is a constant extraction, try to
7580 make it smaller and adjust the byte to point to the byte containing
7581 the value. */
7584 && ! pos_rtx
7589 {
7592 /* The computations below will be correct if the machine is big
7593 endian in both bits and bytes or little endian in bits and bytes.
7594 If it is mixed, we must adjust. */
7596 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7597 adjust OFFSET to compensate. */
7602 /* We can now move to the desired byte. */
7613 }
7615 /* If INNER is not memory, get it into the proper mode. If we are changing
7616 its mode, POS must be a constant and smaller than the size of the new
7617 mode. */
7619 {
7620 /* On the LHS, don't create paradoxical subregs implicitely truncating
7621 the register unless TRULY_NOOP_TRUNCATION. */
7624 wanted_inner_mode))
7636 pos_rtx
7638 ? HOST_WIDE_INT_M1U
7642 }
7644 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7645 have to zero extend. Otherwise, we can just use a SUBREG. */
7648 {
7652 /* If we know that no extraneous bits are set, and that the high
7653 bit is not set, convert extraction to cheaper one - either
7654 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7655 cases. */
7663 {
7667 /* Prefer ZERO_EXTENSION, since it gives more information to
7668 backends. */
7672 }
7674 }
7676 /* Make POS_RTX unless we already have it and it is correct. If we don't
7677 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7678 be a CONST_INT. */
7685 /* Make the required operation. See if we can use existing rtx. */
7692 }
7693 \f
7694 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7695 with any other operations in X. Return X without that shift if so. */
7697 static rtx
7699 {
7702 rtx tem;
7705 {
7707 /* This is the shift itself. If it is wide enough, we will return
7708 either the value being shifted if the shift count is equal to
7709 COUNT or a shift for the difference. */
7723 /* If we can safely shift this constant and we find the inner shift,
7724 make a new operation. */
7729 {
7733 }
7738 }
7741 }
7742 \f
7743 /* Look at the expression rooted at X. Look for expressions
7744 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7745 Form these expressions.
7747 Return the new rtx, usually just X.
7749 Also, for machines like the VAX that don't have logical shift insns,
7750 try to convert logical to arithmetic shift operations in cases where
7751 they are equivalent. This undoes the canonicalizations to logical
7752 shifts done elsewhere.
7754 We try, as much as possible, to re-use rtl expressions to save memory.
7756 IN_CODE says what kind of expression we are processing. Normally, it is
7757 SET. In a memory address it is MEM. When processing the arguments of
7758 a comparison or a COMPARE against zero, it is COMPARE. */
7760 rtx
7762 {
7770 rtx tem;
7773 /* PR rtl-optimization/70944. */
7777 /* Select the code to be used in recursive calls. Once we are inside an
7778 address, we stay there. If we have a comparison, set to COMPARE,
7779 but once inside, go back to our default of SET. */
7786 /* Process depending on the code of this operation. If NEW is set
7787 nonzero, it will be returned. */
7790 {
7792 /* Convert shifts by constants into multiplications if inside
7793 an address. */
7798 {
7804 {
7807 }
7810 }
7820 {
7824 }
7827 {
7831 mode));
7833 }
7834 else
7835 {
7839 }
7850 {
7854 }
7857 {
7861 mode));
7863 }
7864 else
7865 {
7869 }
7873 /* If the second operand is not a constant, we can't do anything
7874 with it. */
7878 /* If the constant is a power of two minus one and the first operand
7879 is a logical right shift, make an extraction. */
7882 {
7886 }
7888 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7893 {
7902 {
7903 /* If we narrowed the mode when dropping the subreg, then
7904 we must zero-extend to keep the semantics of the AND. */
7906 ;
7910 else
7912 }
7914 /* If that didn't give anything, see if the AND simplifies on
7915 its own. */
7917 {
7921 }
7922 }
7923 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7929 {
7930 /* Apply the distributive law, and then try to make extractions. */
7937 }
7939 /* If we are have (and (rotate X C) M) and C is larger than the number
7940 of bits in M, this is an extraction. */
7946 {
7952 }
7954 /* On machines without logical shifts, if the operand of the AND is
7955 a logical shift and our mask turns off all the propagated sign
7956 bits, we can replace the logical shift with an arithmetic shift. */
7964 {
7971 make_compound_operation
7974 }
7976 /* If the constant is one less than a power of two, this might be
7977 representable by an extraction even if no shift is present.
7978 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7979 we are in a COMPARE. */
7983 next_code),
7986 /* If we are in a comparison and this is an AND with a power of two,
7987 convert this into the appropriate bit extract. */
7992 next_code),
7995 /* If the one operand is a paradoxical subreg of a register or memory and
7996 the constant (limited to the smaller mode) has only zero bits where
7997 the sub expression has known zero bits, this can be expressed as
7998 a zero_extend. */
8000 {
8001 rtx sub;
8007 {
8011 /* original AND constant with all the known zero bits set */
8014 {
8019 }
8020 }
8021 }
8026 /* If the sign bit is known to be zero, replace this with an
8027 arithmetic shift. */
8032 {
8035 next_code),
8038 }
8040 /* ... fall through ... */
8046 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8047 this is a SIGN_EXTRACT. */
8054 {
8061 }
8063 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8064 If so, try to merge the shifts into a SIGN_EXTEND. We could
8065 also do this for some cases of SIGN_EXTRACT, but it doesn't
8066 seem worth the effort; the case checked for occurs on Alpha. */
8083 /* Call ourselves recursively on the inner expression. If we are
8084 narrowing the object and it has a different RTL code from
8085 what it originally did, do this SUBREG as a force_to_mode. */
8086 {
8090 /* If in_code is COMPARE, it isn't always safe to pass it through
8091 to the recursive make_compound_operation call. */
8095 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8096 is (const_int 0), rather than
8097 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8107 simplified
8115 {
8116 rtx newer
8119 /* If we have something other than a SUBREG, we might have
8120 done an expansion, so rerun ourselves. */
8124 /* force_to_mode can expand compounds. If it just re-expanded the
8125 compound, use gen_lowpart to convert to the desired mode. */
8127 /* Likewise if it re-expanded the compound only partially.
8128 This happens for SUBREG of ZERO_EXTRACT if they extract
8129 the same number of bits. */
8138 }
8142 }
8147 }
8150 {
8153 }
8155 /* Now recursively process each operand of this operation. We need to
8156 handle ZERO_EXTEND specially so that we don't lose track of the
8157 inner mode. */
8159 {
8167 }
8172 {
8175 }
8178 {
8181 }
8183 maybe_swap:
8184 /* If this is a commutative operation, the changes to the operands
8185 may have made it noncanonical. */
8188 {
8192 }
8195 }
8196 \f
8197 /* Given M see if it is a value that would select a field of bits
8198 within an item, but not the entire word. Return -1 if not.
8199 Otherwise, return the starting position of the field, where 0 is the
8200 low-order bit.
8202 *PLEN is set to the length of the field. */
8204 static int
8206 {
8207 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8212 /* Now shift off the low-order zero bits and see if we have a
8213 power of two minus 1. */
8221 }
8222 \f
8223 /* If X refers to a register that equals REG in value, replace these
8224 references with REG. */
8225 static rtx
8227 {
8235 {
8271 {
8275 else
8277 }
8279 /* fall through */
8286 {
8289 {
8291 {
8294 }
8296 }
8297 }
8299 {
8302 {
8305 {
8307 {
8310 }
8312 }
8313 }
8314 }
8317 }
8320 }
8322 /* Return X converted to MODE. If the value is already truncated to
8323 MODE we can just return a subreg even though in the general case we
8324 would need an explicit truncation. */
8326 static rtx
8328 {
8333 {
8334 /* Bit-cast X into an integer mode. */
8339 }
8342 }
8344 /* See if X can be simplified knowing that we will only refer to it in
8345 MODE and will only refer to those bits that are nonzero in MASK.
8346 If other bits are being computed or if masking operations are done
8347 that select a superset of the bits in MASK, they can sometimes be
8348 ignored.
8350 Return a possibly simplified expression, but always convert X to
8351 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8353 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8354 are all off in X. This is used when X will be complemented, by either
8355 NOT, NEG, or XOR. */
8357 static rtx
8360 {
8363 machine_mode op_mode;
8367 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8368 code below will do the wrong thing since the mode of such an
8369 expression is VOIDmode.
8371 Also do nothing if X is a CLOBBER; this can happen if X was
8372 the return value from a call to gen_lowpart. */
8376 /* We want to perform the operation in its present mode unless we know
8377 that the operation is valid in MODE, in which case we do the operation
8378 in MODE. */
8383 /* It is not valid to do a right-shift in a narrower mode
8384 than the one it came in with. */
8389 /* Truncate MASK to fit OP_MODE. */
8393 /* When we have an arithmetic operation, or a shift whose count we
8394 do not know, we need to assume that all bits up to the highest-order
8395 bit in MASK will be needed. This is how we form such a mask. */
8398 else
8402 /* Determine what bits of X are guaranteed to be (non)zero. */
8405 /* If none of the bits in X are needed, return a zero. */
8409 /* If X is a CONST_INT, return a new one. Do this here since the
8410 test below will fail. */
8412 {
8415 else
8416 {
8419 }
8420 }
8422 /* If X is narrower than MODE and we want all the bits in X's mode, just
8423 get X in the proper mode. */
8428 /* We can ignore the effect of a SUBREG if it narrows the mode or
8429 if the constant masks to zero all the bits the mode doesn't have. */
8439 /* The arithmetic simplifications here only work for scalar integer modes. */
8444 {
8446 /* If X is a (clobber (const_int)), return it since we know we are
8447 generating something that won't match. */
8460 /* Similarly for a truncate. */
8464 /* If this is an AND with a constant, convert it into an AND
8465 whose constant is the AND of that constant with MASK. If it
8466 remains an AND of MASK, delete it since it is redundant. */
8469 {
8473 /* If X is still an AND, see if it is an AND with a mask that
8474 is just some low-order bits. If so, and it is MASK, we don't
8475 need it. */
8482 /* If it remains an AND, try making another AND with the bits
8483 in the mode mask that aren't in MASK turned on. If the
8484 constant in the AND is wide enough, this might make a
8485 cheaper constant. */
8490 {
8491 unsigned HOST_WIDE_INT cval
8494 rtx y;
8501 }
8504 }
8509 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8510 low-order bits (as in an alignment operation) and FOO is already
8511 aligned to that boundary, mask C1 to that boundary as well.
8512 This may eliminate that PLUS and, later, the AND. */
8514 {
8518 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8519 number, sign extend it. */
8532 }
8534 /* ... fall through ... */
8537 /* Substituting into the operands of a widening MULT is not likely to
8538 create RTL matching a machine insn. */
8548 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8549 most significant bit in MASK since carries from those bits will
8550 affect the bits we are interested in. */
8555 /* If X is (minus C Y) where C's least set bit is larger than any bit
8556 in the mask, then we may replace with (neg Y). */
8559 {
8563 }
8565 /* Similarly, if C contains every bit in the fuller_mask, then we may
8566 replace with (not Y). */
8569 {
8573 }
8580 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8581 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8582 operation which may be a bitfield extraction. Ensure that the
8583 constant we form is not wider than the mode of X. */
8595 {
8604 }
8606 binop:
8607 /* For most binary operations, just propagate into the operation and
8608 change the mode if we have an operation of that mode. */
8613 /* If we ended up truncating both operands, truncate the result of the
8614 operation instead. */
8617 {
8620 }
8630 /* For left shifts, do the same, but just for the first operand.
8631 However, we cannot do anything with shifts where we cannot
8632 guarantee that the counts are smaller than the size of the mode
8633 because such a count will have a different meaning in a
8634 wider mode. */
8644 /* If the shift count is a constant and we can do arithmetic in
8645 the mode of the shift, refine which bits we need. Otherwise, use the
8646 conservative form of the mask. */
8652 else
8664 /* Here we can only do something if the shift count is a constant,
8665 this shift constant is valid for the host, and we can do arithmetic
8666 in OP_MODE. */
8672 {
8676 /* Select the mask of the bits we need for the shift operand. */
8679 /* We can only change the mode of the shift if we can do arithmetic
8680 in the mode of the shift and INNER_MASK is no wider than the
8681 width of X's mode. */
8689 }
8691 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8692 shift and AND produces only copies of the sign bit (C2 is one less
8693 than a power of two), we can do this with just a shift. */
8697 /* The shift puts one of the sign bit copies in the least significant
8698 bit. */
8703 /* Number of bits left after the shift must be more than the mask
8704 needs. */
8707 /* Must be more sign bit copies than the mask needs. */
8717 /* If we are just looking for the sign bit, we don't need this shift at
8718 all, even if it has a variable count. */
8722 /* If this is a shift by a constant, get a mask that contains those bits
8723 that are not copies of the sign bit. We then have two cases: If
8724 MASK only includes those bits, this can be a logical shift, which may
8725 allow simplifications. If MASK is a single-bit field not within
8726 those bits, we are requesting a copy of the sign bit and hence can
8727 shift the sign bit to the appropriate location. */
8731 {
8734 /* If the considered data is wider than HOST_WIDE_INT, we can't
8735 represent a mask for all its bits in a single scalar.
8736 But we only care about the lower bits, so calculate these. */
8739 {
8742 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8743 is the number of bits a full-width mask would have set.
8744 We need only shift if these are fewer than nonzero can
8745 hold. If not, we must keep all bits set in nonzero. */
8750 + HOST_BITS_PER_WIDE_INT
8752 }
8753 else
8754 {
8757 }
8760 {
8765 }
8768 {
8769 x = simplify_shift_const
8775 }
8776 }
8778 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8779 even if the shift count isn't a constant. */
8784 shiftrt:
8786 /* If this is a zero- or sign-extension operation that just affects bits
8787 we don't care about, remove it. Be sure the call above returned
8788 something that is still a shift. */
8798 next_select);
8804 /* If the shift count is constant and we can do computations
8805 in the mode of X, compute where the bits we care about are.
8806 Otherwise, we can't do anything. Don't change the mode of
8807 the shift or propagate MODE into the shift, though. */
8810 {
8820 }
8824 /* If we just want the low-order bit, the NEG isn't needed since it
8825 won't change the low-order bit. */
8829 /* We need any bits less significant than the most significant bit in
8830 MASK since carries from those bits will affect the bits we are
8831 interested in. */
8836 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8837 same as the XOR case above. Ensure that the constant we form is not
8838 wider than the mode of X. */
8846 {
8855 }
8857 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8858 use the full mask inside the NOT. */
8861 unop:
8864 next_select));
8870 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8871 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8872 which is equal to STORE_FLAG_VALUE. */
8884 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8885 written in a narrower mode. We play it safe and do not do so. */
8901 }
8903 /* Ensure we return a value of the proper mode. */
8905 }
8906 \f
8907 /* Return nonzero if X is an expression that has one of two values depending on
8908 whether some other value is zero or nonzero. In that case, we return the
8909 value that is being tested, *PTRUE is set to the value if the rtx being
8910 returned has a nonzero value, and *PFALSE is set to the other alternative.
8912 If we return zero, we set *PTRUE and *PFALSE to X. */
8914 static rtx
8916 {
8922 /* If we are comparing a value against zero, we are done. */
8925 {
8929 }
8931 /* If this is a unary operation whose operand has one of two values, apply
8932 our opcode to compute those values. */
8935 {
8940 }
8942 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8943 make can't possibly match and would suppress other optimizations. */
8945 ;
8947 /* If this is a binary operation, see if either side has only one of two
8948 values. If either one does or if both do and they are conditional on
8949 the same value, compute the new true and false values. */
8951 {
8957 {
8958 /* If if_then_else_cond returned zero, then true/false are the
8959 same rtl. We must copy one of them to prevent invalid rtl
8960 sharing. */
8967 {
8972 }
8973 else
8974 {
8977 }
8980 }
8982 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8983 operands is zero when the other is nonzero, and vice-versa,
8984 and STORE_FLAG_VALUE is 1 or -1. */
8990 {
9007 {
9014 const_true_rtx);
9016 }
9017 }
9019 /* Similarly for MULT, AND and UMIN, except that for these the result
9020 is always zero. */
9024 {
9038 {
9041 }
9042 }
9043 }
9046 {
9047 /* If we have IF_THEN_ELSE already, extract the condition and
9048 canonicalize it if it is NE or EQ. */
9054 {
9057 }
9058 else
9060 }
9062 /* If X is a SUBREG, we can narrow both the true and false values
9063 if the inner expression, if there is a condition. */
9067 {
9073 {
9077 }
9078 }
9080 /* If X is a constant, this isn't special and will cause confusions
9081 if we treat it as such. Likewise if it is equivalent to a constant. */
9084 ;
9086 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9087 will be least confusing to the rest of the compiler. */
9089 {
9092 }
9094 /* If X is known to be either 0 or -1, those are the true and
9095 false values when testing X. */
9099 {
9102 }
9104 /* Likewise for 0 or a single bit. */
9107 {
9110 }
9112 /* Otherwise fail; show no condition with true and false values the same. */
9115 }
9116 \f
9117 /* Return the value of expression X given the fact that condition COND
9118 is known to be true when applied to REG as its first operand and VAL
9119 as its second. X is known to not be shared and so can be modified in
9120 place.
9122 We only handle the simplest cases, and specifically those cases that
9123 arise with IF_THEN_ELSE expressions. */
9125 static rtx
9127 {
9135 /* If either operand of the condition is a floating point value,
9136 then we have to avoid collapsing an EQ comparison. */
9146 /* If X is (abs REG) and we know something about REG's relationship
9147 with zero, we may be able to simplify this. */
9151 {
9160 }
9162 /* The only other cases we handle are MIN, MAX, and comparisons if the
9163 operands are the same as REG and VAL. */
9166 {
9168 {
9171 }
9174 {
9176 {
9184 else
9186 }
9189 {
9192 /* Do not reverse the condition when it is NE or EQ.
9193 This is because we cannot conclude anything about
9194 the value of 'SMAX (x, y)' when x is not equal to y,
9195 but we can when x equals y. */
9201 {
9212 }
9213 }
9214 }
9215 }
9217 {
9222 {
9223 /* We must simplify subreg here, before we lose track of the
9224 original inner_mode. */
9229 else
9231 }
9234 }
9235 /* We don't have to handle SIGN_EXTEND here, because even in the
9236 case of replacing something with a modeless CONST_INT, a
9237 CONST_INT is already (supposed to be) a valid sign extension for
9238 its narrower mode, which implies it's already properly
9239 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9240 story is different. */
9242 {
9247 {
9248 /* We must simplify the zero_extend here, before we lose
9249 track of the original inner_mode. */
9254 else
9256 }
9259 }
9263 {
9270 }
9273 }
9274 \f
9275 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9276 assignment as a field assignment. */
9278 static int
9280 {
9282 {
9287 /* For big endian, adjust the memory offset. */
9292 else
9294 }
9302 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9303 Note that all SUBREGs of MEM are paradoxical; otherwise they
9304 would have been rewritten. */
9317 /* We used to see if get_last_value of X and Y were the same but that's
9318 not correct. In one direction, we'll cause the assignment to have
9319 the wrong destination and in the case, we'll import a register into this
9320 insn that might have already have been dead. So fail if none of the
9321 above cases are true. */
9323 }
9324 \f
9325 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9326 Return that assignment if so.
9328 We only handle the most common cases. */
9330 static rtx
9332 {
9335 rtx assign;
9337 HOST_WIDE_INT c1;
9338 HOST_WIDE_INT pos;
9340 rtx other;
9341 machine_mode mode;
9343 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9344 a clear of a one-bit field. We will have changed it to
9345 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9346 for a SUBREG. */
9352 {
9358 }
9368 {
9375 }
9377 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9378 one-bit field. */
9382 {
9388 }
9390 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9391 SRC is an AND with all bits of that field set, then we can discard
9392 the AND. */
9397 {
9404 else
9407 /* Complete overlap. We can remove the source AND. */
9411 /* Partial overlap. We can reduce the source AND. */
9413 {
9418 }
9419 }
9421 /* The other case we handle is assignments into a constant-position
9422 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9423 a mask that has all one bits except for a group of zero bits and
9424 OTHER is known to have zeros where C1 has ones, this is such an
9425 assignment. Compute the position and length from C1. Shift OTHER
9426 to the appropriate position, force it to the required mode, and
9427 make the extraction. Check for the AND in both operands. */
9429 /* One or more SUBREGs might obscure the constant-position field
9430 assignment. The first one we are likely to encounter is an outer
9431 narrowing SUBREG, which we can just strip for the purposes of
9432 identifying the constant-field assignment. */
9446 /* The second SUBREG that might get in the way is a paradoxical
9447 SUBREG around the first operand of the AND. We want to
9448 pretend the operand is as wide as the destination here. We
9449 do this by adjusting the MEM to wider mode for the sole
9450 purpose of the call to rtx_equal_for_field_assignment_p. Also
9451 note this trick only works for MEMs. */
9463 /* The second SUBREG that might get in the way is a paradoxical
9464 SUBREG around the first operand of the AND. We want to
9465 pretend the operand is as wide as the destination here. We
9466 do this by adjusting the MEM to wider mode for the sole
9467 purpose of the call to rtx_equal_for_field_assignment_p. Also
9468 note this trick only works for MEMs. */
9476 else
9489 /* The mode to use for the source is the mode of the assignment, or of
9490 what is inside a possible STRICT_LOW_PART. */
9494 /* Shift OTHER right POS places and make it the source, restricting it
9495 to the proper length and mode. */
9500 dest);
9503 ? HOST_WIDE_INT_M1U
9507 /* If SRC is masked by an AND that does not make a difference in
9508 the value being stored, strip it. */
9519 }
9520 \f
9521 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9522 if so. */
9524 static rtx
9526 {
9530 rtx tem;
9532 /* Distributivity is not true for floating point as it can change the
9533 value. So we don't do it unless -funsafe-math-optimizations. */
9538 /* The outer operation can only be one of the following: */
9546 /* If either operand is a primitive we can't do anything, so get out
9547 fast. */
9557 /* See if the inner and outer operations distribute. */
9559 {
9564 /* These all distribute except over PLUS. */
9575 /* This is also a multiply, so it distributes over everything. */
9578 /* This used to handle SUBREG, but this turned out to be counter-
9579 productive, since (subreg (op ...)) usually is not handled by
9580 insn patterns, and this "optimization" therefore transformed
9581 recognizable patterns into unrecognizable ones. Therefore the
9582 SUBREG case was removed from here.
9584 It is possible that distributing SUBREG over arithmetic operations
9585 leads to an intermediate result than can then be optimized further,
9586 e.g. by moving the outer SUBREG to the other side of a SET as done
9587 in simplify_set. This seems to have been the original intent of
9588 handling SUBREGs here.
9590 However, with current GCC this does not appear to actually happen,
9591 at least on major platforms. If some case is found where removing
9592 the SUBREG case here prevents follow-on optimizations, distributing
9593 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9597 }
9599 /* Set LHS and RHS to the inner operands (A and B in the example
9600 above) and set OTHER to the common operand (C in the example).
9601 There is only one way to do this unless the inner operation is
9602 commutative. */
9614 else
9617 /* Form the new inner operation, seeing if it simplifies first. */
9620 /* There is one exception to the general way of distributing:
9621 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9623 {
9626 }
9628 /* We may be able to continuing distributing the result, so call
9629 ourselves recursively on the inner operation before forming the
9630 outer operation, which we return. */
9633 }
9635 /* See if X is of the form (* (+ A B) C), and if so convert to
9636 (+ (* A C) (* B C)) and try to simplify.
9638 Most of the time, this results in no change. However, if some of
9639 the operands are the same or inverses of each other, simplifications
9640 will result.
9642 For example, (and (ior A B) (not B)) can occur as the result of
9643 expanding a bit field assignment. When we apply the distributive
9644 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9645 which then simplifies to (and (A (not B))).
9647 Note that no checks happen on the validity of applying the inverse
9648 distributive law. This is pointless since we can do it in the
9649 few places where this routine is called.
9651 N is the index of the term that is decomposed (the arithmetic operation,
9652 i.e. (+ A B) in the first example above). !N is the index of the term that
9653 is distributed, i.e. of C in the first example above. */
9654 static rtx
9656 {
9657 machine_mode mode;
9661 /* Distributivity is not true for floating point as it can change the
9662 value. So we don't do it unless -funsafe-math-optimizations. */
9679 /* Special case (and (xor B C) (not A)), which is equivalent to
9680 (xor (ior A B) (ior A C)) */
9682 {
9685 }
9688 {
9689 /* Distribute the second term. */
9692 }
9693 else
9694 {
9695 /* Distribute the first term. */
9698 }
9708 }
9709 \f
9710 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9711 in MODE. Return an equivalent form, if different from (and VAROP
9712 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9714 static rtx
9717 {
9720 rtx orig_varop;
9728 /* Simplify VAROP knowing that we will be only looking at some of the
9729 bits in it.
9731 Note by passing in CONSTOP, we guarantee that the bits not set in
9732 CONSTOP are not significant and will never be examined. We must
9733 ensure that is the case by explicitly masking out those bits
9734 before returning. */
9737 /* If VAROP is a CLOBBER, we will fail so return it. */
9741 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9742 to VAROP and return the new constant. */
9746 /* See what bits may be nonzero in VAROP. Unlike the general case of
9747 a call to nonzero_bits, here we don't care about bits outside
9748 MODE. */
9752 /* Turn off all bits in the constant that are known to already be zero.
9753 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9754 which is tested below. */
9758 /* If we don't have any bits left, return zero. */
9762 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9763 a power of two, we can replace this with an ASHIFT. */
9768 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9769 or XOR, then try to apply the distributive law. This may eliminate
9770 operations if either branch can be simplified because of the AND.
9771 It may also make some cases more complex, but those cases probably
9772 won't match a pattern either with or without this. */
9775 return
9776 gen_lowpart
9778 apply_distributive_law
9783 constop),
9787 constop))));
9789 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9790 the AND and see if one of the operands simplifies to zero. If so, we
9791 may eliminate it. */
9795 {
9804 }
9806 /* Make a SUBREG if necessary. If we can't make it, fail. */
9811 /* If we are only masking insignificant bits, return VAROP. */
9818 /* Otherwise, return an AND. */
9820 }
9823 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9824 in MODE.
9826 Return an equivalent form, if different from X. Otherwise, return X. If
9827 X is zero, we are to always construct the equivalent form. */
9829 static rtx
9832 {
9843 }
9844 \f
9845 /* Given a REG, X, compute which bits in X can be nonzero.
9846 We don't care about bits outside of those defined in MODE.
9848 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9849 a shift, AND, or zero_extract, we can do better. */
9851 static rtx
9853 const_rtx known_x ATTRIBUTE_UNUSED,
9854 machine_mode known_mode ATTRIBUTE_UNUSED,
9857 {
9858 rtx tem;
9861 /* If X is a register whose nonzero bits value is current, use it.
9862 Otherwise, if X is a register whose value we can find, use that
9863 value. Otherwise, use the previously-computed global nonzero bits
9864 for this register. */
9878 && !REGNO_REG_SET_P
9881 {
9885 /* We don't know anything about the upper bits. */
9890 }
9895 {
9901 }
9903 {
9907 /* We don't know anything about the upper bits. */
9911 }
9914 }
9916 /* Return the number of bits at the high-order end of X that are known to
9917 be equal to the sign bit. X will be used in mode MODE; if MODE is
9918 VOIDmode, X will be used in its own mode. The returned value will always
9919 be between 1 and the number of bits in MODE. */
9921 static rtx
9923 const_rtx known_x ATTRIBUTE_UNUSED,
9924 machine_mode known_mode
9925 ATTRIBUTE_UNUSED,
9928 {
9929 rtx tem;
9942 && !REGNO_REG_SET_P
9945 {
9948 }
9959 }
9960 \f
9961 /* Return the number of "extended" bits there are in X, when interpreted
9962 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9963 unsigned quantities, this is the number of high-order zero bits.
9964 For signed quantities, this is the number of copies of the sign bit
9965 minus 1. In both case, this function returns the number of "spare"
9966 bits. For example, if two quantities for which this function returns
9967 at least 1 are added, the addition is known not to overflow.
9969 This function will always return 0 unless called during combine, which
9970 implies that it must be called from a define_split. */
9972 unsigned int
9974 {
9984 }
9986 /* This function is called from `simplify_shift_const' to merge two
9987 outer operations. Specifically, we have already found that we need
9988 to perform operation *POP0 with constant *PCONST0 at the outermost
9989 position. We would now like to also perform OP1 with constant CONST1
9990 (with *POP0 being done last).
9992 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9993 the resulting operation. *PCOMP_P is set to 1 if we would need to
9994 complement the innermost operand, otherwise it is unchanged.
9996 MODE is the mode in which the operation will be done. No bits outside
9997 the width of this mode matter. It is assumed that the width of this mode
9998 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10000 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10001 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10002 result is simply *PCONST0.
10004 If the resulting operation cannot be expressed as one operation, we
10005 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10007 static int
10008 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10009 {
10016 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10020 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10021 if OP0 is SET. */
10030 {
10032 {
10050 }
10051 }
10053 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10057 /* If the two constants aren't the same, we can't do anything. The
10058 remaining six cases can all be done. */
10062 else
10064 {
10067 /* (a & b) | b == b */
10070 /* (a ^ b) | b == a | b */
10071 {;}
10076 /* (a & b) ^ b == (~a) & b */
10079 /* (a | b) ^ b == a & ~b */
10085 /* (a | b) & b == b */
10088 /* (a ^ b) & b) == (~a) & b */
10093 }
10095 /* Check for NO-OP cases. */
10108 /* ??? Slightly redundant with the above mask, but not entirely.
10109 Moving this above means we'd have to sign-extend the mode mask
10110 for the final test. */
10115 }
10116 \f
10117 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10118 the shift in. The original shift operation CODE is performed on OP in
10119 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10120 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10121 result of the shift is subject to operation OUTER_CODE with operand
10122 OUTER_CONST. */
10124 static machine_mode
10128 {
10133 /* In general we can't perform in wider mode for right shift and rotate. */
10135 {
10137 /* We can still widen if the bits brought in from the left are identical
10138 to the sign bit of ORIG_MODE. */
10146 /* Similarly here but with zero bits. */
10151 /* We can also widen if the bits brought in will be masked off. This
10152 operation is performed in ORIG_MODE. */
10154 {
10160 }
10161 /* fall through */
10171 }
10172 }
10174 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10175 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10176 if we cannot simplify it. Otherwise, return a simplified value.
10178 The shift is normally computed in the widest mode we find in VAROP, as
10179 long as it isn't a different number of words than RESULT_MODE. Exceptions
10180 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10182 static rtx
10185 {
10191 unsigned int mode_words
10193 /* We form (outer_op (code varop count) (outer_const)). */
10199 /* Make sure and truncate the "natural" shift on the way in. We don't
10200 want to do this inside the loop as it makes it more difficult to
10201 combine shifts. */
10205 /* If we were given an invalid count, don't do anything except exactly
10206 what was requested. */
10213 /* Unless one of the branches of the `if' in this loop does a `continue',
10214 we will `break' the loop after the `if'. */
10217 {
10218 /* If we have an operand of (clobber (const_int 0)), fail. */
10222 /* Convert ROTATERT to ROTATE. */
10224 {
10229 else
10231 }
10236 /* Handle cases where the count is greater than the size of the mode
10237 minus 1. For ASHIFT, use the size minus one as the count (this can
10238 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10239 take the count modulo the size. For other shifts, the result is
10240 zero.
10242 Since these shifts are being produced by the compiler by combining
10243 multiple operations, each of which are defined, we know what the
10244 result is supposed to be. */
10247 {
10252 else
10253 {
10254 /* We can't simply return zero because there may be an
10255 outer op. */
10259 }
10260 }
10262 /* If we discovered we had to complement VAROP, leave. Making a NOT
10263 here would cause an infinite loop. */
10267 /* An arithmetic right shift of a quantity known to be -1 or 0
10268 is a no-op. */
10272 {
10275 }
10277 /* If we are doing an arithmetic right shift and discarding all but
10278 the sign bit copies, this is equivalent to doing a shift by the
10279 bitsize minus one. Convert it into that shift because it will often
10280 allow other simplifications. */
10287 /* We simplify the tests below and elsewhere by converting
10288 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10289 `make_compound_operation' will convert it to an ASHIFTRT for
10290 those machines (such as VAX) that don't have an LSHIFTRT. */
10307 {
10314 {
10317 }
10321 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10322 minus the width of a smaller mode, we can do this with a
10323 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10330 {
10339 }
10343 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10344 the same number of words as what we've seen so far. Then store
10345 the widest mode in MODE. */
10351 == mode_words
10354 {
10359 }
10363 /* Some machines use MULT instead of ASHIFT because MULT
10364 is cheaper. But it is still better on those machines to
10365 merge two shifts into one. */
10368 {
10369 varop
10375 }
10379 /* Similar, for when divides are cheaper. */
10382 {
10383 varop
10389 }
10393 /* If we are extracting just the sign bit of an arithmetic
10394 right shift, that shift is not needed. However, the sign
10395 bit of a wider mode may be different from what would be
10396 interpreted as the sign bit in a narrower mode, so, if
10397 the result is narrower, don't discard the shift. */
10402 {
10405 }
10407 /* ... fall through ... */
10412 /* Here we have two nested shifts. The result is usually the
10413 AND of a new shift with a mask. We compute the result below. */
10420 {
10424 rtx mask_rtx;
10426 /* We have one common special case. We can't do any merging if
10427 the inner code is an ASHIFTRT of a smaller mode. However, if
10428 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10429 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10430 we can convert it to
10431 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10432 This simplifies certain SIGN_EXTEND operations. */
10436 {
10437 /* C3 has the low-order C1 bits zero. */
10449 }
10451 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10452 than C1 high-order bits equal to the sign bit, we can convert
10453 this to either an ASHIFT or an ASHIFTRT depending on the
10454 two counts.
10456 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10462 {
10466 {
10469 }
10472 }
10474 /* There are some cases we can't do. If CODE is ASHIFTRT,
10475 we can only do this if FIRST_CODE is also ASHIFTRT.
10477 We can't do the case when CODE is ROTATE and FIRST_CODE is
10478 ASHIFTRT.
10480 If the mode of this shift is not the mode of the outer shift,
10481 we can't do this if either shift is a right shift or ROTATE.
10483 Finally, we can't do any of these if the mode is too wide
10484 unless the codes are the same.
10486 Handle the case where the shift codes are the same
10487 first. */
10490 {
10499 }
10510 /* To compute the mask to apply after the shift, shift the
10511 nonzero bits of the inner shift the same way the
10512 outer shift will. */
10515 result_mode);
10517 mask_rtx
10521 /* Give up if we can't compute an outer operation to use. */
10529 /* If the shifts are in the same direction, we add the
10530 counts. Otherwise, we subtract them. */
10534 else
10537 /* If COUNT is positive, the new shift is usually CODE,
10538 except for the two exceptions below, in which case it is
10539 FIRST_CODE. If the count is negative, FIRST_CODE should
10540 always be used */
10550 }
10552 /* If we have (A << B << C) for any shift, we can convert this to
10553 (A << C << B). This wins if A is a constant. Only try this if
10554 B is not a constant. */
10559 {
10560 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10561 sure the result will be masked. See PR70222. */
10569 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10570 up outer sign extension (often left and right shift) is
10571 hardly more efficient than the original. See PR70429. */
10581 }
10588 /* Make this fit the case below. */
10595 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10596 with C the size of VAROP - 1 and the shift is logical if
10597 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10598 we have an (le X 0) operation. If we have an arithmetic shift
10599 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10600 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10608 {
10611 const0_rtx);
10617 }
10619 /* If we have (shift (logical)), move the logical to the outside
10620 to allow it to possibly combine with another logical and the
10621 shift to combine with another shift. This also canonicalizes to
10622 what a ZERO_EXTRACT looks like. Also, some machines have
10623 (and (shift)) insns. */
10626 /* We can't do this if we have (ashiftrt (xor)) and the
10627 constant has its sign bit set in shift_mode with shift_mode
10628 wider than result_mode. */
10632 shift_mode))
10640 {
10643 }
10645 /* If we can't do that, try to simplify the shift in each arm of the
10646 logical expression, make a new logical expression, and apply
10647 the inverse distributive law. This also can't be done for
10648 (ashiftrt (xor)) where we've widened the shift and the constant
10649 changes the sign bit. */
10654 shift_mode)))
10655 {
10667 }
10671 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10672 says that the sign bit can be tested, FOO has mode MODE, C is
10673 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10674 that may be nonzero. */
10684 {
10688 }
10692 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10693 than the number of bits in the mode is equivalent to A. */
10697 {
10701 }
10703 /* NEG commutes with ASHIFT since it is multiplication. Move the
10704 NEG outside to allow shifts to combine. */
10708 {
10711 }
10715 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10716 is one less than the number of bits in the mode is
10717 equivalent to (xor A 1). */
10724 {
10728 }
10730 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10731 that might be nonzero in BAR are those being shifted out and those
10732 bits are known zero in FOO, we can replace the PLUS with FOO.
10733 Similarly in the other operand order. This code occurs when
10734 we are computing the size of a variable-size array. */
10741 {
10744 }
10752 result_mode)))
10753 {
10756 }
10758 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10768 {
10771 }
10773 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10774 signbit', and attempt to change the PLUS to an XOR and move it to
10775 the outer operation as is done above in the AND/IOR/XOR case
10776 leg for shift(logical). See details in logical handling above
10777 for reasoning in doing so. */
10788 {
10791 }
10796 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10797 with C the size of VAROP - 1 and the shift is logical if
10798 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10799 we have a (gt X 0) operation. If the shift is arithmetic with
10800 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10801 we have a (neg (gt X 0)) operation. */
10810 {
10813 const0_rtx);
10819 }
10823 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10824 if the truncate does not affect the value. */
10831 {
10834 varop_inner
10837 GEN_INT
10842 }
10847 }
10850 }
10855 /* We have now finished analyzing the shift. The result should be
10856 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10857 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10858 to the result of the shift. OUTER_CONST is the relevant constant,
10859 but we must turn off all bits turned off in the shift. */
10867 /* Make a SUBREG if necessary. If we can't make it, fail. */
10872 /* If we have an outer operation and we just made a shift, it is
10873 possible that we could have simplified the shift were it not
10874 for the outer operation. So try to do the simplification
10875 recursively. */
10879 else
10885 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10886 turn off all the bits that the shift would have turned off. */
10891 /* Do the remainder of the processing in RESULT_MODE. */
10894 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10895 operation. */
10900 {
10908 {
10909 /* This means that we have determined that the result is
10910 equivalent to a constant. This should be rare. */
10913 }
10916 else
10919 }
10922 }
10924 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10925 The result of the shift is RESULT_MODE. If we cannot simplify it,
10926 return X or, if it is NULL, synthesize the expression with
10927 simplify_gen_binary. Otherwise, return a simplified value.
10929 The shift is normally computed in the widest mode we find in VAROP, as
10930 long as it isn't a different number of words than RESULT_MODE. Exceptions
10931 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10933 static rtx
10936 {
10946 }
10948 \f
10949 /* A subroutine of recog_for_combine. See there for arguments and
10950 return value. */
10952 static int
10954 {
10956 rtx pat_without_clobbers;
10964 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10965 we use to indicate that something didn't match. If we find such a
10966 thing, force rejection. */
10980 {
10983 else
10986 }
10988 /* If it isn't, there is the possibility that we previously had an insn
10989 that clobbered some register as a side effect, but the combined
10990 insn doesn't need to do that. So try once more without the clobbers
10991 unless this represents an ASM insn. */
10995 {
11000 {
11003 pos++;
11004 }
11014 {
11017 else
11020 }
11021 }
11028 /* Recognize all noop sets, these will be killed by followup pass. */
11032 /* If we had any clobbers to add, make a new pattern than contains
11033 them. Then check to make sure that all of them are dead. */
11035 {
11045 else
11052 {
11057 {
11061 }
11062 }
11064 }
11068 {
11075 /* Allow targets to reject combined insn. */
11077 {
11080 dump_file);
11082 /* Callers expect recog_for_combine to strip
11083 clobbers from the pattern on failure. */
11088 }
11093 }
11099 }
11101 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11102 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11103 Return whether anything was so changed. */
11105 static bool
11107 {
11112 {
11121 {
11130 }
11136 {
11139 }
11140 else
11148 }
11151 }
11153 /* Like recog, but we receive the address of a pointer to a new pattern.
11154 We try to match the rtx that the pointer points to.
11155 If that fails, we may try to modify or replace the pattern,
11156 storing the replacement into the same pointer object.
11158 Modifications include deletion or addition of CLOBBERs. If the
11159 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11160 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11161 (and undo if that fails).
11163 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11164 the CLOBBERs are placed.
11166 The value is the final insn code from the pattern ultimately matched,
11167 or -1. */
11169 static int
11171 {
11183 {
11186 {
11190 }
11191 }
11194 {
11199 }
11202 }
11203 \f
11204 /* Like gen_lowpart_general but for use by combine. In combine it
11205 is not possible to create any new pseudoregs. However, it is
11206 safe to create invalid memory addresses, because combine will
11207 try to recognize them and all they will do is make the combine
11208 attempt fail.
11210 If for some reason this cannot do its job, an rtx
11211 (clobber (const_int 0)) is returned.
11212 An insn containing that will not be recognized. */
11214 static rtx
11216 {
11220 rtx result;
11225 /* We can only support MODE being wider than a word if X is a
11226 constant integer or has a mode the same size. */
11231 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11232 won't know what to do. So we will strip off the SUBREG here and
11233 process normally. */
11235 {
11238 /* For use in case we fall down into the address adjustments
11239 further below, we need to adjust the known mode and size of
11240 x; imode and isize, since we just adjusted x. */
11247 }
11255 {
11258 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11259 address. */
11264 /* If we want to refer to something bigger than the original memref,
11265 generate a paradoxical subreg instead. That will force a reload
11266 of the original memref X. */
11273 /* Adjust the address so that the address-after-the-data is
11274 unchanged. */
11279 }
11281 /* If X is a comparison operator, rewrite it in a new mode. This
11282 probably won't match, but may allow further simplifications. */
11286 /* If we couldn't simplify X any other way, just enclose it in a
11287 SUBREG. Normally, this SUBREG won't match, but some patterns may
11288 include an explicit SUBREG or we may simplify it further in combine. */
11289 else
11290 {
11291 rtx res;
11294 {
11299 }
11303 }
11305 fail:
11307 }
11308 \f
11309 /* Try to simplify a comparison between OP0 and a constant OP1,
11310 where CODE is the comparison code that will be tested, into a
11311 (CODE OP0 const0_rtx) form.
11313 The result is a possibly different comparison code to use.
11314 *POP1 may be updated. */
11316 static enum rtx_code
11319 {
11323 /* Get the constant we are comparing against and turn off all bits
11324 not on in our mode. */
11328 /* If we are comparing against a constant power of two and the value
11329 being compared can only have that single bit nonzero (e.g., it was
11330 `and'ed with that bit), we can replace this with a comparison
11331 with zero. */
11339 {
11342 }
11344 /* Similarly, if we are comparing a value known to be either -1 or
11345 0 with -1, change it to the opposite comparison against zero. */
11350 {
11353 }
11355 /* Do some canonicalizations based on the comparison code. We prefer
11356 comparisons against zero and then prefer equality comparisons.
11357 If we can reduce the size of a constant, we will do that too. */
11359 {
11361 /* < C is equivalent to <= (C - 1) */
11363 {
11366 /* ... fall through to LE case below. */
11367 }
11368 else
11372 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11374 {
11377 }
11379 /* If we are doing a <= 0 comparison on a value known to have
11380 a zero sign bit, we can replace this with == 0. */
11390 /* >= C is equivalent to > (C - 1). */
11392 {
11395 /* ... fall through to GT below. */
11396 }
11397 else
11401 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11403 {
11406 }
11408 /* If we are doing a > 0 comparison on a value known to have
11409 a zero sign bit, we can replace this with != 0. */
11419 /* < C is equivalent to <= (C - 1). */
11421 {
11424 /* ... fall through ... */
11425 }
11426 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11430 {
11434 }
11435 else
11439 /* unsigned <= 0 is equivalent to == 0 */
11442 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11446 {
11449 }
11453 /* >= C is equivalent to > (C - 1). */
11455 {
11458 /* ... fall through ... */
11459 }
11461 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11465 {
11469 }
11470 else
11474 /* unsigned > 0 is equivalent to != 0 */
11477 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11481 {
11484 }
11489 }
11493 }
11494 \f
11495 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11496 comparison code that will be tested.
11498 The result is a possibly different comparison code to use. *POP0 and
11499 *POP1 may be updated.
11501 It is possible that we might detect that a comparison is either always
11502 true or always false. However, we do not perform general constant
11503 folding in combine, so this knowledge isn't useful. Such tautologies
11504 should have been detected earlier. Hence we ignore all such cases. */
11506 static enum rtx_code
11508 {
11515 /* Try a few ways of applying the same transformation to both operands. */
11517 {
11518 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11519 so check specially. */
11535 - (GET_MODE_PRECISION
11537 {
11540 }
11542 /* If both operands are the same constant shift, see if we can ignore the
11543 shift. We can if the shift is a rotate or if the bits shifted out of
11544 this shift are known to be zero for both inputs and if the type of
11545 comparison is compatible with the shift. */
11558 {
11571 else
11573 }
11575 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11576 SUBREGs are of the same mode, and, in both cases, the AND would
11577 be redundant if the comparison was done in the narrower mode,
11578 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11579 and the operand's possibly nonzero bits are 0xffffff01; in that case
11580 if we only care about QImode, we don't need the AND). This case
11581 occurs if the output mode of an scc insn is not SImode and
11582 STORE_FLAG_VALUE == 1 (e.g., the 386).
11584 Similarly, check for a case where the AND's are ZERO_EXTEND
11585 operations from some narrower mode even though a SUBREG is not
11586 present. */
11591 {
11608 {
11612 /* The resulting comparison is always unsigned since we masked
11613 off the original sign bit. */
11617 }
11624 {
11630 }
11634 }
11636 /* If both operands are NOT, we can strip off the outer operation
11637 and adjust the comparison code for swapped operands; similarly for
11638 NEG, except that this must be an equality comparison. */
11644 else
11646 }
11648 /* If the first operand is a constant, swap the operands and adjust the
11649 comparison code appropriately, but don't do this if the second operand
11650 is already a constant integer. */
11652 {
11655 }
11657 /* We now enter a loop during which we will try to simplify the comparison.
11658 For the most part, we only are concerned with comparisons with zero,
11659 but some things may really be comparisons with zero but not start
11660 out looking that way. */
11663 {
11670 HOST_WIDE_INT const_op;
11672 /* We only want to handle integral modes. This catches VOIDmode,
11673 CCmode, and the floating-point modes. An exception is that we
11674 can handle VOIDmode if OP0 is a COMPARE or a comparison
11675 operation. */
11682 /* Try to simplify the compare to constant, possibly changing the
11683 comparison op, and/or changing op1 to zero. */
11687 /* Compute some predicates to simplify code below. */
11694 /* If this is a sign bit comparison and we can do arithmetic in
11695 MODE, say that we will only be needing the sign bit of OP0. */
11698 HOST_WIDE_INT_1U
11702 /* Now try cases based on the opcode of OP0. If none of the cases
11703 does a "continue", we exit this loop immediately after the
11704 switch. */
11707 {
11709 /* If we are extracting a single bit from a variable position in
11710 a constant that has only a single bit set and are comparing it
11711 with zero, we can convert this into an equality comparison
11712 between the position and the location of the single bit. */
11713 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11714 have already reduced the shift count modulo the word size. */
11720 {
11728 /* Result is nonzero iff shift count is equal to I. */
11731 }
11733 /* ... fall through ... */
11738 {
11741 }
11745 /* If testing for equality, we can take the NOT of the constant. */
11748 {
11752 }
11754 /* If just looking at the sign bit, reverse the sense of the
11755 comparison. */
11757 {
11761 }
11765 /* If testing for equality, we can take the NEG of the constant. */
11768 {
11772 }
11774 /* The remaining cases only apply to comparisons with zero. */
11778 /* When X is ABS or is known positive,
11779 (neg X) is < 0 if and only if X != 0. */
11787 {
11791 }
11793 /* If we have NEG of something whose two high-order bits are the
11794 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11796 {
11800 }
11804 /* If we are testing equality and our count is a constant, we
11805 can perform the inverse operation on our RHS. */
11809 {
11813 }
11815 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11816 a particular bit. Convert it to an AND of a constant of that
11817 bit. This will be converted into a ZERO_EXTRACT. */
11821 {
11823 (HOST_WIDE_INT_1U
11828 }
11830 /* Fall through. */
11833 /* ABS is ignorable inside an equality comparison with zero. */
11835 {
11838 }
11842 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11843 (compare FOO CONST) if CONST fits in FOO's mode and we
11844 are either testing inequality or have an unsigned
11845 comparison with ZERO_EXTEND or a signed comparison with
11846 SIGN_EXTEND. But don't do it if we don't have a compare
11847 insn of the given mode, since we'd have to revert it
11848 later on, and then we wouldn't know whether to sign- or
11849 zero-extend. */
11852 && ! unsigned_comparison_p
11856 {
11859 }
11863 /* Check for the case where we are comparing A - C1 with C2, that is
11865 (subreg:MODE (plus (A) (-C1))) op (C2)
11867 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11868 comparison in the wider mode. One of the following two conditions
11869 must be true in order for this to be valid:
11871 1. The mode extension results in the same bit pattern being added
11872 on both sides and the comparison is equality or unsigned. As
11873 C2 has been truncated to fit in MODE, the pattern can only be
11874 all 0s or all 1s.
11876 2. The mode extension results in the sign bit being copied on
11877 each side.
11879 The difficulty here is that we have predicates for A but not for
11880 (A - C1) so we need to check that C1 is within proper bounds so
11881 as to perturbate A as little as possible. */
11888 {
11897 /* (A - C1) zero-extends if it is positive and sign-extends
11898 if it is negative, C2 both zero- and sign-extends. */
11902 /* (A - C1) sign-extends if it is positive and 1-extends
11903 if it is negative, C2 both sign- and 1-extends. */
11910 /* (A - C1) always sign-extends, like C2. */
11914 {
11917 }
11918 }
11920 /* If the inner mode is narrower and we are extracting the low part,
11921 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11925 else
11928 /* ... fall through ... */
11938 {
11941 }
11945 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11946 this for equality comparisons due to pathological cases involving
11947 overflows. */
11951 {
11955 }
11957 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11960 {
11964 }
11968 /* We used to optimize signed comparisons against zero, but that
11969 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11970 arrive here as equality comparisons, or (GEU, LTU) are
11971 optimized away. No need to special-case them. */
11973 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11974 (eq B (minus A C)), whichever simplifies. We can only do
11975 this for equality comparisons due to pathological cases involving
11976 overflows. */
11980 {
11984 }
11989 {
11993 }
11995 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11996 of bits in X minus 1, is one iff X > 0. */
12001 {
12005 }
12009 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12010 if C is zero or B is a constant. */
12014 {
12018 }
12026 /* We can't do anything if OP0 is a condition code value, rather
12027 than an actual data value. */
12033 /* Get the two operands being compared. */
12036 else
12039 /* Check for the cases where we simply want the result of the
12040 earlier test or the opposite of that result. */
12044 {
12048 else
12052 {
12057 }
12058 }
12062 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12063 iff X <= 0. */
12067 {
12071 }
12075 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12076 will be converted to a ZERO_EXTRACT later. */
12080 {
12085 }
12087 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12088 zero and X is a comparison and C1 and C2 describe only bits set
12089 in STORE_FLAG_VALUE, we can compare with X. */
12097 {
12104 {
12107 }
12108 }
12110 /* If we are doing an equality comparison of an AND of a bit equal
12111 to the sign bit, replace this with a LT or GE comparison of
12112 the underlying value. */
12119 {
12123 }
12125 /* If this AND operation is really a ZERO_EXTEND from a narrower
12126 mode, the constant fits within that mode, and this is either an
12127 equality or unsigned comparison, try to do this comparison in
12128 the narrower mode.
12130 Note that in:
12132 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12133 -> (ne:DI (reg:SI 4) (const_int 0))
12135 unless TRULY_NOOP_TRUNCATION allows it or the register is
12136 known to hold a value of the required mode the
12137 transformation is invalid. */
12145 {
12148 }
12150 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12151 fits in both M1 and M2 and the SUBREG is either paradoxical
12152 or represents the low part, permute the SUBREG and the AND
12153 and try again. */
12156 {
12159 /* Require an integral mode, to avoid creating something like
12160 (AND:SF ...). */
12162 /* It is unsafe to commute the AND into the SUBREG if the
12163 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12164 not defined. As originally written the upper bits
12165 have a defined value due to the AND operation.
12166 However, if we commute the AND inside the SUBREG then
12167 they no longer have defined values and the meaning of
12168 the code has been changed.
12169 Also C1 should not change value in the smaller mode,
12170 see PR67028 (a positive C1 can become negative in the
12171 smaller mode, so that the AND does no longer mask the
12172 upper bits). */
12173 && ((WORD_REGISTER_OPERATIONS
12185 {
12191 }
12192 }
12194 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12198 {
12203 }
12205 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12206 (eq (and (lshiftrt X) 1) 0).
12207 Also handle the case where (not X) is expressed using xor. */
12211 {
12221 == HOST_WIDE_INT_1U
12223 {
12224 op0
12229 }
12230 }
12234 /* If we have (compare (ashift FOO N) (const_int C)) and
12235 the high order N bits of FOO (N+1 if an inequality comparison)
12236 are known to be zero, we can do this by comparing FOO with C
12237 shifted right N bits so long as the low-order N bits of C are
12238 zero. */
12250 {
12251 /* We must perform a logical shift, not an arithmetic one,
12252 as we want the top N bits of C to be zero. */
12259 }
12261 /* If we are doing a sign bit comparison, it means we are testing
12262 a particular bit. Convert it to the appropriate AND. */
12265 {
12267 (HOST_WIDE_INT_1U
12272 }
12274 /* If this an equality comparison with zero and we are shifting
12275 the low bit to the sign bit, we can convert this to an AND of the
12276 low-order bit. */
12280 {
12283 }
12287 /* If this is an equality comparison with zero, we can do this
12288 as a logical shift, which might be much simpler. */
12291 {
12296 }
12298 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12299 do the comparison in a narrower mode. */
12309 {
12312 }
12314 /* Likewise if OP0 is a PLUS of a sign extension with a
12315 constant, which is usually represented with the PLUS
12316 between the shifts. */
12328 {
12336 new_const);
12338 }
12340 /* ... fall through ... */
12342 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12343 the low order N bits of FOO are known to be zero, we can do this
12344 by comparing FOO with C shifted left N bits so long as no
12345 overflow occurs. Even if the low order N bits of FOO aren't known
12346 to be zero, if the comparison is >= or < we can use the same
12347 optimization and for > or <= by setting all the low
12348 order N bits in the comparison constant. */
12359 {
12360 unsigned HOST_WIDE_INT low_bits
12362 & ((HOST_WIDE_INT_1U
12365 {
12366 /* If the shift was logical, then we must make the condition
12367 unsigned. */
12375 const_op
12380 }
12381 }
12383 /* If we are using this shift to extract just the sign bit, we
12384 can replace this with an LT or GE comparison. */
12389 {
12393 }
12398 }
12401 }
12403 /* Now make any compound operations involved in this comparison. Then,
12404 check for an outmost SUBREG on OP0 that is not doing anything or is
12405 paradoxical. The latter transformation must only be performed when
12406 it is known that the "extra" bits will be the same in op0 and op1 or
12407 that they don't matter. There are three cases to consider:
12409 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12410 care bits and we can assume they have any convenient value. So
12411 making the transformation is safe.
12413 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12414 In this case the upper bits of op0 are undefined. We should not make
12415 the simplification in that case as we do not know the contents of
12416 those bits.
12418 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12419 UNKNOWN. In that case we know those bits are zeros or ones. We must
12420 also be sure that they are the same as the upper bits of op1.
12422 We can never remove a SUBREG for a non-equality comparison because
12423 the sign bit is in a different place in the underlying object. */
12432 {
12434 {
12435 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12436 implemented. */
12438 {
12441 }
12442 }
12448 {
12454 }
12455 }
12457 /* We now do the opposite procedure: Some machines don't have compare
12458 insns in all modes. If OP0's mode is an integer mode smaller than a
12459 word and we can't do a compare in that mode, see if there is a larger
12460 mode for which we can do the compare. There are a number of cases in
12461 which we can use the wider mode. */
12471 {
12474 /* If this is a test for negative, we can make an explicit
12475 test of the sign bit. Test this first so we can use
12476 a paradoxical subreg to extend OP0. */
12480 {
12481 unsigned HOST_WIDE_INT sign
12488 }
12490 /* If the only nonzero bits in OP0 and OP1 are those in the
12491 narrower mode and this is an equality or unsigned comparison,
12492 we can use the wider mode. Similarly for sign-extended
12493 values, in which case it is true for all comparisons. */
12510 {
12511 /* If OP0 is an AND and we don't have an AND in MODE either,
12512 make a new AND in the proper mode. */
12520 else
12521 {
12523 {
12526 }
12527 else
12528 {
12531 }
12533 }
12534 }
12535 }
12537 /* We may have changed the comparison operands. Re-canonicalize. */
12539 {
12542 }
12544 /* If this machine only supports a subset of valid comparisons, see if we
12545 can convert an unsupported one into a supported one. */
12552 }
12553 \f
12554 /* Utility function for record_value_for_reg. Count number of
12555 rtxs in X. */
12556 static int
12558 {
12565 {
12585 }
12596 }
12597 \f
12598 /* Utility function for following routine. Called when X is part of a value
12599 being stored into last_set_value. Sets last_set_table_tick
12600 for each register mentioned. Similar to mention_regs in cse.c */
12602 static void
12604 {
12610 {
12616 {
12619 }
12622 }
12626 {
12627 /* Check for identical subexpressions. If x contains
12628 identical subexpression we only have to traverse one of
12629 them. */
12631 {
12632 /* Note that at this point x1 has already been
12633 processed. */
12637 /* If x0 and x1 are identical then there is no need to
12638 process x0. */
12642 /* If x0 is identical to a subexpression of x1 then while
12643 processing x1, x0 has already been processed. Thus we
12644 are done with x. */
12649 /* If x1 is identical to a subexpression of x0 then we
12650 still have to process the rest of x0. */
12653 {
12656 }
12657 }
12660 }
12664 }
12666 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12667 are saying that the register is clobbered and we no longer know its
12668 value. If INSN is zero, don't update reg_stat[].last_set; this is
12669 only permitted with VALUE also zero and is used to invalidate the
12670 register. */
12672 static void
12674 {
12680 /* If VALUE contains REG and we have a previous value for REG, substitute
12681 the previous value. */
12683 {
12684 rtx tem;
12686 /* Set things up so get_last_value is allowed to see anything set up to
12687 our insn. */
12691 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12692 it isn't going to be useful and will take a lot of time to process,
12693 so just use the CLOBBER. */
12696 {
12702 {
12703 /* If there are two or more occurrences of REG in VALUE,
12704 prevent the value from growing too much. */
12707 }
12710 }
12711 }
12713 /* For each register modified, show we don't know its value, that
12714 we don't know about its bitwise content, that its value has been
12715 updated, and that we don't know the location of the death of the
12716 register. */
12718 {
12730 }
12732 /* Mark registers that are being referenced in this value. */
12736 /* Now update the status of each register being set.
12737 If someone is using this register in this block, set this register
12738 to invalid since we will get confused between the two lives in this
12739 basic block. This makes using this register always invalid. In cse, we
12740 scan the table to invalidate all entries using this register, but this
12741 is too much work for us. */
12744 {
12750 else
12752 }
12754 /* The value being assigned might refer to X (like in "x++;"). In that
12755 case, we must replace it with (clobber (const_int 0)) to prevent
12756 infinite loops. */
12759 {
12763 }
12765 /* For the main register being modified, update the value, the mode, the
12766 nonzero bits, and the number of sign bit copies. */
12771 {
12779 rsp->last_set_sign_bit_copies
12781 }
12782 }
12784 /* Called via note_stores from record_dead_and_set_regs to handle one
12785 SET or CLOBBER in an insn. DATA is the instruction in which the
12786 set is occurring. */
12788 static void
12790 {
12797 {
12801 }
12804 {
12805 /* If we are setting the whole register, we know its value. Otherwise
12806 show that we don't know the value. We can handle SUBREG in
12807 some cases. */
12818 else
12820 }
12822 /* Ignore pushes, they clobber nothing. */
12825 }
12827 /* Update the records of when each REG was most recently set or killed
12828 for the things done by INSN. This is the last thing done in processing
12829 INSN in the combiner loop.
12831 We update reg_stat[], in particular fields last_set, last_set_value,
12832 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12833 last_death, and also the similar information mem_last_set (which insn
12834 most recently modified memory) and last_call_luid (which insn was the
12835 most recent subroutine call). */
12837 static void
12839 {
12840 rtx link;
12844 {
12847 {
12852 {
12857 }
12858 }
12861 }
12864 {
12865 hard_reg_set_iterator hrsi;
12867 {
12879 }
12883 /* We can't combine into a call pattern. Remember, though, that
12884 the return value register is set at this LUID. We could
12885 still replace a register with the return value from the
12886 wrong subroutine call! */
12888 }
12889 else
12891 }
12893 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12894 register present in the SUBREG, so for each such SUBREG go back and
12895 adjust nonzero and sign bit information of the registers that are
12896 known to have some zero/sign bits set.
12898 This is needed because when combine blows the SUBREGs away, the
12899 information on zero/sign bits is lost and further combines can be
12900 missed because of that. */
12902 static void
12904 {
12906 rtx set;
12914 {
12923 {
12926 }
12930 {
12933 }
12936 {
12939 }
12940 else
12942 }
12943 }
12945 /* Check if X, a register, is known to contain a value already
12946 truncated to MODE. In this case we can use a subreg to refer to
12947 the truncated value even though in the generic case we would need
12948 an explicit truncation. */
12950 static bool
12952 {
12964 }
12966 /* If X is a hard reg or a subreg record the mode that the register is
12967 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12968 to turn a truncate into a subreg using this information. Return true
12969 if traversing X is complete. */
12971 static bool
12973 {
12974 machine_mode truncated_mode;
12978 {
12989 }
12990 /* ??? For hard-regs we now record everything. We might be able to
12991 optimize this using last_set_mode. */
12994 else
13002 {
13005 }
13008 }
13010 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13011 the modes they are used in. This can help truning TRUNCATEs into
13012 SUBREGs. */
13014 static void
13016 {
13021 }
13023 /* Scan X for promoted SUBREGs. For each one found,
13024 note what it implies to the registers used in it. */
13026 static void
13028 {
13033 else
13034 {
13040 {
13050 }
13051 }
13052 }
13053 \f
13054 /* Verify that all the registers and memory references mentioned in *LOC are
13055 still valid. *LOC was part of a value set in INSN when label_tick was
13056 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13057 the invalid references with (clobber (const_int 0)) and return 1. This
13058 replacement is useful because we often can get useful information about
13059 the form of a value (e.g., if it was produced by a shift that always
13060 produces -1 or 0) even though we don't know exactly what registers it
13061 was produced from. */
13063 static int
13065 {
13072 {
13078 {
13081 /* If this is a pseudo-register that was only set once and not
13082 live at the beginning of the function, it is always valid. */
13086 && (!REGNO_REG_SET_P
13088 regno)))
13090 {
13094 }
13095 }
13098 }
13099 /* If this is a memory reference, make sure that there were no stores after
13100 it that might have clobbered the value. We don't have alias info, so we
13101 assume any store invalidates it. Moreover, we only have local UIDs, so
13102 we also assume that there were stores in the intervening basic blocks. */
13105 {
13109 }
13112 {
13114 {
13115 /* Check for identical subexpressions. If x contains
13116 identical subexpression we only have to traverse one of
13117 them. */
13119 {
13120 /* Note that at this point x0 has already been checked
13121 and found valid. */
13125 /* If x0 and x1 are identical then x is also valid. */
13129 /* If x1 is identical to a subexpression of x0 then
13130 while checking x0, x1 has already been checked. Thus
13131 it is valid and so as x. */
13136 /* If x0 is identical to a subexpression of x1 then x is
13137 valid iff the rest of x1 is valid. */
13140 return
13144 }
13149 }
13155 }
13157 /* If we haven't found a reason for it to be invalid, it is valid. */
13159 }
13161 /* Get the last value assigned to X, if known. Some registers
13162 in the value may be replaced with (clobber (const_int 0)) if their value
13163 is known longer known reliably. */
13165 static rtx
13167 {
13169 rtx value;
13172 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13173 then convert it to the desired mode. If this is a paradoxical SUBREG,
13174 we cannot predict what values the "extra" bits might have. */
13188 /* If we don't have a value, or if it isn't for this basic block and
13189 it's either a hard register, set more than once, or it's a live
13190 at the beginning of the function, return 0.
13192 Because if it's not live at the beginning of the function then the reg
13193 is always set before being used (is never used without being set).
13194 And, if it's set only once, and it's always set before use, then all
13195 uses must have the same last value, even if it's not from this basic
13196 block. */
13203 || REGNO_REG_SET_P
13207 /* If the value was set in a later insn than the ones we are processing,
13208 we can't use it even if the register was only set once. */
13213 /* If fewer bits were set than what we are asked for now, we cannot use
13214 the value. */
13219 /* If the value has all its registers valid, return it. */
13223 /* Otherwise, make a copy and replace any invalid register with
13224 (clobber (const_int 0)). If that fails for some reason, return 0. */
13231 }
13232 \f
13233 /* Return nonzero if expression X refers to a REG or to memory
13234 that is set in an instruction more recent than FROM_LUID. */
13236 static int
13238 {
13244 {
13248 #ifdef PUSH_ROUNDING
13249 /* Don't allow uses of the stack pointer to be moved,
13250 because we don't know whether the move crosses a push insn. */
13253 #endif
13255 {
13261 }
13263 }
13271 {
13273 {
13278 }
13282 }
13284 }
13285 \f
13286 /* Define three variables used for communication between the following
13287 routines. */
13292 /* Function called via note_stores from reg_dead_at_p.
13294 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13295 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13297 static void
13299 {
13309 }
13311 /* Return nonzero if REG is known to be dead at INSN.
13313 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13314 referencing REG, it is dead. If we hit a SET referencing REG, it is
13315 live. Otherwise, see if it is live or dead at the start of the basic
13316 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13317 must be assumed to be always live. */
13319 static int
13321 {
13322 basic_block block;
13325 /* Set variables for reg_dead_at_p_1. */
13331 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13332 we allow the machine description to decide whether use-and-clobber
13333 patterns are OK. */
13335 {
13339 }
13341 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13342 beginning of basic block. */
13345 {
13347 {
13357 }
13363 }
13365 /* Look at live-in sets for the basic block that we were in. */
13371 }
13372 \f
13373 /* Note hard registers in X that are used. */
13375 static void
13377 {
13383 {
13387 CASE_CONST_ANY:
13392 /* CC0 must die in the insn after it is set, so we don't need to take
13393 special note of it here. */
13398 /* If we are clobbering a MEM, mark any hard registers inside the
13399 address as used. */
13406 /* A hard reg in a wide mode may really be multiple registers.
13407 If so, mark all of them just like the first. */
13409 {
13410 /* None of this applies to the stack, frame or arg pointers. */
13412 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13420 }
13424 {
13425 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13426 the address. */
13438 }
13443 }
13445 /* Recursively scan the operands of this expression. */
13447 {
13451 {
13455 {
13460 }
13461 }
13462 }
13463 }
13464 \f
13465 /* Remove register number REGNO from the dead registers list of INSN.
13467 Return the note used to record the death, if there was one. */
13469 rtx
13471 {
13478 }
13480 /* For each register (hardware or pseudo) used within expression X, if its
13481 death is in an instruction with luid between FROM_LUID (inclusive) and
13482 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13483 list headed by PNOTES.
13485 That said, don't move registers killed by maybe_kill_insn.
13487 This is done when X is being merged by combination into TO_INSN. These
13488 notes will then be distributed as needed. */
13490 static void
13493 {
13499 {
13503 /* Don't move the register if it gets killed in between from and to. */
13512 {
13515 /* It is possible for the call above to return 0. This can occur
13516 when last_death points to I2 or I1 that we combined with.
13517 In that case make a new note.
13519 We must also check for the case where X is a hard register
13520 and NOTE is a death note for a range of hard registers
13521 including X. In that case, we must put REG_DEAD notes for
13522 the remaining registers in place of NOTE. */
13527 {
13536 }
13538 /* If we didn't find any note, or if we found a REG_DEAD note that
13539 covers only part of the given reg, and we have a multi-reg hard
13540 register, then to be safe we must check for REG_DEAD notes
13541 for each register other than the first. They could have
13542 their own REG_DEAD notes lying around. */
13549 {
13556 else
13562 }
13565 {
13568 }
13569 else
13571 }
13574 }
13577 {
13582 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13583 that accesses one word of a multi-word item, some
13584 piece of everything register in the expression is used by
13585 this insn, so remove any old death. */
13586 /* ??? So why do we test for equality of the sizes? */
13595 {
13598 }
13600 /* If this is some other SUBREG, we know it replaces the entire
13601 value, so use that as the destination. */
13605 /* If this is a MEM, adjust deaths of anything used in the address.
13606 For a REG (the only other possibility), the entire value is
13607 being replaced so the old value is not used in this insn. */
13613 }
13622 {
13624 {
13629 }
13632 }
13633 }
13634 \f
13635 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13636 pattern of an insn. X must be a REG. */
13638 static int
13640 {
13644 {
13646 rtx target;
13653 else
13670 }
13678 }
13679 \f
13680 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13681 as appropriate. I3 and I2 are the insns resulting from the combination
13682 insns including FROM (I2 may be zero).
13684 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13685 not need REG_DEAD notes because they are being substituted for. This
13686 saves searching in the most common cases.
13688 Each note in the list is either ignored or placed on some insns, depending
13689 on the type of note. */
13691 static void
13694 {
13696 rtx tem_note;
13700 {
13705 {
13708 /* Doesn't matter much where we put this, as long as it's somewhere.
13709 It is preferable to keep these notes on branches, which is most
13710 likely to be i3. */
13717 else
13718 {
13721 }
13725 /* These notes must remain with the call or trapping instruction. */
13730 else
13731 {
13737 /* ??? Otherwise assume we've combined things such that we
13738 can now prove that the instructions can't trap. Drop the
13739 note in this case. */
13740 }
13744 /* ??? How to distribute between i3-i1. Assume i3 contains the
13745 entire adjustment. Assert i3 contains at least some adjust. */
13747 {
13749 /* fixup_args_size_notes looks at REG_NORETURN note,
13750 so ensure the note is placed there first. */
13752 {
13756 {
13762 }
13763 }
13765 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13766 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13769 && !ACCUMULATE_OUTGOING_ARGS
13771 }
13778 /* These notes must remain with the call. It should not be
13779 possible for both I2 and I3 to be a call. */
13782 else
13783 {
13786 }
13790 /* Any clobbers for i3 may still exist, and so we must process
13791 REG_UNUSED notes from that insn.
13793 Any clobbers from i2 or i1 can only exist if they were added by
13794 recog_for_combine. In that case, recog_for_combine created the
13795 necessary REG_UNUSED notes. Trying to keep any original
13796 REG_UNUSED notes from these insns can cause incorrect output
13797 if it is for the same register as the original i3 dest.
13798 In that case, we will notice that the register is set in i3,
13799 and then add a REG_UNUSED note for the destination of i3, which
13800 is wrong. However, it is possible to have REG_UNUSED notes from
13801 i2 or i1 for register which were both used and clobbered, so
13802 we keep notes from i2 or i1 if they will turn into REG_DEAD
13803 notes. */
13805 /* If this register is set or clobbered in I3, put the note there
13806 unless there is one already. */
13808 {
13816 }
13817 /* Otherwise, if this register is used by I3, then this register
13818 now dies here, so we must put a REG_DEAD note here unless there
13819 is one already. */
13825 {
13828 }
13834 /* These notes say something about results of an insn. We can
13835 only support them if they used to be on I3 in which case they
13836 remain on I3. Otherwise they are ignored.
13838 If the note refers to an expression that is not a constant, we
13839 must also ignore the note since we cannot tell whether the
13840 equivalence is still true. It might be possible to do
13841 slightly better than this (we only have a problem if I2DEST
13842 or I1DEST is present in the expression), but it doesn't
13843 seem worth the trouble. */
13851 /* These notes say something about how a register is used. They must
13852 be present on any use of the register in I2 or I3. */
13857 {
13860 else
13862 }
13867 /* This can show up in several ways -- either directly in the
13868 pattern, or hidden off in the constant pool with (or without?)
13869 a REG_EQUAL note. */
13870 /* ??? Ignore the without-reg_equal-note problem for now. */
13882 {
13885 else
13887 }
13889 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13890 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13891 there. */
13896 {
13903 }
13909 {
13917 }
13921 /* This note says something about the value of a register prior
13922 to the execution of an insn. It is too much trouble to see
13923 if the note is still correct in all situations. It is better
13924 to simply delete it. */
13928 /* If we replaced the right hand side of FROM_INSN with a
13929 REG_EQUAL note, the original use of the dying register
13930 will not have been combined into I3 and I2. In such cases,
13931 FROM_INSN is guaranteed to be the first of the combined
13932 instructions, so we simply need to search back before
13933 FROM_INSN for the previous use or set of this register,
13934 then alter the notes there appropriately.
13936 If the register is used as an input in I3, it dies there.
13937 Similarly for I2, if it is nonzero and adjacent to I3.
13939 If the register is not used as an input in either I3 or I2
13940 and it is not one of the registers we were supposed to eliminate,
13941 there are two possibilities. We might have a non-adjacent I2
13942 or we might have somehow eliminated an additional register
13943 from a computation. For example, we might have had A & B where
13944 we discover that B will always be zero. In this case we will
13945 eliminate the reference to A.
13947 In both cases, we must search to see if we can find a previous
13948 use of A and put the death note there. */
13954 else
13955 {
13966 && !(i2mod
13968 i2mod_old_rhs)))
13973 /* If the new I2 sets the same register that is marked dead
13974 in the note, we do not know where to put the note.
13975 Give up. */
13978 }
13981 {
13985 {
13987 {
13991 }
13993 /* If the register is being set at TEM_INSN, see if that is all
13994 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13995 into a REG_UNUSED note instead. Don't delete sets to
13996 global register vars. */
14000 {
14011 ;
14013 /* Verify that it was the set, and not a clobber that
14014 modified the register.
14016 CC0 targets must be careful to maintain setter/user
14017 pairs. If we cannot delete the setter due to side
14018 effects, mark the user with an UNUSED note instead
14019 of deleting it. */
14023 && (!HAVE_cc0
14027 {
14028 /* Move the notes and links of TEM_INSN elsewhere.
14029 This might delete other dead insns recursively.
14030 First set the pattern to something that won't use
14031 any register. */
14045 /* Delete the setter too. */
14047 {
14060 }
14061 }
14062 else
14063 {
14066 /* If there isn't already a REG_UNUSED note, put one
14067 here. Do not place a REG_DEAD note, even if
14068 the register is also used here; that would not
14069 match the algorithm used in lifetime analysis
14070 and can cause the consistency check in the
14071 scheduler to fail. */
14076 }
14077 }
14081 {
14084 /* If we are doing a 3->2 combination, and we have a
14085 register which formerly died in i3 and was not used
14086 by i2, which now no longer dies in i3 and is used in
14087 i2 but does not die in i2, and place is between i2
14088 and i3, then we may need to move a link from place to
14089 i2. */
14091 && from_insn
14094 {
14098 }
14100 }
14104 }
14106 }
14108 /* If the register is set or already dead at PLACE, we needn't do
14109 anything with this note if it is still a REG_DEAD note.
14110 We check here if it is set at all, not if is it totally replaced,
14111 which is what `dead_or_set_p' checks, so also check for it being
14112 set partially. */
14115 {
14121 {
14122 /* Unless the register previously died in PLACE, clear
14123 last_death. [I no longer understand why this is
14124 being done.] */
14128 }
14129 else
14132 /* If this is a death note for a hard reg that is occupying
14133 multiple registers, ensure that we are still using all
14134 parts of the object. If we find a piece of the object
14135 that is unused, we must arrange for an appropriate REG_DEAD
14136 note to be added for it. However, we can't just emit a USE
14137 and tag the note to it, since the register might actually
14138 be dead; so we recourse, and the recursive call then finds
14139 the previous insn that used this register. */
14142 {
14151 {
14154 }
14157 {
14158 /* Put only REG_DEAD notes for pieces that are
14159 not already dead or set. */
14163 {
14170 {
14172 NULL_RTX);
14176 NULL_RTX);
14177 }
14182 {
14184 {
14188 }
14192 {
14195 }
14196 }
14197 }
14200 }
14201 }
14202 }
14206 /* Any other notes should not be present at this point in the
14207 compilation. */
14209 }
14212 {
14215 }
14219 }
14220 }
14221 \f
14222 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14223 I3, I2, and I1 to new locations. This is also called to add a link
14224 pointing at I3 when I3's destination is changed. */
14226 static void
14228 {
14232 {
14239 /* If the insn that this link points to is a NOTE, ignore it. */
14248 {
14251 {
14267 }
14270 }
14271 else
14281 /* A LOG_LINK is defined as being placed on the first insn that uses
14282 a register and points to the insn that sets the register. Start
14283 searching at the next insn after the target of the link and stop
14284 when we reach a set of the register or the end of the basic block.
14286 Note that this correctly handles the link that used to point from
14287 I3 to I2. Also note that not much searching is typically done here
14288 since most links don't point very far away. */
14297 {
14301 }
14304 {
14307 }
14311 /* If we found a place to put the link, place it there unless there
14312 is already a link to the same insn as LINK at that point. */
14315 {
14323 {
14327 /* Set added_links_insn to the earliest insn we added a
14328 link to. */
14332 }
14333 }
14334 }
14335 }
14336 \f
14337 /* Check for any register or memory mentioned in EQUIV that is not
14338 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14339 of EXPR where some registers may have been replaced by constants. */
14341 static bool
14343 {
14346 {
14351 }
14353 }
14354 \f
14355 DEBUG_FUNCTION void
14357 {
14358 fprintf
14360 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14362 }
14364 void
14366 {
14367 fprintf
14369 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14371 }
14372 \f
14373 /* Try combining insns through substitution. */
14374 static unsigned int
14376 {
14386 rebuild_jump_labels_after_combine
14389 /* Combining insns may have turned an indirect jump into a
14390 direct jump. Rebuild the JUMP_LABEL fields of jumping
14391 instructions. */
14393 {
14398 }
14402 }
14407 {
14417 };
14420 {
14424 {}
14426 /* opt_pass methods: */
14429 {
14431 }
14437 rtl_opt_pass *
14439 {
14441 }