1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return true if OP is either a i387 or SSE fp register.
21 (define_predicate "any_fp_register_operand"
22 (and (match_code "reg")
23 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
25 ;; Return true if OP is an i387 fp register.
26 (define_predicate "fp_register_operand"
27 (and (match_code "reg")
28 (match_test "STACK_REGNO_P (REGNO (op))")))
30 ;; True if the operand is a GENERAL class register.
31 (define_predicate "general_reg_operand"
32 (and (match_code "reg")
33 (match_test "GENERAL_REGNO_P (REGNO (op))")))
35 ;; True if the operand is a nonimmediate operand with GENERAL class register.
36 (define_predicate "nonimmediate_gr_operand"
37 (if_then_else (match_code "reg")
38 (match_test "GENERAL_REGNO_P (REGNO (op))")
39 (match_operand 0 "nonimmediate_operand")))
41 ;; True if the operand is a general operand with GENERAL class register.
42 (define_predicate "general_gr_operand"
43 (if_then_else (match_code "reg")
44 (match_test "GENERAL_REGNO_P (REGNO (op))")
45 (match_operand 0 "general_operand")))
47 ;; True if the operand is an MMX register.
48 (define_predicate "mmx_reg_operand"
49 (and (match_code "reg")
50 (match_test "MMX_REGNO_P (REGNO (op))")))
52 ;; True if the operand is an SSE register.
53 (define_predicate "sse_reg_operand"
54 (and (match_code "reg")
55 (match_test "SSE_REGNO_P (REGNO (op))")))
57 ;; True if the operand is an AVX-512 new register.
58 (define_predicate "ext_sse_reg_operand"
59 (and (match_code "reg")
60 (match_test "EXT_REX_SSE_REGNO_P (REGNO (op))")))
62 ;; Return true if op is a QImode register.
63 (define_predicate "any_QIreg_operand"
64 (and (match_code "reg")
65 (match_test "ANY_QI_REGNO_P (REGNO (op))")))
67 ;; Return true if op is one of QImode registers: %[abcd][hl].
68 (define_predicate "QIreg_operand"
69 (and (match_code "reg")
70 (match_test "QI_REGNO_P (REGNO (op))")))
72 ;; Return true if op is a QImode register operand other than %[abcd][hl].
73 (define_predicate "ext_QIreg_operand"
74 (and (match_test "TARGET_64BIT")
76 (not (match_test "QI_REGNO_P (REGNO (op))"))))
78 ;; Return true if op is the AX register.
79 (define_predicate "ax_reg_operand"
80 (and (match_code "reg")
81 (match_test "REGNO (op) == AX_REG")))
83 ;; Return true if op is the flags register.
84 (define_predicate "flags_reg_operand"
85 (and (match_code "reg")
86 (match_test "REGNO (op) == FLAGS_REG")))
88 ;; Match a DI, SI or HImode register for a zero_extract.
89 (define_special_predicate "ext_register_operand"
90 (and (match_operand 0 "register_operand")
91 (ior (and (match_test "TARGET_64BIT")
92 (match_test "GET_MODE (op) == DImode"))
93 (match_test "GET_MODE (op) == SImode")
94 (match_test "GET_MODE (op) == HImode"))))
96 ;; Match register operands, but include memory operands for TARGET_SSE_MATH.
97 (define_predicate "register_ssemem_operand"
99 (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
100 (match_operand 0 "nonimmediate_operand")
101 (match_operand 0 "register_operand")))
103 ;; Match nonimmediate operands, but exclude memory operands
104 ;; for TARGET_SSE_MATH if TARGET_MIX_SSE_I387 is not enabled.
105 (define_predicate "nonimm_ssenomem_operand"
107 (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
108 (not (match_test "TARGET_MIX_SSE_I387")))
109 (match_operand 0 "register_operand")
110 (match_operand 0 "nonimmediate_operand")))
112 ;; The above predicate, suitable for x87 arithmetic operators.
113 (define_predicate "x87nonimm_ssenomem_operand"
115 (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
116 (not (match_test "TARGET_MIX_SSE_I387 && X87_ENABLE_ARITH (mode)")))
117 (match_operand 0 "register_operand")
118 (match_operand 0 "nonimmediate_operand")))
120 ;; Match register operands, include memory operand for TARGET_SSE4_1.
121 (define_predicate "register_sse4nonimm_operand"
122 (if_then_else (match_test "TARGET_SSE4_1")
123 (match_operand 0 "nonimmediate_operand")
124 (match_operand 0 "register_operand")))
126 ;; Return true if VALUE is symbol reference
127 (define_predicate "symbol_operand"
128 (match_code "symbol_ref"))
130 ;; Return true if VALUE can be stored in a sign extended immediate field.
131 (define_predicate "x86_64_immediate_operand"
132 (match_code "const_int,symbol_ref,label_ref,const")
135 return immediate_operand (op, mode);
137 switch (GET_CODE (op))
141 HOST_WIDE_INT val = INTVAL (op);
142 return trunc_int_for_mode (val, SImode) == val;
145 /* TLS symbols are not constant. */
146 if (SYMBOL_REF_TLS_MODEL (op))
149 /* Load the external function address via the GOT slot. */
150 if (ix86_force_load_from_GOT_p (op))
153 /* For certain code models, the symbolic references are known to fit.
154 in CM_SMALL_PIC model we know it fits if it is local to the shared
155 library. Don't count TLS SYMBOL_REFs here, since they should fit
156 only if inside of UNSPEC handled below. */
157 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
158 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
161 /* For certain code models, the code is near as well. */
162 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
163 || ix86_cmodel == CM_KERNEL);
166 /* We also may accept the offsetted memory references in certain
168 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
169 switch (XINT (XEXP (op, 0), 1))
171 case UNSPEC_GOTPCREL:
173 case UNSPEC_GOTNTPOFF:
180 if (GET_CODE (XEXP (op, 0)) == PLUS)
182 rtx op1 = XEXP (XEXP (op, 0), 0);
183 rtx op2 = XEXP (XEXP (op, 0), 1);
185 if (ix86_cmodel == CM_LARGE)
187 if (!CONST_INT_P (op2))
190 HOST_WIDE_INT offset = INTVAL (op2);
191 if (trunc_int_for_mode (offset, SImode) != offset)
194 switch (GET_CODE (op1))
197 /* TLS symbols are not constant. */
198 if (SYMBOL_REF_TLS_MODEL (op1))
201 /* Load the external function address via the GOT slot. */
202 if (ix86_force_load_from_GOT_p (op1))
205 /* For CM_SMALL assume that latest object is 16MB before
206 end of 31bits boundary. We may also accept pretty
207 large negative constants knowing that all objects are
208 in the positive half of address space. */
209 if ((ix86_cmodel == CM_SMALL
210 || (ix86_cmodel == CM_MEDIUM
211 && !SYMBOL_REF_FAR_ADDR_P (op1)))
212 && offset < 16*1024*1024)
214 /* For CM_KERNEL we know that all object resist in the
215 negative half of 32bits address space. We may not
216 accept negative offsets, since they may be just off
217 and we may accept pretty large positive ones. */
218 if (ix86_cmodel == CM_KERNEL
224 /* These conditions are similar to SYMBOL_REF ones, just the
225 constraints for code models differ. */
226 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
227 && offset < 16*1024*1024)
229 if (ix86_cmodel == CM_KERNEL
235 switch (XINT (op1, 1))
256 ;; Return true if VALUE can be stored in the zero extended immediate field.
257 (define_predicate "x86_64_zext_immediate_operand"
258 (match_code "const_int,symbol_ref,label_ref,const")
260 switch (GET_CODE (op))
263 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
266 /* TLS symbols are not constant. */
267 if (SYMBOL_REF_TLS_MODEL (op))
270 /* Load the external function address via the GOT slot. */
271 if (ix86_force_load_from_GOT_p (op))
274 /* For certain code models, the symbolic references are known to fit. */
275 return (ix86_cmodel == CM_SMALL
276 || (ix86_cmodel == CM_MEDIUM
277 && !SYMBOL_REF_FAR_ADDR_P (op)));
280 /* For certain code models, the code is near as well. */
281 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
284 /* We also may accept the offsetted memory references in certain
286 if (GET_CODE (XEXP (op, 0)) == PLUS)
288 rtx op1 = XEXP (XEXP (op, 0), 0);
289 rtx op2 = XEXP (XEXP (op, 0), 1);
291 if (ix86_cmodel == CM_LARGE)
293 if (!CONST_INT_P (op2))
296 HOST_WIDE_INT offset = INTVAL (op2);
297 if (trunc_int_for_mode (offset, SImode) != offset)
300 switch (GET_CODE (op1))
303 /* TLS symbols are not constant. */
304 if (SYMBOL_REF_TLS_MODEL (op1))
307 /* Load the external function address via the GOT slot. */
308 if (ix86_force_load_from_GOT_p (op1))
311 /* For small code model we may accept pretty large positive
312 offsets, since one bit is available for free. Negative
313 offsets are limited by the size of NULL pointer area
314 specified by the ABI. */
315 if ((ix86_cmodel == CM_SMALL
316 || (ix86_cmodel == CM_MEDIUM
317 && !SYMBOL_REF_FAR_ADDR_P (op1)))
318 && offset > -0x10000)
320 /* ??? For the kernel, we may accept adjustment of
321 -0x10000000, since we know that it will just convert
322 negative address space to positive, but perhaps this
323 is not worthwhile. */
327 /* These conditions are similar to SYMBOL_REF ones, just the
328 constraints for code models differ. */
329 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
330 && offset > -0x10000)
346 ;; Return true if VALUE is a constant integer whose low and high words satisfy
347 ;; x86_64_immediate_operand.
348 (define_predicate "x86_64_hilo_int_operand"
349 (match_code "const_int,const_wide_int")
351 switch (GET_CODE (op))
354 return x86_64_immediate_operand (op, mode);
357 gcc_assert (CONST_WIDE_INT_NUNITS (op) == 2);
358 return (x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op, 0)),
360 && x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op,
369 ;; Return true if size of VALUE can be stored in a sign
370 ;; extended immediate field.
371 (define_predicate "x86_64_immediate_size_operand"
372 (and (match_code "symbol_ref")
373 (ior (not (match_test "TARGET_64BIT"))
374 (match_test "ix86_cmodel == CM_SMALL")
375 (match_test "ix86_cmodel == CM_KERNEL"))))
377 ;; Return true if OP is general operand representable on x86_64.
378 (define_predicate "x86_64_general_operand"
379 (if_then_else (match_test "TARGET_64BIT")
380 (ior (match_operand 0 "nonimmediate_operand")
381 (match_operand 0 "x86_64_immediate_operand"))
382 (match_operand 0 "general_operand")))
384 ;; Return true if OP's both words are general operands representable
386 (define_predicate "x86_64_hilo_general_operand"
387 (if_then_else (match_test "TARGET_64BIT")
388 (ior (match_operand 0 "nonimmediate_operand")
389 (match_operand 0 "x86_64_hilo_int_operand"))
390 (match_operand 0 "general_operand")))
392 ;; Return true if OP is non-VOIDmode general operand representable
393 ;; on x86_64. This predicate is used in sign-extending conversion
394 ;; operations that require non-VOIDmode immediate operands.
395 (define_predicate "x86_64_sext_operand"
396 (and (match_test "GET_MODE (op) != VOIDmode")
397 (match_operand 0 "x86_64_general_operand")))
399 ;; Return true if OP is non-VOIDmode general operand. This predicate
400 ;; is used in sign-extending conversion operations that require
401 ;; non-VOIDmode immediate operands.
402 (define_predicate "sext_operand"
403 (and (match_test "GET_MODE (op) != VOIDmode")
404 (match_operand 0 "general_operand")))
406 ;; Return true if OP is representable on x86_64 as zero-extended operand.
407 ;; This predicate is used in zero-extending conversion operations that
408 ;; require non-VOIDmode immediate operands.
409 (define_predicate "x86_64_zext_operand"
410 (if_then_else (match_test "TARGET_64BIT")
411 (ior (match_operand 0 "nonimmediate_operand")
412 (and (match_operand 0 "x86_64_zext_immediate_operand")
413 (match_test "GET_MODE (op) != VOIDmode")))
414 (match_operand 0 "nonimmediate_operand")))
416 ;; Return true if OP is general operand representable on x86_64
417 ;; as either sign extended or zero extended constant.
418 (define_predicate "x86_64_szext_general_operand"
419 (if_then_else (match_test "TARGET_64BIT")
420 (ior (match_operand 0 "nonimmediate_operand")
421 (match_operand 0 "x86_64_immediate_operand")
422 (match_operand 0 "x86_64_zext_immediate_operand"))
423 (match_operand 0 "general_operand")))
425 ;; Return true if OP is nonmemory operand representable on x86_64.
426 (define_predicate "x86_64_nonmemory_operand"
427 (if_then_else (match_test "TARGET_64BIT")
428 (ior (match_operand 0 "register_operand")
429 (match_operand 0 "x86_64_immediate_operand"))
430 (match_operand 0 "nonmemory_operand")))
432 ;; Return true if OP is nonmemory operand representable on x86_64.
433 (define_predicate "x86_64_szext_nonmemory_operand"
434 (if_then_else (match_test "TARGET_64BIT")
435 (ior (match_operand 0 "register_operand")
436 (match_operand 0 "x86_64_immediate_operand")
437 (match_operand 0 "x86_64_zext_immediate_operand"))
438 (match_operand 0 "nonmemory_operand")))
440 ;; Return true when operand is PIC expression that can be computed by lea
442 (define_predicate "pic_32bit_operand"
443 (match_code "const,symbol_ref,label_ref")
448 /* Rule out relocations that translate into 64bit constants. */
449 if (TARGET_64BIT && GET_CODE (op) == CONST)
452 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
454 if (GET_CODE (op) == UNSPEC
455 && (XINT (op, 1) == UNSPEC_GOTOFF
456 || XINT (op, 1) == UNSPEC_GOT))
460 return symbolic_operand (op, mode);
463 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
464 (define_predicate "x86_64_movabs_operand"
465 (and (match_operand 0 "nonmemory_operand")
466 (not (match_operand 0 "pic_32bit_operand"))))
468 ;; Return true if OP is either a symbol reference or a sum of a symbol
469 ;; reference and a constant.
470 (define_predicate "symbolic_operand"
471 (match_code "symbol_ref,label_ref,const")
473 switch (GET_CODE (op))
481 if (GET_CODE (op) == SYMBOL_REF
482 || GET_CODE (op) == LABEL_REF
483 || (GET_CODE (op) == UNSPEC
484 && (XINT (op, 1) == UNSPEC_GOT
485 || XINT (op, 1) == UNSPEC_GOTOFF
486 || XINT (op, 1) == UNSPEC_PCREL
487 || XINT (op, 1) == UNSPEC_GOTPCREL)))
489 if (GET_CODE (op) != PLUS
490 || !CONST_INT_P (XEXP (op, 1)))
494 if (GET_CODE (op) == SYMBOL_REF
495 || GET_CODE (op) == LABEL_REF)
497 /* Only @GOTOFF gets offsets. */
498 if (GET_CODE (op) != UNSPEC
499 || XINT (op, 1) != UNSPEC_GOTOFF)
502 op = XVECEXP (op, 0, 0);
503 if (GET_CODE (op) == SYMBOL_REF
504 || GET_CODE (op) == LABEL_REF)
513 ;; Return true if OP is a symbolic operand that resolves locally.
514 (define_predicate "local_symbolic_operand"
515 (match_code "const,label_ref,symbol_ref")
517 if (GET_CODE (op) == CONST
518 && GET_CODE (XEXP (op, 0)) == PLUS
519 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
520 op = XEXP (XEXP (op, 0), 0);
522 if (GET_CODE (op) == LABEL_REF)
525 if (GET_CODE (op) != SYMBOL_REF)
528 if (SYMBOL_REF_TLS_MODEL (op))
531 /* Dll-imported symbols are always external. */
532 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
534 if (SYMBOL_REF_LOCAL_P (op))
537 /* There is, however, a not insubstantial body of code in the rest of
538 the compiler that assumes it can just stick the results of
539 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
540 /* ??? This is a hack. Should update the body of the compiler to
541 always create a DECL an invoke targetm.encode_section_info. */
542 if (strncmp (XSTR (op, 0), internal_label_prefix,
543 internal_label_prefix_len) == 0)
549 ;; Test for a legitimate @GOTOFF operand.
551 ;; VxWorks does not impose a fixed gap between segments; the run-time
552 ;; gap can be different from the object-file gap. We therefore can't
553 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
554 ;; same segment as the GOT. Unfortunately, the flexibility of linker
555 ;; scripts means that we can't be sure of that in general, so assume
556 ;; that @GOTOFF is never valid on VxWorks.
557 (define_predicate "gotoff_operand"
558 (and (not (match_test "TARGET_VXWORKS_RTP"))
559 (match_operand 0 "local_symbolic_operand")))
561 ;; Test for various thread-local symbols.
562 (define_special_predicate "tls_symbolic_operand"
563 (and (match_code "symbol_ref")
564 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
566 (define_special_predicate "tls_modbase_operand"
567 (and (match_code "symbol_ref")
568 (match_test "op == ix86_tls_module_base ()")))
570 (define_predicate "tls_address_pattern"
571 (and (match_code "set,parallel,unspec,unspec_volatile")
572 (match_test "ix86_tls_address_pattern_p (op)")))
574 ;; Test for a pc-relative call operand
575 (define_predicate "constant_call_address_operand"
576 (match_code "symbol_ref")
578 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
580 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
585 ;; P6 processors will jump to the address after the decrement when %esp
586 ;; is used as a call operand, so they will execute return address as a code.
587 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
589 (define_predicate "call_register_no_elim_operand"
590 (match_operand 0 "register_operand")
593 op = SUBREG_REG (op);
595 if (!TARGET_64BIT && op == stack_pointer_rtx)
598 return register_no_elim_operand (op, mode);
601 ;; True for any non-virtual or eliminable register. Used in places where
602 ;; instantiation of such a register may cause the pattern to not be recognized.
603 (define_predicate "register_no_elim_operand"
604 (match_operand 0 "register_operand")
607 op = SUBREG_REG (op);
608 return !(op == arg_pointer_rtx
609 || op == frame_pointer_rtx
610 || IN_RANGE (REGNO (op),
611 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
614 ;; Similarly, but include the stack pointer. This is used to prevent esp
615 ;; from being used as an index reg.
616 (define_predicate "index_register_operand"
617 (match_operand 0 "register_operand")
620 op = SUBREG_REG (op);
621 if (reload_completed)
622 return REG_OK_FOR_INDEX_STRICT_P (op);
624 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
627 ;; Return false if this is any eliminable register. Otherwise general_operand.
628 (define_predicate "general_no_elim_operand"
629 (if_then_else (match_code "reg,subreg")
630 (match_operand 0 "register_no_elim_operand")
631 (match_operand 0 "general_operand")))
633 ;; Return false if this is any eliminable register. Otherwise
634 ;; register_operand or a constant.
635 (define_predicate "nonmemory_no_elim_operand"
636 (ior (match_operand 0 "register_no_elim_operand")
637 (match_operand 0 "immediate_operand")))
639 ;; Test for a valid operand for indirect branch.
640 (define_predicate "indirect_branch_operand"
641 (ior (match_operand 0 "register_operand")
642 (and (not (match_test "TARGET_X32"))
643 (match_operand 0 "memory_operand"))))
645 ;; Return true if OP is a memory operands that can be used in sibcalls.
646 ;; Since sibcall never returns, we can only use call-clobbered register
647 ;; as GOT base. Allow GOT slot here only with pseudo register as GOT
648 ;; base. Properly handle sibcall over GOT slot with *sibcall_GOT_32
649 ;; and *sibcall_value_GOT_32 patterns.
650 (define_predicate "sibcall_memory_operand"
651 (match_operand 0 "memory_operand")
656 if (GET_CODE (op) == PLUS && REG_P (XEXP (op, 0)))
658 int regno = REGNO (XEXP (op, 0));
659 if (!HARD_REGISTER_NUM_P (regno) || call_used_regs[regno])
662 if (GOT32_symbol_operand (op, VOIDmode))
669 ;; Return true if OP is a GOT memory operand.
670 (define_predicate "GOT_memory_operand"
671 (match_operand 0 "memory_operand")
674 return (GET_CODE (op) == CONST
675 && GET_CODE (XEXP (op, 0)) == UNSPEC
676 && XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL);
679 ;; Test for a valid operand for a call instruction.
680 ;; Allow constant call address operands in Pmode only.
681 (define_special_predicate "call_insn_operand"
682 (ior (match_test "constant_call_address_operand
683 (op, mode == VOIDmode ? mode : Pmode)")
684 (match_operand 0 "call_register_no_elim_operand")
685 (ior (and (not (match_test "TARGET_X32"))
686 (match_operand 0 "memory_operand"))
687 (and (match_test "TARGET_X32 && Pmode == DImode")
688 (match_operand 0 "GOT_memory_operand")))))
690 ;; Similarly, but for tail calls, in which we cannot allow memory references.
691 (define_special_predicate "sibcall_insn_operand"
692 (ior (match_test "constant_call_address_operand
693 (op, mode == VOIDmode ? mode : Pmode)")
694 (match_operand 0 "register_no_elim_operand")
695 (ior (and (not (match_test "TARGET_X32"))
696 (match_operand 0 "sibcall_memory_operand"))
697 (and (match_test "TARGET_X32 && Pmode == DImode")
698 (match_operand 0 "GOT_memory_operand")))))
700 ;; Return true if OP is a 32-bit GOT symbol operand.
701 (define_predicate "GOT32_symbol_operand"
702 (match_test "GET_CODE (op) == CONST
703 && GET_CODE (XEXP (op, 0)) == UNSPEC
704 && XINT (XEXP (op, 0), 1) == UNSPEC_GOT"))
706 ;; Match exactly zero.
707 (define_predicate "const0_operand"
708 (match_code "const_int,const_double,const_vector")
710 if (mode == VOIDmode)
711 mode = GET_MODE (op);
712 return op == CONST0_RTX (mode);
715 ;; Match one or a vector with all elements equal to one.
716 (define_predicate "const1_operand"
717 (match_code "const_int,const_double,const_vector")
719 if (mode == VOIDmode)
720 mode = GET_MODE (op);
721 return op == CONST1_RTX (mode);
725 (define_predicate "constm1_operand"
726 (and (match_code "const_int")
727 (match_test "op == constm1_rtx")))
729 ;; Match exactly eight.
730 (define_predicate "const8_operand"
731 (and (match_code "const_int")
732 (match_test "INTVAL (op) == 8")))
734 ;; Match exactly 128.
735 (define_predicate "const128_operand"
736 (and (match_code "const_int")
737 (match_test "INTVAL (op) == 128")))
739 ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
740 (define_predicate "const_32bit_mask"
741 (and (match_code "const_int")
742 (match_test "trunc_int_for_mode (INTVAL (op), DImode)
743 == (HOST_WIDE_INT) 0xffffffff")))
745 ;; Match 2, 4, or 8. Used for leal multiplicands.
746 (define_predicate "const248_operand"
747 (match_code "const_int")
749 HOST_WIDE_INT i = INTVAL (op);
750 return i == 2 || i == 4 || i == 8;
753 ;; Match 1, 2, or 3. Used for lea shift amounts.
754 (define_predicate "const123_operand"
755 (match_code "const_int")
757 HOST_WIDE_INT i = INTVAL (op);
758 return i == 1 || i == 2 || i == 3;
761 ;; Match 2, 3, 6, or 7
762 (define_predicate "const2367_operand"
763 (match_code "const_int")
765 HOST_WIDE_INT i = INTVAL (op);
766 return i == 2 || i == 3 || i == 6 || i == 7;
769 ;; Match 1, 2, 4, or 8
770 (define_predicate "const1248_operand"
771 (match_code "const_int")
773 HOST_WIDE_INT i = INTVAL (op);
774 return i == 1 || i == 2 || i == 4 || i == 8;
777 ;; Match 3, 5, or 9. Used for leal multiplicands.
778 (define_predicate "const359_operand"
779 (match_code "const_int")
781 HOST_WIDE_INT i = INTVAL (op);
782 return i == 3 || i == 5 || i == 9;
785 ;; Match 4 or 8 to 11. Used for embeded rounding.
786 (define_predicate "const_4_or_8_to_11_operand"
787 (match_code "const_int")
789 HOST_WIDE_INT i = INTVAL (op);
790 return i == 4 || (i >= 8 && i <= 11);
793 ;; Match 4 or 8. Used for SAE.
794 (define_predicate "const48_operand"
795 (match_code "const_int")
797 HOST_WIDE_INT i = INTVAL (op);
798 return i == 4 || i == 8;
802 (define_predicate "const_0_to_1_operand"
803 (and (match_code "const_int")
804 (ior (match_test "op == const0_rtx")
805 (match_test "op == const1_rtx"))))
808 (define_predicate "const_0_to_3_operand"
809 (and (match_code "const_int")
810 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
813 (define_predicate "const_0_to_4_operand"
814 (and (match_code "const_int")
815 (match_test "IN_RANGE (INTVAL (op), 0, 4)")))
818 (define_predicate "const_0_to_5_operand"
819 (and (match_code "const_int")
820 (match_test "IN_RANGE (INTVAL (op), 0, 5)")))
823 (define_predicate "const_0_to_7_operand"
824 (and (match_code "const_int")
825 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
828 (define_predicate "const_0_to_15_operand"
829 (and (match_code "const_int")
830 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
833 (define_predicate "const_0_to_31_operand"
834 (and (match_code "const_int")
835 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
838 (define_predicate "const_0_to_63_operand"
839 (and (match_code "const_int")
840 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
843 (define_predicate "const_0_to_255_operand"
844 (and (match_code "const_int")
845 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
847 ;; Match (0 to 255) * 8
848 (define_predicate "const_0_to_255_mul_8_operand"
849 (match_code "const_int")
851 unsigned HOST_WIDE_INT val = INTVAL (op);
852 return val <= 255*8 && val % 8 == 0;
855 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
856 ;; for shift & compare patterns, as shifting by 0 does not change flags).
857 (define_predicate "const_1_to_31_operand"
858 (and (match_code "const_int")
859 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
861 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
862 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
863 (define_predicate "const_1_to_63_operand"
864 (and (match_code "const_int")
865 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
868 (define_predicate "const_2_to_3_operand"
869 (and (match_code "const_int")
870 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
873 (define_predicate "const_4_to_5_operand"
874 (and (match_code "const_int")
875 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
878 (define_predicate "const_4_to_7_operand"
879 (and (match_code "const_int")
880 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
883 (define_predicate "const_6_to_7_operand"
884 (and (match_code "const_int")
885 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
888 (define_predicate "const_8_to_9_operand"
889 (and (match_code "const_int")
890 (match_test "IN_RANGE (INTVAL (op), 8, 9)")))
893 (define_predicate "const_8_to_11_operand"
894 (and (match_code "const_int")
895 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
898 (define_predicate "const_8_to_15_operand"
899 (and (match_code "const_int")
900 (match_test "IN_RANGE (INTVAL (op), 8, 15)")))
903 (define_predicate "const_10_to_11_operand"
904 (and (match_code "const_int")
905 (match_test "IN_RANGE (INTVAL (op), 10, 11)")))
908 (define_predicate "const_12_to_13_operand"
909 (and (match_code "const_int")
910 (match_test "IN_RANGE (INTVAL (op), 12, 13)")))
913 (define_predicate "const_12_to_15_operand"
914 (and (match_code "const_int")
915 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
918 (define_predicate "const_14_to_15_operand"
919 (and (match_code "const_int")
920 (match_test "IN_RANGE (INTVAL (op), 14, 15)")))
923 (define_predicate "const_16_to_19_operand"
924 (and (match_code "const_int")
925 (match_test "IN_RANGE (INTVAL (op), 16, 19)")))
928 (define_predicate "const_16_to_31_operand"
929 (and (match_code "const_int")
930 (match_test "IN_RANGE (INTVAL (op), 16, 31)")))
933 (define_predicate "const_20_to_23_operand"
934 (and (match_code "const_int")
935 (match_test "IN_RANGE (INTVAL (op), 20, 23)")))
938 (define_predicate "const_24_to_27_operand"
939 (and (match_code "const_int")
940 (match_test "IN_RANGE (INTVAL (op), 24, 27)")))
943 (define_predicate "const_28_to_31_operand"
944 (and (match_code "const_int")
945 (match_test "IN_RANGE (INTVAL (op), 28, 31)")))
947 ;; True if this is a constant appropriate for an increment or decrement.
948 (define_predicate "incdec_operand"
949 (match_code "const_int")
951 /* On Pentium4, the inc and dec operations causes extra dependency on flag
952 registers, since carry flag is not set. */
953 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
955 return op == const1_rtx || op == constm1_rtx;
958 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
959 (define_predicate "reg_or_pm1_operand"
960 (ior (match_operand 0 "register_operand")
961 (and (match_code "const_int")
962 (ior (match_test "op == const1_rtx")
963 (match_test "op == constm1_rtx")))))
965 ;; True if OP is acceptable as operand of DImode shift expander.
966 (define_predicate "shiftdi_operand"
967 (if_then_else (match_test "TARGET_64BIT")
968 (match_operand 0 "nonimmediate_operand")
969 (match_operand 0 "register_operand")))
971 (define_predicate "ashldi_input_operand"
972 (if_then_else (match_test "TARGET_64BIT")
973 (match_operand 0 "nonimmediate_operand")
974 (match_operand 0 "reg_or_pm1_operand")))
976 ;; Return true if OP is a vector load from the constant pool with just
977 ;; the first element nonzero.
978 (define_predicate "zero_extended_scalar_load_operand"
982 op = maybe_get_pool_constant (op);
984 if (!(op && GET_CODE (op) == CONST_VECTOR))
987 n_elts = CONST_VECTOR_NUNITS (op);
989 for (n_elts--; n_elts > 0; n_elts--)
991 rtx elt = CONST_VECTOR_ELT (op, n_elts);
992 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
998 /* Return true if operand is a vector constant that is all ones. */
999 (define_predicate "vector_all_ones_operand"
1000 (and (match_code "const_vector")
1001 (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
1002 (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
1004 ; Return true when OP is operand acceptable for vector memory operand.
1005 ; Only AVX can have misaligned memory operand.
1006 (define_predicate "vector_memory_operand"
1007 (and (match_operand 0 "memory_operand")
1008 (ior (match_test "TARGET_AVX")
1009 (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)"))))
1011 ; Return true when OP is register_operand or vector_memory_operand.
1012 (define_predicate "vector_operand"
1013 (ior (match_operand 0 "register_operand")
1014 (match_operand 0 "vector_memory_operand")))
1016 ; Return true when OP is operand acceptable for standard SSE move.
1017 (define_predicate "vector_move_operand"
1018 (ior (match_operand 0 "nonimmediate_operand")
1019 (match_operand 0 "const0_operand")))
1021 ;; Return true when OP is either nonimmediate operand, or any
1023 (define_predicate "nonimmediate_or_const_vector_operand"
1024 (ior (match_operand 0 "nonimmediate_operand")
1025 (match_code "const_vector")))
1027 ;; Return true when OP is nonimmediate or standard SSE constant.
1028 (define_predicate "nonimmediate_or_sse_const_operand"
1029 (ior (match_operand 0 "nonimmediate_operand")
1030 (match_test "standard_sse_constant_p (op, mode)")))
1032 ;; Return true if OP is a register or a zero.
1033 (define_predicate "reg_or_0_operand"
1034 (ior (match_operand 0 "register_operand")
1035 (match_operand 0 "const0_operand")))
1037 (define_predicate "norex_memory_operand"
1038 (and (match_operand 0 "memory_operand")
1039 (not (match_test "x86_extended_reg_mentioned_p (op)"))))
1041 ;; Return true for RTX codes that force SImode address.
1042 (define_predicate "SImode_address_operand"
1043 (match_code "subreg,zero_extend,and"))
1045 ;; Return true if op if a valid address for LEA, and does not contain
1046 ;; a segment override. Defined as a special predicate to allow
1047 ;; mode-less const_int operands pass to address_operand.
1048 (define_special_predicate "address_no_seg_operand"
1049 (match_test "address_operand (op, VOIDmode)")
1051 struct ix86_address parts;
1054 if (!CONST_INT_P (op)
1056 && GET_MODE (op) != mode)
1059 ok = ix86_decompose_address (op, &parts);
1061 return parts.seg == ADDR_SPACE_GENERIC;
1064 ;; Return true if op if a valid base register, displacement or
1065 ;; sum of base register and displacement for VSIB addressing.
1066 (define_predicate "vsib_address_operand"
1067 (match_test "address_operand (op, VOIDmode)")
1069 struct ix86_address parts;
1073 ok = ix86_decompose_address (op, &parts);
1075 if (parts.index || parts.seg != ADDR_SPACE_GENERIC)
1078 /* VSIB addressing doesn't support (%rip). */
1082 if (GET_CODE (disp) == CONST)
1084 disp = XEXP (disp, 0);
1085 if (GET_CODE (disp) == PLUS)
1086 disp = XEXP (disp, 0);
1087 if (GET_CODE (disp) == UNSPEC)
1088 switch (XINT (disp, 1))
1090 case UNSPEC_GOTPCREL:
1092 case UNSPEC_GOTNTPOFF:
1098 && (GET_CODE (disp) == SYMBOL_REF
1099 || GET_CODE (disp) == LABEL_REF))
1106 ;; Return true if op is valid MPX address operand without base
1107 (define_predicate "address_mpx_no_base_operand"
1108 (match_test "address_operand (op, VOIDmode)")
1110 struct ix86_address parts;
1113 ok = ix86_decompose_address (op, &parts);
1116 if (parts.index && parts.base)
1119 if (parts.seg != ADDR_SPACE_GENERIC)
1122 /* Do not support (%rip). */
1123 if (parts.disp && flag_pic && TARGET_64BIT
1124 && SYMBOLIC_CONST (parts.disp))
1126 if (GET_CODE (parts.disp) != CONST
1127 || GET_CODE (XEXP (parts.disp, 0)) != PLUS
1128 || GET_CODE (XEXP (XEXP (parts.disp, 0), 0)) != UNSPEC
1129 || !CONST_INT_P (XEXP (XEXP (parts.disp, 0), 1))
1130 || (XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_DTPOFF
1131 && XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_NTPOFF))
1138 ;; Return true if op is valid MPX address operand without index
1139 (define_predicate "address_mpx_no_index_operand"
1140 (match_test "address_operand (op, VOIDmode)")
1142 struct ix86_address parts;
1145 ok = ix86_decompose_address (op, &parts);
1151 if (parts.seg != ADDR_SPACE_GENERIC)
1154 /* Do not support (%rip). */
1155 if (parts.disp && flag_pic && TARGET_64BIT
1156 && SYMBOLIC_CONST (parts.disp)
1157 && (GET_CODE (parts.disp) != CONST
1158 || GET_CODE (XEXP (parts.disp, 0)) != PLUS
1159 || GET_CODE (XEXP (XEXP (parts.disp, 0), 0)) != UNSPEC
1160 || !CONST_INT_P (XEXP (XEXP (parts.disp, 0), 1))
1161 || (XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_DTPOFF
1162 && XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_NTPOFF)))
1168 (define_predicate "vsib_mem_operator"
1171 (define_predicate "bnd_mem_operator"
1174 ;; Return true if the rtx is known to be at least 32 bits aligned.
1175 (define_predicate "aligned_operand"
1176 (match_operand 0 "general_operand")
1178 struct ix86_address parts;
1181 /* Registers and immediate operands are always "aligned". */
1185 /* All patterns using aligned_operand on memory operands ends up
1186 in promoting memory operand to 64bit and thus causing memory mismatch. */
1187 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
1190 /* Don't even try to do any aligned optimizations with volatiles. */
1191 if (MEM_VOLATILE_P (op))
1194 if (MEM_ALIGN (op) >= 32)
1199 /* Pushes and pops are only valid on the stack pointer. */
1200 if (GET_CODE (op) == PRE_DEC
1201 || GET_CODE (op) == POST_INC)
1204 /* Decode the address. */
1205 ok = ix86_decompose_address (op, &parts);
1208 if (parts.base && SUBREG_P (parts.base))
1209 parts.base = SUBREG_REG (parts.base);
1210 if (parts.index && SUBREG_P (parts.index))
1211 parts.index = SUBREG_REG (parts.index);
1213 /* Look for some component that isn't known to be aligned. */
1216 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
1221 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
1226 if (!CONST_INT_P (parts.disp)
1227 || (INTVAL (parts.disp) & 3))
1231 /* Didn't find one -- this must be an aligned address. */
1235 ;; Return true if OP is memory operand with a displacement.
1236 (define_predicate "memory_displacement_operand"
1237 (match_operand 0 "memory_operand")
1239 struct ix86_address parts;
1242 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1244 return parts.disp != NULL_RTX;
1247 ;; Return true if OP is memory operand with a displacement only.
1248 (define_predicate "memory_displacement_only_operand"
1249 (match_operand 0 "memory_operand")
1251 struct ix86_address parts;
1257 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1260 if (parts.base || parts.index)
1263 return parts.disp != NULL_RTX;
1266 ;; Return true if OP is memory operand that cannot be represented
1267 ;; by the modRM array.
1268 (define_predicate "long_memory_operand"
1269 (and (match_operand 0 "memory_operand")
1270 (match_test "memory_address_length (op, false)")))
1272 ;; Return true if OP is a comparison operator that can be issued by fcmov.
1273 (define_predicate "fcmov_comparison_operator"
1274 (match_operand 0 "comparison_operator")
1276 machine_mode inmode = GET_MODE (XEXP (op, 0));
1277 enum rtx_code code = GET_CODE (op);
1279 if (inmode == CCFPmode || inmode == CCFPUmode)
1281 if (!ix86_trivial_fp_comparison_operator (op, mode))
1283 code = ix86_fp_compare_code_to_integer (code);
1285 /* i387 supports just limited amount of conditional codes. */
1288 case LTU: case GTU: case LEU: case GEU:
1289 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
1290 || inmode == CCCmode)
1293 case ORDERED: case UNORDERED:
1301 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1302 ;; The first set are supported directly; the second set can't be done with
1303 ;; full IEEE support, i.e. NaNs.
1305 (define_predicate "sse_comparison_operator"
1306 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1307 (and (match_test "TARGET_AVX")
1308 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1310 (define_predicate "ix86_comparison_int_operator"
1311 (match_code "ne,eq,ge,gt,le,lt"))
1313 (define_predicate "ix86_comparison_uns_operator"
1314 (match_code "ne,eq,geu,gtu,leu,ltu"))
1316 (define_predicate "bt_comparison_operator"
1317 (match_code "ne,eq"))
1319 ;; Return true if OP is a valid comparison operator in valid mode.
1320 (define_predicate "ix86_comparison_operator"
1321 (match_operand 0 "comparison_operator")
1323 machine_mode inmode = GET_MODE (XEXP (op, 0));
1324 enum rtx_code code = GET_CODE (op);
1326 if (inmode == CCFPmode || inmode == CCFPUmode)
1327 return ix86_trivial_fp_comparison_operator (op, mode);
1334 if (inmode == CCmode || inmode == CCGCmode
1335 || inmode == CCGOCmode || inmode == CCNOmode)
1338 case LTU: case GTU: case LEU: case GEU:
1339 if (inmode == CCmode || inmode == CCCmode)
1342 case ORDERED: case UNORDERED:
1343 if (inmode == CCmode)
1347 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1355 ;; Return true if OP is a valid comparison operator
1356 ;; testing carry flag to be set.
1357 (define_predicate "ix86_carry_flag_operator"
1358 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1360 machine_mode inmode = GET_MODE (XEXP (op, 0));
1361 enum rtx_code code = GET_CODE (op);
1363 if (inmode == CCFPmode || inmode == CCFPUmode)
1365 if (!ix86_trivial_fp_comparison_operator (op, mode))
1367 code = ix86_fp_compare_code_to_integer (code);
1369 else if (inmode == CCCmode)
1370 return code == LTU || code == GTU;
1371 else if (inmode != CCmode)
1377 ;; Return true if this comparison only requires testing one flag bit.
1378 (define_predicate "ix86_trivial_fp_comparison_operator"
1379 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1381 ;; Return true if we know how to do this comparison. Others require
1382 ;; testing more than one flag bit, and we let the generic middle-end
1384 (define_predicate "ix86_fp_comparison_operator"
1385 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1386 == IX86_FPCMP_ARITH")
1387 (match_operand 0 "comparison_operator")
1388 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1390 ;; Same as above, but for swapped comparison used in *jcc<fp>_<int>_i387.
1391 (define_predicate "ix86_swapped_fp_comparison_operator"
1392 (match_operand 0 "comparison_operator")
1394 enum rtx_code code = GET_CODE (op);
1397 PUT_CODE (op, swap_condition (code));
1398 ret = ix86_fp_comparison_operator (op, mode);
1399 PUT_CODE (op, code);
1403 ;; Nearly general operand, but accept any const_double, since we wish
1404 ;; to be able to drop them into memory rather than have them get pulled
1406 (define_predicate "cmp_fp_expander_operand"
1407 (ior (match_code "const_double")
1408 (match_operand 0 "general_operand")))
1410 ;; Return true if this is a valid binary floating-point operation.
1411 (define_predicate "binary_fp_operator"
1412 (match_code "plus,minus,mult,div"))
1414 ;; Return true if this is a multiply operation.
1415 (define_predicate "mult_operator"
1416 (match_code "mult"))
1418 ;; Return true if this is a division operation.
1419 (define_predicate "div_operator"
1422 ;; Return true if this is a plus, minus, and, ior or xor operation.
1423 (define_predicate "plusminuslogic_operator"
1424 (match_code "plus,minus,and,ior,xor"))
1426 ;; Return true if this is a float extend operation.
1427 (define_predicate "float_operator"
1428 (match_code "float"))
1430 ;; Return true for ARITHMETIC_P.
1431 (define_predicate "arith_or_logical_operator"
1432 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1433 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1435 ;; Return true for COMMUTATIVE_P.
1436 (define_predicate "commutative_operator"
1437 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1439 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1440 (define_predicate "promotable_binary_operator"
1441 (ior (match_code "plus,minus,and,ior,xor,ashift")
1442 (and (match_code "mult")
1443 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1445 (define_predicate "compare_operator"
1446 (match_code "compare"))
1448 (define_predicate "absneg_operator"
1449 (match_code "abs,neg"))
1451 ;; Return true if OP is a memory operand, aligned to
1452 ;; less than its natural alignment.
1453 (define_predicate "misaligned_operand"
1454 (and (match_code "mem")
1455 (match_test "MEM_ALIGN (op) < GET_MODE_BITSIZE (mode)")))
1457 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1458 (define_predicate "emms_operation"
1459 (match_code "parallel")
1463 if (XVECLEN (op, 0) != 17)
1466 for (i = 0; i < 8; i++)
1468 rtx elt = XVECEXP (op, 0, i+1);
1470 if (GET_CODE (elt) != CLOBBER
1471 || GET_CODE (SET_DEST (elt)) != REG
1472 || GET_MODE (SET_DEST (elt)) != XFmode
1473 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1476 elt = XVECEXP (op, 0, i+9);
1478 if (GET_CODE (elt) != CLOBBER
1479 || GET_CODE (SET_DEST (elt)) != REG
1480 || GET_MODE (SET_DEST (elt)) != DImode
1481 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1487 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1488 (define_predicate "vzeroall_operation"
1489 (match_code "parallel")
1491 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1493 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1496 for (i = 0; i < nregs; i++)
1498 rtx elt = XVECEXP (op, 0, i+1);
1500 if (GET_CODE (elt) != SET
1501 || GET_CODE (SET_DEST (elt)) != REG
1502 || GET_MODE (SET_DEST (elt)) != V8SImode
1503 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1504 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1510 ;; return true if OP is a vzeroupper operation.
1511 (define_predicate "vzeroupper_operation"
1512 (and (match_code "unspec_volatile")
1513 (match_test "XINT (op, 1) == UNSPECV_VZEROUPPER")))
1515 ;; Return true if OP is an addsub vec_merge operation
1516 (define_predicate "addsub_vm_operator"
1517 (match_code "vec_merge")
1528 if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1530 else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1535 mask = INTVAL (XEXP (op, 2));
1536 nunits = GET_MODE_NUNITS (mode);
1538 for (elt = 0; elt < nunits; elt++)
1540 /* bit clear: take from op0, set: take from op1 */
1541 int bit = !(mask & (HOST_WIDE_INT_1U << elt));
1543 if (bit != ((elt & 1) ^ swapped))
1550 ;; Return true if OP is an addsub vec_select/vec_concat operation
1551 (define_predicate "addsub_vs_operator"
1552 (and (match_code "vec_select")
1553 (match_code "vec_concat" "0"))
1559 op0 = XEXP (XEXP (op, 0), 0);
1560 op1 = XEXP (XEXP (op, 0), 1);
1563 if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1565 else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1570 nunits = GET_MODE_NUNITS (mode);
1571 if (XVECLEN (XEXP (op, 1), 0) != nunits)
1574 /* We already checked that permutation is suitable for addsub,
1575 so only look at the first element of the parallel. */
1576 elt = INTVAL (XVECEXP (XEXP (op, 1), 0, 0));
1578 return elt == (swapped ? nunits : 0);
1581 ;; Return true if OP is a parallel for an addsub vec_select.
1582 (define_predicate "addsub_vs_parallel"
1583 (and (match_code "parallel")
1584 (match_code "const_int" "a"))
1586 int nelt = XVECLEN (op, 0);
1592 /* Check that the permutation is suitable for addsub.
1593 For example, { 0 9 2 11 4 13 6 15 } or { 8 1 10 3 12 5 14 7 }. */
1594 elt = INTVAL (XVECEXP (op, 0, 0));
1597 for (i = 1; i < nelt; ++i)
1598 if (INTVAL (XVECEXP (op, 0, i)) != (i + (i & 1) * nelt))
1601 else if (elt == nelt)
1603 for (i = 1; i < nelt; ++i)
1604 if (INTVAL (XVECEXP (op, 0, i)) != (elt + i - (i & 1) * nelt))
1613 ;; Return true if OP is a parallel for a vbroadcast permute.
1614 (define_predicate "avx_vbroadcast_operand"
1615 (and (match_code "parallel")
1616 (match_code "const_int" "a"))
1618 rtx elt = XVECEXP (op, 0, 0);
1619 int i, nelt = XVECLEN (op, 0);
1621 /* Don't bother checking there are the right number of operands,
1622 merely that they're all identical. */
1623 for (i = 1; i < nelt; ++i)
1624 if (XVECEXP (op, 0, i) != elt)
1629 ;; Return true if OP is a parallel for a palignr permute.
1630 (define_predicate "palignr_operand"
1631 (and (match_code "parallel")
1632 (match_code "const_int" "a"))
1634 int elt = INTVAL (XVECEXP (op, 0, 0));
1635 int i, nelt = XVECLEN (op, 0);
1637 /* Check that an order in the permutation is suitable for palignr.
1638 For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm". */
1639 for (i = 1; i < nelt; ++i)
1640 if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt))
1645 ;; Return true if OP is a proper third operand to vpblendw256.
1646 (define_predicate "avx2_pblendw_operand"
1647 (match_code "const_int")
1649 HOST_WIDE_INT val = INTVAL (op);
1650 HOST_WIDE_INT low = val & 0xff;
1651 return val == ((low << 8) | low);
1654 ;; Return true if OP is vector_operand or CONST_VECTOR.
1655 (define_predicate "general_vector_operand"
1656 (ior (match_operand 0 "vector_operand")
1657 (match_code "const_vector")))
1659 ;; Return true if OP is either -1 constant or stored in register.
1660 (define_predicate "register_or_constm1_operand"
1661 (ior (match_operand 0 "register_operand")
1662 (and (match_code "const_int")
1663 (match_test "op == constm1_rtx"))))
1665 ;; Return true if the vector ends with between 12 and 18 register saves using
1666 ;; RAX as the base address.
1667 (define_predicate "save_multiple"
1668 (match_code "parallel")
1670 const unsigned len = XVECLEN (op, 0);
1673 /* Starting from end of vector, count register saves. */
1674 for (i = 0; i < len; ++i)
1676 rtx src, dest, addr;
1677 rtx e = XVECEXP (op, 0, len - 1 - i);
1679 if (GET_CODE (e) != SET)
1683 dest = SET_DEST (e);
1685 if (!REG_P (src) || !MEM_P (dest))
1688 addr = XEXP (dest, 0);
1690 /* Good if dest address is in RAX. */
1691 if (REG_P (addr) && REGNO (addr) == AX_REG)
1694 /* Good if dest address is offset of RAX. */
1695 if (GET_CODE (addr) == PLUS
1696 && REG_P (XEXP (addr, 0))
1697 && REGNO (XEXP (addr, 0)) == AX_REG)
1702 return (i >= 12 && i <= 18);
1706 ;; Return true if the vector ends with between 12 and 18 register loads using
1707 ;; RSI as the base address.
1708 (define_predicate "restore_multiple"
1709 (match_code "parallel")
1711 const unsigned len = XVECLEN (op, 0);
1714 /* Starting from end of vector, count register restores. */
1715 for (i = 0; i < len; ++i)
1717 rtx src, dest, addr;
1718 rtx e = XVECEXP (op, 0, len - 1 - i);
1720 if (GET_CODE (e) != SET)
1724 dest = SET_DEST (e);
1726 if (!MEM_P (src) || !REG_P (dest))
1729 addr = XEXP (src, 0);
1731 /* Good if src address is in RSI. */
1732 if (REG_P (addr) && REGNO (addr) == SI_REG)
1735 /* Good if src address is offset of RSI. */
1736 if (GET_CODE (addr) == PLUS
1737 && REG_P (XEXP (addr, 0))
1738 && REGNO (XEXP (addr, 0)) == SI_REG)
1743 return (i >= 12 && i <= 18);