gcc/config/cr16/cr16.h

   1 /* Definitions of target machine for GNU compiler, for CR16.
   2    Copyright (C) 2012-2017 Free Software Foundation, Inc.
   3    Contributed by KPIT Cummins Infosystems Limited.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef GCC_CR16_H
  22 #define GCC_CR16_H
  23
  24 #define OBJECT_FORMAT_ELF
  25
  26 /* Controlling the driver.  */
  27
  28 /* The GNU C++ standard library requires that these macros be defined.  */
  29 #undef CPLUSPLUS_CPP_SPEC
  30 #define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
  31
  32 #undef  STARTFILE_SPEC
  33 #define STARTFILE_SPEC "crt1.o%s crti.o%s crtbegin.o%s crtlibid.o%s"
  34
  35 #undef  ENDFILE_SPEC
  36 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
  37
  38 #undef  MATH_LIBRARY
  39 #define MATH_LIBRARY ""
  40
  41 #undef  LIB_SPEC
  42 #define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
  43 %{msim*:%{!T*:-Tsim.ld}} \
  44 %{!T*:%{!msim*: %{-Telf32cr16.x}}}"
  45
  46 /* Run-time target specification.  */
  47 #ifndef TARGET_CPU_CPP_BUILTINS
  48 #define TARGET_CPU_CPP_BUILTINS()          \
  49 do                                         \
  50   {                                        \
  51     builtin_define ("__CR__");             \
  52     builtin_define ("__CR16__");           \
  53     builtin_define ("__CR16C__");          \
  54     if (TARGET_CR16CP)                     \
  55       builtin_define ("__CR16CP__");       \
  56     else                                   \
  57       builtin_define ("__CR16CSTD__");     \
  58     if (CR16_TARGET_DATA_NEAR)             \
  59       builtin_define ("__DATA_NEAR__");    \
  60     if (CR16_TARGET_DATA_MEDIUM)           \
  61       builtin_define ("__DATA_MEDIUM__");  \
  62     if (CR16_TARGET_DATA_FAR)              \
  63       builtin_define ("__DATA_FAR__");     \
  64     if (TARGET_INT32)                      \
  65       builtin_define ("__INT32__");        \
  66   }                                        \
  67 while (0)
  68 #endif
  69
  70 /* Force the generation of dwarf .debug_frame sections even if not
  71    compiling -g.  This guarantees that we can unwind the stack.  */
  72 #define DWARF2_FRAME_INFO 1
  73
  74 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
  75
  76 /* Generate .file/.loc directives, so that the assembler generates the
  77    line table.  */
  78 #define DWARF2_ASM_LINE_DEBUG_INFO 1
  79
  80 #define CR16_TARGET_DATA_NEAR   cr16_is_data_model (DM_NEAR)
  81 #define CR16_TARGET_DATA_MEDIUM cr16_is_data_model (DM_DEFAULT)
  82 #define CR16_TARGET_DATA_FAR    cr16_is_data_model (DM_FAR)
  83
  84 /* Storage layout.  */
  85 #define BITS_BIG_ENDIAN     0
  86
  87 #define BYTES_BIG_ENDIAN    0
  88
  89 #define WORDS_BIG_ENDIAN    0
  90
  91 #define UNITS_PER_WORD      2
  92
  93 /* Units per 32-bit (DWORD).  */
  94 #define CR16_UNITS_PER_DWORD 4
  95
  96 #define POINTER_SIZE        32
  97
  98 #define PARM_BOUNDARY       16
  99
 100 #define STACK_BOUNDARY      (MAX (BIGGEST_ALIGNMENT, PARM_BOUNDARY))
 101
 102 #define FUNCTION_BOUNDARY   BIGGEST_ALIGNMENT
 103
 104 /* Biggest alignment on CR16C+ is 32-bit as internal bus is AMBA based
 105    where as CR16C is proprietary internal bus architecture.  */
 106 #define BIGGEST_ALIGNMENT   ((TARGET_CR16CP) ? 32 : 16)
 107
 108 #define MAX_FIXED_MODE_SIZE 64
 109
 110 /* In CR16 arrays of chars are word-aligned, so strcpy () will be faster.  */
 111 #define DATA_ALIGNMENT(TYPE, ALIGN)              \
 112   (((TREE_CODE (TYPE) == ARRAY_TYPE)             \
 113      && (TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
 114      && ((ALIGN) < BITS_PER_WORD))               \
 115      ? (BITS_PER_WORD) : (ALIGN))
 116
 117 /* In CR16 strings are word-aligned; strcpy from constants will be faster.  */
 118 #define CONSTANT_ALIGNMENT(CONSTANT, ALIGN)                            \
 119   (((TREE_CODE (CONSTANT) == STRING_CST) && ((ALIGN) < BITS_PER_WORD)) \
 120      ? (BITS_PER_WORD) : (ALIGN))
 121
 122 #define STRICT_ALIGNMENT 0
 123
 124 #define PCC_BITFIELD_TYPE_MATTERS 1
 125
 126 /* Layout of source language data types.  */
 127 #define INT_TYPE_SIZE       (TARGET_INT32 ? 32 : 16)
 128
 129 #define SHORT_TYPE_SIZE     16
 130
 131 #define LONG_TYPE_SIZE      32
 132
 133 #define LONG_LONG_TYPE_SIZE 64
 134
 135 #define FLOAT_TYPE_SIZE     32
 136
 137 #define DOUBLE_TYPE_SIZE    64
 138
 139 #define LONG_DOUBLE_TYPE_SIZE 64
 140
 141 #define DEFAULT_SIGNED_CHAR 1
 142
 143 #define SIZE_TYPE           "long unsigned int"
 144
 145 #define PTRDIFF_TYPE        "long int"
 146
 147 #define WCHAR_TYPE          "short unsigned int"
 148
 149 #define WCHAR_TYPE_SIZE     16
 150
 151 /* By default, the C++ compiler will use the lowest bit of the pointer
 152    to function to indicate a pointer-to-member-function points to a
 153    virtual member function.  However, in CR architecture FUNCTION_BOUNDARY
 154    indicates function addresses are always even, but function pointers can be
 155    odd (after right-shifting them when loading them into a register), and the
 156    default doesn't work.  In that case, the lowest bit of the delta
 157    field will be used (the remainder of the field is shifted to the left).  */
 158 #define TARGET_PTRMEMFUNC_VBIT_LOCATION     ptrmemfunc_vbit_in_delta
 159
 160 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
 161    values must be in memory.  */
 162 #define DEFAULT_PCC_STRUCT_RETURN 0
 163
 164 /* Register usage.  */
 165
 166 /* First 32-bit register is R12.  */
 167 #define CR16_FIRST_DWORD_REGISTER   12
 168
 169 #define FIRST_PSEUDO_REGISTER       16
 170
 171 /* 1 for registers that have pervasive standard uses
 172    and are not available for the register allocator.
 173    On the CR16, only the stack pointer (r15) is such.  */
 174 #define FIXED_REGISTERS                               \
 175   {                                                   \
 176   /* r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10.  */ \
 177     0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,        \
 178   /* r11 r12 r13 ra  sp.  */                          \
 179     0,  0,  0,  0,  1                                 \
 180   }
 181
 182 /* 1 for registers not available across function calls.
 183    These must include the FIXED_REGISTERS and also any
 184    registers that can be used without being saved.
 185    The latter must include the registers where values are returned
 186    and the register where structure-value addresses are passed.
 187
 188    On the CR16, calls clobbers r0-r6 (scratch registers),
 189    ra (the return address) and sp (the stack pointer).  */
 190 #define CALL_USED_REGISTERS                           \
 191   {                                                   \
 192   /* r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10.  */ \
 193     1,  1,  1,  1,  1,  1,  1,  0,  0,  0,  0,        \
 194   /* r11 r12 r13 ra  sp.  */                          \
 195     0,  0,  0,  1,  1                                 \
 196   }
 197
 198 /* Returns 1 if the register is longer than word size, 0 otherwise.  */
 199 #define LONG_REG_P(REGNO)                                                    \
 200   (targetm.hard_regno_nregs (REGNO,                                          \
 201                              GET_MODE_WIDER_MODE (word_mode).require ()) == 1)
 202
 203 #define NOTICE_UPDATE_CC(EXP, INSN) \
 204    notice_update_cc ((EXP))
 205
 206 /* Interrupt functions can only use registers that have already been
 207    saved by the prologue, even if they would normally be call-clobbered
 208    Check if sizes are same and then check if it is possible to rename.  */
 209 #define HARD_REGNO_RENAME_OK(SRC, DEST)                 \
 210   (!cr16_interrupt_function_p () || (df_regs_ever_live_p (DEST)))
 211
 212 /* Exception handling stuff.  */
 213
 214 /*To ensure correct dwarf unwinding.  */
 215 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((optimize ("no-gcse","no-dse")))
 216
 217 #define gen_rtx_RA      gen_rtx_REG (Pmode, RETURN_ADDRESS_REGNUM)
 218
 219 /* Use (r8,r7) and (r10,r9) to pass exception handling information.  */
 220 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N*2 + 7) : INVALID_REGNUM)
 221
 222 #define DWARF2_UNWIND_INFO 1
 223
 224 /* (r5,r4) holds a stack adjustment for returning to a handler.  */
 225 #define EH_RETURN_STACKADJ_RTX          gen_rtx_REG (Pmode, 4)
 226
 227 #define EH_RETURN_HANDLER_RTX \
 228   gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, -4))
 229
 230 #define INCOMING_RETURN_ADDR_RTX        gen_rtx_RA
 231
 232 #define DWARF_FRAME_RETURN_COLUMN       \
 233   DWARF_FRAME_REGNUM (RETURN_ADDRESS_REGNUM)
 234
 235 #define INCOMING_FRAME_SP_OFFSET                0
 236 #define FRAME_POINTER_CFA_OFFSET(FNDECL)        0
 237
 238 /* A C expression whose value is RTL representing the value of the return
 239    address for the frame COUNT steps up from the current frame.  */
 240 #define RETURN_ADDR_RTX(COUNT, FRAME)                                   \
 241   (0 == COUNT)  ?  gen_rtx_PLUS (Pmode, gen_rtx_RA, gen_rtx_RA)         \
 242                 :  const0_rtx
 243
 244 enum reg_class
 245 {
 246   NO_REGS,
 247   SHORT_REGS,
 248   LONG_REGS,
 249   NOSP_REGS,
 250   DOUBLE_BASE_REGS,
 251   GENERAL_REGS,
 252   ALL_REGS,
 253   LIM_REG_CLASSES
 254 };
 255
 256 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 257
 258 #define REG_CLASS_NAMES \
 259   {                     \
 260     "NO_REGS",          \
 261     "SHORT_REGS",       \
 262     "LONG_REGS",        \
 263     "NOSP_REGS",        \
 264     "DOUBLE_BASE_REGS", \
 265     "GENERAL_REGS",     \
 266     "ALL_REGS"          \
 267   }
 268
 269 #define REG_CLASS_CONTENTS                                      \
 270   {                                                             \
 271     {0x00000000}, /* NO_REGS                         */         \
 272     {0x00000FFF}, /* SHORT_REGS         : 0 - 11     */         \
 273     {0x0000F000}, /* LONG_REGS          : 12 - 15    */         \
 274     {0x00007FFF}, /* NOSP_REGS          : 0 - 14     */         \
 275     {0x0000F555}, /* DOUBLE_BASE_REGS   : 2,4,6,8,10 */         \
 276     {0x0000FFFF}, /* GENERAL_REGS       : 0 - 15     */         \
 277     {0x0000FFFF}  /* ALL_REGS           : 0 - 15     */         \
 278   }
 279
 280 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P  hook_bool_mode_true
 281
 282 #define REGNO_REG_CLASS(REGNO)  cr16_regno_reg_class (REGNO)
 283
 284 #define BASE_REG_CLASS      GENERAL_REGS
 285
 286 #define MODE_BASE_REG_CLASS(MODE) \
 287   (GET_MODE_SIZE (MODE) <= 4 ?  (BASE_REG_CLASS) :  (DOUBLE_BASE_REGS))
 288
 289 #define INDEX_REG_CLASS      LONG_REGS
 290
 291 #define CR16_REGNO_OK_FOR_BASE_P(REGNO)                  \
 292   (((REGNO) < FIRST_PSEUDO_REGISTER)                     \
 293      || (reg_renumber && ((unsigned) reg_renumber[REGNO] \
 294                         < FIRST_PSEUDO_REGISTER)))
 295
 296 /* Use even-numbered reg for 64-bit accesses.  */
 297 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE)     \
 298         (CR16_REGNO_OK_FOR_BASE_P(REGNO)  &&      \
 299           ((GET_MODE_SIZE (MODE) > 4  &&          \
 300              (REGNO) < CR16_FIRST_DWORD_REGISTER) \
 301              ? (0 == ((REGNO) & 1))               \
 302              : 1))
 303
 304 /* TODO: For now lets not support index addressing mode.  */
 305 #define REGNO_OK_FOR_INDEX_P(REGNO)        \
 306   (((REGNO >= CR16_FIRST_DWORD_REGISTER)   \
 307      && ((REGNO) < FIRST_PSEUDO_REGISTER)) \
 308    || (reg_renumber                        \
 309        && (((unsigned) reg_renumber[REGNO] >= CR16_FIRST_DWORD_REGISTER)  \
 310             && ((unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER))) \
 311   )
 312
 313 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
 314
 315 /* The maximum number of consecutive registers of class CLASS needed to
 316    hold a value of mode MODE.
 317    On the CompactRISC architecture, the size of MODE in words.
 318    The size of MODE in double words for the class LONG_REGS.
 319
 320    The following check assumes if the class is not LONG_REGS, then
 321    all (NO_REGS, SHORT_REGS, NOSP_REGS and GENERAL_REGS) other classes are
 322    short.  We may have to check if this can cause any degradation in
 323    performance.  */
 324 #define CLASS_MAX_NREGS(CLASS, MODE) \
 325   (CLASS == LONG_REGS \
 326    ? (GET_MODE_SIZE (MODE) + CR16_UNITS_PER_DWORD - 1) / CR16_UNITS_PER_DWORD\
 327    : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 328
 329 /* Macros to check the range of integers . These macros were used across
 330    the port, majorly in constraints.md, predicates.md files. */
 331 #define SIGNED_INT_FITS_N_BITS(imm, N)           \
 332   ((((imm) < ((HOST_WIDE_INT) 1 << ((N) - 1)))       \
 333       && ((imm) >= -((HOST_WIDE_INT) 1 << ((N) - 1)))) ? 1 : 0)
 334
 335 #define UNSIGNED_INT_FITS_N_BITS(imm, N) \
 336   (((imm) < ((HOST_WIDE_INT) 1 << (N)) && (imm) >= (HOST_WIDE_INT) 0) ? 1 : 0)
 337
 338 #define IN_RANGE_P(VALUE, LOW, HIGH)                            \
 339   ((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW))           \
 340    && (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH))))
 341
 342 #define IN_RAN(VALUE, LOW, HIGH)                             \
 343   (((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW))       \
 344    && (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH)))) ? 1 : 0)
 345
 346 /* This check is for sbit/cbit instruction.  */
 347 #define OK_FOR_Z(OP) \
 348   ((GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST_INT) \
 349    || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) \
 350    || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \
 351        && GET_CODE (XEXP ((XEXP (OP, 0)), 0)) == REG \
 352        && GET_CODE (XEXP ((XEXP (OP, 0)), 1)) == CONST_INT))
 353
 354 /* Stack layout and calling conventions.  */
 355 #define STACK_GROWS_DOWNWARD 1
 356
 357 #define STARTING_FRAME_OFFSET   0
 358
 359 #define STACK_POINTER_REGNUM    15
 360
 361 #define FRAME_POINTER_REGNUM    13
 362
 363 #define ARG_POINTER_REGNUM      12
 364
 365 #define STATIC_CHAIN_REGNUM     1
 366
 367 #define RETURN_ADDRESS_REGNUM   14
 368
 369 #define FIRST_PARM_OFFSET(FNDECL) 0
 370
 371 #define ELIMINABLE_REGS                            \
 372   {                                                \
 373     { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM}, \
 374     { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM}, \
 375     { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}  \
 376   }
 377
 378 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)              \
 379   do                                                              \
 380     {                                                             \
 381       (OFFSET) = cr16_initial_elimination_offset ((FROM), (TO));  \
 382     }                                                             \
 383   while (0)
 384
 385 /* Passing function arguments.  */
 386
 387 #define ACCUMULATE_OUTGOING_ARGS 0
 388
 389 #define PUSH_ARGS 1
 390
 391 #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
 392
 393 #ifndef CUMULATIVE_ARGS
 394 struct cumulative_args
 395 {
 396   int ints;
 397   int last_parm_in_reg;
 398 };
 399
 400 #define CUMULATIVE_ARGS struct cumulative_args
 401 #endif
 402
 403 /* On the CR16 architecture, Varargs routines should receive their parameters
 404    on the stack.  */
 405
 406 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
 407   cr16_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
 408
 409 #define FUNCTION_ARG_REGNO_P(REGNO)  cr16_function_arg_regno_p (REGNO)
 410
 411 /* Generating code for profiling - NOT IMPLEMENTED.  */
 412 #undef  FUNCTION_PROFILER
 413 #define FUNCTION_PROFILER(STREAM, LABELNO)      \
 414 {                                               \
 415   sorry ("profiler support for CR16");          \
 416 }
 417
 418 /* Trampolines for nested functions - NOT SUPPORTED.  */
 419 #define TRAMPOLINE_SIZE    16
 420
 421 /* ADDRESSING MODES.  */
 422
 423 #define CONSTANT_ADDRESS_P(X)       \
 424   (GET_CODE (X) == LABEL_REF        \
 425    || GET_CODE (X) == SYMBOL_REF    \
 426    || GET_CODE (X) == CONST         \
 427    || GET_CODE (X) == CONST_INT)
 428
 429 #define MAX_REGS_PER_ADDRESS    2
 430
 431 #define HAVE_POST_INCREMENT     0
 432 #define HAVE_POST_DECREMENT     0
 433 #define HAVE_POST_MODIFY_DISP   0
 434 #define HAVE_POST_MODIFY_REG    0
 435
 436 #ifdef REG_OK_STRICT
 437 #define CR16_REG_OK_FOR_BASE_P(X)       CR16_REGNO_OK_FOR_BASE_P (REGNO (X))
 438 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 439   REGNO_MODE_OK_FOR_BASE_P (REGNO(X), MODE)
 440 #define REG_OK_FOR_INDEX_P(X)   REGNO_OK_FOR_INDEX_P (REGNO (X))
 441 #else /* not REG_OK_STRICT.  */
 442 #define CR16_REG_OK_FOR_BASE_P(X)       1
 443 #define REG_MODE_OK_FOR_BASE_P(X, MODE) 1
 444 #define REG_OK_FOR_INDEX_P(X)   1
 445 #endif /* not REG_OK_STRICT.  */
 446
 447 /* Assume best case (branch predicted).  */
 448 #define BRANCH_COST(speed_p, predictable_p)       2
 449
 450 #define SLOW_BYTE_ACCESS  1
 451
 452 /* It is as good or better to call a constant function address than to
 453    call an address kept in a register.  */
 454 #define NO_FUNCTION_CSE 1
 455
 456 /* Dividing the output into sections.  */
 457
 458 #define TEXT_SECTION_ASM_OP "\t.section\t.text"
 459
 460 #define DATA_SECTION_ASM_OP "\t.section\t.data"
 461
 462 #define BSS_SECTION_ASM_OP  "\t.section\t.bss"
 463
 464 /* Position independent code (PIC).  */
 465 /* NEAR_PIC for -fpic option.  */
 466
 467 #define NEAR_PIC 1
 468
 469 /* FAR_PIC for -fPIC option.  */
 470
 471 #define FAR_PIC  2
 472
 473 #define PIC_OFFSET_TABLE_REGNUM  12
 474
 475 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
 476
 477 /* Assembler format.  */
 478
 479 /* Character to start a comment.  */
 480 #define ASM_COMMENT_START "#"
 481
 482 #define GLOBAL_ASM_OP "\t.globl\t"
 483
 484 #undef USER_LABEL_PREFIX
 485 #define USER_LABEL_PREFIX "_"
 486
 487 #undef ASM_OUTPUT_LABELREF
 488 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
 489   asm_fprintf (STREAM, "%U%s", (*targetm.strip_name_encoding) (NAME));
 490
 491 #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL)   \
 492   do                                            \
 493     {                                           \
 494       const char *rn = XSTR (SYMBOL, 0);        \
 495       assemble_name (STREAM, rn);               \
 496       if (SYMBOL_REF_FUNCTION_P (SYMBOL))       \
 497       {                                         \
 498         fprintf ((STREAM), "@c");               \
 499       }                                         \
 500     }                                           \
 501   while (0)
 502
 503 #undef ASM_APP_ON
 504 #define ASM_APP_ON   "#APP\n"
 505
 506 #undef ASM_APP_OFF
 507 #define ASM_APP_OFF  "#NO_APP\n"
 508
 509 /* Switch into a generic section.  */
 510 #define TARGET_ASM_NAMED_SECTION        default_elf_asm_named_section
 511
 512 #undef INIT_SECTION_ASM_OP
 513 #define INIT_SECTION_ASM_OP             "\t.section\t.init"
 514
 515 #undef FINI_SECTION_ASM_OP
 516 #define FINI_SECTION_ASM_OP             "\t.section\t.fini"
 517
 518 /* Instruction output.  */
 519
 520 #define REGISTER_NAMES                                     \
 521   {                                                        \
 522     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7", \
 523     "r8",  "r9",  "r10", "r11", "r12", "r13", "ra",  "sp"  \
 524   }
 525
 526 /* Output of dispatch tables.  */
 527
 528 /* Revisit. No PC relative case as label expressions are not
 529    properly supported in binutils else we could have done this:
 530    #define CASE_VECTOR_PC_RELATIVE (optimize_size ? 1 : 0).  */
 531 #define CASE_VECTOR_PC_RELATIVE 0
 532
 533 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)    \
 534   ((GET_MODE (BODY) == QImode)                              \
 535    ? fprintf ((FILE), "\t.byte (.L%d-.L%d) >> 1\n",         \
 536               VALUE, REL)                                   \
 537    : fprintf ((FILE), "\t.word (.L%d-.L%d) >> 1\n",         \
 538               VALUE, REL))
 539
 540 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
 541   asm_fprintf ((STREAM), "\t.long\t.L%d@c\n", (VALUE))
 542
 543 /* Alignment in assembler file.  */
 544
 545 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
 546   asm_fprintf ((STREAM), "\t.align\t%d\n", 1 << (POWER))
 547
 548 /* Miscellaneous parameters.  */
 549
 550 #define CASE_VECTOR_MODE  Pmode
 551
 552 #define MOVE_MAX 4
 553
 554 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)  1
 555
 556 #define STORE_FLAG_VALUE  1
 557
 558 #define Pmode SImode
 559
 560 #define FUNCTION_MODE QImode
 561
 562 /* Define this boolean macro(s) to indicate whether or not your architecture
 563    has (un)conditional branches that can span all of memory.  It is used in
 564    conjunction with an optimization that partitions hot and cold basic blocks
 565    into separate sections of the executable.
 566    CR16 contains branch instructions that span whole address space.  */
 567 #define HAS_LONG_COND_BRANCH    1
 568 #define HAS_LONG_UNCOND_BRANCH  1
 569
 570 #endif /* End of GCC_CR16_H.  */