1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 static int bb_reload_num
;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn
*curr_insn
;
144 static rtx curr_insn_set
;
145 static basic_block curr_bb
;
146 static lra_insn_recog_data_t curr_id
;
147 static struct lra_static_insn_data
*curr_static_id
;
148 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
156 /* Start numbers for new registers and insns at the current constraints
158 static int new_regno_start
;
159 static int new_insn_uid_start
;
161 /* If LOC is nonnull, strip any outer subreg from it. */
163 strip_subreg (rtx
*loc
)
165 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
171 get_try_hard_regno (int regno
)
174 enum reg_class rclass
;
176 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
177 hard_regno
= lra_get_regno_hard_regno (regno
);
180 rclass
= lra_get_allocno_class (regno
);
181 if (rclass
== NO_REGS
)
183 return ira_class_hard_regs
[rclass
][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
191 get_hard_regno (rtx x
, bool final_p
)
198 reg
= SUBREG_REG (x
);
201 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
202 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
206 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
208 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
209 SUBREG_BYTE (x
), GET_MODE (x
));
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno
)
222 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
223 hard_regno
= lra_get_regno_hard_regno (regno
);
226 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
227 return REGNO_REG_CLASS (hard_regno
);
229 if (regno
>= new_regno_start
)
230 return lra_get_allocno_class (regno
);
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
243 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
245 enum reg_class rclass
, common_class
;
246 machine_mode reg_mode
;
247 int class_size
, hard_regno
, nregs
, i
, j
;
248 int regno
= REGNO (reg
);
250 if (new_class
!= NULL
)
251 *new_class
= NO_REGS
;
252 if (regno
< FIRST_PSEUDO_REGISTER
)
255 rtx
*final_loc
= &final_reg
;
257 lra_eliminate_reg_if_possible (final_loc
);
258 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
260 reg_mode
= GET_MODE (reg
);
261 rclass
= get_reg_class (regno
);
262 if (regno
< new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn
) >= new_insn_uid_start
269 && curr_insn_set
!= NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set
))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
272 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
278 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
279 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
280 lra_no_alloc_regs
)));
283 common_class
= ira_reg_class_subset
[rclass
][cl
];
284 if (new_class
!= NULL
)
285 *new_class
= common_class
;
286 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
289 /* Check that there are enough allocatable regs. */
290 class_size
= ira_class_hard_regs_num
[common_class
];
291 for (i
= 0; i
< class_size
; i
++)
293 hard_regno
= ira_class_hard_regs
[common_class
][i
];
294 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
297 for (j
= 0; j
< nregs
; j
++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
299 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
309 /* Return true if REGNO satisfies a memory constraint. */
313 return get_reg_class (regno
) == NO_REGS
;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
321 rtx addr
, addr_space_t as
)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as
));
325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
331 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
336 /* Temporarily eliminates registers in an address (for the lifetime of
338 class address_eliminator
{
340 address_eliminator (struct address_info
*ad
);
341 ~address_eliminator ();
344 struct address_info
*m_ad
;
352 address_eliminator::address_eliminator (struct address_info
*ad
)
354 m_base_loc (strip_subreg (ad
->base_term
)),
355 m_base_reg (NULL_RTX
),
356 m_index_loc (strip_subreg (ad
->index_term
)),
357 m_index_reg (NULL_RTX
)
359 if (m_base_loc
!= NULL
)
361 m_base_reg
= *m_base_loc
;
362 lra_eliminate_reg_if_possible (m_base_loc
);
363 if (m_ad
->base_term2
!= NULL
)
364 *m_ad
->base_term2
= *m_ad
->base_term
;
366 if (m_index_loc
!= NULL
)
368 m_index_reg
= *m_index_loc
;
369 lra_eliminate_reg_if_possible (m_index_loc
);
373 address_eliminator::~address_eliminator ()
375 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
377 *m_base_loc
= m_base_reg
;
378 if (m_ad
->base_term2
!= NULL
)
379 *m_ad
->base_term2
= *m_ad
->base_term
;
381 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
382 *m_index_loc
= m_index_reg
;
385 /* Return true if the eliminated form of AD is a legitimate target address. */
387 valid_address_p (struct address_info
*ad
)
389 address_eliminator
eliminator (ad
);
390 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
396 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
398 struct address_info ad
;
400 decompose_mem_address (&ad
, op
);
401 address_eliminator
eliminator (&ad
);
402 return constraint_satisfied_p (op
, constraint
);
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
408 satisfies_address_constraint_p (struct address_info
*ad
,
409 enum constraint_num constraint
)
411 address_eliminator
eliminator (ad
);
412 return constraint_satisfied_p (*ad
->outer
, constraint
);
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
418 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
420 struct address_info ad
;
422 decompose_lea_address (&ad
, &op
);
423 return satisfies_address_constraint_p (&ad
, constraint
);
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
430 lra_init_equiv (void)
432 ira_expand_reg_equiv ();
433 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
437 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
438 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
439 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
440 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
444 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
450 update_equiv (int regno
)
454 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
455 ira_reg_equiv
[regno
].memory
456 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
458 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].invariant
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
472 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv
[regno
].defined_p
474 || ! ira_reg_equiv
[regno
].profitable_p
475 || lra_get_regno_hard_regno (regno
) >= 0)
477 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
479 if (targetm
.cannot_substitute_mem_equiv_p (res
))
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
501 false, false, 0, true);
504 /* Set up curr_operand_mode. */
506 init_curr_operand_mode (void)
508 int nop
= curr_static_id
->n_operands
;
509 for (int i
= 0; i
< nop
; i
++)
511 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
512 if (mode
== VOIDmode
)
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
519 mode
= curr_static_id
->operand
[i
].mode
;
521 curr_operand_mode
[i
] = mode
;
527 /* The page contains code to reuse input reloads. */
529 /* Structure describes input reload of the current insns. */
532 /* True for input reload of matched operands. */
534 /* Reloaded value. */
536 /* Reload pseudo used. */
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num
;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
546 /* Initiate data concerning reuse of input reloads for the current
549 init_curr_insn_input_reloads (void)
551 curr_insn_input_reloads_num
= 0;
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
562 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
563 enum reg_class rclass
, bool in_subreg_p
,
564 const char *title
, rtx
*result_reg
)
567 enum reg_class new_class
;
568 bool unique_p
= false;
573 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original
))
579 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
581 if (! curr_insn_input_reloads
[i
].match_p
582 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
583 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
585 rtx reg
= curr_insn_input_reloads
[i
].reg
;
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg
) != mode
)
594 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg
)),
595 GET_MODE_SIZE (mode
)))
597 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
598 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
602 if (lra_dump_file
!= NULL
)
604 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
605 dump_value_slim (lra_dump_file
, original
, 1);
607 if (new_class
!= lra_get_allocno_class (regno
))
608 lra_change_class (regno
, new_class
, ", change to", false);
609 if (lra_dump_file
!= NULL
)
610 fprintf (lra_dump_file
, "\n");
613 /* If we have an input reload with a different mode, make sure it
614 will get a different hard reg. */
615 else if (REG_P (original
)
616 && REG_P (curr_insn_input_reloads
[i
].input
)
617 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
618 && (GET_MODE (original
)
619 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
622 *result_reg
= (unique_p
623 ? lra_create_new_reg_with_unique_value
624 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
625 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
626 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
627 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
628 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
634 /* The page contains code to extract memory address parts. */
636 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
638 ok_for_index_p_nonstrict (rtx reg
)
640 unsigned regno
= REGNO (reg
);
642 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
645 /* A version of regno_ok_for_base_p for use here, when all pseudos
646 should count as OK. Arguments as for regno_ok_for_base_p. */
648 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
649 enum rtx_code outer_code
, enum rtx_code index_code
)
651 unsigned regno
= REGNO (reg
);
653 if (regno
>= FIRST_PSEUDO_REGISTER
)
655 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
660 /* The page contains major code to choose the current insn alternative
661 and generate reloads for it. */
663 /* Return the offset from REGNO of the least significant register
666 This function is used to tell whether two registers satisfy
667 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
669 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
670 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
672 lra_constraint_offset (int regno
, machine_mode mode
)
674 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
676 scalar_int_mode int_mode
;
678 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
679 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
680 return hard_regno_nregs (regno
, mode
) - 1;
684 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
685 if they are the same hard reg, and has special hacks for
686 auto-increment and auto-decrement. This is specifically intended for
687 process_alt_operands to use in determining whether two operands
688 match. X is the operand whose number is the lower of the two.
690 It is supposed that X is the output operand and Y is the input
691 operand. Y_HARD_REGNO is the final hard regno of register Y or
692 register in subreg Y as we know it now. Otherwise, it is a
695 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
698 RTX_CODE code
= GET_CODE (x
);
703 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
704 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
708 i
= get_hard_regno (x
, false);
712 if ((j
= y_hard_regno
) < 0)
715 i
+= lra_constraint_offset (i
, GET_MODE (x
));
716 j
+= lra_constraint_offset (j
, GET_MODE (y
));
721 /* If two operands must match, because they are really a single
722 operand of an assembler insn, then two post-increments are invalid
723 because the assembler insn would increment only once. On the
724 other hand, a post-increment matches ordinary indexing if the
725 post-increment is the output operand. */
726 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
727 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
729 /* Two pre-increments are invalid because the assembler insn would
730 increment only once. On the other hand, a pre-increment matches
731 ordinary indexing if the pre-increment is the input operand. */
732 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
733 || GET_CODE (y
) == PRE_MODIFY
)
734 return operands_match_p (x
, XEXP (y
, 0), -1);
738 if (code
== REG
&& REG_P (y
))
739 return REGNO (x
) == REGNO (y
);
741 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
742 && x
== SUBREG_REG (y
))
744 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
745 && SUBREG_REG (x
) == y
)
748 /* Now we have disposed of all the cases in which different rtx
750 if (code
!= GET_CODE (y
))
753 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
754 if (GET_MODE (x
) != GET_MODE (y
))
763 return label_ref_label (x
) == label_ref_label (y
);
765 return XSTR (x
, 0) == XSTR (y
, 0);
771 /* Compare the elements. If any pair of corresponding elements fail
772 to match, return false for the whole things. */
774 fmt
= GET_RTX_FORMAT (code
);
775 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
781 if (XWINT (x
, i
) != XWINT (y
, i
))
786 if (XINT (x
, i
) != XINT (y
, i
))
791 if (maybe_ne (SUBREG_BYTE (x
), SUBREG_BYTE (y
)))
796 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
805 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
807 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
809 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
815 /* It is believed that rtx's at this level will never
816 contain anything but integers and other rtx's, except for
817 within LABEL_REFs and SYMBOL_REFs. */
825 /* True if X is a constant that can be forced into the constant pool.
826 MODE is the mode of the operand, or VOIDmode if not known. */
827 #define CONST_POOL_OK_P(MODE, X) \
828 ((MODE) != VOIDmode \
830 && GET_CODE (X) != HIGH \
831 && GET_MODE_SIZE (MODE).is_constant () \
832 && !targetm.cannot_force_const_mem (MODE, X))
834 /* True if C is a non-empty register class that has too few registers
835 to be safely used as a reload target class. */
836 #define SMALL_REGISTER_CLASS_P(C) \
837 (ira_class_hard_regs_num [(C)] == 1 \
838 || (ira_class_hard_regs_num [(C)] >= 1 \
839 && targetm.class_likely_spilled_p (C)))
841 /* If REG is a reload pseudo, try to make its class satisfying CL. */
843 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
845 enum reg_class rclass
;
847 /* Do not make more accurate class from reloads generated. They are
848 mostly moves with a lot of constraints. Making more accurate
849 class may results in very narrow class and impossibility of find
850 registers for several reloads of one insn. */
851 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
853 if (GET_CODE (reg
) == SUBREG
)
854 reg
= SUBREG_REG (reg
);
855 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
857 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
858 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
861 /* Searches X for any reference to a reg with the same value as REGNO,
862 returning the rtx of the reference found if any. Otherwise,
865 regno_val_use_in (unsigned int regno
, rtx x
)
871 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
874 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
875 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
879 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
882 else if (fmt
[i
] == 'E')
883 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
884 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
891 /* Return true if all current insn non-output operands except INS (it
892 has a negaitve end marker) do not use pseudos with the same value
895 check_conflict_input_operands (int regno
, signed char *ins
)
898 int n_operands
= curr_static_id
->n_operands
;
900 for (int nop
= 0; nop
< n_operands
; nop
++)
901 if (! curr_static_id
->operand
[nop
].is_operator
902 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
904 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
908 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
914 /* Generate reloads for matching OUT and INS (array of input operand
915 numbers with end marker -1) with reg class GOAL_CLASS, considering
916 output operands OUTS (similar array to INS) needing to be in different
917 registers. Add input and output reloads correspondingly to the lists
918 *BEFORE and *AFTER. OUT might be negative. In this case we generate
919 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
920 that the output operand is early clobbered for chosen alternative. */
922 match_reload (signed char out
, signed char *ins
, signed char *outs
,
923 enum reg_class goal_class
, rtx_insn
**before
,
924 rtx_insn
**after
, bool early_clobber_p
)
928 rtx new_in_reg
, new_out_reg
, reg
;
929 machine_mode inmode
, outmode
;
930 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
931 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
933 inmode
= curr_operand_mode
[ins
[0]];
934 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
935 push_to_sequence (*before
);
936 if (inmode
!= outmode
)
938 /* process_alt_operands has already checked that the mode sizes
940 if (partial_subreg_p (outmode
, inmode
))
943 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
945 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
946 LRA_SUBREG_P (new_out_reg
) = 1;
947 /* If the input reg is dying here, we can use the same hard
948 register for REG and IN_RTX. We do it only for original
949 pseudos as reload pseudos can die although original
950 pseudos still live where reload pseudos dies. */
951 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
952 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
954 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
955 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
960 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
962 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
963 /* NEW_IN_REG is non-paradoxical subreg. We don't want
964 NEW_OUT_REG living above. We add clobber clause for
965 this. This is just a temporary clobber. We can remove
966 it at the end of LRA work. */
967 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
968 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
969 LRA_SUBREG_P (new_in_reg
) = 1;
970 if (GET_CODE (in_rtx
) == SUBREG
)
972 rtx subreg_reg
= SUBREG_REG (in_rtx
);
974 /* If SUBREG_REG is dying here and sub-registers IN_RTX
975 and NEW_IN_REG are similar, we can use the same hard
976 register for REG and SUBREG_REG. */
977 if (REG_P (subreg_reg
)
978 && (int) REGNO (subreg_reg
) < lra_new_regno_start
979 && GET_MODE (subreg_reg
) == outmode
980 && known_eq (SUBREG_BYTE (in_rtx
), SUBREG_BYTE (new_in_reg
))
981 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
982 && (! early_clobber_p
983 || check_conflict_input_operands (REGNO (subreg_reg
),
985 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
991 /* Pseudos have values -- see comments for lra_reg_info.
992 Different pseudos with the same value do not conflict even if
993 they live in the same place. When we create a pseudo we
994 assign value of original pseudo (if any) from which we
995 created the new pseudo. If we create the pseudo from the
996 input pseudo, the new pseudo will have no conflict with the
997 input pseudo which is wrong when the input pseudo lives after
998 the insn and as the new pseudo value is changed by the insn
999 output. Therefore we create the new pseudo from the output
1000 except the case when we have single matched dying input
1003 We cannot reuse the current output register because we might
1004 have a situation like "a <- a op b", where the constraints
1005 force the second input operand ("b") to match the output
1006 operand ("a"). "b" must then be copied into a new register
1007 so that it doesn't clobber the current value of "a".
1009 We can not use the same value if the output pseudo is
1010 early clobbered or the input pseudo is mentioned in the
1011 output, e.g. as an address part in memory, because
1012 output reload will actually extend the pseudo liveness.
1013 We don't care about eliminable hard regs here as we are
1014 interesting only in pseudos. */
1016 /* Matching input's register value is the same as one of the other
1017 output operand. Output operands in a parallel insn must be in
1018 different registers. */
1019 out_conflict
= false;
1022 for (i
= 0; outs
[i
] >= 0; i
++)
1024 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1025 if (REG_P (other_out_rtx
)
1026 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1029 out_conflict
= true;
1035 new_in_reg
= new_out_reg
1036 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1037 && (int) REGNO (in_rtx
) < lra_new_regno_start
1038 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1039 && (! early_clobber_p
1040 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1042 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1044 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1045 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1048 /* In operand can be got from transformations before processing insn
1049 constraints. One example of such transformations is subreg
1050 reloading (see function simplify_operand_subreg). The new
1051 pseudos created by the transformations might have inaccurate
1052 class (ALL_REGS) and we should make their classes more
1054 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1055 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1056 *before
= get_insns ();
1058 /* Add the new pseudo to consider values of subsequent input reload
1060 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1061 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1062 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1063 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1064 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1067 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1068 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1069 *curr_id
->operand_loc
[in
] = new_in_reg
;
1071 lra_update_dups (curr_id
, ins
);
1074 /* See a comment for the input operand above. */
1075 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1076 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1079 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1081 *after
= get_insns ();
1084 *curr_id
->operand_loc
[out
] = new_out_reg
;
1085 lra_update_dup (curr_id
, out
);
1088 /* Return register class which is union of all reg classes in insn
1089 constraint alternative string starting with P. */
1090 static enum reg_class
1091 reg_class_from_constraints (const char *p
)
1094 enum reg_class op_class
= NO_REGS
;
1097 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1104 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1108 enum constraint_num cn
= lookup_constraint (p
);
1109 enum reg_class cl
= reg_class_for_constraint (cn
);
1112 if (insn_extra_address_constraint (cn
))
1114 = (reg_class_subunion
1115 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1116 ADDRESS
, SCRATCH
)]);
1120 op_class
= reg_class_subunion
[op_class
][cl
];
1123 while ((p
+= len
), c
);
1127 /* If OP is a register, return the class of the register as per
1128 get_reg_class, otherwise return NO_REGS. */
1129 static inline enum reg_class
1130 get_op_class (rtx op
)
1132 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1135 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1136 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1137 SUBREG for VAL to make them equal. */
1139 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1141 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1143 /* Usually size of mem_pseudo is greater than val size but in
1144 rare cases it can be less as it can be defined by target
1145 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1148 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1149 GET_CODE (val
) == SUBREG
1150 ? SUBREG_REG (val
) : val
);
1151 LRA_SUBREG_P (val
) = 1;
1155 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1156 LRA_SUBREG_P (mem_pseudo
) = 1;
1159 return to_p
? gen_move_insn (mem_pseudo
, val
)
1160 : gen_move_insn (val
, mem_pseudo
);
1163 /* Process a special case insn (register move), return true if we
1164 don't need to process it anymore. INSN should be a single set
1165 insn. Set up that RTL was changed through CHANGE_P and that hook
1166 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1169 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1172 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1174 enum reg_class dclass
, sclass
, secondary_class
;
1175 secondary_reload_info sri
;
1177 lra_assert (curr_insn_set
!= NULL_RTX
);
1178 dreg
= dest
= SET_DEST (curr_insn_set
);
1179 sreg
= src
= SET_SRC (curr_insn_set
);
1180 if (GET_CODE (dest
) == SUBREG
)
1181 dreg
= SUBREG_REG (dest
);
1182 if (GET_CODE (src
) == SUBREG
)
1183 sreg
= SUBREG_REG (src
);
1184 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1186 sclass
= dclass
= NO_REGS
;
1188 dclass
= get_reg_class (REGNO (dreg
));
1189 gcc_assert (dclass
< LIM_REG_CLASSES
);
1190 if (dclass
== ALL_REGS
)
1191 /* ALL_REGS is used for new pseudos created by transformations
1192 like reload of SUBREG_REG (see function
1193 simplify_operand_subreg). We don't know their class yet. We
1194 should figure out the class from processing the insn
1195 constraints not in this fast path function. Even if ALL_REGS
1196 were a right class for the pseudo, secondary_... hooks usually
1197 are not define for ALL_REGS. */
1200 sclass
= get_reg_class (REGNO (sreg
));
1201 gcc_assert (sclass
< LIM_REG_CLASSES
);
1202 if (sclass
== ALL_REGS
)
1203 /* See comments above. */
1205 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1207 if (targetm
.secondary_memory_needed (GET_MODE (src
), sclass
, dclass
)
1208 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1210 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1215 if (! REG_P (dreg
) || ! REG_P (sreg
))
1217 sri
.prev_sri
= NULL
;
1218 sri
.icode
= CODE_FOR_nothing
;
1220 secondary_class
= NO_REGS
;
1221 /* Set up hard register for a reload pseudo for hook
1222 secondary_reload because some targets just ignore unassigned
1223 pseudos in the hook. */
1224 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1226 dregno
= REGNO (dreg
);
1227 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1231 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1233 sregno
= REGNO (sreg
);
1234 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1238 if (sclass
!= NO_REGS
)
1240 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1241 (reg_class_t
) sclass
,
1242 GET_MODE (src
), &sri
);
1243 if (sclass
== NO_REGS
1244 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1245 && dclass
!= NO_REGS
))
1247 enum reg_class old_sclass
= secondary_class
;
1248 secondary_reload_info old_sri
= sri
;
1250 sri
.prev_sri
= NULL
;
1251 sri
.icode
= CODE_FOR_nothing
;
1254 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1255 (reg_class_t
) dclass
,
1256 GET_MODE (src
), &sri
);
1257 /* Check the target hook consistency. */
1259 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1260 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1261 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1264 reg_renumber
[sregno
] = -1;
1266 reg_renumber
[dregno
] = -1;
1267 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1271 if (secondary_class
!= NO_REGS
)
1272 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1276 if (sri
.icode
== CODE_FOR_nothing
)
1277 lra_emit_move (new_reg
, src
);
1280 enum reg_class scratch_class
;
1282 scratch_class
= (reg_class_from_constraints
1283 (insn_data
[sri
.icode
].operand
[2].constraint
));
1284 scratch_reg
= (lra_create_new_reg_with_unique_value
1285 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1286 scratch_class
, "scratch"));
1287 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1290 before
= get_insns ();
1292 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1293 if (new_reg
!= NULL_RTX
)
1294 SET_SRC (curr_insn_set
) = new_reg
;
1297 if (lra_dump_file
!= NULL
)
1299 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1300 dump_insn_slim (lra_dump_file
, curr_insn
);
1302 lra_set_insn_deleted (curr_insn
);
1308 /* The following data describe the result of process_alt_operands.
1309 The data are used in curr_insn_transform to generate reloads. */
1311 /* The chosen reg classes which should be used for the corresponding
1313 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1314 /* True if the operand should be the same as another operand and that
1315 other operand does not need a reload. */
1316 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1317 /* True if the operand does not need a reload. */
1318 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1319 /* True if the operand can be offsetable memory. */
1320 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1321 /* The number of an operand to which given operand can be matched to. */
1322 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1323 /* The number of elements in the following array. */
1324 static int goal_alt_dont_inherit_ops_num
;
1325 /* Numbers of operands whose reload pseudos should not be inherited. */
1326 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1327 /* True if the insn commutative operands should be swapped. */
1328 static bool goal_alt_swapped
;
1329 /* The chosen insn alternative. */
1330 static int goal_alt_number
;
1332 /* True if the corresponding operand is the result of an equivalence
1334 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1336 /* The following five variables are used to choose the best insn
1337 alternative. They reflect final characteristics of the best
1340 /* Number of necessary reloads and overall cost reflecting the
1341 previous value and other unpleasantness of the best alternative. */
1342 static int best_losers
, best_overall
;
1343 /* Overall number hard registers used for reloads. For example, on
1344 some targets we need 2 general registers to reload DFmode and only
1345 one floating point register. */
1346 static int best_reload_nregs
;
1347 /* Overall number reflecting distances of previous reloading the same
1348 value. The distances are counted from the current BB start. It is
1349 used to improve inheritance chances. */
1350 static int best_reload_sum
;
1352 /* True if the current insn should have no correspondingly input or
1354 static bool no_input_reloads_p
, no_output_reloads_p
;
1356 /* True if we swapped the commutative operands in the current
1358 static int curr_swapped
;
1360 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1361 register of class CL. Add any input reloads to list BEFORE. AFTER
1362 is nonnull if *LOC is an automodified value; handle that case by
1363 adding the required output reloads to list AFTER. Return true if
1364 the RTL was changed.
1366 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1367 register. Return false if the address register is correct. */
1369 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1373 enum reg_class rclass
, new_class
;
1377 bool subreg_p
, before_p
= false;
1379 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1382 reg
= SUBREG_REG (*loc
);
1383 mode
= GET_MODE (reg
);
1385 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1386 between two registers with different classes, but there normally will
1387 be "mov" which transfers element of vector register into the general
1388 register, and this normally will be a subreg which should be reloaded
1389 as a whole. This is particularly likely to be triggered when
1390 -fno-split-wide-types specified. */
1392 || in_class_p (reg
, cl
, &new_class
)
1393 || known_le (GET_MODE_SIZE (mode
), GET_MODE_SIZE (ptr_mode
)))
1394 loc
= &SUBREG_REG (*loc
);
1398 mode
= GET_MODE (reg
);
1403 /* Always reload memory in an address even if the target supports
1405 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1410 regno
= REGNO (reg
);
1411 rclass
= get_reg_class (regno
);
1413 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1415 if (lra_dump_file
!= NULL
)
1417 fprintf (lra_dump_file
,
1418 "Changing pseudo %d in address of insn %u on equiv ",
1419 REGNO (reg
), INSN_UID (curr_insn
));
1420 dump_value_slim (lra_dump_file
, *loc
, 1);
1421 fprintf (lra_dump_file
, "\n");
1423 *loc
= copy_rtx (*loc
);
1425 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1430 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1431 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1434 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1438 lra_change_class (regno
, new_class
, " Change to", true);
1446 push_to_sequence (*before
);
1447 lra_emit_move (new_reg
, reg
);
1448 *before
= get_insns ();
1455 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1457 *after
= get_insns ();
1463 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1464 the insn to be inserted before curr insn. AFTER returns the
1465 the insn to be inserted after curr insn. ORIGREG and NEWREG
1466 are the original reg and new reg for reload. */
1468 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1473 push_to_sequence (*before
);
1474 lra_emit_move (newreg
, origreg
);
1475 *before
= get_insns ();
1481 lra_emit_move (origreg
, newreg
);
1483 *after
= get_insns ();
1488 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1489 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1491 /* Make reloads for subreg in operand NOP with internal subreg mode
1492 REG_MODE, add new reloads for further processing. Return true if
1493 any change was done. */
1495 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1498 rtx_insn
*before
, *after
;
1499 machine_mode mode
, innermode
;
1501 rtx operand
= *curr_id
->operand_loc
[nop
];
1502 enum reg_class regclass
;
1505 before
= after
= NULL
;
1507 if (GET_CODE (operand
) != SUBREG
)
1510 mode
= GET_MODE (operand
);
1511 reg
= SUBREG_REG (operand
);
1512 innermode
= GET_MODE (reg
);
1513 type
= curr_static_id
->operand
[nop
].type
;
1516 const bool addr_was_valid
1517 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1518 alter_subreg (curr_id
->operand_loc
[nop
], false);
1519 rtx subst
= *curr_id
->operand_loc
[nop
];
1520 lra_assert (MEM_P (subst
));
1523 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1524 MEM_ADDR_SPACE (subst
))
1525 || ((get_constraint_type (lookup_constraint
1526 (curr_static_id
->operand
[nop
].constraint
))
1527 != CT_SPECIAL_MEMORY
)
1528 /* We still can reload address and if the address is
1529 valid, we can remove subreg without reloading its
1531 && valid_address_p (GET_MODE (subst
),
1533 [ira_class_hard_regs
1534 [base_reg_class (GET_MODE (subst
),
1535 MEM_ADDR_SPACE (subst
),
1536 ADDRESS
, SCRATCH
)][0]],
1537 MEM_ADDR_SPACE (subst
))))
1539 /* If we change the address for a paradoxical subreg of memory, the
1540 new address might violate the necessary alignment or the access
1541 might be slow; take this into consideration. We need not worry
1542 about accesses beyond allocated memory for paradoxical memory
1543 subregs as we don't substitute such equiv memory (see processing
1544 equivalences in function lra_constraints) and because for spilled
1545 pseudos we allocate stack memory enough for the biggest
1546 corresponding paradoxical subreg.
1548 However, do not blindly simplify a (subreg (mem ...)) for
1549 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1550 data into a register when the inner is narrower than outer or
1551 missing important data from memory when the inner is wider than
1552 outer. This rule only applies to modes that are no wider than
1554 if (!(maybe_ne (GET_MODE_PRECISION (mode
),
1555 GET_MODE_PRECISION (innermode
))
1556 && known_le (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
1557 && known_le (GET_MODE_SIZE (innermode
), UNITS_PER_WORD
)
1558 && WORD_REGISTER_OPERATIONS
)
1559 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1560 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1561 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1562 && targetm
.slow_unaligned_access (innermode
,
1566 *curr_id
->operand_loc
[nop
] = operand
;
1568 /* But if the address was not valid, we cannot reload the MEM without
1569 reloading the address first. */
1570 if (!addr_was_valid
)
1571 process_address (nop
, false, &before
, &after
);
1573 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1574 enum reg_class rclass
1575 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1576 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1577 reg
, rclass
, TRUE
, "slow mem", &new_reg
))
1579 bool insert_before
, insert_after
;
1580 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1582 insert_before
= (type
!= OP_OUT
1583 || partial_subreg_p (mode
, innermode
));
1584 insert_after
= type
!= OP_IN
;
1585 insert_move_for_subreg (insert_before
? &before
: NULL
,
1586 insert_after
? &after
: NULL
,
1589 SUBREG_REG (operand
) = new_reg
;
1591 /* Convert to MODE. */
1594 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1595 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1596 rclass
, TRUE
, "slow mem", &new_reg
))
1598 bool insert_before
, insert_after
;
1599 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1601 insert_before
= type
!= OP_OUT
;
1602 insert_after
= type
!= OP_IN
;
1603 insert_move_for_subreg (insert_before
? &before
: NULL
,
1604 insert_after
? &after
: NULL
,
1607 *curr_id
->operand_loc
[nop
] = new_reg
;
1608 lra_process_new_insns (curr_insn
, before
, after
,
1609 "Inserting slow mem reload");
1613 /* If the address was valid and became invalid, prefer to reload
1614 the memory. Typical case is when the index scale should
1615 correspond the memory. */
1616 *curr_id
->operand_loc
[nop
] = operand
;
1617 /* Do not return false here as the MEM_P (reg) will be processed
1618 later in this function. */
1620 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1622 alter_subreg (curr_id
->operand_loc
[nop
], false);
1625 else if (CONSTANT_P (reg
))
1627 /* Try to simplify subreg of constant. It is usually result of
1628 equivalence substitution. */
1629 if (innermode
== VOIDmode
1630 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1631 innermode
= curr_static_id
->operand
[nop
].mode
;
1632 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1633 SUBREG_BYTE (operand
))) != NULL_RTX
)
1635 *curr_id
->operand_loc
[nop
] = new_reg
;
1639 /* Put constant into memory when we have mixed modes. It generates
1640 a better code in most cases as it does not need a secondary
1641 reload memory. It also prevents LRA looping when LRA is using
1642 secondary reload memory again and again. */
1643 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1644 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1646 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1647 alter_subreg (curr_id
->operand_loc
[nop
], false);
1650 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1651 if there may be a problem accessing OPERAND in the outer
1654 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1655 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1656 /* Don't reload paradoxical subregs because we could be looping
1657 having repeatedly final regno out of hard regs range. */
1658 && (hard_regno_nregs (hard_regno
, innermode
)
1659 >= hard_regno_nregs (hard_regno
, mode
))
1660 && simplify_subreg_regno (hard_regno
, innermode
,
1661 SUBREG_BYTE (operand
), mode
) < 0
1662 /* Don't reload subreg for matching reload. It is actually
1663 valid subreg in LRA. */
1664 && ! LRA_SUBREG_P (operand
))
1665 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1667 enum reg_class rclass
;
1670 /* There is a big probability that we will get the same class
1671 for the new pseudo and we will get the same insn which
1672 means infinite looping. So spill the new pseudo. */
1675 /* The class will be defined later in curr_insn_transform. */
1677 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1679 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1680 rclass
, TRUE
, "subreg reg", &new_reg
))
1682 bool insert_before
, insert_after
;
1683 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1685 insert_before
= (type
!= OP_OUT
1686 || read_modify_subreg_p (operand
));
1687 insert_after
= (type
!= OP_IN
);
1688 insert_move_for_subreg (insert_before
? &before
: NULL
,
1689 insert_after
? &after
: NULL
,
1692 SUBREG_REG (operand
) = new_reg
;
1693 lra_process_new_insns (curr_insn
, before
, after
,
1694 "Inserting subreg reload");
1697 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1698 IRA allocates hardreg to the inner pseudo reg according to its mode
1699 instead of the outermode, so the size of the hardreg may not be enough
1700 to contain the outermode operand, in that case we may need to insert
1701 reload for the reg. For the following two types of paradoxical subreg,
1702 we need to insert reload:
1703 1. If the op_type is OP_IN, and the hardreg could not be paired with
1704 other hardreg to contain the outermode operand
1705 (checked by in_hard_reg_set_p), we need to insert the reload.
1706 2. If the op_type is OP_OUT or OP_INOUT.
1708 Here is a paradoxical subreg example showing how the reload is generated:
1710 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1711 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1713 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1714 here, if reg107 is assigned to hardreg R15, because R15 is the last
1715 hardreg, compiler cannot find another hardreg to pair with R15 to
1716 contain TImode data. So we insert a TImode reload reg180 for it.
1717 After reload is inserted:
1719 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1720 (reg:DI 107 [ __comp ])) -1
1721 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1722 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1724 Two reload hard registers will be allocated to reg180 to save TImode data
1726 else if (REG_P (reg
)
1727 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1728 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1729 && (hard_regno_nregs (hard_regno
, innermode
)
1730 < hard_regno_nregs (hard_regno
, mode
))
1731 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1733 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1736 /* The class will be defined later in curr_insn_transform. */
1737 enum reg_class rclass
1738 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1740 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1741 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1744 bool insert_before
, insert_after
;
1746 PUT_MODE (new_reg
, mode
);
1747 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1748 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1750 insert_before
= (type
!= OP_OUT
);
1751 insert_after
= (type
!= OP_IN
);
1752 insert_move_for_subreg (insert_before
? &before
: NULL
,
1753 insert_after
? &after
: NULL
,
1756 SUBREG_REG (operand
) = new_reg
;
1757 lra_process_new_insns (curr_insn
, before
, after
,
1758 "Inserting paradoxical subreg reload");
1764 /* Return TRUE if X refers for a hard register from SET. */
1766 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1768 int i
, j
, x_hard_regno
;
1775 code
= GET_CODE (x
);
1776 mode
= GET_MODE (x
);
1779 mode
= wider_subreg_mode (x
);
1781 code
= GET_CODE (x
);
1786 x_hard_regno
= get_hard_regno (x
, true);
1787 return (x_hard_regno
>= 0
1788 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1792 struct address_info ad
;
1794 decompose_mem_address (&ad
, x
);
1795 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1797 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1800 fmt
= GET_RTX_FORMAT (code
);
1801 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1805 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1808 else if (fmt
[i
] == 'E')
1810 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1811 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1818 /* Return true if OP is a spilled pseudo. */
1820 spilled_pseudo_p (rtx op
)
1823 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1826 /* Return true if X is a general constant. */
1828 general_constant_p (rtx x
)
1830 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1834 reg_in_class_p (rtx reg
, enum reg_class cl
)
1837 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1838 return in_class_p (reg
, cl
, NULL
);
1841 /* Return true if SET of RCLASS contains no hard regs which can be
1844 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1850 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1851 COPY_HARD_REG_SET (temp
, set
);
1852 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1853 return (hard_reg_set_subset_p
1854 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1858 /* Used to check validity info about small class input operands. It
1859 should be incremented at start of processing an insn
1861 static unsigned int curr_small_class_check
= 0;
1863 /* Update number of used inputs of class OP_CLASS for operand NOP.
1864 Return true if we have more such class operands than the number of
1867 update_and_check_small_class_inputs (int nop
, enum reg_class op_class
)
1869 static unsigned int small_class_check
[LIM_REG_CLASSES
];
1870 static int small_class_input_nums
[LIM_REG_CLASSES
];
1872 if (SMALL_REGISTER_CLASS_P (op_class
)
1873 /* We are interesting in classes became small because of fixing
1874 some hard regs, e.g. by an user through GCC options. */
1875 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
1877 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
1878 || curr_static_id
->operand
[nop
].early_clobber
))
1880 if (small_class_check
[op_class
] == curr_small_class_check
)
1881 small_class_input_nums
[op_class
]++;
1884 small_class_check
[op_class
] = curr_small_class_check
;
1885 small_class_input_nums
[op_class
] = 1;
1887 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
1893 /* Major function to choose the current insn alternative and what
1894 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1895 negative we should consider only this alternative. Return false if
1896 we can not choose the alternative or find how to reload the
1899 process_alt_operands (int only_alternative
)
1902 int nop
, overall
, nalt
;
1903 int n_alternatives
= curr_static_id
->n_alternatives
;
1904 int n_operands
= curr_static_id
->n_operands
;
1905 /* LOSERS counts the operands that don't fit this alternative and
1906 would require loading. */
1909 /* REJECT is a count of how undesirable this alternative says it is
1910 if any reloading is required. If the alternative matches exactly
1911 then REJECT is ignored, but otherwise it gets this much counted
1912 against it in addition to the reloading needed. */
1914 /* This is defined by '!' or '?' alternative constraint and added to
1915 reject. But in some cases it can be ignored. */
1918 /* The number of elements in the following array. */
1919 int early_clobbered_regs_num
;
1920 /* Numbers of operands which are early clobber registers. */
1921 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1922 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1923 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1924 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1925 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1926 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1927 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1928 /* The number of elements in the following array. */
1929 int curr_alt_dont_inherit_ops_num
;
1930 /* Numbers of operands whose reload pseudos should not be inherited. */
1931 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1933 /* The register when the operand is a subreg of register, otherwise the
1935 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1936 /* The register if the operand is a register or subreg of register,
1938 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1939 int hard_regno
[MAX_RECOG_OPERANDS
];
1940 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1941 int reload_nregs
, reload_sum
;
1945 /* Calculate some data common for all alternatives to speed up the
1947 for (nop
= 0; nop
< n_operands
; nop
++)
1951 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1952 /* The real hard regno of the operand after the allocation. */
1953 hard_regno
[nop
] = get_hard_regno (op
, true);
1955 operand_reg
[nop
] = reg
= op
;
1956 biggest_mode
[nop
] = GET_MODE (op
);
1957 if (GET_CODE (op
) == SUBREG
)
1959 biggest_mode
[nop
] = wider_subreg_mode (op
);
1960 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1963 operand_reg
[nop
] = NULL_RTX
;
1964 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1965 || ((int) REGNO (reg
)
1966 == lra_get_elimination_hard_regno (REGNO (reg
))))
1967 no_subreg_reg_operand
[nop
] = reg
;
1969 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1970 /* Just use natural mode for elimination result. It should
1971 be enough for extra constraints hooks. */
1972 = regno_reg_rtx
[hard_regno
[nop
]];
1975 /* The constraints are made of several alternatives. Each operand's
1976 constraint looks like foo,bar,... with commas separating the
1977 alternatives. The first alternatives for all operands go
1978 together, the second alternatives go together, etc.
1980 First loop over alternatives. */
1981 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1982 if (only_alternative
>= 0)
1983 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1985 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1987 /* Loop over operands for one constraint alternative. */
1988 if (!TEST_BIT (preferred
, nalt
))
1991 curr_small_class_check
++;
1992 overall
= losers
= addr_losers
= 0;
1993 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
1994 for (nop
= 0; nop
< n_operands
; nop
++)
1996 int inc
= (curr_static_id
1997 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1998 if (lra_dump_file
!= NULL
&& inc
!= 0)
1999 fprintf (lra_dump_file
,
2000 " Staticly defined alt reject+=%d\n", inc
);
2001 static_reject
+= inc
;
2003 reject
+= static_reject
;
2004 early_clobbered_regs_num
= 0;
2006 for (nop
= 0; nop
< n_operands
; nop
++)
2010 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2011 bool win
, did_match
, offmemok
, early_clobber_p
;
2012 /* false => this operand can be reloaded somehow for this
2015 /* true => this operand can be reloaded if the alternative
2018 /* True if a constant forced into memory would be OK for
2021 enum reg_class this_alternative
, this_costly_alternative
;
2022 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2023 bool this_alternative_match_win
, this_alternative_win
;
2024 bool this_alternative_offmemok
;
2027 enum constraint_num cn
;
2029 opalt_num
= nalt
* n_operands
+ nop
;
2030 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2032 /* Fast track for no constraints at all. */
2033 curr_alt
[nop
] = NO_REGS
;
2034 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2035 curr_alt_win
[nop
] = true;
2036 curr_alt_match_win
[nop
] = false;
2037 curr_alt_offmemok
[nop
] = false;
2038 curr_alt_matches
[nop
] = -1;
2042 op
= no_subreg_reg_operand
[nop
];
2043 mode
= curr_operand_mode
[nop
];
2045 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2048 early_clobber_p
= false;
2049 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2051 this_costly_alternative
= this_alternative
= NO_REGS
;
2052 /* We update set of possible hard regs besides its class
2053 because reg class might be inaccurate. For example,
2054 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2055 is translated in HI_REGS because classes are merged by
2056 pairs and there is no accurate intermediate class. */
2057 CLEAR_HARD_REG_SET (this_alternative_set
);
2058 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2059 this_alternative_win
= false;
2060 this_alternative_match_win
= false;
2061 this_alternative_offmemok
= false;
2062 this_alternative_matches
= -1;
2064 /* An empty constraint should be excluded by the fast
2066 lra_assert (*p
!= 0 && *p
!= ',');
2069 /* Scan this alternative's specs for this operand; set WIN
2070 if the operand fits any letter in this alternative.
2071 Otherwise, clear BADOP if this operand could fit some
2072 letter after reloads, or set WINREG if this operand could
2073 fit after reloads provided the constraint allows some
2078 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2088 early_clobber_p
= true;
2092 op_reject
+= LRA_MAX_REJECT
;
2095 op_reject
+= LRA_LOSER_COST_FACTOR
;
2099 /* Ignore rest of this alternative. */
2103 case '0': case '1': case '2': case '3': case '4':
2104 case '5': case '6': case '7': case '8': case '9':
2109 m
= strtoul (p
, &end
, 10);
2112 lra_assert (nop
> m
);
2114 /* Reject matches if we don't know which operand is
2115 bigger. This situation would arguably be a bug in
2116 an .md pattern, but could also occur in a user asm. */
2117 if (!ordered_p (GET_MODE_SIZE (biggest_mode
[m
]),
2118 GET_MODE_SIZE (biggest_mode
[nop
])))
2121 this_alternative_matches
= m
;
2122 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2123 /* We are supposed to match a previous operand.
2124 If we do, we win if that one did. If we do
2125 not, count both of the operands as losers.
2126 (This is too conservative, since most of the
2127 time only a single reload insn will be needed
2128 to make the two operands win. As a result,
2129 this alternative may be rejected when it is
2130 actually desirable.) */
2132 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2133 *curr_id
->operand_loc
[m
], m_hregno
))
2135 /* We should reject matching of an early
2136 clobber operand if the matching operand is
2137 not dying in the insn. */
2138 if (! curr_static_id
->operand
[m
].early_clobber
2139 || operand_reg
[nop
] == NULL_RTX
2140 || (find_regno_note (curr_insn
, REG_DEAD
,
2142 || REGNO (op
) == REGNO (operand_reg
[m
])))
2147 /* If we are matching a non-offsettable
2148 address where an offsettable address was
2149 expected, then we must reject this
2150 combination, because we can't reload
2152 if (curr_alt_offmemok
[m
]
2153 && MEM_P (*curr_id
->operand_loc
[m
])
2154 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2159 /* Operands don't match. Both operands must
2160 allow a reload register, otherwise we
2161 cannot make them match. */
2162 if (curr_alt
[m
] == NO_REGS
)
2164 /* Retroactively mark the operand we had to
2165 match as a loser, if it wasn't already and
2166 it wasn't matched to a register constraint
2167 (e.g it might be matched by memory). */
2169 && (operand_reg
[m
] == NULL_RTX
2170 || hard_regno
[m
] < 0))
2174 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2175 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2178 /* Prefer matching earlyclobber alternative as
2179 it results in less hard regs required for
2180 the insn than a non-matching earlyclobber
2182 if (curr_static_id
->operand
[m
].early_clobber
)
2184 if (lra_dump_file
!= NULL
)
2187 " %d Matching earlyclobber alt:"
2192 /* Otherwise we prefer no matching
2193 alternatives because it gives more freedom
2195 else if (operand_reg
[nop
] == NULL_RTX
2196 || (find_regno_note (curr_insn
, REG_DEAD
,
2197 REGNO (operand_reg
[nop
]))
2200 if (lra_dump_file
!= NULL
)
2203 " %d Matching alt: reject+=2\n",
2208 /* If we have to reload this operand and some
2209 previous operand also had to match the same
2210 thing as this operand, we don't know how to do
2212 if (!match_p
|| !curr_alt_win
[m
])
2214 for (i
= 0; i
< nop
; i
++)
2215 if (curr_alt_matches
[i
] == m
)
2223 /* This can be fixed with reloads if the operand
2224 we are supposed to match can be fixed with
2227 this_alternative
= curr_alt
[m
];
2228 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2229 winreg
= this_alternative
!= NO_REGS
;
2235 || general_constant_p (op
)
2236 || spilled_pseudo_p (op
))
2242 cn
= lookup_constraint (p
);
2243 switch (get_constraint_type (cn
))
2246 cl
= reg_class_for_constraint (cn
);
2252 if (CONST_INT_P (op
)
2253 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2259 && satisfies_memory_constraint_p (op
, cn
))
2261 else if (spilled_pseudo_p (op
))
2264 /* If we didn't already win, we can reload constants
2265 via force_const_mem or put the pseudo value into
2266 memory, or make other memory by reloading the
2267 address like for 'o'. */
2268 if (CONST_POOL_OK_P (mode
, op
)
2269 || MEM_P (op
) || REG_P (op
)
2270 /* We can restore the equiv insn by a
2272 || equiv_substition_p
[nop
])
2279 /* An asm operand with an address constraint
2280 that doesn't satisfy address_operand has
2281 is_address cleared, so that we don't try to
2282 make a non-address fit. */
2283 if (!curr_static_id
->operand
[nop
].is_address
)
2285 /* If we didn't already win, we can reload the address
2286 into a base register. */
2287 if (satisfies_address_constraint_p (op
, cn
))
2289 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2295 if (constraint_satisfied_p (op
, cn
))
2299 case CT_SPECIAL_MEMORY
:
2301 && satisfies_memory_constraint_p (op
, cn
))
2303 else if (spilled_pseudo_p (op
))
2310 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2311 IOR_HARD_REG_SET (this_alternative_set
,
2312 reg_class_contents
[cl
]);
2315 this_costly_alternative
2316 = reg_class_subunion
[this_costly_alternative
][cl
];
2317 IOR_HARD_REG_SET (this_costly_alternative_set
,
2318 reg_class_contents
[cl
]);
2320 if (mode
== BLKmode
)
2325 if (hard_regno
[nop
] >= 0
2326 && in_hard_reg_set_p (this_alternative_set
,
2327 mode
, hard_regno
[nop
]))
2329 else if (hard_regno
[nop
] < 0
2330 && in_class_p (op
, this_alternative
, NULL
))
2335 if (c
!= ' ' && c
!= '\t')
2336 costly_p
= c
== '*';
2338 while ((p
+= len
), c
);
2340 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2341 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2342 /* Record which operands fit this alternative. */
2345 this_alternative_win
= true;
2346 if (operand_reg
[nop
] != NULL_RTX
)
2348 if (hard_regno
[nop
] >= 0)
2350 if (in_hard_reg_set_p (this_costly_alternative_set
,
2351 mode
, hard_regno
[nop
]))
2353 if (lra_dump_file
!= NULL
)
2354 fprintf (lra_dump_file
,
2355 " %d Costly set: reject++\n",
2362 /* Prefer won reg to spilled pseudo under other
2363 equal conditions for possibe inheritance. */
2366 if (lra_dump_file
!= NULL
)
2369 " %d Non pseudo reload: reject++\n",
2373 if (in_class_p (operand_reg
[nop
],
2374 this_costly_alternative
, NULL
))
2376 if (lra_dump_file
!= NULL
)
2379 " %d Non pseudo costly reload:"
2385 /* We simulate the behavior of old reload here.
2386 Although scratches need hard registers and it
2387 might result in spilling other pseudos, no reload
2388 insns are generated for the scratches. So it
2389 might cost something but probably less than old
2390 reload pass believes. */
2393 if (lra_dump_file
!= NULL
)
2394 fprintf (lra_dump_file
,
2395 " %d Scratch win: reject+=2\n",
2402 this_alternative_match_win
= true;
2405 int const_to_mem
= 0;
2408 reject
+= op_reject
;
2409 /* Never do output reload of stack pointer. It makes
2410 impossible to do elimination when SP is changed in
2412 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2413 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2416 /* If this alternative asks for a specific reg class, see if there
2417 is at least one allocatable register in that class. */
2419 = (this_alternative
== NO_REGS
2420 || (hard_reg_set_subset_p
2421 (reg_class_contents
[this_alternative
],
2422 lra_no_alloc_regs
)));
2424 /* For asms, verify that the class for this alternative is possible
2425 for the mode that is specified. */
2426 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2429 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2430 if (targetm
.hard_regno_mode_ok (i
, mode
)
2431 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2434 if (i
== FIRST_PSEUDO_REGISTER
)
2438 /* If this operand accepts a register, and if the
2439 register class has at least one allocatable register,
2440 then this operand can be reloaded. */
2441 if (winreg
&& !no_regs_p
)
2446 if (lra_dump_file
!= NULL
)
2447 fprintf (lra_dump_file
,
2448 " alt=%d: Bad operand -- refuse\n",
2453 if (this_alternative
!= NO_REGS
)
2455 HARD_REG_SET available_regs
;
2457 COPY_HARD_REG_SET (available_regs
,
2458 reg_class_contents
[this_alternative
]);
2459 AND_COMPL_HARD_REG_SET
2461 ira_prohibited_class_mode_regs
[this_alternative
][mode
]);
2462 AND_COMPL_HARD_REG_SET (available_regs
, lra_no_alloc_regs
);
2463 if (hard_reg_set_empty_p (available_regs
))
2465 /* There are no hard regs holding a value of given
2469 this_alternative
= NO_REGS
;
2470 if (lra_dump_file
!= NULL
)
2471 fprintf (lra_dump_file
,
2472 " %d Using memory because of"
2473 " a bad mode: reject+=2\n",
2479 if (lra_dump_file
!= NULL
)
2480 fprintf (lra_dump_file
,
2481 " alt=%d: Wrong mode -- refuse\n",
2488 /* If not assigned pseudo has a class which a subset of
2489 required reg class, it is a less costly alternative
2490 as the pseudo still can get a hard reg of necessary
2492 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2493 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2494 && ira_class_subset_p
[this_alternative
][cl
])
2496 if (lra_dump_file
!= NULL
)
2499 " %d Super set class reg: reject-=3\n", nop
);
2503 this_alternative_offmemok
= offmemok
;
2504 if (this_costly_alternative
!= NO_REGS
)
2506 if (lra_dump_file
!= NULL
)
2507 fprintf (lra_dump_file
,
2508 " %d Costly loser: reject++\n", nop
);
2511 /* If the operand is dying, has a matching constraint,
2512 and satisfies constraints of the matched operand
2513 which failed to satisfy the own constraints, most probably
2514 the reload for this operand will be gone. */
2515 if (this_alternative_matches
>= 0
2516 && !curr_alt_win
[this_alternative_matches
]
2518 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2519 && (hard_regno
[nop
] >= 0
2520 ? in_hard_reg_set_p (this_alternative_set
,
2521 mode
, hard_regno
[nop
])
2522 : in_class_p (op
, this_alternative
, NULL
)))
2524 if (lra_dump_file
!= NULL
)
2527 " %d Dying matched operand reload: reject++\n",
2533 /* Strict_low_part requires to reload the register
2534 not the sub-register. In this case we should
2535 check that a final reload hard reg can hold the
2537 if (curr_static_id
->operand
[nop
].strict_low
2539 && hard_regno
[nop
] < 0
2540 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2541 && ira_class_hard_regs_num
[this_alternative
] > 0
2542 && (!targetm
.hard_regno_mode_ok
2543 (ira_class_hard_regs
[this_alternative
][0],
2544 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2546 if (lra_dump_file
!= NULL
)
2549 " alt=%d: Strict low subreg reload -- refuse\n",
2555 if (operand_reg
[nop
] != NULL_RTX
2556 /* Output operands and matched input operands are
2557 not inherited. The following conditions do not
2558 exactly describe the previous statement but they
2559 are pretty close. */
2560 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2561 && (this_alternative_matches
< 0
2562 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2564 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2568 /* The value of reload_sum has sense only if we
2569 process insns in their order. It happens only on
2570 the first constraints sub-pass when we do most of
2572 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2573 reload_sum
+= last_reload
- bb_reload_num
;
2575 /* If this is a constant that is reloaded into the
2576 desired class by copying it to memory first, count
2577 that as another reload. This is consistent with
2578 other code and is required to avoid choosing another
2579 alternative when the constant is moved into memory.
2580 Note that the test here is precisely the same as in
2581 the code below that calls force_const_mem. */
2582 if (CONST_POOL_OK_P (mode
, op
)
2583 && ((targetm
.preferred_reload_class
2584 (op
, this_alternative
) == NO_REGS
)
2585 || no_input_reloads_p
))
2592 /* Alternative loses if it requires a type of reload not
2593 permitted for this insn. We can always reload
2594 objects with a REG_UNUSED note. */
2595 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2596 && no_output_reloads_p
2597 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2598 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2599 && no_input_reloads_p
&& ! const_to_mem
)
2600 || (this_alternative_matches
>= 0
2601 && (no_input_reloads_p
2602 || (no_output_reloads_p
2603 && (curr_static_id
->operand
2604 [this_alternative_matches
].type
!= OP_IN
)
2605 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2606 no_subreg_reg_operand
2607 [this_alternative_matches
])))))
2609 if (lra_dump_file
!= NULL
)
2612 " alt=%d: No input/otput reload -- refuse\n",
2617 /* Alternative loses if it required class pseudo can not
2618 hold value of required mode. Such insns can be
2619 described by insn definitions with mode iterators. */
2620 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2621 && ! hard_reg_set_empty_p (this_alternative_set
)
2622 /* It is common practice for constraints to use a
2623 class which does not have actually enough regs to
2624 hold the value (e.g. x86 AREG for mode requiring
2625 more one general reg). Therefore we have 2
2626 conditions to check that the reload pseudo can
2627 not hold the mode value. */
2628 && (!targetm
.hard_regno_mode_ok
2629 (ira_class_hard_regs
[this_alternative
][0],
2630 GET_MODE (*curr_id
->operand_loc
[nop
])))
2631 /* The above condition is not enough as the first
2632 reg in ira_class_hard_regs can be not aligned for
2633 multi-words mode values. */
2634 && (prohibited_class_reg_set_mode_p
2635 (this_alternative
, this_alternative_set
,
2636 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2638 if (lra_dump_file
!= NULL
)
2639 fprintf (lra_dump_file
,
2640 " alt=%d: reload pseudo for op %d "
2641 " can not hold the mode value -- refuse\n",
2646 /* Check strong discouragement of reload of non-constant
2647 into class THIS_ALTERNATIVE. */
2648 if (! CONSTANT_P (op
) && ! no_regs_p
2649 && (targetm
.preferred_reload_class
2650 (op
, this_alternative
) == NO_REGS
2651 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2652 && (targetm
.preferred_output_reload_class
2653 (op
, this_alternative
) == NO_REGS
))))
2655 if (lra_dump_file
!= NULL
)
2656 fprintf (lra_dump_file
,
2657 " %d Non-prefered reload: reject+=%d\n",
2658 nop
, LRA_MAX_REJECT
);
2659 reject
+= LRA_MAX_REJECT
;
2662 if (! (MEM_P (op
) && offmemok
)
2663 && ! (const_to_mem
&& constmemok
))
2665 /* We prefer to reload pseudos over reloading other
2666 things, since such reloads may be able to be
2667 eliminated later. So bump REJECT in other cases.
2668 Don't do this in the case where we are forcing a
2669 constant into memory and it will then win since
2670 we don't want to have a different alternative
2672 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2674 if (lra_dump_file
!= NULL
)
2677 " %d Non-pseudo reload: reject+=2\n",
2684 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2686 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2688 if (lra_dump_file
!= NULL
)
2691 " %d Small class reload: reject+=%d\n",
2692 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2693 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2697 /* We are trying to spill pseudo into memory. It is
2698 usually more costly than moving to a hard register
2699 although it might takes the same number of
2702 Non-pseudo spill may happen also. Suppose a target allows both
2703 register and memory in the operand constraint alternatives,
2704 then it's typical that an eliminable register has a substition
2705 of "base + offset" which can either be reloaded by a simple
2706 "new_reg <= base + offset" which will match the register
2707 constraint, or a similar reg addition followed by further spill
2708 to and reload from memory which will match the memory
2709 constraint, but this memory spill will be much more costly
2712 Code below increases the reject for both pseudo and non-pseudo
2715 && !(MEM_P (op
) && offmemok
)
2716 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2718 if (lra_dump_file
!= NULL
)
2721 " %d Spill %spseudo into memory: reject+=3\n",
2722 nop
, REG_P (op
) ? "" : "Non-");
2724 if (VECTOR_MODE_P (mode
))
2726 /* Spilling vectors into memory is usually more
2727 costly as they contain big values. */
2728 if (lra_dump_file
!= NULL
)
2731 " %d Spill vector pseudo: reject+=2\n",
2737 /* When we use an operand requiring memory in given
2738 alternative, the insn should write *and* read the
2739 value to/from memory it is costly in comparison with
2740 an insn alternative which does not use memory
2741 (e.g. register or immediate operand). We exclude
2742 memory operand for such case as we can satisfy the
2743 memory constraints by reloading address. */
2744 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
2746 if (lra_dump_file
!= NULL
)
2749 " Using memory insn operand %d: reject+=3\n",
2754 /* If reload requires moving value through secondary
2755 memory, it will need one more insn at least. */
2756 if (this_alternative
!= NO_REGS
2757 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2758 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2759 && targetm
.secondary_memory_needed (GET_MODE (op
), cl
,
2761 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2762 && (targetm
.secondary_memory_needed
2763 (GET_MODE (op
), this_alternative
, cl
)))))
2766 /* Input reloads can be inherited more often than output
2767 reloads can be removed, so penalize output
2769 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2771 if (lra_dump_file
!= NULL
)
2774 " %d Non input pseudo reload: reject++\n",
2779 if (MEM_P (op
) && offmemok
)
2781 else if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
2783 if (lra_dump_file
!= NULL
)
2786 " %d Input/Output reload: reject+=%d\n",
2787 nop
, LRA_LOSER_COST_FACTOR
);
2788 reject
+= LRA_LOSER_COST_FACTOR
;
2792 if (early_clobber_p
&& ! scratch_p
)
2794 if (lra_dump_file
!= NULL
)
2795 fprintf (lra_dump_file
,
2796 " %d Early clobber: reject++\n", nop
);
2799 /* ??? We check early clobbers after processing all operands
2800 (see loop below) and there we update the costs more.
2801 Should we update the cost (may be approximately) here
2802 because of early clobber register reloads or it is a rare
2803 or non-important thing to be worth to do it. */
2804 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
2805 - (addr_losers
== losers
? static_reject
: 0));
2806 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2808 if (lra_dump_file
!= NULL
)
2809 fprintf (lra_dump_file
,
2810 " alt=%d,overall=%d,losers=%d -- refuse\n",
2811 nalt
, overall
, losers
);
2815 if (update_and_check_small_class_inputs (nop
, this_alternative
))
2817 if (lra_dump_file
!= NULL
)
2818 fprintf (lra_dump_file
,
2819 " alt=%d, not enough small class regs -- refuse\n",
2823 curr_alt
[nop
] = this_alternative
;
2824 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2825 curr_alt_win
[nop
] = this_alternative_win
;
2826 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2827 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2828 curr_alt_matches
[nop
] = this_alternative_matches
;
2830 if (this_alternative_matches
>= 0
2831 && !did_match
&& !this_alternative_win
)
2832 curr_alt_win
[this_alternative_matches
] = false;
2834 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2835 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2838 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2839 /* Prevent processing non-move insns. */
2840 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2841 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2842 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2843 && REG_P (no_subreg_reg_operand
[0])
2844 && REG_P (no_subreg_reg_operand
[1])
2845 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2846 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2847 || (! curr_alt_win
[0] && curr_alt_win
[1]
2848 && REG_P (no_subreg_reg_operand
[1])
2849 /* Check that we reload memory not the memory
2851 && ! (curr_alt_offmemok
[0]
2852 && MEM_P (no_subreg_reg_operand
[0]))
2853 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2854 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2855 && REG_P (no_subreg_reg_operand
[0])
2856 /* Check that we reload memory not the memory
2858 && ! (curr_alt_offmemok
[1]
2859 && MEM_P (no_subreg_reg_operand
[1]))
2860 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2861 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2862 no_subreg_reg_operand
[1])
2863 || (targetm
.preferred_reload_class
2864 (no_subreg_reg_operand
[1],
2865 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2866 /* If it is a result of recent elimination in move
2867 insn we can transform it into an add still by
2868 using this alternative. */
2869 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
2870 /* Likewise if the source has been replaced with an
2871 equivalent value. This only happens once -- the reload
2872 will use the equivalent value instead of the register it
2873 replaces -- so there should be no danger of cycling. */
2874 && !equiv_substition_p
[1])))
2876 /* We have a move insn and a new reload insn will be similar
2877 to the current insn. We should avoid such situation as
2878 it results in LRA cycling. */
2879 if (lra_dump_file
!= NULL
)
2880 fprintf (lra_dump_file
,
2881 " Cycle danger: overall += LRA_MAX_REJECT\n");
2882 overall
+= LRA_MAX_REJECT
;
2885 curr_alt_dont_inherit_ops_num
= 0;
2886 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2888 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2889 HARD_REG_SET temp_set
;
2891 i
= early_clobbered_nops
[nop
];
2892 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2893 || hard_regno
[i
] < 0)
2895 lra_assert (operand_reg
[i
] != NULL_RTX
);
2896 clobbered_hard_regno
= hard_regno
[i
];
2897 CLEAR_HARD_REG_SET (temp_set
);
2898 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2899 first_conflict_j
= last_conflict_j
= -1;
2900 for (j
= 0; j
< n_operands
; j
++)
2902 /* We don't want process insides of match_operator and
2903 match_parallel because otherwise we would process
2904 their operands once again generating a wrong
2906 || curr_static_id
->operand
[j
].is_operator
)
2908 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2909 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2911 /* If we don't reload j-th operand, check conflicts. */
2912 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2913 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2915 if (first_conflict_j
< 0)
2916 first_conflict_j
= j
;
2917 last_conflict_j
= j
;
2919 if (last_conflict_j
< 0)
2921 /* If earlyclobber operand conflicts with another
2922 non-matching operand which is actually the same register
2923 as the earlyclobber operand, it is better to reload the
2924 another operand as an operand matching the earlyclobber
2925 operand can be also the same. */
2926 if (first_conflict_j
== last_conflict_j
2927 && operand_reg
[last_conflict_j
] != NULL_RTX
2928 && ! curr_alt_match_win
[last_conflict_j
]
2929 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2931 curr_alt_win
[last_conflict_j
] = false;
2932 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2935 /* Early clobber was already reflected in REJECT. */
2936 lra_assert (reject
> 0);
2937 if (lra_dump_file
!= NULL
)
2940 " %d Conflict early clobber reload: reject--\n",
2943 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2947 /* We need to reload early clobbered register and the
2948 matched registers. */
2949 for (j
= 0; j
< n_operands
; j
++)
2950 if (curr_alt_matches
[j
] == i
)
2952 curr_alt_match_win
[j
] = false;
2954 overall
+= LRA_LOSER_COST_FACTOR
;
2956 if (! curr_alt_match_win
[i
])
2957 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2960 /* Remember pseudos used for match reloads are never
2962 lra_assert (curr_alt_matches
[i
] >= 0);
2963 curr_alt_win
[curr_alt_matches
[i
]] = false;
2965 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2967 /* Early clobber was already reflected in REJECT. */
2968 lra_assert (reject
> 0);
2969 if (lra_dump_file
!= NULL
)
2972 " %d Matched conflict early clobber reloads: "
2976 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2979 if (lra_dump_file
!= NULL
)
2980 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2981 nalt
, overall
, losers
, reload_nregs
);
2983 /* If this alternative can be made to work by reloading, and it
2984 needs less reloading than the others checked so far, record
2985 it as the chosen goal for reloading. */
2986 if ((best_losers
!= 0 && losers
== 0)
2987 || (((best_losers
== 0 && losers
== 0)
2988 || (best_losers
!= 0 && losers
!= 0))
2989 && (best_overall
> overall
2990 || (best_overall
== overall
2991 /* If the cost of the reloads is the same,
2992 prefer alternative which requires minimal
2993 number of reload regs. */
2994 && (reload_nregs
< best_reload_nregs
2995 || (reload_nregs
== best_reload_nregs
2996 && (best_reload_sum
< reload_sum
2997 || (best_reload_sum
== reload_sum
2998 && nalt
< goal_alt_number
))))))))
3000 for (nop
= 0; nop
< n_operands
; nop
++)
3002 goal_alt_win
[nop
] = curr_alt_win
[nop
];
3003 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
3004 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
3005 goal_alt
[nop
] = curr_alt
[nop
];
3006 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
3008 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
3009 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
3010 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
3011 goal_alt_swapped
= curr_swapped
;
3012 best_overall
= overall
;
3013 best_losers
= losers
;
3014 best_reload_nregs
= reload_nregs
;
3015 best_reload_sum
= reload_sum
;
3016 goal_alt_number
= nalt
;
3019 /* Everything is satisfied. Do not process alternatives
3028 /* Make reload base reg from address AD. */
3030 base_to_reg (struct address_info
*ad
)
3034 rtx new_inner
= NULL_RTX
;
3035 rtx new_reg
= NULL_RTX
;
3037 rtx_insn
*last_insn
= get_last_insn();
3039 lra_assert (ad
->disp
== ad
->disp_term
);
3040 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3041 get_index_code (ad
));
3042 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
,
3044 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3045 ad
->disp_term
== NULL
3048 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3050 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3051 code
= recog_memoized (insn
);
3054 delete_insns_since (last_insn
);
3061 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3063 base_plus_disp_to_reg (struct address_info
*ad
, rtx disp
)
3068 lra_assert (ad
->base
== ad
->base_term
);
3069 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3070 get_index_code (ad
));
3071 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
3073 lra_emit_add (new_reg
, *ad
->base_term
, disp
);
3077 /* Make reload of index part of address AD. Return the new
3080 index_part_to_reg (struct address_info
*ad
)
3084 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3085 INDEX_REG_CLASS
, "index term");
3086 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3087 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3091 /* Return true if we can add a displacement to address AD, even if that
3092 makes the address invalid. The fix-up code requires any new address
3093 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3095 can_add_disp_p (struct address_info
*ad
)
3097 return (!ad
->autoinc_p
3098 && ad
->segment
== NULL
3099 && ad
->base
== ad
->base_term
3100 && ad
->disp
== ad
->disp_term
);
3103 /* Make equiv substitution in address AD. Return true if a substitution
3106 equiv_address_substitution (struct address_info
*ad
)
3108 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3110 HOST_WIDE_INT scale
;
3113 base_term
= strip_subreg (ad
->base_term
);
3114 if (base_term
== NULL
)
3115 base_reg
= new_base_reg
= NULL_RTX
;
3118 base_reg
= *base_term
;
3119 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3121 index_term
= strip_subreg (ad
->index_term
);
3122 if (index_term
== NULL
)
3123 index_reg
= new_index_reg
= NULL_RTX
;
3126 index_reg
= *index_term
;
3127 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3129 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3133 if (lra_dump_file
!= NULL
)
3135 fprintf (lra_dump_file
, "Changing address in insn %d ",
3136 INSN_UID (curr_insn
));
3137 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3139 if (base_reg
!= new_base_reg
)
3142 if (REG_P (new_base_reg
))
3144 *base_term
= new_base_reg
;
3147 else if (GET_CODE (new_base_reg
) == PLUS
3148 && REG_P (XEXP (new_base_reg
, 0))
3149 && poly_int_rtx_p (XEXP (new_base_reg
, 1), &offset
)
3150 && can_add_disp_p (ad
))
3153 *base_term
= XEXP (new_base_reg
, 0);
3156 if (ad
->base_term2
!= NULL
)
3157 *ad
->base_term2
= *ad
->base_term
;
3159 if (index_reg
!= new_index_reg
)
3162 if (REG_P (new_index_reg
))
3164 *index_term
= new_index_reg
;
3167 else if (GET_CODE (new_index_reg
) == PLUS
3168 && REG_P (XEXP (new_index_reg
, 0))
3169 && poly_int_rtx_p (XEXP (new_index_reg
, 1), &offset
)
3170 && can_add_disp_p (ad
)
3171 && (scale
= get_index_scale (ad
)))
3173 disp
+= offset
* scale
;
3174 *index_term
= XEXP (new_index_reg
, 0);
3178 if (maybe_ne (disp
, 0))
3180 if (ad
->disp
!= NULL
)
3181 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3184 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3185 update_address (ad
);
3189 if (lra_dump_file
!= NULL
)
3192 fprintf (lra_dump_file
, " -- no change\n");
3195 fprintf (lra_dump_file
, " on equiv ");
3196 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3197 fprintf (lra_dump_file
, "\n");
3203 /* Major function to make reloads for an address in operand NOP or
3204 check its correctness (If CHECK_ONLY_P is true). The supported
3207 1) an address that existed before LRA started, at which point it
3208 must have been valid. These addresses are subject to elimination
3209 and may have become invalid due to the elimination offset being out
3212 2) an address created by forcing a constant to memory
3213 (force_const_to_mem). The initial form of these addresses might
3214 not be valid, and it is this function's job to make them valid.
3216 3) a frame address formed from a register and a (possibly zero)
3217 constant offset. As above, these addresses might not be valid and
3218 this function must make them so.
3220 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3221 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3222 address. Return true for any RTL change.
3224 The function is a helper function which does not produce all
3225 transformations (when CHECK_ONLY_P is false) which can be
3226 necessary. It does just basic steps. To do all necessary
3227 transformations use function process_address. */
3229 process_address_1 (int nop
, bool check_only_p
,
3230 rtx_insn
**before
, rtx_insn
**after
)
3232 struct address_info ad
;
3234 HOST_WIDE_INT scale
;
3235 rtx op
= *curr_id
->operand_loc
[nop
];
3236 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3237 enum constraint_num cn
= lookup_constraint (constraint
);
3238 bool change_p
= false;
3241 && GET_MODE (op
) == BLKmode
3242 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3245 if (insn_extra_address_constraint (cn
)
3246 /* When we find an asm operand with an address constraint that
3247 doesn't satisfy address_operand to begin with, we clear
3248 is_address, so that we don't try to make a non-address fit.
3249 If the asm statement got this far, it's because other
3250 constraints are available, and we'll use them, disregarding
3251 the unsatisfiable address ones. */
3252 && curr_static_id
->operand
[nop
].is_address
)
3253 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3254 /* Do not attempt to decompose arbitrary addresses generated by combine
3255 for asm operands with loose constraints, e.g 'X'. */
3257 && !(INSN_CODE (curr_insn
) < 0
3258 && get_constraint_type (cn
) == CT_FIXED_FORM
3259 && constraint_satisfied_p (op
, cn
)))
3260 decompose_mem_address (&ad
, op
);
3261 else if (GET_CODE (op
) == SUBREG
3262 && MEM_P (SUBREG_REG (op
)))
3263 decompose_mem_address (&ad
, SUBREG_REG (op
));
3266 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3267 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3268 when INDEX_REG_CLASS is a single register class. */
3269 if (ad
.base_term
!= NULL
3270 && ad
.index_term
!= NULL
3271 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3272 && REG_P (*ad
.base_term
)
3273 && REG_P (*ad
.index_term
)
3274 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3275 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3277 std::swap (ad
.base
, ad
.index
);
3278 std::swap (ad
.base_term
, ad
.index_term
);
3281 change_p
= equiv_address_substitution (&ad
);
3282 if (ad
.base_term
!= NULL
3283 && (process_addr_reg
3284 (ad
.base_term
, check_only_p
, before
,
3286 && !(REG_P (*ad
.base_term
)
3287 && find_regno_note (curr_insn
, REG_DEAD
,
3288 REGNO (*ad
.base_term
)) != NULL_RTX
)
3290 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3291 get_index_code (&ad
)))))
3294 if (ad
.base_term2
!= NULL
)
3295 *ad
.base_term2
= *ad
.base_term
;
3297 if (ad
.index_term
!= NULL
3298 && process_addr_reg (ad
.index_term
, check_only_p
,
3299 before
, NULL
, INDEX_REG_CLASS
))
3302 /* Target hooks sometimes don't treat extra-constraint addresses as
3303 legitimate address_operands, so handle them specially. */
3304 if (insn_extra_address_constraint (cn
)
3305 && satisfies_address_constraint_p (&ad
, cn
))
3311 /* There are three cases where the shape of *AD.INNER may now be invalid:
3313 1) the original address was valid, but either elimination or
3314 equiv_address_substitution was applied and that made
3315 the address invalid.
3317 2) the address is an invalid symbolic address created by
3320 3) the address is a frame address with an invalid offset.
3322 4) the address is a frame address with an invalid base.
3324 All these cases involve a non-autoinc address, so there is no
3325 point revalidating other types. */
3326 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3329 /* Any index existed before LRA started, so we can assume that the
3330 presence and shape of the index is valid. */
3331 push_to_sequence (*before
);
3332 lra_assert (ad
.disp
== ad
.disp_term
);
3333 if (ad
.base
== NULL
)
3335 if (ad
.index
== NULL
)
3338 rtx_insn
*last
= get_last_insn ();
3340 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3342 rtx addr
= *ad
.inner
;
3344 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3347 /* addr => lo_sum (new_base, addr), case (2) above. */
3348 insn
= emit_insn (gen_rtx_SET
3350 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3351 code
= recog_memoized (insn
);
3354 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3355 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3357 /* Try to put lo_sum into register. */
3358 insn
= emit_insn (gen_rtx_SET
3360 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3361 code
= recog_memoized (insn
);
3364 *ad
.inner
= new_reg
;
3365 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3375 delete_insns_since (last
);
3380 /* addr => new_base, case (2) above. */
3381 lra_emit_move (new_reg
, addr
);
3383 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3385 insn
= NEXT_INSN (insn
))
3386 if (recog_memoized (insn
) < 0)
3388 if (insn
!= NULL_RTX
)
3390 /* Do nothing if we cannot generate right insns.
3391 This is analogous to reload pass behavior. */
3392 delete_insns_since (last
);
3396 *ad
.inner
= new_reg
;
3401 /* index * scale + disp => new base + index * scale,
3403 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3404 GET_CODE (*ad
.index
));
3406 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3407 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3408 lra_emit_move (new_reg
, *ad
.disp
);
3409 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3410 new_reg
, *ad
.index
);
3413 else if (ad
.index
== NULL
)
3418 rtx_insn
*insns
, *last_insn
;
3419 /* Try to reload base into register only if the base is invalid
3420 for the address but with valid offset, case (4) above. */
3422 new_reg
= base_to_reg (&ad
);
3424 /* base + disp => new base, cases (1) and (3) above. */
3425 /* Another option would be to reload the displacement into an
3426 index register. However, postreload has code to optimize
3427 address reloads that have the same base and different
3428 displacements, so reloading into an index register would
3429 not necessarily be a win. */
3430 if (new_reg
== NULL_RTX
)
3432 /* See if the target can split the displacement into a
3433 legitimate new displacement from a local anchor. */
3434 gcc_assert (ad
.disp
== ad
.disp_term
);
3435 poly_int64 orig_offset
;
3436 rtx offset1
, offset2
;
3437 if (poly_int_rtx_p (*ad
.disp
, &orig_offset
)
3438 && targetm
.legitimize_address_displacement (&offset1
, &offset2
,
3442 new_reg
= base_plus_disp_to_reg (&ad
, offset1
);
3443 new_reg
= gen_rtx_PLUS (GET_MODE (new_reg
), new_reg
, offset2
);
3446 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3448 insns
= get_insns ();
3449 last_insn
= get_last_insn ();
3450 /* If we generated at least two insns, try last insn source as
3451 an address. If we succeed, we generate one less insn. */
3453 && last_insn
!= insns
3454 && (set
= single_set (last_insn
)) != NULL_RTX
3455 && GET_CODE (SET_SRC (set
)) == PLUS
3456 && REG_P (XEXP (SET_SRC (set
), 0))
3457 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3459 *ad
.inner
= SET_SRC (set
);
3460 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3462 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3463 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3464 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3465 get_index_code (&ad
));
3466 regno
= REGNO (*ad
.base_term
);
3467 if (regno
>= FIRST_PSEUDO_REGISTER
3468 && cl
!= lra_get_allocno_class (regno
))
3469 lra_change_class (regno
, cl
, " Change to", true);
3470 new_reg
= SET_SRC (set
);
3471 delete_insns_since (PREV_INSN (last_insn
));
3476 *ad
.inner
= new_reg
;
3478 else if (ad
.disp_term
!= NULL
)
3480 /* base + scale * index + disp => new base + scale * index,
3482 gcc_assert (ad
.disp
== ad
.disp_term
);
3483 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3484 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3485 new_reg
, *ad
.index
);
3487 else if ((scale
= get_index_scale (&ad
)) == 1)
3489 /* The last transformation to one reg will be made in
3490 curr_insn_transform function. */
3494 else if (scale
!= 0)
3496 /* base + scale * index => base + new_reg,
3498 Index part of address may become invalid. For example, we
3499 changed pseudo on the equivalent memory and a subreg of the
3500 pseudo onto the memory of different mode for which the scale is
3502 new_reg
= index_part_to_reg (&ad
);
3503 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3504 *ad
.base_term
, new_reg
);
3508 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3510 rtx addr
= *ad
.inner
;
3512 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3513 /* addr => new_base. */
3514 lra_emit_move (new_reg
, addr
);
3515 *ad
.inner
= new_reg
;
3517 *before
= get_insns ();
3522 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3523 Use process_address_1 as a helper function. Return true for any
3526 If CHECK_ONLY_P is true, just check address correctness. Return
3527 false if the address correct. */
3529 process_address (int nop
, bool check_only_p
,
3530 rtx_insn
**before
, rtx_insn
**after
)
3534 while (process_address_1 (nop
, check_only_p
, before
, after
))
3543 /* Emit insns to reload VALUE into a new register. VALUE is an
3544 auto-increment or auto-decrement RTX whose operand is a register or
3545 memory location; so reloading involves incrementing that location.
3546 IN is either identical to VALUE, or some cheaper place to reload
3547 value being incremented/decremented from.
3549 INC_AMOUNT is the number to increment or decrement by (always
3550 positive and ignored for POST_MODIFY/PRE_MODIFY).
3552 Return pseudo containing the result. */
3554 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, poly_int64 inc_amount
)
3556 /* REG or MEM to be copied and incremented. */
3557 rtx incloc
= XEXP (value
, 0);
3558 /* Nonzero if increment after copying. */
3559 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3560 || GET_CODE (value
) == POST_MODIFY
);
3565 rtx real_in
= in
== value
? incloc
: in
;
3569 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3571 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3572 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3573 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3574 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3575 inc
= XEXP (XEXP (value
, 1), 1);
3579 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3580 inc_amount
= -inc_amount
;
3582 inc
= gen_int_mode (inc_amount
, GET_MODE (value
));
3585 if (! post
&& REG_P (incloc
))
3588 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3591 if (real_in
!= result
)
3593 /* First copy the location to the result register. */
3594 lra_assert (REG_P (result
));
3595 emit_insn (gen_move_insn (result
, real_in
));
3598 /* We suppose that there are insns to add/sub with the constant
3599 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3600 old reload worked with this assumption. If the assumption
3601 becomes wrong, we should use approach in function
3602 base_plus_disp_to_reg. */
3605 /* See if we can directly increment INCLOC. */
3606 last
= get_last_insn ();
3607 add_insn
= emit_insn (plus_p
3608 ? gen_add2_insn (incloc
, inc
)
3609 : gen_sub2_insn (incloc
, inc
));
3611 code
= recog_memoized (add_insn
);
3614 if (! post
&& result
!= incloc
)
3615 emit_insn (gen_move_insn (result
, incloc
));
3618 delete_insns_since (last
);
3621 /* If couldn't do the increment directly, must increment in RESULT.
3622 The way we do this depends on whether this is pre- or
3623 post-increment. For pre-increment, copy INCLOC to the reload
3624 register, increment it there, then save back. */
3627 if (real_in
!= result
)
3628 emit_insn (gen_move_insn (result
, real_in
));
3630 emit_insn (gen_add2_insn (result
, inc
));
3632 emit_insn (gen_sub2_insn (result
, inc
));
3633 if (result
!= incloc
)
3634 emit_insn (gen_move_insn (incloc
, result
));
3640 Because this might be a jump insn or a compare, and because
3641 RESULT may not be available after the insn in an input
3642 reload, we must do the incrementing before the insn being
3645 We have already copied IN to RESULT. Increment the copy in
3646 RESULT, save that back, then decrement RESULT so it has
3647 the original value. */
3649 emit_insn (gen_add2_insn (result
, inc
));
3651 emit_insn (gen_sub2_insn (result
, inc
));
3652 emit_insn (gen_move_insn (incloc
, result
));
3653 /* Restore non-modified value for the result. We prefer this
3654 way because it does not require an additional hard
3659 if (poly_int_rtx_p (inc
, &offset
))
3660 emit_insn (gen_add2_insn (result
,
3661 gen_int_mode (-offset
,
3662 GET_MODE (result
))));
3664 emit_insn (gen_sub2_insn (result
, inc
));
3667 emit_insn (gen_add2_insn (result
, inc
));
3672 /* Return true if the current move insn does not need processing as we
3673 already know that it satisfies its constraints. */
3675 simple_move_p (void)
3678 enum reg_class dclass
, sclass
;
3680 lra_assert (curr_insn_set
!= NULL_RTX
);
3681 dest
= SET_DEST (curr_insn_set
);
3682 src
= SET_SRC (curr_insn_set
);
3684 /* If the instruction has multiple sets we need to process it even if it
3685 is single_set. This can happen if one or more of the SETs are dead.
3687 if (multiple_sets (curr_insn
))
3690 return ((dclass
= get_op_class (dest
)) != NO_REGS
3691 && (sclass
= get_op_class (src
)) != NO_REGS
3692 /* The backend guarantees that register moves of cost 2
3693 never need reloads. */
3694 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3697 /* Swap operands NOP and NOP + 1. */
3699 swap_operands (int nop
)
3701 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3702 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3703 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3704 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3705 /* Swap the duplicates too. */
3706 lra_update_dup (curr_id
, nop
);
3707 lra_update_dup (curr_id
, nop
+ 1);
3710 /* Main entry point of the constraint code: search the body of the
3711 current insn to choose the best alternative. It is mimicking insn
3712 alternative cost calculation model of former reload pass. That is
3713 because machine descriptions were written to use this model. This
3714 model can be changed in future. Make commutative operand exchange
3717 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3718 constraints. Return true if any change happened during function
3721 If CHECK_ONLY_P is true then don't do any transformation. Just
3722 check that the insn satisfies all constraints. If the insn does
3723 not satisfy any constraint, return true. */
3725 curr_insn_transform (bool check_only_p
)
3732 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3733 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3734 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3735 rtx_insn
*before
, *after
;
3737 /* Flag that the insn has been changed through a transformation. */
3741 int max_regno_before
;
3742 int reused_alternative_num
;
3744 curr_insn_set
= single_set (curr_insn
);
3745 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3747 /* We assume that the corresponding insn alternative has no
3748 earlier clobbers. If it is not the case, don't define move
3749 cost equal to 2 for the corresponding register classes. */
3750 lra_set_used_insn_alternative (curr_insn
, LRA_NON_CLOBBERED_ALT
);
3754 no_input_reloads_p
= no_output_reloads_p
= false;
3755 goal_alt_number
= -1;
3756 change_p
= sec_mem_p
= false;
3757 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3758 reloads; neither are insns that SET cc0. Insns that use CC0 are
3759 not allowed to have any input reloads. */
3760 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3761 no_output_reloads_p
= true;
3763 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3764 no_input_reloads_p
= true;
3765 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3766 no_output_reloads_p
= true;
3768 n_operands
= curr_static_id
->n_operands
;
3769 n_alternatives
= curr_static_id
->n_alternatives
;
3771 /* Just return "no reloads" if insn has no operands with
3773 if (n_operands
== 0 || n_alternatives
== 0)
3776 max_regno_before
= max_reg_num ();
3778 for (i
= 0; i
< n_operands
; i
++)
3780 goal_alt_matched
[i
][0] = -1;
3781 goal_alt_matches
[i
] = -1;
3784 commutative
= curr_static_id
->commutative
;
3786 /* Now see what we need for pseudos that didn't get hard regs or got
3787 the wrong kind of hard reg. For this, we must consider all the
3788 operands together against the register constraints. */
3790 best_losers
= best_overall
= INT_MAX
;
3791 best_reload_sum
= 0;
3793 curr_swapped
= false;
3794 goal_alt_swapped
= false;
3797 /* Make equivalence substitution and memory subreg elimination
3798 before address processing because an address legitimacy can
3799 depend on memory mode. */
3800 for (i
= 0; i
< n_operands
; i
++)
3803 bool op_change_p
= false;
3805 if (curr_static_id
->operand
[i
].is_operator
)
3808 old
= op
= *curr_id
->operand_loc
[i
];
3809 if (GET_CODE (old
) == SUBREG
)
3810 old
= SUBREG_REG (old
);
3811 subst
= get_equiv_with_elimination (old
, curr_insn
);
3812 original_subreg_reg_mode
[i
] = VOIDmode
;
3813 equiv_substition_p
[i
] = false;
3816 equiv_substition_p
[i
] = true;
3817 subst
= copy_rtx (subst
);
3818 lra_assert (REG_P (old
));
3819 if (GET_CODE (op
) != SUBREG
)
3820 *curr_id
->operand_loc
[i
] = subst
;
3823 SUBREG_REG (op
) = subst
;
3824 if (GET_MODE (subst
) == VOIDmode
)
3825 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3827 if (lra_dump_file
!= NULL
)
3829 fprintf (lra_dump_file
,
3830 "Changing pseudo %d in operand %i of insn %u on equiv ",
3831 REGNO (old
), i
, INSN_UID (curr_insn
));
3832 dump_value_slim (lra_dump_file
, subst
, 1);
3833 fprintf (lra_dump_file
, "\n");
3835 op_change_p
= change_p
= true;
3837 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3840 lra_update_dup (curr_id
, i
);
3844 /* Reload address registers and displacements. We do it before
3845 finding an alternative because of memory constraints. */
3846 before
= after
= NULL
;
3847 for (i
= 0; i
< n_operands
; i
++)
3848 if (! curr_static_id
->operand
[i
].is_operator
3849 && process_address (i
, check_only_p
, &before
, &after
))
3854 lra_update_dup (curr_id
, i
);
3858 /* If we've changed the instruction then any alternative that
3859 we chose previously may no longer be valid. */
3860 lra_set_used_insn_alternative (curr_insn
, LRA_UNKNOWN_ALT
);
3862 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3863 && check_and_process_move (&change_p
, &sec_mem_p
))
3868 reused_alternative_num
= check_only_p
? LRA_UNKNOWN_ALT
: curr_id
->used_insn_alternative
;
3869 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3870 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3871 reused_alternative_num
, INSN_UID (curr_insn
));
3873 if (process_alt_operands (reused_alternative_num
))
3877 return ! alt_p
|| best_losers
!= 0;
3879 /* If insn is commutative (it's safe to exchange a certain pair of
3880 operands) then we need to try each alternative twice, the second
3881 time matching those two operands as if we had exchanged them. To
3882 do this, really exchange them in operands.
3884 If we have just tried the alternatives the second time, return
3885 operands to normal and drop through. */
3887 if (reused_alternative_num
< 0 && commutative
>= 0)
3889 curr_swapped
= !curr_swapped
;
3892 swap_operands (commutative
);
3896 swap_operands (commutative
);
3899 if (! alt_p
&& ! sec_mem_p
)
3901 /* No alternative works with reloads?? */
3902 if (INSN_CODE (curr_insn
) >= 0)
3903 fatal_insn ("unable to generate reloads for:", curr_insn
);
3904 error_for_asm (curr_insn
,
3905 "inconsistent operand constraints in an %<asm%>");
3906 /* Avoid further trouble with this insn. Don't generate use
3907 pattern here as we could use the insn SP offset. */
3908 lra_set_insn_deleted (curr_insn
);
3912 /* If the best alternative is with operands 1 and 2 swapped, swap
3913 them. Update the operand numbers of any reloads already
3916 if (goal_alt_swapped
)
3918 if (lra_dump_file
!= NULL
)
3919 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3920 INSN_UID (curr_insn
));
3922 /* Swap the duplicates too. */
3923 swap_operands (commutative
);
3927 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3928 too conservatively. So we use the secondary memory only if there
3929 is no any alternative without reloads. */
3930 use_sec_mem_p
= false;
3932 use_sec_mem_p
= true;
3935 for (i
= 0; i
< n_operands
; i
++)
3936 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3938 use_sec_mem_p
= i
< n_operands
;
3943 int in
= -1, out
= -1;
3944 rtx new_reg
, src
, dest
, rld
;
3945 machine_mode sec_mode
, rld_mode
;
3947 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3948 dest
= SET_DEST (curr_insn_set
);
3949 src
= SET_SRC (curr_insn_set
);
3950 for (i
= 0; i
< n_operands
; i
++)
3951 if (*curr_id
->operand_loc
[i
] == dest
)
3953 else if (*curr_id
->operand_loc
[i
] == src
)
3955 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3956 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3957 out
= curr_static_id
->dup_num
[i
];
3958 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3959 in
= curr_static_id
->dup_num
[i
];
3960 lra_assert (out
>= 0 && in
>= 0
3961 && curr_static_id
->operand
[out
].type
== OP_OUT
3962 && curr_static_id
->operand
[in
].type
== OP_IN
);
3963 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
3964 rld_mode
= GET_MODE (rld
);
3965 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
3966 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3967 NO_REGS
, "secondary");
3968 /* If the mode is changed, it should be wider. */
3969 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
3970 if (sec_mode
!= rld_mode
)
3972 /* If the target says specifically to use another mode for
3973 secondary memory moves we can not reuse the original
3975 after
= emit_spill_move (false, new_reg
, dest
);
3976 lra_process_new_insns (curr_insn
, NULL
, after
,
3977 "Inserting the sec. move");
3978 /* We may have non null BEFORE here (e.g. after address
3980 push_to_sequence (before
);
3981 before
= emit_spill_move (true, new_reg
, src
);
3983 before
= get_insns ();
3985 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3986 lra_set_insn_deleted (curr_insn
);
3988 else if (dest
== rld
)
3990 *curr_id
->operand_loc
[out
] = new_reg
;
3991 lra_update_dup (curr_id
, out
);
3992 after
= emit_spill_move (false, new_reg
, dest
);
3993 lra_process_new_insns (curr_insn
, NULL
, after
,
3994 "Inserting the sec. move");
3998 *curr_id
->operand_loc
[in
] = new_reg
;
3999 lra_update_dup (curr_id
, in
);
4000 /* See comments above. */
4001 push_to_sequence (before
);
4002 before
= emit_spill_move (true, new_reg
, src
);
4004 before
= get_insns ();
4006 lra_process_new_insns (curr_insn
, before
, NULL
,
4007 "Inserting the sec. move");
4009 lra_update_insn_regno_info (curr_insn
);
4013 lra_assert (goal_alt_number
>= 0);
4014 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
4016 if (lra_dump_file
!= NULL
)
4020 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4021 goal_alt_number
, INSN_UID (curr_insn
));
4022 for (i
= 0; i
< n_operands
; i
++)
4024 p
= (curr_static_id
->operand_alternative
4025 [goal_alt_number
* n_operands
+ i
].constraint
);
4028 fprintf (lra_dump_file
, " (%d) ", i
);
4029 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
4030 fputc (*p
, lra_dump_file
);
4032 if (INSN_CODE (curr_insn
) >= 0
4033 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4034 fprintf (lra_dump_file
, " {%s}", p
);
4035 if (maybe_ne (curr_id
->sp_offset
, 0))
4037 fprintf (lra_dump_file
, " (sp_off=");
4038 print_dec (curr_id
->sp_offset
, lra_dump_file
);
4039 fprintf (lra_dump_file
, ")");
4041 fprintf (lra_dump_file
, "\n");
4044 /* Right now, for any pair of operands I and J that are required to
4045 match, with J < I, goal_alt_matches[I] is J. Add I to
4046 goal_alt_matched[J]. */
4048 for (i
= 0; i
< n_operands
; i
++)
4049 if ((j
= goal_alt_matches
[i
]) >= 0)
4051 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4053 /* We allow matching one output operand and several input
4056 || (curr_static_id
->operand
[j
].type
== OP_OUT
4057 && curr_static_id
->operand
[i
].type
== OP_IN
4058 && (curr_static_id
->operand
4059 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4060 goal_alt_matched
[j
][k
] = i
;
4061 goal_alt_matched
[j
][k
+ 1] = -1;
4064 for (i
= 0; i
< n_operands
; i
++)
4065 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4067 /* Any constants that aren't allowed and can't be reloaded into
4068 registers are here changed into memory references. */
4069 for (i
= 0; i
< n_operands
; i
++)
4070 if (goal_alt_win
[i
])
4073 enum reg_class new_class
;
4074 rtx reg
= *curr_id
->operand_loc
[i
];
4076 if (GET_CODE (reg
) == SUBREG
)
4077 reg
= SUBREG_REG (reg
);
4079 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4081 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4083 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4086 lra_change_class (regno
, new_class
, " Change to", true);
4092 const char *constraint
;
4094 rtx op
= *curr_id
->operand_loc
[i
];
4095 rtx subreg
= NULL_RTX
;
4096 machine_mode mode
= curr_operand_mode
[i
];
4098 if (GET_CODE (op
) == SUBREG
)
4101 op
= SUBREG_REG (op
);
4102 mode
= GET_MODE (op
);
4105 if (CONST_POOL_OK_P (mode
, op
)
4106 && ((targetm
.preferred_reload_class
4107 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4108 || no_input_reloads_p
))
4110 rtx tem
= force_const_mem (mode
, op
);
4113 if (subreg
!= NULL_RTX
)
4114 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4116 *curr_id
->operand_loc
[i
] = tem
;
4117 lra_update_dup (curr_id
, i
);
4118 process_address (i
, false, &before
, &after
);
4120 /* If the alternative accepts constant pool refs directly
4121 there will be no reload needed at all. */
4122 if (subreg
!= NULL_RTX
)
4124 /* Skip alternatives before the one requested. */
4125 constraint
= (curr_static_id
->operand_alternative
4126 [goal_alt_number
* n_operands
+ i
].constraint
);
4128 (c
= *constraint
) && c
!= ',' && c
!= '#';
4129 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4131 enum constraint_num cn
= lookup_constraint (constraint
);
4132 if ((insn_extra_memory_constraint (cn
)
4133 || insn_extra_special_memory_constraint (cn
))
4134 && satisfies_memory_constraint_p (tem
, cn
))
4137 if (c
== '\0' || c
== ',' || c
== '#')
4140 goal_alt_win
[i
] = true;
4146 for (i
= 0; i
< n_operands
; i
++)
4149 bool optional_p
= false;
4151 rtx op
= *curr_id
->operand_loc
[i
];
4153 if (goal_alt_win
[i
])
4155 if (goal_alt
[i
] == NO_REGS
4157 /* When we assign NO_REGS it means that we will not
4158 assign a hard register to the scratch pseudo by
4159 assigment pass and the scratch pseudo will be
4160 spilled. Spilled scratch pseudos are transformed
4161 back to scratches at the LRA end. */
4162 && lra_former_scratch_operand_p (curr_insn
, i
)
4163 && lra_former_scratch_p (REGNO (op
)))
4165 int regno
= REGNO (op
);
4166 lra_change_class (regno
, NO_REGS
, " Change to", true);
4167 if (lra_get_regno_hard_regno (regno
) >= 0)
4168 /* We don't have to mark all insn affected by the
4169 spilled pseudo as there is only one such insn, the
4171 reg_renumber
[regno
] = -1;
4172 lra_assert (bitmap_single_bit_set_p
4173 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4175 /* We can do an optional reload. If the pseudo got a hard
4176 reg, we might improve the code through inheritance. If
4177 it does not get a hard register we coalesce memory/memory
4178 moves later. Ignore move insns to avoid cycling. */
4180 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4181 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4182 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4183 && regno
< new_regno_start
4184 && ! lra_former_scratch_p (regno
)
4185 && reg_renumber
[regno
] < 0
4186 /* Check that the optional reload pseudo will be able to
4187 hold given mode value. */
4188 && ! (prohibited_class_reg_set_mode_p
4189 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4190 PSEUDO_REGNO_MODE (regno
)))
4191 && (curr_insn_set
== NULL_RTX
4192 || !((REG_P (SET_SRC (curr_insn_set
))
4193 || MEM_P (SET_SRC (curr_insn_set
))
4194 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4195 && (REG_P (SET_DEST (curr_insn_set
))
4196 || MEM_P (SET_DEST (curr_insn_set
))
4197 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4203 /* Operands that match previous ones have already been handled. */
4204 if (goal_alt_matches
[i
] >= 0)
4207 /* We should not have an operand with a non-offsettable address
4208 appearing where an offsettable address will do. It also may
4209 be a case when the address should be special in other words
4210 not a general one (e.g. it needs no index reg). */
4211 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4213 enum reg_class rclass
;
4214 rtx
*loc
= &XEXP (op
, 0);
4215 enum rtx_code code
= GET_CODE (*loc
);
4217 push_to_sequence (before
);
4218 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4220 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4221 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4222 /* This value does not matter for MODIFY. */
4223 GET_MODE_SIZE (GET_MODE (op
)));
4224 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4225 "offsetable address", &new_reg
))
4228 enum rtx_code code
= GET_CODE (addr
);
4230 if (code
== AND
&& CONST_INT_P (XEXP (addr
, 1)))
4231 /* (and ... (const_int -X)) is used to align to X bytes. */
4232 addr
= XEXP (*loc
, 0);
4233 lra_emit_move (new_reg
, addr
);
4235 emit_move_insn (new_reg
, gen_rtx_AND (GET_MODE (new_reg
), new_reg
, XEXP (*loc
, 1)));
4237 before
= get_insns ();
4240 lra_update_dup (curr_id
, i
);
4242 else if (goal_alt_matched
[i
][0] == -1)
4247 enum op_type type
= curr_static_id
->operand
[i
].type
;
4249 loc
= curr_id
->operand_loc
[i
];
4250 mode
= curr_operand_mode
[i
];
4251 if (GET_CODE (*loc
) == SUBREG
)
4253 reg
= SUBREG_REG (*loc
);
4254 poly_int64 byte
= SUBREG_BYTE (*loc
);
4256 /* Strict_low_part requires reloading the register and not
4257 just the subreg. Likewise for a strict subreg no wider
4258 than a word for WORD_REGISTER_OPERATIONS targets. */
4259 && (curr_static_id
->operand
[i
].strict_low
4260 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4262 = get_try_hard_regno (REGNO (reg
))) >= 0
4263 && (simplify_subreg_regno
4265 GET_MODE (reg
), byte
, mode
) < 0)
4266 && (goal_alt
[i
] == NO_REGS
4267 || (simplify_subreg_regno
4268 (ira_class_hard_regs
[goal_alt
[i
]][0],
4269 GET_MODE (reg
), byte
, mode
) >= 0)))
4270 || (partial_subreg_p (mode
, GET_MODE (reg
))
4271 && known_le (GET_MODE_SIZE (GET_MODE (reg
)),
4273 && WORD_REGISTER_OPERATIONS
)))
4275 /* An OP_INOUT is required when reloading a subreg of a
4276 mode wider than a word to ensure that data beyond the
4277 word being reloaded is preserved. Also automatically
4278 ensure that strict_low_part reloads are made into
4279 OP_INOUT which should already be true from the backend
4282 && (curr_static_id
->operand
[i
].strict_low
4283 || read_modify_subreg_p (*loc
)))
4285 loc
= &SUBREG_REG (*loc
);
4286 mode
= GET_MODE (*loc
);
4290 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4291 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4294 push_to_sequence (before
);
4295 lra_emit_move (new_reg
, old
);
4296 before
= get_insns ();
4301 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4304 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4306 after
= get_insns ();
4310 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4311 if (goal_alt_dont_inherit_ops
[j
] == i
)
4313 lra_set_regno_unique_value (REGNO (new_reg
));
4316 lra_update_dup (curr_id
, i
);
4318 else if (curr_static_id
->operand
[i
].type
== OP_IN
4319 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4321 || (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4323 && (operands_match_p
4324 (*curr_id
->operand_loc
[i
],
4325 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4328 /* generate reloads for input and matched outputs. */
4329 match_inputs
[0] = i
;
4330 match_inputs
[1] = -1;
4331 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4332 goal_alt
[i
], &before
, &after
,
4333 curr_static_id
->operand_alternative
4334 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4337 else if ((curr_static_id
->operand
[i
].type
== OP_OUT
4338 || (curr_static_id
->operand
[i
].type
== OP_INOUT
4339 && (operands_match_p
4340 (*curr_id
->operand_loc
[i
],
4341 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4343 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4345 /* Generate reloads for output and matched inputs. */
4346 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4347 &after
, curr_static_id
->operand_alternative
4348 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4349 else if (curr_static_id
->operand
[i
].type
== OP_IN
4350 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4353 /* Generate reloads for matched inputs. */
4354 match_inputs
[0] = i
;
4355 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4356 match_inputs
[j
+ 1] = k
;
4357 match_inputs
[j
+ 1] = -1;
4358 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4362 /* We must generate code in any case when function
4363 process_alt_operands decides that it is possible. */
4366 /* Memorise processed outputs so that output remaining to be processed
4367 can avoid using the same register value (see match_reload). */
4368 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4370 outputs
[n_outputs
++] = i
;
4371 outputs
[n_outputs
] = -1;
4378 lra_assert (REG_P (reg
));
4379 regno
= REGNO (reg
);
4380 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4381 if (GET_CODE (op
) == SUBREG
)
4382 op
= SUBREG_REG (op
);
4383 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4384 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4385 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4386 if (lra_dump_file
!= NULL
)
4387 fprintf (lra_dump_file
,
4388 " Making reload reg %d for reg %d optional\n",
4392 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4393 || max_regno_before
!= max_reg_num ())
4397 lra_update_operator_dups (curr_id
);
4398 /* Something changes -- process the insn. */
4399 lra_update_insn_regno_info (curr_insn
);
4401 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4405 /* Return true if INSN satisfies all constraints. In other words, no
4406 reload insns are needed. */
4408 lra_constrain_insn (rtx_insn
*insn
)
4410 int saved_new_regno_start
= new_regno_start
;
4411 int saved_new_insn_uid_start
= new_insn_uid_start
;
4415 curr_id
= lra_get_insn_recog_data (curr_insn
);
4416 curr_static_id
= curr_id
->insn_static_data
;
4417 new_insn_uid_start
= get_max_uid ();
4418 new_regno_start
= max_reg_num ();
4419 change_p
= curr_insn_transform (true);
4420 new_regno_start
= saved_new_regno_start
;
4421 new_insn_uid_start
= saved_new_insn_uid_start
;
4425 /* Return true if X is in LIST. */
4427 in_list_p (rtx x
, rtx list
)
4429 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4430 if (XEXP (list
, 0) == x
)
4435 /* Return true if X contains an allocatable hard register (if
4436 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4438 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4444 code
= GET_CODE (x
);
4447 int regno
= REGNO (x
);
4448 HARD_REG_SET alloc_regs
;
4452 if (regno
>= FIRST_PSEUDO_REGISTER
)
4453 regno
= lra_get_regno_hard_regno (regno
);
4456 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4457 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4461 if (regno
< FIRST_PSEUDO_REGISTER
)
4465 return lra_get_regno_hard_regno (regno
) < 0;
4468 fmt
= GET_RTX_FORMAT (code
);
4469 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4473 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4476 else if (fmt
[i
] == 'E')
4478 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4479 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4486 /* Process all regs in location *LOC and change them on equivalent
4487 substitution. Return true if any change was done. */
4489 loc_equivalence_change_p (rtx
*loc
)
4491 rtx subst
, reg
, x
= *loc
;
4492 bool result
= false;
4493 enum rtx_code code
= GET_CODE (x
);
4499 reg
= SUBREG_REG (x
);
4500 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4501 && GET_MODE (subst
) == VOIDmode
)
4503 /* We cannot reload debug location. Simplify subreg here
4504 while we know the inner mode. */
4505 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4506 GET_MODE (reg
), SUBREG_BYTE (x
));
4510 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4516 /* Scan all the operand sub-expressions. */
4517 fmt
= GET_RTX_FORMAT (code
);
4518 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4521 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4522 else if (fmt
[i
] == 'E')
4523 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4525 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4530 /* Similar to loc_equivalence_change_p, but for use as
4531 simplify_replace_fn_rtx callback. DATA is insn for which the
4532 elimination is done. If it null we don't do the elimination. */
4534 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4539 rtx subst
= (data
== NULL
4540 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4547 /* Maximum number of generated reload insns per an insn. It is for
4548 preventing this pass cycling in a bug case. */
4549 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4551 /* The current iteration number of this LRA pass. */
4552 int lra_constraint_iter
;
4554 /* True if we substituted equiv which needs checking register
4555 allocation correctness because the equivalent value contains
4556 allocatable hard registers or when we restore multi-register
4558 bool lra_risky_transformations_p
;
4560 /* Return true if REGNO is referenced in more than one block. */
4562 multi_block_pseudo_p (int regno
)
4564 basic_block bb
= NULL
;
4568 if (regno
< FIRST_PSEUDO_REGISTER
)
4571 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4573 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4574 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4579 /* Return true if LIST contains a deleted insn. */
4581 contains_deleted_insn_p (rtx_insn_list
*list
)
4583 for (; list
!= NULL_RTX
; list
= list
->next ())
4584 if (NOTE_P (list
->insn ())
4585 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4590 /* Return true if X contains a pseudo dying in INSN. */
4592 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4599 return (insn
!= NULL_RTX
4600 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4601 code
= GET_CODE (x
);
4602 fmt
= GET_RTX_FORMAT (code
);
4603 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4607 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4610 else if (fmt
[i
] == 'E')
4612 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4613 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4620 /* Return true if INSN contains a dying pseudo in INSN right hand
4623 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4625 rtx set
= single_set (insn
);
4627 gcc_assert (set
!= NULL
);
4628 return dead_pseudo_p (SET_SRC (set
), insn
);
4631 /* Return true if any init insn of REGNO contains a dying pseudo in
4632 insn right hand side. */
4634 init_insn_rhs_dead_pseudo_p (int regno
)
4636 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4640 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4641 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4646 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4647 reverse only if we have one init insn with given REGNO as a
4650 reverse_equiv_p (int regno
)
4652 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4657 if (! INSN_P (insns
->insn ())
4658 || insns
->next () != NULL
)
4660 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4662 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4665 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4666 call this function only for non-reverse equivalence. */
4668 contains_reloaded_insn_p (int regno
)
4671 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4673 for (; list
!= NULL
; list
= list
->next ())
4674 if ((set
= single_set (list
->insn ())) == NULL_RTX
4675 || ! REG_P (SET_DEST (set
))
4676 || (int) REGNO (SET_DEST (set
)) != regno
)
4681 /* Entry function of LRA constraint pass. Return true if the
4682 constraint pass did change the code. */
4684 lra_constraints (bool first_p
)
4687 int i
, hard_regno
, new_insns_num
;
4688 unsigned int min_len
, new_min_len
, uid
;
4689 rtx set
, x
, reg
, dest_reg
;
4690 basic_block last_bb
;
4693 lra_constraint_iter
++;
4694 if (lra_dump_file
!= NULL
)
4695 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4696 lra_constraint_iter
);
4698 if (pic_offset_table_rtx
4699 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4700 lra_risky_transformations_p
= true;
4702 /* On the first iteration we should check IRA assignment
4703 correctness. In rare cases, the assignments can be wrong as
4704 early clobbers operands are ignored in IRA. */
4705 lra_risky_transformations_p
= first_p
;
4706 new_insn_uid_start
= get_max_uid ();
4707 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4708 /* Mark used hard regs for target stack size calulations. */
4709 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4710 if (lra_reg_info
[i
].nrefs
!= 0
4711 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4715 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
4716 for (j
= 0; j
< nregs
; j
++)
4717 df_set_regs_ever_live (hard_regno
+ j
, true);
4719 /* Do elimination before the equivalence processing as we can spill
4720 some pseudos during elimination. */
4721 lra_eliminate (false, first_p
);
4722 auto_bitmap
equiv_insn_bitmap (®_obstack
);
4723 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4724 if (lra_reg_info
[i
].nrefs
!= 0)
4726 ira_reg_equiv
[i
].profitable_p
= true;
4727 reg
= regno_reg_rtx
[i
];
4728 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4730 bool pseudo_p
= contains_reg_p (x
, false, false);
4732 /* After RTL transformation, we can not guarantee that
4733 pseudo in the substitution was not reloaded which might
4734 make equivalence invalid. For example, in reverse
4741 the memory address register was reloaded before the 2nd
4743 if ((! first_p
&& pseudo_p
)
4744 /* We don't use DF for compilation speed sake. So it
4745 is problematic to update live info when we use an
4746 equivalence containing pseudos in more than one
4748 || (pseudo_p
&& multi_block_pseudo_p (i
))
4749 /* If an init insn was deleted for some reason, cancel
4750 the equiv. We could update the equiv insns after
4751 transformations including an equiv insn deletion
4752 but it is not worthy as such cases are extremely
4754 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4755 /* If it is not a reverse equivalence, we check that a
4756 pseudo in rhs of the init insn is not dying in the
4757 insn. Otherwise, the live info at the beginning of
4758 the corresponding BB might be wrong after we
4759 removed the insn. When the equiv can be a
4760 constant, the right hand side of the init insn can
4762 || (! reverse_equiv_p (i
)
4763 && (init_insn_rhs_dead_pseudo_p (i
)
4764 /* If we reloaded the pseudo in an equivalence
4765 init insn, we can not remove the equiv init
4766 insns and the init insns might write into
4767 const memory in this case. */
4768 || contains_reloaded_insn_p (i
)))
4769 /* Prevent access beyond equivalent memory for
4770 paradoxical subregs. */
4772 && maybe_gt (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
),
4773 GET_MODE_SIZE (GET_MODE (x
))))
4774 || (pic_offset_table_rtx
4775 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4776 && (targetm
.preferred_reload_class
4777 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4778 || contains_symbol_ref_p (x
))))
4779 ira_reg_equiv
[i
].defined_p
= false;
4780 if (contains_reg_p (x
, false, true))
4781 ira_reg_equiv
[i
].profitable_p
= false;
4782 if (get_equiv (reg
) != reg
)
4783 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4786 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4788 /* We should add all insns containing pseudos which should be
4789 substituted by their equivalences. */
4790 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
4791 lra_push_insn_by_uid (uid
);
4792 min_len
= lra_insn_stack_length ();
4796 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4798 curr_insn
= lra_pop_insn ();
4800 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4801 if (curr_bb
!= last_bb
)
4804 bb_reload_num
= lra_curr_reload_num
;
4806 if (min_len
> new_min_len
)
4808 min_len
= new_min_len
;
4811 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4813 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4814 MAX_RELOAD_INSNS_NUMBER
);
4816 if (DEBUG_INSN_P (curr_insn
))
4818 /* We need to check equivalence in debug insn and change
4819 pseudo to the equivalent value if necessary. */
4820 curr_id
= lra_get_insn_recog_data (curr_insn
);
4821 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4823 rtx old
= *curr_id
->operand_loc
[0];
4824 *curr_id
->operand_loc
[0]
4825 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4826 loc_equivalence_callback
, curr_insn
);
4827 if (old
!= *curr_id
->operand_loc
[0])
4829 lra_update_insn_regno_info (curr_insn
);
4834 else if (INSN_P (curr_insn
))
4836 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4838 dest_reg
= SET_DEST (set
);
4839 /* The equivalence pseudo could be set up as SUBREG in a
4840 case when it is a call restore insn in a mode
4841 different from the pseudo mode. */
4842 if (GET_CODE (dest_reg
) == SUBREG
)
4843 dest_reg
= SUBREG_REG (dest_reg
);
4844 if ((REG_P (dest_reg
)
4845 && (x
= get_equiv (dest_reg
)) != dest_reg
4846 /* Remove insns which set up a pseudo whose value
4847 can not be changed. Such insns might be not in
4848 init_insns because we don't update equiv data
4849 during insn transformations.
4851 As an example, let suppose that a pseudo got
4852 hard register and on the 1st pass was not
4853 changed to equivalent constant. We generate an
4854 additional insn setting up the pseudo because of
4855 secondary memory movement. Then the pseudo is
4856 spilled and we use the equiv constant. In this
4857 case we should remove the additional insn and
4858 this insn is not init_insns list. */
4859 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4860 /* Check that this is actually an insn setting
4861 up the equivalence. */
4862 || in_list_p (curr_insn
,
4864 [REGNO (dest_reg
)].init_insns
)))
4865 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4866 && in_list_p (curr_insn
,
4868 [REGNO (SET_SRC (set
))].init_insns
)))
4870 /* This is equiv init insn of pseudo which did not get a
4871 hard register -- remove the insn. */
4872 if (lra_dump_file
!= NULL
)
4874 fprintf (lra_dump_file
,
4875 " Removing equiv init insn %i (freq=%d)\n",
4876 INSN_UID (curr_insn
),
4877 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4878 dump_insn_slim (lra_dump_file
, curr_insn
);
4880 if (contains_reg_p (x
, true, false))
4881 lra_risky_transformations_p
= true;
4882 lra_set_insn_deleted (curr_insn
);
4886 curr_id
= lra_get_insn_recog_data (curr_insn
);
4887 curr_static_id
= curr_id
->insn_static_data
;
4888 init_curr_insn_input_reloads ();
4889 init_curr_operand_mode ();
4890 if (curr_insn_transform (false))
4892 /* Check non-transformed insns too for equiv change as USE
4893 or CLOBBER don't need reloads but can contain pseudos
4894 being changed on their equivalences. */
4895 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
4896 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4898 lra_update_insn_regno_info (curr_insn
);
4904 /* If we used a new hard regno, changed_p should be true because the
4905 hard reg is assigned to a new pseudo. */
4906 if (flag_checking
&& !changed_p
)
4908 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4909 if (lra_reg_info
[i
].nrefs
!= 0
4910 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4912 int j
, nregs
= hard_regno_nregs (hard_regno
,
4913 PSEUDO_REGNO_MODE (i
));
4915 for (j
= 0; j
< nregs
; j
++)
4916 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4922 static void initiate_invariants (void);
4923 static void finish_invariants (void);
4925 /* Initiate the LRA constraint pass. It is done once per
4928 lra_constraints_init (void)
4930 initiate_invariants ();
4933 /* Finalize the LRA constraint pass. It is done once per
4936 lra_constraints_finish (void)
4938 finish_invariants ();
4943 /* Structure describes invariants for ineheritance. */
4944 struct lra_invariant
4946 /* The order number of the invariant. */
4948 /* The invariant RTX. */
4950 /* The origin insn of the invariant. */
4954 typedef lra_invariant invariant_t
;
4955 typedef invariant_t
*invariant_ptr_t
;
4956 typedef const invariant_t
*const_invariant_ptr_t
;
4958 /* Pointer to the inheritance invariants. */
4959 static vec
<invariant_ptr_t
> invariants
;
4961 /* Allocation pool for the invariants. */
4962 static object_allocator
<lra_invariant
> *invariants_pool
;
4964 /* Hash table for the invariants. */
4965 static htab_t invariant_table
;
4967 /* Hash function for INVARIANT. */
4969 invariant_hash (const void *invariant
)
4971 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
4972 return lra_rtx_hash (inv
);
4975 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4977 invariant_eq_p (const void *invariant1
, const void *invariant2
)
4979 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
4980 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
4982 return rtx_equal_p (inv1
, inv2
);
4985 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
4986 invariant which is in the table. */
4987 static invariant_ptr_t
4988 insert_invariant (rtx invariant_rtx
)
4991 invariant_t invariant
;
4992 invariant_ptr_t invariant_ptr
;
4994 invariant
.invariant_rtx
= invariant_rtx
;
4995 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
4996 if (*entry_ptr
== NULL
)
4998 invariant_ptr
= invariants_pool
->allocate ();
4999 invariant_ptr
->invariant_rtx
= invariant_rtx
;
5000 invariant_ptr
->insn
= NULL
;
5001 invariants
.safe_push (invariant_ptr
);
5002 *entry_ptr
= (void *) invariant_ptr
;
5004 return (invariant_ptr_t
) *entry_ptr
;
5007 /* Initiate the invariant table. */
5009 initiate_invariants (void)
5011 invariants
.create (100);
5013 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
5014 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
5017 /* Finish the invariant table. */
5019 finish_invariants (void)
5021 htab_delete (invariant_table
);
5022 delete invariants_pool
;
5023 invariants
.release ();
5026 /* Make the invariant table empty. */
5028 clear_invariants (void)
5030 htab_empty (invariant_table
);
5031 invariants_pool
->release ();
5032 invariants
.truncate (0);
5037 /* This page contains code to do inheritance/split
5040 /* Number of reloads passed so far in current EBB. */
5041 static int reloads_num
;
5043 /* Number of calls passed so far in current EBB. */
5044 static int calls_num
;
5046 /* Current reload pseudo check for validity of elements in
5048 static int curr_usage_insns_check
;
5050 /* Info about last usage of registers in EBB to do inheritance/split
5051 transformation. Inheritance transformation is done from a spilled
5052 pseudo and split transformations from a hard register or a pseudo
5053 assigned to a hard register. */
5056 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5057 value INSNS is valid. The insns is chain of optional debug insns
5058 and a finishing non-debug insn using the corresponding reg. The
5059 value is also used to mark the registers which are set up in the
5060 current insn. The negated insn uid is used for this. */
5062 /* Value of global reloads_num at the last insn in INSNS. */
5064 /* Value of global reloads_nums at the last insn in INSNS. */
5066 /* It can be true only for splitting. And it means that the restore
5067 insn should be put after insn given by the following member. */
5069 /* Next insns in the current EBB which use the original reg and the
5070 original reg value is not changed between the current insn and
5071 the next insns. In order words, e.g. for inheritance, if we need
5072 to use the original reg value again in the next insns we can try
5073 to use the value in a hard register from a reload insn of the
5078 /* Map: regno -> corresponding pseudo usage insns. */
5079 static struct usage_insns
*usage_insns
;
5082 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5084 usage_insns
[regno
].check
= curr_usage_insns_check
;
5085 usage_insns
[regno
].insns
= insn
;
5086 usage_insns
[regno
].reloads_num
= reloads_num
;
5087 usage_insns
[regno
].calls_num
= calls_num
;
5088 usage_insns
[regno
].after_p
= after_p
;
5091 /* The function is used to form list REGNO usages which consists of
5092 optional debug insns finished by a non-debug insn using REGNO.
5093 RELOADS_NUM is current number of reload insns processed so far. */
5095 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5097 rtx next_usage_insns
;
5099 if (usage_insns
[regno
].check
== curr_usage_insns_check
5100 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5101 && DEBUG_INSN_P (insn
))
5103 /* Check that we did not add the debug insn yet. */
5104 if (next_usage_insns
!= insn
5105 && (GET_CODE (next_usage_insns
) != INSN_LIST
5106 || XEXP (next_usage_insns
, 0) != insn
))
5107 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5110 else if (NONDEBUG_INSN_P (insn
))
5111 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5113 usage_insns
[regno
].check
= 0;
5116 /* Return first non-debug insn in list USAGE_INSNS. */
5118 skip_usage_debug_insns (rtx usage_insns
)
5122 /* Skip debug insns. */
5123 for (insn
= usage_insns
;
5124 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5125 insn
= XEXP (insn
, 1))
5127 return safe_as_a
<rtx_insn
*> (insn
);
5130 /* Return true if we need secondary memory moves for insn in
5131 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5134 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5135 rtx usage_insns ATTRIBUTE_UNUSED
)
5141 if (inher_cl
== ALL_REGS
5142 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5144 lra_assert (INSN_P (insn
));
5145 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5147 dest
= SET_DEST (set
);
5150 lra_assert (inher_cl
!= NO_REGS
);
5151 cl
= get_reg_class (REGNO (dest
));
5152 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5153 && targetm
.secondary_memory_needed (GET_MODE (dest
), inher_cl
, cl
));
5156 /* Registers involved in inheritance/split in the current EBB
5157 (inheritance/split pseudos and original registers). */
5158 static bitmap_head check_only_regs
;
5160 /* Reload pseudos can not be involded in invariant inheritance in the
5162 static bitmap_head invalid_invariant_regs
;
5164 /* Do inheritance transformations for insn INSN, which defines (if
5165 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5166 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5167 form as the "insns" field of usage_insns. Return true if we
5168 succeed in such transformation.
5170 The transformations look like:
5173 ... p <- i (new insn)
5175 <- ... p ... <- ... i ...
5177 ... i <- p (new insn)
5178 <- ... p ... <- ... i ...
5180 <- ... p ... <- ... i ...
5181 where p is a spilled original pseudo and i is a new inheritance pseudo.
5184 The inheritance pseudo has the smallest class of two classes CL and
5185 class of ORIGINAL REGNO. */
5187 inherit_reload_reg (bool def_p
, int original_regno
,
5188 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5190 if (optimize_function_for_size_p (cfun
))
5193 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5194 rtx original_reg
= regno_reg_rtx
[original_regno
];
5195 rtx new_reg
, usage_insn
;
5196 rtx_insn
*new_insns
;
5198 lra_assert (! usage_insns
[original_regno
].after_p
);
5199 if (lra_dump_file
!= NULL
)
5200 fprintf (lra_dump_file
,
5201 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5202 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5204 if (lra_dump_file
!= NULL
)
5206 fprintf (lra_dump_file
,
5207 " Rejecting inheritance for %d "
5208 "because of disjoint classes %s and %s\n",
5209 original_regno
, reg_class_names
[cl
],
5210 reg_class_names
[rclass
]);
5211 fprintf (lra_dump_file
,
5212 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5216 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5217 /* We don't use a subset of two classes because it can be
5218 NO_REGS. This transformation is still profitable in most
5219 cases even if the classes are not intersected as register
5220 move is probably cheaper than a memory load. */
5221 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5223 if (lra_dump_file
!= NULL
)
5224 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5225 reg_class_names
[cl
], reg_class_names
[rclass
]);
5229 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5231 /* Reject inheritance resulting in secondary memory moves.
5232 Otherwise, there is a danger in LRA cycling. Also such
5233 transformation will be unprofitable. */
5234 if (lra_dump_file
!= NULL
)
5236 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5237 rtx set
= single_set (insn
);
5239 lra_assert (set
!= NULL_RTX
);
5241 rtx dest
= SET_DEST (set
);
5243 lra_assert (REG_P (dest
));
5244 fprintf (lra_dump_file
,
5245 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5246 "as secondary mem is needed\n",
5247 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5248 original_regno
, reg_class_names
[rclass
]);
5249 fprintf (lra_dump_file
,
5250 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5254 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5255 rclass
, "inheritance");
5258 lra_emit_move (original_reg
, new_reg
);
5260 lra_emit_move (new_reg
, original_reg
);
5261 new_insns
= get_insns ();
5263 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5265 if (lra_dump_file
!= NULL
)
5267 fprintf (lra_dump_file
,
5268 " Rejecting inheritance %d->%d "
5269 "as it results in 2 or more insns:\n",
5270 original_regno
, REGNO (new_reg
));
5271 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5272 fprintf (lra_dump_file
,
5273 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5277 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5278 lra_update_insn_regno_info (insn
);
5280 /* We now have a new usage insn for original regno. */
5281 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5282 if (lra_dump_file
!= NULL
)
5283 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5284 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5285 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5286 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5287 bitmap_set_bit (&check_only_regs
, original_regno
);
5288 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5290 lra_process_new_insns (insn
, NULL
, new_insns
,
5291 "Add original<-inheritance");
5293 lra_process_new_insns (insn
, new_insns
, NULL
,
5294 "Add inheritance<-original");
5295 while (next_usage_insns
!= NULL_RTX
)
5297 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5299 usage_insn
= next_usage_insns
;
5300 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5301 next_usage_insns
= NULL
;
5305 usage_insn
= XEXP (next_usage_insns
, 0);
5306 lra_assert (DEBUG_INSN_P (usage_insn
));
5307 next_usage_insns
= XEXP (next_usage_insns
, 1);
5309 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5310 DEBUG_INSN_P (usage_insn
));
5311 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5312 if (lra_dump_file
!= NULL
)
5314 basic_block bb
= BLOCK_FOR_INSN (usage_insn
);
5315 fprintf (lra_dump_file
,
5316 " Inheritance reuse change %d->%d (bb%d):\n",
5317 original_regno
, REGNO (new_reg
),
5318 bb
? bb
->index
: -1);
5319 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5322 if (lra_dump_file
!= NULL
)
5323 fprintf (lra_dump_file
,
5324 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5328 /* Return true if we need a caller save/restore for pseudo REGNO which
5329 was assigned to a hard register. */
5331 need_for_call_save_p (int regno
)
5333 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5334 return (usage_insns
[regno
].calls_num
< calls_num
5335 && (overlaps_hard_reg_set_p
5337 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
5338 ? lra_reg_info
[regno
].actual_call_used_reg_set
5339 : call_used_reg_set
,
5340 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
5341 || (targetm
.hard_regno_call_part_clobbered
5342 (reg_renumber
[regno
], PSEUDO_REGNO_MODE (regno
)))));
5345 /* Global registers occurring in the current EBB. */
5346 static bitmap_head ebb_global_regs
;
5348 /* Return true if we need a split for hard register REGNO or pseudo
5349 REGNO which was assigned to a hard register.
5350 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5351 used for reloads since the EBB end. It is an approximation of the
5352 used hard registers in the split range. The exact value would
5353 require expensive calculations. If we were aggressive with
5354 splitting because of the approximation, the split pseudo will save
5355 the same hard register assignment and will be removed in the undo
5356 pass. We still need the approximation because too aggressive
5357 splitting would result in too inaccurate cost calculation in the
5358 assignment pass because of too many generated moves which will be
5359 probably removed in the undo pass. */
5361 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5363 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5365 lra_assert (hard_regno
>= 0);
5366 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5367 /* Don't split eliminable hard registers, otherwise we can
5368 split hard registers like hard frame pointer, which
5369 lives on BB start/end according to DF-infrastructure,
5370 when there is a pseudo assigned to the register and
5371 living in the same BB. */
5372 && (regno
>= FIRST_PSEUDO_REGISTER
5373 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5374 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5375 /* Don't split call clobbered hard regs living through
5376 calls, otherwise we might have a check problem in the
5377 assign sub-pass as in the most cases (exception is a
5378 situation when lra_risky_transformations_p value is
5379 true) the assign pass assumes that all pseudos living
5380 through calls are assigned to call saved hard regs. */
5381 && (regno
>= FIRST_PSEUDO_REGISTER
5382 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
5383 || usage_insns
[regno
].calls_num
== calls_num
)
5384 /* We need at least 2 reloads to make pseudo splitting
5385 profitable. We should provide hard regno splitting in
5386 any case to solve 1st insn scheduling problem when
5387 moving hard register definition up might result in
5388 impossibility to find hard register for reload pseudo of
5389 small register class. */
5390 && (usage_insns
[regno
].reloads_num
5391 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5392 && (regno
< FIRST_PSEUDO_REGISTER
5393 /* For short living pseudos, spilling + inheritance can
5394 be considered a substitution for splitting.
5395 Therefore we do not splitting for local pseudos. It
5396 decreases also aggressiveness of splitting. The
5397 minimal number of references is chosen taking into
5398 account that for 2 references splitting has no sense
5399 as we can just spill the pseudo. */
5400 || (regno
>= FIRST_PSEUDO_REGISTER
5401 && lra_reg_info
[regno
].nrefs
> 3
5402 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5403 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5406 /* Return class for the split pseudo created from original pseudo with
5407 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5408 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5409 results in no secondary memory movements. */
5410 static enum reg_class
5411 choose_split_class (enum reg_class allocno_class
,
5412 int hard_regno ATTRIBUTE_UNUSED
,
5413 machine_mode mode ATTRIBUTE_UNUSED
)
5416 enum reg_class cl
, best_cl
= NO_REGS
;
5417 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5418 = REGNO_REG_CLASS (hard_regno
);
5420 if (! targetm
.secondary_memory_needed (mode
, allocno_class
, allocno_class
)
5421 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5422 return allocno_class
;
5424 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5426 if (! targetm
.secondary_memory_needed (mode
, cl
, hard_reg_class
)
5427 && ! targetm
.secondary_memory_needed (mode
, hard_reg_class
, cl
)
5428 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5429 && (best_cl
== NO_REGS
5430 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5435 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5436 It only makes sense to call this function if NEW_REGNO is always
5437 equal to ORIGINAL_REGNO. */
5440 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
)
5442 if (!ira_reg_equiv
[original_regno
].defined_p
)
5445 ira_expand_reg_equiv ();
5446 ira_reg_equiv
[new_regno
].defined_p
= true;
5447 if (ira_reg_equiv
[original_regno
].memory
)
5448 ira_reg_equiv
[new_regno
].memory
5449 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
5450 if (ira_reg_equiv
[original_regno
].constant
)
5451 ira_reg_equiv
[new_regno
].constant
5452 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
5453 if (ira_reg_equiv
[original_regno
].invariant
)
5454 ira_reg_equiv
[new_regno
].invariant
5455 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
5458 /* Do split transformations for insn INSN, which defines or uses
5459 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5460 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5461 "insns" field of usage_insns. If TO is not NULL, we don't use
5462 usage_insns, we put restore insns after TO insn.
5464 The transformations look like:
5467 ... s <- p (new insn -- save)
5469 ... p <- s (new insn -- restore)
5470 <- ... p ... <- ... p ...
5472 <- ... p ... <- ... p ...
5473 ... s <- p (new insn -- save)
5475 ... p <- s (new insn -- restore)
5476 <- ... p ... <- ... p ...
5478 where p is an original pseudo got a hard register or a hard
5479 register and s is a new split pseudo. The save is put before INSN
5480 if BEFORE_P is true. Return true if we succeed in such
5483 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5484 rtx next_usage_insns
, rtx_insn
*to
)
5486 enum reg_class rclass
;
5488 int hard_regno
, nregs
;
5489 rtx new_reg
, usage_insn
;
5490 rtx_insn
*restore
, *save
;
5495 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5497 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5498 hard_regno
= original_regno
;
5499 call_save_p
= false;
5501 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5502 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5503 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5504 as part of a multi-word register. In that case, or if the biggest
5505 mode was larger than a register, just use the reg_rtx. Otherwise,
5506 limit the size to that of the biggest access in the function. */
5507 if (mode
== VOIDmode
5508 || paradoxical_subreg_p (mode
, reg_rtx_mode
))
5510 original_reg
= regno_reg_rtx
[hard_regno
];
5511 mode
= reg_rtx_mode
;
5514 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5518 mode
= PSEUDO_REGNO_MODE (original_regno
);
5519 hard_regno
= reg_renumber
[original_regno
];
5520 nregs
= hard_regno_nregs (hard_regno
, mode
);
5521 rclass
= lra_get_allocno_class (original_regno
);
5522 original_reg
= regno_reg_rtx
[original_regno
];
5523 call_save_p
= need_for_call_save_p (original_regno
);
5525 lra_assert (hard_regno
>= 0);
5526 if (lra_dump_file
!= NULL
)
5527 fprintf (lra_dump_file
,
5528 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5532 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5533 hard_regno_nregs (hard_regno
, mode
),
5535 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5539 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5540 if (rclass
== NO_REGS
)
5542 if (lra_dump_file
!= NULL
)
5544 fprintf (lra_dump_file
,
5545 " Rejecting split of %d(%s): "
5546 "no good reg class for %d(%s)\n",
5548 reg_class_names
[lra_get_allocno_class (original_regno
)],
5550 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5553 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5557 /* Split_if_necessary can split hard registers used as part of a
5558 multi-register mode but splits each register individually. The
5559 mode used for each independent register may not be supported
5560 so reject the split. Splitting the wider mode should theoretically
5561 be possible but is not implemented. */
5562 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
5564 if (lra_dump_file
!= NULL
)
5566 fprintf (lra_dump_file
,
5567 " Rejecting split of %d(%s): unsuitable mode %s\n",
5569 reg_class_names
[lra_get_allocno_class (original_regno
)],
5570 GET_MODE_NAME (mode
));
5573 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5577 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5578 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5580 int new_regno
= REGNO (new_reg
);
5581 save
= emit_spill_move (true, new_reg
, original_reg
);
5582 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5584 if (lra_dump_file
!= NULL
)
5588 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5589 original_regno
, new_regno
);
5590 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5591 fprintf (lra_dump_file
,
5592 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5596 restore
= emit_spill_move (false, new_reg
, original_reg
);
5597 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5599 if (lra_dump_file
!= NULL
)
5601 fprintf (lra_dump_file
,
5602 " Rejecting split %d->%d "
5603 "resulting in > 2 restore insns:\n",
5604 original_regno
, new_regno
);
5605 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5606 fprintf (lra_dump_file
,
5607 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5611 /* Transfer equivalence information to the spill register, so that
5612 if we fail to allocate the spill register, we have the option of
5613 rematerializing the original value instead of spilling to the stack. */
5614 if (!HARD_REGISTER_NUM_P (original_regno
)
5615 && mode
== PSEUDO_REGNO_MODE (original_regno
))
5616 lra_copy_reg_equiv (new_regno
, original_regno
);
5617 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
5618 bitmap_set_bit (&check_only_regs
, new_regno
);
5619 bitmap_set_bit (&check_only_regs
, original_regno
);
5620 bitmap_set_bit (&lra_split_regs
, new_regno
);
5628 after_p
= usage_insns
[original_regno
].after_p
;
5631 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5633 usage_insn
= next_usage_insns
;
5636 usage_insn
= XEXP (next_usage_insns
, 0);
5637 lra_assert (DEBUG_INSN_P (usage_insn
));
5638 next_usage_insns
= XEXP (next_usage_insns
, 1);
5639 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5641 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5642 if (lra_dump_file
!= NULL
)
5644 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5645 original_regno
, new_regno
);
5646 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5650 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5651 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5652 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5653 after_p
? NULL
: restore
,
5654 after_p
? restore
: NULL
,
5656 ? "Add reg<-save" : "Add reg<-split");
5657 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5658 before_p
? NULL
: save
,
5660 ? "Add save<-reg" : "Add split<-reg");
5662 /* If we are trying to split multi-register. We should check
5663 conflicts on the next assignment sub-pass. IRA can allocate on
5664 sub-register levels, LRA do this on pseudos level right now and
5665 this discrepancy may create allocation conflicts after
5667 lra_risky_transformations_p
= true;
5668 if (lra_dump_file
!= NULL
)
5669 fprintf (lra_dump_file
,
5670 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5674 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
5675 in the range [FROM, TO]. Return true if did a split. Otherwise,
5678 spill_hard_reg_in_range (int regno
, enum reg_class rclass
, rtx_insn
*from
, rtx_insn
*to
)
5684 lra_assert (from
!= NULL
&& to
!= NULL
);
5685 rclass_size
= ira_class_hard_regs_num
[rclass
];
5686 for (i
= 0; i
< rclass_size
; i
++)
5688 hard_regno
= ira_class_hard_regs
[rclass
][i
];
5689 if (! TEST_HARD_REG_BIT (lra_reg_info
[regno
].conflict_hard_regs
, hard_regno
))
5691 for (insn
= from
; insn
!= NEXT_INSN (to
); insn
= NEXT_INSN (insn
))
5692 if (bitmap_bit_p (&lra_reg_info
[hard_regno
].insn_bitmap
,
5695 if (insn
!= NEXT_INSN (to
))
5697 if (split_reg (TRUE
, hard_regno
, from
, NULL
, to
))
5703 /* Recognize that we need a split transformation for insn INSN, which
5704 defines or uses REGNO in its insn biggest MODE (we use it only if
5705 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5706 hard registers which might be used for reloads since the EBB end.
5707 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5708 uid before starting INSN processing. Return true if we succeed in
5709 such transformation. */
5711 split_if_necessary (int regno
, machine_mode mode
,
5712 HARD_REG_SET potential_reload_hard_regs
,
5713 bool before_p
, rtx_insn
*insn
, int max_uid
)
5717 rtx next_usage_insns
;
5719 if (regno
< FIRST_PSEUDO_REGISTER
)
5720 nregs
= hard_regno_nregs (regno
, mode
);
5721 for (i
= 0; i
< nregs
; i
++)
5722 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5723 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5724 /* To avoid processing the register twice or more. */
5725 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5726 && INSN_UID (next_usage_insns
) < max_uid
)
5727 || (GET_CODE (next_usage_insns
) == INSN_LIST
5728 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5729 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5730 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
, NULL
))
5735 /* Return TRUE if rtx X is considered as an invariant for
5738 invariant_p (const_rtx x
)
5745 code
= GET_CODE (x
);
5746 mode
= GET_MODE (x
);
5750 code
= GET_CODE (x
);
5751 mode
= wider_subreg_mode (mode
, GET_MODE (x
));
5759 int i
, nregs
, regno
= REGNO (x
);
5761 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5762 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5763 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5765 nregs
= hard_regno_nregs (regno
, mode
);
5766 for (i
= 0; i
< nregs
; i
++)
5767 if (! fixed_regs
[regno
+ i
]
5768 /* A hard register may be clobbered in the current insn
5769 but we can ignore this case because if the hard
5770 register is used it should be set somewhere after the
5772 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
5775 fmt
= GET_RTX_FORMAT (code
);
5776 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5780 if (! invariant_p (XEXP (x
, i
)))
5783 else if (fmt
[i
] == 'E')
5785 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5786 if (! invariant_p (XVECEXP (x
, i
, j
)))
5793 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5794 inheritance transformation (using dest_reg instead invariant in a
5795 subsequent insn). */
5797 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
5799 invariant_ptr_t invariant_ptr
;
5800 rtx_insn
*insn
, *new_insns
;
5801 rtx insn_set
, insn_reg
, new_reg
;
5803 bool succ_p
= false;
5804 int dst_regno
= REGNO (dst_reg
);
5805 machine_mode dst_mode
= GET_MODE (dst_reg
);
5806 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
5808 invariant_ptr
= insert_invariant (invariant_rtx
);
5809 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
5811 /* We have a subsequent insn using the invariant. */
5812 insn_set
= single_set (insn
);
5813 lra_assert (insn_set
!= NULL
);
5814 insn_reg
= SET_DEST (insn_set
);
5815 lra_assert (REG_P (insn_reg
));
5816 insn_regno
= REGNO (insn_reg
);
5817 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
5819 if (dst_mode
== GET_MODE (insn_reg
)
5820 /* We should consider only result move reg insns which are
5822 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
5823 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
5825 if (lra_dump_file
!= NULL
)
5826 fprintf (lra_dump_file
,
5827 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5828 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
5829 cl
, "invariant inheritance");
5830 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5831 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5832 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
5834 lra_emit_move (new_reg
, dst_reg
);
5835 new_insns
= get_insns ();
5837 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
5838 "Add invariant inheritance<-original");
5840 lra_emit_move (SET_DEST (insn_set
), new_reg
);
5841 new_insns
= get_insns ();
5843 lra_process_new_insns (insn
, NULL
, new_insns
,
5844 "Changing reload<-inheritance");
5845 lra_set_insn_deleted (insn
);
5847 if (lra_dump_file
!= NULL
)
5849 fprintf (lra_dump_file
,
5850 " Invariant inheritance reuse change %d (bb%d):\n",
5851 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5852 dump_insn_slim (lra_dump_file
, insn
);
5853 fprintf (lra_dump_file
,
5854 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5858 invariant_ptr
->insn
= curr_insn
;
5862 /* Check only registers living at the current program point in the
5864 static bitmap_head live_regs
;
5866 /* Update live info in EBB given by its HEAD and TAIL insns after
5867 inheritance/split transformation. The function removes dead moves
5870 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5875 rtx_insn
*prev_insn
;
5878 basic_block last_bb
, prev_bb
, curr_bb
;
5880 struct lra_insn_reg
*reg
;
5884 last_bb
= BLOCK_FOR_INSN (tail
);
5886 for (curr_insn
= tail
;
5887 curr_insn
!= PREV_INSN (head
);
5888 curr_insn
= prev_insn
)
5890 prev_insn
= PREV_INSN (curr_insn
);
5891 /* We need to process empty blocks too. They contain
5892 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5893 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5895 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5896 if (curr_bb
!= prev_bb
)
5898 if (prev_bb
!= NULL
)
5900 /* Update df_get_live_in (prev_bb): */
5901 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5902 if (bitmap_bit_p (&live_regs
, j
))
5903 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5905 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5907 if (curr_bb
!= last_bb
)
5909 /* Update df_get_live_out (curr_bb): */
5910 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5912 live_p
= bitmap_bit_p (&live_regs
, j
);
5914 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5915 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5921 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5923 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5927 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5929 if (! NONDEBUG_INSN_P (curr_insn
))
5931 curr_id
= lra_get_insn_recog_data (curr_insn
);
5932 curr_static_id
= curr_id
->insn_static_data
;
5934 if ((set
= single_set (curr_insn
)) != NULL_RTX
5935 && REG_P (SET_DEST (set
))
5936 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5937 && SET_DEST (set
) != pic_offset_table_rtx
5938 && bitmap_bit_p (&check_only_regs
, regno
)
5939 && ! bitmap_bit_p (&live_regs
, regno
))
5941 /* See which defined values die here. */
5942 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5943 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5944 bitmap_clear_bit (&live_regs
, reg
->regno
);
5945 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5946 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5947 bitmap_clear_bit (&live_regs
, reg
->regno
);
5948 if (curr_id
->arg_hard_regs
!= NULL
)
5949 /* Make clobbered argument hard registers die. */
5950 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5951 if (regno
>= FIRST_PSEUDO_REGISTER
)
5952 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
5953 /* Mark each used value as live. */
5954 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5955 if (reg
->type
!= OP_OUT
5956 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5957 bitmap_set_bit (&live_regs
, reg
->regno
);
5958 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5959 if (reg
->type
!= OP_OUT
5960 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5961 bitmap_set_bit (&live_regs
, reg
->regno
);
5962 if (curr_id
->arg_hard_regs
!= NULL
)
5963 /* Make used argument hard registers live. */
5964 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5965 if (regno
< FIRST_PSEUDO_REGISTER
5966 && bitmap_bit_p (&check_only_regs
, regno
))
5967 bitmap_set_bit (&live_regs
, regno
);
5968 /* It is quite important to remove dead move insns because it
5969 means removing dead store. We don't need to process them for
5973 if (lra_dump_file
!= NULL
)
5975 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5976 dump_insn_slim (lra_dump_file
, curr_insn
);
5978 lra_set_insn_deleted (curr_insn
);
5983 /* The structure describes info to do an inheritance for the current
5984 insn. We need to collect such info first before doing the
5985 transformations because the transformations change the insn
5986 internal representation. */
5989 /* Original regno. */
5991 /* Subsequent insns which can inherit original reg value. */
5995 /* Array containing all info for doing inheritance from the current
5997 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5999 /* Number elements in the previous array. */
6000 static int to_inherit_num
;
6002 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6003 structure to_inherit. */
6005 add_to_inherit (int regno
, rtx insns
)
6009 for (i
= 0; i
< to_inherit_num
; i
++)
6010 if (to_inherit
[i
].regno
== regno
)
6012 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
6013 to_inherit
[to_inherit_num
].regno
= regno
;
6014 to_inherit
[to_inherit_num
++].insns
= insns
;
6017 /* Return the last non-debug insn in basic block BB, or the block begin
6020 get_last_insertion_point (basic_block bb
)
6024 FOR_BB_INSNS_REVERSE (bb
, insn
)
6025 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
6030 /* Set up RES by registers living on edges FROM except the edge (FROM,
6031 TO) or by registers set up in a jump insn in BB FROM. */
6033 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
6036 struct lra_insn_reg
*reg
;
6040 lra_assert (to
!= NULL
);
6042 FOR_EACH_EDGE (e
, ei
, from
->succs
)
6044 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
6045 last
= get_last_insertion_point (from
);
6046 if (! JUMP_P (last
))
6048 curr_id
= lra_get_insn_recog_data (last
);
6049 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6050 if (reg
->type
!= OP_IN
)
6051 bitmap_set_bit (res
, reg
->regno
);
6054 /* Used as a temporary results of some bitmap calculations. */
6055 static bitmap_head temp_bitmap
;
6057 /* We split for reloads of small class of hard regs. The following
6058 defines how many hard regs the class should have to be qualified as
6059 small. The code is mostly oriented to x86/x86-64 architecture
6060 where some insns need to use only specific register or pair of
6061 registers and these register can live in RTL explicitly, e.g. for
6062 parameter passing. */
6063 static const int max_small_class_regs_num
= 2;
6065 /* Do inheritance/split transformations in EBB starting with HEAD and
6066 finishing on TAIL. We process EBB insns in the reverse order.
6067 Return true if we did any inheritance/split transformation in the
6070 We should avoid excessive splitting which results in worse code
6071 because of inaccurate cost calculations for spilling new split
6072 pseudos in such case. To achieve this we do splitting only if
6073 register pressure is high in given basic block and there are reload
6074 pseudos requiring hard registers. We could do more register
6075 pressure calculations at any given program point to avoid necessary
6076 splitting even more but it is to expensive and the current approach
6077 works well enough. */
6079 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6081 int i
, src_regno
, dst_regno
, nregs
;
6082 bool change_p
, succ_p
, update_reloads_num_p
;
6083 rtx_insn
*prev_insn
, *last_insn
;
6084 rtx next_usage_insns
, curr_set
;
6086 struct lra_insn_reg
*reg
;
6087 basic_block last_processed_bb
, curr_bb
= NULL
;
6088 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6092 bool head_p
, after_p
;
6095 curr_usage_insns_check
++;
6096 clear_invariants ();
6097 reloads_num
= calls_num
= 0;
6098 bitmap_clear (&check_only_regs
);
6099 bitmap_clear (&invalid_invariant_regs
);
6100 last_processed_bb
= NULL
;
6101 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6102 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
6103 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
6104 /* We don't process new insns generated in the loop. */
6105 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6107 prev_insn
= PREV_INSN (curr_insn
);
6108 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6109 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6110 if (last_processed_bb
!= curr_bb
)
6112 /* We are at the end of BB. Add qualified living
6113 pseudos for potential splitting. */
6114 to_process
= df_get_live_out (curr_bb
);
6115 if (last_processed_bb
!= NULL
)
6117 /* We are somewhere in the middle of EBB. */
6118 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6120 to_process
= &temp_bitmap
;
6122 last_processed_bb
= curr_bb
;
6123 last_insn
= get_last_insertion_point (curr_bb
);
6124 after_p
= (! JUMP_P (last_insn
)
6125 && (! CALL_P (last_insn
)
6126 || (find_reg_note (last_insn
,
6127 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6128 && ! SIBLING_CALL_P (last_insn
))));
6129 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6130 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6132 if ((int) j
>= lra_constraint_new_regno_start
)
6134 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6136 if (j
< FIRST_PSEUDO_REGISTER
)
6137 SET_HARD_REG_BIT (live_hard_regs
, j
);
6139 add_to_hard_reg_set (&live_hard_regs
,
6140 PSEUDO_REGNO_MODE (j
),
6142 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6146 src_regno
= dst_regno
= -1;
6147 curr_set
= single_set (curr_insn
);
6148 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6149 dst_regno
= REGNO (SET_DEST (curr_set
));
6150 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6151 src_regno
= REGNO (SET_SRC (curr_set
));
6152 update_reloads_num_p
= true;
6153 if (src_regno
< lra_constraint_new_regno_start
6154 && src_regno
>= FIRST_PSEUDO_REGISTER
6155 && reg_renumber
[src_regno
] < 0
6156 && dst_regno
>= lra_constraint_new_regno_start
6157 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6159 /* 'reload_pseudo <- original_pseudo'. */
6160 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6162 update_reloads_num_p
= false;
6164 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6165 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6166 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6167 curr_insn
, next_usage_insns
);
6171 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6172 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6173 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6174 reg_class_contents
[cl
]);
6176 else if (src_regno
< 0
6177 && dst_regno
>= lra_constraint_new_regno_start
6178 && invariant_p (SET_SRC (curr_set
))
6179 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6180 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6181 && ! bitmap_bit_p (&invalid_invariant_regs
,
6182 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6184 /* 'reload_pseudo <- invariant'. */
6185 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6187 update_reloads_num_p
= false;
6188 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6190 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6191 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6192 reg_class_contents
[cl
]);
6194 else if (src_regno
>= lra_constraint_new_regno_start
6195 && dst_regno
< lra_constraint_new_regno_start
6196 && dst_regno
>= FIRST_PSEUDO_REGISTER
6197 && reg_renumber
[dst_regno
] < 0
6198 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6199 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6200 && (next_usage_insns
6201 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6203 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6205 update_reloads_num_p
= false;
6206 /* 'original_pseudo <- reload_pseudo'. */
6207 if (! JUMP_P (curr_insn
)
6208 && inherit_reload_reg (true, dst_regno
, cl
,
6209 curr_insn
, next_usage_insns
))
6212 usage_insns
[dst_regno
].check
= 0;
6213 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6214 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6215 reg_class_contents
[cl
]);
6217 else if (INSN_P (curr_insn
))
6220 int max_uid
= get_max_uid ();
6222 curr_id
= lra_get_insn_recog_data (curr_insn
);
6223 curr_static_id
= curr_id
->insn_static_data
;
6225 /* Process insn definitions. */
6226 for (iter
= 0; iter
< 2; iter
++)
6227 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6230 if (reg
->type
!= OP_IN
6231 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6233 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6234 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6235 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6236 && (next_usage_insns
6237 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6239 struct lra_insn_reg
*r
;
6241 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6242 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6244 /* Don't do inheritance if the pseudo is also
6245 used in the insn. */
6247 /* We can not do inheritance right now
6248 because the current insn reg info (chain
6249 regs) can change after that. */
6250 add_to_inherit (dst_regno
, next_usage_insns
);
6252 /* We can not process one reg twice here because of
6253 usage_insns invalidation. */
6254 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6255 || reg_renumber
[dst_regno
] >= 0)
6256 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6260 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6261 potential_reload_hard_regs
,
6262 false, curr_insn
, max_uid
))
6264 CLEAR_HARD_REG_SET (s
);
6265 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6266 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6268 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6269 reg_renumber
[dst_regno
]);
6270 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
6272 /* We should invalidate potential inheritance or
6273 splitting for the current insn usages to the next
6274 usage insns (see code below) as the output pseudo
6276 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6277 && reg_renumber
[dst_regno
] < 0)
6278 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6279 && (dst_regno
< FIRST_PSEUDO_REGISTER
6280 || reg_renumber
[dst_regno
] >= 0)))
6282 /* Invalidate and mark definitions. */
6283 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6284 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6287 nregs
= hard_regno_nregs (dst_regno
,
6289 for (i
= 0; i
< nregs
; i
++)
6290 usage_insns
[dst_regno
+ i
].check
6291 = -(int) INSN_UID (curr_insn
);
6295 /* Process clobbered call regs. */
6296 if (curr_id
->arg_hard_regs
!= NULL
)
6297 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6298 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6299 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6300 = -(int) INSN_UID (curr_insn
);
6301 if (! JUMP_P (curr_insn
))
6302 for (i
= 0; i
< to_inherit_num
; i
++)
6303 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6304 ALL_REGS
, curr_insn
,
6305 to_inherit
[i
].insns
))
6307 if (CALL_P (curr_insn
))
6309 rtx cheap
, pat
, dest
;
6311 int regno
, hard_regno
;
6314 if ((cheap
= find_reg_note (curr_insn
,
6315 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6316 && ((cheap
= XEXP (cheap
, 0)), true)
6317 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6318 && (hard_regno
= reg_renumber
[regno
]) >= 0
6319 && usage_insns
[regno
].check
== curr_usage_insns_check
6320 /* If there are pending saves/restores, the
6321 optimization is not worth. */
6322 && usage_insns
[regno
].calls_num
== calls_num
- 1
6323 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
6325 /* Restore the pseudo from the call result as
6326 REG_RETURNED note says that the pseudo value is
6327 in the call result and the pseudo is an argument
6329 pat
= PATTERN (curr_insn
);
6330 if (GET_CODE (pat
) == PARALLEL
)
6331 pat
= XVECEXP (pat
, 0, 0);
6332 dest
= SET_DEST (pat
);
6333 /* For multiple return values dest is PARALLEL.
6334 Currently we handle only single return value case. */
6338 emit_move_insn (cheap
, copy_rtx (dest
));
6339 restore
= get_insns ();
6341 lra_process_new_insns (curr_insn
, NULL
, restore
,
6342 "Inserting call parameter restore");
6343 /* We don't need to save/restore of the pseudo from
6345 usage_insns
[regno
].calls_num
= calls_num
;
6346 bitmap_set_bit (&check_only_regs
, regno
);
6351 /* Process insn usages. */
6352 for (iter
= 0; iter
< 2; iter
++)
6353 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6356 if ((reg
->type
!= OP_OUT
6357 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6358 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6360 if (src_regno
>= FIRST_PSEUDO_REGISTER
6361 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6363 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6364 && (next_usage_insns
6365 = usage_insns
[src_regno
].insns
) != NULL_RTX
6366 && NONDEBUG_INSN_P (curr_insn
))
6367 add_to_inherit (src_regno
, next_usage_insns
);
6368 else if (usage_insns
[src_regno
].check
6369 != -(int) INSN_UID (curr_insn
))
6370 /* Add usages but only if the reg is not set up
6371 in the same insn. */
6372 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6374 else if (src_regno
< FIRST_PSEUDO_REGISTER
6375 || reg_renumber
[src_regno
] >= 0)
6378 rtx_insn
*use_insn
= curr_insn
;
6380 before_p
= (JUMP_P (curr_insn
)
6381 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6382 if (NONDEBUG_INSN_P (curr_insn
)
6383 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6384 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6385 potential_reload_hard_regs
,
6386 before_p
, curr_insn
, max_uid
))
6389 lra_risky_transformations_p
= true;
6392 usage_insns
[src_regno
].check
= 0;
6394 use_insn
= PREV_INSN (curr_insn
);
6396 if (NONDEBUG_INSN_P (curr_insn
))
6398 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6399 add_to_hard_reg_set (&live_hard_regs
,
6400 reg
->biggest_mode
, src_regno
);
6402 add_to_hard_reg_set (&live_hard_regs
,
6403 PSEUDO_REGNO_MODE (src_regno
),
6404 reg_renumber
[src_regno
]);
6406 if (src_regno
>= FIRST_PSEUDO_REGISTER
)
6407 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6410 for (i
= 0; i
< hard_regno_nregs (src_regno
, reg
->biggest_mode
); i
++)
6411 add_next_usage_insn (src_regno
+ i
, use_insn
, reloads_num
);
6415 /* Process used call regs. */
6416 if (curr_id
->arg_hard_regs
!= NULL
)
6417 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6418 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6420 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6421 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6423 for (i
= 0; i
< to_inherit_num
; i
++)
6425 src_regno
= to_inherit
[i
].regno
;
6426 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6427 curr_insn
, to_inherit
[i
].insns
))
6430 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6433 if (update_reloads_num_p
6434 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6437 if ((REG_P (SET_DEST (curr_set
))
6438 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6439 && reg_renumber
[regno
] < 0
6440 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6441 || (REG_P (SET_SRC (curr_set
))
6442 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6443 && reg_renumber
[regno
] < 0
6444 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6446 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6448 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6449 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6450 reg_class_contents
[cl
]);
6453 if (NONDEBUG_INSN_P (curr_insn
))
6457 /* Invalidate invariants with changed regs. */
6458 curr_id
= lra_get_insn_recog_data (curr_insn
);
6459 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6460 if (reg
->type
!= OP_IN
)
6462 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6463 bitmap_set_bit (&invalid_invariant_regs
,
6464 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6466 curr_static_id
= curr_id
->insn_static_data
;
6467 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6468 if (reg
->type
!= OP_IN
)
6469 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6470 if (curr_id
->arg_hard_regs
!= NULL
)
6471 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6472 if (regno
>= FIRST_PSEUDO_REGISTER
)
6473 bitmap_set_bit (&invalid_invariant_regs
,
6474 regno
- FIRST_PSEUDO_REGISTER
);
6476 /* We reached the start of the current basic block. */
6477 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6478 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6480 /* We reached the beginning of the current block -- do
6481 rest of spliting in the current BB. */
6482 to_process
= df_get_live_in (curr_bb
);
6483 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6485 /* We are somewhere in the middle of EBB. */
6486 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6487 curr_bb
, &temp_bitmap
);
6488 to_process
= &temp_bitmap
;
6491 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6493 if ((int) j
>= lra_constraint_new_regno_start
)
6495 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6496 && usage_insns
[j
].check
== curr_usage_insns_check
6497 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6499 if (need_for_split_p (potential_reload_hard_regs
, j
))
6501 if (lra_dump_file
!= NULL
&& head_p
)
6503 fprintf (lra_dump_file
,
6504 " ----------------------------------\n");
6507 if (split_reg (false, j
, bb_note (curr_bb
),
6508 next_usage_insns
, NULL
))
6511 usage_insns
[j
].check
= 0;
6519 /* This value affects EBB forming. If probability of edge from EBB to
6520 a BB is not greater than the following value, we don't add the BB
6522 #define EBB_PROBABILITY_CUTOFF \
6523 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6525 /* Current number of inheritance/split iteration. */
6526 int lra_inheritance_iter
;
6528 /* Entry function for inheritance/split pass. */
6530 lra_inheritance (void)
6533 basic_block bb
, start_bb
;
6536 lra_inheritance_iter
++;
6537 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6539 timevar_push (TV_LRA_INHERITANCE
);
6540 if (lra_dump_file
!= NULL
)
6541 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6542 lra_inheritance_iter
);
6543 curr_usage_insns_check
= 0;
6544 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6545 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6546 usage_insns
[i
].check
= 0;
6547 bitmap_initialize (&check_only_regs
, ®_obstack
);
6548 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6549 bitmap_initialize (&live_regs
, ®_obstack
);
6550 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6551 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6552 FOR_EACH_BB_FN (bb
, cfun
)
6555 if (lra_dump_file
!= NULL
)
6556 fprintf (lra_dump_file
, "EBB");
6557 /* Form a EBB starting with BB. */
6558 bitmap_clear (&ebb_global_regs
);
6559 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6562 if (lra_dump_file
!= NULL
)
6563 fprintf (lra_dump_file
, " %d", bb
->index
);
6564 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6565 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6567 e
= find_fallthru_edge (bb
->succs
);
6570 if (e
->probability
.initialized_p ()
6571 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
6575 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6576 if (lra_dump_file
!= NULL
)
6577 fprintf (lra_dump_file
, "\n");
6578 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6579 /* Remember that the EBB head and tail can change in
6581 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6583 bitmap_clear (&ebb_global_regs
);
6584 bitmap_clear (&temp_bitmap
);
6585 bitmap_clear (&live_regs
);
6586 bitmap_clear (&invalid_invariant_regs
);
6587 bitmap_clear (&check_only_regs
);
6590 timevar_pop (TV_LRA_INHERITANCE
);
6595 /* This page contains code to undo failed inheritance/split
6598 /* Current number of iteration undoing inheritance/split. */
6599 int lra_undo_inheritance_iter
;
6601 /* Fix BB live info LIVE after removing pseudos created on pass doing
6602 inheritance/split which are REMOVED_PSEUDOS. */
6604 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6609 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6610 if (bitmap_clear_bit (live
, regno
)
6611 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6612 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6615 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6620 if (GET_CODE (reg
) == SUBREG
)
6621 reg
= SUBREG_REG (reg
);
6627 /* Delete a move INSN with destination reg DREGNO and a previous
6628 clobber insn with the same regno. The inheritance/split code can
6629 generate moves with preceding clobber and when we delete such moves
6630 we should delete the clobber insn too to keep the correct life
6633 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6635 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6637 lra_set_insn_deleted (insn
);
6638 lra_assert (dregno
>= 0);
6639 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6640 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6641 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6642 lra_set_insn_deleted (prev_insn
);
6645 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6646 return true if we did any change. The undo transformations for
6647 inheritance looks like
6651 p <- i, i <- p, and i <- i3
6652 where p is original pseudo from which inheritance pseudo i was
6653 created, i and i3 are removed inheritance pseudos, i2 is another
6654 not removed inheritance pseudo. All split pseudos or other
6655 occurrences of removed inheritance pseudos are changed on the
6656 corresponding original pseudos.
6658 The function also schedules insns changed and created during
6659 inheritance/split pass for processing by the subsequent constraint
6662 remove_inheritance_pseudos (bitmap remove_pseudos
)
6665 int regno
, sregno
, prev_sregno
, dregno
;
6668 rtx_insn
*prev_insn
;
6669 bool change_p
, done_p
;
6671 change_p
= ! bitmap_empty_p (remove_pseudos
);
6672 /* We can not finish the function right away if CHANGE_P is true
6673 because we need to marks insns affected by previous
6674 inheritance/split pass for processing by the subsequent
6676 FOR_EACH_BB_FN (bb
, cfun
)
6678 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6679 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6680 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6682 if (! INSN_P (curr_insn
))
6685 sregno
= dregno
= -1;
6686 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6687 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6689 dregno
= get_regno (SET_DEST (set
));
6690 sregno
= get_regno (SET_SRC (set
));
6693 if (sregno
>= 0 && dregno
>= 0)
6695 if (bitmap_bit_p (remove_pseudos
, dregno
)
6696 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6698 /* invariant inheritance pseudo <- original pseudo */
6699 if (lra_dump_file
!= NULL
)
6701 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6702 dump_insn_slim (lra_dump_file
, curr_insn
);
6703 fprintf (lra_dump_file
, "\n");
6705 delete_move_and_clobber (curr_insn
, dregno
);
6708 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6709 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6711 /* reload pseudo <- invariant inheritance pseudo */
6713 /* We can not just change the source. It might be
6714 an insn different from the move. */
6715 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6716 rtx_insn
*new_insns
= get_insns ();
6718 lra_assert (single_set (new_insns
) != NULL
6719 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6720 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6721 "Changing reload<-invariant inheritance");
6722 delete_move_and_clobber (curr_insn
, dregno
);
6725 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6726 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6727 || (bitmap_bit_p (remove_pseudos
, dregno
)
6728 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6729 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6730 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6731 || (bitmap_bit_p (remove_pseudos
, dregno
)
6732 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6733 /* One of the following cases:
6734 original <- removed inheritance pseudo
6735 removed inherit pseudo <- another removed inherit pseudo
6736 removed inherit pseudo <- original pseudo
6738 removed_split_pseudo <- original_reg
6739 original_reg <- removed_split_pseudo */
6741 if (lra_dump_file
!= NULL
)
6743 fprintf (lra_dump_file
, " Removing %s:\n",
6744 bitmap_bit_p (&lra_split_regs
, sregno
)
6745 || bitmap_bit_p (&lra_split_regs
, dregno
)
6746 ? "split" : "inheritance");
6747 dump_insn_slim (lra_dump_file
, curr_insn
);
6749 delete_move_and_clobber (curr_insn
, dregno
);
6752 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6753 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6755 /* Search the following pattern:
6756 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6757 original_pseudo <- inherit_or_split_pseudo1
6758 where the 2nd insn is the current insn and
6759 inherit_or_split_pseudo2 is not removed. If it is found,
6760 change the current insn onto:
6761 original_pseudo <- inherit_or_split_pseudo2. */
6762 for (prev_insn
= PREV_INSN (curr_insn
);
6763 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6764 prev_insn
= PREV_INSN (prev_insn
))
6766 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6767 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6768 /* There should be no subregs in insn we are
6769 searching because only the original reg might
6770 be in subreg when we changed the mode of
6771 load/store for splitting. */
6772 && REG_P (SET_DEST (prev_set
))
6773 && REG_P (SET_SRC (prev_set
))
6774 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6775 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6776 >= FIRST_PSEUDO_REGISTER
)
6777 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
6779 /* As we consider chain of inheritance or
6780 splitting described in above comment we should
6781 check that sregno and prev_sregno were
6782 inheritance/split pseudos created from the
6783 same original regno. */
6784 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6785 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6786 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
6787 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6789 lra_assert (GET_MODE (SET_SRC (prev_set
))
6790 == GET_MODE (regno_reg_rtx
[sregno
]));
6791 /* Although we have a single set, the insn can
6792 contain more one sregno register occurrence
6793 as a source. Change all occurrences. */
6794 lra_substitute_pseudo_within_insn (curr_insn
, sregno
,
6797 /* As we are finishing with processing the insn
6798 here, check the destination too as it might
6799 inheritance pseudo for another pseudo. */
6800 if (bitmap_bit_p (remove_pseudos
, dregno
)
6801 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6803 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
6805 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6806 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
6808 SET_DEST (set
) = restore_rtx
;
6810 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6811 lra_set_used_insn_alternative_by_uid
6812 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
6814 if (lra_dump_file
!= NULL
)
6816 fprintf (lra_dump_file
, " Change reload insn:\n");
6817 dump_insn_slim (lra_dump_file
, curr_insn
);
6824 struct lra_insn_reg
*reg
;
6825 bool restored_regs_p
= false;
6826 bool kept_regs_p
= false;
6828 curr_id
= lra_get_insn_recog_data (curr_insn
);
6829 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6832 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
6833 if (restore_rtx
!= NULL_RTX
)
6835 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6837 lra_substitute_pseudo_within_insn
6838 (curr_insn
, regno
, restore_rtx
, false);
6839 restored_regs_p
= true;
6845 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6847 /* The instruction has changed since the previous
6848 constraints pass. */
6849 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6850 lra_set_used_insn_alternative_by_uid
6851 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
6853 else if (restored_regs_p
)
6854 /* The instruction has been restored to the form that
6855 it had during the previous constraints pass. */
6856 lra_update_insn_regno_info (curr_insn
);
6857 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6859 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6860 dump_insn_slim (lra_dump_file
, curr_insn
);
6868 /* If optional reload pseudos failed to get a hard register or was not
6869 inherited, it is better to remove optional reloads. We do this
6870 transformation after undoing inheritance to figure out necessity to
6871 remove optional reloads easier. Return true if we do any
6874 undo_optional_reloads (void)
6876 bool change_p
, keep_p
;
6877 unsigned int regno
, uid
;
6878 bitmap_iterator bi
, bi2
;
6881 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
6883 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6884 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6887 /* Keep optional reloads from previous subpasses. */
6888 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
6889 /* If the original pseudo changed its allocation, just
6890 removing the optional pseudo is dangerous as the original
6891 pseudo will have longer live range. */
6892 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
6894 else if (reg_renumber
[regno
] >= 0)
6895 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6897 insn
= lra_insn_recog_data
[uid
]->insn
;
6898 if ((set
= single_set (insn
)) == NULL_RTX
)
6900 src
= SET_SRC (set
);
6901 dest
= SET_DEST (set
);
6902 if (! REG_P (src
) || ! REG_P (dest
))
6904 if (REGNO (dest
) == regno
6905 /* Ignore insn for optional reloads itself. */
6906 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
6907 /* Check only inheritance on last inheritance pass. */
6908 && (int) REGNO (src
) >= new_regno_start
6909 /* Check that the optional reload was inherited. */
6910 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6918 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
6919 if (lra_dump_file
!= NULL
)
6920 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6923 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
6924 auto_bitmap
insn_bitmap (®_obstack
);
6925 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
6927 if (lra_dump_file
!= NULL
)
6928 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6929 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6930 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
6932 insn
= lra_insn_recog_data
[uid
]->insn
;
6933 if ((set
= single_set (insn
)) != NULL_RTX
)
6935 src
= SET_SRC (set
);
6936 dest
= SET_DEST (set
);
6937 if (REG_P (src
) && REG_P (dest
)
6938 && ((REGNO (src
) == regno
6939 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6941 || (REGNO (dest
) == regno
6942 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6945 if (lra_dump_file
!= NULL
)
6947 fprintf (lra_dump_file
, " Deleting move %u\n",
6949 dump_insn_slim (lra_dump_file
, insn
);
6951 delete_move_and_clobber (insn
, REGNO (dest
));
6954 /* We should not worry about generation memory-memory
6955 moves here as if the corresponding inheritance did
6956 not work (inheritance pseudo did not get a hard reg),
6957 we remove the inheritance pseudo and the optional
6960 lra_substitute_pseudo_within_insn
6961 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
6962 lra_update_insn_regno_info (insn
);
6963 if (lra_dump_file
!= NULL
)
6965 fprintf (lra_dump_file
,
6966 " Restoring original insn:\n");
6967 dump_insn_slim (lra_dump_file
, insn
);
6971 /* Clear restore_regnos. */
6972 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6973 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6977 /* Entry function for undoing inheritance/split transformation. Return true
6978 if we did any RTL change in this pass. */
6980 lra_undo_inheritance (void)
6984 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6989 lra_undo_inheritance_iter
++;
6990 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6992 if (lra_dump_file
!= NULL
)
6993 fprintf (lra_dump_file
,
6994 "\n********** Undoing inheritance #%d: **********\n\n",
6995 lra_undo_inheritance_iter
);
6996 auto_bitmap
remove_pseudos (®_obstack
);
6997 n_inherit
= n_all_inherit
= 0;
6998 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6999 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
7002 if (reg_renumber
[regno
] < 0
7003 /* If the original pseudo changed its allocation, just
7004 removing inheritance is dangerous as for changing
7005 allocation we used shorter live-ranges. */
7006 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
7007 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
7008 bitmap_set_bit (remove_pseudos
, regno
);
7012 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
7013 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
7014 n_inherit
, n_all_inherit
,
7015 (double) n_inherit
/ n_all_inherit
* 100);
7016 n_split
= n_all_split
= 0;
7017 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7018 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
7020 int restore_regno
= REGNO (restore_rtx
);
7023 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
7024 ? reg_renumber
[restore_regno
] : restore_regno
);
7025 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
7026 bitmap_set_bit (remove_pseudos
, regno
);
7030 if (lra_dump_file
!= NULL
)
7031 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
7032 regno
, restore_regno
);
7035 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
7036 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
7037 n_split
, n_all_split
,
7038 (double) n_split
/ n_all_split
* 100);
7039 change_p
= remove_inheritance_pseudos (remove_pseudos
);
7040 /* Clear restore_regnos. */
7041 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7042 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7043 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7044 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7045 change_p
= undo_optional_reloads () || change_p
;