1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by the Center for Software Science at the University
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Uses of UNSPEC in this file:
31 (define_c_enum "unspec"
32 [UNSPEC_CFFC ; canonicalize_funcptr_for_compare
33 UNSPEC_GOTO ; indirect_goto
49 (define_c_enum "unspecv"
50 [UNSPECV_BLOCKAGE ; blockage
51 UNSPECV_DCACHE ; dcacheflush
52 UNSPECV_ICACHE ; icacheflush
53 UNSPECV_OPC ; outline_prologue_call
54 UNSPECV_OEC ; outline_epilogue_call
55 UNSPECV_LONGJMP ; builtin_longjmp
58 ;; Maximum pc-relative branch offsets.
60 ;; These numbers are a bit smaller than the maximum allowable offsets
61 ;; so that a few instructions may be inserted before the actual branch.
64 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
65 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
68 ;; Mode and code iterators
70 ;; This mode iterator allows :P to be used for patterns that operate on
71 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
72 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
74 ;; This attribute defines the condition prefix for word and double word
75 ;; add, compare, subtract and logical instructions.
76 (define_mode_attr dwc [(SI "") (DI "*")])
78 ;; Insn type. Used to default other attribute values.
80 ;; type "unary" insns have one input operand (1) and one output operand (0)
81 ;; type "binary" insns have two input operands (1,2) and one output (0)
84 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch,fpstore_load,store_fpload"
85 (const_string "binary"))
87 (define_attr "pa_combine_type"
88 "fmpy,faddsub,uncond_branch,addmove,none"
89 (const_string "none"))
91 ;; Processor type (for scheduling, not code generation) -- this attribute
92 ;; must exactly match the processor_type enumeration in pa.h.
94 ;; FIXME: Add 800 scheduling for completeness?
96 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
98 ;; Length (in # of bytes).
99 (define_attr "length" ""
100 (cond [(eq_attr "type" "load,fpload")
101 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
102 (const_int 8) (const_int 4))
104 (eq_attr "type" "store,fpstore")
105 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
106 (const_int 8) (const_int 4))
108 (eq_attr "type" "binary,shift,nullshift")
109 (if_then_else (match_operand 2 "arith14_operand" "")
110 (const_int 4) (const_int 12))
112 (eq_attr "type" "move,unary,shift,nullshift")
113 (if_then_else (match_operand 1 "arith14_operand" "")
114 (const_int 4) (const_int 8))]
118 (define_asm_attributes
119 [(set_attr "length" "4")
120 (set_attr "type" "multi")])
122 ;; Attributes for instruction and branch scheduling
124 ;; For conditional branches. Frame related instructions are not allowed
125 ;; because they confuse the unwind support.
126 (define_attr "in_branch_delay" "false,true"
127 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
128 (eq_attr "length" "4")
129 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
130 (const_string "true")
131 (const_string "false")))
133 ;; Disallow instructions which use the FPU since they will tie up the FPU
134 ;; even if the instruction is nullified.
135 (define_attr "in_nullified_branch_delay" "false,true"
136 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
137 (eq_attr "length" "4")
138 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
139 (const_string "true")
140 (const_string "false")))
142 ;; For calls and millicode calls. Allow unconditional branches in the
144 (define_attr "in_call_delay" "false,true"
145 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
146 (eq_attr "length" "4")
147 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
148 (const_string "true")
149 (eq_attr "type" "uncond_branch")
150 (if_then_else (match_test "TARGET_JUMP_IN_DELAY")
151 (const_string "true")
152 (const_string "false"))]
153 (const_string "false")))
156 ;; Call delay slot description.
157 (define_delay (eq_attr "type" "call")
158 [(eq_attr "in_call_delay" "true") (nil) (nil)])
160 ;; Millicode call delay slot description.
161 (define_delay (eq_attr "type" "milli")
162 [(eq_attr "in_call_delay" "true") (nil) (nil)])
164 ;; Return and other similar instructions.
165 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
166 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
168 ;; Floating point conditional branch delay slot description.
169 (define_delay (eq_attr "type" "fbranch")
170 [(eq_attr "in_branch_delay" "true")
171 (eq_attr "in_nullified_branch_delay" "true")
174 ;; Integer conditional branch delay slot description.
175 ;; Nullification of conditional branches on the PA is dependent on the
176 ;; direction of the branch. Forward branches nullify true and
177 ;; backward branches nullify false. If the direction is unknown
178 ;; then nullification is not allowed.
179 (define_delay (eq_attr "type" "cbranch")
180 [(eq_attr "in_branch_delay" "true")
181 (and (eq_attr "in_nullified_branch_delay" "true")
182 (attr_flag "forward"))
183 (and (eq_attr "in_nullified_branch_delay" "true")
184 (attr_flag "backward"))])
186 (define_delay (and (eq_attr "type" "uncond_branch")
187 (not (match_test "pa_following_call (insn)")))
188 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
190 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
191 ;; load: 2, fpload: 3
192 ;; store, fpstore: 3, no D-cache operations should be scheduled.
194 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
196 ;; Instruction Time Unit Minimum Distance (unit contention)
203 ;; fmpyadd 3 ALU,MPY 2
204 ;; fmpysub 3 ALU,MPY 2
205 ;; fmpycfxt 3 ALU,MPY 2
208 ;; fdiv,sgl 10 MPY 10
209 ;; fdiv,dbl 12 MPY 12
210 ;; fsqrt,sgl 14 MPY 14
211 ;; fsqrt,dbl 18 MPY 18
213 ;; We don't model fmpyadd/fmpysub properly as those instructions
214 ;; keep both the FP ALU and MPY units busy. Given that these
215 ;; processors are obsolete, I'm not going to spend the time to
216 ;; model those instructions correctly.
218 (define_automaton "pa700")
219 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
221 (define_insn_reservation "W0" 4
222 (and (eq_attr "type" "fpcc")
223 (eq_attr "cpu" "700"))
226 (define_insn_reservation "W1" 3
227 (and (eq_attr "type" "fpalu")
228 (eq_attr "cpu" "700"))
231 (define_insn_reservation "W2" 3
232 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
233 (eq_attr "cpu" "700"))
236 (define_insn_reservation "W3" 10
237 (and (eq_attr "type" "fpdivsgl")
238 (eq_attr "cpu" "700"))
241 (define_insn_reservation "W4" 12
242 (and (eq_attr "type" "fpdivdbl")
243 (eq_attr "cpu" "700"))
246 (define_insn_reservation "W5" 14
247 (and (eq_attr "type" "fpsqrtsgl")
248 (eq_attr "cpu" "700"))
251 (define_insn_reservation "W6" 18
252 (and (eq_attr "type" "fpsqrtdbl")
253 (eq_attr "cpu" "700"))
256 (define_insn_reservation "W7" 2
257 (and (eq_attr "type" "load")
258 (eq_attr "cpu" "700"))
261 (define_insn_reservation "W8" 2
262 (and (eq_attr "type" "fpload")
263 (eq_attr "cpu" "700"))
266 (define_insn_reservation "W9" 3
267 (and (eq_attr "type" "store")
268 (eq_attr "cpu" "700"))
271 (define_insn_reservation "W10" 3
272 (and (eq_attr "type" "fpstore")
273 (eq_attr "cpu" "700"))
276 (define_insn_reservation "W11" 5
277 (and (eq_attr "type" "fpstore_load")
278 (eq_attr "cpu" "700"))
281 (define_insn_reservation "W12" 6
282 (and (eq_attr "type" "store_fpload")
283 (eq_attr "cpu" "700"))
286 (define_insn_reservation "W13" 1
287 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
288 (eq_attr "cpu" "700"))
291 ;; We have a bypass for all computations in the FP unit which feed an
292 ;; FP store as long as the sizes are the same.
293 (define_bypass 2 "W1,W2" "W10,W11" "pa_fpstore_bypass_p")
294 (define_bypass 9 "W3" "W10,W11" "pa_fpstore_bypass_p")
295 (define_bypass 11 "W4" "W10,W11" "pa_fpstore_bypass_p")
296 (define_bypass 13 "W5" "W10,W11" "pa_fpstore_bypass_p")
297 (define_bypass 17 "W6" "W10,W11" "pa_fpstore_bypass_p")
299 ;; We have an "anti-bypass" for FP loads which feed an FP store.
300 (define_bypass 4 "W8,W12" "W10,W11" "pa_fpstore_bypass_p")
302 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
303 ;; floating point computations with non-floating point computations (fp loads
304 ;; and stores are not fp computations).
306 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
307 ;; take two cycles, during which no Dcache operations should be scheduled.
308 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
309 ;; all have the same memory characteristics if one disregards cache misses.
311 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
312 ;; There's no value in modeling the ALU and MUL separately though
313 ;; since there can never be a functional unit conflict given the
314 ;; latency and issue rates for those units.
317 ;; Instruction Time Unit Minimum Distance (unit contention)
324 ;; fmpyadd 2 ALU,MPY 1
325 ;; fmpysub 2 ALU,MPY 1
326 ;; fmpycfxt 2 ALU,MPY 1
330 ;; fdiv,dbl 15 DIV 15
332 ;; fsqrt,dbl 15 DIV 15
334 (define_automaton "pa7100")
335 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
337 (define_insn_reservation "X0" 2
338 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
339 (eq_attr "cpu" "7100"))
342 (define_insn_reservation "X1" 8
343 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
344 (eq_attr "cpu" "7100"))
345 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
347 (define_insn_reservation "X2" 15
348 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
349 (eq_attr "cpu" "7100"))
350 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
352 (define_insn_reservation "X3" 2
353 (and (eq_attr "type" "load")
354 (eq_attr "cpu" "7100"))
357 (define_insn_reservation "X4" 2
358 (and (eq_attr "type" "fpload")
359 (eq_attr "cpu" "7100"))
362 (define_insn_reservation "X5" 2
363 (and (eq_attr "type" "store")
364 (eq_attr "cpu" "7100"))
365 "i_7100+mem_7100,mem_7100")
367 (define_insn_reservation "X6" 2
368 (and (eq_attr "type" "fpstore")
369 (eq_attr "cpu" "7100"))
370 "i_7100+mem_7100,mem_7100")
372 (define_insn_reservation "X7" 4
373 (and (eq_attr "type" "fpstore_load")
374 (eq_attr "cpu" "7100"))
375 "i_7100+mem_7100,mem_7100*3")
377 (define_insn_reservation "X8" 4
378 (and (eq_attr "type" "store_fpload")
379 (eq_attr "cpu" "7100"))
380 "i_7100+mem_7100,mem_7100*3")
382 (define_insn_reservation "X9" 1
383 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
384 (eq_attr "cpu" "7100"))
387 ;; We have a bypass for all computations in the FP unit which feed an
388 ;; FP store as long as the sizes are the same.
389 (define_bypass 1 "X0" "X6,X7" "pa_fpstore_bypass_p")
390 (define_bypass 7 "X1" "X6,X7" "pa_fpstore_bypass_p")
391 (define_bypass 14 "X2" "X6,X7" "pa_fpstore_bypass_p")
393 ;; We have an "anti-bypass" for FP loads which feed an FP store.
394 (define_bypass 3 "X4,X8" "X6,X7" "pa_fpstore_bypass_p")
396 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
397 ;; There's no value in modeling the ALU and MUL separately though
398 ;; since there can never be a functional unit conflict that
399 ;; can be avoided given the latency, issue rates and mandatory
400 ;; one cycle cpu-wide lock for a double precision fp multiply.
403 ;; Instruction Time Unit Minimum Distance (unit contention)
410 ;; fmpyadd,sgl 2 ALU,MPY 1
411 ;; fmpyadd,dbl 3 ALU,MPY 2
412 ;; fmpysub,sgl 2 ALU,MPY 1
413 ;; fmpysub,dbl 3 ALU,MPY 2
414 ;; fmpycfxt,sgl 2 ALU,MPY 1
415 ;; fmpycfxt,dbl 3 ALU,MPY 2
420 ;; fdiv,dbl 15 DIV 15
422 ;; fsqrt,dbl 15 DIV 15
424 ;; The PA7200 is just like the PA7100LC except that there is
425 ;; no store-store penalty.
427 ;; The PA7300 is just like the PA7200 except that there is
428 ;; no store-load penalty.
430 ;; Note there are some aspects of the 7100LC we are not modeling
431 ;; at the moment. I'll be reviewing the 7100LC scheduling info
432 ;; shortly and updating this description.
436 ;; other issue modeling
438 (define_automaton "pa7100lc")
439 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
440 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
441 (define_cpu_unit "mem_7100lc" "pa7100lc")
443 ;; Double precision multiplies lock the entire CPU for one
444 ;; cycle. There is no way to avoid this lock and trying to
445 ;; schedule around the lock is pointless and thus there is no
446 ;; value in trying to model this lock.
448 ;; Not modeling the lock allows us to treat fp multiplies just
449 ;; like any other FP alu instruction. It allows for a smaller
450 ;; DFA and may reduce register pressure.
451 (define_insn_reservation "Y0" 2
452 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
453 (eq_attr "cpu" "7100LC,7200,7300"))
454 "f_7100lc,fpmac_7100lc")
456 ;; fp division and sqrt instructions lock the entire CPU for
457 ;; 7 cycles (single precision) or 14 cycles (double precision).
458 ;; There is no way to avoid this lock and trying to schedule
459 ;; around the lock is pointless and thus there is no value in
460 ;; trying to model this lock. Not modeling the lock allows
461 ;; for a smaller DFA and may reduce register pressure.
462 (define_insn_reservation "Y1" 1
463 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
464 (eq_attr "cpu" "7100LC,7200,7300"))
467 (define_insn_reservation "Y2" 2
468 (and (eq_attr "type" "load")
469 (eq_attr "cpu" "7100LC,7200,7300"))
470 "i1_7100lc+mem_7100lc")
472 (define_insn_reservation "Y3" 2
473 (and (eq_attr "type" "fpload")
474 (eq_attr "cpu" "7100LC,7200,7300"))
475 "i1_7100lc+mem_7100lc")
477 (define_insn_reservation "Y4" 2
478 (and (eq_attr "type" "store")
479 (eq_attr "cpu" "7100LC"))
480 "i1_7100lc+mem_7100lc,mem_7100lc")
482 (define_insn_reservation "Y5" 2
483 (and (eq_attr "type" "fpstore")
484 (eq_attr "cpu" "7100LC"))
485 "i1_7100lc+mem_7100lc,mem_7100lc")
487 (define_insn_reservation "Y6" 4
488 (and (eq_attr "type" "fpstore_load")
489 (eq_attr "cpu" "7100LC"))
490 "i1_7100lc+mem_7100lc,mem_7100lc*3")
492 (define_insn_reservation "Y7" 4
493 (and (eq_attr "type" "store_fpload")
494 (eq_attr "cpu" "7100LC"))
495 "i1_7100lc+mem_7100lc,mem_7100lc*3")
497 (define_insn_reservation "Y8" 1
498 (and (eq_attr "type" "shift,nullshift")
499 (eq_attr "cpu" "7100LC,7200,7300"))
502 (define_insn_reservation "Y9" 1
503 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
504 (eq_attr "cpu" "7100LC,7200,7300"))
505 "(i0_7100lc|i1_7100lc)")
507 ;; The 7200 has a store-load penalty
508 (define_insn_reservation "Y10" 2
509 (and (eq_attr "type" "store")
510 (eq_attr "cpu" "7200"))
511 "i1_7100lc,mem_7100lc")
513 (define_insn_reservation "Y11" 2
514 (and (eq_attr "type" "fpstore")
515 (eq_attr "cpu" "7200"))
516 "i1_7100lc,mem_7100lc")
518 (define_insn_reservation "Y12" 4
519 (and (eq_attr "type" "fpstore_load")
520 (eq_attr "cpu" "7200"))
521 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
523 (define_insn_reservation "Y13" 4
524 (and (eq_attr "type" "store_fpload")
525 (eq_attr "cpu" "7200"))
526 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
528 ;; The 7300 has no penalty for store-store or store-load
529 (define_insn_reservation "Y14" 2
530 (and (eq_attr "type" "store")
531 (eq_attr "cpu" "7300"))
534 (define_insn_reservation "Y15" 2
535 (and (eq_attr "type" "fpstore")
536 (eq_attr "cpu" "7300"))
539 (define_insn_reservation "Y16" 4
540 (and (eq_attr "type" "fpstore_load")
541 (eq_attr "cpu" "7300"))
542 "i1_7100lc,i1_7100lc+mem_7100lc")
544 (define_insn_reservation "Y17" 4
545 (and (eq_attr "type" "store_fpload")
546 (eq_attr "cpu" "7300"))
547 "i1_7100lc,i1_7100lc+mem_7100lc")
549 ;; We have an "anti-bypass" for FP loads which feed an FP store.
550 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "pa_fpstore_bypass_p")
552 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
553 ;; traditional architecture.
555 ;; The PA8000 has a large (56) entry reorder buffer that is split between
556 ;; memory and non-memory operations.
558 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
559 ;; the function units, with the exception of branches and multi-output
560 ;; instructions. The PA8000 can retire two non-memory operations per cycle
561 ;; and two memory operations per cycle, only one of which may be a store.
563 ;; Given the large reorder buffer, the processor can hide most latencies.
564 ;; According to HP, they've got the best results by scheduling for retirement
565 ;; bandwidth with limited latency scheduling for floating point operations.
566 ;; Latency for integer operations and memory references is ignored.
569 ;; We claim floating point operations have a 2 cycle latency and are
570 ;; fully pipelined, except for div and sqrt which are not pipelined and
571 ;; take from 17 to 31 cycles to complete.
573 ;; It's worth noting that there is no way to saturate all the functional
574 ;; units on the PA8000 as there is not enough issue bandwidth.
576 (define_automaton "pa8000")
577 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
578 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
579 (define_cpu_unit "store_8000" "pa8000")
580 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
581 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
582 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
583 (define_reservation "im_8000" "im0_8000 | im1_8000")
584 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
585 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
586 (define_reservation "f_8000" "f0_8000 | f1_8000")
587 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
589 ;; We can issue any two memops per cycle, but we can only retire
590 ;; one memory store per cycle. We assume that the reorder buffer
591 ;; will hide any memory latencies per HP's recommendation.
592 (define_insn_reservation "Z0" 0
594 (eq_attr "type" "load,fpload")
595 (eq_attr "cpu" "8000"))
598 (define_insn_reservation "Z1" 0
600 (eq_attr "type" "store,fpstore")
601 (eq_attr "cpu" "8000"))
602 "im_8000,rm_8000+store_8000")
604 (define_insn_reservation "Z2" 0
605 (and (eq_attr "type" "fpstore_load,store_fpload")
606 (eq_attr "cpu" "8000"))
607 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
609 ;; We can issue and retire two non-memory operations per cycle with
610 ;; a few exceptions (branches). This group catches those we want
611 ;; to assume have zero latency.
612 (define_insn_reservation "Z3" 0
614 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
615 (eq_attr "cpu" "8000"))
618 ;; Branches use both slots in the non-memory issue and
620 (define_insn_reservation "Z4" 0
622 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
623 (eq_attr "cpu" "8000"))
624 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
626 ;; We partial latency schedule the floating point units.
627 ;; They can issue/retire two at a time in the non-memory
628 ;; units. We fix their latency at 2 cycles and they
629 ;; are fully pipelined.
630 (define_insn_reservation "Z5" 1
632 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
633 (eq_attr "cpu" "8000"))
634 "inm_8000,f_8000,rnm_8000")
636 ;; The fdivsqrt units are not pipelined and have a very long latency.
637 ;; To keep the DFA from exploding, we do not show all the
638 ;; reservations for the divsqrt unit.
639 (define_insn_reservation "Z6" 17
641 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
642 (eq_attr "cpu" "8000"))
643 "inm_8000,fdivsqrt_8000*6,rnm_8000")
645 (define_insn_reservation "Z7" 31
647 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
648 (eq_attr "cpu" "8000"))
649 "inm_8000,fdivsqrt_8000*6,rnm_8000")
651 ;; Operand and operator predicates and constraints
653 (include "predicates.md")
654 (include "constraints.md")
656 ;; Compare instructions.
657 ;; This controls RTL generation and register allocation.
661 (match_operator:CCFP 2 "comparison_operator"
662 [(match_operand:SF 0 "reg_or_0_operand" "fG")
663 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
664 "! TARGET_SOFT_FLOAT"
665 "fcmp,sgl,%Y2 %f0,%f1"
666 [(set_attr "length" "4")
667 (set_attr "type" "fpcc")])
671 (match_operator:CCFP 2 "comparison_operator"
672 [(match_operand:DF 0 "reg_or_0_operand" "fG")
673 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
674 "! TARGET_SOFT_FLOAT"
675 "fcmp,dbl,%Y2 %f0,%f1"
676 [(set_attr "length" "4")
677 (set_attr "type" "fpcc")])
679 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
680 ;; placeholders. This is necessary in rare situations when a
681 ;; placeholder is re-emitted (see PR 8705).
683 (define_expand "movccfp"
685 (match_operand 0 "const_int_operand" ""))]
686 "! TARGET_SOFT_FLOAT"
689 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
693 ;; The following patterns are optimization placeholders. In almost
694 ;; all cases, the user of the condition code will be simplified and the
695 ;; original condition code setting insn should be eliminated.
697 (define_insn "*movccfp0"
700 "! TARGET_SOFT_FLOAT"
701 "fcmp,dbl,= %%fr0,%%fr0"
702 [(set_attr "length" "4")
703 (set_attr "type" "fpcc")])
705 (define_insn "*movccfp1"
708 "! TARGET_SOFT_FLOAT"
709 "fcmp,dbl,!= %%fr0,%%fr0"
710 [(set_attr "length" "4")
711 (set_attr "type" "fpcc")])
715 (define_expand "cstoresi4"
716 [(set (match_operand:SI 0 "register_operand")
717 (match_operator:SI 1 "ordered_comparison_operator"
718 [(match_operand:SI 2 "reg_or_0_operand" "")
719 (match_operand:SI 3 "arith5_operand" "")]))]
723 ;; Instruction canonicalization puts immediate operands second, which
724 ;; is the reverse of what we want.
727 [(set (match_operand:SI 0 "register_operand" "=r")
728 (match_operator:SI 3 "comparison_operator"
729 [(match_operand:SI 1 "register_operand" "r")
730 (match_operand:SI 2 "arith11_operand" "rI")]))]
732 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
733 [(set_attr "type" "binary")
734 (set_attr "length" "8")])
737 [(set (match_operand:DI 0 "register_operand" "=r")
738 (match_operator:DI 3 "comparison_operator"
739 [(match_operand:DI 1 "register_operand" "r")
740 (match_operand:DI 2 "arith11_operand" "rI")]))]
742 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
743 [(set_attr "type" "binary")
744 (set_attr "length" "8")])
746 (define_insn "iorscc"
747 [(set (match_operand:SI 0 "register_operand" "=r")
748 (ior:SI (match_operator:SI 3 "comparison_operator"
749 [(match_operand:SI 1 "register_operand" "r")
750 (match_operand:SI 2 "arith11_operand" "rI")])
751 (match_operator:SI 6 "comparison_operator"
752 [(match_operand:SI 4 "register_operand" "r")
753 (match_operand:SI 5 "arith11_operand" "rI")])))]
755 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
756 [(set_attr "type" "binary")
757 (set_attr "length" "12")])
760 [(set (match_operand:DI 0 "register_operand" "=r")
761 (ior:DI (match_operator:DI 3 "comparison_operator"
762 [(match_operand:DI 1 "register_operand" "r")
763 (match_operand:DI 2 "arith11_operand" "rI")])
764 (match_operator:DI 6 "comparison_operator"
765 [(match_operand:DI 4 "register_operand" "r")
766 (match_operand:DI 5 "arith11_operand" "rI")])))]
768 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
769 [(set_attr "type" "binary")
770 (set_attr "length" "12")])
772 ;; Combiner patterns for common operations performed with the output
773 ;; from an scc insn (negscc and incscc).
774 (define_insn "negscc"
775 [(set (match_operand:SI 0 "register_operand" "=r")
776 (neg:SI (match_operator:SI 3 "comparison_operator"
777 [(match_operand:SI 1 "register_operand" "r")
778 (match_operand:SI 2 "arith11_operand" "rI")])))]
780 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
781 [(set_attr "type" "binary")
782 (set_attr "length" "8")])
785 [(set (match_operand:DI 0 "register_operand" "=r")
786 (neg:DI (match_operator:DI 3 "comparison_operator"
787 [(match_operand:DI 1 "register_operand" "r")
788 (match_operand:DI 2 "arith11_operand" "rI")])))]
790 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
791 [(set_attr "type" "binary")
792 (set_attr "length" "8")])
794 ;; Patterns for adding/subtracting the result of a boolean expression from
795 ;; a register. First we have special patterns that make use of the carry
796 ;; bit, and output only two instructions. For the cases we can't in
797 ;; general do in two instructions, the incscc pattern at the end outputs
798 ;; two or three instructions.
801 [(set (match_operand:SI 0 "register_operand" "=r")
802 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
803 (match_operand:SI 3 "arith11_operand" "rI"))
804 (match_operand:SI 1 "register_operand" "r")))]
806 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
807 [(set_attr "type" "binary")
808 (set_attr "length" "8")])
811 [(set (match_operand:DI 0 "register_operand" "=r")
812 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
813 (match_operand:DI 3 "arith11_operand" "rI"))
814 (match_operand:DI 1 "register_operand" "r")))]
816 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
817 [(set_attr "type" "binary")
818 (set_attr "length" "8")])
820 ; This need only accept registers for op3, since canonicalization
821 ; replaces geu with gtu when op3 is an integer.
823 [(set (match_operand:SI 0 "register_operand" "=r")
824 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
825 (match_operand:SI 3 "register_operand" "r"))
826 (match_operand:SI 1 "register_operand" "r")))]
828 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
829 [(set_attr "type" "binary")
830 (set_attr "length" "8")])
833 [(set (match_operand:DI 0 "register_operand" "=r")
834 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
835 (match_operand:DI 3 "register_operand" "r"))
836 (match_operand:DI 1 "register_operand" "r")))]
838 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
839 [(set_attr "type" "binary")
840 (set_attr "length" "8")])
842 ; Match only integers for op3 here. This is used as canonical form of the
843 ; geu pattern when op3 is an integer. Don't match registers since we can't
844 ; make better code than the general incscc pattern.
846 [(set (match_operand:SI 0 "register_operand" "=r")
847 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
848 (match_operand:SI 3 "int11_operand" "I"))
849 (match_operand:SI 1 "register_operand" "r")))]
851 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
852 [(set_attr "type" "binary")
853 (set_attr "length" "8")])
856 [(set (match_operand:DI 0 "register_operand" "=r")
857 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
858 (match_operand:DI 3 "int11_operand" "I"))
859 (match_operand:DI 1 "register_operand" "r")))]
861 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
862 [(set_attr "type" "binary")
863 (set_attr "length" "8")])
865 (define_insn "incscc"
866 [(set (match_operand:SI 0 "register_operand" "=r,r")
867 (plus:SI (match_operator:SI 4 "comparison_operator"
868 [(match_operand:SI 2 "register_operand" "r,r")
869 (match_operand:SI 3 "arith11_operand" "rI,rI")])
870 (match_operand:SI 1 "register_operand" "0,?r")))]
873 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
874 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
875 [(set_attr "type" "binary,binary")
876 (set_attr "length" "8,12")])
879 [(set (match_operand:DI 0 "register_operand" "=r,r")
880 (plus:DI (match_operator:DI 4 "comparison_operator"
881 [(match_operand:DI 2 "register_operand" "r,r")
882 (match_operand:DI 3 "arith11_operand" "rI,rI")])
883 (match_operand:DI 1 "register_operand" "0,?r")))]
886 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
887 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
888 [(set_attr "type" "binary,binary")
889 (set_attr "length" "8,12")])
892 [(set (match_operand:SI 0 "register_operand" "=r")
893 (minus:SI (match_operand:SI 1 "register_operand" "r")
894 (gtu:SI (match_operand:SI 2 "register_operand" "r")
895 (match_operand:SI 3 "arith11_operand" "rI"))))]
897 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
898 [(set_attr "type" "binary")
899 (set_attr "length" "8")])
902 [(set (match_operand:DI 0 "register_operand" "=r")
903 (minus:DI (match_operand:DI 1 "register_operand" "r")
904 (gtu:DI (match_operand:DI 2 "register_operand" "r")
905 (match_operand:DI 3 "arith11_operand" "rI"))))]
907 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
912 [(set (match_operand:SI 0 "register_operand" "=r")
913 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
914 (gtu:SI (match_operand:SI 2 "register_operand" "r")
915 (match_operand:SI 3 "arith11_operand" "rI")))
916 (match_operand:SI 4 "register_operand" "r")))]
918 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
919 [(set_attr "type" "binary")
920 (set_attr "length" "8")])
923 [(set (match_operand:DI 0 "register_operand" "=r")
924 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
925 (gtu:DI (match_operand:DI 2 "register_operand" "r")
926 (match_operand:DI 3 "arith11_operand" "rI")))
927 (match_operand:DI 4 "register_operand" "r")))]
929 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
930 [(set_attr "type" "binary")
931 (set_attr "length" "8")])
933 ; This need only accept registers for op3, since canonicalization
934 ; replaces ltu with leu when op3 is an integer.
936 [(set (match_operand:SI 0 "register_operand" "=r")
937 (minus:SI (match_operand:SI 1 "register_operand" "r")
938 (ltu:SI (match_operand:SI 2 "register_operand" "r")
939 (match_operand:SI 3 "register_operand" "r"))))]
941 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
942 [(set_attr "type" "binary")
943 (set_attr "length" "8")])
946 [(set (match_operand:DI 0 "register_operand" "=r")
947 (minus:DI (match_operand:DI 1 "register_operand" "r")
948 (ltu:DI (match_operand:DI 2 "register_operand" "r")
949 (match_operand:DI 3 "register_operand" "r"))))]
951 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
952 [(set_attr "type" "binary")
953 (set_attr "length" "8")])
956 [(set (match_operand:SI 0 "register_operand" "=r")
957 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
958 (ltu:SI (match_operand:SI 2 "register_operand" "r")
959 (match_operand:SI 3 "register_operand" "r")))
960 (match_operand:SI 4 "register_operand" "r")))]
962 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
963 [(set_attr "type" "binary")
964 (set_attr "length" "8")])
967 [(set (match_operand:DI 0 "register_operand" "=r")
968 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
969 (ltu:DI (match_operand:DI 2 "register_operand" "r")
970 (match_operand:DI 3 "register_operand" "r")))
971 (match_operand:DI 4 "register_operand" "r")))]
973 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
974 [(set_attr "type" "binary")
975 (set_attr "length" "8")])
977 ; Match only integers for op3 here. This is used as canonical form of the
978 ; ltu pattern when op3 is an integer. Don't match registers since we can't
979 ; make better code than the general incscc pattern.
981 [(set (match_operand:SI 0 "register_operand" "=r")
982 (minus:SI (match_operand:SI 1 "register_operand" "r")
983 (leu:SI (match_operand:SI 2 "register_operand" "r")
984 (match_operand:SI 3 "int11_operand" "I"))))]
986 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
987 [(set_attr "type" "binary")
988 (set_attr "length" "8")])
991 [(set (match_operand:DI 0 "register_operand" "=r")
992 (minus:DI (match_operand:DI 1 "register_operand" "r")
993 (leu:DI (match_operand:DI 2 "register_operand" "r")
994 (match_operand:DI 3 "int11_operand" "I"))))]
996 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
997 [(set_attr "type" "binary")
998 (set_attr "length" "8")])
1001 [(set (match_operand:SI 0 "register_operand" "=r")
1002 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1003 (leu:SI (match_operand:SI 2 "register_operand" "r")
1004 (match_operand:SI 3 "int11_operand" "I")))
1005 (match_operand:SI 4 "register_operand" "r")))]
1007 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1008 [(set_attr "type" "binary")
1009 (set_attr "length" "8")])
1012 [(set (match_operand:DI 0 "register_operand" "=r")
1013 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1014 (leu:DI (match_operand:DI 2 "register_operand" "r")
1015 (match_operand:DI 3 "int11_operand" "I")))
1016 (match_operand:DI 4 "register_operand" "r")))]
1018 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1019 [(set_attr "type" "binary")
1020 (set_attr "length" "8")])
1022 (define_insn "decscc"
1023 [(set (match_operand:SI 0 "register_operand" "=r,r")
1024 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1025 (match_operator:SI 4 "comparison_operator"
1026 [(match_operand:SI 2 "register_operand" "r,r")
1027 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1030 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1031 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1032 [(set_attr "type" "binary,binary")
1033 (set_attr "length" "8,12")])
1036 [(set (match_operand:DI 0 "register_operand" "=r,r")
1037 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1038 (match_operator:DI 4 "comparison_operator"
1039 [(match_operand:DI 2 "register_operand" "r,r")
1040 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1043 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1044 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1045 [(set_attr "type" "binary,binary")
1046 (set_attr "length" "8,12")])
1048 ; Patterns for max and min. (There is no need for an earlyclobber in the
1049 ; last alternative since the middle alternative will match if op0 == op1.)
1051 (define_insn "sminsi3"
1052 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1053 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1054 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1057 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1058 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1059 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1060 [(set_attr "type" "multi,multi,multi")
1061 (set_attr "length" "8,8,8")])
1063 (define_insn "smindi3"
1064 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1065 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1066 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1069 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1070 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1071 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1072 [(set_attr "type" "multi,multi,multi")
1073 (set_attr "length" "8,8,8")])
1075 (define_insn "uminsi3"
1076 [(set (match_operand:SI 0 "register_operand" "=r,r")
1077 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1078 (match_operand:SI 2 "arith11_operand" "r,I")))]
1081 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1082 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1083 [(set_attr "type" "multi,multi")
1084 (set_attr "length" "8,8")])
1086 (define_insn "umindi3"
1087 [(set (match_operand:DI 0 "register_operand" "=r,r")
1088 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1089 (match_operand:DI 2 "arith11_operand" "r,I")))]
1092 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1093 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1094 [(set_attr "type" "multi,multi")
1095 (set_attr "length" "8,8")])
1097 (define_insn "smaxsi3"
1098 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1099 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1100 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1103 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1104 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1105 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1106 [(set_attr "type" "multi,multi,multi")
1107 (set_attr "length" "8,8,8")])
1109 (define_insn "smaxdi3"
1110 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1111 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1112 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1115 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1116 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1117 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1118 [(set_attr "type" "multi,multi,multi")
1119 (set_attr "length" "8,8,8")])
1121 (define_insn "umaxsi3"
1122 [(set (match_operand:SI 0 "register_operand" "=r,r")
1123 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1124 (match_operand:SI 2 "arith11_operand" "r,I")))]
1127 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1128 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1129 [(set_attr "type" "multi,multi")
1130 (set_attr "length" "8,8")])
1132 (define_insn "umaxdi3"
1133 [(set (match_operand:DI 0 "register_operand" "=r,r")
1134 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1135 (match_operand:DI 2 "arith11_operand" "r,I")))]
1138 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1139 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1140 [(set_attr "type" "multi,multi")
1141 (set_attr "length" "8,8")])
1143 (define_insn "abssi2"
1144 [(set (match_operand:SI 0 "register_operand" "=r")
1145 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1147 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1148 [(set_attr "type" "multi")
1149 (set_attr "length" "8")])
1151 (define_insn "absdi2"
1152 [(set (match_operand:DI 0 "register_operand" "=r")
1153 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1155 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1156 [(set_attr "type" "multi")
1157 (set_attr "length" "8")])
1159 ;;; Experimental conditional move patterns
1161 (define_expand "movsicc"
1162 [(set (match_operand:SI 0 "register_operand" "")
1164 (match_operand 1 "comparison_operator" "")
1165 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1166 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1170 if (GET_MODE (XEXP (operands[1], 0)) != SImode
1171 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1175 ;; We used to accept any register for op1.
1177 ;; However, it loses sometimes because the compiler will end up using
1178 ;; different registers for op0 and op1 in some critical cases. local-alloc
1179 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1181 ;; If/when global register allocation supports tying we should allow any
1182 ;; register for op1 again.
1184 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1186 (match_operator 2 "comparison_operator"
1187 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1188 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1189 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1193 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1194 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1195 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1196 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1197 [(set_attr "type" "multi,multi,multi,nullshift")
1198 (set_attr "length" "8,8,8,8")])
1201 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1203 (match_operator 5 "comparison_operator"
1204 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1205 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1206 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1207 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1210 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1211 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1212 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1213 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1214 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1215 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1216 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1217 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1218 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1219 (set_attr "length" "8,8,8,8,8,8,8,8")])
1221 (define_expand "movdicc"
1222 [(set (match_operand:DI 0 "register_operand" "")
1224 (match_operand 1 "comparison_operator" "")
1225 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1226 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1230 if (GET_MODE (XEXP (operands[1], 0)) != DImode
1231 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1235 ; We need the first constraint alternative in order to avoid
1236 ; earlyclobbers on all other alternatives.
1238 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1240 (match_operator 2 "comparison_operator"
1241 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1242 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1243 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1247 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1248 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1249 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1250 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1251 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1252 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1253 (set_attr "length" "8,8,8,8,8")])
1256 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1258 (match_operator 5 "comparison_operator"
1259 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1260 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1261 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1262 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1265 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1266 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1267 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1268 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1269 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1270 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1271 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1272 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1273 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1274 (set_attr "length" "8,8,8,8,8,8,8,8")])
1276 ;; Conditional Branches
1278 (define_expand "cbranchdi4"
1280 (if_then_else (match_operator 0 "ordered_comparison_operator"
1281 [(match_operand:DI 1 "reg_or_0_operand" "")
1282 (match_operand:DI 2 "register_operand" "")])
1283 (label_ref (match_operand 3 "" ""))
1288 (define_expand "cbranchsi4"
1290 (if_then_else (match_operator 0 "ordered_comparison_operator"
1291 [(match_operand:SI 1 "reg_or_0_operand" "")
1292 (match_operand:SI 2 "arith5_operand" "")])
1293 (label_ref (match_operand 3 "" ""))
1298 (define_expand "cbranchsf4"
1300 (if_then_else (match_operator 0 "comparison_operator"
1301 [(match_operand:SF 1 "reg_or_0_operand" "")
1302 (match_operand:SF 2 "reg_or_0_operand" "")])
1303 (label_ref (match_operand 3 "" ""))
1308 pa_emit_bcond_fp (operands);
1313 (define_expand "cbranchdf4"
1315 (if_then_else (match_operator 0 "comparison_operator"
1316 [(match_operand:DF 1 "reg_or_0_operand" "")
1317 (match_operand:DF 2 "reg_or_0_operand" "")])
1318 (label_ref (match_operand 3 "" ""))
1323 pa_emit_bcond_fp (operands);
1327 ;; Match the branch patterns.
1330 ;; Note a long backward conditional branch with an annulled delay slot
1331 ;; has a length of 12.
1335 (match_operator 3 "comparison_operator"
1336 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1337 (match_operand:SI 2 "arith5_operand" "rL")])
1338 (label_ref (match_operand 0 "" ""))
1343 return pa_output_cbranch (operands, 0, insn);
1345 [(set_attr "type" "cbranch")
1346 (set (attr "length")
1347 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1348 (const_int MAX_12BIT_OFFSET))
1350 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1351 (const_int MAX_17BIT_OFFSET))
1353 (match_test "TARGET_PORTABLE_RUNTIME")
1355 (not (match_test "flag_pic"))
1359 ;; Match the negated branch.
1364 (match_operator 3 "comparison_operator"
1365 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1366 (match_operand:SI 2 "arith5_operand" "rL")])
1368 (label_ref (match_operand 0 "" ""))))]
1372 return pa_output_cbranch (operands, 1, insn);
1374 [(set_attr "type" "cbranch")
1375 (set (attr "length")
1376 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1377 (const_int MAX_12BIT_OFFSET))
1379 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1380 (const_int MAX_17BIT_OFFSET))
1382 (match_test "TARGET_PORTABLE_RUNTIME")
1384 (not (match_test "flag_pic"))
1391 (match_operator 3 "comparison_operator"
1392 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1393 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1394 (label_ref (match_operand 0 "" ""))
1399 return pa_output_cbranch (operands, 0, insn);
1401 [(set_attr "type" "cbranch")
1402 (set (attr "length")
1403 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1404 (const_int MAX_12BIT_OFFSET))
1406 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1407 (const_int MAX_17BIT_OFFSET))
1409 (match_test "TARGET_PORTABLE_RUNTIME")
1411 (not (match_test "flag_pic"))
1415 ;; Match the negated branch.
1420 (match_operator 3 "comparison_operator"
1421 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1422 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1424 (label_ref (match_operand 0 "" ""))))]
1428 return pa_output_cbranch (operands, 1, insn);
1430 [(set_attr "type" "cbranch")
1431 (set (attr "length")
1432 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1433 (const_int MAX_12BIT_OFFSET))
1435 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1436 (const_int MAX_17BIT_OFFSET))
1438 (match_test "TARGET_PORTABLE_RUNTIME")
1440 (not (match_test "flag_pic"))
1446 (match_operator 3 "cmpib_comparison_operator"
1447 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1448 (match_operand:DI 2 "arith5_operand" "rL")])
1449 (label_ref (match_operand 0 "" ""))
1454 return pa_output_cbranch (operands, 0, insn);
1456 [(set_attr "type" "cbranch")
1457 (set (attr "length")
1458 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1459 (const_int MAX_12BIT_OFFSET))
1461 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1462 (const_int MAX_17BIT_OFFSET))
1464 (match_test "TARGET_PORTABLE_RUNTIME")
1466 (not (match_test "flag_pic"))
1470 ;; Match the negated branch.
1475 (match_operator 3 "cmpib_comparison_operator"
1476 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1477 (match_operand:DI 2 "arith5_operand" "rL")])
1479 (label_ref (match_operand 0 "" ""))))]
1483 return pa_output_cbranch (operands, 1, insn);
1485 [(set_attr "type" "cbranch")
1486 (set (attr "length")
1487 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1488 (const_int MAX_12BIT_OFFSET))
1490 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1491 (const_int MAX_17BIT_OFFSET))
1493 (match_test "TARGET_PORTABLE_RUNTIME")
1495 (not (match_test "flag_pic"))
1499 ;; Branch on Bit patterns.
1503 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1505 (match_operand:SI 1 "uint5_operand" ""))
1507 (label_ref (match_operand 2 "" ""))
1512 return pa_output_bb (operands, 0, insn, 0);
1514 [(set_attr "type" "cbranch")
1515 (set (attr "length")
1516 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1517 (const_int MAX_12BIT_OFFSET))
1519 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1520 (const_int MAX_17BIT_OFFSET))
1522 (match_test "TARGET_PORTABLE_RUNTIME")
1524 (not (match_test "flag_pic"))
1531 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1533 (match_operand:DI 1 "uint32_operand" ""))
1535 (label_ref (match_operand 2 "" ""))
1540 return pa_output_bb (operands, 0, insn, 0);
1542 [(set_attr "type" "cbranch")
1543 (set (attr "length")
1544 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1545 (const_int MAX_12BIT_OFFSET))
1547 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1548 (const_int MAX_17BIT_OFFSET))
1550 (match_test "TARGET_PORTABLE_RUNTIME")
1552 (not (match_test "flag_pic"))
1559 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1561 (match_operand:SI 1 "uint5_operand" ""))
1564 (label_ref (match_operand 2 "" ""))))]
1568 return pa_output_bb (operands, 1, insn, 0);
1570 [(set_attr "type" "cbranch")
1571 (set (attr "length")
1572 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1573 (const_int MAX_12BIT_OFFSET))
1575 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1576 (const_int MAX_17BIT_OFFSET))
1578 (match_test "TARGET_PORTABLE_RUNTIME")
1580 (not (match_test "flag_pic"))
1587 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1589 (match_operand:DI 1 "uint32_operand" ""))
1592 (label_ref (match_operand 2 "" ""))))]
1596 return pa_output_bb (operands, 1, insn, 0);
1598 [(set_attr "type" "cbranch")
1599 (set (attr "length")
1600 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1601 (const_int MAX_12BIT_OFFSET))
1603 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1604 (const_int MAX_17BIT_OFFSET))
1606 (match_test "TARGET_PORTABLE_RUNTIME")
1608 (not (match_test "flag_pic"))
1615 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1617 (match_operand:SI 1 "uint5_operand" ""))
1619 (label_ref (match_operand 2 "" ""))
1624 return pa_output_bb (operands, 0, insn, 1);
1626 [(set_attr "type" "cbranch")
1627 (set (attr "length")
1628 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1629 (const_int MAX_12BIT_OFFSET))
1631 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1632 (const_int MAX_17BIT_OFFSET))
1634 (match_test "TARGET_PORTABLE_RUNTIME")
1636 (not (match_test "flag_pic"))
1643 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1645 (match_operand:DI 1 "uint32_operand" ""))
1647 (label_ref (match_operand 2 "" ""))
1652 return pa_output_bb (operands, 0, insn, 1);
1654 [(set_attr "type" "cbranch")
1655 (set (attr "length")
1656 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1657 (const_int MAX_12BIT_OFFSET))
1659 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1660 (const_int MAX_17BIT_OFFSET))
1662 (match_test "TARGET_PORTABLE_RUNTIME")
1664 (not (match_test "flag_pic"))
1671 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1673 (match_operand:SI 1 "uint5_operand" ""))
1676 (label_ref (match_operand 2 "" ""))))]
1680 return pa_output_bb (operands, 1, insn, 1);
1682 [(set_attr "type" "cbranch")
1683 (set (attr "length")
1684 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1685 (const_int MAX_12BIT_OFFSET))
1687 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1688 (const_int MAX_17BIT_OFFSET))
1690 (match_test "TARGET_PORTABLE_RUNTIME")
1692 (not (match_test "flag_pic"))
1699 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1701 (match_operand:DI 1 "uint32_operand" ""))
1704 (label_ref (match_operand 2 "" ""))))]
1708 return pa_output_bb (operands, 1, insn, 1);
1710 [(set_attr "type" "cbranch")
1711 (set (attr "length")
1712 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1713 (const_int MAX_12BIT_OFFSET))
1715 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1716 (const_int MAX_17BIT_OFFSET))
1718 (match_test "TARGET_PORTABLE_RUNTIME")
1720 (not (match_test "flag_pic"))
1724 ;; Branch on Variable Bit patterns.
1728 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1730 (match_operand:SI 1 "register_operand" "q"))
1732 (label_ref (match_operand 2 "" ""))
1737 return pa_output_bvb (operands, 0, insn, 0);
1739 [(set_attr "type" "cbranch")
1740 (set (attr "length")
1741 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1742 (const_int MAX_12BIT_OFFSET))
1744 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1745 (const_int MAX_17BIT_OFFSET))
1747 (match_test "TARGET_PORTABLE_RUNTIME")
1749 (not (match_test "flag_pic"))
1756 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1758 (match_operand:DI 1 "register_operand" "q"))
1760 (label_ref (match_operand 2 "" ""))
1765 return pa_output_bvb (operands, 0, insn, 0);
1767 [(set_attr "type" "cbranch")
1768 (set (attr "length")
1769 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1770 (const_int MAX_12BIT_OFFSET))
1772 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1773 (const_int MAX_17BIT_OFFSET))
1775 (match_test "TARGET_PORTABLE_RUNTIME")
1777 (not (match_test "flag_pic"))
1784 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1786 (match_operand:SI 1 "register_operand" "q"))
1789 (label_ref (match_operand 2 "" ""))))]
1793 return pa_output_bvb (operands, 1, insn, 0);
1795 [(set_attr "type" "cbranch")
1796 (set (attr "length")
1797 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1798 (const_int MAX_12BIT_OFFSET))
1800 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1801 (const_int MAX_17BIT_OFFSET))
1803 (match_test "TARGET_PORTABLE_RUNTIME")
1805 (not (match_test "flag_pic"))
1812 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1814 (match_operand:DI 1 "register_operand" "q"))
1817 (label_ref (match_operand 2 "" ""))))]
1821 return pa_output_bvb (operands, 1, insn, 0);
1823 [(set_attr "type" "cbranch")
1824 (set (attr "length")
1825 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1826 (const_int MAX_12BIT_OFFSET))
1828 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1829 (const_int MAX_17BIT_OFFSET))
1831 (match_test "TARGET_PORTABLE_RUNTIME")
1833 (not (match_test "flag_pic"))
1840 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1842 (match_operand:SI 1 "register_operand" "q"))
1844 (label_ref (match_operand 2 "" ""))
1849 return pa_output_bvb (operands, 0, insn, 1);
1851 [(set_attr "type" "cbranch")
1852 (set (attr "length")
1853 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1854 (const_int MAX_12BIT_OFFSET))
1856 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1857 (const_int MAX_17BIT_OFFSET))
1859 (match_test "TARGET_PORTABLE_RUNTIME")
1861 (not (match_test "flag_pic"))
1868 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1870 (match_operand:DI 1 "register_operand" "q"))
1872 (label_ref (match_operand 2 "" ""))
1877 return pa_output_bvb (operands, 0, insn, 1);
1879 [(set_attr "type" "cbranch")
1880 (set (attr "length")
1881 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1882 (const_int MAX_12BIT_OFFSET))
1884 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1885 (const_int MAX_17BIT_OFFSET))
1887 (match_test "TARGET_PORTABLE_RUNTIME")
1889 (not (match_test "flag_pic"))
1896 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1898 (match_operand:SI 1 "register_operand" "q"))
1901 (label_ref (match_operand 2 "" ""))))]
1905 return pa_output_bvb (operands, 1, insn, 1);
1907 [(set_attr "type" "cbranch")
1908 (set (attr "length")
1909 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1910 (const_int MAX_12BIT_OFFSET))
1912 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1913 (const_int MAX_17BIT_OFFSET))
1915 (match_test "TARGET_PORTABLE_RUNTIME")
1917 (not (match_test "flag_pic"))
1924 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1926 (match_operand:DI 1 "register_operand" "q"))
1929 (label_ref (match_operand 2 "" ""))))]
1933 return pa_output_bvb (operands, 1, insn, 1);
1935 [(set_attr "type" "cbranch")
1936 (set (attr "length")
1937 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1938 (const_int MAX_12BIT_OFFSET))
1940 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1941 (const_int MAX_17BIT_OFFSET))
1943 (match_test "TARGET_PORTABLE_RUNTIME")
1945 (not (match_test "flag_pic"))
1949 ;; Floating point branches
1951 ;; ??? Nullification is handled differently from other branches.
1952 ;; If nullification is specified, the delay slot is nullified on any
1953 ;; taken branch regardless of branch direction.
1955 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1956 (label_ref (match_operand 0 "" ""))
1958 "!TARGET_SOFT_FLOAT"
1961 int length = get_attr_length (insn);
1963 int nullify, xdelay;
1966 return \"ftest\;b%* %l0\";
1968 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
1972 xoperands[0] = GEN_INT (length - 8);
1978 xoperands[0] = GEN_INT (length - 4);
1982 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
1984 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
1985 return pa_output_lbranch (operands[0], insn, xdelay);
1987 [(set_attr "type" "fbranch")
1988 (set (attr "length")
1989 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1990 (const_int MAX_17BIT_OFFSET))
1992 (match_test "TARGET_PORTABLE_RUNTIME")
1994 (not (match_test "flag_pic"))
1999 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2001 (label_ref (match_operand 0 "" ""))))]
2002 "!TARGET_SOFT_FLOAT"
2005 int length = get_attr_length (insn);
2007 int nullify, xdelay;
2010 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2012 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2016 xoperands[0] = GEN_INT (length - 4);
2022 xoperands[0] = GEN_INT (length);
2026 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2028 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2029 return pa_output_lbranch (operands[0], insn, xdelay);
2031 [(set_attr "type" "fbranch")
2032 (set (attr "length")
2033 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2034 (const_int MAX_17BIT_OFFSET))
2036 (match_test "TARGET_PORTABLE_RUNTIME")
2038 (not (match_test "flag_pic"))
2042 ;; Move instructions
2044 (define_expand "movsi"
2045 [(set (match_operand:SI 0 "general_operand" "")
2046 (match_operand:SI 1 "general_operand" ""))]
2050 if (pa_emit_move_sequence (operands, SImode, 0))
2054 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2055 (define_expand "reload_insi_r1"
2056 [(set (match_operand:SI 0 "register_operand" "=Z")
2057 (match_operand:SI 1 "non_hard_reg_operand" ""))
2058 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2062 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2065 /* We don't want the clobber emitted, so handle this ourselves. */
2066 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2070 ;; Handle SImode input reloads requiring a general register as a
2071 ;; scratch register.
2072 (define_expand "reload_insi"
2073 [(set (match_operand:SI 0 "register_operand" "=Z")
2074 (match_operand:SI 1 "non_hard_reg_operand" ""))
2075 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2079 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2082 /* We don't want the clobber emitted, so handle this ourselves. */
2083 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2087 ;; Handle SImode output reloads requiring a general register as a
2088 ;; scratch register.
2089 (define_expand "reload_outsi"
2090 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2091 (match_operand:SI 1 "register_operand" "Z"))
2092 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2096 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2099 /* We don't want the clobber emitted, so handle this ourselves. */
2100 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2105 [(set (match_operand:SI 0 "move_dest_operand"
2106 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2107 (match_operand:SI 1 "move_src_operand"
2108 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2109 "(register_operand (operands[0], SImode)
2110 || reg_or_0_operand (operands[1], SImode))
2111 && !TARGET_SOFT_FLOAT
2118 {zdepi|depwi,z} %Z1,%0
2122 {mfctl|mfctl,w} %%sar,%0
2126 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2127 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2128 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2129 (set_attr "pa_combine_type" "addmove")
2130 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2133 [(set (match_operand:SI 0 "move_dest_operand"
2134 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2135 (match_operand:SI 1 "move_src_operand"
2136 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2137 "(register_operand (operands[0], SImode)
2138 || reg_or_0_operand (operands[1], SImode))
2139 && !TARGET_SOFT_FLOAT
2146 {zdepi|depwi,z} %Z1,%0
2150 {mfctl|mfctl,w} %%sar,%0
2154 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2155 (set_attr "pa_combine_type" "addmove")
2156 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2159 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2160 (match_operand:SI 1 "register_operand" "f"))]
2162 && !TARGET_DISABLE_INDEXING
2163 && reload_completed"
2165 [(set_attr "type" "fpstore")
2166 (set_attr "pa_combine_type" "addmove")
2167 (set_attr "length" "4")])
2169 ; Rewrite RTL using an indexed store. This will allow the insn that
2170 ; computes the address to be deleted if the register it sets is dead.
2172 [(set (match_operand:SI 0 "register_operand" "")
2173 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2175 (match_operand:SI 2 "register_operand" "")))
2176 (set (mem:SI (match_dup 0))
2177 (match_operand:SI 3 "register_operand" ""))]
2179 && !TARGET_DISABLE_INDEXING
2180 && REG_OK_FOR_BASE_P (operands[2])
2181 && FP_REGNO_P (REGNO (operands[3]))"
2182 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2184 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2189 [(set (match_operand:SI 0 "register_operand" "")
2190 (plus:SI (match_operand:SI 2 "register_operand" "")
2191 (mult:SI (match_operand:SI 1 "register_operand" "")
2193 (set (mem:SI (match_dup 0))
2194 (match_operand:SI 3 "register_operand" ""))]
2196 && !TARGET_DISABLE_INDEXING
2197 && REG_OK_FOR_BASE_P (operands[2])
2198 && FP_REGNO_P (REGNO (operands[3]))"
2199 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2201 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2206 [(set (match_operand:DI 0 "register_operand" "")
2207 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2209 (match_operand:DI 2 "register_operand" "")))
2210 (set (mem:SI (match_dup 0))
2211 (match_operand:SI 3 "register_operand" ""))]
2213 && !TARGET_DISABLE_INDEXING
2215 && REG_OK_FOR_BASE_P (operands[2])
2216 && FP_REGNO_P (REGNO (operands[3]))"
2217 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2219 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2224 [(set (match_operand:DI 0 "register_operand" "")
2225 (plus:DI (match_operand:DI 2 "register_operand" "")
2226 (mult:DI (match_operand:DI 1 "register_operand" "")
2228 (set (mem:SI (match_dup 0))
2229 (match_operand:SI 3 "register_operand" ""))]
2231 && !TARGET_DISABLE_INDEXING
2233 && REG_OK_FOR_BASE_P (operands[2])
2234 && FP_REGNO_P (REGNO (operands[3]))"
2235 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2237 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2242 [(set (match_operand:SI 0 "register_operand" "")
2243 (plus:SI (match_operand:SI 1 "register_operand" "")
2244 (match_operand:SI 2 "register_operand" "")))
2245 (set (mem:SI (match_dup 0))
2246 (match_operand:SI 3 "register_operand" ""))]
2248 && !TARGET_DISABLE_INDEXING
2249 && TARGET_NO_SPACE_REGS
2250 && REG_OK_FOR_INDEX_P (operands[1])
2251 && REG_OK_FOR_BASE_P (operands[2])
2252 && FP_REGNO_P (REGNO (operands[3]))"
2253 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2255 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2259 [(set (match_operand:SI 0 "register_operand" "")
2260 (plus:SI (match_operand:SI 1 "register_operand" "")
2261 (match_operand:SI 2 "register_operand" "")))
2262 (set (mem:SI (match_dup 0))
2263 (match_operand:SI 3 "register_operand" ""))]
2265 && !TARGET_DISABLE_INDEXING
2266 && TARGET_NO_SPACE_REGS
2267 && REG_OK_FOR_BASE_P (operands[1])
2268 && REG_OK_FOR_INDEX_P (operands[2])
2269 && FP_REGNO_P (REGNO (operands[3]))"
2270 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2272 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2276 [(set (match_operand:DI 0 "register_operand" "")
2277 (plus:DI (match_operand:DI 1 "register_operand" "")
2278 (match_operand:DI 2 "register_operand" "")))
2279 (set (mem:SI (match_dup 0))
2280 (match_operand:SI 3 "register_operand" ""))]
2282 && !TARGET_DISABLE_INDEXING
2284 && TARGET_NO_SPACE_REGS
2285 && REG_OK_FOR_INDEX_P (operands[1])
2286 && REG_OK_FOR_BASE_P (operands[2])
2287 && FP_REGNO_P (REGNO (operands[3]))"
2288 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2290 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2294 [(set (match_operand:DI 0 "register_operand" "")
2295 (plus:DI (match_operand:DI 1 "register_operand" "")
2296 (match_operand:DI 2 "register_operand" "")))
2297 (set (mem:SI (match_dup 0))
2298 (match_operand:SI 3 "register_operand" ""))]
2300 && !TARGET_DISABLE_INDEXING
2302 && TARGET_NO_SPACE_REGS
2303 && REG_OK_FOR_BASE_P (operands[1])
2304 && REG_OK_FOR_INDEX_P (operands[2])
2305 && FP_REGNO_P (REGNO (operands[3]))"
2306 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2308 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2312 [(set (match_operand:SI 0 "move_dest_operand"
2313 "=r,r,r,r,r,r,Q,!*q,!r")
2314 (match_operand:SI 1 "move_src_operand"
2315 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2316 "(register_operand (operands[0], SImode)
2317 || reg_or_0_operand (operands[1], SImode))
2318 && TARGET_SOFT_FLOAT"
2324 {zdepi|depwi,z} %Z1,%0
2328 {mfctl|mfctl,w} %%sar,%0"
2329 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2330 (set_attr "pa_combine_type" "addmove")
2331 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2333 ;; Load or store with base-register modification.
2335 [(set (match_operand:SI 0 "register_operand" "=r")
2336 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2337 (match_operand:DI 2 "int5_operand" "L"))))
2339 (plus:DI (match_dup 1) (match_dup 2)))]
2342 [(set_attr "type" "load")
2343 (set_attr "length" "4")])
2345 ; And a zero extended variant.
2347 [(set (match_operand:DI 0 "register_operand" "=r")
2348 (zero_extend:DI (mem:SI
2350 (match_operand:DI 1 "register_operand" "+r")
2351 (match_operand:DI 2 "int5_operand" "L")))))
2353 (plus:DI (match_dup 1) (match_dup 2)))]
2356 [(set_attr "type" "load")
2357 (set_attr "length" "4")])
2359 (define_expand "pre_load"
2360 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2361 (mem (plus (match_operand 1 "register_operand" "")
2362 (match_operand 2 "pre_cint_operand" ""))))
2364 (plus (match_dup 1) (match_dup 2)))])]
2370 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2373 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2377 (define_insn "pre_ldw"
2378 [(set (match_operand:SI 0 "register_operand" "=r")
2379 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2380 (match_operand:SI 2 "pre_cint_operand" ""))))
2382 (plus:SI (match_dup 1) (match_dup 2)))]
2386 if (INTVAL (operands[2]) < 0)
2387 return \"{ldwm|ldw,mb} %2(%1),%0\";
2388 return \"{ldws|ldw},mb %2(%1),%0\";
2390 [(set_attr "type" "load")
2391 (set_attr "length" "4")])
2393 (define_insn "pre_ldd"
2394 [(set (match_operand:DI 0 "register_operand" "=r")
2395 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2396 (match_operand:DI 2 "pre_cint_operand" ""))))
2398 (plus:DI (match_dup 1) (match_dup 2)))]
2401 [(set_attr "type" "load")
2402 (set_attr "length" "4")])
2405 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2406 (match_operand:SI 1 "pre_cint_operand" "")))
2407 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2409 (plus:SI (match_dup 0) (match_dup 1)))]
2413 if (INTVAL (operands[1]) < 0)
2414 return \"{stwm|stw,mb} %r2,%1(%0)\";
2415 return \"{stws|stw},mb %r2,%1(%0)\";
2417 [(set_attr "type" "store")
2418 (set_attr "length" "4")])
2421 [(set (match_operand:SI 0 "register_operand" "=r")
2422 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2424 (plus:SI (match_dup 1)
2425 (match_operand:SI 2 "post_cint_operand" "")))]
2429 if (INTVAL (operands[2]) > 0)
2430 return \"{ldwm|ldw,ma} %2(%1),%0\";
2431 return \"{ldws|ldw},ma %2(%1),%0\";
2433 [(set_attr "type" "load")
2434 (set_attr "length" "4")])
2436 (define_expand "post_store"
2437 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2438 (match_operand 1 "reg_or_0_operand" ""))
2441 (match_operand 2 "post_cint_operand" "")))])]
2447 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2450 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2454 (define_insn "post_stw"
2455 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2456 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2458 (plus:SI (match_dup 0)
2459 (match_operand:SI 2 "post_cint_operand" "")))]
2463 if (INTVAL (operands[2]) > 0)
2464 return \"{stwm|stw,ma} %r1,%2(%0)\";
2465 return \"{stws|stw},ma %r1,%2(%0)\";
2467 [(set_attr "type" "store")
2468 (set_attr "length" "4")])
2470 (define_insn "post_std"
2471 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2472 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2474 (plus:DI (match_dup 0)
2475 (match_operand:DI 2 "post_cint_operand" "")))]
2478 [(set_attr "type" "store")
2479 (set_attr "length" "4")])
2481 ;; For loading the address of a label while generating PIC code.
2482 ;; Note since this pattern can be created at reload time (via movsi), all
2483 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2485 [(set (match_operand 0 "pmode_register_operand" "=a")
2486 (match_operand 1 "pic_label_operand" ""))]
2492 xoperands[0] = operands[0];
2493 xoperands[1] = operands[1];
2494 xoperands[2] = gen_label_rtx ();
2496 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2497 CODE_LABEL_NUMBER (xoperands[2]));
2498 output_asm_insn (\"mfia %0\", xoperands);
2500 /* If we're trying to load the address of a label that happens to be
2501 close, then we can use a shorter sequence. */
2502 if (GET_CODE (operands[1]) == LABEL_REF
2503 && !LABEL_REF_NONLOCAL_P (operands[1])
2504 && INSN_ADDRESSES_SET_P ()
2505 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2506 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2507 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2510 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2511 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2515 [(set_attr "type" "multi")
2516 (set_attr "length" "12")]) ; 8 or 12
2519 [(set (match_operand 0 "pmode_register_operand" "=a")
2520 (match_operand 1 "pic_label_operand" ""))]
2526 xoperands[0] = operands[0];
2527 xoperands[1] = operands[1];
2528 xoperands[2] = gen_label_rtx ();
2530 output_asm_insn (\"bl .+8,%0\", xoperands);
2531 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2532 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2533 CODE_LABEL_NUMBER (xoperands[2]));
2535 /* If we're trying to load the address of a label that happens to be
2536 close, then we can use a shorter sequence. */
2537 if (GET_CODE (operands[1]) == LABEL_REF
2538 && !LABEL_REF_NONLOCAL_P (operands[1])
2539 && INSN_ADDRESSES_SET_P ()
2540 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2541 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2542 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2545 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2546 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2550 [(set_attr "type" "multi")
2551 (set_attr "length" "16")]) ; 12 or 16
2554 [(set (match_operand:SI 0 "register_operand" "=a")
2555 (plus:SI (match_operand:SI 1 "register_operand" "r")
2556 (high:SI (match_operand 2 "" ""))))]
2557 "symbolic_operand (operands[2], Pmode)
2558 && ! function_label_operand (operands[2], Pmode)
2561 [(set_attr "type" "binary")
2562 (set_attr "length" "4")])
2565 [(set (match_operand:DI 0 "register_operand" "=a")
2566 (plus:DI (match_operand:DI 1 "register_operand" "r")
2567 (high:DI (match_operand 2 "" ""))))]
2568 "symbolic_operand (operands[2], Pmode)
2569 && ! function_label_operand (operands[2], Pmode)
2573 [(set_attr "type" "binary")
2574 (set_attr "length" "4")])
2576 ;; Always use addil rather than ldil;add sequences. This allows the
2577 ;; HP linker to eliminate the dp relocation if the symbolic operand
2578 ;; lives in the TEXT space.
2580 [(set (match_operand:SI 0 "register_operand" "=a")
2581 (high:SI (match_operand 1 "" "")))]
2582 "symbolic_operand (operands[1], Pmode)
2583 && ! function_label_operand (operands[1], Pmode)
2584 && ! read_only_operand (operands[1], Pmode)
2588 if (TARGET_LONG_LOAD_STORE)
2589 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2591 return \"addil LR'%H1,%%r27\";
2593 [(set_attr "type" "binary")
2594 (set (attr "length")
2595 (if_then_else (not (match_test "TARGET_LONG_LOAD_STORE"))
2600 ;; This is for use in the prologue/epilogue code. We need it
2601 ;; to add large constants to a stack pointer or frame pointer.
2602 ;; Because of the additional %r1 pressure, we probably do not
2603 ;; want to use this in general code, so make it available
2604 ;; only after reload.
2606 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2607 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2608 (high:SI (match_operand 2 "const_int_operand" ""))))]
2612 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2613 [(set_attr "type" "binary,binary")
2614 (set_attr "length" "4,8")])
2617 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2618 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2619 (high:DI (match_operand 2 "const_int_operand" ""))))]
2620 "reload_completed && TARGET_64BIT"
2623 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2624 [(set_attr "type" "binary,binary")
2625 (set_attr "length" "4,8")])
2628 [(set (match_operand:SI 0 "register_operand" "=r")
2629 (high:SI (match_operand 1 "" "")))]
2630 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2631 && !pa_is_function_label_plus_const (operands[1])"
2634 if (symbolic_operand (operands[1], Pmode))
2635 return \"ldil LR'%H1,%0\";
2637 return \"ldil L'%G1,%0\";
2639 [(set_attr "type" "move")
2640 (set_attr "length" "4")])
2643 [(set (match_operand:DI 0 "register_operand" "=r")
2644 (high:DI (match_operand 1 "const_int_operand" "")))]
2647 [(set_attr "type" "move")
2648 (set_attr "length" "4")])
2651 [(set (match_operand:DI 0 "register_operand" "=r")
2652 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2653 (match_operand:DI 2 "const_int_operand" "i")))]
2656 [(set_attr "type" "move")
2657 (set_attr "length" "4")])
2660 [(set (match_operand:SI 0 "register_operand" "=r")
2661 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2662 (match_operand:SI 2 "immediate_operand" "i")))]
2663 "!pa_is_function_label_plus_const (operands[2])"
2666 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
2668 if (symbolic_operand (operands[2], Pmode))
2669 return \"ldo RR'%G2(%1),%0\";
2671 return \"ldo R'%G2(%1),%0\";
2673 [(set_attr "type" "move")
2674 (set_attr "length" "4")])
2676 ;; Now that a symbolic_address plus a constant is broken up early
2677 ;; in the compilation phase (for better CSE) we need a special
2678 ;; combiner pattern to load the symbolic address plus the constant
2679 ;; in only 2 instructions. (For cases where the symbolic address
2680 ;; was not a common subexpression.)
2682 [(set (match_operand:SI 0 "register_operand" "")
2683 (match_operand:SI 1 "symbolic_operand" ""))
2684 (clobber (match_operand:SI 2 "register_operand" ""))]
2685 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2686 [(set (match_dup 2) (high:SI (match_dup 1)))
2687 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2690 ;; hppa_legitimize_address goes to a great deal of trouble to
2691 ;; create addresses which use indexing. In some cases, this
2692 ;; is a lose because there isn't any store instructions which
2693 ;; allow indexed addresses (with integer register source).
2695 ;; These define_splits try to turn a 3 insn store into
2696 ;; a 2 insn store with some creative RTL rewriting.
2698 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2699 (match_operand:SI 1 "shadd_operand" ""))
2700 (plus:SI (match_operand:SI 2 "register_operand" "")
2701 (match_operand:SI 3 "const_int_operand" ""))))
2702 (match_operand:SI 4 "register_operand" ""))
2703 (clobber (match_operand:SI 5 "register_operand" ""))]
2705 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2707 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2711 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2712 (match_operand:SI 1 "shadd_operand" ""))
2713 (plus:SI (match_operand:SI 2 "register_operand" "")
2714 (match_operand:SI 3 "const_int_operand" ""))))
2715 (match_operand:HI 4 "register_operand" ""))
2716 (clobber (match_operand:SI 5 "register_operand" ""))]
2718 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2720 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2724 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2725 (match_operand:SI 1 "shadd_operand" ""))
2726 (plus:SI (match_operand:SI 2 "register_operand" "")
2727 (match_operand:SI 3 "const_int_operand" ""))))
2728 (match_operand:QI 4 "register_operand" ""))
2729 (clobber (match_operand:SI 5 "register_operand" ""))]
2731 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2733 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2736 (define_expand "movhi"
2737 [(set (match_operand:HI 0 "general_operand" "")
2738 (match_operand:HI 1 "general_operand" ""))]
2742 if (pa_emit_move_sequence (operands, HImode, 0))
2746 ;; Handle HImode input reloads requiring a general register as a
2747 ;; scratch register.
2748 (define_expand "reload_inhi"
2749 [(set (match_operand:HI 0 "register_operand" "=Z")
2750 (match_operand:HI 1 "non_hard_reg_operand" ""))
2751 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2755 if (pa_emit_move_sequence (operands, HImode, operands[2]))
2758 /* We don't want the clobber emitted, so handle this ourselves. */
2759 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2763 ;; Handle HImode output reloads requiring a general register as a
2764 ;; scratch register.
2765 (define_expand "reload_outhi"
2766 [(set (match_operand:HI 0 "non_hard_reg_operand" "")
2767 (match_operand:HI 1 "register_operand" "Z"))
2768 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2772 if (pa_emit_move_sequence (operands, HImode, operands[2]))
2775 /* We don't want the clobber emitted, so handle this ourselves. */
2776 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2781 [(set (match_operand:HI 0 "move_dest_operand"
2782 "=r,r,r,r,r,Q,!*q,!r")
2783 (match_operand:HI 1 "move_src_operand"
2784 "r,J,N,K,RQ,rM,!rM,!*q"))]
2785 "(register_operand (operands[0], HImode)
2786 || reg_or_0_operand (operands[1], HImode))"
2791 {zdepi|depwi,z} %Z1,%0
2795 {mfctl|mfctl,w} %sar,%0"
2796 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2797 (set_attr "pa_combine_type" "addmove")
2798 (set_attr "length" "4,4,4,4,4,4,4,4")])
2801 [(set (match_operand:HI 0 "register_operand" "=r")
2802 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2803 (match_operand:SI 2 "int5_operand" "L"))))
2805 (plus:SI (match_dup 1) (match_dup 2)))]
2807 "{ldhs|ldh},mb %2(%1),%0"
2808 [(set_attr "type" "load")
2809 (set_attr "length" "4")])
2812 [(set (match_operand:HI 0 "register_operand" "=r")
2813 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2814 (match_operand:DI 2 "int5_operand" "L"))))
2816 (plus:DI (match_dup 1) (match_dup 2)))]
2819 [(set_attr "type" "load")
2820 (set_attr "length" "4")])
2822 ; And a zero extended variant.
2824 [(set (match_operand:DI 0 "register_operand" "=r")
2825 (zero_extend:DI (mem:HI
2827 (match_operand:DI 1 "register_operand" "+r")
2828 (match_operand:DI 2 "int5_operand" "L")))))
2830 (plus:DI (match_dup 1) (match_dup 2)))]
2833 [(set_attr "type" "load")
2834 (set_attr "length" "4")])
2837 [(set (match_operand:SI 0 "register_operand" "=r")
2838 (zero_extend:SI (mem:HI
2840 (match_operand:SI 1 "register_operand" "+r")
2841 (match_operand:SI 2 "int5_operand" "L")))))
2843 (plus:SI (match_dup 1) (match_dup 2)))]
2845 "{ldhs|ldh},mb %2(%1),%0"
2846 [(set_attr "type" "load")
2847 (set_attr "length" "4")])
2850 [(set (match_operand:SI 0 "register_operand" "=r")
2851 (zero_extend:SI (mem:HI
2853 (match_operand:DI 1 "register_operand" "+r")
2854 (match_operand:DI 2 "int5_operand" "L")))))
2856 (plus:DI (match_dup 1) (match_dup 2)))]
2859 [(set_attr "type" "load")
2860 (set_attr "length" "4")])
2863 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2864 (match_operand:SI 1 "int5_operand" "L")))
2865 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2867 (plus:SI (match_dup 0) (match_dup 1)))]
2869 "{sths|sth},mb %r2,%1(%0)"
2870 [(set_attr "type" "store")
2871 (set_attr "length" "4")])
2874 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2875 (match_operand:DI 1 "int5_operand" "L")))
2876 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2878 (plus:DI (match_dup 0) (match_dup 1)))]
2881 [(set_attr "type" "store")
2882 (set_attr "length" "4")])
2884 (define_insn "addhi3"
2885 [(set (match_operand:HI 0 "register_operand" "=r,r")
2886 (plus:HI (match_operand:HI 1 "register_operand" "%r,r")
2887 (match_operand:HI 2 "arith14_operand" "r,J")))]
2890 {addl|add,l} %1,%2,%0
2892 [(set_attr "type" "binary,binary")
2893 (set_attr "pa_combine_type" "addmove")
2894 (set_attr "length" "4,4")])
2896 (define_expand "movqi"
2897 [(set (match_operand:QI 0 "general_operand" "")
2898 (match_operand:QI 1 "general_operand" ""))]
2902 if (pa_emit_move_sequence (operands, QImode, 0))
2906 ;; Handle QImode input reloads requiring a general register as a
2907 ;; scratch register.
2908 (define_expand "reload_inqi"
2909 [(set (match_operand:QI 0 "register_operand" "=Z")
2910 (match_operand:QI 1 "non_hard_reg_operand" ""))
2911 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
2915 if (pa_emit_move_sequence (operands, QImode, operands[2]))
2918 /* We don't want the clobber emitted, so handle this ourselves. */
2919 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2923 ;; Handle QImode output reloads requiring a general register as a
2924 ;; scratch register.
2925 (define_expand "reload_outqi"
2926 [(set (match_operand:QI 0 "non_hard_reg_operand" "")
2927 (match_operand:QI 1 "register_operand" "Z"))
2928 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
2932 if (pa_emit_move_sequence (operands, QImode, operands[2]))
2935 /* We don't want the clobber emitted, so handle this ourselves. */
2936 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2941 [(set (match_operand:QI 0 "move_dest_operand"
2942 "=r,r,r,r,r,Q,!*q,!r")
2943 (match_operand:QI 1 "move_src_operand"
2944 "r,J,N,K,RQ,rM,!rM,!*q"))]
2945 "(register_operand (operands[0], QImode)
2946 || reg_or_0_operand (operands[1], QImode))"
2951 {zdepi|depwi,z} %Z1,%0
2955 {mfctl|mfctl,w} %%sar,%0"
2956 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2957 (set_attr "pa_combine_type" "addmove")
2958 (set_attr "length" "4,4,4,4,4,4,4,4")])
2961 [(set (match_operand:QI 0 "register_operand" "=r")
2962 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2963 (match_operand:SI 2 "int5_operand" "L"))))
2964 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2966 "{ldbs|ldb},mb %2(%1),%0"
2967 [(set_attr "type" "load")
2968 (set_attr "length" "4")])
2971 [(set (match_operand:QI 0 "register_operand" "=r")
2972 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2973 (match_operand:DI 2 "int5_operand" "L"))))
2974 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2977 [(set_attr "type" "load")
2978 (set_attr "length" "4")])
2980 ; Now the same thing with zero extensions.
2982 [(set (match_operand:DI 0 "register_operand" "=r")
2983 (zero_extend:DI (mem:QI (plus:DI
2984 (match_operand:DI 1 "register_operand" "+r")
2985 (match_operand:DI 2 "int5_operand" "L")))))
2986 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2989 [(set_attr "type" "load")
2990 (set_attr "length" "4")])
2993 [(set (match_operand:SI 0 "register_operand" "=r")
2994 (zero_extend:SI (mem:QI (plus:SI
2995 (match_operand:SI 1 "register_operand" "+r")
2996 (match_operand:SI 2 "int5_operand" "L")))))
2997 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2999 "{ldbs|ldb},mb %2(%1),%0"
3000 [(set_attr "type" "load")
3001 (set_attr "length" "4")])
3004 [(set (match_operand:SI 0 "register_operand" "=r")
3005 (zero_extend:SI (mem:QI (plus:DI
3006 (match_operand:DI 1 "register_operand" "+r")
3007 (match_operand:DI 2 "int5_operand" "L")))))
3008 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3011 [(set_attr "type" "load")
3012 (set_attr "length" "4")])
3015 [(set (match_operand:HI 0 "register_operand" "=r")
3016 (zero_extend:HI (mem:QI (plus:SI
3017 (match_operand:SI 1 "register_operand" "+r")
3018 (match_operand:SI 2 "int5_operand" "L")))))
3019 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3021 "{ldbs|ldb},mb %2(%1),%0"
3022 [(set_attr "type" "load")
3023 (set_attr "length" "4")])
3026 [(set (match_operand:HI 0 "register_operand" "=r")
3027 (zero_extend:HI (mem:QI (plus:DI
3028 (match_operand:DI 1 "register_operand" "+r")
3029 (match_operand:DI 2 "int5_operand" "L")))))
3030 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3033 [(set_attr "type" "load")
3034 (set_attr "length" "4")])
3037 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3038 (match_operand:SI 1 "int5_operand" "L")))
3039 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3041 (plus:SI (match_dup 0) (match_dup 1)))]
3043 "{stbs|stb},mb %r2,%1(%0)"
3044 [(set_attr "type" "store")
3045 (set_attr "length" "4")])
3048 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3049 (match_operand:DI 1 "int5_operand" "L")))
3050 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3052 (plus:DI (match_dup 0) (match_dup 1)))]
3055 [(set_attr "type" "store")
3056 (set_attr "length" "4")])
3058 ;; The definition of this insn does not really explain what it does,
3059 ;; but it should suffice that anything generated as this insn will be
3060 ;; recognized as a movmemsi operation, and that it will not successfully
3061 ;; combine with anything.
3062 (define_expand "movmemsi"
3063 [(parallel [(set (match_operand:BLK 0 "" "")
3064 (match_operand:BLK 1 "" ""))
3065 (clobber (match_dup 4))
3066 (clobber (match_dup 5))
3067 (clobber (match_dup 6))
3068 (clobber (match_dup 7))
3069 (clobber (match_dup 8))
3070 (use (match_operand:SI 2 "arith14_operand" ""))
3071 (use (match_operand:SI 3 "const_int_operand" ""))])]
3072 "!TARGET_64BIT && optimize > 0"
3077 /* HP provides very fast block move library routine for the PA;
3078 this routine includes:
3080 4x4 byte at a time block moves,
3081 1x4 byte at a time with alignment checked at runtime with
3082 attempts to align the source and destination as needed
3085 With that in mind, here's the heuristics to try and guess when
3086 the inlined block move will be better than the library block
3089 If the size isn't constant, then always use the library routines.
3091 If the size is large in respect to the known alignment, then use
3092 the library routines.
3094 If the size is small in respect to the known alignment, then open
3095 code the copy (since that will lead to better scheduling).
3097 Else use the block move pattern. */
3099 /* Undetermined size, use the library routine. */
3100 if (GET_CODE (operands[2]) != CONST_INT)
3103 size = INTVAL (operands[2]);
3104 align = INTVAL (operands[3]);
3105 align = align > 4 ? 4 : (align ? align : 1);
3107 /* If size/alignment is large, then use the library routines. */
3108 if (size / align > 16)
3111 /* This does happen, but not often enough to worry much about. */
3112 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3115 /* Fall through means we're going to use our block move pattern. */
3117 = replace_equiv_address (operands[0],
3118 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3120 = replace_equiv_address (operands[1],
3121 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3122 operands[4] = gen_reg_rtx (SImode);
3123 operands[5] = gen_reg_rtx (SImode);
3124 operands[6] = gen_reg_rtx (SImode);
3125 operands[7] = gen_reg_rtx (SImode);
3126 operands[8] = gen_reg_rtx (SImode);
3129 ;; The operand constraints are written like this to support both compile-time
3130 ;; and run-time determined byte counts. The expander and pa_output_block_move
3131 ;; only support compile-time determined counts at this time.
3133 ;; If the count is run-time determined, the register with the byte count
3134 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3136 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3137 ;; broke this semantic for pseudo registers. We can't use match_scratch
3138 ;; as this requires two registers in the class R1_REGS when the MEMs for
3139 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3140 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3141 ;; respectively. We then split or peephole optimize after reload.
3142 (define_insn "movmemsi_prereload"
3143 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3144 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3145 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3146 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3147 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3148 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3149 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3150 (use (match_operand:SI 4 "arith14_operand" "J,2")) ;byte count
3151 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3154 [(set_attr "type" "multi,multi")])
3157 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3158 (match_operand:BLK 1 "memory_operand" ""))
3159 (clobber (match_operand:SI 2 "register_operand" ""))
3160 (clobber (match_operand:SI 3 "register_operand" ""))
3161 (clobber (match_operand:SI 6 "register_operand" ""))
3162 (clobber (match_operand:SI 7 "register_operand" ""))
3163 (clobber (match_operand:SI 8 "register_operand" ""))
3164 (use (match_operand:SI 4 "arith14_operand" ""))
3165 (use (match_operand:SI 5 "const_int_operand" ""))])]
3166 "!TARGET_64BIT && reload_completed && !flag_peephole2
3167 && GET_CODE (operands[0]) == MEM
3168 && register_operand (XEXP (operands[0], 0), SImode)
3169 && GET_CODE (operands[1]) == MEM
3170 && register_operand (XEXP (operands[1], 0), SImode)"
3171 [(set (match_dup 7) (match_dup 9))
3172 (set (match_dup 8) (match_dup 10))
3173 (parallel [(set (match_dup 0) (match_dup 1))
3174 (clobber (match_dup 2))
3175 (clobber (match_dup 3))
3176 (clobber (match_dup 6))
3177 (clobber (match_dup 7))
3178 (clobber (match_dup 8))
3184 operands[9] = XEXP (operands[0], 0);
3185 operands[10] = XEXP (operands[1], 0);
3186 operands[0] = replace_equiv_address (operands[0], operands[7]);
3187 operands[1] = replace_equiv_address (operands[1], operands[8]);
3191 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3192 (match_operand:BLK 1 "memory_operand" ""))
3193 (clobber (match_operand:SI 2 "register_operand" ""))
3194 (clobber (match_operand:SI 3 "register_operand" ""))
3195 (clobber (match_operand:SI 6 "register_operand" ""))
3196 (clobber (match_operand:SI 7 "register_operand" ""))
3197 (clobber (match_operand:SI 8 "register_operand" ""))
3198 (use (match_operand:SI 4 "arith14_operand" ""))
3199 (use (match_operand:SI 5 "const_int_operand" ""))])]
3201 && GET_CODE (operands[0]) == MEM
3202 && register_operand (XEXP (operands[0], 0), SImode)
3203 && GET_CODE (operands[1]) == MEM
3204 && register_operand (XEXP (operands[1], 0), SImode)"
3205 [(parallel [(set (match_dup 0) (match_dup 1))
3206 (clobber (match_dup 2))
3207 (clobber (match_dup 3))
3208 (clobber (match_dup 6))
3209 (clobber (match_dup 7))
3210 (clobber (match_dup 8))
3216 rtx addr = XEXP (operands[0], 0);
3217 if (dead_or_set_p (curr_insn, addr))
3221 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3222 operands[0] = replace_equiv_address (operands[0], operands[7]);
3225 addr = XEXP (operands[1], 0);
3226 if (dead_or_set_p (curr_insn, addr))
3230 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3231 operands[1] = replace_equiv_address (operands[1], operands[8]);
3235 (define_insn "movmemsi_postreload"
3236 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3237 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3238 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3239 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3240 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3241 (clobber (match_dup 0))
3242 (clobber (match_dup 1))
3243 (use (match_operand:SI 4 "arith14_operand" "J,2")) ;byte count
3244 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3246 "!TARGET_64BIT && reload_completed"
3247 "* return pa_output_block_move (operands, !which_alternative);"
3248 [(set_attr "type" "multi,multi")])
3250 (define_expand "movmemdi"
3251 [(parallel [(set (match_operand:BLK 0 "" "")
3252 (match_operand:BLK 1 "" ""))
3253 (clobber (match_dup 4))
3254 (clobber (match_dup 5))
3255 (clobber (match_dup 6))
3256 (clobber (match_dup 7))
3257 (clobber (match_dup 8))
3258 (use (match_operand:DI 2 "arith14_operand" ""))
3259 (use (match_operand:DI 3 "const_int_operand" ""))])]
3260 "TARGET_64BIT && optimize > 0"
3265 /* HP provides very fast block move library routine for the PA;
3266 this routine includes:
3268 4x4 byte at a time block moves,
3269 1x4 byte at a time with alignment checked at runtime with
3270 attempts to align the source and destination as needed
3273 With that in mind, here's the heuristics to try and guess when
3274 the inlined block move will be better than the library block
3277 If the size isn't constant, then always use the library routines.
3279 If the size is large in respect to the known alignment, then use
3280 the library routines.
3282 If the size is small in respect to the known alignment, then open
3283 code the copy (since that will lead to better scheduling).
3285 Else use the block move pattern. */
3287 /* Undetermined size, use the library routine. */
3288 if (GET_CODE (operands[2]) != CONST_INT)
3291 size = INTVAL (operands[2]);
3292 align = INTVAL (operands[3]);
3293 align = align > 8 ? 8 : (align ? align : 1);
3295 /* If size/alignment is large, then use the library routines. */
3296 if (size / align > 16)
3299 /* This does happen, but not often enough to worry much about. */
3300 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3303 /* Fall through means we're going to use our block move pattern. */
3305 = replace_equiv_address (operands[0],
3306 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3308 = replace_equiv_address (operands[1],
3309 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3310 operands[4] = gen_reg_rtx (DImode);
3311 operands[5] = gen_reg_rtx (DImode);
3312 operands[6] = gen_reg_rtx (DImode);
3313 operands[7] = gen_reg_rtx (DImode);
3314 operands[8] = gen_reg_rtx (DImode);
3317 ;; The operand constraints are written like this to support both compile-time
3318 ;; and run-time determined byte counts. The expander and pa_output_block_move
3319 ;; only support compile-time determined counts at this time.
3321 ;; If the count is run-time determined, the register with the byte count
3322 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3324 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3325 ;; broke this semantic for pseudo registers. We can't use match_scratch
3326 ;; as this requires two registers in the class R1_REGS when the MEMs for
3327 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3328 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3329 ;; respectively. We then split or peephole optimize after reload.
3330 (define_insn "movmemdi_prereload"
3331 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3332 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3333 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3334 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3335 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3336 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3337 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3338 (use (match_operand:DI 4 "arith14_operand" "J,2")) ;byte count
3339 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3342 [(set_attr "type" "multi,multi")])
3345 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3346 (match_operand:BLK 1 "memory_operand" ""))
3347 (clobber (match_operand:DI 2 "register_operand" ""))
3348 (clobber (match_operand:DI 3 "register_operand" ""))
3349 (clobber (match_operand:DI 6 "register_operand" ""))
3350 (clobber (match_operand:DI 7 "register_operand" ""))
3351 (clobber (match_operand:DI 8 "register_operand" ""))
3352 (use (match_operand:DI 4 "arith14_operand" ""))
3353 (use (match_operand:DI 5 "const_int_operand" ""))])]
3354 "TARGET_64BIT && reload_completed && !flag_peephole2
3355 && GET_CODE (operands[0]) == MEM
3356 && register_operand (XEXP (operands[0], 0), DImode)
3357 && GET_CODE (operands[1]) == MEM
3358 && register_operand (XEXP (operands[1], 0), DImode)"
3359 [(set (match_dup 7) (match_dup 9))
3360 (set (match_dup 8) (match_dup 10))
3361 (parallel [(set (match_dup 0) (match_dup 1))
3362 (clobber (match_dup 2))
3363 (clobber (match_dup 3))
3364 (clobber (match_dup 6))
3365 (clobber (match_dup 7))
3366 (clobber (match_dup 8))
3372 operands[9] = XEXP (operands[0], 0);
3373 operands[10] = XEXP (operands[1], 0);
3374 operands[0] = replace_equiv_address (operands[0], operands[7]);
3375 operands[1] = replace_equiv_address (operands[1], operands[8]);
3379 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3380 (match_operand:BLK 1 "memory_operand" ""))
3381 (clobber (match_operand:DI 2 "register_operand" ""))
3382 (clobber (match_operand:DI 3 "register_operand" ""))
3383 (clobber (match_operand:DI 6 "register_operand" ""))
3384 (clobber (match_operand:DI 7 "register_operand" ""))
3385 (clobber (match_operand:DI 8 "register_operand" ""))
3386 (use (match_operand:DI 4 "arith14_operand" ""))
3387 (use (match_operand:DI 5 "const_int_operand" ""))])]
3389 && GET_CODE (operands[0]) == MEM
3390 && register_operand (XEXP (operands[0], 0), DImode)
3391 && GET_CODE (operands[1]) == MEM
3392 && register_operand (XEXP (operands[1], 0), DImode)"
3393 [(parallel [(set (match_dup 0) (match_dup 1))
3394 (clobber (match_dup 2))
3395 (clobber (match_dup 3))
3396 (clobber (match_dup 6))
3397 (clobber (match_dup 7))
3398 (clobber (match_dup 8))
3404 rtx addr = XEXP (operands[0], 0);
3405 if (dead_or_set_p (curr_insn, addr))
3409 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3410 operands[0] = replace_equiv_address (operands[0], operands[7]);
3413 addr = XEXP (operands[1], 0);
3414 if (dead_or_set_p (curr_insn, addr))
3418 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3419 operands[1] = replace_equiv_address (operands[1], operands[8]);
3423 (define_insn "movmemdi_postreload"
3424 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3425 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3426 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3427 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3428 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3429 (clobber (match_dup 0))
3430 (clobber (match_dup 1))
3431 (use (match_operand:DI 4 "arith14_operand" "J,2")) ;byte count
3432 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3434 "TARGET_64BIT && reload_completed"
3435 "* return pa_output_block_move (operands, !which_alternative);"
3436 [(set_attr "type" "multi,multi")])
3438 (define_expand "setmemsi"
3439 [(parallel [(set (match_operand:BLK 0 "" "")
3440 (match_operand 2 "const_int_operand" ""))
3441 (clobber (match_dup 4))
3442 (clobber (match_dup 5))
3443 (use (match_operand:SI 1 "arith14_operand" ""))
3444 (use (match_operand:SI 3 "const_int_operand" ""))])]
3445 "!TARGET_64BIT && optimize > 0"
3450 /* If value to set is not zero, use the library routine. */
3451 if (operands[2] != const0_rtx)
3454 /* Undetermined size, use the library routine. */
3455 if (GET_CODE (operands[1]) != CONST_INT)
3458 size = INTVAL (operands[1]);
3459 align = INTVAL (operands[3]);
3460 align = align > 4 ? 4 : align;
3462 /* If size/alignment is large, then use the library routines. */
3463 if (size / align > 16)
3466 /* This does happen, but not often enough to worry much about. */
3467 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3470 /* Fall through means we're going to use our block clear pattern. */
3472 = replace_equiv_address (operands[0],
3473 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3474 operands[4] = gen_reg_rtx (SImode);
3475 operands[5] = gen_reg_rtx (SImode);
3478 (define_insn "clrmemsi_prereload"
3479 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3481 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3482 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3483 (use (match_operand:SI 2 "arith14_operand" "J,1")) ;byte count
3484 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3487 [(set_attr "type" "multi,multi")])
3490 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3492 (clobber (match_operand:SI 1 "register_operand" ""))
3493 (clobber (match_operand:SI 4 "register_operand" ""))
3494 (use (match_operand:SI 2 "arith14_operand" ""))
3495 (use (match_operand:SI 3 "const_int_operand" ""))])]
3496 "!TARGET_64BIT && reload_completed && !flag_peephole2
3497 && GET_CODE (operands[0]) == MEM
3498 && register_operand (XEXP (operands[0], 0), SImode)"
3499 [(set (match_dup 4) (match_dup 5))
3500 (parallel [(set (match_dup 0) (const_int 0))
3501 (clobber (match_dup 1))
3502 (clobber (match_dup 4))
3508 operands[5] = XEXP (operands[0], 0);
3509 operands[0] = replace_equiv_address (operands[0], operands[4]);
3513 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3515 (clobber (match_operand:SI 1 "register_operand" ""))
3516 (clobber (match_operand:SI 4 "register_operand" ""))
3517 (use (match_operand:SI 2 "arith14_operand" ""))
3518 (use (match_operand:SI 3 "const_int_operand" ""))])]
3520 && GET_CODE (operands[0]) == MEM
3521 && register_operand (XEXP (operands[0], 0), SImode)"
3522 [(parallel [(set (match_dup 0) (const_int 0))
3523 (clobber (match_dup 1))
3524 (clobber (match_dup 4))
3530 rtx addr = XEXP (operands[0], 0);
3531 if (dead_or_set_p (curr_insn, addr))
3535 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3536 operands[0] = replace_equiv_address (operands[0], operands[4]);
3540 (define_insn "clrmemsi_postreload"
3541 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3543 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3544 (clobber (match_dup 0))
3545 (use (match_operand:SI 2 "arith14_operand" "J,1")) ;byte count
3546 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3548 "!TARGET_64BIT && reload_completed"
3549 "* return pa_output_block_clear (operands, !which_alternative);"
3550 [(set_attr "type" "multi,multi")])
3552 (define_expand "setmemdi"
3553 [(parallel [(set (match_operand:BLK 0 "" "")
3554 (match_operand 2 "const_int_operand" ""))
3555 (clobber (match_dup 4))
3556 (clobber (match_dup 5))
3557 (use (match_operand:DI 1 "arith14_operand" ""))
3558 (use (match_operand:DI 3 "const_int_operand" ""))])]
3559 "TARGET_64BIT && optimize > 0"
3564 /* If value to set is not zero, use the library routine. */
3565 if (operands[2] != const0_rtx)
3568 /* Undetermined size, use the library routine. */
3569 if (GET_CODE (operands[1]) != CONST_INT)
3572 size = INTVAL (operands[1]);
3573 align = INTVAL (operands[3]);
3574 align = align > 8 ? 8 : align;
3576 /* If size/alignment is large, then use the library routines. */
3577 if (size / align > 16)
3580 /* This does happen, but not often enough to worry much about. */
3581 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3584 /* Fall through means we're going to use our block clear pattern. */
3586 = replace_equiv_address (operands[0],
3587 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3588 operands[4] = gen_reg_rtx (DImode);
3589 operands[5] = gen_reg_rtx (DImode);
3592 (define_insn "clrmemdi_prereload"
3593 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3595 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3596 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3597 (use (match_operand:DI 2 "arith14_operand" "J,1")) ;byte count
3598 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3601 [(set_attr "type" "multi,multi")])
3604 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3606 (clobber (match_operand:DI 1 "register_operand" ""))
3607 (clobber (match_operand:DI 4 "register_operand" ""))
3608 (use (match_operand:DI 2 "arith14_operand" ""))
3609 (use (match_operand:DI 3 "const_int_operand" ""))])]
3610 "TARGET_64BIT && reload_completed && !flag_peephole2
3611 && GET_CODE (operands[0]) == MEM
3612 && register_operand (XEXP (operands[0], 0), DImode)"
3613 [(set (match_dup 4) (match_dup 5))
3614 (parallel [(set (match_dup 0) (const_int 0))
3615 (clobber (match_dup 1))
3616 (clobber (match_dup 4))
3622 operands[5] = XEXP (operands[0], 0);
3623 operands[0] = replace_equiv_address (operands[0], operands[4]);
3627 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3629 (clobber (match_operand:DI 1 "register_operand" ""))
3630 (clobber (match_operand:DI 4 "register_operand" ""))
3631 (use (match_operand:DI 2 "arith14_operand" ""))
3632 (use (match_operand:DI 3 "const_int_operand" ""))])]
3634 && GET_CODE (operands[0]) == MEM
3635 && register_operand (XEXP (operands[0], 0), DImode)"
3636 [(parallel [(set (match_dup 0) (const_int 0))
3637 (clobber (match_dup 1))
3638 (clobber (match_dup 4))
3644 rtx addr = XEXP (operands[0], 0);
3645 if (dead_or_set_p (curr_insn, addr))
3649 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3650 operands[0] = replace_equiv_address (operands[0], operands[4]);
3654 (define_insn "clrmemdi_postreload"
3655 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3657 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3658 (clobber (match_dup 0))
3659 (use (match_operand:DI 2 "arith14_operand" "J,1")) ;byte count
3660 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3662 "TARGET_64BIT && reload_completed"
3663 "* return pa_output_block_clear (operands, !which_alternative);"
3664 [(set_attr "type" "multi,multi")])
3666 ;; Floating point move insns
3668 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3669 ;; to be reloaded by putting the constant into memory when
3670 ;; reg is a floating point register.
3672 ;; For integer registers we use ldil;ldo to set the appropriate
3675 ;; This must come before the movdf pattern, and it must be present
3676 ;; to handle obscure reloading cases.
3678 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3679 (match_operand:DF 1 "" "?F,m"))]
3680 "GET_CODE (operands[1]) == CONST_DOUBLE
3681 && operands[1] != CONST0_RTX (DFmode)
3683 && !TARGET_SOFT_FLOAT"
3684 "* return (which_alternative == 0 ? pa_output_move_double (operands)
3685 : \"fldd%F1 %1,%0\");"
3686 [(set_attr "type" "move,fpload")
3687 (set_attr "length" "16,4")])
3689 (define_expand "movdf"
3690 [(set (match_operand:DF 0 "general_operand" "")
3691 (match_operand:DF 1 "general_operand" ""))]
3695 if (GET_CODE (operands[1]) == CONST_DOUBLE
3696 && operands[1] != CONST0_RTX (DFmode))
3698 /* Reject CONST_DOUBLE loads to all hard registers when
3699 generating 64-bit code and to floating point registers
3700 when generating 32-bit code. */
3701 if (REG_P (operands[0])
3702 && HARD_REGISTER_P (operands[0])
3703 && (TARGET_64BIT || REGNO (operands[0]) >= 32))
3707 operands[1] = force_const_mem (DFmode, operands[1]);
3710 if (pa_emit_move_sequence (operands, DFmode, 0))
3714 ;; Handle DFmode input reloads requiring a general register as a
3715 ;; scratch register.
3716 (define_expand "reload_indf"
3717 [(set (match_operand:DF 0 "register_operand" "=Z")
3718 (match_operand:DF 1 "non_hard_reg_operand" ""))
3719 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3723 if (pa_emit_move_sequence (operands, DFmode, operands[2]))
3726 /* We don't want the clobber emitted, so handle this ourselves. */
3727 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3731 ;; Handle DFmode output reloads requiring a general register as a
3732 ;; scratch register.
3733 (define_expand "reload_outdf"
3734 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3735 (match_operand:DF 1 "register_operand" "Z"))
3736 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3740 if (pa_emit_move_sequence (operands, DFmode, operands[2]))
3743 /* We don't want the clobber emitted, so handle this ourselves. */
3744 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3749 [(set (match_operand:DF 0 "move_dest_operand"
3750 "=f,*r,Q,?o,?Q,f,*r,*r,?*r,?f")
3751 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3752 "fG,*rG,f,*r,*r,RQ,o,RQ,f,*r"))]
3753 "(register_operand (operands[0], DFmode)
3754 || reg_or_0_operand (operands[1], DFmode))
3755 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3756 && GET_CODE (operands[0]) == MEM)
3758 && !TARGET_SOFT_FLOAT"
3761 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3762 || operands[1] == CONST0_RTX (DFmode))
3763 && !(REG_P (operands[0]) && REG_P (operands[1])
3764 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
3765 return pa_output_fp_move_double (operands);
3766 return pa_output_move_double (operands);
3768 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
3769 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
3772 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3773 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3775 && !TARGET_DISABLE_INDEXING
3776 && reload_completed"
3778 [(set_attr "type" "fpstore")
3779 (set_attr "pa_combine_type" "addmove")
3780 (set_attr "length" "4")])
3783 [(set (match_operand:SI 0 "register_operand" "")
3784 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3786 (match_operand:SI 2 "register_operand" "")))
3787 (set (mem:DF (match_dup 0))
3788 (match_operand:DF 3 "register_operand" ""))]
3790 && !TARGET_DISABLE_INDEXING
3791 && REG_OK_FOR_BASE_P (operands[2])
3792 && FP_REGNO_P (REGNO (operands[3]))"
3793 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3795 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3800 [(set (match_operand:SI 0 "register_operand" "")
3801 (plus:SI (match_operand:SI 2 "register_operand" "")
3802 (mult:SI (match_operand:SI 1 "register_operand" "")
3804 (set (mem:DF (match_dup 0))
3805 (match_operand:DF 3 "register_operand" ""))]
3807 && !TARGET_DISABLE_INDEXING
3808 && REG_OK_FOR_BASE_P (operands[2])
3809 && FP_REGNO_P (REGNO (operands[3]))"
3810 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3812 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3817 [(set (match_operand:DI 0 "register_operand" "")
3818 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3820 (match_operand:DI 2 "register_operand" "")))
3821 (set (mem:DF (match_dup 0))
3822 (match_operand:DF 3 "register_operand" ""))]
3824 && !TARGET_DISABLE_INDEXING
3826 && REG_OK_FOR_BASE_P (operands[2])
3827 && FP_REGNO_P (REGNO (operands[3]))"
3828 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3830 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3835 [(set (match_operand:DI 0 "register_operand" "")
3836 (plus:DI (match_operand:DI 2 "register_operand" "")
3837 (mult:DI (match_operand:DI 1 "register_operand" "")
3839 (set (mem:DF (match_dup 0))
3840 (match_operand:DF 3 "register_operand" ""))]
3842 && !TARGET_DISABLE_INDEXING
3844 && REG_OK_FOR_BASE_P (operands[2])
3845 && FP_REGNO_P (REGNO (operands[3]))"
3846 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3848 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3853 [(set (match_operand:SI 0 "register_operand" "")
3854 (plus:SI (match_operand:SI 1 "register_operand" "")
3855 (match_operand:SI 2 "register_operand" "")))
3856 (set (mem:DF (match_dup 0))
3857 (match_operand:DF 3 "register_operand" ""))]
3859 && !TARGET_DISABLE_INDEXING
3860 && TARGET_NO_SPACE_REGS
3861 && REG_OK_FOR_INDEX_P (operands[1])
3862 && REG_OK_FOR_BASE_P (operands[2])
3863 && FP_REGNO_P (REGNO (operands[3]))"
3864 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3866 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3870 [(set (match_operand:SI 0 "register_operand" "")
3871 (plus:SI (match_operand:SI 1 "register_operand" "")
3872 (match_operand:SI 2 "register_operand" "")))
3873 (set (mem:DF (match_dup 0))
3874 (match_operand:DF 3 "register_operand" ""))]
3876 && !TARGET_DISABLE_INDEXING
3877 && TARGET_NO_SPACE_REGS
3878 && REG_OK_FOR_BASE_P (operands[1])
3879 && REG_OK_FOR_INDEX_P (operands[2])
3880 && FP_REGNO_P (REGNO (operands[3]))"
3881 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3883 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3887 [(set (match_operand:DI 0 "register_operand" "")
3888 (plus:DI (match_operand:DI 1 "register_operand" "")
3889 (match_operand:DI 2 "register_operand" "")))
3890 (set (mem:DF (match_dup 0))
3891 (match_operand:DF 3 "register_operand" ""))]
3893 && !TARGET_DISABLE_INDEXING
3895 && TARGET_NO_SPACE_REGS
3896 && REG_OK_FOR_INDEX_P (operands[1])
3897 && REG_OK_FOR_BASE_P (operands[2])
3898 && FP_REGNO_P (REGNO (operands[3]))"
3899 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3901 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3905 [(set (match_operand:DI 0 "register_operand" "")
3906 (plus:DI (match_operand:DI 1 "register_operand" "")
3907 (match_operand:DI 2 "register_operand" "")))
3908 (set (mem:DF (match_dup 0))
3909 (match_operand:DF 3 "register_operand" ""))]
3911 && !TARGET_DISABLE_INDEXING
3913 && TARGET_NO_SPACE_REGS
3914 && REG_OK_FOR_BASE_P (operands[1])
3915 && REG_OK_FOR_INDEX_P (operands[2])
3916 && FP_REGNO_P (REGNO (operands[3]))"
3917 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3919 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3923 [(set (match_operand:DF 0 "move_dest_operand"
3925 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3927 "(register_operand (operands[0], DFmode)
3928 || reg_or_0_operand (operands[1], DFmode))
3930 && TARGET_SOFT_FLOAT"
3933 return pa_output_move_double (operands);
3935 [(set_attr "type" "move,store,store,load,load")
3936 (set_attr "length" "8,8,16,8,16")])
3939 [(set (match_operand:DF 0 "move_dest_operand"
3940 "=!*r,*r,*r,*r,*r,Q,f,f,T")
3941 (match_operand:DF 1 "move_src_operand"
3942 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
3943 "(register_operand (operands[0], DFmode)
3944 || reg_or_0_operand (operands[1], DFmode))
3945 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3956 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
3957 (set_attr "pa_combine_type" "addmove")
3958 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3961 (define_expand "movdi"
3962 [(set (match_operand:DI 0 "general_operand" "")
3963 (match_operand:DI 1 "general_operand" ""))]
3967 /* Except for zero, we don't support loading a CONST_INT directly
3968 to a hard floating-point register since a scratch register is
3969 needed for the operation. While the operation could be handled
3970 before register allocation, the simplest solution is to fail. */
3972 && GET_CODE (operands[1]) == CONST_INT
3973 && operands[1] != CONST0_RTX (DImode)
3974 && REG_P (operands[0])
3975 && HARD_REGISTER_P (operands[0])
3976 && REGNO (operands[0]) >= 32)
3979 if (pa_emit_move_sequence (operands, DImode, 0))
3983 ;; Handle DImode input reloads requiring %r1 as a scratch register.
3984 (define_expand "reload_indi_r1"
3985 [(set (match_operand:DI 0 "register_operand" "=Z")
3986 (match_operand:DI 1 "non_hard_reg_operand" ""))
3987 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
3991 if (pa_emit_move_sequence (operands, DImode, operands[2]))
3994 /* We don't want the clobber emitted, so handle this ourselves. */
3995 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3999 ;; Handle DImode input reloads requiring a general register as a
4000 ;; scratch register.
4001 (define_expand "reload_indi"
4002 [(set (match_operand:DI 0 "register_operand" "=Z")
4003 (match_operand:DI 1 "non_hard_reg_operand" ""))
4004 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4008 if (pa_emit_move_sequence (operands, DImode, operands[2]))
4011 /* We don't want the clobber emitted, so handle this ourselves. */
4012 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4016 ;; Handle DImode output reloads requiring a general register as a
4017 ;; scratch register.
4018 (define_expand "reload_outdi"
4019 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4020 (match_operand:DI 1 "register_operand" "Z"))
4021 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4025 if (pa_emit_move_sequence (operands, DImode, operands[2]))
4028 /* We don't want the clobber emitted, so handle this ourselves. */
4029 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4034 [(set (match_operand:DI 0 "register_operand" "=r")
4035 (high:DI (match_operand 1 "" "")))]
4039 rtx op0 = operands[0];
4040 rtx op1 = operands[1];
4042 switch (GET_CODE (op1))
4045 #if HOST_BITS_PER_WIDE_INT <= 32
4046 operands[0] = operand_subword (op0, 1, 0, DImode);
4047 output_asm_insn (\"ldil L'%1,%0\", operands);
4049 operands[0] = operand_subword (op0, 0, 0, DImode);
4050 if (INTVAL (op1) < 0)
4051 output_asm_insn (\"ldi -1,%0\", operands);
4053 output_asm_insn (\"ldi 0,%0\", operands);
4055 operands[0] = operand_subword (op0, 1, 0, DImode);
4056 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4057 output_asm_insn (\"ldil L'%1,%0\", operands);
4059 operands[0] = operand_subword (op0, 0, 0, DImode);
4060 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4061 output_asm_insn (pa_singlemove_string (operands), operands);
4066 operands[0] = operand_subword (op0, 1, 0, DImode);
4067 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4068 output_asm_insn (\"ldil L'%1,%0\", operands);
4070 operands[0] = operand_subword (op0, 0, 0, DImode);
4071 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4072 output_asm_insn (pa_singlemove_string (operands), operands);
4080 [(set_attr "type" "move")
4081 (set_attr "length" "12")])
4084 [(set (match_operand:DI 0 "move_dest_operand"
4085 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4086 (match_operand:DI 1 "general_operand"
4087 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4088 "(register_operand (operands[0], DImode)
4089 || reg_or_0_operand (operands[1], DImode))
4091 && !TARGET_SOFT_FLOAT"
4094 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4095 || operands[1] == CONST0_RTX (DFmode))
4096 && !(REG_P (operands[0]) && REG_P (operands[1])
4097 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4098 return pa_output_fp_move_double (operands);
4099 return pa_output_move_double (operands);
4102 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4103 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4106 [(set (match_operand:DI 0 "move_dest_operand"
4107 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4108 (match_operand:DI 1 "move_src_operand"
4109 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4110 "(register_operand (operands[0], DImode)
4111 || reg_or_0_operand (operands[1], DImode))
4112 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4122 {mfctl|mfctl,w} %%sar,%0
4126 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4127 (set_attr "pa_combine_type" "addmove")
4128 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4131 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4132 (match_operand:DI 1 "register_operand" "f"))]
4135 && !TARGET_DISABLE_INDEXING
4136 && reload_completed"
4138 [(set_attr "type" "fpstore")
4139 (set_attr "pa_combine_type" "addmove")
4140 (set_attr "length" "4")])
4143 [(set (match_operand:DI 0 "register_operand" "")
4144 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4146 (match_operand:DI 2 "register_operand" "")))
4147 (set (mem:DI (match_dup 0))
4148 (match_operand:DI 3 "register_operand" ""))]
4150 && !TARGET_DISABLE_INDEXING
4152 && REG_OK_FOR_BASE_P (operands[2])
4153 && FP_REGNO_P (REGNO (operands[3]))"
4154 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4156 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4161 [(set (match_operand:DI 0 "register_operand" "")
4162 (plus:DI (match_operand:DI 2 "register_operand" "")
4163 (mult:DI (match_operand:DI 1 "register_operand" "")
4165 (set (mem:DI (match_dup 0))
4166 (match_operand:DI 3 "register_operand" ""))]
4168 && !TARGET_DISABLE_INDEXING
4170 && REG_OK_FOR_BASE_P (operands[2])
4171 && FP_REGNO_P (REGNO (operands[3]))"
4172 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4174 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4179 [(set (match_operand:DI 0 "register_operand" "")
4180 (plus:DI (match_operand:DI 1 "register_operand" "")
4181 (match_operand:DI 2 "register_operand" "")))
4182 (set (mem:DI (match_dup 0))
4183 (match_operand:DI 3 "register_operand" ""))]
4185 && !TARGET_DISABLE_INDEXING
4187 && TARGET_NO_SPACE_REGS
4188 && REG_OK_FOR_INDEX_P (operands[1])
4189 && REG_OK_FOR_BASE_P (operands[2])
4190 && FP_REGNO_P (REGNO (operands[3]))"
4191 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4193 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4197 [(set (match_operand:DI 0 "register_operand" "")
4198 (plus:DI (match_operand:DI 1 "register_operand" "")
4199 (match_operand:DI 2 "register_operand" "")))
4200 (set (mem:DI (match_dup 0))
4201 (match_operand:DI 3 "register_operand" ""))]
4203 && !TARGET_DISABLE_INDEXING
4205 && TARGET_NO_SPACE_REGS
4206 && REG_OK_FOR_BASE_P (operands[1])
4207 && REG_OK_FOR_INDEX_P (operands[2])
4208 && FP_REGNO_P (REGNO (operands[3]))"
4209 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4211 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4215 [(set (match_operand:DI 0 "move_dest_operand"
4217 (match_operand:DI 1 "general_operand"
4219 "(register_operand (operands[0], DImode)
4220 || reg_or_0_operand (operands[1], DImode))
4222 && TARGET_SOFT_FLOAT"
4225 return pa_output_move_double (operands);
4227 [(set_attr "type" "move,store,store,load,load,multi")
4228 (set_attr "length" "8,8,16,8,16,16")])
4231 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4232 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4233 (match_operand:DI 2 "immediate_operand" "i,i")))]
4237 /* Don't output a 64-bit constant, since we can't trust the assembler to
4238 handle it correctly. */
4239 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4240 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4241 else if (HOST_BITS_PER_WIDE_INT > 32
4242 && GET_CODE (operands[2]) == CONST_INT)
4243 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4244 if (which_alternative == 1)
4245 output_asm_insn (\"copy %1,%0\", operands);
4246 return \"ldo R'%G2(%R1),%R0\";
4248 [(set_attr "type" "move,move")
4249 (set_attr "length" "4,8")])
4251 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4252 ;; to be reloaded by putting the constant into memory when
4253 ;; reg is a floating point register.
4255 ;; For integer registers we use ldil;ldo to set the appropriate
4258 ;; This must come before the movsf pattern, and it must be present
4259 ;; to handle obscure reloading cases.
4261 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4262 (match_operand:SF 1 "" "?F,m"))]
4263 "GET_CODE (operands[1]) == CONST_DOUBLE
4264 && operands[1] != CONST0_RTX (SFmode)
4265 && ! TARGET_SOFT_FLOAT"
4266 "* return (which_alternative == 0 ? pa_singlemove_string (operands)
4267 : \" fldw%F1 %1,%0\");"
4268 [(set_attr "type" "move,fpload")
4269 (set_attr "length" "8,4")])
4271 (define_expand "movsf"
4272 [(set (match_operand:SF 0 "general_operand" "")
4273 (match_operand:SF 1 "general_operand" ""))]
4277 /* Reject CONST_DOUBLE loads to floating point registers. */
4278 if (GET_CODE (operands[1]) == CONST_DOUBLE
4279 && operands[1] != CONST0_RTX (SFmode)
4280 && REG_P (operands[0])
4281 && HARD_REGISTER_P (operands[0])
4282 && REGNO (operands[0]) >= 32)
4285 if (pa_emit_move_sequence (operands, SFmode, 0))
4289 ;; Handle SFmode input reloads requiring a general register as a
4290 ;; scratch register.
4291 (define_expand "reload_insf"
4292 [(set (match_operand:SF 0 "register_operand" "=Z")
4293 (match_operand:SF 1 "non_hard_reg_operand" ""))
4294 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4298 if (pa_emit_move_sequence (operands, SFmode, operands[2]))
4301 /* We don't want the clobber emitted, so handle this ourselves. */
4302 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4306 ;; Handle SFmode output reloads requiring a general register as a
4307 ;; scratch register.
4308 (define_expand "reload_outsf"
4309 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4310 (match_operand:SF 1 "register_operand" "Z"))
4311 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4315 if (pa_emit_move_sequence (operands, SFmode, operands[2]))
4318 /* We don't want the clobber emitted, so handle this ourselves. */
4319 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4324 [(set (match_operand:SF 0 "move_dest_operand"
4325 "=f,!*r,f,*r,Q,Q,?*r,?f")
4326 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4327 "fG,!*rG,RQ,RQ,f,*rG,f,*r"))]
4328 "(register_operand (operands[0], SFmode)
4329 || reg_or_0_operand (operands[1], SFmode))
4330 && !TARGET_SOFT_FLOAT
4339 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4340 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4341 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4342 (set_attr "pa_combine_type" "addmove")
4343 (set_attr "length" "4,4,4,4,4,4,8,8")])
4346 [(set (match_operand:SF 0 "move_dest_operand"
4348 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4349 "fG,!*rG,RQ,RQ,f,*rG"))]
4350 "(register_operand (operands[0], SFmode)
4351 || reg_or_0_operand (operands[1], SFmode))
4352 && !TARGET_SOFT_FLOAT
4361 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4362 (set_attr "pa_combine_type" "addmove")
4363 (set_attr "length" "4,4,4,4,4,4")])
4366 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4367 (match_operand:SF 1 "register_operand" "f"))]
4369 && !TARGET_DISABLE_INDEXING
4370 && reload_completed"
4372 [(set_attr "type" "fpstore")
4373 (set_attr "pa_combine_type" "addmove")
4374 (set_attr "length" "4")])
4377 [(set (match_operand:SI 0 "register_operand" "")
4378 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4380 (match_operand:SI 2 "register_operand" "")))
4381 (set (mem:SF (match_dup 0))
4382 (match_operand:SF 3 "register_operand" ""))]
4384 && !TARGET_DISABLE_INDEXING
4385 && REG_OK_FOR_BASE_P (operands[2])
4386 && FP_REGNO_P (REGNO (operands[3]))"
4387 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4389 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4394 [(set (match_operand:SI 0 "register_operand" "")
4395 (plus:SI (match_operand:SI 2 "register_operand" "")
4396 (mult:SI (match_operand:SI 1 "register_operand" "")
4398 (set (mem:SF (match_dup 0))
4399 (match_operand:SF 3 "register_operand" ""))]
4401 && !TARGET_DISABLE_INDEXING
4402 && REG_OK_FOR_BASE_P (operands[2])
4403 && FP_REGNO_P (REGNO (operands[3]))"
4404 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4406 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4411 [(set (match_operand:DI 0 "register_operand" "")
4412 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4414 (match_operand:DI 2 "register_operand" "")))
4415 (set (mem:SF (match_dup 0))
4416 (match_operand:SF 3 "register_operand" ""))]
4418 && !TARGET_DISABLE_INDEXING
4420 && REG_OK_FOR_BASE_P (operands[2])
4421 && FP_REGNO_P (REGNO (operands[3]))"
4422 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4424 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4429 [(set (match_operand:DI 0 "register_operand" "")
4430 (plus:DI (match_operand:DI 2 "register_operand" "")
4431 (mult:DI (match_operand:DI 1 "register_operand" "")
4433 (set (mem:SF (match_dup 0))
4434 (match_operand:SF 3 "register_operand" ""))]
4436 && !TARGET_DISABLE_INDEXING
4438 && REG_OK_FOR_BASE_P (operands[2])
4439 && FP_REGNO_P (REGNO (operands[3]))"
4440 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4442 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4447 [(set (match_operand:SI 0 "register_operand" "")
4448 (plus:SI (match_operand:SI 1 "register_operand" "")
4449 (match_operand:SI 2 "register_operand" "")))
4450 (set (mem:SF (match_dup 0))
4451 (match_operand:SF 3 "register_operand" ""))]
4453 && !TARGET_DISABLE_INDEXING
4454 && TARGET_NO_SPACE_REGS
4455 && REG_OK_FOR_INDEX_P (operands[1])
4456 && REG_OK_FOR_BASE_P (operands[2])
4457 && FP_REGNO_P (REGNO (operands[3]))"
4458 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4460 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4464 [(set (match_operand:SI 0 "register_operand" "")
4465 (plus:SI (match_operand:SI 1 "register_operand" "")
4466 (match_operand:SI 2 "register_operand" "")))
4467 (set (mem:SF (match_dup 0))
4468 (match_operand:SF 3 "register_operand" ""))]
4470 && !TARGET_DISABLE_INDEXING
4471 && TARGET_NO_SPACE_REGS
4472 && REG_OK_FOR_BASE_P (operands[1])
4473 && REG_OK_FOR_INDEX_P (operands[2])
4474 && FP_REGNO_P (REGNO (operands[3]))"
4475 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4477 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4481 [(set (match_operand:DI 0 "register_operand" "")
4482 (plus:DI (match_operand:DI 1 "register_operand" "")
4483 (match_operand:DI 2 "register_operand" "")))
4484 (set (mem:SF (match_dup 0))
4485 (match_operand:SF 3 "register_operand" ""))]
4487 && !TARGET_DISABLE_INDEXING
4489 && TARGET_NO_SPACE_REGS
4490 && REG_OK_FOR_INDEX_P (operands[1])
4491 && REG_OK_FOR_BASE_P (operands[2])
4492 && FP_REGNO_P (REGNO (operands[3]))"
4493 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4495 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4499 [(set (match_operand:DI 0 "register_operand" "")
4500 (plus:DI (match_operand:DI 1 "register_operand" "")
4501 (match_operand:DI 2 "register_operand" "")))
4502 (set (mem:SF (match_dup 0))
4503 (match_operand:SF 3 "register_operand" ""))]
4505 && !TARGET_DISABLE_INDEXING
4507 && TARGET_NO_SPACE_REGS
4508 && REG_OK_FOR_BASE_P (operands[1])
4509 && REG_OK_FOR_INDEX_P (operands[2])
4510 && FP_REGNO_P (REGNO (operands[3]))"
4511 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4513 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4517 [(set (match_operand:SF 0 "move_dest_operand"
4519 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4521 "(register_operand (operands[0], SFmode)
4522 || reg_or_0_operand (operands[1], SFmode))
4523 && TARGET_SOFT_FLOAT"
4528 [(set_attr "type" "move,load,store")
4529 (set_attr "pa_combine_type" "addmove")
4530 (set_attr "length" "4,4,4")])
4534 ;;- zero extension instructions
4535 ;; We have define_expand for zero extension patterns to make sure the
4536 ;; operands get loaded into registers. The define_insns accept
4537 ;; memory operands. This gives us better overall code than just
4538 ;; having a pattern that does or does not accept memory operands.
4540 (define_expand "zero_extendqihi2"
4541 [(set (match_operand:HI 0 "register_operand" "")
4543 (match_operand:QI 1 "register_operand" "")))]
4548 [(set (match_operand:HI 0 "register_operand" "=r,r")
4550 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4551 "GET_CODE (operands[1]) != CONST_INT"
4553 {extru|extrw,u} %1,31,8,%0
4555 [(set_attr "type" "shift,load")
4556 (set_attr "length" "4,4")])
4558 (define_expand "zero_extendqisi2"
4559 [(set (match_operand:SI 0 "register_operand" "")
4561 (match_operand:QI 1 "register_operand" "")))]
4566 [(set (match_operand:SI 0 "register_operand" "=r,r")
4568 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4569 "GET_CODE (operands[1]) != CONST_INT"
4571 {extru|extrw,u} %1,31,8,%0
4573 [(set_attr "type" "shift,load")
4574 (set_attr "length" "4,4")])
4576 (define_expand "zero_extendhisi2"
4577 [(set (match_operand:SI 0 "register_operand" "")
4579 (match_operand:HI 1 "register_operand" "")))]
4584 [(set (match_operand:SI 0 "register_operand" "=r,r")
4586 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4587 "GET_CODE (operands[1]) != CONST_INT"
4589 {extru|extrw,u} %1,31,16,%0
4591 [(set_attr "type" "shift,load")
4592 (set_attr "length" "4,4")])
4594 (define_expand "zero_extendqidi2"
4595 [(set (match_operand:DI 0 "register_operand" "")
4597 (match_operand:QI 1 "register_operand" "")))]
4602 [(set (match_operand:DI 0 "register_operand" "=r,r")
4604 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4605 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4609 [(set_attr "type" "shift,load")
4610 (set_attr "length" "4,4")])
4612 (define_expand "zero_extendhidi2"
4613 [(set (match_operand:DI 0 "register_operand" "")
4615 (match_operand:HI 1 "register_operand" "")))]
4620 [(set (match_operand:DI 0 "register_operand" "=r,r")
4622 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4623 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4627 [(set_attr "type" "shift,load")
4628 (set_attr "length" "4,4")])
4630 (define_expand "zero_extendsidi2"
4631 [(set (match_operand:DI 0 "register_operand" "")
4633 (match_operand:SI 1 "register_operand" "")))]
4638 [(set (match_operand:DI 0 "register_operand" "=r,r")
4640 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4641 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4645 [(set_attr "type" "shift,load")
4646 (set_attr "length" "4,4")])
4648 ;;- sign extension instructions
4650 (define_insn "extendhisi2"
4651 [(set (match_operand:SI 0 "register_operand" "=r")
4652 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4654 "{extrs|extrw,s} %1,31,16,%0"
4655 [(set_attr "type" "shift")
4656 (set_attr "length" "4")])
4658 (define_insn "extendqihi2"
4659 [(set (match_operand:HI 0 "register_operand" "=r")
4660 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4662 "{extrs|extrw,s} %1,31,8,%0"
4663 [(set_attr "type" "shift")
4664 (set_attr "length" "4")])
4666 (define_insn "extendqisi2"
4667 [(set (match_operand:SI 0 "register_operand" "=r")
4668 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4670 "{extrs|extrw,s} %1,31,8,%0"
4671 [(set_attr "type" "shift")
4672 (set_attr "length" "4")])
4674 (define_insn "extendqidi2"
4675 [(set (match_operand:DI 0 "register_operand" "=r")
4676 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4678 "extrd,s %1,63,8,%0"
4679 [(set_attr "type" "shift")
4680 (set_attr "length" "4")])
4682 (define_insn "extendhidi2"
4683 [(set (match_operand:DI 0 "register_operand" "=r")
4684 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4686 "extrd,s %1,63,16,%0"
4687 [(set_attr "type" "shift")
4688 (set_attr "length" "4")])
4690 (define_insn "extendsidi2"
4691 [(set (match_operand:DI 0 "register_operand" "=r")
4692 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4694 "extrd,s %1,63,32,%0"
4695 [(set_attr "type" "shift")
4696 (set_attr "length" "4")])
4699 ;; Conversions between float and double.
4701 (define_insn "extendsfdf2"
4702 [(set (match_operand:DF 0 "register_operand" "=f")
4704 (match_operand:SF 1 "register_operand" "f")))]
4705 "! TARGET_SOFT_FLOAT"
4706 "{fcnvff|fcnv},sgl,dbl %1,%0"
4707 [(set_attr "type" "fpalu")
4708 (set_attr "length" "4")])
4710 (define_insn "truncdfsf2"
4711 [(set (match_operand:SF 0 "register_operand" "=f")
4713 (match_operand:DF 1 "register_operand" "f")))]
4714 "! TARGET_SOFT_FLOAT"
4715 "{fcnvff|fcnv},dbl,sgl %1,%0"
4716 [(set_attr "type" "fpalu")
4717 (set_attr "length" "4")])
4719 ;; Conversion between fixed point and floating point.
4720 ;; Note that among the fix-to-float insns
4721 ;; the ones that start with SImode come first.
4722 ;; That is so that an operand that is a CONST_INT
4723 ;; (and therefore lacks a specific machine mode).
4724 ;; will be recognized as SImode (which is always valid)
4725 ;; rather than as QImode or HImode.
4727 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4728 ;; to be reloaded by putting the constant into memory.
4729 ;; It must come before the more general floatsisf2 pattern.
4731 [(set (match_operand:SF 0 "register_operand" "=f")
4732 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4733 "! TARGET_SOFT_FLOAT"
4734 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4735 [(set_attr "type" "fpalu")
4736 (set_attr "length" "8")])
4738 (define_insn "floatsisf2"
4739 [(set (match_operand:SF 0 "register_operand" "=f")
4740 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4741 "! TARGET_SOFT_FLOAT"
4742 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4743 [(set_attr "type" "fpalu")
4744 (set_attr "length" "4")])
4746 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4747 ;; to be reloaded by putting the constant into memory.
4748 ;; It must come before the more general floatsidf2 pattern.
4750 [(set (match_operand:DF 0 "register_operand" "=f")
4751 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4752 "! TARGET_SOFT_FLOAT"
4753 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4754 [(set_attr "type" "fpalu")
4755 (set_attr "length" "8")])
4757 (define_insn "floatsidf2"
4758 [(set (match_operand:DF 0 "register_operand" "=f")
4759 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4760 "! TARGET_SOFT_FLOAT"
4761 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4762 [(set_attr "type" "fpalu")
4763 (set_attr "length" "4")])
4765 (define_expand "floatunssisf2"
4766 [(set (subreg:SI (match_dup 2) 4)
4767 (match_operand:SI 1 "register_operand" ""))
4768 (set (subreg:SI (match_dup 2) 0)
4770 (set (match_operand:SF 0 "register_operand" "")
4771 (float:SF (match_dup 2)))]
4772 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4777 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4780 operands[2] = gen_reg_rtx (DImode);
4783 (define_expand "floatunssidf2"
4784 [(set (subreg:SI (match_dup 2) 4)
4785 (match_operand:SI 1 "register_operand" ""))
4786 (set (subreg:SI (match_dup 2) 0)
4788 (set (match_operand:DF 0 "register_operand" "")
4789 (float:DF (match_dup 2)))]
4790 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4795 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4798 operands[2] = gen_reg_rtx (DImode);
4801 (define_insn "floatdisf2"
4802 [(set (match_operand:SF 0 "register_operand" "=f")
4803 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4804 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4805 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4806 [(set_attr "type" "fpalu")
4807 (set_attr "length" "4")])
4809 (define_insn "floatdidf2"
4810 [(set (match_operand:DF 0 "register_operand" "=f")
4811 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4812 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4813 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4814 [(set_attr "type" "fpalu")
4815 (set_attr "length" "4")])
4817 ;; Convert a float to an actual integer.
4818 ;; Truncation is performed as part of the conversion.
4820 (define_insn "fix_truncsfsi2"
4821 [(set (match_operand:SI 0 "register_operand" "=f")
4822 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4823 "! TARGET_SOFT_FLOAT"
4824 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4825 [(set_attr "type" "fpalu")
4826 (set_attr "length" "4")])
4828 (define_insn "fix_truncdfsi2"
4829 [(set (match_operand:SI 0 "register_operand" "=f")
4830 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4831 "! TARGET_SOFT_FLOAT"
4832 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4833 [(set_attr "type" "fpalu")
4834 (set_attr "length" "4")])
4836 (define_insn "fix_truncsfdi2"
4837 [(set (match_operand:DI 0 "register_operand" "=f")
4838 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4839 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4840 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4841 [(set_attr "type" "fpalu")
4842 (set_attr "length" "4")])
4844 (define_insn "fix_truncdfdi2"
4845 [(set (match_operand:DI 0 "register_operand" "=f")
4846 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4847 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4848 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4849 [(set_attr "type" "fpalu")
4850 (set_attr "length" "4")])
4852 (define_insn "floatunssidf2_pa20"
4853 [(set (match_operand:DF 0 "register_operand" "=f")
4854 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4855 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4857 [(set_attr "type" "fpalu")
4858 (set_attr "length" "4")])
4860 (define_insn "floatunssisf2_pa20"
4861 [(set (match_operand:SF 0 "register_operand" "=f")
4862 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4863 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4865 [(set_attr "type" "fpalu")
4866 (set_attr "length" "4")])
4868 (define_insn "floatunsdisf2"
4869 [(set (match_operand:SF 0 "register_operand" "=f")
4870 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4871 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4872 "fcnv,udw,sgl %1,%0"
4873 [(set_attr "type" "fpalu")
4874 (set_attr "length" "4")])
4876 (define_insn "floatunsdidf2"
4877 [(set (match_operand:DF 0 "register_operand" "=f")
4878 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4879 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4880 "fcnv,udw,dbl %1,%0"
4881 [(set_attr "type" "fpalu")
4882 (set_attr "length" "4")])
4884 (define_insn "fixuns_truncsfsi2"
4885 [(set (match_operand:SI 0 "register_operand" "=f")
4886 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4887 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4888 "fcnv,t,sgl,uw %1,%0"
4889 [(set_attr "type" "fpalu")
4890 (set_attr "length" "4")])
4892 (define_insn "fixuns_truncdfsi2"
4893 [(set (match_operand:SI 0 "register_operand" "=f")
4894 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4895 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4896 "fcnv,t,dbl,uw %1,%0"
4897 [(set_attr "type" "fpalu")
4898 (set_attr "length" "4")])
4900 (define_insn "fixuns_truncsfdi2"
4901 [(set (match_operand:DI 0 "register_operand" "=f")
4902 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4903 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4904 "fcnv,t,sgl,udw %1,%0"
4905 [(set_attr "type" "fpalu")
4906 (set_attr "length" "4")])
4908 (define_insn "fixuns_truncdfdi2"
4909 [(set (match_operand:DI 0 "register_operand" "=f")
4910 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4911 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4912 "fcnv,t,dbl,udw %1,%0"
4913 [(set_attr "type" "fpalu")
4914 (set_attr "length" "4")])
4916 ;;- arithmetic instructions
4918 (define_expand "adddi3"
4919 [(set (match_operand:DI 0 "register_operand" "")
4920 (plus:DI (match_operand:DI 1 "register_operand" "")
4921 (match_operand:DI 2 "adddi3_operand" "")))]
4926 [(set (match_operand:DI 0 "register_operand" "=r")
4927 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4928 (match_operand:DI 2 "arith11_operand" "rI")))]
4932 if (GET_CODE (operands[2]) == CONST_INT)
4934 if (INTVAL (operands[2]) >= 0)
4935 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4937 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4940 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4942 [(set_attr "type" "binary")
4943 (set_attr "length" "8")])
4946 [(set (match_operand:DI 0 "register_operand" "=r,r")
4947 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4948 (match_operand:DI 2 "arith14_operand" "r,J")))]
4953 [(set_attr "type" "binary,binary")
4954 (set_attr "pa_combine_type" "addmove")
4955 (set_attr "length" "4,4")])
4958 [(set (match_operand:DI 0 "register_operand" "=r")
4959 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4960 (match_operand:DI 2 "register_operand" "r")))]
4963 [(set_attr "type" "binary")
4964 (set_attr "length" "4")])
4967 [(set (match_operand:SI 0 "register_operand" "=r")
4968 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4969 (match_operand:SI 2 "register_operand" "r")))]
4972 [(set_attr "type" "binary")
4973 (set_attr "length" "4")])
4975 (define_expand "addvdi3"
4976 [(parallel [(set (match_operand:DI 0 "register_operand" "")
4977 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
4978 (match_operand:DI 2 "arith11_operand" "")))
4979 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4980 (sign_extend:TI (match_dup 2)))
4981 (sign_extend:TI (plus:DI (match_dup 1)
4988 [(set (match_operand:DI 0 "register_operand" "=r,r")
4989 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
4990 (match_operand:DI 2 "arith11_operand" "r,I")))
4991 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4992 (sign_extend:TI (match_dup 2)))
4993 (sign_extend:TI (plus:DI (match_dup 1)
4999 addi,tsv,* %2,%1,%0"
5000 [(set_attr "type" "binary,binary")
5001 (set_attr "length" "4,4")])
5004 [(set (match_operand:DI 0 "register_operand" "=r")
5005 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5006 (match_operand:DI 2 "arith11_operand" "rI")))
5007 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5008 (sign_extend:TI (match_dup 2)))
5009 (sign_extend:TI (plus:DI (match_dup 1)
5015 if (GET_CODE (operands[2]) == CONST_INT)
5017 if (INTVAL (operands[2]) >= 0)
5018 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5020 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5023 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5025 [(set_attr "type" "binary")
5026 (set_attr "length" "8")])
5028 ;; define_splits to optimize cases of adding a constant integer
5029 ;; to a register when the constant does not fit in 14 bits. */
5031 [(set (match_operand:SI 0 "register_operand" "")
5032 (plus:SI (match_operand:SI 1 "register_operand" "")
5033 (match_operand:SI 2 "const_int_operand" "")))
5034 (clobber (match_operand:SI 4 "register_operand" ""))]
5035 "! pa_cint_ok_for_move (INTVAL (operands[2]))
5036 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5037 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5038 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5041 int val = INTVAL (operands[2]);
5042 int low = (val < 0) ? -0x2000 : 0x1fff;
5043 int rest = val - low;
5045 operands[2] = GEN_INT (rest);
5046 operands[3] = GEN_INT (low);
5050 [(set (match_operand:SI 0 "register_operand" "")
5051 (plus:SI (match_operand:SI 1 "register_operand" "")
5052 (match_operand:SI 2 "const_int_operand" "")))
5053 (clobber (match_operand:SI 4 "register_operand" ""))]
5054 "! pa_cint_ok_for_move (INTVAL (operands[2]))"
5055 [(set (match_dup 4) (match_dup 2))
5056 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5060 HOST_WIDE_INT intval = INTVAL (operands[2]);
5062 /* Try dividing the constant by 2, then 4, and finally 8 to see
5063 if we can get a constant which can be loaded into a register
5064 in a single instruction (pa_cint_ok_for_move).
5066 If that fails, try to negate the constant and subtract it
5067 from our input operand. */
5068 if (intval % 2 == 0 && pa_cint_ok_for_move (intval / 2))
5070 operands[2] = GEN_INT (intval / 2);
5071 operands[3] = const2_rtx;
5073 else if (intval % 4 == 0 && pa_cint_ok_for_move (intval / 4))
5075 operands[2] = GEN_INT (intval / 4);
5076 operands[3] = GEN_INT (4);
5078 else if (intval % 8 == 0 && pa_cint_ok_for_move (intval / 8))
5080 operands[2] = GEN_INT (intval / 8);
5081 operands[3] = GEN_INT (8);
5083 else if (pa_cint_ok_for_move (-intval))
5085 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5086 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5093 (define_insn "addsi3"
5094 [(set (match_operand:SI 0 "register_operand" "=r,r")
5095 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5096 (match_operand:SI 2 "arith14_operand" "r,J")))]
5099 {addl|add,l} %1,%2,%0
5101 [(set_attr "type" "binary,binary")
5102 (set_attr "pa_combine_type" "addmove")
5103 (set_attr "length" "4,4")])
5105 (define_insn "addvsi3"
5106 [(set (match_operand:SI 0 "register_operand" "=r,r")
5107 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5108 (match_operand:SI 2 "arith11_operand" "r,I")))
5109 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5110 (sign_extend:DI (match_dup 2)))
5111 (sign_extend:DI (plus:SI (match_dup 1)
5116 {addo|add,tsv} %2,%1,%0
5117 {addio|addi,tsv} %2,%1,%0"
5118 [(set_attr "type" "binary,binary")
5119 (set_attr "length" "4,4")])
5121 (define_expand "subdi3"
5122 [(set (match_operand:DI 0 "register_operand" "")
5123 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5124 (match_operand:DI 2 "reg_or_0_operand" "")))]
5129 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5130 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5131 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5137 [(set_attr "type" "binary,binary,move")
5138 (set_attr "length" "4,4,4")])
5141 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5142 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5143 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5147 if (GET_CODE (operands[1]) == CONST_INT)
5149 if (INTVAL (operands[1]) >= 0)
5150 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5152 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5155 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5157 [(set_attr "type" "binary")
5158 (set (attr "length")
5159 (if_then_else (eq_attr "alternative" "0")
5161 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5166 (define_expand "subvdi3"
5167 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5168 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5169 (match_operand:DI 2 "reg_or_0_operand" "")))
5170 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5171 (sign_extend:TI (match_dup 2)))
5172 (sign_extend:TI (minus:DI (match_dup 1)
5179 [(set (match_operand:DI 0 "register_operand" "=r,r")
5180 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5181 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5182 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5183 (sign_extend:TI (match_dup 2)))
5184 (sign_extend:TI (minus:DI (match_dup 1)
5189 {subo|sub,tsv} %1,%2,%0
5190 {subio|subi,tsv} %1,%2,%0"
5191 [(set_attr "type" "binary,binary")
5192 (set_attr "length" "4,4")])
5195 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5196 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5197 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5198 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5199 (sign_extend:TI (match_dup 2)))
5200 (sign_extend:TI (minus:DI (match_dup 1)
5206 if (GET_CODE (operands[1]) == CONST_INT)
5208 if (INTVAL (operands[1]) >= 0)
5209 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5211 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5214 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5216 [(set_attr "type" "binary,binary")
5217 (set (attr "length")
5218 (if_then_else (eq_attr "alternative" "0")
5220 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5225 (define_expand "subsi3"
5226 [(set (match_operand:SI 0 "register_operand" "")
5227 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5228 (match_operand:SI 2 "register_operand" "")))]
5233 [(set (match_operand:SI 0 "register_operand" "=r,r")
5234 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5235 (match_operand:SI 2 "register_operand" "r,r")))]
5240 [(set_attr "type" "binary,binary")
5241 (set_attr "length" "4,4")])
5244 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5245 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5246 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5252 [(set_attr "type" "binary,binary,move")
5253 (set_attr "length" "4,4,4")])
5255 (define_insn "subvsi3"
5256 [(set (match_operand:SI 0 "register_operand" "=r,r")
5257 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5258 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5259 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5260 (sign_extend:DI (match_dup 2)))
5261 (sign_extend:DI (minus:SI (match_dup 1)
5266 {subo|sub,tsv} %1,%2,%0
5267 {subio|subi,tsv} %1,%2,%0"
5268 [(set_attr "type" "binary,binary")
5269 (set_attr "length" "4,4")])
5271 ;; Clobbering a "register_operand" instead of a match_scratch
5272 ;; in operand3 of millicode calls avoids spilling %r1 and
5273 ;; produces better code.
5275 ;; The mulsi3 insns set up registers for the millicode call.
5276 (define_expand "mulsi3"
5277 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5278 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5279 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5280 (clobber (match_dup 3))
5281 (clobber (reg:SI 26))
5282 (clobber (reg:SI 25))
5283 (clobber (match_dup 4))])
5284 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5288 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5289 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5291 rtx scratch = gen_reg_rtx (DImode);
5292 operands[1] = force_reg (SImode, operands[1]);
5293 operands[2] = force_reg (SImode, operands[2]);
5294 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5295 emit_insn (gen_movsi (operands[0],
5296 gen_rtx_SUBREG (SImode, scratch,
5297 GET_MODE_SIZE (SImode))));
5300 operands[3] = gen_reg_rtx (SImode);
5303 (define_insn "umulsidi3"
5304 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5305 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5306 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5307 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5309 [(set_attr "type" "fpmuldbl")
5310 (set_attr "length" "4")])
5313 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5314 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5315 (match_operand:DI 2 "uint32_operand" "f")))]
5316 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5318 [(set_attr "type" "fpmuldbl")
5319 (set_attr "length" "4")])
5322 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5323 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5324 (match_operand:DI 2 "uint32_operand" "f")))]
5325 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5327 [(set_attr "type" "fpmuldbl")
5328 (set_attr "length" "4")])
5331 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5332 (clobber (match_operand:SI 0 "register_operand" "=a"))
5333 (clobber (reg:SI 26))
5334 (clobber (reg:SI 25))
5335 (clobber (reg:SI 31))]
5337 "* return pa_output_mul_insn (0, insn);"
5338 [(set_attr "type" "milli")
5339 (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
5342 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5343 (clobber (match_operand:SI 0 "register_operand" "=a"))
5344 (clobber (reg:SI 26))
5345 (clobber (reg:SI 25))
5346 (clobber (reg:SI 2))]
5348 "* return pa_output_mul_insn (0, insn);"
5349 [(set_attr "type" "milli")
5350 (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
5352 (define_expand "muldi3"
5353 [(set (match_operand:DI 0 "register_operand" "")
5354 (mult:DI (match_operand:DI 1 "register_operand" "")
5355 (match_operand:DI 2 "register_operand" "")))]
5356 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5359 rtx low_product = gen_reg_rtx (DImode);
5360 rtx cross_product1 = gen_reg_rtx (DImode);
5361 rtx cross_product2 = gen_reg_rtx (DImode);
5362 rtx cross_scratch = gen_reg_rtx (DImode);
5363 rtx cross_product = gen_reg_rtx (DImode);
5364 rtx op1l, op1r, op2l, op2r;
5365 rtx op1shifted, op2shifted;
5367 op1shifted = gen_reg_rtx (DImode);
5368 op2shifted = gen_reg_rtx (DImode);
5369 op1l = gen_reg_rtx (SImode);
5370 op1r = gen_reg_rtx (SImode);
5371 op2l = gen_reg_rtx (SImode);
5372 op2r = gen_reg_rtx (SImode);
5374 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5376 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5378 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5379 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5380 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5381 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5383 /* Emit multiplies for the cross products. */
5384 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5385 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5387 /* Emit a multiply for the low sub-word. */
5388 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5390 /* Sum the cross products and shift them into proper position. */
5391 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5392 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5394 /* Add the cross product to the low product and store the result
5395 into the output operand . */
5396 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5400 ;;; Division and mod.
5401 (define_expand "divsi3"
5402 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5403 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5404 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5405 (clobber (match_dup 3))
5406 (clobber (match_dup 4))
5407 (clobber (reg:SI 26))
5408 (clobber (reg:SI 25))
5409 (clobber (match_dup 5))])
5410 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5414 operands[3] = gen_reg_rtx (SImode);
5417 operands[5] = gen_rtx_REG (SImode, 2);
5418 operands[4] = operands[5];
5422 operands[5] = gen_rtx_REG (SImode, 31);
5423 operands[4] = gen_reg_rtx (SImode);
5425 if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 0))
5431 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5432 (clobber (match_operand:SI 1 "register_operand" "=a"))
5433 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5434 (clobber (reg:SI 26))
5435 (clobber (reg:SI 25))
5436 (clobber (reg:SI 31))]
5439 return pa_output_div_insn (operands, 0, insn);"
5440 [(set_attr "type" "milli")
5441 (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
5445 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5446 (clobber (match_operand:SI 1 "register_operand" "=a"))
5447 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5448 (clobber (reg:SI 26))
5449 (clobber (reg:SI 25))
5450 (clobber (reg:SI 2))]
5453 return pa_output_div_insn (operands, 0, insn);"
5454 [(set_attr "type" "milli")
5455 (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
5457 (define_expand "udivsi3"
5458 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5459 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5460 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5461 (clobber (match_dup 3))
5462 (clobber (match_dup 4))
5463 (clobber (reg:SI 26))
5464 (clobber (reg:SI 25))
5465 (clobber (match_dup 5))])
5466 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5470 operands[3] = gen_reg_rtx (SImode);
5474 operands[5] = gen_rtx_REG (SImode, 2);
5475 operands[4] = operands[5];
5479 operands[5] = gen_rtx_REG (SImode, 31);
5480 operands[4] = gen_reg_rtx (SImode);
5482 if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 1))
5488 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5489 (clobber (match_operand:SI 1 "register_operand" "=a"))
5490 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5491 (clobber (reg:SI 26))
5492 (clobber (reg:SI 25))
5493 (clobber (reg:SI 31))]
5496 return pa_output_div_insn (operands, 1, insn);"
5497 [(set_attr "type" "milli")
5498 (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
5502 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5503 (clobber (match_operand:SI 1 "register_operand" "=a"))
5504 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5505 (clobber (reg:SI 26))
5506 (clobber (reg:SI 25))
5507 (clobber (reg:SI 2))]
5510 return pa_output_div_insn (operands, 1, insn);"
5511 [(set_attr "type" "milli")
5512 (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
5514 (define_expand "modsi3"
5515 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5516 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5517 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5518 (clobber (match_dup 3))
5519 (clobber (match_dup 4))
5520 (clobber (reg:SI 26))
5521 (clobber (reg:SI 25))
5522 (clobber (match_dup 5))])
5523 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5529 operands[5] = gen_rtx_REG (SImode, 2);
5530 operands[4] = operands[5];
5534 operands[5] = gen_rtx_REG (SImode, 31);
5535 operands[4] = gen_reg_rtx (SImode);
5537 operands[3] = gen_reg_rtx (SImode);
5541 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5542 (clobber (match_operand:SI 0 "register_operand" "=a"))
5543 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5544 (clobber (reg:SI 26))
5545 (clobber (reg:SI 25))
5546 (clobber (reg:SI 31))]
5549 return pa_output_mod_insn (0, insn);"
5550 [(set_attr "type" "milli")
5551 (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
5554 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5555 (clobber (match_operand:SI 0 "register_operand" "=a"))
5556 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5557 (clobber (reg:SI 26))
5558 (clobber (reg:SI 25))
5559 (clobber (reg:SI 2))]
5562 return pa_output_mod_insn (0, insn);"
5563 [(set_attr "type" "milli")
5564 (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
5566 (define_expand "umodsi3"
5567 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5568 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5569 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5570 (clobber (match_dup 3))
5571 (clobber (match_dup 4))
5572 (clobber (reg:SI 26))
5573 (clobber (reg:SI 25))
5574 (clobber (match_dup 5))])
5575 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5581 operands[5] = gen_rtx_REG (SImode, 2);
5582 operands[4] = operands[5];
5586 operands[5] = gen_rtx_REG (SImode, 31);
5587 operands[4] = gen_reg_rtx (SImode);
5589 operands[3] = gen_reg_rtx (SImode);
5593 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5594 (clobber (match_operand:SI 0 "register_operand" "=a"))
5595 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5596 (clobber (reg:SI 26))
5597 (clobber (reg:SI 25))
5598 (clobber (reg:SI 31))]
5601 return pa_output_mod_insn (1, insn);"
5602 [(set_attr "type" "milli")
5603 (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
5606 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5607 (clobber (match_operand:SI 0 "register_operand" "=a"))
5608 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5609 (clobber (reg:SI 26))
5610 (clobber (reg:SI 25))
5611 (clobber (reg:SI 2))]
5614 return pa_output_mod_insn (1, insn);"
5615 [(set_attr "type" "milli")
5616 (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
5618 ;;- and instructions
5619 ;; We define DImode `and` so with DImode `not` we can get
5620 ;; DImode `andn`. Other combinations are possible.
5622 (define_expand "anddi3"
5623 [(set (match_operand:DI 0 "register_operand" "")
5624 (and:DI (match_operand:DI 1 "register_operand" "")
5625 (match_operand:DI 2 "and_operand" "")))]
5630 [(set (match_operand:DI 0 "register_operand" "=r,r")
5631 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5632 (match_operand:DI 2 "and_operand" "rO,P")))]
5634 "* return pa_output_64bit_and (operands); "
5635 [(set_attr "type" "binary")
5636 (set_attr "length" "4")])
5638 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5639 ; constant with ldil;ldo.
5640 (define_insn "andsi3"
5641 [(set (match_operand:SI 0 "register_operand" "=r,r")
5642 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5643 (match_operand:SI 2 "and_operand" "rO,P")))]
5645 "* return pa_output_and (operands); "
5646 [(set_attr "type" "binary,shift")
5647 (set_attr "length" "4,4")])
5650 [(set (match_operand:DI 0 "register_operand" "=r")
5651 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5652 (match_operand:DI 2 "register_operand" "r")))]
5655 [(set_attr "type" "binary")
5656 (set_attr "length" "4")])
5659 [(set (match_operand:SI 0 "register_operand" "=r")
5660 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5661 (match_operand:SI 2 "register_operand" "r")))]
5664 [(set_attr "type" "binary")
5665 (set_attr "length" "4")])
5667 (define_expand "iordi3"
5668 [(set (match_operand:DI 0 "register_operand" "")
5669 (ior:DI (match_operand:DI 1 "register_operand" "")
5670 (match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
5675 [(set (match_operand:DI 0 "register_operand" "=r,r")
5676 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5677 (match_operand:DI 2 "cint_ior_operand" "M,i")))]
5679 "* return pa_output_64bit_ior (operands); "
5680 [(set_attr "type" "binary,shift")
5681 (set_attr "length" "4,4")])
5684 [(set (match_operand:DI 0 "register_operand" "=r")
5685 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5686 (match_operand:DI 2 "register_operand" "r")))]
5689 [(set_attr "type" "binary")
5690 (set_attr "length" "4")])
5692 ;; Need a define_expand because we've run out of CONST_OK... characters.
5693 (define_expand "iorsi3"
5694 [(set (match_operand:SI 0 "register_operand" "")
5695 (ior:SI (match_operand:SI 1 "register_operand" "")
5696 (match_operand:SI 2 "reg_or_cint_ior_operand" "")))]
5701 [(set (match_operand:SI 0 "register_operand" "=r,r")
5702 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5703 (match_operand:SI 2 "cint_ior_operand" "M,i")))]
5705 "* return pa_output_ior (operands); "
5706 [(set_attr "type" "binary,shift")
5707 (set_attr "length" "4,4")])
5710 [(set (match_operand:SI 0 "register_operand" "=r")
5711 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5712 (match_operand:SI 2 "register_operand" "r")))]
5715 [(set_attr "type" "binary")
5716 (set_attr "length" "4")])
5718 (define_expand "xordi3"
5719 [(set (match_operand:DI 0 "register_operand" "")
5720 (xor:DI (match_operand:DI 1 "register_operand" "")
5721 (match_operand:DI 2 "register_operand" "")))]
5726 [(set (match_operand:DI 0 "register_operand" "=r")
5727 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5728 (match_operand:DI 2 "register_operand" "r")))]
5731 [(set_attr "type" "binary")
5732 (set_attr "length" "4")])
5734 (define_insn "xorsi3"
5735 [(set (match_operand:SI 0 "register_operand" "=r")
5736 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5737 (match_operand:SI 2 "register_operand" "r")))]
5740 [(set_attr "type" "binary")
5741 (set_attr "length" "4")])
5743 (define_expand "negdi2"
5744 [(set (match_operand:DI 0 "register_operand" "")
5745 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5750 [(set (match_operand:DI 0 "register_operand" "=r")
5751 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5753 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5754 [(set_attr "type" "unary")
5755 (set_attr "length" "8")])
5758 [(set (match_operand:DI 0 "register_operand" "=r")
5759 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5762 [(set_attr "type" "unary")
5763 (set_attr "length" "4")])
5765 (define_expand "negvdi2"
5766 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5767 (neg:DI (match_operand:DI 1 "register_operand" "")))
5768 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5769 (sign_extend:TI (neg:DI (match_dup 1))))
5775 [(set (match_operand:DI 0 "register_operand" "=r")
5776 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5777 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5778 (sign_extend:TI (neg:DI (match_dup 1))))
5781 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
5782 [(set_attr "type" "unary")
5783 (set_attr "length" "8")])
5786 [(set (match_operand:DI 0 "register_operand" "=r")
5787 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5788 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5789 (sign_extend:TI (neg:DI (match_dup 1))))
5792 "sub,tsv %%r0,%1,%0"
5793 [(set_attr "type" "unary")
5794 (set_attr "length" "4")])
5796 (define_insn "negsi2"
5797 [(set (match_operand:SI 0 "register_operand" "=r")
5798 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5801 [(set_attr "type" "unary")
5802 (set_attr "length" "4")])
5804 (define_insn "negvsi2"
5805 [(set (match_operand:SI 0 "register_operand" "=r")
5806 (neg:SI (match_operand:SI 1 "register_operand" "r")))
5807 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
5808 (sign_extend:DI (neg:SI (match_dup 1))))
5811 "{subo|sub,tsv} %%r0,%1,%0"
5812 [(set_attr "type" "unary")
5813 (set_attr "length" "4")])
5815 (define_expand "one_cmpldi2"
5816 [(set (match_operand:DI 0 "register_operand" "")
5817 (not:DI (match_operand:DI 1 "register_operand" "")))]
5824 [(set (match_operand:DI 0 "register_operand" "=r")
5825 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5827 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5828 [(set_attr "type" "unary")
5829 (set_attr "length" "8")])
5832 [(set (match_operand:DI 0 "register_operand" "=r")
5833 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5836 [(set_attr "type" "unary")
5837 (set_attr "length" "4")])
5839 (define_insn "one_cmplsi2"
5840 [(set (match_operand:SI 0 "register_operand" "=r")
5841 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5844 [(set_attr "type" "unary")
5845 (set_attr "length" "4")])
5847 ;; Floating point arithmetic instructions.
5849 (define_insn "adddf3"
5850 [(set (match_operand:DF 0 "register_operand" "=f")
5851 (plus:DF (match_operand:DF 1 "register_operand" "f")
5852 (match_operand:DF 2 "register_operand" "f")))]
5853 "! TARGET_SOFT_FLOAT"
5855 [(set_attr "type" "fpalu")
5856 (set_attr "pa_combine_type" "faddsub")
5857 (set_attr "length" "4")])
5859 (define_insn "addsf3"
5860 [(set (match_operand:SF 0 "register_operand" "=f")
5861 (plus:SF (match_operand:SF 1 "register_operand" "f")
5862 (match_operand:SF 2 "register_operand" "f")))]
5863 "! TARGET_SOFT_FLOAT"
5865 [(set_attr "type" "fpalu")
5866 (set_attr "pa_combine_type" "faddsub")
5867 (set_attr "length" "4")])
5869 (define_insn "subdf3"
5870 [(set (match_operand:DF 0 "register_operand" "=f")
5871 (minus:DF (match_operand:DF 1 "register_operand" "f")
5872 (match_operand:DF 2 "register_operand" "f")))]
5873 "! TARGET_SOFT_FLOAT"
5875 [(set_attr "type" "fpalu")
5876 (set_attr "pa_combine_type" "faddsub")
5877 (set_attr "length" "4")])
5879 (define_insn "subsf3"
5880 [(set (match_operand:SF 0 "register_operand" "=f")
5881 (minus:SF (match_operand:SF 1 "register_operand" "f")
5882 (match_operand:SF 2 "register_operand" "f")))]
5883 "! TARGET_SOFT_FLOAT"
5885 [(set_attr "type" "fpalu")
5886 (set_attr "pa_combine_type" "faddsub")
5887 (set_attr "length" "4")])
5889 (define_insn "muldf3"
5890 [(set (match_operand:DF 0 "register_operand" "=f")
5891 (mult:DF (match_operand:DF 1 "register_operand" "f")
5892 (match_operand:DF 2 "register_operand" "f")))]
5893 "! TARGET_SOFT_FLOAT"
5895 [(set_attr "type" "fpmuldbl")
5896 (set_attr "pa_combine_type" "fmpy")
5897 (set_attr "length" "4")])
5899 (define_insn "mulsf3"
5900 [(set (match_operand:SF 0 "register_operand" "=f")
5901 (mult:SF (match_operand:SF 1 "register_operand" "f")
5902 (match_operand:SF 2 "register_operand" "f")))]
5903 "! TARGET_SOFT_FLOAT"
5905 [(set_attr "type" "fpmulsgl")
5906 (set_attr "pa_combine_type" "fmpy")
5907 (set_attr "length" "4")])
5909 (define_insn "divdf3"
5910 [(set (match_operand:DF 0 "register_operand" "=f")
5911 (div:DF (match_operand:DF 1 "register_operand" "f")
5912 (match_operand:DF 2 "register_operand" "f")))]
5913 "! TARGET_SOFT_FLOAT"
5915 [(set_attr "type" "fpdivdbl")
5916 (set_attr "length" "4")])
5918 (define_insn "divsf3"
5919 [(set (match_operand:SF 0 "register_operand" "=f")
5920 (div:SF (match_operand:SF 1 "register_operand" "f")
5921 (match_operand:SF 2 "register_operand" "f")))]
5922 "! TARGET_SOFT_FLOAT"
5924 [(set_attr "type" "fpdivsgl")
5925 (set_attr "length" "4")])
5927 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5928 ;; negation can be done by subtracting from plus zero. However, this
5929 ;; violates the IEEE standard when negating plus and minus zero.
5930 ;; The slow path toggles the sign bit in the general registers.
5931 (define_expand "negdf2"
5932 [(set (match_operand:DF 0 "register_operand" "")
5933 (neg:DF (match_operand:DF 1 "register_operand" "")))]
5934 "!TARGET_SOFT_FLOAT"
5936 if (TARGET_PA_20 || !flag_signed_zeros)
5937 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5939 emit_insn (gen_negdf2_slow (operands[0], operands[1]));
5943 (define_insn "negdf2_slow"
5944 [(set (match_operand:DF 0 "register_operand" "=r")
5945 (neg:DF (match_operand:DF 1 "register_operand" "r")))]
5946 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
5949 if (rtx_equal_p (operands[0], operands[1]))
5950 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\";
5952 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\;copy %R1,%R0\";
5954 [(set_attr "type" "multi")
5955 (set (attr "length")
5956 (if_then_else (match_test "rtx_equal_p (operands[0], operands[1])")
5960 (define_insn "negdf2_fast"
5961 [(set (match_operand:DF 0 "register_operand" "=f")
5962 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5963 "!TARGET_SOFT_FLOAT"
5967 return \"fneg,dbl %1,%0\";
5969 return \"fsub,dbl %%fr0,%1,%0\";
5971 [(set_attr "type" "fpalu")
5972 (set_attr "length" "4")])
5974 (define_expand "negsf2"
5975 [(set (match_operand:SF 0 "register_operand" "")
5976 (neg:SF (match_operand:SF 1 "register_operand" "")))]
5977 "!TARGET_SOFT_FLOAT"
5979 if (TARGET_PA_20 || !flag_signed_zeros)
5980 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
5982 emit_insn (gen_negsf2_slow (operands[0], operands[1]));
5986 (define_insn "negsf2_slow"
5987 [(set (match_operand:SF 0 "register_operand" "=r")
5988 (neg:SF (match_operand:SF 1 "register_operand" "r")))]
5989 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
5990 "and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0"
5991 [(set_attr "type" "multi")
5992 (set_attr "length" "12")])
5994 (define_insn "negsf2_fast"
5995 [(set (match_operand:SF 0 "register_operand" "=f")
5996 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
5997 "!TARGET_SOFT_FLOAT"
6001 return \"fneg,sgl %1,%0\";
6003 return \"fsub,sgl %%fr0,%1,%0\";
6005 [(set_attr "type" "fpalu")
6006 (set_attr "length" "4")])
6008 (define_insn "absdf2"
6009 [(set (match_operand:DF 0 "register_operand" "=f")
6010 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6011 "! TARGET_SOFT_FLOAT"
6013 [(set_attr "type" "fpalu")
6014 (set_attr "length" "4")])
6016 (define_insn "abssf2"
6017 [(set (match_operand:SF 0 "register_operand" "=f")
6018 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6019 "! TARGET_SOFT_FLOAT"
6021 [(set_attr "type" "fpalu")
6022 (set_attr "length" "4")])
6024 (define_insn "sqrtdf2"
6025 [(set (match_operand:DF 0 "register_operand" "=f")
6026 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6027 "! TARGET_SOFT_FLOAT"
6029 [(set_attr "type" "fpsqrtdbl")
6030 (set_attr "length" "4")])
6032 (define_insn "sqrtsf2"
6033 [(set (match_operand:SF 0 "register_operand" "=f")
6034 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6035 "! TARGET_SOFT_FLOAT"
6037 [(set_attr "type" "fpsqrtsgl")
6038 (set_attr "length" "4")])
6040 ;; PA 2.0 floating point instructions
6043 (define_insn "fmadf4"
6044 [(set (match_operand:DF 0 "register_operand" "=f")
6045 (fma:DF (match_operand:DF 1 "register_operand" "f")
6046 (match_operand:DF 2 "register_operand" "f")
6047 (match_operand:DF 3 "register_operand" "f")))]
6048 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6049 "fmpyfadd,dbl %1,%2,%3,%0"
6050 [(set_attr "type" "fpmuldbl")
6051 (set_attr "length" "4")])
6053 (define_insn "fmasf4"
6054 [(set (match_operand:SF 0 "register_operand" "=f")
6055 (fma:SF (match_operand:SF 1 "register_operand" "f")
6056 (match_operand:SF 2 "register_operand" "f")
6057 (match_operand:SF 3 "register_operand" "f")))]
6058 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6059 "fmpyfadd,sgl %1,%2,%3,%0"
6060 [(set_attr "type" "fpmulsgl")
6061 (set_attr "length" "4")])
6063 ; fmpynfadd patterns
6064 (define_insn "fnmadf4"
6065 [(set (match_operand:DF 0 "register_operand" "=f")
6066 (fma:DF (neg:DF (match_operand:DF 1 "register_operand" "f"))
6067 (match_operand:DF 2 "register_operand" "f")
6068 (match_operand:DF 3 "register_operand" "f")))]
6069 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6070 "fmpynfadd,dbl %1,%2,%3,%0"
6071 [(set_attr "type" "fpmuldbl")
6072 (set_attr "length" "4")])
6074 (define_insn "fnmasf4"
6075 [(set (match_operand:SF 0 "register_operand" "=f")
6076 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
6077 (match_operand:SF 2 "register_operand" "f")
6078 (match_operand:SF 3 "register_operand" "f")))]
6079 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6080 "fmpynfadd,sgl %1,%2,%3,%0"
6081 [(set_attr "type" "fpmulsgl")
6082 (set_attr "length" "4")])
6086 [(set (match_operand:DF 0 "register_operand" "=f")
6087 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6088 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6090 [(set_attr "type" "fpalu")
6091 (set_attr "length" "4")])
6094 [(set (match_operand:SF 0 "register_operand" "=f")
6095 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6096 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6098 [(set_attr "type" "fpalu")
6099 (set_attr "length" "4")])
6102 [(set (match_operand:DF 0 "register_operand" "=f")
6103 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6104 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6105 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6106 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6108 [(set_attr "type" "fpalu")
6109 (set_attr "length" "8")])
6112 [(set (match_operand:DF 0 "register_operand" "")
6113 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6114 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6115 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6116 [(set (match_dup 2) (abs:DF (match_dup 1)))
6117 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6121 [(set (match_operand:SF 0 "register_operand" "=f")
6122 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6123 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6124 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6125 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6127 [(set_attr "type" "fpalu")
6128 (set_attr "length" "8")])
6131 [(set (match_operand:SF 0 "register_operand" "")
6132 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6133 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6134 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6135 [(set (match_dup 2) (abs:SF (match_dup 1)))
6136 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6139 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6140 ;; instruction if we can ignore the sign of zero.
6142 [(set (match_operand:DF 0 "register_operand" "=f")
6143 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6144 (match_operand:DF 2 "register_operand" "f"))))]
6145 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6146 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6147 [(set_attr "type" "fpmuldbl")
6148 (set_attr "length" "4")])
6151 [(set (match_operand:SF 0 "register_operand" "=f")
6152 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6153 (match_operand:SF 2 "register_operand" "f"))))]
6154 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6155 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6156 [(set_attr "type" "fpmuldbl")
6157 (set_attr "length" "4")])
6160 [(set (match_operand:DF 0 "register_operand" "=f")
6161 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6162 (match_operand:DF 2 "register_operand" "f"))))
6163 (set (match_operand:DF 3 "register_operand" "=&f")
6164 (mult:DF (match_dup 1) (match_dup 2)))]
6165 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6166 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6167 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6169 [(set_attr "type" "fpmuldbl")
6170 (set_attr "length" "8")])
6173 [(set (match_operand:DF 0 "register_operand" "")
6174 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6175 (match_operand:DF 2 "register_operand" ""))))
6176 (set (match_operand:DF 3 "register_operand" "")
6177 (mult:DF (match_dup 1) (match_dup 2)))]
6178 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6179 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6180 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6184 [(set (match_operand:SF 0 "register_operand" "=f")
6185 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6186 (match_operand:SF 2 "register_operand" "f"))))
6187 (set (match_operand:SF 3 "register_operand" "=&f")
6188 (mult:SF (match_dup 1) (match_dup 2)))]
6189 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6190 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6191 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6193 [(set_attr "type" "fpmuldbl")
6194 (set_attr "length" "8")])
6197 [(set (match_operand:SF 0 "register_operand" "")
6198 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6199 (match_operand:SF 2 "register_operand" ""))))
6200 (set (match_operand:SF 3 "register_operand" "")
6201 (mult:SF (match_dup 1) (match_dup 2)))]
6202 "!TARGET_SOFT_FLOAT && TARGET_PA_20&& !flag_signed_zeros"
6203 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6204 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6207 ;;- Shift instructions
6209 ;; Optimized special case of shifting.
6212 [(set (match_operand:SI 0 "register_operand" "=r")
6213 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6217 [(set_attr "type" "load")
6218 (set_attr "length" "4")])
6221 [(set (match_operand:SI 0 "register_operand" "=r")
6222 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6226 [(set_attr "type" "load")
6227 (set_attr "length" "4")])
6230 [(set (match_operand:SI 0 "register_operand" "=r")
6231 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6232 (match_operand:SI 3 "shadd_operand" ""))
6233 (match_operand:SI 1 "register_operand" "r")))]
6235 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6236 [(set_attr "type" "binary")
6237 (set_attr "length" "4")])
6240 [(set (match_operand:DI 0 "register_operand" "=r")
6241 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6242 (match_operand:DI 3 "shadd_operand" ""))
6243 (match_operand:DI 1 "register_operand" "r")))]
6245 "shladd,l %2,%O3,%1,%0"
6246 [(set_attr "type" "binary")
6247 (set_attr "length" "4")])
6249 (define_expand "ashlsi3"
6250 [(set (match_operand:SI 0 "register_operand" "")
6251 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6252 (match_operand:SI 2 "arith32_operand" "")))]
6256 if (GET_CODE (operands[2]) != CONST_INT)
6258 rtx temp = gen_reg_rtx (SImode);
6259 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6260 if (GET_CODE (operands[1]) == CONST_INT)
6261 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6263 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6266 /* Make sure both inputs are not constants,
6267 there are no patterns for that. */
6268 operands[1] = force_reg (SImode, operands[1]);
6272 [(set (match_operand:SI 0 "register_operand" "=r")
6273 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6274 (match_operand:SI 2 "const_int_operand" "n")))]
6276 "{zdep|depw,z} %1,%P2,%L2,%0"
6277 [(set_attr "type" "shift")
6278 (set_attr "length" "4")])
6280 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6281 ; Doing it like this makes slightly better code since reload can
6282 ; replace a register with a known value in range -16..15 with a
6283 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6284 ; but since we have no more CONST_OK... characters, that is not
6286 (define_insn "zvdep32"
6287 [(set (match_operand:SI 0 "register_operand" "=r,r")
6288 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6289 (minus:SI (const_int 31)
6290 (match_operand:SI 2 "register_operand" "q,q"))))]
6293 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6294 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6295 [(set_attr "type" "shift,shift")
6296 (set_attr "length" "4,4")])
6298 (define_insn "zvdep_imm32"
6299 [(set (match_operand:SI 0 "register_operand" "=r")
6300 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6301 (minus:SI (const_int 31)
6302 (match_operand:SI 2 "register_operand" "q"))))]
6306 unsigned HOST_WIDE_INT x = UINTVAL (operands[1]);
6307 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6308 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6309 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6311 [(set_attr "type" "shift")
6312 (set_attr "length" "4")])
6314 (define_insn "vdepi_ior"
6315 [(set (match_operand:SI 0 "register_operand" "=r")
6316 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6317 (minus:SI (const_int 31)
6318 (match_operand:SI 2 "register_operand" "q")))
6319 (match_operand:SI 3 "register_operand" "0")))]
6320 ; accept ...0001...1, can this be generalized?
6321 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
6324 HOST_WIDE_INT x = INTVAL (operands[1]);
6325 operands[2] = GEN_INT (exact_log2 (x + 1));
6326 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6328 [(set_attr "type" "shift")
6329 (set_attr "length" "4")])
6331 (define_insn "vdepi_and"
6332 [(set (match_operand:SI 0 "register_operand" "=r")
6333 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6334 (minus:SI (const_int 31)
6335 (match_operand:SI 2 "register_operand" "q")))
6336 (match_operand:SI 3 "register_operand" "0")))]
6337 ; this can be generalized...!
6338 "INTVAL (operands[1]) == -2"
6341 HOST_WIDE_INT x = INTVAL (operands[1]);
6342 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6343 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6345 [(set_attr "type" "shift")
6346 (set_attr "length" "4")])
6348 (define_expand "ashldi3"
6349 [(set (match_operand:DI 0 "register_operand" "")
6350 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6351 (match_operand:DI 2 "arith32_operand" "")))]
6355 if (GET_CODE (operands[2]) != CONST_INT)
6357 rtx temp = gen_reg_rtx (DImode);
6358 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6359 if (GET_CODE (operands[1]) == CONST_INT)
6360 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6362 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6365 /* Make sure both inputs are not constants,
6366 there are no patterns for that. */
6367 operands[1] = force_reg (DImode, operands[1]);
6371 [(set (match_operand:DI 0 "register_operand" "=r")
6372 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6373 (match_operand:DI 2 "const_int_operand" "n")))]
6375 "depd,z %1,%p2,%Q2,%0"
6376 [(set_attr "type" "shift")
6377 (set_attr "length" "4")])
6379 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6380 ; Doing it like this makes slightly better code since reload can
6381 ; replace a register with a known value in range -16..15 with a
6382 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6383 ; but since we have no more CONST_OK... characters, that is not
6385 (define_insn "zvdep64"
6386 [(set (match_operand:DI 0 "register_operand" "=r,r")
6387 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6388 (minus:DI (const_int 63)
6389 (match_operand:DI 2 "register_operand" "q,q"))))]
6392 depd,z %1,%%sar,64,%0
6393 depdi,z %1,%%sar,64,%0"
6394 [(set_attr "type" "shift,shift")
6395 (set_attr "length" "4,4")])
6397 (define_insn "zvdep_imm64"
6398 [(set (match_operand:DI 0 "register_operand" "=r")
6399 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6400 (minus:DI (const_int 63)
6401 (match_operand:DI 2 "register_operand" "q"))))]
6405 unsigned HOST_WIDE_INT x = UINTVAL (operands[1]);
6406 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6407 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6408 return \"depdi,z %1,%%sar,%2,%0\";
6410 [(set_attr "type" "shift")
6411 (set_attr "length" "4")])
6414 [(set (match_operand:DI 0 "register_operand" "=r")
6415 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6416 (minus:DI (const_int 63)
6417 (match_operand:DI 2 "register_operand" "q")))
6418 (match_operand:DI 3 "register_operand" "0")))]
6419 ; accept ...0001...1, can this be generalized?
6420 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
6423 HOST_WIDE_INT x = INTVAL (operands[1]);
6424 operands[2] = GEN_INT (exact_log2 (x + 1));
6425 return \"depdi -1,%%sar,%2,%0\";
6427 [(set_attr "type" "shift")
6428 (set_attr "length" "4")])
6431 [(set (match_operand:DI 0 "register_operand" "=r")
6432 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6433 (minus:DI (const_int 63)
6434 (match_operand:DI 2 "register_operand" "q")))
6435 (match_operand:DI 3 "register_operand" "0")))]
6436 ; this can be generalized...!
6437 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6440 HOST_WIDE_INT x = INTVAL (operands[1]);
6441 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6442 return \"depdi 0,%%sar,%2,%0\";
6444 [(set_attr "type" "shift")
6445 (set_attr "length" "4")])
6447 (define_expand "ashrsi3"
6448 [(set (match_operand:SI 0 "register_operand" "")
6449 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6450 (match_operand:SI 2 "arith32_operand" "")))]
6454 if (GET_CODE (operands[2]) != CONST_INT)
6456 rtx temp = gen_reg_rtx (SImode);
6457 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6458 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6464 [(set (match_operand:SI 0 "register_operand" "=r")
6465 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6466 (match_operand:SI 2 "const_int_operand" "n")))]
6468 "{extrs|extrw,s} %1,%P2,%L2,%0"
6469 [(set_attr "type" "shift")
6470 (set_attr "length" "4")])
6472 (define_insn "vextrs32"
6473 [(set (match_operand:SI 0 "register_operand" "=r")
6474 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6475 (minus:SI (const_int 31)
6476 (match_operand:SI 2 "register_operand" "q"))))]
6478 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6479 [(set_attr "type" "shift")
6480 (set_attr "length" "4")])
6482 (define_expand "ashrdi3"
6483 [(set (match_operand:DI 0 "register_operand" "")
6484 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6485 (match_operand:DI 2 "arith32_operand" "")))]
6489 if (GET_CODE (operands[2]) != CONST_INT)
6491 rtx temp = gen_reg_rtx (DImode);
6492 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6493 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6499 [(set (match_operand:DI 0 "register_operand" "=r")
6500 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6501 (match_operand:DI 2 "const_int_operand" "n")))]
6503 "extrd,s %1,%p2,%Q2,%0"
6504 [(set_attr "type" "shift")
6505 (set_attr "length" "4")])
6507 (define_insn "vextrs64"
6508 [(set (match_operand:DI 0 "register_operand" "=r")
6509 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6510 (minus:DI (const_int 63)
6511 (match_operand:DI 2 "register_operand" "q"))))]
6513 "extrd,s %1,%%sar,64,%0"
6514 [(set_attr "type" "shift")
6515 (set_attr "length" "4")])
6517 (define_insn "lshrsi3"
6518 [(set (match_operand:SI 0 "register_operand" "=r,r")
6519 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6520 (match_operand:SI 2 "arith32_operand" "q,n")))]
6523 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6524 {extru|extrw,u} %1,%P2,%L2,%0"
6525 [(set_attr "type" "shift")
6526 (set_attr "length" "4")])
6528 (define_insn "lshrdi3"
6529 [(set (match_operand:DI 0 "register_operand" "=r,r")
6530 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6531 (match_operand:DI 2 "arith32_operand" "q,n")))]
6534 shrpd %%r0,%1,%%sar,%0
6535 extrd,u %1,%p2,%Q2,%0"
6536 [(set_attr "type" "shift")
6537 (set_attr "length" "4")])
6539 (define_insn "rotrsi3"
6540 [(set (match_operand:SI 0 "register_operand" "=r,r")
6541 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6542 (match_operand:SI 2 "arith32_operand" "q,n")))]
6546 if (GET_CODE (operands[2]) == CONST_INT)
6548 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6549 return \"{shd|shrpw} %1,%1,%2,%0\";
6552 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6554 [(set_attr "type" "shift")
6555 (set_attr "length" "4")])
6557 (define_expand "rotlsi3"
6558 [(set (match_operand:SI 0 "register_operand" "")
6559 (rotate:SI (match_operand:SI 1 "register_operand" "")
6560 (match_operand:SI 2 "arith32_operand" "")))]
6564 if (GET_CODE (operands[2]) != CONST_INT)
6566 rtx temp = gen_reg_rtx (SImode);
6567 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6568 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6571 /* Else expand normally. */
6575 [(set (match_operand:SI 0 "register_operand" "=r")
6576 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6577 (match_operand:SI 2 "const_int_operand" "n")))]
6581 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6582 return \"{shd|shrpw} %1,%1,%2,%0\";
6584 [(set_attr "type" "shift")
6585 (set_attr "length" "4")])
6588 [(set (match_operand:SI 0 "register_operand" "=r")
6589 (match_operator:SI 5 "plus_xor_ior_operator"
6590 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6591 (match_operand:SI 3 "const_int_operand" "n"))
6592 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6593 (match_operand:SI 4 "const_int_operand" "n"))]))]
6594 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6595 "{shd|shrpw} %1,%2,%4,%0"
6596 [(set_attr "type" "shift")
6597 (set_attr "length" "4")])
6600 [(set (match_operand:SI 0 "register_operand" "=r")
6601 (match_operator:SI 5 "plus_xor_ior_operator"
6602 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6603 (match_operand:SI 4 "const_int_operand" "n"))
6604 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6605 (match_operand:SI 3 "const_int_operand" "n"))]))]
6606 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6607 "{shd|shrpw} %1,%2,%4,%0"
6608 [(set_attr "type" "shift")
6609 (set_attr "length" "4")])
6612 [(set (match_operand:SI 0 "register_operand" "=r")
6613 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6614 (match_operand:SI 2 "const_int_operand" ""))
6615 (match_operand:SI 3 "const_int_operand" "")))]
6616 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
6619 int cnt = INTVAL (operands[2]) & 31;
6620 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6621 operands[2] = GEN_INT (31 - cnt);
6622 return \"{zdep|depw,z} %1,%2,%3,%0\";
6624 [(set_attr "type" "shift")
6625 (set_attr "length" "4")])
6627 ;; Unconditional and other jump instructions.
6629 ;; Trivial return used when no epilogue is needed.
6630 (define_insn "return"
6633 "pa_can_use_return_insn ()"
6637 return \"bve%* (%%r2)\";
6638 return \"bv%* %%r0(%%r2)\";
6640 [(set_attr "type" "branch")
6641 (set_attr "length" "4")])
6643 ;; This is used for most returns.
6644 (define_insn "return_internal"
6651 return \"bve%* (%%r2)\";
6652 return \"bv%* %%r0(%%r2)\";
6654 [(set_attr "type" "branch")
6655 (set_attr "length" "4")])
6657 ;; This is used for eh returns which bypass the return stub.
6658 (define_insn "return_external_pic"
6660 (clobber (reg:SI 1))
6662 "!TARGET_NO_SPACE_REGS
6664 && flag_pic && crtl->calls_eh_return"
6665 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6666 [(set_attr "type" "branch")
6667 (set_attr "length" "12")])
6669 (define_expand "prologue"
6672 "pa_expand_prologue ();DONE;")
6674 (define_expand "sibcall_epilogue"
6679 pa_expand_epilogue ();
6683 (define_expand "epilogue"
6690 /* Try to use the trivial return first. Else use the full epilogue. */
6691 if (pa_can_use_return_insn ())
6695 pa_expand_epilogue ();
6697 /* EH returns bypass the normal return stub. Thus, we must do an
6698 interspace branch to return from functions that call eh_return.
6699 This is only a problem for returns from shared code on ports
6700 using space registers. */
6701 if (!TARGET_NO_SPACE_REGS
6703 && flag_pic && crtl->calls_eh_return)
6704 x = gen_return_external_pic ();
6706 x = gen_return_internal ();
6712 ; Used by hppa_profile_hook to load the starting address of the current
6713 ; function; operand 1 contains the address of the label in operand 3
6714 (define_insn "load_offset_label_address"
6715 [(set (match_operand:SI 0 "register_operand" "=r")
6716 (plus:SI (match_operand:SI 1 "register_operand" "r")
6717 (minus:SI (match_operand:SI 2 "" "")
6718 (label_ref:SI (match_operand 3 "" "")))))]
6721 [(set_attr "type" "multi")
6722 (set_attr "length" "4")])
6724 ; Output a code label and load its address.
6725 (define_insn "lcla1"
6726 [(set (match_operand:SI 0 "register_operand" "=r")
6727 (label_ref:SI (match_operand 1 "" "")))
6732 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6733 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6734 CODE_LABEL_NUMBER (operands[1]));
6737 [(set_attr "type" "multi")
6738 (set_attr "length" "8")])
6740 (define_insn "lcla2"
6741 [(set (match_operand:SI 0 "register_operand" "=r")
6742 (label_ref:SI (match_operand 1 "" "")))
6747 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6748 CODE_LABEL_NUMBER (operands[1]));
6751 [(set_attr "type" "move")
6752 (set_attr "length" "4")])
6754 (define_insn "blockage"
6755 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
6758 [(set_attr "length" "0")])
6761 [(set (pc) (label_ref (match_operand 0 "" "")))]
6765 /* An unconditional branch which can reach its target. */
6766 if (get_attr_length (insn) < 16)
6769 return pa_output_lbranch (operands[0], insn, 1);
6771 [(set_attr "type" "uncond_branch")
6772 (set_attr "pa_combine_type" "uncond_branch")
6773 (set (attr "length")
6774 (cond [(match_test "pa_jump_in_call_delay (insn)")
6775 (if_then_else (lt (abs (minus (match_dup 0)
6776 (plus (pc) (const_int 8))))
6777 (const_int MAX_12BIT_OFFSET))
6780 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6781 (const_int MAX_17BIT_OFFSET))
6783 (match_test "TARGET_PORTABLE_RUNTIME")
6785 (not (match_test "flag_pic"))
6789 ;;; Hope this is only within a function...
6790 (define_insn "indirect_jump"
6791 [(set (pc) (match_operand 0 "register_operand" "r"))]
6792 "GET_MODE (operands[0]) == word_mode"
6794 [(set_attr "type" "branch")
6795 (set_attr "length" "4")])
6797 ;;; An indirect jump can be optimized to a direct jump. GAS for the
6798 ;;; SOM target doesn't allow branching to a label inside a function.
6799 ;;; We also don't correctly compute branch distances for labels
6800 ;;; outside the current function. Thus, we use an indirect jump can't
6801 ;;; be optimized to a direct jump for all targets. We assume that
6802 ;;; the branch target is in the same space (i.e., nested function
6803 ;;; jumping to a label in an outer function in the same translation
6805 (define_expand "nonlocal_goto"
6806 [(use (match_operand 0 "general_operand" ""))
6807 (use (match_operand 1 "general_operand" ""))
6808 (use (match_operand 2 "general_operand" ""))
6809 (use (match_operand 3 "general_operand" ""))]
6812 rtx lab = operands[1];
6813 rtx stack = operands[2];
6814 rtx fp = operands[3];
6816 lab = copy_to_reg (lab);
6818 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
6819 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
6821 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
6822 instead of the hard_frame_pointer_rtx in the save area. As a
6823 result, an extra instruction is needed to adjust for the offset
6824 of the virtual stack variables and the hard frame pointer. */
6825 if (GET_CODE (fp) != REG)
6826 fp = force_reg (Pmode, fp);
6827 emit_move_insn (hard_frame_pointer_rtx, plus_constant (Pmode, fp, -8));
6829 emit_stack_restore (SAVE_NONLOCAL, stack);
6831 emit_use (hard_frame_pointer_rtx);
6832 emit_use (stack_pointer_rtx);
6834 /* Nonlocal goto jumps are only used between functions in the same
6835 translation unit. Thus, we can avoid the extra overhead of an
6837 emit_jump_insn (gen_indirect_goto (lab));
6842 (define_insn "indirect_goto"
6843 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
6844 "GET_MODE (operands[0]) == word_mode"
6846 [(set_attr "type" "branch")
6847 (set_attr "length" "4")])
6849 ;;; This jump is used in branch tables where the insn length is fixed.
6850 ;;; The length of this insn is adjusted if the delay slot is not filled.
6851 (define_insn "short_jump"
6852 [(set (pc) (label_ref (match_operand 0 "" "")))
6856 [(set_attr "type" "btable_branch")
6857 (set_attr "length" "4")])
6859 ;; Subroutines of "casesi".
6860 ;; operand 0 is index
6861 ;; operand 1 is the minimum bound
6862 ;; operand 2 is the maximum bound - minimum bound + 1
6863 ;; operand 3 is CODE_LABEL for the table;
6864 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6866 (define_expand "casesi"
6867 [(match_operand:SI 0 "general_operand" "")
6868 (match_operand:SI 1 "const_int_operand" "")
6869 (match_operand:SI 2 "const_int_operand" "")
6870 (match_operand 3 "" "")
6871 (match_operand 4 "" "")]
6875 if (GET_CODE (operands[0]) != REG)
6876 operands[0] = force_reg (SImode, operands[0]);
6878 if (operands[1] != const0_rtx)
6880 rtx index = gen_reg_rtx (SImode);
6882 operands[1] = gen_int_mode (-INTVAL (operands[1]), SImode);
6883 if (!INT_14_BITS (operands[1]))
6884 operands[1] = force_reg (SImode, operands[1]);
6885 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6886 operands[0] = index;
6889 if (!INT_5_BITS (operands[2]))
6890 operands[2] = force_reg (SImode, operands[2]);
6892 /* This branch prevents us finding an insn for the delay slot of the
6893 following vectored branch. It might be possible to use the delay
6894 slot if an index value of -1 was used to transfer to the out-of-range
6895 label. In order to do this, we would have to output the -1 vector
6896 element after the delay insn. The casesi output code would have to
6897 check if the casesi insn is in a delay branch sequence and output
6898 the delay insn if one is found. If this was done, then it might
6899 then be worthwhile to split the casesi patterns to improve scheduling.
6900 However, it's not clear that all this extra complexity is worth
6903 rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
6904 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
6907 /* In 64bit mode we must make sure to wipe the upper bits of the register
6908 just in case the addition overflowed or we had random bits in the
6909 high part of the register. */
6912 rtx index = gen_reg_rtx (DImode);
6914 emit_insn (gen_extendsidi2 (index, operands[0]));
6915 operands[0] = index;
6918 if (TARGET_BIG_SWITCH)
6921 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
6923 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
6925 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
6928 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
6932 ;;; The rtl for this pattern doesn't accurately describe what the insn
6933 ;;; actually does, particularly when case-vector elements are exploded
6934 ;;; in pa_reorg. However, the initial SET in these patterns must show
6935 ;;; the connection of the insn to the following jump table.
6936 (define_insn "casesi0"
6937 [(set (pc) (mem:SI (plus:SI
6938 (mult:SI (match_operand:SI 0 "register_operand" "r")
6940 (label_ref (match_operand 1 "" "")))))]
6942 "blr,n %0,%%r0\;nop"
6943 [(set_attr "type" "multi")
6944 (set_attr "length" "8")])
6946 ;;; 32-bit code, absolute branch table.
6947 (define_insn "casesi32"
6948 [(set (pc) (mem:SI (plus:SI
6949 (mult:SI (match_operand:SI 0 "register_operand" "r")
6951 (label_ref (match_operand 1 "" "")))))
6952 (clobber (match_scratch:SI 2 "=&r"))]
6954 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
6955 [(set_attr "type" "multi")
6956 (set_attr "length" "16")])
6958 ;;; 32-bit code, relative branch table.
6959 (define_insn "casesi32p"
6960 [(set (pc) (mem:SI (plus:SI
6961 (mult:SI (match_operand:SI 0 "register_operand" "r")
6963 (label_ref (match_operand 1 "" "")))))
6964 (clobber (match_scratch:SI 2 "=&r"))
6965 (clobber (match_scratch:SI 3 "=&r"))]
6967 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {%l1-.|%l1+4-.}(%2),%2\;\
6968 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
6969 [(set_attr "type" "multi")
6970 (set (attr "length")
6971 (if_then_else (match_test "TARGET_PA_20")
6975 ;;; 64-bit code, 32-bit relative branch table.
6976 (define_insn "casesi64p"
6977 [(set (pc) (mem:DI (plus:DI
6978 (mult:DI (match_operand:DI 0 "register_operand" "r")
6980 (label_ref (match_operand 1 "" "")))))
6981 (clobber (match_scratch:DI 2 "=&r"))
6982 (clobber (match_scratch:DI 3 "=&r"))]
6984 "mfia %2\;ldo %l1+4-.(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
6985 add,l %2,%3,%3\;bv,n %%r0(%3)"
6986 [(set_attr "type" "multi")
6987 (set_attr "length" "24")])
6991 ;;- jump to subroutine
6993 (define_expand "call"
6994 [(parallel [(call (match_operand:SI 0 "" "")
6995 (match_operand 1 "" ""))
6996 (clobber (reg:SI 2))])]
7001 rtx nb = operands[1];
7003 if (TARGET_PORTABLE_RUNTIME)
7004 op = force_reg (SImode, XEXP (operands[0], 0));
7006 op = XEXP (operands[0], 0);
7010 if (!virtuals_instantiated)
7011 emit_move_insn (arg_pointer_rtx,
7012 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7016 /* The loop pass can generate new libcalls after the virtual
7017 registers are instantiated when fpregs are disabled because
7018 the only method that we have for doing DImode multiplication
7019 is with a libcall. This could be trouble if we haven't
7020 allocated enough space for the outgoing arguments. */
7021 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7023 emit_move_insn (arg_pointer_rtx,
7024 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7025 GEN_INT (STACK_POINTER_OFFSET + 64)));
7029 /* Use two different patterns for calls to explicitly named functions
7030 and calls through function pointers. This is necessary as these two
7031 types of calls use different calling conventions, and CSE might try
7032 to change the named call into an indirect call in some cases (using
7033 two patterns keeps CSE from performing this optimization).
7035 We now use even more call patterns as there was a subtle bug in
7036 attempting to restore the pic register after a call using a simple
7037 move insn. During reload, a instruction involving a pseudo register
7038 with no explicit dependence on the PIC register can be converted
7039 to an equivalent load from memory using the PIC register. If we
7040 emit a simple move to restore the PIC register in the initial rtl
7041 generation, then it can potentially be repositioned during scheduling.
7042 and an instruction that eventually uses the PIC register may end up
7043 between the call and the PIC register restore.
7045 This only worked because there is a post call group of instructions
7046 that are scheduled with the call. These instructions are included
7047 in the same basic block as the call. However, calls can throw in
7048 C++ code and a basic block has to terminate at the call if the call
7049 can throw. This results in the PIC register restore being scheduled
7050 independently from the call. So, we now hide the save and restore
7051 of the PIC register in the call pattern until after reload. Then,
7052 we split the moves out. A small side benefit is that we now don't
7053 need to have a use of the PIC register in the return pattern and
7054 the final save/restore operation is not needed.
7056 I elected to just use register %r4 in the PIC patterns instead
7057 of trying to force hppa_pic_save_rtx () to a callee saved register.
7058 This might have required a new register class and constraint. It
7059 was also simpler to just handle the restore from a register than a
7063 rtx r4 = gen_rtx_REG (word_mode, 4);
7064 if (GET_CODE (op) == SYMBOL_REF)
7065 emit_call_insn (gen_call_symref_64bit (op, nb, r4));
7068 op = force_reg (word_mode, op);
7069 emit_call_insn (gen_call_reg_64bit (op, nb, r4));
7074 if (GET_CODE (op) == SYMBOL_REF)
7078 rtx r4 = gen_rtx_REG (word_mode, 4);
7079 emit_call_insn (gen_call_symref_pic (op, nb, r4));
7082 emit_call_insn (gen_call_symref (op, nb));
7086 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7087 emit_move_insn (tmpreg, force_reg (word_mode, op));
7090 rtx r4 = gen_rtx_REG (word_mode, 4);
7091 emit_call_insn (gen_call_reg_pic (nb, r4));
7094 emit_call_insn (gen_call_reg (nb));
7101 ;; We use function calls to set the attribute length of calls and millicode
7102 ;; calls. This is necessary because of the large variety of call sequences.
7103 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7104 ;; we need the same calculation in several places, maintenance becomes a
7107 ;; However, this has a subtle impact on branch shortening. When the
7108 ;; expression used to set the length attribute of an instruction depends
7109 ;; on a relative address (e.g., pc or a branch address), genattrtab
7110 ;; notes that the insn's length is variable, and attempts to determine a
7111 ;; worst-case default length and code to compute an insn's current length.
7113 ;; The use of a function call hides the variable dependence of our calls
7114 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7115 ;; as variable and it only generates code for the default case using our
7116 ;; function call. Because of this, calls and millicode calls have a fixed
7117 ;; length in the branch shortening pass, and some branches will use a longer
7118 ;; code sequence than necessary. However, the length of any given call
7119 ;; will still reflect its final code location and it may be shorter than
7120 ;; the initial length estimate.
7122 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7123 ;; in the set. However, when genattrtab hits a function call in its attempt
7124 ;; to compute the default length, it marks the result as unknown and sets
7125 ;; the default result to MAX_INT ;-( One possible fix that would allow
7126 ;; calls to participate in branch shortening would be to make the call to
7127 ;; insn_default_length a target option. Then, we could massage unknown
7128 ;; results. Another fix might be to change genattrtab so that it just does
7129 ;; the call in the variable case as it already does for the fixed case.
7131 (define_insn "call_symref"
7132 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7133 (match_operand 1 "" "i"))
7134 (clobber (reg:SI 1))
7135 (clobber (reg:SI 2))
7136 (use (const_int 0))]
7137 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7140 pa_output_arg_descriptor (insn);
7141 return pa_output_call (insn, operands[0], 0);
7143 [(set_attr "type" "call")
7144 (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
7146 (define_insn "call_symref_pic"
7147 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7148 (match_operand 1 "" "i"))
7149 (clobber (reg:SI 1))
7150 (clobber (reg:SI 2))
7151 (clobber (match_operand 2))
7153 (use (const_int 0))]
7154 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7157 ;; Split out the PIC register save and restore after reload. As the
7158 ;; split is done after reload, there are some situations in which we
7159 ;; unnecessarily save and restore %r4. This happens when there is a
7160 ;; single call and the PIC register is not used after the call.
7162 ;; The split has to be done since call_from_call_insn () can't handle
7163 ;; the pattern as is. Noreturn calls are special because they have to
7164 ;; terminate the basic block. The split has to contain more than one
7167 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7168 (match_operand 1 "" ""))
7169 (clobber (reg:SI 1))
7170 (clobber (reg:SI 2))
7171 (clobber (match_operand 2))
7173 (use (const_int 0))])]
7174 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7175 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7176 [(set (match_dup 2) (reg:SI 19))
7177 (parallel [(call (mem:SI (match_dup 0))
7179 (clobber (reg:SI 1))
7180 (clobber (reg:SI 2))
7182 (use (const_int 0))])]
7186 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7187 (match_operand 1 "" ""))
7188 (clobber (reg:SI 1))
7189 (clobber (reg:SI 2))
7190 (clobber (match_operand 2))
7192 (use (const_int 0))])]
7193 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7194 [(set (match_dup 2) (reg:SI 19))
7195 (parallel [(call (mem:SI (match_dup 0))
7197 (clobber (reg:SI 1))
7198 (clobber (reg:SI 2))
7200 (use (const_int 0))])
7201 (set (reg:SI 19) (match_dup 2))]
7204 (define_insn "*call_symref_pic_post_reload"
7205 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7206 (match_operand 1 "" "i"))
7207 (clobber (reg:SI 1))
7208 (clobber (reg:SI 2))
7210 (use (const_int 0))]
7211 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7214 pa_output_arg_descriptor (insn);
7215 return pa_output_call (insn, operands[0], 0);
7217 [(set_attr "type" "call")
7218 (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
7220 ;; This pattern is split if it is necessary to save and restore the
7222 (define_insn "call_symref_64bit"
7223 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7224 (match_operand 1 "" "i"))
7225 (clobber (reg:DI 1))
7226 (clobber (reg:DI 2))
7227 (clobber (match_operand 2))
7230 (use (const_int 0))]
7234 ;; Split out the PIC register save and restore after reload. As the
7235 ;; split is done after reload, there are some situations in which we
7236 ;; unnecessarily save and restore %r4. This happens when there is a
7237 ;; single call and the PIC register is not used after the call.
7239 ;; The split has to be done since call_from_call_insn () can't handle
7240 ;; the pattern as is. Noreturn calls are special because they have to
7241 ;; terminate the basic block. The split has to contain more than one
7244 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7245 (match_operand 1 "" ""))
7246 (clobber (reg:DI 1))
7247 (clobber (reg:DI 2))
7248 (clobber (match_operand 2))
7251 (use (const_int 0))])]
7252 "TARGET_64BIT && reload_completed
7253 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7254 [(set (match_dup 2) (reg:DI 27))
7255 (parallel [(call (mem:SI (match_dup 0))
7257 (clobber (reg:DI 1))
7258 (clobber (reg:DI 2))
7261 (use (const_int 0))])]
7265 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7266 (match_operand 1 "" ""))
7267 (clobber (reg:DI 1))
7268 (clobber (reg:DI 2))
7269 (clobber (match_operand 2))
7272 (use (const_int 0))])]
7273 "TARGET_64BIT && reload_completed"
7274 [(set (match_dup 2) (reg:DI 27))
7275 (parallel [(call (mem:SI (match_dup 0))
7277 (clobber (reg:DI 1))
7278 (clobber (reg:DI 2))
7281 (use (const_int 0))])
7282 (set (reg:DI 27) (match_dup 2))]
7285 (define_insn "*call_symref_64bit_post_reload"
7286 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7287 (match_operand 1 "" "i"))
7288 (clobber (reg:DI 1))
7289 (clobber (reg:DI 2))
7292 (use (const_int 0))]
7296 pa_output_arg_descriptor (insn);
7297 return pa_output_call (insn, operands[0], 0);
7299 [(set_attr "type" "call")
7300 (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
7302 (define_insn "call_reg"
7303 [(call (mem:SI (reg:SI 22))
7304 (match_operand 0 "" "i"))
7305 (clobber (reg:SI 1))
7306 (clobber (reg:SI 2))
7307 (use (const_int 1))]
7311 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7313 [(set_attr "type" "dyncall")
7314 (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
7316 ;; This pattern is split if it is necessary to save and restore the
7318 (define_insn "call_reg_pic"
7319 [(call (mem:SI (reg:SI 22))
7320 (match_operand 0 "" "i"))
7321 (clobber (reg:SI 1))
7322 (clobber (reg:SI 2))
7323 (clobber (match_operand 1))
7325 (use (const_int 1))]
7329 ;; Split out the PIC register save and restore after reload. As the
7330 ;; split is done after reload, there are some situations in which we
7331 ;; unnecessarily save and restore %r4. This happens when there is a
7332 ;; single call and the PIC register is not used after the call.
7334 ;; The split has to be done since call_from_call_insn () can't handle
7335 ;; the pattern as is. Noreturn calls are special because they have to
7336 ;; terminate the basic block. The split has to contain more than one
7339 [(parallel [(call (mem:SI (reg:SI 22))
7340 (match_operand 0 "" ""))
7341 (clobber (reg:SI 1))
7342 (clobber (reg:SI 2))
7343 (clobber (match_operand 1))
7345 (use (const_int 1))])]
7346 "!TARGET_64BIT && reload_completed
7347 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7348 [(set (match_dup 1) (reg:SI 19))
7349 (parallel [(call (mem:SI (reg:SI 22))
7351 (clobber (reg:SI 1))
7352 (clobber (reg:SI 2))
7354 (use (const_int 1))])]
7358 [(parallel [(call (mem:SI (reg:SI 22))
7359 (match_operand 0 "" ""))
7360 (clobber (reg:SI 1))
7361 (clobber (reg:SI 2))
7362 (clobber (match_operand 1))
7364 (use (const_int 1))])]
7365 "!TARGET_64BIT && reload_completed"
7366 [(set (match_dup 1) (reg:SI 19))
7367 (parallel [(call (mem:SI (reg:SI 22))
7369 (clobber (reg:SI 1))
7370 (clobber (reg:SI 2))
7372 (use (const_int 1))])
7373 (set (reg:SI 19) (match_dup 1))]
7376 (define_insn "*call_reg_pic_post_reload"
7377 [(call (mem:SI (reg:SI 22))
7378 (match_operand 0 "" "i"))
7379 (clobber (reg:SI 1))
7380 (clobber (reg:SI 2))
7382 (use (const_int 1))]
7386 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7388 [(set_attr "type" "dyncall")
7389 (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
7391 ;; This pattern is split if it is necessary to save and restore the
7393 (define_insn "call_reg_64bit"
7394 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7395 (match_operand 1 "" "i"))
7396 (clobber (reg:DI 1))
7397 (clobber (reg:DI 2))
7398 (clobber (match_operand 2))
7401 (use (const_int 1))]
7405 ;; Split out the PIC register save and restore after reload. As the
7406 ;; split is done after reload, there are some situations in which we
7407 ;; unnecessarily save and restore %r4. This happens when there is a
7408 ;; single call and the PIC register is not used after the call.
7410 ;; The split has to be done since call_from_call_insn () can't handle
7411 ;; the pattern as is. Noreturn calls are special because they have to
7412 ;; terminate the basic block. The split has to contain more than one
7415 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7416 (match_operand 1 "" ""))
7417 (clobber (reg:DI 1))
7418 (clobber (reg:DI 2))
7419 (clobber (match_operand 2))
7422 (use (const_int 1))])]
7423 "TARGET_64BIT && reload_completed
7424 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7425 [(set (match_dup 2) (reg:DI 27))
7426 (parallel [(call (mem:SI (match_dup 0))
7428 (clobber (reg:DI 1))
7429 (clobber (reg:DI 2))
7432 (use (const_int 1))])]
7436 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7437 (match_operand 1 "" ""))
7438 (clobber (reg:DI 1))
7439 (clobber (reg:DI 2))
7440 (clobber (match_operand 2))
7443 (use (const_int 1))])]
7444 "TARGET_64BIT && reload_completed"
7445 [(set (match_dup 2) (reg:DI 27))
7446 (parallel [(call (mem:SI (match_dup 0))
7448 (clobber (reg:DI 1))
7449 (clobber (reg:DI 2))
7452 (use (const_int 1))])
7453 (set (reg:DI 27) (match_dup 2))]
7456 (define_insn "*call_reg_64bit_post_reload"
7457 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7458 (match_operand 1 "" "i"))
7459 (clobber (reg:DI 1))
7460 (clobber (reg:DI 2))
7463 (use (const_int 1))]
7467 return pa_output_indirect_call (insn, operands[0]);
7469 [(set_attr "type" "dyncall")
7470 (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
7472 (define_expand "call_value"
7473 [(parallel [(set (match_operand 0 "" "")
7474 (call (match_operand:SI 1 "" "")
7475 (match_operand 2 "" "")))
7476 (clobber (reg:SI 2))])]
7481 rtx dst = operands[0];
7482 rtx nb = operands[2];
7484 if (TARGET_PORTABLE_RUNTIME)
7485 op = force_reg (SImode, XEXP (operands[1], 0));
7487 op = XEXP (operands[1], 0);
7491 if (!virtuals_instantiated)
7492 emit_move_insn (arg_pointer_rtx,
7493 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7497 /* The loop pass can generate new libcalls after the virtual
7498 registers are instantiated when fpregs are disabled because
7499 the only method that we have for doing DImode multiplication
7500 is with a libcall. This could be trouble if we haven't
7501 allocated enough space for the outgoing arguments. */
7502 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7504 emit_move_insn (arg_pointer_rtx,
7505 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7506 GEN_INT (STACK_POINTER_OFFSET + 64)));
7510 /* Use two different patterns for calls to explicitly named functions
7511 and calls through function pointers. This is necessary as these two
7512 types of calls use different calling conventions, and CSE might try
7513 to change the named call into an indirect call in some cases (using
7514 two patterns keeps CSE from performing this optimization).
7516 We now use even more call patterns as there was a subtle bug in
7517 attempting to restore the pic register after a call using a simple
7518 move insn. During reload, a instruction involving a pseudo register
7519 with no explicit dependence on the PIC register can be converted
7520 to an equivalent load from memory using the PIC register. If we
7521 emit a simple move to restore the PIC register in the initial rtl
7522 generation, then it can potentially be repositioned during scheduling.
7523 and an instruction that eventually uses the PIC register may end up
7524 between the call and the PIC register restore.
7526 This only worked because there is a post call group of instructions
7527 that are scheduled with the call. These instructions are included
7528 in the same basic block as the call. However, calls can throw in
7529 C++ code and a basic block has to terminate at the call if the call
7530 can throw. This results in the PIC register restore being scheduled
7531 independently from the call. So, we now hide the save and restore
7532 of the PIC register in the call pattern until after reload. Then,
7533 we split the moves out. A small side benefit is that we now don't
7534 need to have a use of the PIC register in the return pattern and
7535 the final save/restore operation is not needed.
7537 I elected to just use register %r4 in the PIC patterns instead
7538 of trying to force hppa_pic_save_rtx () to a callee saved register.
7539 This might have required a new register class and constraint. It
7540 was also simpler to just handle the restore from a register than a
7544 rtx r4 = gen_rtx_REG (word_mode, 4);
7545 if (GET_CODE (op) == SYMBOL_REF)
7546 emit_call_insn (gen_call_val_symref_64bit (dst, op, nb, r4));
7549 op = force_reg (word_mode, op);
7550 emit_call_insn (gen_call_val_reg_64bit (dst, op, nb, r4));
7555 if (GET_CODE (op) == SYMBOL_REF)
7559 rtx r4 = gen_rtx_REG (word_mode, 4);
7560 emit_call_insn (gen_call_val_symref_pic (dst, op, nb, r4));
7563 emit_call_insn (gen_call_val_symref (dst, op, nb));
7567 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7568 emit_move_insn (tmpreg, force_reg (word_mode, op));
7571 rtx r4 = gen_rtx_REG (word_mode, 4);
7572 emit_call_insn (gen_call_val_reg_pic (dst, nb, r4));
7575 emit_call_insn (gen_call_val_reg (dst, nb));
7582 (define_insn "call_val_symref"
7583 [(set (match_operand 0 "" "")
7584 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7585 (match_operand 2 "" "i")))
7586 (clobber (reg:SI 1))
7587 (clobber (reg:SI 2))
7588 (use (const_int 0))]
7589 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7592 pa_output_arg_descriptor (insn);
7593 return pa_output_call (insn, operands[1], 0);
7595 [(set_attr "type" "call")
7596 (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
7598 (define_insn "call_val_symref_pic"
7599 [(set (match_operand 0 "" "")
7600 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7601 (match_operand 2 "" "i")))
7602 (clobber (reg:SI 1))
7603 (clobber (reg:SI 2))
7604 (clobber (match_operand 3))
7606 (use (const_int 0))]
7607 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7610 ;; Split out the PIC register save and restore after reload. As the
7611 ;; split is done after reload, there are some situations in which we
7612 ;; unnecessarily save and restore %r4. This happens when there is a
7613 ;; single call and the PIC register is not used after the call.
7615 ;; The split has to be done since call_from_call_insn () can't handle
7616 ;; the pattern as is. Noreturn calls are special because they have to
7617 ;; terminate the basic block. The split has to contain more than one
7620 [(parallel [(set (match_operand 0 "" "")
7621 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7622 (match_operand 2 "" "")))
7623 (clobber (reg:SI 1))
7624 (clobber (reg:SI 2))
7625 (clobber (match_operand 3))
7627 (use (const_int 0))])]
7628 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7629 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7630 [(set (match_dup 3) (reg:SI 19))
7631 (parallel [(set (match_dup 0)
7632 (call (mem:SI (match_dup 1))
7634 (clobber (reg:SI 1))
7635 (clobber (reg:SI 2))
7637 (use (const_int 0))])]
7641 [(parallel [(set (match_operand 0 "" "")
7642 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7643 (match_operand 2 "" "")))
7644 (clobber (reg:SI 1))
7645 (clobber (reg:SI 2))
7646 (clobber (match_operand 3))
7648 (use (const_int 0))])]
7649 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7650 [(set (match_dup 3) (reg:SI 19))
7651 (parallel [(set (match_dup 0)
7652 (call (mem:SI (match_dup 1))
7654 (clobber (reg:SI 1))
7655 (clobber (reg:SI 2))
7657 (use (const_int 0))])
7658 (set (reg:SI 19) (match_dup 3))]
7661 (define_insn "*call_val_symref_pic_post_reload"
7662 [(set (match_operand 0 "" "")
7663 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7664 (match_operand 2 "" "i")))
7665 (clobber (reg:SI 1))
7666 (clobber (reg:SI 2))
7668 (use (const_int 0))]
7669 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7672 pa_output_arg_descriptor (insn);
7673 return pa_output_call (insn, operands[1], 0);
7675 [(set_attr "type" "call")
7676 (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
7678 ;; This pattern is split if it is necessary to save and restore the
7680 (define_insn "call_val_symref_64bit"
7681 [(set (match_operand 0 "" "")
7682 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7683 (match_operand 2 "" "i")))
7684 (clobber (reg:DI 1))
7685 (clobber (reg:DI 2))
7686 (clobber (match_operand 3))
7689 (use (const_int 0))]
7693 ;; Split out the PIC register save and restore after reload. As the
7694 ;; split is done after reload, there are some situations in which we
7695 ;; unnecessarily save and restore %r4. This happens when there is a
7696 ;; single call and the PIC register is not used after the call.
7698 ;; The split has to be done since call_from_call_insn () can't handle
7699 ;; the pattern as is. Noreturn calls are special because they have to
7700 ;; terminate the basic block. The split has to contain more than one
7703 [(parallel [(set (match_operand 0 "" "")
7704 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7705 (match_operand 2 "" "")))
7706 (clobber (reg:DI 1))
7707 (clobber (reg:DI 2))
7708 (clobber (match_operand 3))
7711 (use (const_int 0))])]
7712 "TARGET_64BIT && reload_completed
7713 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7714 [(set (match_dup 3) (reg:DI 27))
7715 (parallel [(set (match_dup 0)
7716 (call (mem:SI (match_dup 1))
7718 (clobber (reg:DI 1))
7719 (clobber (reg:DI 2))
7722 (use (const_int 0))])]
7726 [(parallel [(set (match_operand 0 "" "")
7727 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7728 (match_operand 2 "" "")))
7729 (clobber (reg:DI 1))
7730 (clobber (reg:DI 2))
7731 (clobber (match_operand 3))
7734 (use (const_int 0))])]
7735 "TARGET_64BIT && reload_completed"
7736 [(set (match_dup 3) (reg:DI 27))
7737 (parallel [(set (match_dup 0)
7738 (call (mem:SI (match_dup 1))
7740 (clobber (reg:DI 1))
7741 (clobber (reg:DI 2))
7744 (use (const_int 0))])
7745 (set (reg:DI 27) (match_dup 3))]
7748 (define_insn "*call_val_symref_64bit_post_reload"
7749 [(set (match_operand 0 "" "")
7750 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7751 (match_operand 2 "" "i")))
7752 (clobber (reg:DI 1))
7753 (clobber (reg:DI 2))
7756 (use (const_int 0))]
7760 pa_output_arg_descriptor (insn);
7761 return pa_output_call (insn, operands[1], 0);
7763 [(set_attr "type" "call")
7764 (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
7766 (define_insn "call_val_reg"
7767 [(set (match_operand 0 "" "")
7768 (call (mem:SI (reg:SI 22))
7769 (match_operand 1 "" "i")))
7770 (clobber (reg:SI 1))
7771 (clobber (reg:SI 2))
7772 (use (const_int 1))]
7776 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7778 [(set_attr "type" "dyncall")
7779 (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
7781 ;; This pattern is split if it is necessary to save and restore the
7783 (define_insn "call_val_reg_pic"
7784 [(set (match_operand 0 "" "")
7785 (call (mem:SI (reg:SI 22))
7786 (match_operand 1 "" "i")))
7787 (clobber (reg:SI 1))
7788 (clobber (reg:SI 2))
7789 (clobber (match_operand 2))
7791 (use (const_int 1))]
7795 ;; Split out the PIC register save and restore after reload. As the
7796 ;; split is done after reload, there are some situations in which we
7797 ;; unnecessarily save and restore %r4. This happens when there is a
7798 ;; single call and the PIC register is not used after the call.
7800 ;; The split has to be done since call_from_call_insn () can't handle
7801 ;; the pattern as is. Noreturn calls are special because they have to
7802 ;; terminate the basic block. The split has to contain more than one
7805 [(parallel [(set (match_operand 0 "" "")
7806 (call (mem:SI (reg:SI 22))
7807 (match_operand 1 "" "")))
7808 (clobber (reg:SI 1))
7809 (clobber (reg:SI 2))
7810 (clobber (match_operand 2))
7812 (use (const_int 1))])]
7813 "!TARGET_64BIT && reload_completed
7814 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7815 [(set (match_dup 2) (reg:SI 19))
7816 (parallel [(set (match_dup 0)
7817 (call (mem:SI (reg:SI 22))
7819 (clobber (reg:SI 1))
7820 (clobber (reg:SI 2))
7822 (use (const_int 1))])]
7826 [(parallel [(set (match_operand 0 "" "")
7827 (call (mem:SI (reg:SI 22))
7828 (match_operand 1 "" "")))
7829 (clobber (reg:SI 1))
7830 (clobber (reg:SI 2))
7831 (clobber (match_operand 2))
7833 (use (const_int 1))])]
7834 "!TARGET_64BIT && reload_completed"
7835 [(set (match_dup 2) (reg:SI 19))
7836 (parallel [(set (match_dup 0)
7837 (call (mem:SI (reg:SI 22))
7839 (clobber (reg:SI 1))
7840 (clobber (reg:SI 2))
7842 (use (const_int 1))])
7843 (set (reg:SI 19) (match_dup 2))]
7846 (define_insn "*call_val_reg_pic_post_reload"
7847 [(set (match_operand 0 "" "")
7848 (call (mem:SI (reg:SI 22))
7849 (match_operand 1 "" "i")))
7850 (clobber (reg:SI 1))
7851 (clobber (reg:SI 2))
7853 (use (const_int 1))]
7857 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7859 [(set_attr "type" "dyncall")
7860 (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
7862 ;; This pattern is split if it is necessary to save and restore the
7864 (define_insn "call_val_reg_64bit"
7865 [(set (match_operand 0 "" "")
7866 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7867 (match_operand 2 "" "i")))
7868 (clobber (reg:DI 1))
7869 (clobber (reg:DI 2))
7870 (clobber (match_operand 3))
7873 (use (const_int 1))]
7877 ;; Split out the PIC register save and restore after reload. As the
7878 ;; split is done after reload, there are some situations in which we
7879 ;; unnecessarily save and restore %r4. This happens when there is a
7880 ;; single call and the PIC register is not used after the call.
7882 ;; The split has to be done since call_from_call_insn () can't handle
7883 ;; the pattern as is. Noreturn calls are special because they have to
7884 ;; terminate the basic block. The split has to contain more than one
7887 [(parallel [(set (match_operand 0 "" "")
7888 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7889 (match_operand 2 "" "")))
7890 (clobber (reg:DI 1))
7891 (clobber (reg:DI 2))
7892 (clobber (match_operand 3))
7895 (use (const_int 1))])]
7896 "TARGET_64BIT && reload_completed
7897 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7898 [(set (match_dup 3) (reg:DI 27))
7899 (parallel [(set (match_dup 0)
7900 (call (mem:SI (match_dup 1))
7902 (clobber (reg:DI 1))
7903 (clobber (reg:DI 2))
7906 (use (const_int 1))])]
7910 [(parallel [(set (match_operand 0 "" "")
7911 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7912 (match_operand 2 "" "")))
7913 (clobber (reg:DI 1))
7914 (clobber (reg:DI 2))
7915 (clobber (match_operand 3))
7918 (use (const_int 1))])]
7919 "TARGET_64BIT && reload_completed"
7920 [(set (match_dup 3) (reg:DI 27))
7921 (parallel [(set (match_dup 0)
7922 (call (mem:SI (match_dup 1))
7924 (clobber (reg:DI 1))
7925 (clobber (reg:DI 2))
7928 (use (const_int 1))])
7929 (set (reg:DI 27) (match_dup 3))]
7932 (define_insn "*call_val_reg_64bit_post_reload"
7933 [(set (match_operand 0 "" "")
7934 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7935 (match_operand 2 "" "i")))
7936 (clobber (reg:DI 1))
7937 (clobber (reg:DI 2))
7940 (use (const_int 1))]
7944 return pa_output_indirect_call (insn, operands[1]);
7946 [(set_attr "type" "dyncall")
7947 (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
7949 ;; Call subroutine returning any type.
7951 (define_expand "untyped_call"
7952 [(parallel [(call (match_operand 0 "" "")
7954 (match_operand 1 "" "")
7955 (match_operand 2 "" "")])]
7961 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7963 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7965 rtx set = XVECEXP (operands[2], 0, i);
7966 emit_move_insn (SET_DEST (set), SET_SRC (set));
7969 /* The optimizer does not know that the call sets the function value
7970 registers we stored in the result block. We avoid problems by
7971 claiming that all hard registers are used and clobbered at this
7973 emit_insn (gen_blockage ());
7978 (define_expand "sibcall"
7979 [(call (match_operand:SI 0 "" "")
7980 (match_operand 1 "" ""))]
7981 "!TARGET_PORTABLE_RUNTIME"
7985 rtx nb = operands[1];
7987 op = XEXP (operands[0], 0);
7991 if (!virtuals_instantiated)
7992 emit_move_insn (arg_pointer_rtx,
7993 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7997 /* The loop pass can generate new libcalls after the virtual
7998 registers are instantiated when fpregs are disabled because
7999 the only method that we have for doing DImode multiplication
8000 is with a libcall. This could be trouble if we haven't
8001 allocated enough space for the outgoing arguments. */
8002 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8004 emit_move_insn (arg_pointer_rtx,
8005 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8006 GEN_INT (STACK_POINTER_OFFSET + 64)));
8010 /* Indirect sibling calls are not allowed. */
8012 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8014 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8016 call_insn = emit_call_insn (call_insn);
8019 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8021 /* We don't have to restore the PIC register. */
8023 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8028 (define_insn "sibcall_internal_symref"
8029 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8030 (match_operand 1 "" "i"))
8031 (clobber (reg:SI 1))
8033 (use (const_int 0))]
8034 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8037 pa_output_arg_descriptor (insn);
8038 return pa_output_call (insn, operands[0], 1);
8040 [(set_attr "type" "call")
8041 (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
8043 (define_insn "sibcall_internal_symref_64bit"
8044 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8045 (match_operand 1 "" "i"))
8046 (clobber (reg:DI 1))
8048 (use (const_int 0))]
8052 pa_output_arg_descriptor (insn);
8053 return pa_output_call (insn, operands[0], 1);
8055 [(set_attr "type" "call")
8056 (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
8058 (define_expand "sibcall_value"
8059 [(set (match_operand 0 "" "")
8060 (call (match_operand:SI 1 "" "")
8061 (match_operand 2 "" "")))]
8062 "!TARGET_PORTABLE_RUNTIME"
8066 rtx nb = operands[1];
8068 op = XEXP (operands[1], 0);
8072 if (!virtuals_instantiated)
8073 emit_move_insn (arg_pointer_rtx,
8074 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8078 /* The loop pass can generate new libcalls after the virtual
8079 registers are instantiated when fpregs are disabled because
8080 the only method that we have for doing DImode multiplication
8081 is with a libcall. This could be trouble if we haven't
8082 allocated enough space for the outgoing arguments. */
8083 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8085 emit_move_insn (arg_pointer_rtx,
8086 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8087 GEN_INT (STACK_POINTER_OFFSET + 64)));
8091 /* Indirect sibling calls are not allowed. */
8094 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8097 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8099 call_insn = emit_call_insn (call_insn);
8102 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8104 /* We don't have to restore the PIC register. */
8106 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8111 (define_insn "sibcall_value_internal_symref"
8112 [(set (match_operand 0 "" "")
8113 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8114 (match_operand 2 "" "i")))
8115 (clobber (reg:SI 1))
8117 (use (const_int 0))]
8118 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8121 pa_output_arg_descriptor (insn);
8122 return pa_output_call (insn, operands[1], 1);
8124 [(set_attr "type" "call")
8125 (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
8127 (define_insn "sibcall_value_internal_symref_64bit"
8128 [(set (match_operand 0 "" "")
8129 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8130 (match_operand 2 "" "i")))
8131 (clobber (reg:DI 1))
8133 (use (const_int 0))]
8137 pa_output_arg_descriptor (insn);
8138 return pa_output_call (insn, operands[1], 1);
8140 [(set_attr "type" "call")
8141 (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
8147 [(set_attr "type" "move")
8148 (set_attr "length" "4")])
8150 ;; These are just placeholders so we know where branch tables
8152 (define_insn "begin_brtab"
8157 /* Only GAS actually supports this pseudo-op. */
8159 return \".begin_brtab\";
8163 [(set_attr "type" "move")
8164 (set_attr "length" "0")])
8166 (define_insn "end_brtab"
8171 /* Only GAS actually supports this pseudo-op. */
8173 return \".end_brtab\";
8177 [(set_attr "type" "move")
8178 (set_attr "length" "0")])
8180 ;;; EH does longjmp's from and within the data section. Thus,
8181 ;;; an interspace branch is required for the longjmp implementation.
8182 ;;; Registers r1 and r2 are used as scratch registers for the jump
8184 (define_expand "interspace_jump"
8186 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8187 (clobber (match_dup 1))])]
8191 operands[1] = gen_rtx_REG (word_mode, 2);
8195 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8196 (clobber (reg:SI 2))]
8197 "TARGET_PA_20 && !TARGET_64BIT"
8199 [(set_attr "type" "branch")
8200 (set_attr "length" "4")])
8203 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8204 (clobber (reg:SI 2))]
8205 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8207 [(set_attr "type" "branch")
8208 (set_attr "length" "4")])
8211 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8212 (clobber (reg:SI 2))]
8214 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8215 [(set_attr "type" "branch")
8216 (set_attr "length" "12")])
8219 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8220 (clobber (reg:DI 2))]
8223 [(set_attr "type" "branch")
8224 (set_attr "length" "4")])
8226 (define_expand "builtin_longjmp"
8227 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8231 /* The elements of the buffer are, in order: */
8232 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8233 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
8234 POINTER_SIZE / BITS_PER_UNIT));
8235 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
8236 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8237 rtx pv = gen_rtx_REG (Pmode, 1);
8239 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
8240 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
8242 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8243 instead of the hard_frame_pointer_rtx in the save area. We need
8244 to adjust for the offset between these two values. */
8245 if (GET_CODE (fp) != REG)
8246 fp = force_reg (Pmode, fp);
8247 emit_move_insn (hard_frame_pointer_rtx, plus_constant (Pmode, fp, -8));
8249 /* This bit is the same as expand_builtin_longjmp. */
8250 emit_stack_restore (SAVE_NONLOCAL, stack);
8251 emit_use (hard_frame_pointer_rtx);
8252 emit_use (stack_pointer_rtx);
8254 /* Load the label we are jumping through into r1 so that we know
8255 where to look for it when we get back to setjmp's function for
8256 restoring the gp. */
8257 emit_move_insn (pv, lab);
8259 /* Prevent the insns above from being scheduled into the delay slot
8260 of the interspace jump because the space register could change. */
8261 emit_insn (gen_blockage ());
8263 emit_jump_insn (gen_interspace_jump (pv));
8268 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8269 (define_expand "extzv"
8270 [(set (match_operand 0 "register_operand" "")
8271 (zero_extract (match_operand 1 "register_operand" "")
8272 (match_operand 2 "uint32_operand" "")
8273 (match_operand 3 "uint32_operand" "")))]
8277 HOST_WIDE_INT len = INTVAL (operands[2]);
8278 HOST_WIDE_INT pos = INTVAL (operands[3]);
8280 /* PA extraction insns don't support zero length bitfields or fields
8281 extending beyond the left or right-most bits. Also, we reject lengths
8282 equal to a word as they are better handled by the move patterns. */
8283 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8286 /* From mips.md: extract_bit_field doesn't verify that our source
8287 matches the predicate, so check it again here. */
8288 if (!register_operand (operands[1], VOIDmode))
8292 emit_insn (gen_extzv_64 (operands[0], operands[1],
8293 operands[2], operands[3]));
8295 emit_insn (gen_extzv_32 (operands[0], operands[1],
8296 operands[2], operands[3]));
8300 (define_insn "extzv_32"
8301 [(set (match_operand:SI 0 "register_operand" "=r")
8302 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8303 (match_operand:SI 2 "uint5_operand" "")
8304 (match_operand:SI 3 "uint5_operand" "")))]
8306 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8307 [(set_attr "type" "shift")
8308 (set_attr "length" "4")])
8311 [(set (match_operand:SI 0 "register_operand" "=r")
8312 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8314 (match_operand:SI 2 "register_operand" "q")))]
8316 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8317 [(set_attr "type" "shift")
8318 (set_attr "length" "4")])
8320 (define_insn "extzv_64"
8321 [(set (match_operand:DI 0 "register_operand" "=r")
8322 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8323 (match_operand:DI 2 "uint32_operand" "")
8324 (match_operand:DI 3 "uint32_operand" "")))]
8326 "extrd,u %1,%3+%2-1,%2,%0"
8327 [(set_attr "type" "shift")
8328 (set_attr "length" "4")])
8331 [(set (match_operand:DI 0 "register_operand" "=r")
8332 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8334 (match_operand:DI 2 "register_operand" "q")))]
8336 "extrd,u %1,%%sar,1,%0"
8337 [(set_attr "type" "shift")
8338 (set_attr "length" "4")])
8340 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8341 (define_expand "extv"
8342 [(set (match_operand 0 "register_operand" "")
8343 (sign_extract (match_operand 1 "register_operand" "")
8344 (match_operand 2 "uint32_operand" "")
8345 (match_operand 3 "uint32_operand" "")))]
8349 HOST_WIDE_INT len = INTVAL (operands[2]);
8350 HOST_WIDE_INT pos = INTVAL (operands[3]);
8352 /* PA extraction insns don't support zero length bitfields or fields
8353 extending beyond the left or right-most bits. Also, we reject lengths
8354 equal to a word as they are better handled by the move patterns. */
8355 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8358 /* From mips.md: extract_bit_field doesn't verify that our source
8359 matches the predicate, so check it again here. */
8360 if (!register_operand (operands[1], VOIDmode))
8364 emit_insn (gen_extv_64 (operands[0], operands[1],
8365 operands[2], operands[3]));
8367 emit_insn (gen_extv_32 (operands[0], operands[1],
8368 operands[2], operands[3]));
8372 (define_insn "extv_32"
8373 [(set (match_operand:SI 0 "register_operand" "=r")
8374 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8375 (match_operand:SI 2 "uint5_operand" "")
8376 (match_operand:SI 3 "uint5_operand" "")))]
8378 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8379 [(set_attr "type" "shift")
8380 (set_attr "length" "4")])
8383 [(set (match_operand:SI 0 "register_operand" "=r")
8384 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8386 (match_operand:SI 2 "register_operand" "q")))]
8388 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8389 [(set_attr "type" "shift")
8390 (set_attr "length" "4")])
8392 (define_insn "extv_64"
8393 [(set (match_operand:DI 0 "register_operand" "=r")
8394 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8395 (match_operand:DI 2 "uint32_operand" "")
8396 (match_operand:DI 3 "uint32_operand" "")))]
8398 "extrd,s %1,%3+%2-1,%2,%0"
8399 [(set_attr "type" "shift")
8400 (set_attr "length" "4")])
8403 [(set (match_operand:DI 0 "register_operand" "=r")
8404 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8406 (match_operand:DI 2 "register_operand" "q")))]
8408 "extrd,s %1,%%sar,1,%0"
8409 [(set_attr "type" "shift")
8410 (set_attr "length" "4")])
8412 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8413 (define_expand "insv"
8414 [(set (zero_extract (match_operand 0 "register_operand" "")
8415 (match_operand 1 "uint32_operand" "")
8416 (match_operand 2 "uint32_operand" ""))
8417 (match_operand 3 "arith5_operand" ""))]
8421 HOST_WIDE_INT len = INTVAL (operands[1]);
8422 HOST_WIDE_INT pos = INTVAL (operands[2]);
8424 /* PA insertion insns don't support zero length bitfields or fields
8425 extending beyond the left or right-most bits. Also, we reject lengths
8426 equal to a word as they are better handled by the move patterns. */
8427 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8430 /* From mips.md: insert_bit_field doesn't verify that our destination
8431 matches the predicate, so check it again here. */
8432 if (!register_operand (operands[0], VOIDmode))
8436 emit_insn (gen_insv_64 (operands[0], operands[1],
8437 operands[2], operands[3]));
8439 emit_insn (gen_insv_32 (operands[0], operands[1],
8440 operands[2], operands[3]));
8444 (define_insn "insv_32"
8445 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8446 (match_operand:SI 1 "uint5_operand" "")
8447 (match_operand:SI 2 "uint5_operand" ""))
8448 (match_operand:SI 3 "arith5_operand" "r,L"))]
8451 {dep|depw} %3,%2+%1-1,%1,%0
8452 {depi|depwi} %3,%2+%1-1,%1,%0"
8453 [(set_attr "type" "shift,shift")
8454 (set_attr "length" "4,4")])
8456 ;; Optimize insertion of const_int values of type 1...1xxxx.
8458 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8459 (match_operand:SI 1 "uint5_operand" "")
8460 (match_operand:SI 2 "uint5_operand" ""))
8461 (match_operand:SI 3 "const_int_operand" ""))]
8462 "(INTVAL (operands[3]) & 0x10) != 0 &&
8463 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8466 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8467 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8469 [(set_attr "type" "shift")
8470 (set_attr "length" "4")])
8472 (define_insn "insv_64"
8473 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8474 (match_operand:DI 1 "uint32_operand" "")
8475 (match_operand:DI 2 "uint32_operand" ""))
8476 (match_operand:DI 3 "arith32_operand" "r,L"))]
8479 depd %3,%2+%1-1,%1,%0
8480 depdi %3,%2+%1-1,%1,%0"
8481 [(set_attr "type" "shift,shift")
8482 (set_attr "length" "4,4")])
8484 ;; Optimize insertion of const_int values of type 1...1xxxx.
8486 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8487 (match_operand:DI 1 "uint32_operand" "")
8488 (match_operand:DI 2 "uint32_operand" ""))
8489 (match_operand:DI 3 "const_int_operand" ""))]
8490 "(INTVAL (operands[3]) & 0x10) != 0
8492 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8495 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8496 return \"depdi %3,%2+%1-1,%1,%0\";
8498 [(set_attr "type" "shift")
8499 (set_attr "length" "4")])
8502 [(set (match_operand:DI 0 "register_operand" "=r")
8503 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8506 "depd,z %1,31,32,%0"
8507 [(set_attr "type" "shift")
8508 (set_attr "length" "4")])
8510 ;; This insn is used for some loop tests, typically loops reversed when
8511 ;; strength reduction is used. It is actually created when the instruction
8512 ;; combination phase combines the special loop test. Since this insn
8513 ;; is both a jump insn and has an output, it must deal with its own
8514 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8515 ;; to not choose the register alternatives in the event a reload is needed.
8516 (define_insn "decrement_and_branch_until_zero"
8519 (match_operator 2 "comparison_operator"
8521 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8522 (match_operand:SI 1 "int5_operand" "L,L,L"))
8524 (label_ref (match_operand 3 "" ""))
8527 (plus:SI (match_dup 0) (match_dup 1)))
8528 (clobber (match_scratch:SI 4 "=X,r,r"))]
8530 "* return pa_output_dbra (operands, insn, which_alternative); "
8531 ;; Do not expect to understand this the first time through.
8532 [(set_attr "type" "cbranch,multi,multi")
8533 (set (attr "length")
8534 (if_then_else (eq_attr "alternative" "0")
8535 ;; Loop counter in register case
8536 ;; Short branch has length of 4
8537 ;; Long branch has length of 8, 20, 24 or 28
8538 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8539 (const_int MAX_12BIT_OFFSET))
8541 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8542 (const_int MAX_17BIT_OFFSET))
8544 (match_test "TARGET_PORTABLE_RUNTIME")
8546 (not (match_test "flag_pic"))
8550 ;; Loop counter in FP reg case.
8551 ;; Extra goo to deal with additional reload insns.
8552 (if_then_else (eq_attr "alternative" "1")
8553 (if_then_else (lt (match_dup 3) (pc))
8554 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8555 (const_int MAX_12BIT_OFFSET))
8557 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8558 (const_int MAX_17BIT_OFFSET))
8560 (match_test "TARGET_PORTABLE_RUNTIME")
8562 (not (match_test "flag_pic"))
8565 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8566 (const_int MAX_12BIT_OFFSET))
8568 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8569 (const_int MAX_17BIT_OFFSET))
8571 (match_test "TARGET_PORTABLE_RUNTIME")
8573 (not (match_test "flag_pic"))
8577 ;; Loop counter in memory case.
8578 ;; Extra goo to deal with additional reload insns.
8579 (if_then_else (lt (match_dup 3) (pc))
8580 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8581 (const_int MAX_12BIT_OFFSET))
8583 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8584 (const_int MAX_17BIT_OFFSET))
8586 (match_test "TARGET_PORTABLE_RUNTIME")
8588 (not (match_test "flag_pic"))
8591 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8592 (const_int MAX_12BIT_OFFSET))
8594 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8595 (const_int MAX_17BIT_OFFSET))
8597 (match_test "TARGET_PORTABLE_RUNTIME")
8599 (not (match_test "flag_pic"))
8601 (const_int 36))))))])
8606 (match_operator 2 "movb_comparison_operator"
8607 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8608 (label_ref (match_operand 3 "" ""))
8610 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8613 "* return pa_output_movb (operands, insn, which_alternative, 0); "
8614 ;; Do not expect to understand this the first time through.
8615 [(set_attr "type" "cbranch,multi,multi,multi")
8616 (set (attr "length")
8617 (if_then_else (eq_attr "alternative" "0")
8618 ;; Loop counter in register case
8619 ;; Short branch has length of 4
8620 ;; Long branch has length of 8, 20, 24 or 28
8621 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8622 (const_int MAX_12BIT_OFFSET))
8624 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8625 (const_int MAX_17BIT_OFFSET))
8627 (match_test "TARGET_PORTABLE_RUNTIME")
8629 (not (match_test "flag_pic"))
8633 ;; Loop counter in FP reg case.
8634 ;; Extra goo to deal with additional reload insns.
8635 (if_then_else (eq_attr "alternative" "1")
8636 (if_then_else (lt (match_dup 3) (pc))
8637 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8638 (const_int MAX_12BIT_OFFSET))
8640 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8641 (const_int MAX_17BIT_OFFSET))
8643 (match_test "TARGET_PORTABLE_RUNTIME")
8645 (not (match_test "flag_pic"))
8648 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8649 (const_int MAX_12BIT_OFFSET))
8651 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8652 (const_int MAX_17BIT_OFFSET))
8654 (match_test "TARGET_PORTABLE_RUNTIME")
8656 (not (match_test "flag_pic"))
8660 ;; Loop counter in memory or sar case.
8661 ;; Extra goo to deal with additional reload insns.
8662 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8663 (const_int MAX_12BIT_OFFSET))
8665 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8666 (const_int MAX_17BIT_OFFSET))
8668 (match_test "TARGET_PORTABLE_RUNTIME")
8670 (not (match_test "flag_pic"))
8672 (const_int 32)))))])
8674 ;; Handle negated branch.
8678 (match_operator 2 "movb_comparison_operator"
8679 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8681 (label_ref (match_operand 3 "" ""))))
8682 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8685 "* return pa_output_movb (operands, insn, which_alternative, 1); "
8686 ;; Do not expect to understand this the first time through.
8687 [(set_attr "type" "cbranch,multi,multi,multi")
8688 (set (attr "length")
8689 (if_then_else (eq_attr "alternative" "0")
8690 ;; Loop counter in register case
8691 ;; Short branch has length of 4
8692 ;; Long branch has length of 8
8693 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8694 (const_int MAX_12BIT_OFFSET))
8696 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8697 (const_int MAX_17BIT_OFFSET))
8699 (match_test "TARGET_PORTABLE_RUNTIME")
8701 (not (match_test "flag_pic"))
8705 ;; Loop counter in FP reg case.
8706 ;; Extra goo to deal with additional reload insns.
8707 (if_then_else (eq_attr "alternative" "1")
8708 (if_then_else (lt (match_dup 3) (pc))
8709 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8710 (const_int MAX_12BIT_OFFSET))
8712 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8713 (const_int MAX_17BIT_OFFSET))
8715 (match_test "TARGET_PORTABLE_RUNTIME")
8717 (not (match_test "flag_pic"))
8720 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8721 (const_int MAX_12BIT_OFFSET))
8723 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8724 (const_int MAX_17BIT_OFFSET))
8726 (match_test "TARGET_PORTABLE_RUNTIME")
8728 (not (match_test "flag_pic"))
8732 ;; Loop counter in memory or SAR case.
8733 ;; Extra goo to deal with additional reload insns.
8734 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8735 (const_int MAX_12BIT_OFFSET))
8737 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8738 (const_int MAX_17BIT_OFFSET))
8740 (match_test "TARGET_PORTABLE_RUNTIME")
8742 (not (match_test "flag_pic"))
8744 (const_int 32)))))])
8747 [(set (pc) (label_ref (match_operand 3 "" "" )))
8748 (set (match_operand:SI 0 "ireg_operand" "=r")
8749 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8750 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8751 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8754 return pa_output_parallel_addb (operands, insn);
8756 [(set_attr "type" "parallel_branch")
8757 (set (attr "length")
8758 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8759 (const_int MAX_12BIT_OFFSET))
8761 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8762 (const_int MAX_17BIT_OFFSET))
8764 (match_test "TARGET_PORTABLE_RUNTIME")
8766 (not (match_test "flag_pic"))
8771 [(set (pc) (label_ref (match_operand 2 "" "" )))
8772 (set (match_operand:SF 0 "ireg_operand" "=r")
8773 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8777 return pa_output_parallel_movb (operands, insn);
8779 [(set_attr "type" "parallel_branch")
8780 (set (attr "length")
8781 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8782 (const_int MAX_12BIT_OFFSET))
8784 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8785 (const_int MAX_17BIT_OFFSET))
8787 (match_test "TARGET_PORTABLE_RUNTIME")
8789 (not (match_test "flag_pic"))
8794 [(set (pc) (label_ref (match_operand 2 "" "" )))
8795 (set (match_operand:SI 0 "ireg_operand" "=r")
8796 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8800 return pa_output_parallel_movb (operands, insn);
8802 [(set_attr "type" "parallel_branch")
8803 (set (attr "length")
8804 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8805 (const_int MAX_12BIT_OFFSET))
8807 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8808 (const_int MAX_17BIT_OFFSET))
8810 (match_test "TARGET_PORTABLE_RUNTIME")
8812 (not (match_test "flag_pic"))
8817 [(set (pc) (label_ref (match_operand 2 "" "" )))
8818 (set (match_operand:HI 0 "ireg_operand" "=r")
8819 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
8823 return pa_output_parallel_movb (operands, insn);
8825 [(set_attr "type" "parallel_branch")
8826 (set (attr "length")
8827 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8828 (const_int MAX_12BIT_OFFSET))
8830 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8831 (const_int MAX_17BIT_OFFSET))
8833 (match_test "TARGET_PORTABLE_RUNTIME")
8835 (not (match_test "flag_pic"))
8840 [(set (pc) (label_ref (match_operand 2 "" "" )))
8841 (set (match_operand:QI 0 "ireg_operand" "=r")
8842 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
8846 return pa_output_parallel_movb (operands, insn);
8848 [(set_attr "type" "parallel_branch")
8849 (set (attr "length")
8850 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8851 (const_int MAX_12BIT_OFFSET))
8853 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8854 (const_int MAX_17BIT_OFFSET))
8856 (match_test "TARGET_PORTABLE_RUNTIME")
8858 (not (match_test "flag_pic"))
8863 [(set (match_operand 0 "register_operand" "=f")
8864 (mult (match_operand 1 "register_operand" "f")
8865 (match_operand 2 "register_operand" "f")))
8866 (set (match_operand 3 "register_operand" "+f")
8867 (plus (match_operand 4 "register_operand" "f")
8868 (match_operand 5 "register_operand" "f")))]
8869 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8870 && reload_completed && pa_fmpyaddoperands (operands)"
8873 if (GET_MODE (operands[0]) == DFmode)
8875 if (rtx_equal_p (operands[3], operands[5]))
8876 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8878 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8882 if (rtx_equal_p (operands[3], operands[5]))
8883 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8885 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8888 [(set_attr "type" "fpalu")
8889 (set_attr "length" "4")])
8892 [(set (match_operand 3 "register_operand" "+f")
8893 (plus (match_operand 4 "register_operand" "f")
8894 (match_operand 5 "register_operand" "f")))
8895 (set (match_operand 0 "register_operand" "=f")
8896 (mult (match_operand 1 "register_operand" "f")
8897 (match_operand 2 "register_operand" "f")))]
8898 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8899 && reload_completed && pa_fmpyaddoperands (operands)"
8902 if (GET_MODE (operands[0]) == DFmode)
8904 if (rtx_equal_p (operands[3], operands[5]))
8905 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8907 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8911 if (rtx_equal_p (operands[3], operands[5]))
8912 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8914 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8917 [(set_attr "type" "fpalu")
8918 (set_attr "length" "4")])
8921 [(set (match_operand 0 "register_operand" "=f")
8922 (mult (match_operand 1 "register_operand" "f")
8923 (match_operand 2 "register_operand" "f")))
8924 (set (match_operand 3 "register_operand" "+f")
8925 (minus (match_operand 4 "register_operand" "f")
8926 (match_operand 5 "register_operand" "f")))]
8927 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8928 && reload_completed && pa_fmpysuboperands (operands)"
8931 if (GET_MODE (operands[0]) == DFmode)
8932 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8934 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8936 [(set_attr "type" "fpalu")
8937 (set_attr "length" "4")])
8940 [(set (match_operand 3 "register_operand" "+f")
8941 (minus (match_operand 4 "register_operand" "f")
8942 (match_operand 5 "register_operand" "f")))
8943 (set (match_operand 0 "register_operand" "=f")
8944 (mult (match_operand 1 "register_operand" "f")
8945 (match_operand 2 "register_operand" "f")))]
8946 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8947 && reload_completed && pa_fmpysuboperands (operands)"
8950 if (GET_MODE (operands[0]) == DFmode)
8951 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8953 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8955 [(set_attr "type" "fpalu")
8956 (set_attr "length" "4")])
8958 ;; The following two patterns are used by the trampoline code for nested
8959 ;; functions. They flush the I and D cache lines from the start address
8960 ;; (operand0) to the end address (operand1). No lines are flushed if the
8961 ;; end address is less than the start address (unsigned).
8963 ;; Because the range of memory flushed is variable and the size of a MEM
8964 ;; can only be a CONST_INT, the patterns specify that they perform an
8965 ;; unspecified volatile operation on all memory.
8967 ;; The address range for an icache flush must lie within a single
8968 ;; space on targets with non-equivalent space registers.
8970 ;; Operand 0 contains the start address.
8971 ;; Operand 1 contains the end address.
8972 ;; Operand 2 contains the line length to use.
8973 (define_insn "dcacheflush<P:mode>"
8975 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
8976 (use (match_operand 0 "pmode_register_operand" "r"))
8977 (use (match_operand 1 "pmode_register_operand" "r"))
8978 (use (match_operand 2 "pmode_register_operand" "r"))
8979 (clobber (match_scratch:P 3 "=&0"))]
8981 "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
8982 [(set_attr "type" "multi")
8983 (set_attr "length" "12")])
8985 (define_insn "icacheflush<P:mode>"
8987 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
8988 (use (match_operand 0 "pmode_register_operand" "r"))
8989 (use (match_operand 1 "pmode_register_operand" "r"))
8990 (use (match_operand 2 "pmode_register_operand" "r"))
8991 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
8992 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
8993 (clobber (match_scratch:P 5 "=&0"))]
8995 "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
8996 [(set_attr "type" "multi")
8997 (set_attr "length" "52")])
8999 ;; An out-of-line prologue.
9000 (define_insn "outline_prologue_call"
9001 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9002 (clobber (reg:SI 31))
9003 (clobber (reg:SI 22))
9004 (clobber (reg:SI 21))
9005 (clobber (reg:SI 20))
9006 (clobber (reg:SI 19))
9007 (clobber (reg:SI 1))]
9012 /* We need two different versions depending on whether or not we
9013 need a frame pointer. Also note that we return to the instruction
9014 immediately after the branch rather than two instructions after the
9015 break as normally is the case. */
9016 if (frame_pointer_needed)
9018 /* Must import the magic millicode routine(s). */
9019 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9021 if (TARGET_PORTABLE_RUNTIME)
9023 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9024 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9028 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9032 /* Must import the magic millicode routine(s). */
9033 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9035 if (TARGET_PORTABLE_RUNTIME)
9037 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9038 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9041 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9045 [(set_attr "type" "multi")
9046 (set_attr "length" "8")])
9048 ;; An out-of-line epilogue.
9049 (define_insn "outline_epilogue_call"
9050 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9053 (clobber (reg:SI 31))
9054 (clobber (reg:SI 22))
9055 (clobber (reg:SI 21))
9056 (clobber (reg:SI 20))
9057 (clobber (reg:SI 19))
9058 (clobber (reg:SI 2))
9059 (clobber (reg:SI 1))]
9064 /* We need two different versions depending on whether or not we
9065 need a frame pointer. Also note that we return to the instruction
9066 immediately after the branch rather than two instructions after the
9067 break as normally is the case. */
9068 if (frame_pointer_needed)
9070 /* Must import the magic millicode routine. */
9071 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9073 /* The out-of-line prologue will make sure we return to the right
9075 if (TARGET_PORTABLE_RUNTIME)
9077 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9078 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9082 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9086 /* Must import the magic millicode routine. */
9087 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9089 /* The out-of-line prologue will make sure we return to the right
9091 if (TARGET_PORTABLE_RUNTIME)
9093 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9094 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9097 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9101 [(set_attr "type" "multi")
9102 (set_attr "length" "8")])
9104 ;; Given a function pointer, canonicalize it so it can be
9105 ;; reliably compared to another function pointer. */
9106 (define_expand "canonicalize_funcptr_for_compare"
9107 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9108 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9109 (clobber (match_dup 2))
9110 (clobber (reg:SI 26))
9111 (clobber (reg:SI 22))
9112 (clobber (reg:SI 31))])
9113 (set (match_operand:SI 0 "register_operand" "")
9115 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9120 rtx canonicalize_funcptr_for_compare_libfunc
9121 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9123 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9124 operands[0], LCT_NORMAL, Pmode,
9125 1, operands[1], Pmode);
9129 operands[2] = gen_reg_rtx (SImode);
9130 if (GET_CODE (operands[1]) != REG)
9132 rtx tmp = gen_reg_rtx (Pmode);
9133 emit_move_insn (tmp, operands[1]);
9138 (define_insn "*$$sh_func_adrs"
9139 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9140 (clobber (match_operand:SI 0 "register_operand" "=a"))
9141 (clobber (reg:SI 26))
9142 (clobber (reg:SI 22))
9143 (clobber (reg:SI 31))]
9147 int length = get_attr_length (insn);
9150 xoperands[0] = GEN_INT (length - 8);
9151 xoperands[1] = GEN_INT (length - 16);
9153 /* Must import the magic millicode routine. */
9154 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9156 /* This is absolutely amazing.
9158 First, copy our input parameter into %r29 just in case we don't
9159 need to call $$sh_func_adrs. */
9160 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9161 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9163 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9164 we use %r26 unchanged. */
9165 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9166 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9168 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9169 4096, then again we use %r26 unchanged. */
9170 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9172 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9173 return pa_output_millicode_call (insn,
9174 gen_rtx_SYMBOL_REF (SImode,
9175 \"$$sh_func_adrs\"));
9177 [(set_attr "type" "multi")
9178 (set (attr "length")
9179 (plus (symbol_ref "pa_attr_length_millicode_call (insn)")
9182 ;; On the PA, the PIC register is call clobbered, so it must
9183 ;; be saved & restored around calls by the caller. If the call
9184 ;; doesn't return normally (nonlocal goto, or an exception is
9185 ;; thrown), then the code at the exception handler label must
9186 ;; restore the PIC register.
9187 (define_expand "exception_receiver"
9192 /* On the 64-bit port, we need a blockage because there is
9193 confusion regarding the dependence of the restore on the
9194 frame pointer. As a result, the frame pointer and pic
9195 register restores sometimes are interchanged erroneously. */
9197 emit_insn (gen_blockage ());
9198 /* Restore the PIC register using hppa_pic_save_rtx (). The
9199 PIC register is not saved in the frame in 64-bit ABI. */
9200 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9201 emit_insn (gen_blockage ());
9205 (define_expand "builtin_setjmp_receiver"
9206 [(label_ref (match_operand 0 "" ""))]
9211 emit_insn (gen_blockage ());
9212 /* Restore the PIC register. Hopefully, this will always be from
9213 a stack slot. The only registers that are valid after a
9214 builtin_longjmp are the stack and frame pointers. */
9215 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9216 emit_insn (gen_blockage ());
9220 ;; Allocate new stack space and update the saved stack pointer in the
9221 ;; frame marker. The HP C compilers also copy additional words in the
9222 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9223 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9224 ;; currently don't copy these values.
9226 ;; Since the copy of the frame marker can't be done atomically, I
9227 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9228 ;; The HP compilers appear to raise the stack and copy the frame
9229 ;; marker in a strict instruction sequence. This suggests that the
9230 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9231 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9232 ;; as GAS doesn't support it, or try to keep the instructions emitted
9233 ;; here in strict sequence.
9234 (define_expand "allocate_stack"
9235 [(match_operand 0 "" "")
9236 (match_operand 1 "" "")]
9242 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9243 in operand 0 before adjusting the stack. */
9244 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9245 anti_adjust_stack (operands[1]);
9246 if (TARGET_HPUX_UNWIND_LIBRARY)
9248 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9249 GEN_INT (TARGET_64BIT ? -8 : -4));
9250 emit_move_insn (gen_rtx_MEM (word_mode, addr), hard_frame_pointer_rtx);
9252 if (!TARGET_64BIT && flag_pic)
9254 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9255 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9260 (define_expand "prefetch"
9261 [(match_operand 0 "address_operand" "")
9262 (match_operand 1 "const_int_operand" "")
9263 (match_operand 2 "const_int_operand" "")]
9266 operands[0] = copy_addr_to_reg (operands[0]);
9267 emit_insn (gen_prefetch_20 (operands[0], operands[1], operands[2]));
9271 (define_insn "prefetch_20"
9272 [(prefetch (match_operand 0 "pmode_register_operand" "r")
9273 (match_operand:SI 1 "const_int_operand" "n")
9274 (match_operand:SI 2 "const_int_operand" "n"))]
9277 /* The SL cache-control completer indicates good spatial locality but
9278 poor temporal locality. The ldw instruction with a target of general
9279 register 0 prefetches a cache line for a read. The ldd instruction
9280 prefetches a cache line for a write. */
9281 static const char * const instr[2][2] = {
9283 "ldw,sl 0(%0),%%r0",
9291 int read_or_write = INTVAL (operands[1]) == 0 ? 0 : 1;
9292 int locality = INTVAL (operands[2]) == 0 ? 0 : 1;
9294 return instr [locality][read_or_write];
9296 [(set_attr "type" "load")
9297 (set_attr "length" "4")])
9300 (define_insn "tgd_load"
9301 [(set (match_operand:SI 0 "register_operand" "=r")
9302 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
9303 (clobber (reg:SI 1))
9308 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
9310 [(set_attr "type" "multi")
9311 (set_attr "length" "8")])
9313 (define_insn "tgd_load_pic"
9314 [(set (match_operand:SI 0 "register_operand" "=r")
9315 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
9316 (clobber (reg:SI 1))
9321 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
9323 [(set_attr "type" "multi")
9324 (set_attr "length" "8")])
9326 (define_insn "tld_load"
9327 [(set (match_operand:SI 0 "register_operand" "=r")
9328 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
9329 (clobber (reg:SI 1))
9334 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
9336 [(set_attr "type" "multi")
9337 (set_attr "length" "8")])
9339 (define_insn "tld_load_pic"
9340 [(set (match_operand:SI 0 "register_operand" "=r")
9341 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
9342 (clobber (reg:SI 1))
9347 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
9349 [(set_attr "type" "multi")
9350 (set_attr "length" "8")])
9352 (define_insn "tld_offset_load"
9353 [(set (match_operand:SI 0 "register_operand" "=r")
9354 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
9356 (match_operand:SI 2 "register_operand" "r")))
9357 (clobber (reg:SI 1))]
9361 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
9363 [(set_attr "type" "multi")
9364 (set_attr "length" "8")])
9366 (define_insn "tp_load"
9367 [(set (match_operand:SI 0 "register_operand" "=r")
9368 (unspec:SI [(const_int 0)] UNSPEC_TP))]
9371 [(set_attr "type" "multi")
9372 (set_attr "length" "4")])
9374 (define_insn "tie_load"
9375 [(set (match_operand:SI 0 "register_operand" "=r")
9376 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
9377 (clobber (reg:SI 1))
9382 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
9384 [(set_attr "type" "multi")
9385 (set_attr "length" "8")])
9387 (define_insn "tie_load_pic"
9388 [(set (match_operand:SI 0 "register_operand" "=r")
9389 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
9390 (clobber (reg:SI 1))
9395 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
9397 [(set_attr "type" "multi")
9398 (set_attr "length" "8")])
9400 (define_insn "tle_load"
9401 [(set (match_operand:SI 0 "register_operand" "=r")
9402 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
9404 (match_operand:SI 2 "register_operand" "r")))
9405 (clobber (reg:SI 1))]
9407 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
9408 [(set_attr "type" "multi")
9409 (set_attr "length" "8")])