| blob | cba3c1a4d42c7d543e0ed96a7b41fcd9c925f245 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2015 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
99 /* Defined for convenience. */
100 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
102 /* Classifies an address.
104 ADDRESS_REG_IMM
105 A simple base register plus immediate offset.
107 ADDRESS_REG_WB
108 A base register indexed by immediate offset with writeback.
110 ADDRESS_REG_REG
111 A base register indexed by (optionally scaled) register.
113 ADDRESS_REG_UXTW
114 A base register indexed by (optionally scaled) zero-extended register.
116 ADDRESS_REG_SXTW
117 A base register indexed by (optionally scaled) sign-extended register.
119 ADDRESS_LO_SUM
120 A LO_SUM rtx with a base register and "LO12" symbol relocation.
122 ADDRESS_SYMBOLIC:
123 A constant symbolic address, in pc-relative literal pool. */
126 ADDRESS_REG_IMM,
127 ADDRESS_REG_WB,
128 ADDRESS_REG_REG,
129 ADDRESS_REG_UXTW,
130 ADDRESS_REG_SXTW,
131 ADDRESS_LO_SUM,
132 ADDRESS_SYMBOLIC
133 };
137 rtx base;
138 rtx offset;
141 };
143 struct simd_immediate_info
144 {
145 rtx value;
150 };
152 /* The current code model. */
155 #ifdef HAVE_AS_TLS
156 #undef TARGET_HAVE_TLS
157 #define TARGET_HAVE_TLS 1
158 #endif
162 const_tree,
174 /* Major revision number of the ARM Architecture implemented by the target. */
177 /* The processor for which instructions should be scheduled. */
180 /* The current tuning set. */
183 /* Mask to specify which instructions we are allowed to generate. */
186 /* Mask to specify which instruction scheduling options should be used. */
189 /* Tuning parameters. */
192 {
193 {
198 },
204 };
207 {
208 {
213 },
219 };
222 {
223 {
228 },
234 };
237 {
239 /* Avoid the use of slow int<->fp moves for spilling by setting
240 their cost higher than memmov_cost. */
244 };
247 {
249 /* Avoid the use of slow int<->fp moves for spilling by setting
250 their cost higher than memmov_cost. */
254 };
257 {
259 /* Avoid the use of slow int<->fp moves for spilling by setting
260 their cost higher than memmov_cost. */
264 };
267 {
272 };
275 {
277 /* Avoid the use of slow int<->fp moves for spilling by setting
278 their cost higher than memmov_cost. */
282 };
284 /* Generic costs for vector insn classes. */
286 {
299 };
301 /* Generic costs for vector insn classes. */
303 {
316 };
318 /* Generic costs for vector insn classes. */
320 {
333 };
335 #define AARCH64_FUSE_NOTHING (0)
336 #define AARCH64_FUSE_MOV_MOVK (1 << 0)
337 #define AARCH64_FUSE_ADRP_ADD (1 << 1)
338 #define AARCH64_FUSE_MOVK_MOVK (1 << 2)
339 #define AARCH64_FUSE_ADRP_LDR (1 << 3)
340 #define AARCH64_FUSE_CMP_BRANCH (1 << 4)
343 {
357 };
360 {
375 };
378 {
393 };
396 {
410 };
413 {
427 };
429 /* A processor implementing AArch64. */
430 struct processor
431 {
438 };
440 /* Processor cores implementing AArch64. */
442 {
443 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS) \
444 {NAME, SCHED, #ARCH, ARCH, FLAGS, &COSTS##_tunings},
446 #undef AARCH64_CORE
449 };
451 /* Architectures implementing AArch64. */
453 {
454 #define AARCH64_ARCH(NAME, CORE, ARCH, FLAGS) \
455 {NAME, CORE, #ARCH, ARCH, FLAGS, NULL},
457 #undef AARCH64_ARCH
459 };
461 /* Target specification. These are populated as commandline arguments
462 are processed, or NULL if not specified. */
467 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
469 /* An ISA extension in the co-processor and main instruction set space. */
470 struct aarch64_option_extension
471 {
475 };
477 /* ISA extensions in AArch64. */
479 {
480 #define AARCH64_OPT_EXTENSION(NAME, FLAGS_ON, FLAGS_OFF) \
481 {NAME, FLAGS_ON, FLAGS_OFF},
483 #undef AARCH64_OPT_EXTENSION
485 };
487 /* Used to track the size of an address when generating a pre/post
488 increment address. */
491 /* A table of valid AArch64 "bitmask immediate" values for
492 logical instructions. */
494 #define AARCH64_NUM_BITMASKS 5334
498 {
502 }
503 aarch64_cc;
505 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
507 /* The condition codes of the processor, and the inverse function. */
509 {
512 };
514 static unsigned int
516 {
518 }
520 static int
523 {
531 }
533 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
534 unsigned
536 {
544 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
545 equivalent DWARF register. */
547 }
549 /* Return TRUE if MODE is any of the large INT modes. */
550 static bool
552 {
554 }
556 /* Return TRUE if MODE is any of the vector modes. */
557 static bool
559 {
562 }
564 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
565 static bool
568 {
575 }
577 /* Implement HARD_REGNO_NREGS. */
579 int
581 {
583 {
589 }
591 }
593 /* Implement HARD_REGNO_MODE_OK. */
595 int
597 {
602 /* The purpose of comparing with ptr_mode is to support the
603 global register variable associated with the stack pointer
604 register via the syntax of asm ("wsp") in ILP32. */
614 {
616 return
618 else
620 }
623 }
625 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
626 machine_mode
628 machine_mode mode)
629 {
630 /* Handle modes that fit within single registers. */
632 {
635 else
637 }
638 /* Fall back to generic for multi-reg and very large modes. */
639 else
641 }
643 /* Return true if calls to DECL should be treated as
644 long-calls (ie called via a register). */
645 static bool
647 {
649 }
651 /* Return true if calls to symbol-ref SYM should be treated as
652 long-calls (ie called via a register). */
653 bool
655 {
657 }
659 /* Return true if the offsets to a zero/sign-extract operation
660 represent an expression that matches an extend operation. The
661 operands represent the paramters from
663 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
664 bool
666 rtx extract_imm)
667 {
684 }
686 /* Emit an insn that's a simple single-set. Both the operands must be
687 known to be valid. */
690 {
692 }
694 /* X and Y are two things to compare using CODE. Emit the compare insn and
695 return the rtx for register 0 in the proper mode. */
696 rtx
698 {
704 }
706 /* Build the SYMBOL_REF for __tls_get_addr. */
710 rtx
712 {
716 }
718 /* Return the TLS model to use for ADDR. */
720 static enum tls_model
722 {
727 {
731 }
736 }
738 /* We'll allow lo_sum's in addresses in our legitimate addresses
739 so that combine would take care of combining addresses where
740 necessary, but for generation purposes, we'll generate the address
741 as :
742 RTL Absolute
743 tmp = hi (symbol_ref); adrp x1, foo
744 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
745 nop
747 PIC TLS
748 adrp x1, :got:foo adrp tmp, :tlsgd:foo
749 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
750 bl __tls_get_addr
751 nop
753 Load TLS symbol, depending on TLS mechanism and TLS access model.
755 Global Dynamic - Traditional TLS:
756 adrp tmp, :tlsgd:imm
757 add dest, tmp, #:tlsgd_lo12:imm
758 bl __tls_get_addr
760 Global Dynamic - TLS Descriptors:
761 adrp dest, :tlsdesc:imm
762 ldr tmp, [dest, #:tlsdesc_lo12:imm]
763 add dest, dest, #:tlsdesc_lo12:imm
764 blr tmp
765 mrs tp, tpidr_el0
766 add dest, dest, tp
768 Initial Exec:
769 mrs tp, tpidr_el0
770 adrp tmp, :gottprel:imm
771 ldr dest, [tmp, #:gottprel_lo12:imm]
772 add dest, dest, tp
774 Local Exec:
775 mrs tp, tpidr_el0
776 add t0, tp, #:tprel_hi12:imm, lsl #12
777 add t0, t0, #:tprel_lo12_nc:imm
778 */
780 static void
783 {
785 {
787 {
788 /* In ILP32, the mode of dest can be either SImode or DImode. */
800 }
807 {
808 /* In ILP32, the mode of dest can be either SImode or DImode,
809 while the got entry is always of SImode size. The mode of
810 dest depends on how dest is used: if dest is assigned to a
811 pointer (e.g. in the memory), it has SImode; it may have
812 DImode if dest is dereferenced to access the memeory.
813 This is why we have to handle three different ldr_got_small
814 patterns here (two patterns for ILP32). */
823 {
826 else
828 }
829 else
830 {
833 }
836 }
839 {
851 }
854 {
857 rtx tp;
861 /* In ILP32, the got entry is always of SImode size. Unlike
862 small GOT, the dest is fixed at reg 0. */
865 else
875 }
878 {
879 /* In ILP32, the mode of dest can be either SImode or DImode,
880 while the got entry is always of SImode size. The mode of
881 dest depends on how dest is used: if dest is assigned to a
882 pointer (e.g. in the memory), it has SImode; it may have
883 DImode if dest is dereferenced to access the memeory.
884 This is why we have to handle three different tlsie_small
885 patterns here (two patterns for ILP32). */
891 {
894 else
895 {
898 }
899 }
900 else
901 {
904 }
909 }
912 {
921 }
929 }
930 }
932 /* Emit a move from SRC to DEST. Assume that the move expanders can
933 handle all moves if !can_create_pseudo_p (). The distinction is
934 important because, unlike emit_move_insn, the move expanders know
935 how to force Pmode objects into the constant pool even when the
936 constant pool address is not itself legitimate. */
937 static rtx
939 {
943 }
945 /* Split a 128-bit move operation into two 64-bit move operations,
946 taking care to handle partial overlap of register to register
947 copies. Special cases are needed when moving between GP regs and
948 FP regs. SRC can be a register, constant or memory; DST a register
949 or memory. If either operand is memory it must not have any side
950 effects. */
951 void
953 {
964 {
968 /* Handle FP <-> GP regs. */
970 {
975 {
978 }
979 else
980 {
983 }
985 }
987 {
992 {
995 }
996 else
997 {
1000 }
1002 }
1003 }
1010 /* At most one pairing may overlap. */
1012 {
1015 }
1016 else
1017 {
1020 }
1021 }
1023 bool
1025 {
1028 }
1030 /* Split a complex SIMD combine. */
1032 void
1034 {
1041 {
1045 {
1066 }
1070 }
1071 }
1073 /* Split a complex SIMD move. */
1075 void
1077 {
1084 {
1090 {
1111 }
1115 }
1116 }
1118 static rtx
1120 {
1123 else
1124 {
1127 }
1128 }
1131 static rtx
1133 {
1135 {
1136 rtx high;
1137 /* Load the full offset into a register. This
1138 might be improvable in the future. */
1144 }
1146 }
1148 static int
1150 machine_mode mode)
1151 {
1157 rtx subtarget;
1162 {
1165 num_insns++;
1167 }
1170 {
1171 /* We know we can't do this in 1 insn, and we must be able to do it
1172 in two; so don't mess around looking for sequences that don't buy
1173 us anything. */
1175 {
1180 }
1183 }
1185 /* Remaining cases are all for DImode. */
1196 {
1198 one_match++;
1199 else
1200 {
1204 zero_match++;
1205 }
1206 }
1209 {
1210 /* Set one of the quarters and then insert back into result. */
1213 {
1218 }
1221 }
1228 {
1232 {
1234 {
1240 }
1243 }
1245 {
1247 {
1253 }
1256 }
1258 {
1260 {
1266 }
1269 }
1271 {
1273 {
1279 }
1282 }
1283 }
1285 /* See if we can do it by arithmetically combining two
1286 immediates. */
1288 {
1294 {
1296 {
1302 }
1305 }
1308 {
1310 {
1312 {
1317 }
1320 }
1321 }
1322 }
1324 /* See if we can do it by logically combining two immediates. */
1326 {
1328 {
1333 {
1335 {
1341 }
1344 }
1345 }
1347 {
1352 {
1354 {
1360 }
1363 }
1364 }
1365 }
1368 {
1369 /* Set either first three quarters or all but the third. */
1374 num_insns ++;
1376 /* Now insert other two quarters. */
1379 {
1381 {
1385 num_insns ++;
1386 }
1387 }
1389 }
1391 simple_sequence:
1395 {
1397 {
1399 {
1403 num_insns ++;
1405 }
1406 else
1407 {
1411 num_insns ++;
1412 }
1413 }
1414 }
1417 }
1420 void
1422 {
1427 /* Check on what type of symbol it is. */
1431 {
1435 /* If we have (const (plus symbol offset)), separate out the offset
1436 before we start classifying the symbol. */
1441 {
1445 {
1451 }
1465 {
1471 }
1472 /* FALLTHRU */
1482 }
1483 }
1486 {
1489 else
1490 {
1494 }
1497 }
1500 }
1502 static bool
1504 tree exp ATTRIBUTE_UNUSED)
1505 {
1506 /* Currently, always true. */
1508 }
1510 /* Implement TARGET_PASS_BY_REFERENCE. */
1512 static bool
1514 machine_mode mode,
1515 const_tree type,
1517 {
1518 HOST_WIDE_INT size;
1519 machine_mode dummymode;
1522 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
1526 /* Aggregates are passed by reference based on their size. */
1528 {
1530 }
1532 /* Variable sized arguments are always returned by reference. */
1536 /* Can this be a candidate to be passed in fp/simd register(s)? */
1539 NULL))
1542 /* Arguments which are variable sized or larger than 2 registers are
1543 passed by reference unless they are a homogenous floating point
1544 aggregate. */
1546 }
1548 /* Return TRUE if VALTYPE is padded to its least significant bits. */
1549 static bool
1551 {
1552 machine_mode dummy_mode;
1555 /* Never happens in little-endian mode. */
1559 /* Only composite types smaller than or equal to 16 bytes can
1560 be potentially returned in registers. */
1566 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
1567 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
1568 is always passed/returned in the least significant bits of fp/simd
1569 register(s). */
1575 }
1577 /* Implement TARGET_FUNCTION_VALUE.
1578 Define how to find the value returned by a function. */
1580 static rtx
1583 {
1584 machine_mode mode;
1587 machine_mode ag_mode;
1594 {
1598 {
1601 }
1602 }
1606 {
1608 {
1611 }
1612 else
1613 {
1615 rtx par;
1619 {
1624 }
1626 }
1627 }
1628 else
1630 }
1632 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
1633 Return true if REGNO is the number of a hard register in which the values
1634 of called function may come back. */
1636 static bool
1638 {
1639 /* Maximum of 16 bytes can be returned in the general registers. Examples
1640 of 16-byte return values are: 128-bit integers and 16-byte small
1641 structures (excluding homogeneous floating-point aggregates). */
1645 /* Up to four fp/simd registers can return a function value, e.g. a
1646 homogeneous floating-point aggregate having four members. */
1651 }
1653 /* Implement TARGET_RETURN_IN_MEMORY.
1655 If the type T of the result of a function is such that
1656 void func (T arg)
1657 would require that arg be passed as a value in a register (or set of
1658 registers) according to the parameter passing rules, then the result
1659 is returned in the same registers as would be used for such an
1660 argument. */
1662 static bool
1664 {
1665 HOST_WIDE_INT size;
1666 machine_mode ag_mode;
1672 /* Simple scalar types always returned in registers. */
1676 type,
1679 NULL))
1682 /* Types larger than 2 registers returned in memory. */
1685 }
1687 static bool
1690 {
1693 type,
1695 nregs,
1696 NULL);
1697 }
1699 /* Given MODE and TYPE of a function argument, return the alignment in
1700 bits. The idea is to suppress any stronger alignment requested by
1701 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
1702 This is a helper function for local use only. */
1704 static unsigned int
1706 {
1710 {
1712 {
1715 else
1717 }
1718 else
1720 }
1721 else
1725 }
1727 /* Layout a function argument according to the AAPCS64 rules. The rule
1728 numbers refer to the rule numbers in the AAPCS64. */
1730 static void
1732 const_tree type,
1734 {
1738 HOST_WIDE_INT size;
1740 /* We need to do this once per argument. */
1746 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
1747 size
1749 UNITS_PER_WORD);
1753 mode,
1754 type,
1757 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
1758 The following code thus handles passing by SIMD/FP registers first. */
1762 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
1763 and homogenous short-vector aggregates (HVA). */
1765 {
1767 {
1770 {
1773 }
1774 else
1775 {
1776 rtx par;
1780 {
1783 tmp = gen_rtx_EXPR_LIST
1787 }
1789 }
1791 }
1792 else
1793 {
1794 /* C.3 NSRN is set to 8. */
1797 }
1798 }
1803 /* C6 - C9. though the sign and zero extension semantics are
1804 handled elsewhere. This is the case where the argument fits
1805 entirely general registers. */
1807 {
1812 /* C.8 if the argument has an alignment of 16 then the NGRN is
1813 rounded up to the next even number. */
1815 {
1818 }
1819 /* NREGS can be 0 when e.g. an empty structure is to be passed.
1820 A reg is still generated for it, but the caller should be smart
1821 enough not to use it. */
1823 {
1825 }
1826 else
1827 {
1828 rtx par;
1833 {
1838 }
1840 }
1844 }
1846 /* C.11 */
1849 /* The argument is passed on stack; record the needed number of words for
1850 this argument and align the total size if necessary. */
1851 on_stack:
1857 }
1859 /* Implement TARGET_FUNCTION_ARG. */
1861 static rtx
1864 {
1873 }
1875 void
1877 const_tree fntype ATTRIBUTE_UNUSED,
1878 rtx libname ATTRIBUTE_UNUSED,
1879 const_tree fndecl ATTRIBUTE_UNUSED,
1881 {
1893 }
1895 static void
1897 machine_mode mode,
1898 const_tree type,
1900 {
1903 {
1913 }
1914 }
1916 bool
1918 {
1921 }
1923 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
1924 PARM_BOUNDARY bits of alignment, but will be given anything up
1925 to STACK_BOUNDARY bits if the type requires it. This makes sure
1926 that both before and after the layout of each argument, the Next
1927 Stacked Argument Address (NSAA) will have a minimum alignment of
1928 8 bytes. */
1930 static unsigned int
1932 {
1940 }
1942 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
1944 Return true if an argument passed on the stack should be padded upwards,
1945 i.e. if the least-significant byte of the stack slot has useful data.
1947 Small aggregate types are placed in the lowest memory address.
1949 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
1951 bool
1953 {
1954 /* On little-endian targets, the least significant byte of every stack
1955 argument is passed at the lowest byte address of the stack slot. */
1959 /* Otherwise, integral, floating-point and pointer types are padded downward:
1960 the least significant byte of a stack argument is passed at the highest
1961 byte address of the stack slot. */
1968 /* Everything else padded upward, i.e. data in first byte of stack slot. */
1970 }
1972 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
1974 It specifies padding for the last (may also be the only)
1975 element of a block move between registers and memory. If
1976 assuming the block is in the memory, padding upward means that
1977 the last element is padded after its highest significant byte,
1978 while in downward padding, the last element is padded at the
1979 its least significant byte side.
1981 Small aggregates and small complex types are always padded
1982 upwards.
1984 We don't need to worry about homogeneous floating-point or
1985 short-vector aggregates; their move is not affected by the
1986 padding direction determined here. Regardless of endianness,
1987 each element of such an aggregate is put in the least
1988 significant bits of a fp/simd register.
1990 Return !BYTES_BIG_ENDIAN if the least significant byte of the
1991 register has useful data, and return the opposite if the most
1992 significant byte does. */
1994 bool
1997 {
1999 /* Small composite types are always padded upward. */
2001 {
2006 }
2008 /* Otherwise, use the default padding. */
2010 }
2012 static machine_mode
2014 {
2016 }
2018 static bool
2020 {
2021 /* In aarch64_override_options_after_change
2022 flag_omit_leaf_frame_pointer turns off the frame pointer by
2023 default. Turn it back on now if we've not got a leaf
2024 function. */
2030 }
2032 /* Mark the registers that need to be saved by the callee and calculate
2033 the size of the callee-saved registers area and frame record (both FP
2034 and LR may be omitted). */
2035 static void
2037 {
2044 #define SLOT_NOT_REQUIRED (-2)
2045 #define SLOT_REQUIRED (-1)
2050 /* First mark all the registers that really need to be saved... */
2057 /* ... that includes the eh data registers (if needed)... */
2063 /* ... and any callee saved register that dataflow says is live. */
2076 {
2077 /* FP and LR are placed in the linkage record. */
2084 }
2086 /* Now assign stack slots for them. */
2089 {
2096 }
2100 {
2108 }
2128 }
2130 static bool
2132 {
2134 }
2136 static unsigned
2138 {
2140 regno ++;
2142 }
2144 static void
2146 HOST_WIDE_INT adjustment)
2147 {
2158 }
2160 static rtx
2162 HOST_WIDE_INT adjustment)
2163 {
2165 {
2176 }
2177 }
2179 static void
2182 {
2192 }
2194 static rtx
2196 HOST_WIDE_INT adjustment)
2197 {
2199 {
2208 }
2209 }
2211 static rtx
2213 rtx reg2)
2214 {
2216 {
2225 }
2226 }
2228 static rtx
2230 rtx mem2)
2231 {
2233 {
2242 }
2243 }
2246 static void
2249 {
2259 {
2261 HOST_WIDE_INT offset;
2271 offset));
2279 {
2281 rtx mem2;
2285 offset));
2287 reg2));
2289 /* The first part of a frame-related parallel insn is
2290 always assumed to be relevant to the frame
2291 calculations; subsequent parts, are only
2292 frame-related if explicitly marked. */
2295 }
2296 else
2300 }
2301 }
2303 static void
2307 {
2313 HOST_WIDE_INT offset;
2318 {
2335 {
2337 rtx mem2;
2345 }
2346 else
2349 }
2350 }
2352 /* AArch64 stack frames generated by this compiler look like:
2354 +-------------------------------+
2355 | |
2356 | incoming stack arguments |
2357 | |
2358 +-------------------------------+
2359 | | <-- incoming stack pointer (aligned)
2360 | callee-allocated save area |
2361 | for register varargs |
2362 | |
2363 +-------------------------------+
2364 | local variables | <-- frame_pointer_rtx
2365 | |
2366 +-------------------------------+
2367 | padding0 | \
2368 +-------------------------------+ |
2369 | callee-saved registers | | frame.saved_regs_size
2370 +-------------------------------+ |
2371 | LR' | |
2372 +-------------------------------+ |
2373 | FP' | / <- hard_frame_pointer_rtx (aligned)
2374 +-------------------------------+
2375 | dynamic allocation |
2376 +-------------------------------+
2377 | padding |
2378 +-------------------------------+
2379 | outgoing stack arguments | <-- arg_pointer
2380 | |
2381 +-------------------------------+
2382 | | <-- stack_pointer_rtx (aligned)
2384 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
2385 but leave frame_pointer_rtx and hard_frame_pointer_rtx
2386 unchanged. */
2388 /* Generate the prologue instructions for entry into a function.
2389 Establish the stack frame by decreasing the stack pointer with a
2390 properly calculated size and, if necessary, create a frame record
2391 filled with the values of LR and previous frame pointer. The
2392 current FP is also set up if it is in use. */
2394 void
2396 {
2397 /* sub sp, sp, #<frame_size>
2398 stp {fp, lr}, [sp, #<frame_size> - 16]
2399 add fp, sp, #<frame_size> - hardfp_offset
2400 stp {cs_reg}, [fp, #-16] etc.
2402 sub sp, sp, <final_adjustment_if_any>
2403 */
2406 HOST_WIDE_INT hard_fp_offset;
2418 /* Store pairs and load pairs have a range only -512 to 504. */
2420 {
2421 /* When the frame has a large size, an initial decrease is done on
2422 the stack pointer to jump over the callee-allocated save area for
2423 register varargs, the local variable area and/or the callee-saved
2424 register area. This will allow the pre-index write-back
2425 store pair instructions to be used for setting up the stack frame
2426 efficiently. */
2435 {
2445 }
2447 {
2452 {
2456 }
2458 {
2462 }
2463 }
2464 }
2465 else
2469 {
2473 {
2477 {
2484 }
2485 else
2488 /* Set up frame pointer to point to the location of the
2489 previous frame pointer on the stack. */
2491 stack_pointer_rtx,
2495 }
2496 else
2497 {
2505 {
2509 }
2510 else
2511 {
2518 else
2520 }
2521 }
2524 skip_wb);
2526 skip_wb);
2527 }
2529 /* when offset >= 512,
2530 sub sp, sp, #<outgoing_args_size> */
2532 {
2534 {
2539 }
2540 }
2541 }
2543 /* Return TRUE if we can use a simple_return insn.
2545 This function checks whether the callee saved stack is empty, which
2546 means no restore actions are need. The pro_and_epilogue will use
2547 this to check whether shrink-wrapping opt is feasible. */
2549 bool
2551 {
2561 }
2563 /* Generate the epilogue instructions for returning from a function. */
2564 void
2566 {
2568 HOST_WIDE_INT fp_offset;
2569 HOST_WIDE_INT hard_fp_offset;
2571 /* We need to add memory barrier to prevent read from deallocated stack. */
2581 /* Store pairs and load pairs have a range only -512 to 504. */
2583 {
2591 {
2596 }
2597 }
2598 else
2601 /* If there were outgoing arguments or we've done dynamic stack
2602 allocation, then restore the stack pointer from the frame
2603 pointer. This is at most one insn and more efficient than using
2604 GCC's internal mechanism. */
2607 {
2612 hard_frame_pointer_rtx,
2615 }
2618 {
2641 {
2647 {
2652 }
2653 else
2654 {
2661 }
2662 }
2663 else
2664 {
2667 }
2669 /* Reset the CFA to be SP + FRAME_SIZE. */
2676 }
2679 {
2684 {
2688 }
2689 else
2690 {
2695 {
2700 }
2703 }
2705 /* Reset the CFA to be SP + 0. */
2708 }
2710 /* Stack adjustment for exception handler. */
2712 {
2713 /* We need to unwind the stack by the offset computed by
2714 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
2715 to be SP; letting the CFA move during this adjustment
2716 is just as correct as retaining the CFA from the body
2717 of the function. Therefore, do nothing special. */
2719 }
2724 }
2726 /* Return the place to copy the exception unwinding return address to.
2727 This will probably be a stack slot, but could (in theory be the
2728 return register). */
2729 rtx
2731 {
2732 HOST_WIDE_INT fp_offset;
2742 /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can
2743 result in a store to save LR introduced by builtin_eh_return () being
2744 incorrectly deleted because the alias is not detected.
2745 So in the calculation of the address to copy the exception unwinding
2746 return address to, we note 2 cases.
2747 If FP is needed and the fp_offset is 0, it means that SP = FP and hence
2748 we return a SP-relative location since all the addresses are SP-relative
2749 in this case. This prevents the store from being optimized away.
2750 If the fp_offset is not 0, then the addresses will be FP-relative and
2751 therefore we return a FP-relative location. */
2754 {
2758 else
2761 }
2763 /* If FP is not needed, we calculate the location of LR, which would be
2764 at the top of the saved registers block. */
2768 stack_pointer_rtx,
2769 fp_offset
2772 }
2774 /* Possibly output code to build up a constant in a register. For
2775 the benefit of the costs infrastructure, returns the number of
2776 instructions which would be emitted. GENERATE inhibits or
2777 enables code generation. */
2779 static int
2781 {
2785 {
2789 }
2790 else
2791 {
2796 HOST_WIDE_INT valm;
2797 HOST_WIDE_INT tval;
2800 {
2810 }
2812 /* zcount contains the number of additional MOVK instructions
2813 required if the constant is built up with an initial MOVZ instruction,
2814 while ncount is the number of MOVK instructions required if starting
2815 with a MOVN instruction. Choose the sequence that yields the fewest
2816 number of instructions, preferring MOVZ instructions when they are both
2817 the same. */
2819 {
2824 insns++;
2825 }
2826 else
2827 {
2832 insns++;
2833 }
2838 {
2840 {
2845 insns++;
2846 }
2848 }
2849 }
2851 }
2853 static void
2855 {
2864 {
2867 }
2869 {
2871 {
2877 else
2880 }
2882 {
2886 }
2887 }
2888 }
2890 /* Output code to add DELTA to the first argument, and then jump
2891 to FUNCTION. Used for C++ multiple inheritance. */
2892 static void
2894 HOST_WIDE_INT delta,
2895 HOST_WIDE_INT vcall_offset,
2896 tree function)
2897 {
2898 /* The this pointer is always in x0. Note that this differs from
2899 Arm where the this pointer maybe bumped to r1 if r0 is required
2900 to return a pointer to an aggregate. On AArch64 a result value
2901 pointer will be in x8. */
2911 else
2912 {
2921 {
2925 else
2927 }
2931 else
2938 else
2939 {
2942 }
2946 else
2952 }
2954 /* Generate a tail call to the target function. */
2956 {
2959 }
2971 /* Stop pretending to be a post-reload pass. */
2973 }
2975 static bool
2977 {
2982 {
2986 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
2987 TLS offsets, not real symbol references. */
2990 }
2992 }
2995 static int
2997 {
3006 }
3009 static void
3011 {
3017 {
3021 else
3024 {
3026 {
3027 /* set s consecutive bits to 1 (s < 64) */
3029 /* rotate right by r */
3032 /* replicate the constant depending on SIMD size */
3043 }
3046 }
3047 }
3048 }
3052 aarch64_bitmasks_cmp);
3053 }
3056 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3057 a left shift of 0 or 12 bits. */
3058 bool
3060 {
3063 );
3064 }
3067 /* Return true if val is an immediate that can be loaded into a
3068 register by a MOVZ instruction. */
3069 static bool
3071 {
3073 {
3077 }
3078 else
3079 {
3080 /* Ignore sign extension. */
3082 }
3085 }
3088 /* Return true if val is a valid bitmask immediate. */
3089 bool
3091 {
3093 {
3094 /* Replicate bit pattern. */
3097 }
3100 }
3103 /* Return true if val is an immediate that can be loaded into a
3104 register in a single instruction. */
3105 bool
3107 {
3111 }
3113 static bool
3115 {
3123 {
3127 else
3128 /* Avoid generating a 64-bit relocation in ILP32; leave
3129 to aarch64_expand_mov_immediate to handle it properly. */
3131 }
3134 }
3136 /* Return true if register REGNO is a valid index register.
3137 STRICT_P is true if REG_OK_STRICT is in effect. */
3139 bool
3141 {
3143 {
3151 }
3153 }
3155 /* Return true if register REGNO is a valid base register for mode MODE.
3156 STRICT_P is true if REG_OK_STRICT is in effect. */
3158 bool
3160 {
3162 {
3170 }
3172 /* The fake registers will be eliminated to either the stack or
3173 hard frame pointer, both of which are usually valid base registers.
3174 Reload deals with the cases where the eliminated form isn't valid. */
3179 }
3181 /* Return true if X is a valid base register for mode MODE.
3182 STRICT_P is true if REG_OK_STRICT is in effect. */
3184 static bool
3186 {
3191 }
3193 /* Return true if address offset is a valid index. If it is, fill in INFO
3194 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
3196 static bool
3199 {
3201 rtx index;
3204 /* (reg:P) */
3207 {
3211 }
3212 /* (sign_extend:DI (reg:SI)) */
3217 {
3222 }
3223 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
3230 {
3235 }
3236 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
3243 {
3248 }
3249 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
3256 {
3264 }
3265 /* (and:DI (mult:DI (reg:DI) (const_int scale))
3266 (const_int 0xffffffff<<shift)) */
3273 {
3279 }
3280 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
3287 {
3295 }
3296 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
3297 (const_int 0xffffffff<<shift)) */
3304 {
3310 }
3311 /* (mult:P (reg:P) (const_int scale)) */
3316 {
3320 }
3321 /* (ashift:P (reg:P) (const_int shift)) */
3326 {
3330 }
3331 else
3342 {
3347 }
3350 }
3352 bool
3354 {
3358 }
3362 HOST_WIDE_INT offset)
3363 {
3365 }
3369 {
3373 }
3375 /* Return true if X is a valid address for machine mode MODE. If it is,
3376 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
3377 effect. OUTER_CODE is PARALLEL for a load/store pair. */
3379 static bool
3383 {
3387 /* On BE, we use load/store pair for all large int mode load/stores. */
3389 || (BYTES_BIG_ENDIAN
3393 !load_store_pair_p
3397 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
3398 REG addressing. */
3404 {
3422 {
3428 }
3433 {
3440 /* TImode and TFmode values are allowed in both pairs of X
3441 registers and individual Q registers. The available
3442 address modes are:
3443 X,X: 7-bit signed scaled offset
3444 Q: 9-bit signed offset
3445 We conservatively require an offset representable in either mode.
3446 */
3451 /* A 7bit offset check because OImode will emit a ldp/stp
3452 instruction (only big endian will get here).
3453 For ldp/stp instructions, the offset is scaled for the size of a
3454 single element of the pair. */
3458 /* Three 9/12 bit offsets checks because CImode will emit three
3459 ldr/str instructions (only big endian will get here). */
3466 /* Two 7bit offsets checks because XImode will emit two ldp/stp
3467 instructions (only big endian will get here). */
3476 else
3479 }
3482 {
3483 /* Look for base + (scaled/extended) index register. */
3486 {
3489 }
3492 {
3495 }
3496 }
3517 {
3518 HOST_WIDE_INT offset;
3522 /* TImode and TFmode values are allowed in both pairs of X
3523 registers and individual Q registers. The available
3524 address modes are:
3525 X,X: 7-bit signed scaled offset
3526 Q: 9-bit signed offset
3527 We conservatively require an offset representable in either mode.
3528 */
3536 else
3538 }
3544 /* load literal: pc-relative constant pool entry. Only supported
3545 for SI mode or larger. */
3549 {
3556 }
3565 {
3571 {
3572 /* The symbol and offset must be aligned to the access size. */
3579 {
3583 }
3589 else
3598 }
3599 }
3604 }
3605 }
3607 bool
3609 {
3610 rtx offset;
3614 }
3616 /* Classify the base of symbolic expression X, given that X appears in
3617 context CONTEXT. */
3619 enum aarch64_symbol_type
3622 {
3623 rtx offset;
3627 }
3630 /* Return TRUE if X is a legitimate address for accessing memory in
3631 mode MODE. */
3632 static bool
3634 {
3638 }
3640 /* Return TRUE if X is a legitimate address for accessing memory in
3641 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
3642 pair operation. */
3643 bool
3646 {
3650 }
3652 /* Return TRUE if rtx X is immediate constant 0.0 */
3653 bool
3655 {
3656 REAL_VALUE_TYPE r;
3665 }
3667 /* Return the fixed registers used for condition codes. */
3669 static bool
3671 {
3675 }
3677 /* Emit call insn with PAT and do aarch64-specific handling. */
3679 void
3681 {
3687 }
3689 machine_mode
3691 {
3692 /* All floating point compares return CCFP if it is an equality
3693 comparison, and CCFPE otherwise. */
3695 {
3697 {
3718 }
3719 }
3728 /* A compare with a shifted operand. Because of canonicalization,
3729 the comparison will have to be swapped when we emit the assembly
3730 code. */
3738 /* Similarly for a negated operand, but we can only do this for
3739 equalities. */
3746 /* A compare of a mode narrower than SI mode against zero can be done
3747 by extending the value in the comparison. */
3750 /* Only use sign-extension if we really need it. */
3754 /* For everything else, return CCmode. */
3756 }
3758 static int
3761 int
3763 {
3770 }
3772 static int
3774 {
3777 {
3781 {
3795 }
3850 {
3862 }
3869 {
3881 }
3886 {
3892 }
3897 {
3901 }
3907 }
3916 }
3918 bool
3920 HOST_WIDE_INT minval,
3921 HOST_WIDE_INT maxval)
3922 {
3923 HOST_WIDE_INT firstval;
3940 }
3942 bool
3944 {
3946 }
3948 static unsigned
3950 {
3954 {
3955 count++;
3957 }
3960 }
3962 /* N Z C V. */
3963 #define AARCH64_CC_V 1
3964 #define AARCH64_CC_C (1 << 1)
3965 #define AARCH64_CC_Z (1 << 2)
3966 #define AARCH64_CC_N (1 << 3)
3968 /* N Z C V flags for ccmp. The first code is for AND op and the other
3969 is for IOR op. Indexed by AARCH64_COND_CODE. */
3971 {
3988 };
3990 int
3992 {
3994 {
4027 }
4028 }
4031 void
4033 {
4035 {
4036 /* An integer or symbol address without a preceding # sign. */
4039 {
4051 {
4054 }
4055 /* Fall through. */
4059 }
4063 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4064 {
4069 {
4072 }
4075 {
4088 }
4089 }
4093 {
4096 /* Print N such that 2^N == X. */
4098 {
4101 }
4104 }
4108 /* Print the number of non-zero bits in X (a const_int). */
4110 {
4113 }
4119 /* Print the higher numbered register of a pair (TImode) of regs. */
4121 {
4124 }
4130 {
4132 /* Print a condition (eq, ne, etc). */
4134 /* CONST_TRUE_RTX means always -- that's the default. */
4139 {
4142 }
4147 }
4151 {
4153 /* Print the inverse of a condition (eq <-> ne, etc). */
4155 /* CONST_TRUE_RTX means never -- that's the default. */
4157 {
4160 }
4163 {
4166 }
4171 }
4179 /* Print a scalar FP/SIMD register name. */
4181 {
4182 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4184 }
4192 /* Print the first FP/SIMD register name in a list. */
4194 {
4195 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4197 }
4202 /* Print a scalar FP/SIMD register name + 1. */
4204 {
4205 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4207 }
4212 /* Print bottom 16 bits of integer constant in hex. */
4214 {
4217 }
4223 /* Print a general register name or the zero register (32-bit or
4224 64-bit). */
4227 {
4230 }
4233 {
4236 }
4239 {
4242 }
4244 /* Fall through */
4247 /* Print a normal operand, if it's a general register, then we
4248 assume DImode. */
4250 {
4253 }
4256 {
4277 {
4280 HOST_WIDE_INT_MIN,
4281 HOST_WIDE_INT_MAX));
4283 }
4285 {
4287 }
4288 else
4293 /* CONST_DOUBLE can represent a double-width integer.
4294 In this case, the mode of x is VOIDmode. */
4298 {
4301 }
4303 {
4304 #define buf_size 20
4306 REAL_VALUE_TYPE r;
4313 #undef buf_size
4314 }
4320 }
4328 {
4355 }
4361 {
4388 }
4395 {
4401 }
4406 {
4408 /* Print nzcv. */
4411 {
4414 }
4419 }
4423 {
4425 /* Print nzcv. */
4428 {
4431 }
4436 }
4442 }
4443 }
4445 void
4447 {
4453 {
4457 else
4466 else
4475 else
4484 else
4491 {
4518 }
4529 }
4532 }
4534 bool
4536 {
4543 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
4544 referencing instruction, but they are constant offsets, not
4545 symbols. */
4551 {
4553 {
4559 }
4562 }
4565 }
4567 /* Implement REGNO_REG_CLASS. */
4569 enum reg_class
4571 {
4586 }
4588 static rtx
4590 {
4591 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
4592 where mask is selected by alignment and size of the offset.
4593 We try to pick as large a range for the offset as possible to
4594 maximize the chance of a CSE. However, for aligned addresses
4595 we limit the range to 4k so that structures with different sized
4596 elements are likely to use the same base. */
4599 {
4601 HOST_WIDE_INT base_offset;
4603 /* Does it look like we'll need a load/store-pair operation? */
4608 /* For offsets aren't a multiple of the access size, the limit is
4609 -256...255. */
4612 else
4621 NULL_RTX);
4624 }
4627 }
4629 /* Try a machine-dependent way of reloading an illegitimate address
4630 operand. If we find one, push the reload and return the new rtx. */
4632 rtx
4634 machine_mode mode,
4637 {
4640 /* Do not allow mem (plus (reg, const)) if vector struct mode. */
4645 {
4652 }
4654 /* We must recognize output that we have already generated ourselves. */
4660 {
4665 }
4667 /* We wish to handle large displacements off a base register by splitting
4668 the addend across an add and the mem insn. This can cut the number of
4669 extra insns needed from 3 to 1. It is only useful for load/store of a
4670 single register with 12 bit offset field. */
4678 {
4682 HOST_WIDE_INT offs;
4683 rtx cst;
4686 /* In ILP32, xmode can be either DImode or SImode. */
4689 /* Reload non-zero BLKmode offsets. This is because we cannot ascertain
4690 BLKmode alignment. */
4696 /* Align misaligned offset by adjusting high part to compensate. */
4698 {
4700 {
4701 /* Align down. */
4704 }
4705 else
4706 {
4707 /* Align up. */
4712 }
4713 }
4715 /* Check for overflow. */
4723 /* Reload high part into base reg, leaving the low part
4724 in the mem instruction.
4725 Note that replacing this gen_rtx_PLUS with plus_constant is
4726 wrong in this case because we rely on the
4727 (plus (plus reg c1) c2) structure being preserved so that
4728 XEXP (*p, 0) in push_reload below uses the correct term. */
4737 }
4740 }
4743 static reg_class_t
4745 reg_class_t rclass,
4746 machine_mode mode,
4748 {
4749 /* Without the TARGET_SIMD instructions we cannot move a Q register
4750 to a Q register directly. We need a scratch. */
4754 {
4760 }
4762 /* A TFmode or TImode memory access should be handled via an FP_REGS
4763 because AArch64 has richer addressing modes for LDR/STR instructions
4764 than LDP/STP instructions. */
4773 }
4775 static bool
4777 {
4778 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
4779 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
4782 {
4794 }
4795 else
4796 {
4797 /* If we decided that we didn't need a leaf frame pointer but then used
4798 LR in the function, then we'll want a frame pointer after all, so
4799 prevent this elimination to ensure a frame pointer is used. */
4801 && flag_omit_leaf_frame_pointer
4804 }
4807 }
4809 HOST_WIDE_INT
4811 {
4815 {
4822 }
4825 {
4829 }
4832 }
4834 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
4835 previous frame. */
4837 rtx
4839 {
4843 }
4846 static void
4848 {
4850 {
4853 }
4854 else
4855 {
4858 }
4863 }
4865 static void
4867 {
4871 /* Don't need to copy the trailing D-words, we fill those in below. */
4883 /* XXX We should really define a "clear_cache" pattern and use
4884 gen_clear_cache(). */
4889 ptr_mode);
4890 }
4892 static unsigned char
4894 {
4896 {
4903 return
4914 }
4916 }
4918 static reg_class_t
4920 {
4925 {
4931 }
4933 /* If it's an integer immediate that MOVI can't handle, then
4934 FP_REGS is not an option, so we return NO_REGS instead. */
4939 /* Register eliminiation can result in a request for
4940 SP+constant->FP_REGS. We cannot support such operations which
4941 use SP as source and an FP_REG as destination, so reject out
4942 right now. */
4944 {
4947 /* Look through a possible SUBREG introduced by ILP32. */
4953 POINTER_REGS));
4955 }
4958 }
4960 void
4962 {
4964 }
4966 static void
4968 {
4971 else
4972 {
4980 }
4981 }
4983 static void
4985 {
4988 else
4989 {
4997 }
4998 }
5002 {
5008 {
5009 {
5012 },
5013 {
5016 },
5017 {
5020 },
5021 /* We assume that DImode is only generated when not optimizing and
5022 that we don't really need 64-bit address offsets. That would
5023 imply an object file with 8GB of code in a single function! */
5024 {
5027 }
5028 };
5036 /* Need to implement table size reduction, by chaning the code below. */
5046 }
5049 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5050 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5051 operator. */
5053 int
5055 {
5057 {
5060 {
5064 }
5065 }
5067 }
5069 static bool
5071 const_rtx x ATTRIBUTE_UNUSED)
5072 {
5073 /* We can't use blocks for constants when we're using a per-function
5074 constant pool. */
5076 }
5080 rtx x ATTRIBUTE_UNUSED,
5082 {
5083 /* Force all constant pool entries into the current function section. */
5085 }
5088 /* Costs. */
5090 /* Helper function for rtx cost calculation. Strip a shift expression
5091 from X. Returns the inner operand if successful, or the original
5092 expression on failure. */
5093 static rtx
5095 {
5098 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5099 we can convert both to ROR during final output. */
5114 }
5116 /* Helper function for rtx cost calculation. Strip an extend
5117 expression from X. Returns the inner operand if successful, or the
5118 original expression on failure. We deal with a number of possible
5119 canonicalization variations here. */
5120 static rtx
5122 {
5125 /* Zero and sign extraction of a widened value. */
5133 /* It can also be represented (for zero-extend) as an AND with an
5134 immediate. */
5143 /* Now handle extended register, as this may also have an optional
5144 left shift by 1..4. */
5158 }
5160 /* Helper function for rtx cost calculation. Calculate the cost of
5161 a MULT, which may be part of a multiply-accumulate rtx. Return
5162 the calculated cost of the expression, recursing manually in to
5163 operands where needed. */
5165 static int
5167 {
5183 /* Integer multiply/fma. */
5185 {
5186 /* The multiply will be canonicalized as a shift, cost it as such. */
5189 {
5191 {
5193 /* ADD (shifted register). */
5195 else
5196 /* LSL (immediate). */
5198 }
5203 }
5205 /* Integer multiplies or FMAs have zero/sign extending variants. */
5210 {
5215 {
5217 /* MADD/SMADDL/UMADDL. */
5219 else
5220 /* MUL/SMULL/UMULL. */
5222 }
5225 }
5227 /* This is either an integer multiply or an FMA. In both cases
5228 we want to recurse and cost the operands. */
5233 {
5235 /* MADD. */
5237 else
5238 /* MUL. */
5240 }
5243 }
5244 else
5245 {
5247 {
5248 /* Floating-point FMA/FMUL can also support negations of the
5249 operands. */
5256 /* FMADD/FNMADD/FNMSUB/FMSUB. */
5258 else
5259 /* FMUL/FNMUL. */
5261 }
5266 }
5267 }
5269 static int
5271 machine_mode mode,
5272 addr_space_t as ATTRIBUTE_UNUSED,
5274 {
5282 {
5284 {
5285 /* This is a CONST or SYMBOL ref which will be split
5286 in a different way depending on the code model in use.
5287 Cost it through the generic infrastructure. */
5289 /* Divide through by the cost of one instruction to
5290 bring it to the same units as the address costs. */
5292 /* The cost is then the cost of preparing the address,
5293 followed by an immediate (possibly 0) offset. */
5295 }
5296 else
5297 {
5298 /* This is most likely a jump table from a case
5299 statement. */
5301 }
5302 }
5305 {
5317 else
5333 }
5337 {
5338 /* For the sake of calculating the cost of the shifted register
5339 component, we can treat same sized modes in the same way. */
5341 {
5354 /* We can't tell, or this is a 128-bit vector. */
5358 }
5359 }
5362 }
5364 /* Return true if the RTX X in mode MODE is a zero or sign extract
5365 usable in an ADD or SUB (extended register) instruction. */
5366 static bool
5368 {
5369 /* Catch add with a sign extract.
5370 This is add_<optab><mode>_multp2. */
5373 {
5384 op1))
5385 {
5387 }
5388 }
5391 }
5393 static bool
5395 {
5397 {
5409 }
5410 }
5412 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
5413 storing it in *COST. Result is true if the total cost of the operation
5414 has now been calculated. */
5415 static bool
5417 {
5418 rtx inner;
5419 rtx comparator;
5423 {
5427 }
5428 else
5429 {
5433 }
5436 {
5437 /* Conditional branch. */
5440 else
5441 {
5443 {
5445 {
5446 /* TBZ/TBNZ/CBZ/CBNZ. */
5448 /* TBZ/TBNZ. */
5451 else
5452 /* CBZ/CBNZ. */
5456 }
5457 }
5459 {
5460 /* TBZ/TBNZ. */
5463 }
5464 }
5465 }
5467 {
5468 /* It's a conditional operation based on the status flags,
5469 so it must be some flavor of CSEL. */
5471 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
5480 }
5482 /* We don't know what this is, cost all operands. */
5484 }
5486 /* Calculate the cost of calculating X, storing it in *COST. Result
5487 is true if the total cost of the operation has now been calculated. */
5488 static bool
5491 {
5497 /* By default, assume that everything has equivalent cost to the
5498 cheapest instruction. Any additional costs are applied as a delta
5499 above this default. */
5502 /* TODO: The cost infrastructure currently does not handle
5503 vector operations. Assume that all vector operations
5504 are equally expensive. */
5506 {
5510 }
5513 {
5515 /* The cost depends entirely on the operands to SET. */
5521 {
5524 {
5536 }
5545 /* Fall through. */
5547 /* const0_rtx is in general free, but we will use an
5548 instruction to set a register to 0. */
5550 {
5551 /* The cost is 1 per register copied. */
5555 }
5556 else
5557 /* Cost is just the cost of the RHS of the set. */
5563 /* Bit-field insertion. Strip any redundant widening of
5564 the RHS to meet the width of the target. */
5575 {
5576 /* MOV immediate is assumed to always be cheap. */
5578 }
5579 else
5580 {
5581 /* BFM. */
5585 }
5590 /* We can't make sense of this, assume default cost. */
5593 }
5597 /* If an instruction can incorporate a constant within the
5598 instruction, the instruction's expression avoids calling
5599 rtx_cost() on the constant. If rtx_cost() is called on a
5600 constant, then it is usually because the constant must be
5601 moved into a register by one or more instructions.
5603 The exception is constant 0, which can be expressed
5604 as XZR/WZR and is therefore free. The exception to this is
5605 if we have (set (reg) (const0_rtx)) in which case we must cost
5606 the move. However, we can catch that when we cost the SET, so
5607 we don't need to consider that here. */
5610 else
5611 {
5612 /* To an approximation, building any other constant is
5613 proportionally expensive to the number of instructions
5614 required to build that constant. This is true whether we
5615 are compiling for SPEED or otherwise. */
5618 }
5623 {
5624 /* mov[df,sf]_aarch64. */
5626 /* FMOV (scalar immediate). */
5629 {
5630 /* This will be a load from memory. */
5633 else
5635 }
5636 else
5637 /* Otherwise this is +0.0. We get this using MOVI d0, #0
5638 or MOV v0.s[0], wzr - neither of which are modeled by the
5639 cost tables. Just use the default cost. */
5640 {
5641 }
5642 }
5648 {
5649 /* For loads we want the base cost of a load, plus an
5650 approximation for the additional cost of the addressing
5651 mode. */
5663 }
5671 {
5674 {
5675 /* CSETM. */
5678 }
5680 /* Cost this as SUB wzr, X. */
5684 }
5687 {
5688 /* Support (neg(fma...)) as a single instruction only if
5689 sign of zeros is unimportant. This matches the decision
5690 making in aarch64.md. */
5692 {
5693 /* FNMADD. */
5696 }
5698 /* FNEG. */
5701 }
5718 {
5721 }
5724 {
5725 /* TODO: A write to the CC flags possibly costs extra, this
5726 needs encoding in the cost tables. */
5728 /* CC_ZESWPmode supports zero extend for free. */
5732 /* ANDS. */
5734 {
5737 }
5740 {
5741 /* ADDS (and CMN alias). */
5744 }
5747 {
5748 /* SUBS. */
5751 }
5754 {
5755 /* CMN. */
5762 }
5764 /* CMP.
5766 Compare can freely swap the order of operands, and
5767 canonicalization puts the more complex operation first.
5768 But the integer MINUS logic expects the shift/extend
5769 operation in op1. */
5772 {
5775 }
5777 }
5780 {
5781 /* FCMP. */
5786 {
5787 /* FCMP supports constant 0.0 for no extra cost. */
5789 }
5791 }
5796 {
5800 cost_minus:
5801 /* Detect valid immediates. */
5807 {
5811 /* SUB(S) (immediate). */
5815 }
5817 /* Look for SUB (extended register). */
5819 {
5827 }
5831 /* Cost this as an FMA-alike operation. */
5835 {
5838 speed);
5841 }
5846 {
5848 /* SUB(S). */
5851 /* FSUB. */
5853 }
5855 }
5858 {
5859 rtx new_op0;
5864 cost_plus:
5867 {
5868 /* CSINC. */
5872 }
5877 {
5881 /* ADD (immediate). */
5884 }
5886 /* Look for ADD (extended register). */
5888 {
5896 }
5898 /* Strip any extend, leave shifts behind as we will
5899 cost them through mult_cost. */
5904 {
5906 speed);
5909 }
5915 {
5917 /* ADD. */
5920 /* FADD. */
5922 }
5924 }
5936 {
5943 }
5944 /* Fall through. */
5947 cost_logic:
5957 {
5958 /* This is a UBFM/SBFM. */
5963 }
5966 {
5967 /* We possibly get the immediate for free, this is not
5968 modelled. */
5971 {
5978 }
5979 else
5980 {
5983 /* Handle ORN, EON, or BIC. */
5989 /* If we had a shift on op0 then this is a logical-shift-
5990 by-register/immediate operation. Otherwise, this is just
5991 a logical operation. */
5993 {
5995 {
5996 /* Shift by immediate. */
5999 else
6001 }
6002 else
6004 }
6006 /* In both cases we want to cost both operands. */
6011 }
6012 }
6016 /* MVN. */
6020 /* The logical instruction could have the shifted register form,
6021 but the cost is the same if the shift is processed as a separate
6022 instruction, so we don't bother with it here. */
6028 /* If a value is written in SI mode, then zero extended to DI
6029 mode, the operation will in general be free as a write to
6030 a 'w' register implicitly zeroes the upper bits of an 'x'
6031 register. However, if this is
6033 (set (reg) (zero_extend (reg)))
6035 we must cost the explicit register move. */
6039 {
6043 /* MOV. */
6045 else
6046 /* Free, the cost is that of the SI mode operation. */
6050 }
6052 {
6053 /* All loads can zero extend to any size for free. */
6056 }
6058 /* UXTB/UXTH. */
6066 {
6067 /* LDRSH. */
6069 {
6076 }
6078 }
6089 {
6090 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
6091 aliases. */
6095 /* We can incorporate zero/sign extend for free. */
6102 }
6103 else
6104 {
6105 /* LSLV. */
6110 }
6120 {
6121 /* ASR (immediate) and friends. */
6127 }
6128 else
6129 {
6131 /* ASR (register) and friends. */
6136 }
6141 {
6142 /* LDR. */
6145 }
6148 {
6149 /* ADRP, followed by ADD. */
6153 }
6156 {
6157 /* ADR. */
6160 }
6163 {
6164 /* One extra load instruction, after accessing the GOT. */
6168 }
6173 /* ADRP/ADD (immediate). */
6180 /* UBFX/SBFX. */
6184 /* We can trust that the immediates used will be correct (there
6185 are no by-register forms), so we need only cost op0. */
6191 /* aarch64_rtx_mult_cost always handles recursion to its
6192 operands. */
6198 {
6208 }
6215 {
6217 /* There is no integer SQRT, so only DIV and UDIV can get
6218 here. */
6220 else
6222 }
6250 /* FMSUB, FNMADD, and FNMSUB are free. */
6257 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
6258 and the by-element operand as operand 0. */
6262 /* Catch vector-by-element operations. The by-element operand can
6263 either be (vec_duplicate (vec_select (x))) or just
6264 (vec_select (x)), depending on whether we are multiplying by
6265 a vector or a scalar.
6267 Canonicalization is not very good in these cases, FMA4 will put the
6268 by-element operand as operand 0, FNMA4 will have it as operand 1. */
6279 /* If the remaining parameters are not registers,
6280 get the cost to put them into registers. */
6299 /* Strip the rounding part. They will all be implemented
6300 by the fcvt* family of instructions anyway. */
6302 {
6311 }
6321 {
6322 /* FABS and FNEG are analogous. */
6325 }
6326 else
6327 {
6328 /* Integer ABS will either be split to
6329 two arithmetic instructions, or will be an ABS
6330 (scalar), which we don't model. */
6334 }
6340 {
6341 /* FMAXNM/FMINNM/FMAX/FMIN.
6342 TODO: This may not be accurate for all implementations, but
6343 we do not model this in the cost tables. */
6345 }
6349 /* The floating point round to integer frint* instructions. */
6351 {
6356 }
6359 {
6364 }
6369 /* Decompose <su>muldi3_highpart. */
6371 mode == DImode
6372 /* (lshiftrt:TI */
6375 /* (mult:TI */
6377 /* (ANY_EXTEND:TI (reg:DI))
6378 (ANY_EXTEND:TI (reg:DI))) */
6385 /* (const_int 64) */
6388 {
6389 /* UMULH/SMULH. */
6397 }
6399 /* Fall through. */
6402 }
6409 }
6411 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
6412 calculated for X. This cost is stored in *COST. Returns true
6413 if the total cost of X was calculated. */
6414 static bool
6417 {
6421 {
6426 }
6429 }
6431 static int
6434 {
6440 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
6447 /* Moving between GPR and stack cost is the same as GP2GP. */
6452 /* To/From the stack register, we move via the gprs. */
6458 {
6459 /* 128-bit operations on general registers require 2 instructions. */
6467 /* When AdvSIMD instructions are disabled it is not possible to move
6468 a 128-bit value directly between Q registers. This is handled in
6469 secondary reload. A general register is used as a scratch to move
6470 the upper DI value and the lower DI value is moved directly,
6471 hence the cost is the sum of three moves. */
6476 }
6486 }
6488 static int
6490 reg_class_t rclass ATTRIBUTE_UNUSED,
6492 {
6494 }
6496 /* Return the number of instructions that can be issued per cycle. */
6497 static int
6499 {
6501 }
6503 static int
6505 {
6509 }
6511 /* Vectorizer cost model target hooks. */
6513 /* Implement targetm.vectorize.builtin_vectorization_cost. */
6514 static int
6516 tree vectype,
6518 {
6522 {
6569 }
6570 }
6572 /* Implement targetm.vectorize.add_stmt_cost. */
6573 static unsigned
6577 {
6582 {
6587 /* Statements in an inner loop relative to the loop being
6588 vectorized are weighted more heavily. The value here is
6589 a function (linear for now) of the loop nest level. */
6591 {
6597 }
6601 }
6604 }
6608 /* Parse the architecture extension string. */
6610 static void
6612 {
6613 /* The extension string is parsed left to right. */
6616 /* Flag to say whether we are adding or removing an extension. */
6620 {
6624 str++;
6629 else
6633 {
6637 }
6642 {
6646 }
6648 /* Scan over the extensions table trying to find an exact match. */
6650 {
6652 {
6653 /* Add or remove the extension. */
6656 else
6659 }
6660 }
6663 {
6664 /* Extension not found in list. */
6667 }
6670 };
6673 }
6675 /* Parse the ARCH string. */
6677 static void
6679 {
6691 else
6695 {
6698 }
6700 /* Loop through the list of supported ARCHs to find a match. */
6702 {
6704 {
6712 {
6713 /* ARCH string contains at least one extension. */
6715 }
6718 {
6721 }
6724 }
6725 }
6727 /* ARCH name not found in list. */
6730 }
6732 /* Parse the CPU string. */
6734 static void
6736 {
6748 else
6752 {
6755 }
6757 /* Loop through the list of supported CPUs to find a match. */
6759 {
6761 {
6766 {
6767 /* CPU string contains at least one extension. */
6769 }
6772 }
6773 }
6775 /* CPU name not found in list. */
6778 }
6780 /* Parse the TUNE string. */
6782 static void
6784 {
6789 /* Loop through the list of supported CPUs to find a match. */
6791 {
6793 {
6796 }
6797 }
6799 /* CPU name not found in list. */
6802 }
6805 /* Implement TARGET_OPTION_OVERRIDE. */
6807 static void
6809 {
6810 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
6811 If either of -march or -mtune is given, they override their
6812 respective component of -mcpu.
6814 So, first parse AARCH64_CPU_STRING, then the others, be careful
6815 with -march as, if -mcpu is not present on the command line, march
6816 must set a sensible default CPU. */
6818 {
6820 }
6823 {
6825 }
6828 {
6830 }
6832 #ifndef HAVE_AS_MABI_OPTION
6833 /* The compiler may have been configured with 2.23.* binutils, which does
6834 not have support for ILP32. */
6837 #endif
6843 /* This target defaults to strict volatile bitfields. */
6847 /* If the user did not specify a processor, choose the default
6848 one for them. This will be the CPU set during configuration using
6849 --with-cpu, otherwise it is "generic". */
6851 {
6854 }
6867 {
6868 #ifdef TARGET_FIX_ERR_A53_835769_DEFAULT
6870 #else
6872 #endif
6873 }
6875 /* If not opzimizing for size, set the default
6876 alignment to what the target wants */
6878 {
6885 }
6888 }
6890 /* Implement targetm.override_options_after_change. */
6892 static void
6894 {
6899 }
6903 {
6907 }
6909 void
6911 {
6913 }
6915 /* A checking mechanism for the implementation of the various code models. */
6916 static void
6918 {
6920 {
6922 {
6934 }
6935 }
6936 else
6938 }
6940 /* Return true if SYMBOL_REF X binds locally. */
6942 static bool
6944 {
6948 }
6950 /* Return true if SYMBOL_REF X is thread local */
6951 static bool
6953 {
6961 }
6963 /* Classify a TLS symbol into one of the TLS kinds. */
6964 enum aarch64_symbol_type
6966 {
6970 {
6987 }
6988 }
6990 /* Return the method that should be used to access SYMBOL_REF or
6991 LABEL_REF X in context CONTEXT. */
6993 enum aarch64_symbol_type
6996 {
6998 {
7000 {
7014 }
7015 }
7018 {
7026 {
7028 /* When we retreive symbol + offset address, we have to make sure
7029 the offset does not cause overflow of the final address. But
7030 we have no way of knowing the address of symbol at compile time
7031 so we can't accurately say if the distance between the PC and
7032 symbol + offset is outside the addressible range of +/-1M in the
7033 TINY code model. So we rely on images not being greater than
7034 1M and cap the offset at 1M and anything beyond 1M will have to
7035 be loaded using an alternative mechanism. */
7042 /* Same reasoning as the tiny code model, but the offset cap here is
7043 4G. */
7062 }
7063 }
7065 /* By default push everything into the constant pool. */
7067 }
7069 bool
7071 {
7073 }
7075 bool
7077 {
7085 }
7087 /* Return true if X holds either a quarter-precision or
7088 floating-point +0.0 constant. */
7089 static bool
7091 {
7095 /* TODO: We could handle moving 0.0 to a TFmode register,
7096 but first we would like to refactor the movtf_aarch64
7097 to be more amicable to split moves properly and
7098 correctly gate on TARGET_SIMD. For now - reject all
7099 constants which are not to SFmode or DFmode registers. */
7106 }
7108 static bool
7110 {
7111 /* Do not allow vector struct mode constants. We could support
7112 0 and -1 easily, but they need support in aarch64-simd.md. */
7116 /* This could probably go away because
7117 we now decompose CONST_INTs according to expand_mov_immediate. */
7128 }
7130 rtx
7132 {
7138 /* Can return in any reg. */
7141 }
7143 /* On AAPCS systems, this is the "struct __va_list". */
7146 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
7147 Return the type to use as __builtin_va_list.
7149 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
7151 struct __va_list
7152 {
7153 void *__stack;
7154 void *__gr_top;
7155 void *__vr_top;
7156 int __gr_offs;
7157 int __vr_offs;
7158 }; */
7160 static tree
7162 {
7163 tree va_list_name;
7166 /* Create the type. */
7168 /* Give it the required name. */
7170 TYPE_DECL,
7172 va_list_type);
7177 /* Create the fields. */
7180 ptr_type_node);
7183 ptr_type_node);
7186 ptr_type_node);
7189 integer_type_node);
7192 integer_type_node);
7212 /* Compute its layout. */
7216 }
7218 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
7219 static void
7221 {
7225 tree t;
7231 gr_save_area_size
7233 vr_save_area_size
7237 {
7242 }
7251 NULL_TREE);
7253 NULL_TREE);
7255 NULL_TREE);
7257 NULL_TREE);
7259 NULL_TREE);
7261 /* Emit code to initialize STACK, which points to the next varargs stack
7262 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
7263 by named arguments. STACK is 8-byte aligned. */
7270 /* Emit code to initialize GRTOP, the top of the GR save area.
7271 virtual_incoming_args_rtx should have been 16 byte aligned. */
7276 /* Emit code to initialize VRTOP, the top of the VR save area.
7277 This address is gr_save_area_bytes below GRTOP, rounded
7278 down to the next 16-byte boundary. */
7288 /* Emit code to initialize GROFF, the offset from GRTOP of the
7289 next GPR argument. */
7294 /* Likewise emit code to initialize VROFF, the offset from FTOP
7295 of the next VR argument. */
7299 }
7301 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
7303 static tree
7306 {
7307 tree addr;
7313 machine_mode mode;
7340 type,
7344 {
7345 /* TYPE passed in fp/simd registers. */
7358 {
7361 }
7364 {
7366 }
7367 }
7368 else
7369 {
7370 /* TYPE passed in general registers. */
7383 {
7385 }
7386 }
7388 /* Get a local temporary for the field value. */
7391 /* Emit code to branch if off >= 0. */
7397 {
7398 /* Emit: offs = (offs + 15) & -16. */
7404 }
7405 else
7408 /* Update ap.__[g|v]r_offs */
7413 /* String up. */
7417 /* [cond2] if (ap.__[g|v]r_offs > 0) */
7422 /* String up: make sure the assignment happens before the use. */
7426 /* Prepare the trees handling the argument that is passed on the stack;
7427 the top level node will store in ON_STACK. */
7430 {
7431 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
7439 }
7440 else
7442 /* Advance ap.__stack */
7450 /* String up roundup and advance. */
7453 /* String up with arg */
7455 /* Big-endianness related address adjustment. */
7458 {
7462 }
7467 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
7477 {
7478 /* type ha; // treat as "struct {ftype field[n];}"
7479 ... [computing offs]
7480 for (i = 0; i <nregs; ++i, offs += 16)
7481 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
7482 return ha; */
7486 /* Declare a local variable. */
7490 /* Establish the base type. */
7492 {
7505 /* The half precision and quad precision are not fully supported yet. Enable
7506 the following code after the support is complete. Need to find the correct
7507 type node for __fp16 *. */
7508 #if 0
7513 #endif
7516 {
7520 }
7524 }
7526 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
7534 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
7536 {
7546 }
7550 }
7560 }
7562 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
7564 static void
7568 {
7570 CUMULATIVE_ARGS local_cum;
7573 /* The caller has advanced CUM up to, but not beyond, the last named
7574 argument. Advance a local copy of CUM past the last "real" named
7575 argument, to find out how many registers are left over. */
7579 /* Found out how many registers we need to save. */
7584 {
7589 }
7592 {
7594 {
7597 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
7605 }
7607 {
7608 /* We can't use move_block_from_reg, because it will use
7609 the wrong mode, storing D regs only. */
7613 /* Set OFF to the offset from virtual_incoming_args_rtx of
7614 the first vector register. The VR save area lies below
7615 the GR one, and is aligned to 16 bytes. */
7621 {
7629 }
7630 }
7631 }
7633 /* We don't save the size into *PRETEND_SIZE because we want to avoid
7634 any complication of having crtl->args.pretend_args_size changed. */
7639 }
7641 static void
7643 {
7646 {
7648 {
7651 }
7652 }
7653 }
7655 /* Walk down the type tree of TYPE counting consecutive base elements.
7656 If *MODEP is VOIDmode, then set it to the first valid floating point
7657 type. If a non-floating point type is found, or if a floating point
7658 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
7659 otherwise return the count in the sub-tree. */
7660 static int
7662 {
7663 machine_mode mode;
7664 HOST_WIDE_INT size;
7667 {
7695 /* Use V2SImode and V4SImode as representatives of all 64-bit
7696 and 128-bit vector types. */
7699 {
7708 }
7713 /* Vector modes are considered to be opaque: two vectors are
7714 equivalent for the purposes of being homogeneous aggregates
7715 if they are the same size. */
7722 {
7726 /* Can't handle incomplete types nor sizes that are not
7727 fixed. */
7734 || !index
7745 /* There must be no padding. */
7750 }
7753 {
7756 tree field;
7758 /* Can't handle incomplete types nor sizes that are not
7759 fixed. */
7765 {
7773 }
7775 /* There must be no padding. */
7780 }
7784 {
7785 /* These aren't very interesting except in a degenerate case. */
7788 tree field;
7790 /* Can't handle incomplete types nor sizes that are not
7791 fixed. */
7797 {
7805 }
7807 /* There must be no padding. */
7812 }
7816 }
7819 }
7821 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
7822 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
7823 array types. The C99 floating-point complex types are also considered
7824 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
7825 types, which are GCC extensions and out of the scope of AAPCS64, are
7826 treated as composite types here as well.
7828 Note that MODE itself is not sufficient in determining whether a type
7829 is such a composite type or not. This is because
7830 stor-layout.c:compute_record_mode may have already changed the MODE
7831 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
7832 structure with only one field may have its MODE set to the mode of the
7833 field. Also an integer mode whose size matches the size of the
7834 RECORD_TYPE type may be used to substitute the original mode
7835 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
7836 solely relied on. */
7838 static bool
7840 machine_mode mode)
7841 {
7851 }
7853 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
7854 type as described in AAPCS64 \S 4.1.2.
7856 See the comment above aarch64_composite_type_p for the notes on MODE. */
7858 static bool
7860 machine_mode mode)
7861 {
7872 }
7874 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
7875 shall be passed or returned in simd/fp register(s) (providing these
7876 parameter passing registers are available).
7878 Upon successful return, *COUNT returns the number of needed registers,
7879 *BASE_MODE returns the mode of the individual register and when IS_HAF
7880 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
7881 floating-point aggregate or a homogeneous short-vector aggregate. */
7883 static bool
7885 const_tree type,
7889 {
7897 {
7900 }
7902 {
7906 }
7908 {
7912 {
7915 }
7916 else
7918 }
7919 else
7924 }
7926 /* Implement TARGET_STRUCT_VALUE_RTX. */
7928 static rtx
7931 {
7933 }
7935 /* Implements target hook vector_mode_supported_p. */
7936 static bool
7938 {
7949 }
7951 /* Return appropriate SIMD container
7952 for MODE within a vector of WIDTH bits. */
7953 static machine_mode
7955 {
7958 {
7961 {
7976 }
7977 else
7979 {
7990 }
7991 }
7993 }
7995 /* Return 128-bit container as the preferred SIMD mode for MODE. */
7996 static machine_mode
7998 {
8000 }
8002 /* Return the bitmask of possible vector sizes for the vectorizer
8003 to iterate over. */
8004 static unsigned int
8006 {
8008 }
8010 /* Implement TARGET_MANGLE_TYPE. */
8014 {
8015 /* The AArch64 ABI documents say that "__va_list" has to be
8016 managled as if it is in the "std" namespace. */
8020 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
8021 builtin types. */
8025 /* Use the default mangling. */
8027 }
8030 /* Return true if the rtx_insn contains a MEM RTX somewhere
8031 in it. */
8033 static bool
8035 {
8042 }
8044 /* Find the first rtx_insn before insn that will generate an assembly
8045 instruction. */
8049 {
8053 do
8054 {
8056 }
8060 }
8062 static bool
8064 {
8066 /* A number of these may be AArch32 only. */
8071 };
8074 {
8077 }
8080 }
8082 /* Check if there is a register dependency between a load and the insn
8083 for which we hold recog_data. */
8085 static bool
8087 {
8088 rtx load_reg;
8098 {
8104 }
8106 }
8109 /* When working around the Cortex-A53 erratum 835769,
8110 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
8111 instruction and has a preceding memory instruction such that a NOP
8112 should be inserted between them. */
8114 bool
8116 {
8119 rtx body;
8132 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
8133 Restore recog state to INSN to avoid state corruption. */
8141 /* If the previous insn is a memory op and there is no dependency between
8142 it and the DImode madd, emit a NOP between them. If body is NULL then we
8143 have a complex memory operation, probably a load/store pair.
8144 Be conservative for now and emit a NOP. */
8151 }
8154 /* Implement FINAL_PRESCAN_INSN. */
8156 void
8158 {
8161 }
8164 /* Return the equivalent letter for size. */
8165 static char
8167 {
8169 {
8175 }
8176 }
8178 /* Return true iff x is a uniform vector of floating-point
8179 constants, and the constant can be represented in
8180 quarter-precision form. Note, as aarch64_float_const_representable
8181 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
8182 static bool
8184 {
8199 {
8207 }
8210 }
8212 /* Return true for valid and false for invalid. */
8213 bool
8216 {
8217 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
8218 matches = 1; \
8219 for (i = 0; i < idx; i += (STRIDE)) \
8220 if (!(TEST)) \
8221 matches = 0; \
8222 if (matches) \
8223 { \
8224 immtype = (CLASS); \
8225 elsize = (ELSIZE); \
8226 eshift = (SHIFT); \
8227 emvn = (NEG); \
8228 break; \
8229 }
8239 {
8245 {
8250 }
8253 }
8255 /* Splat vector constant out into a byte vector. */
8257 {
8258 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
8259 it must be laid out in the vector register in reverse order. */
8265 {
8268 }
8270 {
8273 }
8274 else
8278 {
8281 {
8284 }
8287 }
8288 }
8290 /* Sanity check. */
8293 do
8294 {
8343 }
8350 {
8360 /* Un-invert bytes of recognized vector, if necessary. */
8366 {
8367 /* FIXME: Broken on 32-bit H_W_I hosts. */
8376 }
8377 else
8378 {
8382 /* Construct 'abcdefgh' because the assembler cannot handle
8383 generic constants. */
8388 }
8389 }
8392 #undef CHECK
8393 }
8395 /* Check of immediate shift constants are within range. */
8396 bool
8398 {
8402 else
8404 }
8406 /* Return true if X is a uniform vector where all elements
8407 are either the floating-point constant 0.0 or the
8408 integer constant 0. */
8409 bool
8411 {
8413 }
8415 bool
8417 {
8422 {
8427 }
8430 }
8432 bool
8435 machine_mode mode)
8436 {
8449 }
8451 /* Return a const_int vector of VAL. */
8452 rtx
8454 {
8463 }
8465 /* Check OP is a legal scalar immediate for the MOVI instruction. */
8467 bool
8469 {
8470 machine_mode vmode;
8476 }
8478 /* Construct and return a PARALLEL RTX vector with elements numbering the
8479 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
8480 the vector - from the perspective of the architecture. This does not
8481 line up with GCC's perspective on lane numbers, so we end up with
8482 different masks depending on our target endian-ness. The diagram
8483 below may help. We must draw the distinction when building masks
8484 which select one half of the vector. An instruction selecting
8485 architectural low-lanes for a big-endian target, must be described using
8486 a mask selecting GCC high-lanes.
8488 Big-Endian Little-Endian
8490 GCC 0 1 2 3 3 2 1 0
8491 | x | x | x | x | | x | x | x | x |
8492 Architecture 3 2 1 0 3 2 1 0
8494 Low Mask: { 2, 3 } { 0, 1 }
8495 High Mask: { 0, 1 } { 2, 3 }
8496 */
8498 rtx
8500 {
8506 rtx t1;
8511 else
8519 }
8521 /* Check OP for validity as a PARALLEL RTX vector with elements
8522 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
8523 from the perspective of the architecture. See the diagram above
8524 aarch64_simd_vect_par_cnst_half for more details. */
8526 bool
8529 {
8542 {
8549 }
8551 }
8553 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
8554 HIGH (exclusive). */
8555 void
8557 const_tree exp)
8558 {
8559 HOST_WIDE_INT lane;
8564 {
8567 else
8569 }
8570 }
8572 /* Emit code to place a AdvSIMD pair result in memory locations (with equal
8573 registers). */
8574 void
8577 rtx op1)
8578 {
8588 }
8590 /* Return TRUE if OP is a valid vector addressing mode. */
8591 bool
8593 {
8596 }
8598 /* Emit a register copy from operand to operand, taking care not to
8599 early-clobber source registers in the process.
8601 COUNT is the number of components into which the copy needs to be
8602 decomposed. */
8603 void
8606 {
8616 else
8620 }
8622 /* Compute and return the length of aarch64_simd_mov<mode>, where <mode> is
8623 one of VSTRUCT modes: OI, CI or XI. */
8624 int
8626 {
8627 machine_mode mode;
8632 {
8635 {
8644 }
8645 }
8647 }
8649 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
8650 one of VSTRUCT modes: OI, CI, EI, or XI. */
8651 int
8653 {
8655 }
8657 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
8658 alignment of a vector to 128 bits. */
8659 static HOST_WIDE_INT
8661 {
8664 }
8666 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
8667 static bool
8669 {
8673 /* We guarantee alignment for vectors up to 128-bits. */
8678 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
8680 }
8682 /* If VALS is a vector constant that can be loaded into a register
8683 using DUP, generate instructions to do so and return an RTX to
8684 assign to the register. Otherwise return NULL_RTX. */
8685 static rtx
8687 {
8692 rtx x;
8699 {
8703 }
8708 /* We can load this constant by using DUP and a constant in a
8709 single ARM register. This will be cheaper than a vector
8710 load. */
8713 }
8716 /* Generate code to load VALS, which is a PARALLEL containing only
8717 constants (for vec_init) or CONST_VECTOR, efficiently into a
8718 register. Returns an RTX to copy into the register, or NULL_RTX
8719 for a PARALLEL that can not be converted into a CONST_VECTOR. */
8720 static rtx
8722 {
8724 rtx const_dup;
8733 {
8734 /* A CONST_VECTOR must contain only CONST_INTs and
8735 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
8736 Only store valid constants in a CONST_VECTOR. */
8738 {
8741 n_const++;
8742 }
8745 }
8746 else
8751 /* Load using MOVI/MVNI. */
8754 /* Loaded using DUP. */
8757 /* Load from constant pool. We can not take advantage of single-cycle
8758 LD1 because we need a PC-relative addressing mode. */
8760 else
8761 /* A PARALLEL containing something not valid inside CONST_VECTOR.
8762 We can not construct an initializer. */
8764 }
8766 void
8768 {
8782 {
8789 }
8792 {
8795 {
8798 }
8799 }
8801 /* Splat a single non-constant element if we can. */
8803 {
8807 }
8809 /* One field is non-constant. Load constant then overwrite varying
8810 field. This is more efficient than using the stack. */
8812 {
8817 /* Load constant part of vector, substitute neighboring value for
8818 varying element. */
8822 /* Insert variable. */
8828 }
8830 /* Construct the vector in memory one field at a time
8831 and load the whole vector. */
8839 }
8841 static unsigned HOST_WIDE_INT
8843 {
8844 return
8847 }
8849 #ifndef TLS_SECTION_ASM_FLAG
8851 #endif
8853 void
8855 tree decl ATTRIBUTE_UNUSED)
8856 {
8859 /* If we have already declared this section, we can use an
8860 abbreviated form to switch back to it -- unless this section is
8861 part of a COMDAT groups, in which case GAS requires the full
8862 declaration every time. */
8865 {
8868 }
8891 {
8897 else
8900 #ifdef TYPE_OPERAND_FMT
8902 #else
8904 #endif
8911 {
8914 else
8917 }
8918 }
8921 }
8923 /* Select a format to encode pointers in exception handling data. */
8924 int
8926 {
8929 {
8934 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
8935 for everything. */
8939 /* No assumptions here. 8-byte relocs required. */
8942 }
8944 }
8946 /* Emit load exclusive. */
8948 static void
8951 {
8955 {
8962 }
8965 }
8967 /* Emit store exclusive. */
8969 static void
8972 {
8976 {
8983 }
8986 }
8988 /* Mark the previous jump instruction as unlikely. */
8990 static void
8992 {
8997 }
8999 /* Expand a compare and swap pattern. */
9001 void
9003 {
9019 /* Normally the succ memory model must be stronger than fail, but in the
9020 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
9021 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
9028 {
9031 /* For short modes, we're going to perform the comparison in SImode,
9032 so do the zero-extension now. */
9036 /* Fall through. */
9040 /* Force the value into a register if needed. */
9047 }
9050 {
9057 }
9067 }
9069 /* Split a compare and swap pattern. */
9071 void
9073 {
9075 machine_mode mode;
9090 {
9093 }
9107 {
9112 }
9113 else
9114 {
9118 }
9121 }
9123 /* Split an atomic operation. */
9125 void
9128 {
9132 rtx x;
9141 else
9148 {
9162 {
9165 }
9166 /* Fall through. */
9172 }
9181 }
9183 static void
9185 {
9193 }
9195 static void
9197 {
9199 {
9202 }
9204 {
9209 }
9211 }
9213 /* Target hook for c_mode_for_suffix. */
9214 static machine_mode
9216 {
9221 }
9223 /* We can only represent floating point constants which will fit in
9224 "quarter-precision" values. These values are characterised by
9225 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
9226 by:
9228 (-1)^s * (n/16) * 2^r
9230 Where:
9231 's' is the sign bit.
9232 'n' is an integer in the range 16 <= n <= 31.
9233 'r' is an integer in the range -3 <= r <= 4. */
9235 /* Return true iff X can be represented by a quarter-precision
9236 floating point immediate operand X. Note, we cannot represent 0.0. */
9237 bool
9239 {
9240 /* This represents our current view of how many bits
9241 make up the mantissa. */
9256 /* We cannot represent infinities, NaNs or +/-zero. We won't
9257 know if we have +zero until we analyse the mantissa, but we
9258 can reject the other invalid values. */
9263 /* Extract exponent. */
9267 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
9268 highest (sign) bit, with a fixed binary point at bit point_pos.
9269 m1 holds the low part of the mantissa, m2 the high part.
9270 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
9271 bits for the mantissa, this can fail (low bits will be lost). */
9275 /* If the low part of the mantissa has bits set we cannot represent
9276 the value. */
9279 /* We have rejected the lower HOST_WIDE_INT, so update our
9280 understanding of how many bits lie in the mantissa and
9281 look only at the high HOST_WIDE_INT. */
9285 /* We can only represent values with a mantissa of the form 1.xxxx. */
9290 /* Having filtered unrepresentable values, we may now remove all
9291 but the highest 5 bits. */
9294 /* We cannot represent the value 0.0, so reject it. This is handled
9295 elsewhere. */
9299 /* Then, as bit 4 is always set, we can mask it off, leaving
9300 the mantissa in the range [0, 15]. */
9304 /* GCC internally does not use IEEE754-like encoding (where normalized
9305 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
9306 Our mantissa values are shifted 4 places to the left relative to
9307 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
9308 by 5 places to correct for GCC's representation. */
9312 }
9316 machine_mode mode,
9318 {
9328 /* This will return true to show const_vector is legal for use as either
9329 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
9330 also update INFO to show how the immediate should be generated. */
9339 {
9343 else
9344 {
9345 #define buf_size 20
9346 REAL_VALUE_TYPE r;
9350 #undef buf_size
9354 else
9358 }
9359 }
9371 else
9375 }
9379 machine_mode mode)
9380 {
9381 machine_mode vmode;
9387 }
9389 /* Split operands into moves from op[1] + op[2] into op[0]. */
9391 void
9393 {
9404 {
9405 /* No-op move. Can't split to nothing; emit something. */
9408 }
9410 /* Preserve register attributes for variable tracking. */
9415 /* Special case of reversed high/low parts. */
9418 {
9422 }
9424 {
9425 /* Try to avoid unnecessary moves if part of the result
9426 is in the right place already. */
9431 }
9432 else
9433 {
9438 }
9439 }
9441 /* vec_perm support. */
9443 #define MAX_VECT_LEN 16
9445 struct expand_vec_perm_d
9446 {
9449 machine_mode vmode;
9453 };
9455 /* Generate a variable permutation. */
9457 static void
9459 {
9470 {
9472 {
9473 /* Expand the argument to a V16QI mode by duplicating it. */
9477 }
9478 else
9479 {
9481 }
9482 }
9483 else
9484 {
9485 rtx pair;
9488 {
9492 }
9493 else
9494 {
9498 }
9499 }
9500 }
9502 void
9504 {
9508 rtx mask;
9510 /* The TBL instruction does not use a modulo index, so we must take care
9511 of that ourselves. */
9516 /* For big-endian, we also need to reverse the index within the vector
9517 (but not which vector). */
9519 {
9520 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
9525 }
9527 }
9529 /* Recognize patterns suitable for the TRN instructions. */
9530 static bool
9532 {
9541 /* Note that these are little-endian tests.
9542 We correct for big-endian later. */
9547 else
9552 {
9557 }
9559 /* Success! */
9566 {
9569 }
9573 {
9575 {
9588 }
9589 }
9590 else
9591 {
9593 {
9606 }
9607 }
9611 }
9613 /* Recognize patterns suitable for the UZP instructions. */
9614 static bool
9616 {
9625 /* Note that these are little-endian tests.
9626 We correct for big-endian later. */
9631 else
9636 {
9640 }
9642 /* Success! */
9649 {
9652 }
9656 {
9658 {
9671 }
9672 }
9673 else
9674 {
9676 {
9689 }
9690 }
9694 }
9696 /* Recognize patterns suitable for the ZIP instructions. */
9697 static bool
9699 {
9708 /* Note that these are little-endian tests.
9709 We correct for big-endian later. */
9712 /* Do Nothing. */
9713 ;
9716 else
9721 {
9728 }
9730 /* Success! */
9737 {
9740 }
9744 {
9746 {
9759 }
9760 }
9761 else
9762 {
9764 {
9777 }
9778 }
9782 }
9784 /* Recognize patterns for the EXT insn. */
9786 static bool
9788 {
9791 rtx offset;
9795 /* Check if the extracted indices are increasing by one. */
9797 {
9800 {
9801 /* We'll pass the same vector in twice, so allow indices to wrap. */
9803 }
9806 }
9809 {
9822 }
9824 /* Success! */
9828 /* The case where (location == 0) is a no-op for both big- and little-endian,
9829 and is removed by the mid-end at optimization levels -O1 and higher. */
9832 {
9833 /* After setup, we want the high elements of the first vector (stored
9834 at the LSB end of the register), and the low elements of the second
9835 vector (stored at the MSB end of the register). So swap. */
9837 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
9839 }
9844 }
9846 /* Recognize patterns for the REV insns. */
9848 static bool
9850 {
9859 {
9862 {
9867 }
9871 {
9878 }
9882 {
9893 }
9897 }
9901 {
9902 /* This is guaranteed to be true as the value of diff
9903 is 7, 3, 1 and we should have enough elements in the
9904 queue to generate this. Getting a vector mask with a
9905 value of diff other than these values implies that
9906 something is wrong by the time we get here. */
9910 }
9912 /* Success! */
9918 }
9920 static bool
9922 {
9925 rtx in0;
9928 rtx lane;
9932 {
9935 }
9937 /* The generic preparation in aarch64_expand_vec_perm_const_1
9938 swaps the operand order and the permute indices if it finds
9939 d->perm[0] to be in the second operand. Thus, we can always
9940 use d->op0 and need not do any extra arithmetic to get the
9941 correct lane number. */
9946 {
9959 }
9963 }
9965 static bool
9967 {
9975 /* Generic code will try constant permutation twice. Once with the
9976 original mode and again with the elements lowered to QImode.
9977 So wait and don't do the selector expansion ourselves. */
9982 {
9985 /* If big-endian and two vectors we end up with a weird mixed-endian
9986 mode on NEON. Reverse the index within each word but not the word
9987 itself. */
9990 }
9996 }
9998 static bool
10000 {
10001 /* The pattern matching functions above are written to look for a small
10002 number to begin the sequence (0, 1, N/2). If we begin with an index
10003 from the second operand, we can swap the operands. */
10005 {
10013 }
10016 {
10030 }
10032 }
10034 /* Expand a vec_perm_const pattern. */
10036 bool
10038 {
10052 {
10057 }
10060 {
10069 /* The elements of PERM do not suggest that only the first operand
10070 is used, but both operands are identical. Allow easier matching
10071 of the permutation by folding the permutation into the single
10072 input vector. */
10073 /* Fall Through. */
10085 }
10088 }
10090 static bool
10093 {
10103 /* Calculate whether all elements are in one vector. */
10105 {
10109 }
10111 /* If all elements are from the second vector, reindex as if from the
10112 first vector. */
10117 /* Check whether the mask can be applied to a single vector. */
10130 }
10132 rtx
10134 {
10135 /* We have to reverse each vector because we dont have
10136 a permuted load that can reverse-load according to ABI rules. */
10137 rtx mask;
10151 }
10153 /* Implement MODES_TIEABLE_P. */
10155 bool
10157 {
10161 /* We specifically want to allow elements of "structure" modes to
10162 be tieable to the structure. This more general condition allows
10163 other rarer situations too. */
10170 }
10172 /* Return a new RTX holding the result of moving POINTER forward by
10173 AMOUNT bytes. */
10175 static rtx
10177 {
10182 }
10184 /* Return a new RTX holding the result of moving POINTER forward by the
10185 size of the mode it points to. */
10187 static rtx
10189 {
10193 }
10195 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
10196 MODE bytes. */
10198 static void
10200 machine_mode mode)
10201 {
10204 /* "Cast" the pointers to the correct mode. */
10207 /* Emit the memcpy. */
10210 /* Move the pointers forward. */
10213 }
10215 /* Expand movmem, as if from a __builtin_memcpy. Return true if
10216 we succeed, otherwise return false. */
10218 bool
10220 {
10224 rtx base;
10227 /* When optimizing for size, give a better estimate of the length of a
10228 memcpy call, but use the default otherwise. */
10231 /* We can't do anything smart if the amount to copy is not constant. */
10237 /* Try to keep the number of instructions low. For cases below 16 bytes we
10238 need to make at most two moves. For cases above 16 bytes it will be one
10239 move for each 16 byte chunk, then at most two additional moves. */
10249 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
10250 1-byte chunk. */
10252 {
10254 {
10257 }
10263 }
10265 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
10266 4-byte chunk, partially overlapping with the previously copied chunk. */
10268 {
10272 {
10278 }
10280 }
10282 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
10283 them, then (if applicable) an 8-byte chunk. */
10285 {
10287 {
10290 }
10291 else
10292 {
10295 }
10296 }
10298 /* Finish the final bytes of the copy. We can always do this in one
10299 instruction. We either copy the exact amount we need, or partially
10300 overlap with the previous chunk we copied and copy 8-bytes. */
10309 else
10310 {
10312 {
10316 }
10317 else
10318 {
10324 }
10325 }
10328 }
10330 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
10332 static unsigned HOST_WIDE_INT
10334 {
10336 }
10338 static bool
10343 {
10344 /* STORE_BY_PIECES can be used when copying a constant string, but
10345 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
10346 For now we always fail this and let the move_by_pieces code copy
10347 the string from read-only memory. */
10352 }
10354 static enum machine_mode
10356 {
10358 {
10391 }
10392 }
10394 static rtx
10397 {
10416 {
10432 }
10437 {
10440 }
10454 {
10457 }
10462 }
10464 static rtx
10467 {
10486 {
10504 }
10509 {
10512 }
10529 {
10532 }
10538 }
10540 #undef TARGET_GEN_CCMP_FIRST
10541 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
10543 #undef TARGET_GEN_CCMP_NEXT
10544 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
10546 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
10547 instruction fusion of some sort. */
10549 static bool
10551 {
10553 }
10556 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
10557 should be kept together during scheduling. */
10559 static bool
10561 {
10562 rtx set_dest;
10565 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
10573 {
10574 /* We are trying to match:
10575 prev (mov) == (set (reg r0) (const_int imm16))
10576 curr (movk) == (set (zero_extract (reg r0)
10577 (const_int 16)
10578 (const_int 16))
10579 (const_int imm16_1)) */
10591 {
10593 }
10594 }
10598 {
10600 /* We're trying to match:
10601 prev (adrp) == (set (reg r1)
10602 (high (symbol_ref ("SYM"))))
10603 curr (add) == (set (reg r0)
10604 (lo_sum (reg r1)
10605 (symbol_ref ("SYM"))))
10606 Note that r0 need not necessarily be the same as r1, especially
10607 during pre-regalloc scheduling. */
10611 {
10619 }
10620 }
10624 {
10626 /* We're trying to match:
10627 prev (movk) == (set (zero_extract (reg r0)
10628 (const_int 16)
10629 (const_int 32))
10630 (const_int imm16_1))
10631 curr (movk) == (set (zero_extract (reg r0)
10632 (const_int 16)
10633 (const_int 48))
10634 (const_int imm16_2)) */
10650 }
10653 {
10654 /* We're trying to match:
10655 prev (adrp) == (set (reg r0)
10656 (high (symbol_ref ("SYM"))))
10657 curr (ldr) == (set (reg r1)
10658 (mem (lo_sum (reg r0)
10659 (symbol_ref ("SYM")))))
10660 or
10661 curr (ldr) == (set (reg r1)
10662 (zero_extend (mem
10663 (lo_sum (reg r0)
10664 (symbol_ref ("SYM")))))) */
10667 {
10680 }
10681 }
10685 {
10688 /* FIXME: this misses some which is considered simple arthematic
10689 instructions for ThunderX. Simple shifts are missed here. */
10695 }
10698 }
10700 /* If MEM is in the form of [base+offset], extract the two parts
10701 of address and set to BASE and OFFSET, otherwise return false
10702 after clearing BASE and OFFSET. */
10704 bool
10706 {
10707 rtx addr;
10714 {
10718 }
10722 {
10726 }
10732 }
10734 /* Types for scheduling fusion. */
10735 enum sched_fusion_type
10736 {
10738 SCHED_FUSION_LD_SIGN_EXTEND,
10739 SCHED_FUSION_LD_ZERO_EXTEND,
10740 SCHED_FUSION_LD,
10741 SCHED_FUSION_ST,
10742 SCHED_FUSION_NUM
10743 };
10745 /* If INSN is a load or store of address in the form of [base+offset],
10746 extract the two parts and set to BASE and OFFSET. Return scheduling
10747 fusion type this INSN is. */
10749 static enum sched_fusion_type
10751 {
10768 {
10773 }
10775 {
10780 }
10785 {
10788 }
10789 else
10796 }
10798 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
10800 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
10801 and PRI are only calculated for these instructions. For other instruction,
10802 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
10803 type instruction fusion can be added by returning different priorities.
10805 It's important that irrelevant instructions get the largest FUSION_PRI. */
10807 static void
10810 {
10820 {
10824 }
10826 /* Set FUSION_PRI according to fusion type and base register. */
10829 /* Calculate PRI. */
10832 /* INSN with smaller offset goes first. */
10836 else
10841 }
10843 /* Given OPERANDS of consecutive load/store, check if we can merge
10844 them into ldp/stp. LOAD is true if they are load instructions.
10845 MODE is the mode of memory operands. */
10847 bool
10850 {
10856 {
10864 }
10865 else
10866 {
10871 }
10873 /* The mems cannot be volatile. */
10877 /* Check if the addresses are in the form of [base+offset]. */
10885 /* Check if the bases are same. */
10892 /* Check if the offsets are consecutive. */
10896 /* Check if the addresses are clobbered by load. */
10898 {
10902 /* In increasing order, the last load can clobber the address. */
10905 }
10909 else
10914 else
10917 /* Check if the registers are of same class. */
10922 }
10924 /* Given OPERANDS of consecutive load/store, check if we can merge
10925 them into ldp/stp by adjusting the offset. LOAD is true if they
10926 are load instructions. MODE is the mode of memory operands.
10928 Given below consecutive stores:
10930 str w1, [xb, 0x100]
10931 str w1, [xb, 0x104]
10932 str w1, [xb, 0x108]
10933 str w1, [xb, 0x10c]
10935 Though the offsets are out of the range supported by stp, we can
10936 still pair them after adjusting the offset, like:
10938 add scratch, xb, 0x100
10939 stp w1, w1, [scratch]
10940 stp w1, w1, [scratch, 0x8]
10942 The peephole patterns detecting this opportunity should guarantee
10943 the scratch register is avaliable. */
10945 bool
10948 {
10955 {
10968 }
10969 else
10970 {
10979 }
10980 /* Skip if memory operand is by itslef valid for ldp/stp. */
10984 /* The mems cannot be volatile. */
10989 /* Check if the addresses are in the form of [base+offset]. */
11003 /* Check if the bases are same. */
11014 /* Check if the offsets are consecutive. */
11023 /* Check if the addresses are clobbered by load. */
11025 {
11031 /* In increasing order, the last load can clobber the address. */
11034 }
11038 else
11043 else
11048 else
11053 else
11056 /* Check if the registers are of same class. */
11061 }
11063 /* Given OPERANDS of consecutive load/store, this function pairs them
11064 into ldp/stp after adjusting the offset. It depends on the fact
11065 that addresses of load/store instructions are in increasing order.
11066 MODE is the mode of memory operands. CODE is the rtl operator
11067 which should be applied to all memory operands, it's SIGN_EXTEND,
11068 ZERO_EXTEND or UNKNOWN. */
11070 bool
11073 {
11079 {
11084 }
11085 else
11086 {
11092 }
11097 /* Adjust offset thus it can fit in ldp/stp instruction. */
11105 /* Further adjust to make sure all offsets are OK. */
11107 {
11110 }
11112 /* Make sure the adjustment can be done with ADD/SUB instructions. */
11117 {
11120 }
11122 /* Create new memory references. */
11126 /* Check if the adjusted address is OK for ldp/stp. */
11145 {
11150 }
11152 {
11157 }
11160 {
11165 }
11166 else
11167 {
11172 }
11174 /* Emit adjusting instruction. */
11177 /* Emit ldp/stp instructions. */
11185 }
11187 #undef TARGET_ADDRESS_COST
11188 #define TARGET_ADDRESS_COST aarch64_address_cost
11190 /* This hook will determines whether unnamed bitfields affect the alignment
11191 of the containing structure. The hook returns true if the structure
11192 should inherit the alignment requirements of an unnamed bitfield's
11193 type. */
11194 #undef TARGET_ALIGN_ANON_BITFIELD
11195 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
11197 #undef TARGET_ASM_ALIGNED_DI_OP
11200 #undef TARGET_ASM_ALIGNED_HI_OP
11203 #undef TARGET_ASM_ALIGNED_SI_OP
11206 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
11207 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
11208 hook_bool_const_tree_hwi_hwi_const_tree_true
11210 #undef TARGET_ASM_FILE_START
11211 #define TARGET_ASM_FILE_START aarch64_start_file
11213 #undef TARGET_ASM_OUTPUT_MI_THUNK
11214 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
11216 #undef TARGET_ASM_SELECT_RTX_SECTION
11217 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
11219 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
11220 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
11222 #undef TARGET_BUILD_BUILTIN_VA_LIST
11223 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
11225 #undef TARGET_CALLEE_COPIES
11226 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
11228 #undef TARGET_CAN_ELIMINATE
11229 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
11231 #undef TARGET_CANNOT_FORCE_CONST_MEM
11232 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
11234 #undef TARGET_CONDITIONAL_REGISTER_USAGE
11235 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
11237 /* Only the least significant bit is used for initialization guard
11238 variables. */
11239 #undef TARGET_CXX_GUARD_MASK_BIT
11240 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
11242 #undef TARGET_C_MODE_FOR_SUFFIX
11243 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
11245 #ifdef TARGET_BIG_ENDIAN_DEFAULT
11246 #undef TARGET_DEFAULT_TARGET_FLAGS
11247 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
11248 #endif
11250 #undef TARGET_CLASS_MAX_NREGS
11251 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
11253 #undef TARGET_BUILTIN_DECL
11254 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
11256 #undef TARGET_EXPAND_BUILTIN
11257 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
11259 #undef TARGET_EXPAND_BUILTIN_VA_START
11260 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
11262 #undef TARGET_FOLD_BUILTIN
11263 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
11265 #undef TARGET_FUNCTION_ARG
11266 #define TARGET_FUNCTION_ARG aarch64_function_arg
11268 #undef TARGET_FUNCTION_ARG_ADVANCE
11269 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
11271 #undef TARGET_FUNCTION_ARG_BOUNDARY
11272 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
11274 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
11275 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
11277 #undef TARGET_FUNCTION_VALUE
11278 #define TARGET_FUNCTION_VALUE aarch64_function_value
11280 #undef TARGET_FUNCTION_VALUE_REGNO_P
11281 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
11283 #undef TARGET_FRAME_POINTER_REQUIRED
11284 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
11286 #undef TARGET_GIMPLE_FOLD_BUILTIN
11287 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
11289 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
11290 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
11292 #undef TARGET_INIT_BUILTINS
11293 #define TARGET_INIT_BUILTINS aarch64_init_builtins
11295 #undef TARGET_LEGITIMATE_ADDRESS_P
11296 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
11298 #undef TARGET_LEGITIMATE_CONSTANT_P
11299 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
11301 #undef TARGET_LIBGCC_CMP_RETURN_MODE
11302 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
11304 #undef TARGET_LRA_P
11305 #define TARGET_LRA_P hook_bool_void_true
11307 #undef TARGET_MANGLE_TYPE
11308 #define TARGET_MANGLE_TYPE aarch64_mangle_type
11310 #undef TARGET_MEMORY_MOVE_COST
11311 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
11313 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
11314 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
11316 #undef TARGET_MUST_PASS_IN_STACK
11317 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
11319 /* This target hook should return true if accesses to volatile bitfields
11320 should use the narrowest mode possible. It should return false if these
11321 accesses should use the bitfield container type. */
11322 #undef TARGET_NARROW_VOLATILE_BITFIELD
11323 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
11325 #undef TARGET_OPTION_OVERRIDE
11326 #define TARGET_OPTION_OVERRIDE aarch64_override_options
11328 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
11329 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
11330 aarch64_override_options_after_change
11332 #undef TARGET_PASS_BY_REFERENCE
11333 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
11335 #undef TARGET_PREFERRED_RELOAD_CLASS
11336 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
11338 #undef TARGET_SCHED_REASSOCIATION_WIDTH
11339 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
11341 #undef TARGET_SECONDARY_RELOAD
11342 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
11344 #undef TARGET_SHIFT_TRUNCATION_MASK
11345 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
11347 #undef TARGET_SETUP_INCOMING_VARARGS
11348 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
11350 #undef TARGET_STRUCT_VALUE_RTX
11351 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
11353 #undef TARGET_REGISTER_MOVE_COST
11354 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
11356 #undef TARGET_RETURN_IN_MEMORY
11357 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
11359 #undef TARGET_RETURN_IN_MSB
11360 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
11362 #undef TARGET_RTX_COSTS
11363 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
11365 #undef TARGET_SCHED_ISSUE_RATE
11366 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
11368 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
11369 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
11370 aarch64_sched_first_cycle_multipass_dfa_lookahead
11372 #undef TARGET_TRAMPOLINE_INIT
11373 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
11375 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
11376 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
11378 #undef TARGET_VECTOR_MODE_SUPPORTED_P
11379 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
11381 #undef TARGET_ARRAY_MODE_SUPPORTED_P
11382 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
11384 #undef TARGET_VECTORIZE_ADD_STMT_COST
11385 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
11387 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
11388 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
11389 aarch64_builtin_vectorization_cost
11391 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
11392 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
11394 #undef TARGET_VECTORIZE_BUILTINS
11395 #define TARGET_VECTORIZE_BUILTINS
11397 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
11398 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
11399 aarch64_builtin_vectorized_function
11401 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
11402 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
11403 aarch64_autovectorize_vector_sizes
11405 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
11406 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
11407 aarch64_atomic_assign_expand_fenv
11409 /* Section anchor support. */
11411 #undef TARGET_MIN_ANCHOR_OFFSET
11412 #define TARGET_MIN_ANCHOR_OFFSET -256
11414 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
11415 byte offset; we can do much more for larger data types, but have no way
11416 to determine the size of the access. We assume accesses are aligned. */
11417 #undef TARGET_MAX_ANCHOR_OFFSET
11418 #define TARGET_MAX_ANCHOR_OFFSET 4095
11420 #undef TARGET_VECTOR_ALIGNMENT
11421 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
11423 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
11424 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
11425 aarch64_simd_vector_alignment_reachable
11427 /* vec_perm support. */
11429 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
11430 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
11431 aarch64_vectorize_vec_perm_const_ok
11434 #undef TARGET_FIXED_CONDITION_CODE_REGS
11435 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
11437 #undef TARGET_FLAGS_REGNUM
11438 #define TARGET_FLAGS_REGNUM CC_REGNUM
11440 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
11441 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
11443 #undef TARGET_ASAN_SHADOW_OFFSET
11444 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
11446 #undef TARGET_LEGITIMIZE_ADDRESS
11447 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
11449 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
11450 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
11451 aarch64_use_by_pieces_infrastructure_p
11453 #undef TARGET_CAN_USE_DOLOOP_P
11454 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
11456 #undef TARGET_SCHED_MACRO_FUSION_P
11457 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
11459 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
11460 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
11462 #undef TARGET_SCHED_FUSION_PRIORITY
11463 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority