1 ;; Scheduling description for Renesas SH4a
2 ;; Copyright (C) 2003, 2004 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19 ;; Boston, MA 02110-1301, USA.
21 ;; The following description models the SH4A pipeline
22 ;; using the DFA based scheduler.
24 (define_automaton "sh4a")
26 (define_cpu_unit "sh4a_ex" "sh4a")
27 (define_cpu_unit "sh4a_ls" "sh4a")
28 (define_cpu_unit "sh4a_fex" "sh4a")
29 (define_cpu_unit "sh4a_fls" "sh4a")
30 (define_cpu_unit "sh4a_mult" "sh4a")
31 (define_cpu_unit "sh4a_fdiv" "sh4a")
33 ;; Decoding is done on the integer pipeline like the
34 ;; sh4. Define issue to be the | of the two pipelines
35 ;; to control how often instructions are issued.
36 (define_reservation "ID_or" "sh4a_ex|sh4a_ls")
37 (define_reservation "ID_and" "sh4a_ex+sh4a_ls")
40 ;; =======================================================
41 ;; Locking Descriptions
43 ;; Sh4a_Memory access on the LS pipeline.
44 (define_cpu_unit "sh4a_memory" "sh4a")
46 ;; Other access on the LS pipeline.
47 (define_cpu_unit "sh4a_load_store" "sh4a")
49 ;; The address calculator used for branch instructions.
50 ;; This will be reserved after "issue" of branch instructions
51 ;; and this is to make sure that no two branch instructions
52 ;; can be issued in parallel.
53 (define_reservation "sh4a_addrcalc" "sh4a_ex")
55 ;; =======================================================
58 ;; Branch (BF,BF/S,BT,BT/S,BRA,BSR)
60 ;; Latency when taken: 2
61 (define_insn_reservation "sh4a_branch" 2
62 (and (eq_attr "cpu" "sh4a")
63 (eq_attr "type" "cbranch,jump"))
64 "ID_or+sh4a_addrcalc")
69 (define_insn_reservation "sh4a_jump" 3
70 (and (eq_attr "cpu" "sh4a")
71 (eq_attr "type" "return,jump_ind"))
72 "ID_or+sh4a_addrcalc")
77 (define_insn_reservation "sh4a_rte" 3
78 (and (eq_attr "cpu" "sh4a")
79 (eq_attr "type" "rte"))
85 (define_insn_reservation "sh4a_ex" 0
86 (and (eq_attr "cpu" "sh4a")
87 (eq_attr "insn_class" "ex_group"))
93 (define_insn_reservation "sh4a_mova" 1
94 (and (eq_attr "cpu" "sh4a")
95 (eq_attr "type" "mova"))
96 "sh4a_ls+sh4a_load_store")
101 (define_insn_reservation "sh4a_mov" 0
102 (and (eq_attr "cpu" "sh4a")
103 (eq_attr "type" "move"))
109 (define_insn_reservation "sh4a_load" 3
110 (and (eq_attr "cpu" "sh4a")
111 (eq_attr "type" "load,pcload"))
112 "sh4a_ls+sh4a_memory")
114 (define_insn_reservation "sh4a_load_si" 3
115 (and (eq_attr "cpu" "sh4a")
116 (eq_attr "type" "load_si,pcload_si"))
117 "sh4a_ls+sh4a_memory")
122 (define_insn_reservation "sh4a_store" 0
123 (and (eq_attr "cpu" "sh4a")
124 (eq_attr "type" "store"))
125 "sh4a_ls+sh4a_memory")
132 (define_insn_reservation "sh4a_movua" 3
133 (and (eq_attr "cpu" "sh4a")
134 (eq_attr "type" "movua"))
135 "sh4a_ls+sh4a_memory*2")
137 ;; Fixed point multiplication (single)
140 (define_insn_reservation "sh4a_smult" 2
141 (and (eq_attr "cpu" "sh4a")
142 (eq_attr "type" "smpy"))
145 ;; Fixed point multiplication (double)
148 (define_insn_reservation "sh4a_dmult" 3
149 (and (eq_attr "cpu" "sh4a")
150 (eq_attr "type" "dmpy"))
153 (define_insn_reservation "sh4a_mac_gp" 3
154 (and (eq_attr "cpu" "sh4a")
155 (eq_attr "type" "mac_gp"))
158 ;; Other MT group instructions(1 step operations)
161 (define_insn_reservation "sh4a_mt" 1
162 (and (eq_attr "cpu" "sh4a")
163 (eq_attr "type" "mt_group"))
166 ;; Floating point reg move
169 (define_insn_reservation "sh4a_freg_mov" 2
170 (and (eq_attr "cpu" "sh4a")
171 (eq_attr "type" "fmove"))
174 ;; Single precision floating point computation FCMP/EQ,
175 ;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG
178 (define_insn_reservation "sh4a_fp_arith" 3
179 (and (eq_attr "cpu" "sh4a")
180 (eq_attr "type" "fp"))
183 (define_insn_reservation "sh4a_fp_arith_ftrc" 3
184 (and (eq_attr "cpu" "sh4a")
185 (eq_attr "type" "ftrc_s"))
188 ;; Single-precision FDIV/FSQRT
191 (define_insn_reservation "sh4a_fdiv" 20
192 (and (eq_attr "cpu" "sh4a")
193 (eq_attr "type" "fdiv"))
194 "ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex")
196 ;; Double Precision floating point computation
197 ;; (FCNVDS, FCNVSD, FLOAT, FTRC)
200 (define_insn_reservation "sh4a_dp_float" 3
201 (and (eq_attr "cpu" "sh4a")
202 (eq_attr "type" "dfp_conv"))
205 ;; Double-precision floating-point (FADD,FMUL,FSUB)
208 (define_insn_reservation "sh4a_fp_double_arith" 5
209 (and (eq_attr "cpu" "sh4a")
210 (eq_attr "type" "dfp_arith"))
213 ;; Double precision FDIV/SQRT
216 (define_insn_reservation "sh4a_dp_div" 36
217 (and (eq_attr "cpu" "sh4a")
218 (eq_attr "type" "dfdiv"))
219 "ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex*2")
224 (define_insn_reservation "sh4a_fsrra" 5
225 (and (eq_attr "cpu" "sh4a")
226 (eq_attr "type" "fsrra"))
232 (define_insn_reservation "sh4a_fsca" 7
233 (and (eq_attr "cpu" "sh4a")
234 (eq_attr "type" "fsca"))