1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
61 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save & restore registers.
78 Use a maximum gap of 0x100 in the mips16 case. We can then use
79 unextended instructions to save and restore registers, and to
80 allocate and deallocate the top part of the frame.
82 The value in the !mips16 case must be a SMALL_OPERAND and must
83 preserve the maximum stack alignment. */
84 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
86 /* True if INSN is a mips.md pattern or asm statement. */
87 #define USEFUL_INSN_P(INSN) \
89 && GET_CODE (PATTERN (INSN)) != USE \
90 && GET_CODE (PATTERN (INSN)) != CLOBBER \
91 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
92 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
94 /* If INSN is a delayed branch sequence, return the first instruction
95 in the sequence, otherwise return INSN itself. */
96 #define SEQ_BEGIN(INSN) \
97 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
98 ? XVECEXP (PATTERN (INSN), 0, 0) \
101 /* Likewise for the last instruction in a delayed branch sequence. */
102 #define SEQ_END(INSN) \
103 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
104 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
107 /* Execute the following loop body with SUBINSN set to each instruction
108 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
109 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
110 for ((SUBINSN) = SEQ_BEGIN (INSN); \
111 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
112 (SUBINSN) = NEXT_INSN (SUBINSN))
114 /* Classifies an address.
117 A natural register + offset address. The register satisfies
118 mips_valid_base_register_p and the offset is a const_arith_operand.
121 A LO_SUM rtx. The first operand is a valid base register and
122 the second operand is a symbolic address.
125 A signed 16-bit constant address.
128 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
129 enum mips_address_type
{
136 /* Classifies the prototype of a builtin function. */
137 enum mips_function_type
139 MIPS_V2SF_FTYPE_V2SF
,
140 MIPS_V2SF_FTYPE_V2SF_V2SF
,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_INT
,
142 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF
,
143 MIPS_V2SF_FTYPE_SF_SF
,
144 MIPS_INT_FTYPE_V2SF_V2SF
,
145 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF
,
146 MIPS_INT_FTYPE_SF_SF
,
147 MIPS_INT_FTYPE_DF_DF
,
154 /* For MIPS DSP ASE */
156 MIPS_DI_FTYPE_DI_SI_SI
,
157 MIPS_DI_FTYPE_DI_V2HI_V2HI
,
158 MIPS_DI_FTYPE_DI_V4QI_V4QI
,
160 MIPS_SI_FTYPE_PTR_SI
,
164 MIPS_SI_FTYPE_V2HI_V2HI
,
166 MIPS_SI_FTYPE_V4QI_V4QI
,
169 MIPS_V2HI_FTYPE_SI_SI
,
170 MIPS_V2HI_FTYPE_V2HI
,
171 MIPS_V2HI_FTYPE_V2HI_SI
,
172 MIPS_V2HI_FTYPE_V2HI_V2HI
,
173 MIPS_V2HI_FTYPE_V4QI
,
174 MIPS_V2HI_FTYPE_V4QI_V2HI
,
176 MIPS_V4QI_FTYPE_V2HI_V2HI
,
177 MIPS_V4QI_FTYPE_V4QI_SI
,
178 MIPS_V4QI_FTYPE_V4QI_V4QI
,
179 MIPS_VOID_FTYPE_SI_SI
,
180 MIPS_VOID_FTYPE_V2HI_V2HI
,
181 MIPS_VOID_FTYPE_V4QI_V4QI
,
187 /* Specifies how a builtin function should be converted into rtl. */
188 enum mips_builtin_type
190 /* The builtin corresponds directly to an .md pattern. The return
191 value is mapped to operand 0 and the arguments are mapped to
192 operands 1 and above. */
195 /* The builtin corresponds directly to an .md pattern. There is no return
196 value and the arguments are mapped to operands 0 and above. */
197 MIPS_BUILTIN_DIRECT_NO_TARGET
,
199 /* The builtin corresponds to a comparison instruction followed by
200 a mips_cond_move_tf_ps pattern. The first two arguments are the
201 values to compare and the second two arguments are the vector
202 operands for the movt.ps or movf.ps instruction (in assembly order). */
206 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
207 of this instruction is the result of the comparison, which has mode
208 CCV2 or CCV4. The function arguments are mapped to operands 1 and
209 above. The function's return value is an SImode boolean that is
210 true under the following conditions:
212 MIPS_BUILTIN_CMP_ANY: one of the registers is true
213 MIPS_BUILTIN_CMP_ALL: all of the registers are true
214 MIPS_BUILTIN_CMP_LOWER: the first register is true
215 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
216 MIPS_BUILTIN_CMP_ANY
,
217 MIPS_BUILTIN_CMP_ALL
,
218 MIPS_BUILTIN_CMP_UPPER
,
219 MIPS_BUILTIN_CMP_LOWER
,
221 /* As above, but the instruction only sets a single $fcc register. */
222 MIPS_BUILTIN_CMP_SINGLE
,
224 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
225 MIPS_BUILTIN_BPOSGE32
228 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
229 #define MIPS_FP_CONDITIONS(MACRO) \
247 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
248 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
249 enum mips_fp_condition
{
250 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
253 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
254 #define STRINGIFY(X) #X
255 static const char *const mips_fp_conditions
[] = {
256 MIPS_FP_CONDITIONS (STRINGIFY
)
259 /* A function to save or store a register. The first argument is the
260 register and the second is the stack slot. */
261 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
263 struct mips16_constant
;
264 struct mips_arg_info
;
265 struct mips_address_info
;
266 struct mips_integer_op
;
269 static enum mips_symbol_type
mips_classify_symbol (rtx
);
270 static void mips_split_const (rtx
, rtx
*, HOST_WIDE_INT
*);
271 static bool mips_offset_within_object_p (rtx
, HOST_WIDE_INT
);
272 static bool mips_valid_base_register_p (rtx
, enum machine_mode
, int);
273 static bool mips_symbolic_address_p (enum mips_symbol_type
, enum machine_mode
);
274 static bool mips_classify_address (struct mips_address_info
*, rtx
,
275 enum machine_mode
, int);
276 static bool mips_cannot_force_const_mem (rtx
);
277 static int mips_symbol_insns (enum mips_symbol_type
);
278 static bool mips16_unextended_reference_p (enum machine_mode mode
, rtx
, rtx
);
279 static rtx
mips_force_temporary (rtx
, rtx
);
280 static rtx
mips_split_symbol (rtx
, rtx
);
281 static rtx
mips_unspec_offset_high (rtx
, rtx
, rtx
, enum mips_symbol_type
);
282 static rtx
mips_add_offset (rtx
, rtx
, HOST_WIDE_INT
);
283 static unsigned int mips_build_shift (struct mips_integer_op
*, HOST_WIDE_INT
);
284 static unsigned int mips_build_lower (struct mips_integer_op
*,
285 unsigned HOST_WIDE_INT
);
286 static unsigned int mips_build_integer (struct mips_integer_op
*,
287 unsigned HOST_WIDE_INT
);
288 static void mips_move_integer (rtx
, unsigned HOST_WIDE_INT
);
289 static void mips_legitimize_const_move (enum machine_mode
, rtx
, rtx
);
290 static int m16_check_op (rtx
, int, int, int);
291 static bool mips_rtx_costs (rtx
, int, int, int *);
292 static int mips_address_cost (rtx
);
293 static void mips_emit_compare (enum rtx_code
*, rtx
*, rtx
*, bool);
294 static void mips_load_call_address (rtx
, rtx
, int);
295 static bool mips_function_ok_for_sibcall (tree
, tree
);
296 static void mips_block_move_straight (rtx
, rtx
, HOST_WIDE_INT
);
297 static void mips_adjust_block_mem (rtx
, HOST_WIDE_INT
, rtx
*, rtx
*);
298 static void mips_block_move_loop (rtx
, rtx
, HOST_WIDE_INT
);
299 static void mips_arg_info (const CUMULATIVE_ARGS
*, enum machine_mode
,
300 tree
, int, struct mips_arg_info
*);
301 static bool mips_get_unaligned_mem (rtx
*, unsigned int, int, rtx
*, rtx
*);
302 static void mips_set_architecture (const struct mips_cpu_info
*);
303 static void mips_set_tune (const struct mips_cpu_info
*);
304 static bool mips_handle_option (size_t, const char *, int);
305 static struct machine_function
*mips_init_machine_status (void);
306 static void print_operand_reloc (FILE *, rtx
, const char **);
308 static void irix_output_external_libcall (rtx
);
310 static void mips_file_start (void);
311 static void mips_file_end (void);
312 static bool mips_rewrite_small_data_p (rtx
);
313 static int mips_small_data_pattern_1 (rtx
*, void *);
314 static int mips_rewrite_small_data_1 (rtx
*, void *);
315 static bool mips_function_has_gp_insn (void);
316 static unsigned int mips_global_pointer (void);
317 static bool mips_save_reg_p (unsigned int);
318 static void mips_save_restore_reg (enum machine_mode
, int, HOST_WIDE_INT
,
319 mips_save_restore_fn
);
320 static void mips_for_each_saved_reg (HOST_WIDE_INT
, mips_save_restore_fn
);
321 static void mips_output_cplocal (void);
322 static void mips_emit_loadgp (void);
323 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT
);
324 static void mips_set_frame_expr (rtx
);
325 static rtx
mips_frame_set (rtx
, rtx
);
326 static void mips_save_reg (rtx
, rtx
);
327 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT
);
328 static void mips_restore_reg (rtx
, rtx
);
329 static void mips_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
330 HOST_WIDE_INT
, tree
);
331 static int symbolic_expression_p (rtx
);
332 static section
*mips_select_rtx_section (enum machine_mode
, rtx
,
333 unsigned HOST_WIDE_INT
);
334 static section
*mips_function_rodata_section (tree
);
335 static bool mips_in_small_data_p (tree
);
336 static int mips_fpr_return_fields (tree
, tree
*);
337 static bool mips_return_in_msb (tree
);
338 static rtx
mips_return_fpr_pair (enum machine_mode mode
,
339 enum machine_mode mode1
, HOST_WIDE_INT
,
340 enum machine_mode mode2
, HOST_WIDE_INT
);
341 static rtx
mips16_gp_pseudo_reg (void);
342 static void mips16_fp_args (FILE *, int, int);
343 static void build_mips16_function_stub (FILE *);
344 static rtx
dump_constants_1 (enum machine_mode
, rtx
, rtx
);
345 static void dump_constants (struct mips16_constant
*, rtx
);
346 static int mips16_insn_length (rtx
);
347 static int mips16_rewrite_pool_refs (rtx
*, void *);
348 static void mips16_lay_out_constants (void);
349 static void mips_sim_reset (struct mips_sim
*);
350 static void mips_sim_init (struct mips_sim
*, state_t
);
351 static void mips_sim_next_cycle (struct mips_sim
*);
352 static void mips_sim_wait_reg (struct mips_sim
*, rtx
, rtx
);
353 static int mips_sim_wait_regs_2 (rtx
*, void *);
354 static void mips_sim_wait_regs_1 (rtx
*, void *);
355 static void mips_sim_wait_regs (struct mips_sim
*, rtx
);
356 static void mips_sim_wait_units (struct mips_sim
*, rtx
);
357 static void mips_sim_wait_insn (struct mips_sim
*, rtx
);
358 static void mips_sim_record_set (rtx
, rtx
, void *);
359 static void mips_sim_issue_insn (struct mips_sim
*, rtx
);
360 static void mips_sim_issue_nop (struct mips_sim
*);
361 static void mips_sim_finish_insn (struct mips_sim
*, rtx
);
362 static void vr4130_avoid_branch_rt_conflict (rtx
);
363 static void vr4130_align_insns (void);
364 static void mips_avoid_hazard (rtx
, rtx
, int *, rtx
*, rtx
);
365 static void mips_avoid_hazards (void);
366 static void mips_reorg (void);
367 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
368 static bool mips_matching_cpu_name_p (const char *, const char *);
369 static const struct mips_cpu_info
*mips_parse_cpu (const char *);
370 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
371 static bool mips_return_in_memory (tree
, tree
);
372 static bool mips_strict_argument_naming (CUMULATIVE_ARGS
*);
373 static void mips_macc_chains_record (rtx
);
374 static void mips_macc_chains_reorder (rtx
*, int);
375 static void vr4130_true_reg_dependence_p_1 (rtx
, rtx
, void *);
376 static bool vr4130_true_reg_dependence_p (rtx
);
377 static bool vr4130_swap_insns_p (rtx
, rtx
);
378 static void vr4130_reorder (rtx
*, int);
379 static void mips_promote_ready (rtx
*, int, int);
380 static int mips_sched_reorder (FILE *, int, rtx
*, int *, int);
381 static int mips_variable_issue (FILE *, int, rtx
, int);
382 static int mips_adjust_cost (rtx
, rtx
, rtx
, int);
383 static int mips_issue_rate (void);
384 static int mips_multipass_dfa_lookahead (void);
385 static void mips_init_libfuncs (void);
386 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
388 static tree
mips_build_builtin_va_list (void);
389 static tree
mips_gimplify_va_arg_expr (tree
, tree
, tree
*, tree
*);
390 static bool mips_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode mode
,
392 static bool mips_callee_copies (CUMULATIVE_ARGS
*, enum machine_mode mode
,
394 static int mips_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode mode
,
396 static bool mips_valid_pointer_mode (enum machine_mode
);
397 static bool mips_vector_mode_supported_p (enum machine_mode
);
398 static rtx
mips_prepare_builtin_arg (enum insn_code
, unsigned int, tree
*);
399 static rtx
mips_prepare_builtin_target (enum insn_code
, unsigned int, rtx
);
400 static rtx
mips_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
401 static void mips_init_builtins (void);
402 static rtx
mips_expand_builtin_direct (enum insn_code
, rtx
, tree
, bool);
403 static rtx
mips_expand_builtin_movtf (enum mips_builtin_type
,
404 enum insn_code
, enum mips_fp_condition
,
406 static rtx
mips_expand_builtin_compare (enum mips_builtin_type
,
407 enum insn_code
, enum mips_fp_condition
,
409 static rtx
mips_expand_builtin_bposge (enum mips_builtin_type
, rtx
);
410 static void mips_encode_section_info (tree
, rtx
, int);
411 static void mips_extra_live_on_entry (bitmap
);
413 /* Structure to be filled in by compute_frame_size with register
414 save masks, and offsets for the current function. */
416 struct mips_frame_info
GTY(())
418 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
419 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
420 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
421 HOST_WIDE_INT cprestore_size
; /* # bytes that the .cprestore slot takes up */
422 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
423 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
424 unsigned int mask
; /* mask of saved gp registers */
425 unsigned int fmask
; /* mask of saved fp registers */
426 HOST_WIDE_INT gp_save_offset
; /* offset from vfp to store gp registers */
427 HOST_WIDE_INT fp_save_offset
; /* offset from vfp to store fp registers */
428 HOST_WIDE_INT gp_sp_offset
; /* offset from new sp to store gp registers */
429 HOST_WIDE_INT fp_sp_offset
; /* offset from new sp to store fp registers */
430 bool initialized
; /* true if frame size already calculated */
431 int num_gp
; /* number of gp registers saved */
432 int num_fp
; /* number of fp registers saved */
435 struct machine_function
GTY(()) {
436 /* Pseudo-reg holding the value of $28 in a mips16 function which
437 refers to GP relative global variables. */
438 rtx mips16_gp_pseudo_rtx
;
440 /* The number of extra stack bytes taken up by register varargs.
441 This area is allocated by the callee at the very top of the frame. */
444 /* Current frame information, calculated by compute_frame_size. */
445 struct mips_frame_info frame
;
447 /* The register to use as the global pointer within this function. */
448 unsigned int global_pointer
;
450 /* True if mips_adjust_insn_length should ignore an instruction's
452 bool ignore_hazard_length_p
;
454 /* True if the whole function is suitable for .set noreorder and
456 bool all_noreorder_p
;
458 /* True if the function is known to have an instruction that needs $gp. */
462 /* Information about a single argument. */
465 /* True if the argument is passed in a floating-point register, or
466 would have been if we hadn't run out of registers. */
469 /* The number of words passed in registers, rounded up. */
470 unsigned int reg_words
;
472 /* For EABI, the offset of the first register from GP_ARG_FIRST or
473 FP_ARG_FIRST. For other ABIs, the offset of the first register from
474 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
475 comment for details).
477 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
479 unsigned int reg_offset
;
481 /* The number of words that must be passed on the stack, rounded up. */
482 unsigned int stack_words
;
484 /* The offset from the start of the stack overflow area of the argument's
485 first stack word. Only meaningful when STACK_WORDS is nonzero. */
486 unsigned int stack_offset
;
490 /* Information about an address described by mips_address_type.
496 REG is the base register and OFFSET is the constant offset.
499 REG is the register that contains the high part of the address,
500 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
501 is the type of OFFSET's symbol.
504 SYMBOL_TYPE is the type of symbol being referenced. */
506 struct mips_address_info
508 enum mips_address_type type
;
511 enum mips_symbol_type symbol_type
;
515 /* One stage in a constant building sequence. These sequences have
519 A = A CODE[1] VALUE[1]
520 A = A CODE[2] VALUE[2]
523 where A is an accumulator, each CODE[i] is a binary rtl operation
524 and each VALUE[i] is a constant integer. */
525 struct mips_integer_op
{
527 unsigned HOST_WIDE_INT value
;
531 /* The largest number of operations needed to load an integer constant.
532 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
533 When the lowest bit is clear, we can try, but reject a sequence with
534 an extra SLL at the end. */
535 #define MIPS_MAX_INTEGER_OPS 7
538 /* Global variables for machine-dependent things. */
540 /* Threshold for data being put into the small data/bss area, instead
541 of the normal data area. */
542 int mips_section_threshold
= -1;
544 /* Count the number of .file directives, so that .loc is up to date. */
545 int num_source_filenames
= 0;
547 /* Count the number of sdb related labels are generated (to find block
548 start and end boundaries). */
549 int sdb_label_count
= 0;
551 /* Next label # for each statement for Silicon Graphics IRIS systems. */
554 /* Linked list of all externals that are to be emitted when optimizing
555 for the global pointer if they haven't been declared by the end of
556 the program with an appropriate .comm or initialization. */
558 struct extern_list
GTY (())
560 struct extern_list
*next
; /* next external */
561 const char *name
; /* name of the external */
562 int size
; /* size in bytes */
565 static GTY (()) struct extern_list
*extern_head
= 0;
567 /* Name of the file containing the current function. */
568 const char *current_function_file
= "";
570 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
576 /* The next branch instruction is a branch likely, not branch normal. */
577 int mips_branch_likely
;
579 /* The operands passed to the last cmpMM expander. */
582 /* The target cpu for code generation. */
583 enum processor_type mips_arch
;
584 const struct mips_cpu_info
*mips_arch_info
;
586 /* The target cpu for optimization and scheduling. */
587 enum processor_type mips_tune
;
588 const struct mips_cpu_info
*mips_tune_info
;
590 /* Which instruction set architecture to use. */
593 /* Which ABI to use. */
594 int mips_abi
= MIPS_ABI_DEFAULT
;
596 /* Cost information to use. */
597 const struct mips_rtx_cost_data
*mips_cost
;
599 /* Whether we are generating mips16 hard float code. In mips16 mode
600 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
601 -msoft-float was not specified by the user, which means that we
602 should arrange to call mips32 hard floating point code. */
603 int mips16_hard_float
;
605 /* The architecture selected by -mipsN. */
606 static const struct mips_cpu_info
*mips_isa_info
;
608 /* If TRUE, we split addresses into their high and low parts in the RTL. */
609 int mips_split_addresses
;
611 /* Mode used for saving/restoring general purpose registers. */
612 static enum machine_mode gpr_mode
;
614 /* Array giving truth value on whether or not a given hard register
615 can support a given mode. */
616 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
618 /* List of all MIPS punctuation characters used by print_operand. */
619 char mips_print_operand_punct
[256];
621 /* Map GCC register number to debugger register number. */
622 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
624 /* A copy of the original flag_delayed_branch: see override_options. */
625 static int mips_flag_delayed_branch
;
627 static GTY (()) int mips_output_filename_first_time
= 1;
629 /* mips_split_p[X] is true if symbols of type X can be split by
630 mips_split_symbol(). */
631 static bool mips_split_p
[NUM_SYMBOL_TYPES
];
633 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
634 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
635 if they are matched by a special .md file pattern. */
636 static const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
638 /* Likewise for HIGHs. */
639 static const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
641 /* Map hard register number to register class */
642 const enum reg_class mips_regno_to_class
[] =
644 LEA_REGS
, LEA_REGS
, M16_NA_REGS
, V1_REG
,
645 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
646 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
647 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
648 M16_NA_REGS
, M16_NA_REGS
, LEA_REGS
, LEA_REGS
,
649 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
650 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
651 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
652 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
653 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
654 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
655 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
656 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
657 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
658 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
659 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
660 HI_REG
, LO_REG
, NO_REGS
, ST_REGS
,
661 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
662 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
663 NO_REGS
, ALL_REGS
, ALL_REGS
, NO_REGS
,
664 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
665 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
666 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
667 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
668 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
669 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
670 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
671 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
672 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
673 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
674 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
675 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
676 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
677 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
678 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
679 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
680 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
681 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
682 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
683 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
684 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
685 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
686 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
687 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
688 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
689 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
690 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
693 /* Map register constraint character to register class. */
694 enum reg_class mips_char_to_class
[256];
696 /* Table of machine dependent attributes. */
697 const struct attribute_spec mips_attribute_table
[] =
699 { "long_call", 0, 0, false, true, true, NULL
},
700 { NULL
, 0, 0, false, false, false, NULL
}
703 /* A table describing all the processors gcc knows about. Names are
704 matched in the order listed. The first mention of an ISA level is
705 taken as the canonical name for that ISA.
707 To ease comparison, please keep this table in the same order as
708 gas's mips_cpu_info_table[]. */
709 const struct mips_cpu_info mips_cpu_info_table
[] = {
710 /* Entries for generic ISAs */
711 { "mips1", PROCESSOR_R3000
, 1 },
712 { "mips2", PROCESSOR_R6000
, 2 },
713 { "mips3", PROCESSOR_R4000
, 3 },
714 { "mips4", PROCESSOR_R8000
, 4 },
715 { "mips32", PROCESSOR_4KC
, 32 },
716 { "mips32r2", PROCESSOR_M4K
, 33 },
717 { "mips64", PROCESSOR_5KC
, 64 },
720 { "r3000", PROCESSOR_R3000
, 1 },
721 { "r2000", PROCESSOR_R3000
, 1 }, /* = r3000 */
722 { "r3900", PROCESSOR_R3900
, 1 },
725 { "r6000", PROCESSOR_R6000
, 2 },
728 { "r4000", PROCESSOR_R4000
, 3 },
729 { "vr4100", PROCESSOR_R4100
, 3 },
730 { "vr4111", PROCESSOR_R4111
, 3 },
731 { "vr4120", PROCESSOR_R4120
, 3 },
732 { "vr4130", PROCESSOR_R4130
, 3 },
733 { "vr4300", PROCESSOR_R4300
, 3 },
734 { "r4400", PROCESSOR_R4000
, 3 }, /* = r4000 */
735 { "r4600", PROCESSOR_R4600
, 3 },
736 { "orion", PROCESSOR_R4600
, 3 }, /* = r4600 */
737 { "r4650", PROCESSOR_R4650
, 3 },
740 { "r8000", PROCESSOR_R8000
, 4 },
741 { "vr5000", PROCESSOR_R5000
, 4 },
742 { "vr5400", PROCESSOR_R5400
, 4 },
743 { "vr5500", PROCESSOR_R5500
, 4 },
744 { "rm7000", PROCESSOR_R7000
, 4 },
745 { "rm9000", PROCESSOR_R9000
, 4 },
748 { "4kc", PROCESSOR_4KC
, 32 },
749 { "4km", PROCESSOR_4KC
, 32 }, /* = 4kc */
750 { "4kp", PROCESSOR_4KP
, 32 },
752 /* MIPS32 Release 2 */
753 { "m4k", PROCESSOR_M4K
, 33 },
754 { "24k", PROCESSOR_24K
, 33 },
755 { "24kc", PROCESSOR_24K
, 33 }, /* 24K no FPU */
756 { "24kf", PROCESSOR_24K
, 33 }, /* 24K 1:2 FPU */
757 { "24kx", PROCESSOR_24KX
, 33 }, /* 24K 1:1 FPU */
760 { "5kc", PROCESSOR_5KC
, 64 },
761 { "5kf", PROCESSOR_5KF
, 64 },
762 { "20kc", PROCESSOR_20KC
, 64 },
763 { "sb1", PROCESSOR_SB1
, 64 },
764 { "sr71000", PROCESSOR_SR71000
, 64 },
770 /* Default costs. If these are used for a processor we should look
771 up the actual costs. */
772 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
773 COSTS_N_INSNS (7), /* fp_mult_sf */ \
774 COSTS_N_INSNS (8), /* fp_mult_df */ \
775 COSTS_N_INSNS (23), /* fp_div_sf */ \
776 COSTS_N_INSNS (36), /* fp_div_df */ \
777 COSTS_N_INSNS (10), /* int_mult_si */ \
778 COSTS_N_INSNS (10), /* int_mult_di */ \
779 COSTS_N_INSNS (69), /* int_div_si */ \
780 COSTS_N_INSNS (69), /* int_div_di */ \
781 2, /* branch_cost */ \
782 4 /* memory_latency */
784 /* Need to replace these with the costs of calling the appropriate
786 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
787 COSTS_N_INSNS (256), /* fp_mult_sf */ \
788 COSTS_N_INSNS (256), /* fp_mult_df */ \
789 COSTS_N_INSNS (256), /* fp_div_sf */ \
790 COSTS_N_INSNS (256) /* fp_div_df */
792 static struct mips_rtx_cost_data
const mips_rtx_cost_data
[PROCESSOR_MAX
] =
795 COSTS_N_INSNS (2), /* fp_add */
796 COSTS_N_INSNS (4), /* fp_mult_sf */
797 COSTS_N_INSNS (5), /* fp_mult_df */
798 COSTS_N_INSNS (12), /* fp_div_sf */
799 COSTS_N_INSNS (19), /* fp_div_df */
800 COSTS_N_INSNS (12), /* int_mult_si */
801 COSTS_N_INSNS (12), /* int_mult_di */
802 COSTS_N_INSNS (35), /* int_div_si */
803 COSTS_N_INSNS (35), /* int_div_di */
805 4 /* memory_latency */
810 COSTS_N_INSNS (6), /* int_mult_si */
811 COSTS_N_INSNS (6), /* int_mult_di */
812 COSTS_N_INSNS (36), /* int_div_si */
813 COSTS_N_INSNS (36), /* int_div_di */
815 4 /* memory_latency */
819 COSTS_N_INSNS (36), /* int_mult_si */
820 COSTS_N_INSNS (36), /* int_mult_di */
821 COSTS_N_INSNS (37), /* int_div_si */
822 COSTS_N_INSNS (37), /* int_div_di */
824 4 /* memory_latency */
828 COSTS_N_INSNS (4), /* int_mult_si */
829 COSTS_N_INSNS (11), /* int_mult_di */
830 COSTS_N_INSNS (36), /* int_div_si */
831 COSTS_N_INSNS (68), /* int_div_di */
833 4 /* memory_latency */
836 COSTS_N_INSNS (4), /* fp_add */
837 COSTS_N_INSNS (4), /* fp_mult_sf */
838 COSTS_N_INSNS (5), /* fp_mult_df */
839 COSTS_N_INSNS (17), /* fp_div_sf */
840 COSTS_N_INSNS (32), /* fp_div_df */
841 COSTS_N_INSNS (4), /* int_mult_si */
842 COSTS_N_INSNS (11), /* int_mult_di */
843 COSTS_N_INSNS (36), /* int_div_si */
844 COSTS_N_INSNS (68), /* int_div_di */
846 4 /* memory_latency */
852 COSTS_N_INSNS (8), /* fp_add */
853 COSTS_N_INSNS (8), /* fp_mult_sf */
854 COSTS_N_INSNS (10), /* fp_mult_df */
855 COSTS_N_INSNS (34), /* fp_div_sf */
856 COSTS_N_INSNS (64), /* fp_div_df */
857 COSTS_N_INSNS (5), /* int_mult_si */
858 COSTS_N_INSNS (5), /* int_mult_di */
859 COSTS_N_INSNS (41), /* int_div_si */
860 COSTS_N_INSNS (41), /* int_div_di */
862 4 /* memory_latency */
865 COSTS_N_INSNS (4), /* fp_add */
866 COSTS_N_INSNS (4), /* fp_mult_sf */
867 COSTS_N_INSNS (5), /* fp_mult_df */
868 COSTS_N_INSNS (17), /* fp_div_sf */
869 COSTS_N_INSNS (32), /* fp_div_df */
870 COSTS_N_INSNS (5), /* int_mult_si */
871 COSTS_N_INSNS (5), /* int_mult_di */
872 COSTS_N_INSNS (41), /* int_div_si */
873 COSTS_N_INSNS (41), /* int_div_di */
875 4 /* memory_latency */
881 COSTS_N_INSNS (2), /* fp_add */
882 COSTS_N_INSNS (4), /* fp_mult_sf */
883 COSTS_N_INSNS (5), /* fp_mult_df */
884 COSTS_N_INSNS (12), /* fp_div_sf */
885 COSTS_N_INSNS (19), /* fp_div_df */
886 COSTS_N_INSNS (2), /* int_mult_si */
887 COSTS_N_INSNS (2), /* int_mult_di */
888 COSTS_N_INSNS (35), /* int_div_si */
889 COSTS_N_INSNS (35), /* int_div_di */
891 4 /* memory_latency */
894 COSTS_N_INSNS (3), /* fp_add */
895 COSTS_N_INSNS (5), /* fp_mult_sf */
896 COSTS_N_INSNS (6), /* fp_mult_df */
897 COSTS_N_INSNS (15), /* fp_div_sf */
898 COSTS_N_INSNS (16), /* fp_div_df */
899 COSTS_N_INSNS (17), /* int_mult_si */
900 COSTS_N_INSNS (17), /* int_mult_di */
901 COSTS_N_INSNS (38), /* int_div_si */
902 COSTS_N_INSNS (38), /* int_div_di */
904 6 /* memory_latency */
907 COSTS_N_INSNS (6), /* fp_add */
908 COSTS_N_INSNS (7), /* fp_mult_sf */
909 COSTS_N_INSNS (8), /* fp_mult_df */
910 COSTS_N_INSNS (23), /* fp_div_sf */
911 COSTS_N_INSNS (36), /* fp_div_df */
912 COSTS_N_INSNS (10), /* int_mult_si */
913 COSTS_N_INSNS (10), /* int_mult_di */
914 COSTS_N_INSNS (69), /* int_div_si */
915 COSTS_N_INSNS (69), /* int_div_di */
917 6 /* memory_latency */
929 /* The only costs that appear to be updated here are
930 integer multiplication. */
932 COSTS_N_INSNS (4), /* int_mult_si */
933 COSTS_N_INSNS (6), /* int_mult_di */
934 COSTS_N_INSNS (69), /* int_div_si */
935 COSTS_N_INSNS (69), /* int_div_di */
937 4 /* memory_latency */
949 COSTS_N_INSNS (6), /* fp_add */
950 COSTS_N_INSNS (4), /* fp_mult_sf */
951 COSTS_N_INSNS (5), /* fp_mult_df */
952 COSTS_N_INSNS (23), /* fp_div_sf */
953 COSTS_N_INSNS (36), /* fp_div_df */
954 COSTS_N_INSNS (5), /* int_mult_si */
955 COSTS_N_INSNS (5), /* int_mult_di */
956 COSTS_N_INSNS (36), /* int_div_si */
957 COSTS_N_INSNS (36), /* int_div_di */
959 4 /* memory_latency */
962 COSTS_N_INSNS (6), /* fp_add */
963 COSTS_N_INSNS (5), /* fp_mult_sf */
964 COSTS_N_INSNS (6), /* fp_mult_df */
965 COSTS_N_INSNS (30), /* fp_div_sf */
966 COSTS_N_INSNS (59), /* fp_div_df */
967 COSTS_N_INSNS (3), /* int_mult_si */
968 COSTS_N_INSNS (4), /* int_mult_di */
969 COSTS_N_INSNS (42), /* int_div_si */
970 COSTS_N_INSNS (74), /* int_div_di */
972 4 /* memory_latency */
975 COSTS_N_INSNS (6), /* fp_add */
976 COSTS_N_INSNS (5), /* fp_mult_sf */
977 COSTS_N_INSNS (6), /* fp_mult_df */
978 COSTS_N_INSNS (30), /* fp_div_sf */
979 COSTS_N_INSNS (59), /* fp_div_df */
980 COSTS_N_INSNS (5), /* int_mult_si */
981 COSTS_N_INSNS (9), /* int_mult_di */
982 COSTS_N_INSNS (42), /* int_div_si */
983 COSTS_N_INSNS (74), /* int_div_di */
985 4 /* memory_latency */
988 /* The only costs that are changed here are
989 integer multiplication. */
990 COSTS_N_INSNS (6), /* fp_add */
991 COSTS_N_INSNS (7), /* fp_mult_sf */
992 COSTS_N_INSNS (8), /* fp_mult_df */
993 COSTS_N_INSNS (23), /* fp_div_sf */
994 COSTS_N_INSNS (36), /* fp_div_df */
995 COSTS_N_INSNS (5), /* int_mult_si */
996 COSTS_N_INSNS (9), /* int_mult_di */
997 COSTS_N_INSNS (69), /* int_div_si */
998 COSTS_N_INSNS (69), /* int_div_di */
1000 4 /* memory_latency */
1006 /* The only costs that are changed here are
1007 integer multiplication. */
1008 COSTS_N_INSNS (6), /* fp_add */
1009 COSTS_N_INSNS (7), /* fp_mult_sf */
1010 COSTS_N_INSNS (8), /* fp_mult_df */
1011 COSTS_N_INSNS (23), /* fp_div_sf */
1012 COSTS_N_INSNS (36), /* fp_div_df */
1013 COSTS_N_INSNS (3), /* int_mult_si */
1014 COSTS_N_INSNS (8), /* int_mult_di */
1015 COSTS_N_INSNS (69), /* int_div_si */
1016 COSTS_N_INSNS (69), /* int_div_di */
1017 1, /* branch_cost */
1018 4 /* memory_latency */
1021 COSTS_N_INSNS (4), /* fp_add */
1022 COSTS_N_INSNS (4), /* fp_mult_sf */
1023 COSTS_N_INSNS (4), /* fp_mult_df */
1024 COSTS_N_INSNS (24), /* fp_div_sf */
1025 COSTS_N_INSNS (32), /* fp_div_df */
1026 COSTS_N_INSNS (3), /* int_mult_si */
1027 COSTS_N_INSNS (4), /* int_mult_di */
1028 COSTS_N_INSNS (36), /* int_div_si */
1029 COSTS_N_INSNS (68), /* int_div_di */
1030 1, /* branch_cost */
1031 4 /* memory_latency */
1039 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1040 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1041 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1044 /* Initialize the GCC target structure. */
1045 #undef TARGET_ASM_ALIGNED_HI_OP
1046 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1047 #undef TARGET_ASM_ALIGNED_SI_OP
1048 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1049 #undef TARGET_ASM_ALIGNED_DI_OP
1050 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1052 #undef TARGET_ASM_FUNCTION_PROLOGUE
1053 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1054 #undef TARGET_ASM_FUNCTION_EPILOGUE
1055 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1056 #undef TARGET_ASM_SELECT_RTX_SECTION
1057 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1058 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1059 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1061 #undef TARGET_SCHED_REORDER
1062 #define TARGET_SCHED_REORDER mips_sched_reorder
1063 #undef TARGET_SCHED_VARIABLE_ISSUE
1064 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1065 #undef TARGET_SCHED_ADJUST_COST
1066 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1067 #undef TARGET_SCHED_ISSUE_RATE
1068 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1069 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1070 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1071 mips_multipass_dfa_lookahead
1073 #undef TARGET_DEFAULT_TARGET_FLAGS
1074 #define TARGET_DEFAULT_TARGET_FLAGS \
1076 | TARGET_CPU_DEFAULT \
1077 | TARGET_ENDIAN_DEFAULT \
1078 | TARGET_FP_EXCEPTIONS_DEFAULT \
1079 | MASK_CHECK_ZERO_DIV \
1081 #undef TARGET_HANDLE_OPTION
1082 #define TARGET_HANDLE_OPTION mips_handle_option
1084 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1085 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1087 #undef TARGET_VALID_POINTER_MODE
1088 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1089 #undef TARGET_RTX_COSTS
1090 #define TARGET_RTX_COSTS mips_rtx_costs
1091 #undef TARGET_ADDRESS_COST
1092 #define TARGET_ADDRESS_COST mips_address_cost
1094 #undef TARGET_IN_SMALL_DATA_P
1095 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1097 #undef TARGET_MACHINE_DEPENDENT_REORG
1098 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1100 #undef TARGET_ASM_FILE_START
1101 #undef TARGET_ASM_FILE_END
1102 #define TARGET_ASM_FILE_START mips_file_start
1103 #define TARGET_ASM_FILE_END mips_file_end
1104 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1105 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1107 #undef TARGET_INIT_LIBFUNCS
1108 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1110 #undef TARGET_BUILD_BUILTIN_VA_LIST
1111 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1112 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1113 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1115 #undef TARGET_PROMOTE_FUNCTION_ARGS
1116 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1117 #undef TARGET_PROMOTE_FUNCTION_RETURN
1118 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1119 #undef TARGET_PROMOTE_PROTOTYPES
1120 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1122 #undef TARGET_RETURN_IN_MEMORY
1123 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1124 #undef TARGET_RETURN_IN_MSB
1125 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1127 #undef TARGET_ASM_OUTPUT_MI_THUNK
1128 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1129 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1130 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1132 #undef TARGET_SETUP_INCOMING_VARARGS
1133 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1134 #undef TARGET_STRICT_ARGUMENT_NAMING
1135 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1136 #undef TARGET_MUST_PASS_IN_STACK
1137 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1138 #undef TARGET_PASS_BY_REFERENCE
1139 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1140 #undef TARGET_CALLEE_COPIES
1141 #define TARGET_CALLEE_COPIES mips_callee_copies
1142 #undef TARGET_ARG_PARTIAL_BYTES
1143 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1145 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1146 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1148 #undef TARGET_INIT_BUILTINS
1149 #define TARGET_INIT_BUILTINS mips_init_builtins
1150 #undef TARGET_EXPAND_BUILTIN
1151 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1153 #undef TARGET_HAVE_TLS
1154 #define TARGET_HAVE_TLS HAVE_AS_TLS
1156 #undef TARGET_CANNOT_FORCE_CONST_MEM
1157 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1159 #undef TARGET_ENCODE_SECTION_INFO
1160 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1162 #undef TARGET_ATTRIBUTE_TABLE
1163 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1165 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1166 /* With -mabicalls (which is the default on GNU/Linux),
1167 PIC_FUNCTION_ADDR_REGNUM is live on function entry and is to
1168 initialize $28, which is PIC_OFFSET_TABLE_REGNUM. */
1169 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1171 struct gcc_target targetm
= TARGET_INITIALIZER
;
1173 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1175 static enum mips_symbol_type
1176 mips_classify_symbol (rtx x
)
1178 if (GET_CODE (x
) == LABEL_REF
)
1181 return SYMBOL_CONSTANT_POOL
;
1182 if (TARGET_ABICALLS
)
1183 return SYMBOL_GOT_LOCAL
;
1184 return SYMBOL_GENERAL
;
1187 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1189 if (SYMBOL_REF_TLS_MODEL (x
))
1192 if (CONSTANT_POOL_ADDRESS_P (x
))
1195 return SYMBOL_CONSTANT_POOL
;
1197 if (TARGET_ABICALLS
)
1198 return SYMBOL_GOT_LOCAL
;
1200 if (GET_MODE_SIZE (get_pool_mode (x
)) <= mips_section_threshold
)
1201 return SYMBOL_SMALL_DATA
;
1203 return SYMBOL_GENERAL
;
1206 if (SYMBOL_REF_SMALL_P (x
))
1207 return SYMBOL_SMALL_DATA
;
1209 if (TARGET_ABICALLS
)
1211 if (SYMBOL_REF_DECL (x
) == 0)
1212 return SYMBOL_REF_LOCAL_P (x
) ? SYMBOL_GOT_LOCAL
: SYMBOL_GOT_GLOBAL
;
1214 /* There are three cases to consider:
1216 - o32 PIC (either with or without explicit relocs)
1217 - n32/n64 PIC without explicit relocs
1218 - n32/n64 PIC with explicit relocs
1220 In the first case, both local and global accesses will use an
1221 R_MIPS_GOT16 relocation. We must correctly predict which of
1222 the two semantics (local or global) the assembler and linker
1223 will apply. The choice doesn't depend on the symbol's
1224 visibility, so we deliberately ignore decl_visibility and
1227 In the second case, the assembler will not use R_MIPS_GOT16
1228 relocations, but it chooses between local and global accesses
1229 in the same way as for o32 PIC.
1231 In the third case we have more freedom since both forms of
1232 access will work for any kind of symbol. However, there seems
1233 little point in doing things differently. */
1234 if (DECL_P (SYMBOL_REF_DECL (x
)) && TREE_PUBLIC (SYMBOL_REF_DECL (x
)))
1235 return SYMBOL_GOT_GLOBAL
;
1237 return SYMBOL_GOT_LOCAL
;
1240 return SYMBOL_GENERAL
;
1244 /* Split X into a base and a constant offset, storing them in *BASE
1245 and *OFFSET respectively. */
1248 mips_split_const (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
1252 if (GET_CODE (x
) == CONST
)
1255 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1257 *offset
+= INTVAL (XEXP (x
, 1));
1264 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1265 to the same object as SYMBOL. */
1268 mips_offset_within_object_p (rtx symbol
, HOST_WIDE_INT offset
)
1270 if (GET_CODE (symbol
) != SYMBOL_REF
)
1273 if (CONSTANT_POOL_ADDRESS_P (symbol
)
1275 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
1278 if (SYMBOL_REF_DECL (symbol
) != 0
1280 && offset
< int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol
))))
1287 /* Return true if X is a symbolic constant that can be calculated in
1288 the same way as a bare symbol. If it is, store the type of the
1289 symbol in *SYMBOL_TYPE. */
1292 mips_symbolic_constant_p (rtx x
, enum mips_symbol_type
*symbol_type
)
1294 HOST_WIDE_INT offset
;
1296 mips_split_const (x
, &x
, &offset
);
1297 if (UNSPEC_ADDRESS_P (x
))
1298 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1299 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1301 *symbol_type
= mips_classify_symbol (x
);
1302 if (*symbol_type
== SYMBOL_TLS
)
1311 /* Check whether a nonzero offset is valid for the underlying
1313 switch (*symbol_type
)
1315 case SYMBOL_GENERAL
:
1316 case SYMBOL_64_HIGH
:
1319 /* If the target has 64-bit pointers and the object file only
1320 supports 32-bit symbols, the values of those symbols will be
1321 sign-extended. In this case we can't allow an arbitrary offset
1322 in case the 32-bit value X + OFFSET has a different sign from X. */
1323 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1324 return mips_offset_within_object_p (x
, offset
);
1326 /* In other cases the relocations can handle any offset. */
1329 case SYMBOL_CONSTANT_POOL
:
1330 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1331 In this case, we no longer have access to the underlying constant,
1332 but the original symbol-based access was known to be valid. */
1333 if (GET_CODE (x
) == LABEL_REF
)
1338 case SYMBOL_SMALL_DATA
:
1339 /* Make sure that the offset refers to something within the
1340 underlying object. This should guarantee that the final
1341 PC- or GP-relative offset is within the 16-bit limit. */
1342 return mips_offset_within_object_p (x
, offset
);
1344 case SYMBOL_GOT_LOCAL
:
1345 case SYMBOL_GOTOFF_PAGE
:
1346 /* The linker should provide enough local GOT entries for a
1347 16-bit offset. Larger offsets may lead to GOT overflow. */
1348 return SMALL_OPERAND (offset
);
1350 case SYMBOL_GOT_GLOBAL
:
1351 case SYMBOL_GOTOFF_GLOBAL
:
1352 case SYMBOL_GOTOFF_CALL
:
1353 case SYMBOL_GOTOFF_LOADGP
:
1358 case SYMBOL_GOTTPREL
:
1366 /* Return true if X is a symbolic constant whose value is not split
1367 into separate relocations. */
1370 mips_atomic_symbolic_constant_p (rtx x
)
1372 enum mips_symbol_type type
;
1373 return mips_symbolic_constant_p (x
, &type
) && !mips_split_p
[type
];
1377 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1380 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
, int strict
)
1382 if (regno
>= FIRST_PSEUDO_REGISTER
)
1386 regno
= reg_renumber
[regno
];
1389 /* These fake registers will be eliminated to either the stack or
1390 hard frame pointer, both of which are usually valid base registers.
1391 Reload deals with the cases where the eliminated form isn't valid. */
1392 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
1395 /* In mips16 mode, the stack pointer can only address word and doubleword
1396 values, nothing smaller. There are two problems here:
1398 (a) Instantiating virtual registers can introduce new uses of the
1399 stack pointer. If these virtual registers are valid addresses,
1400 the stack pointer should be too.
1402 (b) Most uses of the stack pointer are not made explicit until
1403 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1404 We don't know until that stage whether we'll be eliminating to the
1405 stack pointer (which needs the restriction) or the hard frame
1406 pointer (which doesn't).
1408 All in all, it seems more consistent to only enforce this restriction
1409 during and after reload. */
1410 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
1411 return !strict
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
1413 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
1417 /* Return true if X is a valid base register for the given mode.
1418 Allow only hard registers if STRICT. */
1421 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, int strict
)
1423 if (!strict
&& GET_CODE (x
) == SUBREG
)
1427 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict
));
1431 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1432 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1435 mips_symbolic_address_p (enum mips_symbol_type symbol_type
,
1436 enum machine_mode mode
)
1438 switch (symbol_type
)
1440 case SYMBOL_GENERAL
:
1441 return !TARGET_MIPS16
;
1443 case SYMBOL_SMALL_DATA
:
1446 case SYMBOL_CONSTANT_POOL
:
1447 /* PC-relative addressing is only available for lw and ld. */
1448 return GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
1450 case SYMBOL_GOT_LOCAL
:
1453 case SYMBOL_GOT_GLOBAL
:
1454 /* The address will have to be loaded from the GOT first. */
1461 case SYMBOL_GOTTPREL
:
1465 case SYMBOL_GOTOFF_PAGE
:
1466 case SYMBOL_GOTOFF_GLOBAL
:
1467 case SYMBOL_GOTOFF_CALL
:
1468 case SYMBOL_GOTOFF_LOADGP
:
1469 case SYMBOL_64_HIGH
:
1478 /* Return true if X is a valid address for machine mode MODE. If it is,
1479 fill in INFO appropriately. STRICT is true if we should only accept
1480 hard base registers. */
1483 mips_classify_address (struct mips_address_info
*info
, rtx x
,
1484 enum machine_mode mode
, int strict
)
1486 switch (GET_CODE (x
))
1490 info
->type
= ADDRESS_REG
;
1492 info
->offset
= const0_rtx
;
1493 return mips_valid_base_register_p (info
->reg
, mode
, strict
);
1496 info
->type
= ADDRESS_REG
;
1497 info
->reg
= XEXP (x
, 0);
1498 info
->offset
= XEXP (x
, 1);
1499 return (mips_valid_base_register_p (info
->reg
, mode
, strict
)
1500 && const_arith_operand (info
->offset
, VOIDmode
));
1503 info
->type
= ADDRESS_LO_SUM
;
1504 info
->reg
= XEXP (x
, 0);
1505 info
->offset
= XEXP (x
, 1);
1506 return (mips_valid_base_register_p (info
->reg
, mode
, strict
)
1507 && mips_symbolic_constant_p (info
->offset
, &info
->symbol_type
)
1508 && mips_symbolic_address_p (info
->symbol_type
, mode
)
1509 && mips_lo_relocs
[info
->symbol_type
] != 0);
1512 /* Small-integer addresses don't occur very often, but they
1513 are legitimate if $0 is a valid base register. */
1514 info
->type
= ADDRESS_CONST_INT
;
1515 return !TARGET_MIPS16
&& SMALL_INT (x
);
1520 info
->type
= ADDRESS_SYMBOLIC
;
1521 return (mips_symbolic_constant_p (x
, &info
->symbol_type
)
1522 && mips_symbolic_address_p (info
->symbol_type
, mode
)
1523 && !mips_split_p
[info
->symbol_type
]);
1530 /* Return true if X is a thread-local symbol. */
1533 mips_tls_operand_p (rtx x
)
1535 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1538 /* Return true if X can not be forced into a constant pool. */
1541 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1543 return mips_tls_operand_p (*x
);
1546 /* Return true if X can not be forced into a constant pool. */
1549 mips_cannot_force_const_mem (rtx x
)
1551 if (! TARGET_HAVE_TLS
)
1554 return for_each_rtx (&x
, &mips_tls_symbol_ref_1
, 0);
1557 /* Return the number of instructions needed to load a symbol of the
1558 given type into a register. If valid in an address, the same number
1559 of instructions are needed for loads and stores. Treat extended
1560 mips16 instructions as two instructions. */
1563 mips_symbol_insns (enum mips_symbol_type type
)
1567 case SYMBOL_GENERAL
:
1568 /* In mips16 code, general symbols must be fetched from the
1573 /* When using 64-bit symbols, we need 5 preparatory instructions,
1576 lui $at,%highest(symbol)
1577 daddiu $at,$at,%higher(symbol)
1579 daddiu $at,$at,%hi(symbol)
1582 The final address is then $at + %lo(symbol). With 32-bit
1583 symbols we just need a preparatory lui. */
1584 return (ABI_HAS_64BIT_SYMBOLS
? 6 : 2);
1586 case SYMBOL_SMALL_DATA
:
1589 case SYMBOL_CONSTANT_POOL
:
1590 /* This case is for mips16 only. Assume we'll need an
1591 extended instruction. */
1594 case SYMBOL_GOT_LOCAL
:
1595 case SYMBOL_GOT_GLOBAL
:
1596 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1597 the local/global classification is accurate. See override_options
1600 The worst cases are:
1602 (1) For local symbols when generating o32 or o64 code. The assembler
1608 ...and the final address will be $at + %lo(symbol).
1610 (2) For global symbols when -mxgot. The assembler will use:
1612 lui $at,%got_hi(symbol)
1615 ...and the final address will be $at + %got_lo(symbol). */
1618 case SYMBOL_GOTOFF_PAGE
:
1619 case SYMBOL_GOTOFF_GLOBAL
:
1620 case SYMBOL_GOTOFF_CALL
:
1621 case SYMBOL_GOTOFF_LOADGP
:
1622 case SYMBOL_64_HIGH
:
1628 case SYMBOL_GOTTPREL
:
1630 /* Check whether the offset is a 16- or 32-bit value. */
1631 return mips_split_p
[type
] ? 2 : 1;
1634 /* We don't treat a bare TLS symbol as a constant. */
1640 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1643 mips_stack_address_p (rtx x
, enum machine_mode mode
)
1645 struct mips_address_info addr
;
1647 return (mips_classify_address (&addr
, x
, mode
, false)
1648 && addr
.type
== ADDRESS_REG
1649 && addr
.reg
== stack_pointer_rtx
);
1652 /* Return true if a value at OFFSET bytes from BASE can be accessed
1653 using an unextended mips16 instruction. MODE is the mode of the
1656 Usually the offset in an unextended instruction is a 5-bit field.
1657 The offset is unsigned and shifted left once for HIs, twice
1658 for SIs, and so on. An exception is SImode accesses off the
1659 stack pointer, which have an 8-bit immediate field. */
1662 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
, rtx offset
)
1665 && GET_CODE (offset
) == CONST_INT
1666 && INTVAL (offset
) >= 0
1667 && (INTVAL (offset
) & (GET_MODE_SIZE (mode
) - 1)) == 0)
1669 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
1670 return INTVAL (offset
) < 256 * GET_MODE_SIZE (mode
);
1671 return INTVAL (offset
) < 32 * GET_MODE_SIZE (mode
);
1677 /* Return the number of instructions needed to load or store a value
1678 of mode MODE at X. Return 0 if X isn't valid for MODE.
1680 For mips16 code, count extended instructions as two instructions. */
1683 mips_address_insns (rtx x
, enum machine_mode mode
)
1685 struct mips_address_info addr
;
1688 if (mode
== BLKmode
)
1689 /* BLKmode is used for single unaligned loads and stores. */
1692 /* Each word of a multi-word value will be accessed individually. */
1693 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1695 if (mips_classify_address (&addr
, x
, mode
, false))
1700 && !mips16_unextended_reference_p (mode
, addr
.reg
, addr
.offset
))
1704 case ADDRESS_LO_SUM
:
1705 return (TARGET_MIPS16
? factor
* 2 : factor
);
1707 case ADDRESS_CONST_INT
:
1710 case ADDRESS_SYMBOLIC
:
1711 return factor
* mips_symbol_insns (addr
.symbol_type
);
1717 /* Likewise for constant X. */
1720 mips_const_insns (rtx x
)
1722 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
1723 enum mips_symbol_type symbol_type
;
1724 HOST_WIDE_INT offset
;
1726 switch (GET_CODE (x
))
1730 || !mips_symbolic_constant_p (XEXP (x
, 0), &symbol_type
)
1731 || !mips_split_p
[symbol_type
])
1738 /* Unsigned 8-bit constants can be loaded using an unextended
1739 LI instruction. Unsigned 16-bit constants can be loaded
1740 using an extended LI. Negative constants must be loaded
1741 using LI and then negated. */
1742 return (INTVAL (x
) >= 0 && INTVAL (x
) < 256 ? 1
1743 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
1744 : INTVAL (x
) > -256 && INTVAL (x
) < 0 ? 2
1745 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
1748 return mips_build_integer (codes
, INTVAL (x
));
1752 return (!TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0);
1758 /* See if we can refer to X directly. */
1759 if (mips_symbolic_constant_p (x
, &symbol_type
))
1760 return mips_symbol_insns (symbol_type
);
1762 /* Otherwise try splitting the constant into a base and offset.
1763 16-bit offsets can be added using an extra addiu. Larger offsets
1764 must be calculated separately and then added to the base. */
1765 mips_split_const (x
, &x
, &offset
);
1768 int n
= mips_const_insns (x
);
1771 if (SMALL_OPERAND (offset
))
1774 return n
+ 1 + mips_build_integer (codes
, offset
);
1781 return mips_symbol_insns (mips_classify_symbol (x
));
1789 /* Return the number of instructions needed for memory reference X.
1790 Count extended mips16 instructions as two instructions. */
1793 mips_fetch_insns (rtx x
)
1795 gcc_assert (MEM_P (x
));
1796 return mips_address_insns (XEXP (x
, 0), GET_MODE (x
));
1800 /* Return the number of instructions needed for an integer division. */
1803 mips_idiv_insns (void)
1808 if (TARGET_CHECK_ZERO_DIV
)
1810 if (GENERATE_DIVIDE_TRAPS
)
1816 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
1821 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1822 returns a nonzero value if X is a legitimate address for a memory
1823 operand of the indicated MODE. STRICT is nonzero if this function
1824 is called during reload. */
1827 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1829 struct mips_address_info addr
;
1831 return mips_classify_address (&addr
, x
, mode
, strict
);
1835 /* Copy VALUE to a register and return that register. If new psuedos
1836 are allowed, copy it into a new register, otherwise use DEST. */
1839 mips_force_temporary (rtx dest
, rtx value
)
1841 if (!no_new_pseudos
)
1842 return force_reg (Pmode
, value
);
1845 emit_move_insn (copy_rtx (dest
), value
);
1851 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1852 and is used to load the high part into a register. */
1855 mips_split_symbol (rtx temp
, rtx addr
)
1860 high
= mips16_gp_pseudo_reg ();
1862 high
= mips_force_temporary (temp
, gen_rtx_HIGH (Pmode
, copy_rtx (addr
)));
1863 return gen_rtx_LO_SUM (Pmode
, high
, addr
);
1867 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1868 type SYMBOL_TYPE. */
1871 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
1874 HOST_WIDE_INT offset
;
1876 mips_split_const (address
, &base
, &offset
);
1877 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
1878 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
1879 return plus_constant (gen_rtx_CONST (Pmode
, base
), offset
);
1883 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1884 high part to BASE and return the result. Just return BASE otherwise.
1885 TEMP is available as a temporary register if needed.
1887 The returned expression can be used as the first operand to a LO_SUM. */
1890 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
1891 enum mips_symbol_type symbol_type
)
1893 if (mips_split_p
[symbol_type
])
1895 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
1896 addr
= mips_force_temporary (temp
, addr
);
1897 return mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
1903 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1904 mips_force_temporary; it is only needed when OFFSET is not a
1908 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
1910 if (!SMALL_OPERAND (offset
))
1915 /* Load the full offset into a register so that we can use
1916 an unextended instruction for the address itself. */
1917 high
= GEN_INT (offset
);
1922 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1923 high
= GEN_INT (CONST_HIGH_PART (offset
));
1924 offset
= CONST_LOW_PART (offset
);
1926 high
= mips_force_temporary (temp
, high
);
1927 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
1929 return plus_constant (reg
, offset
);
1932 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1933 referencing, and TYPE is the symbol type to use (either global
1934 dynamic or local dynamic). V0 is an RTX for the return value
1935 location. The entire insn sequence is returned. */
1937 static GTY(()) rtx mips_tls_symbol
;
1940 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
1942 rtx insn
, loc
, tga
, a0
;
1944 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
1946 if (!mips_tls_symbol
)
1947 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
1949 loc
= mips_unspec_address (sym
, type
);
1953 emit_insn (gen_rtx_SET (Pmode
, a0
,
1954 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
1955 tga
= gen_rtx_MEM (Pmode
, mips_tls_symbol
);
1956 insn
= emit_call_insn (gen_call_value (v0
, tga
, const0_rtx
, const0_rtx
));
1957 CONST_OR_PURE_CALL_P (insn
) = 1;
1958 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), v0
);
1959 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
1960 insn
= get_insns ();
1967 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
1968 return value will be a valid address and move_operand (either a REG
1972 mips_legitimize_tls_address (rtx loc
)
1974 rtx dest
, insn
, v0
, v1
, tmp1
, tmp2
, eqv
;
1975 enum tls_model model
;
1977 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
1978 v1
= gen_rtx_REG (Pmode
, GP_RETURN
+ 1);
1980 model
= SYMBOL_REF_TLS_MODEL (loc
);
1984 case TLS_MODEL_GLOBAL_DYNAMIC
:
1985 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
1986 dest
= gen_reg_rtx (Pmode
);
1987 emit_libcall_block (insn
, dest
, v0
, loc
);
1990 case TLS_MODEL_LOCAL_DYNAMIC
:
1991 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
1992 tmp1
= gen_reg_rtx (Pmode
);
1994 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
1995 share the LDM result with other LD model accesses. */
1996 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1998 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2000 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2001 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
,
2002 mips_unspec_address (loc
, SYMBOL_DTPREL
));
2005 case TLS_MODEL_INITIAL_EXEC
:
2006 tmp1
= gen_reg_rtx (Pmode
);
2007 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2008 if (Pmode
== DImode
)
2010 emit_insn (gen_tls_get_tp_di (v1
));
2011 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2015 emit_insn (gen_tls_get_tp_si (v1
));
2016 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2018 dest
= gen_reg_rtx (Pmode
);
2019 emit_insn (gen_add3_insn (dest
, tmp1
, v1
));
2022 case TLS_MODEL_LOCAL_EXEC
:
2024 if (Pmode
== DImode
)
2025 emit_insn (gen_tls_get_tp_di (v1
));
2027 emit_insn (gen_tls_get_tp_si (v1
));
2029 tmp1
= mips_unspec_offset_high (NULL
, v1
, loc
, SYMBOL_TPREL
);
2030 dest
= gen_rtx_LO_SUM (Pmode
, tmp1
,
2031 mips_unspec_address (loc
, SYMBOL_TPREL
));
2041 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2042 be legitimized in a way that the generic machinery might not expect,
2043 put the new address in *XLOC and return true. MODE is the mode of
2044 the memory being accessed. */
2047 mips_legitimize_address (rtx
*xloc
, enum machine_mode mode
)
2049 enum mips_symbol_type symbol_type
;
2051 if (mips_tls_operand_p (*xloc
))
2053 *xloc
= mips_legitimize_tls_address (*xloc
);
2057 /* See if the address can split into a high part and a LO_SUM. */
2058 if (mips_symbolic_constant_p (*xloc
, &symbol_type
)
2059 && mips_symbolic_address_p (symbol_type
, mode
)
2060 && mips_split_p
[symbol_type
])
2062 *xloc
= mips_split_symbol (0, *xloc
);
2066 if (GET_CODE (*xloc
) == PLUS
&& GET_CODE (XEXP (*xloc
, 1)) == CONST_INT
)
2068 /* Handle REG + CONSTANT using mips_add_offset. */
2071 reg
= XEXP (*xloc
, 0);
2072 if (!mips_valid_base_register_p (reg
, mode
, 0))
2073 reg
= copy_to_mode_reg (Pmode
, reg
);
2074 *xloc
= mips_add_offset (0, reg
, INTVAL (XEXP (*xloc
, 1)));
2082 /* Subroutine of mips_build_integer (with the same interface).
2083 Assume that the final action in the sequence should be a left shift. */
2086 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
2088 unsigned int i
, shift
;
2090 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2091 since signed numbers are easier to load than unsigned ones. */
2093 while ((value
& 1) == 0)
2094 value
/= 2, shift
++;
2096 i
= mips_build_integer (codes
, value
);
2097 codes
[i
].code
= ASHIFT
;
2098 codes
[i
].value
= shift
;
2103 /* As for mips_build_shift, but assume that the final action will be
2104 an IOR or PLUS operation. */
2107 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
2109 unsigned HOST_WIDE_INT high
;
2112 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
2113 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
2115 /* The constant is too complex to load with a simple lui/ori pair
2116 so our goal is to clear as many trailing zeros as possible.
2117 In this case, we know bit 16 is set and that the low 16 bits
2118 form a negative number. If we subtract that number from VALUE,
2119 we will clear at least the lowest 17 bits, maybe more. */
2120 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
2121 codes
[i
].code
= PLUS
;
2122 codes
[i
].value
= CONST_LOW_PART (value
);
2126 i
= mips_build_integer (codes
, high
);
2127 codes
[i
].code
= IOR
;
2128 codes
[i
].value
= value
& 0xffff;
2134 /* Fill CODES with a sequence of rtl operations to load VALUE.
2135 Return the number of operations needed. */
2138 mips_build_integer (struct mips_integer_op
*codes
,
2139 unsigned HOST_WIDE_INT value
)
2141 if (SMALL_OPERAND (value
)
2142 || SMALL_OPERAND_UNSIGNED (value
)
2143 || LUI_OPERAND (value
))
2145 /* The value can be loaded with a single instruction. */
2146 codes
[0].code
= UNKNOWN
;
2147 codes
[0].value
= value
;
2150 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
2152 /* Either the constant is a simple LUI/ORI combination or its
2153 lowest bit is set. We don't want to shift in this case. */
2154 return mips_build_lower (codes
, value
);
2156 else if ((value
& 0xffff) == 0)
2158 /* The constant will need at least three actions. The lowest
2159 16 bits are clear, so the final action will be a shift. */
2160 return mips_build_shift (codes
, value
);
2164 /* The final action could be a shift, add or inclusive OR.
2165 Rather than use a complex condition to select the best
2166 approach, try both mips_build_shift and mips_build_lower
2167 and pick the one that gives the shortest sequence.
2168 Note that this case is only used once per constant. */
2169 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
2170 unsigned int cost
, alt_cost
;
2172 cost
= mips_build_shift (codes
, value
);
2173 alt_cost
= mips_build_lower (alt_codes
, value
);
2174 if (alt_cost
< cost
)
2176 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
2184 /* Move VALUE into register DEST. */
2187 mips_move_integer (rtx dest
, unsigned HOST_WIDE_INT value
)
2189 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2190 enum machine_mode mode
;
2191 unsigned int i
, cost
;
2194 mode
= GET_MODE (dest
);
2195 cost
= mips_build_integer (codes
, value
);
2197 /* Apply each binary operation to X. Invariant: X is a legitimate
2198 source operand for a SET pattern. */
2199 x
= GEN_INT (codes
[0].value
);
2200 for (i
= 1; i
< cost
; i
++)
2203 emit_move_insn (dest
, x
), x
= dest
;
2205 x
= force_reg (mode
, x
);
2206 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
2209 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
2213 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2214 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2218 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
2221 HOST_WIDE_INT offset
;
2222 enum mips_symbol_type symbol_type
;
2224 /* Split moves of big integers into smaller pieces. In mips16 code,
2225 it's better to force the constant into memory instead. */
2226 if (GET_CODE (src
) == CONST_INT
&& !TARGET_MIPS16
)
2228 mips_move_integer (dest
, INTVAL (src
));
2232 if (mips_tls_operand_p (src
))
2234 emit_move_insn (dest
, mips_legitimize_tls_address (src
));
2238 /* See if the symbol can be split. For mips16, this is often worse than
2239 forcing it in the constant pool since it needs the single-register form
2240 of addiu or daddiu. */
2242 && mips_symbolic_constant_p (src
, &symbol_type
)
2243 && mips_split_p
[symbol_type
])
2245 emit_move_insn (dest
, mips_split_symbol (dest
, src
));
2249 /* If we have (const (plus symbol offset)), load the symbol first
2250 and then add in the offset. This is usually better than forcing
2251 the constant into memory, at least in non-mips16 code. */
2252 mips_split_const (src
, &base
, &offset
);
2255 && (!no_new_pseudos
|| SMALL_OPERAND (offset
)))
2257 base
= mips_force_temporary (dest
, base
);
2258 emit_move_insn (dest
, mips_add_offset (0, base
, offset
));
2262 src
= force_const_mem (mode
, src
);
2264 /* When using explicit relocs, constant pool references are sometimes
2265 not legitimate addresses. */
2266 if (!memory_operand (src
, VOIDmode
))
2267 src
= replace_equiv_address (src
, mips_split_symbol (dest
, XEXP (src
, 0)));
2268 emit_move_insn (dest
, src
);
2272 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2273 sequence that is valid. */
2276 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
2278 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
2280 emit_move_insn (dest
, force_reg (mode
, src
));
2284 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2285 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
2286 && REG_P (src
) && MD_REG_P (REGNO (src
))
2287 && REG_P (dest
) && GP_REG_P (REGNO (dest
)))
2289 int other_regno
= REGNO (src
) == HI_REGNUM
? LO_REGNUM
: HI_REGNUM
;
2290 if (GET_MODE_SIZE (mode
) <= 4)
2291 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode
, REGNO (dest
)),
2292 gen_rtx_REG (SImode
, REGNO (src
)),
2293 gen_rtx_REG (SImode
, other_regno
)));
2295 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode
, REGNO (dest
)),
2296 gen_rtx_REG (DImode
, REGNO (src
)),
2297 gen_rtx_REG (DImode
, other_regno
)));
2301 /* We need to deal with constants that would be legitimate
2302 immediate_operands but not legitimate move_operands. */
2303 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
2305 mips_legitimize_const_move (mode
, dest
, src
);
2306 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
2312 /* We need a lot of little routines to check constant values on the
2313 mips16. These are used to figure out how long the instruction will
2314 be. It would be much better to do this using constraints, but
2315 there aren't nearly enough letters available. */
2318 m16_check_op (rtx op
, int low
, int high
, int mask
)
2320 return (GET_CODE (op
) == CONST_INT
2321 && INTVAL (op
) >= low
2322 && INTVAL (op
) <= high
2323 && (INTVAL (op
) & mask
) == 0);
2327 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2329 return m16_check_op (op
, 0x1, 0x8, 0);
2333 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2335 return m16_check_op (op
, - 0x8, 0x7, 0);
2339 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2341 return m16_check_op (op
, - 0x7, 0x8, 0);
2345 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2347 return m16_check_op (op
, - 0x10, 0xf, 0);
2351 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2353 return m16_check_op (op
, - 0xf, 0x10, 0);
2357 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2359 return m16_check_op (op
, (- 0x10) << 2, 0xf << 2, 3);
2363 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2365 return m16_check_op (op
, (- 0xf) << 2, 0x10 << 2, 3);
2369 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2371 return m16_check_op (op
, - 0x80, 0x7f, 0);
2375 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2377 return m16_check_op (op
, - 0x7f, 0x80, 0);
2381 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2383 return m16_check_op (op
, 0x0, 0xff, 0);
2387 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2389 return m16_check_op (op
, - 0xff, 0x0, 0);
2393 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2395 return m16_check_op (op
, - 0x1, 0xfe, 0);
2399 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2401 return m16_check_op (op
, 0x0, 0xff << 2, 3);
2405 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2407 return m16_check_op (op
, (- 0xff) << 2, 0x0, 3);
2411 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2413 return m16_check_op (op
, (- 0x80) << 3, 0x7f << 3, 7);
2417 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2419 return m16_check_op (op
, (- 0x7f) << 3, 0x80 << 3, 7);
2423 mips_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2425 enum machine_mode mode
= GET_MODE (x
);
2426 bool float_mode_p
= FLOAT_MODE_P (mode
);
2433 /* A number between 1 and 8 inclusive is efficient for a shift.
2434 Otherwise, we will need an extended instruction. */
2435 if ((outer_code
) == ASHIFT
|| (outer_code
) == ASHIFTRT
2436 || (outer_code
) == LSHIFTRT
)
2438 if (INTVAL (x
) >= 1 && INTVAL (x
) <= 8)
2441 *total
= COSTS_N_INSNS (1);
2445 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2446 if ((outer_code
) == XOR
2447 && INTVAL (x
) >= 0 && INTVAL (x
) < 0x10000)
2453 /* We may be able to use slt or sltu for a comparison with a
2454 signed 16 bit value. (The boundary conditions aren't quite
2455 right, but this is just a heuristic anyhow.) */
2456 if (((outer_code
) == LT
|| (outer_code
) == LE
2457 || (outer_code
) == GE
|| (outer_code
) == GT
2458 || (outer_code
) == LTU
|| (outer_code
) == LEU
2459 || (outer_code
) == GEU
|| (outer_code
) == GTU
)
2460 && INTVAL (x
) >= -0x8000 && INTVAL (x
) < 0x8000)
2466 /* Equality comparisons with 0 are cheap. */
2467 if (((outer_code
) == EQ
|| (outer_code
) == NE
)
2474 /* Constants in the range 0...255 can be loaded with an unextended
2475 instruction. They are therefore as cheap as a register move.
2477 Given the choice between "li R1,0...255" and "move R1,R2"
2478 (where R2 is a known constant), it is usually better to use "li",
2479 since we do not want to unnecessarily extend the lifetime
2481 if (outer_code
== SET
2483 && INTVAL (x
) < 256)
2491 /* These can be used anywhere. */
2496 /* Otherwise fall through to the handling below because
2497 we'll need to construct the constant. */
2503 if (LEGITIMATE_CONSTANT_P (x
))
2505 *total
= COSTS_N_INSNS (1);
2510 /* The value will need to be fetched from the constant pool. */
2511 *total
= CONSTANT_POOL_COST
;
2517 /* If the address is legitimate, return the number of
2518 instructions it needs, otherwise use the default handling. */
2519 int n
= mips_address_insns (XEXP (x
, 0), GET_MODE (x
));
2522 *total
= COSTS_N_INSNS (n
+ 1);
2529 *total
= COSTS_N_INSNS (6);
2533 *total
= COSTS_N_INSNS ((mode
== DImode
&& !TARGET_64BIT
) ? 2 : 1);
2539 if (mode
== DImode
&& !TARGET_64BIT
)
2541 *total
= COSTS_N_INSNS (2);
2549 if (mode
== DImode
&& !TARGET_64BIT
)
2551 *total
= COSTS_N_INSNS ((GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2559 *total
= COSTS_N_INSNS (1);
2561 *total
= COSTS_N_INSNS (4);
2565 *total
= COSTS_N_INSNS (1);
2572 *total
= mips_cost
->fp_add
;
2576 else if (mode
== DImode
&& !TARGET_64BIT
)
2578 *total
= COSTS_N_INSNS (4);
2584 if (mode
== DImode
&& !TARGET_64BIT
)
2586 *total
= COSTS_N_INSNS (4);
2593 *total
= mips_cost
->fp_mult_sf
;
2595 else if (mode
== DFmode
)
2596 *total
= mips_cost
->fp_mult_df
;
2598 else if (mode
== SImode
)
2599 *total
= mips_cost
->int_mult_si
;
2602 *total
= mips_cost
->int_mult_di
;
2611 *total
= mips_cost
->fp_div_sf
;
2613 *total
= mips_cost
->fp_div_df
;
2622 *total
= mips_cost
->int_div_di
;
2624 *total
= mips_cost
->int_div_si
;
2629 /* A sign extend from SImode to DImode in 64 bit mode is often
2630 zero instructions, because the result can often be used
2631 directly by another instruction; we'll call it one. */
2632 if (TARGET_64BIT
&& mode
== DImode
2633 && GET_MODE (XEXP (x
, 0)) == SImode
)
2634 *total
= COSTS_N_INSNS (1);
2636 *total
= COSTS_N_INSNS (2);
2640 if (TARGET_64BIT
&& mode
== DImode
2641 && GET_MODE (XEXP (x
, 0)) == SImode
)
2642 *total
= COSTS_N_INSNS (2);
2644 *total
= COSTS_N_INSNS (1);
2648 case UNSIGNED_FLOAT
:
2651 case FLOAT_TRUNCATE
:
2653 *total
= mips_cost
->fp_add
;
2661 /* Provide the costs of an addressing mode that contains ADDR.
2662 If ADDR is not a valid address, its cost is irrelevant. */
2665 mips_address_cost (rtx addr
)
2667 return mips_address_insns (addr
, SImode
);
2670 /* Return one word of double-word value OP, taking into account the fixed
2671 endianness of certain registers. HIGH_P is true to select the high part,
2672 false to select the low part. */
2675 mips_subword (rtx op
, int high_p
)
2678 enum machine_mode mode
;
2680 mode
= GET_MODE (op
);
2681 if (mode
== VOIDmode
)
2684 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
2685 byte
= UNITS_PER_WORD
;
2691 if (FP_REG_P (REGNO (op
)))
2692 return gen_rtx_REG (word_mode
, high_p
? REGNO (op
) + 1 : REGNO (op
));
2693 if (ACC_HI_REG_P (REGNO (op
)))
2694 return gen_rtx_REG (word_mode
, high_p
? REGNO (op
) : REGNO (op
) + 1);
2698 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
2700 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
2704 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2707 mips_split_64bit_move_p (rtx dest
, rtx src
)
2712 /* FP->FP moves can be done in a single instruction. */
2713 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
2716 /* Check for floating-point loads and stores. They can be done using
2717 ldc1 and sdc1 on MIPS II and above. */
2720 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
2722 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
2729 /* Split a 64-bit move from SRC to DEST assuming that
2730 mips_split_64bit_move_p holds.
2732 Moves into and out of FPRs cause some difficulty here. Such moves
2733 will always be DFmode, since paired FPRs are not allowed to store
2734 DImode values. The most natural representation would be two separate
2735 32-bit moves, such as:
2737 (set (reg:SI $f0) (mem:SI ...))
2738 (set (reg:SI $f1) (mem:SI ...))
2740 However, the second insn is invalid because odd-numbered FPRs are
2741 not allowed to store independent values. Use the patterns load_df_low,
2742 load_df_high and store_df_high instead. */
2745 mips_split_64bit_move (rtx dest
, rtx src
)
2747 if (FP_REG_RTX_P (dest
))
2749 /* Loading an FPR from memory or from GPRs. */
2750 emit_insn (gen_load_df_low (copy_rtx (dest
), mips_subword (src
, 0)));
2751 emit_insn (gen_load_df_high (dest
, mips_subword (src
, 1),
2754 else if (FP_REG_RTX_P (src
))
2756 /* Storing an FPR into memory or GPRs. */
2757 emit_move_insn (mips_subword (dest
, 0), mips_subword (src
, 0));
2758 emit_insn (gen_store_df_high (mips_subword (dest
, 1), src
));
2762 /* The operation can be split into two normal moves. Decide in
2763 which order to do them. */
2766 low_dest
= mips_subword (dest
, 0);
2767 if (REG_P (low_dest
)
2768 && reg_overlap_mentioned_p (low_dest
, src
))
2770 emit_move_insn (mips_subword (dest
, 1), mips_subword (src
, 1));
2771 emit_move_insn (low_dest
, mips_subword (src
, 0));
2775 emit_move_insn (low_dest
, mips_subword (src
, 0));
2776 emit_move_insn (mips_subword (dest
, 1), mips_subword (src
, 1));
2781 /* Return the appropriate instructions to move SRC into DEST. Assume
2782 that SRC is operand 1 and DEST is operand 0. */
2785 mips_output_move (rtx dest
, rtx src
)
2787 enum rtx_code dest_code
, src_code
;
2790 dest_code
= GET_CODE (dest
);
2791 src_code
= GET_CODE (src
);
2792 dbl_p
= (GET_MODE_SIZE (GET_MODE (dest
)) == 8);
2794 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
2797 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
2798 || (!TARGET_MIPS16
&& src
== CONST0_RTX (GET_MODE (dest
))))
2800 if (dest_code
== REG
)
2802 if (GP_REG_P (REGNO (dest
)))
2803 return "move\t%0,%z1";
2805 if (MD_REG_P (REGNO (dest
)))
2808 if (DSP_ACC_REG_P (REGNO (dest
)))
2810 static char retval
[] = "mt__\t%z1,%q0";
2811 retval
[2] = reg_names
[REGNO (dest
)][4];
2812 retval
[3] = reg_names
[REGNO (dest
)][5];
2816 if (FP_REG_P (REGNO (dest
)))
2817 return (dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2819 if (ALL_COP_REG_P (REGNO (dest
)))
2821 static char retval
[] = "dmtc_\t%z1,%0";
2823 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
2824 return (dbl_p
? retval
: retval
+ 1);
2827 if (dest_code
== MEM
)
2828 return (dbl_p
? "sd\t%z1,%0" : "sw\t%z1,%0");
2830 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
2832 if (src_code
== REG
)
2834 if (DSP_ACC_REG_P (REGNO (src
)))
2836 static char retval
[] = "mf__\t%0,%q1";
2837 retval
[2] = reg_names
[REGNO (src
)][4];
2838 retval
[3] = reg_names
[REGNO (src
)][5];
2842 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
2843 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2845 if (FP_REG_P (REGNO (src
)))
2846 return (dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2848 if (ALL_COP_REG_P (REGNO (src
)))
2850 static char retval
[] = "dmfc_\t%0,%1";
2852 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
2853 return (dbl_p
? retval
: retval
+ 1);
2857 if (src_code
== MEM
)
2858 return (dbl_p
? "ld\t%0,%1" : "lw\t%0,%1");
2860 if (src_code
== CONST_INT
)
2862 /* Don't use the X format, because that will give out of
2863 range numbers for 64 bit hosts and 32 bit targets. */
2865 return "li\t%0,%1\t\t\t# %X1";
2867 if (INTVAL (src
) >= 0 && INTVAL (src
) <= 0xffff)
2870 if (INTVAL (src
) < 0 && INTVAL (src
) >= -0xffff)
2874 if (src_code
== HIGH
)
2875 return "lui\t%0,%h1";
2877 if (CONST_GP_P (src
))
2878 return "move\t%0,%1";
2880 if (symbolic_operand (src
, VOIDmode
))
2881 return (dbl_p
? "dla\t%0,%1" : "la\t%0,%1");
2883 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
2885 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2887 if (GET_MODE (dest
) == V2SFmode
)
2888 return "mov.ps\t%0,%1";
2890 return (dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2893 if (dest_code
== MEM
)
2894 return (dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0");
2896 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2898 if (src_code
== MEM
)
2899 return (dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2901 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
2903 static char retval
[] = "l_c_\t%0,%1";
2905 retval
[1] = (dbl_p
? 'd' : 'w');
2906 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
2909 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
2911 static char retval
[] = "s_c_\t%1,%0";
2913 retval
[1] = (dbl_p
? 'd' : 'w');
2914 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
2920 /* Restore $gp from its save slot. Valid only when using o32 or
2924 mips_restore_gp (void)
2928 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
);
2930 address
= mips_add_offset (pic_offset_table_rtx
,
2931 frame_pointer_needed
2932 ? hard_frame_pointer_rtx
2933 : stack_pointer_rtx
,
2934 current_function_outgoing_args_size
);
2935 slot
= gen_rtx_MEM (Pmode
, address
);
2937 emit_move_insn (pic_offset_table_rtx
, slot
);
2938 if (!TARGET_EXPLICIT_RELOCS
)
2939 emit_insn (gen_blockage ());
2942 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2945 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2947 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2948 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2951 /* Return true if CMP1 is a suitable second operand for relational
2952 operator CODE. See also the *sCC patterns in mips.md. */
2955 mips_relational_operand_ok_p (enum rtx_code code
, rtx cmp1
)
2961 return reg_or_0_operand (cmp1
, VOIDmode
);
2965 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
2969 return arith_operand (cmp1
, VOIDmode
);
2972 return sle_operand (cmp1
, VOIDmode
);
2975 return sleu_operand (cmp1
, VOIDmode
);
2982 /* Canonicalize LE or LEU comparisons into LT comparisons when
2983 possible to avoid extra instructions or inverting the
2987 mips_canonicalize_comparison (enum rtx_code
*code
, rtx
*cmp1
,
2988 enum machine_mode mode
)
2990 HOST_WIDE_INT original
, plus_one
;
2992 if (GET_CODE (*cmp1
) != CONST_INT
)
2995 original
= INTVAL (*cmp1
);
2996 plus_one
= trunc_int_for_mode ((unsigned HOST_WIDE_INT
) original
+ 1, mode
);
3001 if (original
< plus_one
)
3004 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
3013 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
3026 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3027 result in TARGET. CMP0 and TARGET are register_operands that have
3028 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3029 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3032 mips_emit_int_relational (enum rtx_code code
, bool *invert_ptr
,
3033 rtx target
, rtx cmp0
, rtx cmp1
)
3035 /* First see if there is a MIPS instruction that can do this operation
3036 with CMP1 in its current form. If not, try to canonicalize the
3037 comparison to LT. If that fails, try doing the same for the
3038 inverse operation. If that also fails, force CMP1 into a register
3040 if (mips_relational_operand_ok_p (code
, cmp1
))
3041 mips_emit_binary (code
, target
, cmp0
, cmp1
);
3042 else if (mips_canonicalize_comparison (&code
, &cmp1
, GET_MODE (target
)))
3043 mips_emit_binary (code
, target
, cmp0
, cmp1
);
3046 enum rtx_code inv_code
= reverse_condition (code
);
3047 if (!mips_relational_operand_ok_p (inv_code
, cmp1
))
3049 cmp1
= force_reg (GET_MODE (cmp0
), cmp1
);
3050 mips_emit_int_relational (code
, invert_ptr
, target
, cmp0
, cmp1
);
3052 else if (invert_ptr
== 0)
3054 rtx inv_target
= gen_reg_rtx (GET_MODE (target
));
3055 mips_emit_binary (inv_code
, inv_target
, cmp0
, cmp1
);
3056 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
3060 *invert_ptr
= !*invert_ptr
;
3061 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
3066 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3067 The register will have the same mode as CMP0. */
3070 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
3072 if (cmp1
== const0_rtx
)
3075 if (uns_arith_operand (cmp1
, VOIDmode
))
3076 return expand_binop (GET_MODE (cmp0
), xor_optab
,
3077 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
3079 return expand_binop (GET_MODE (cmp0
), sub_optab
,
3080 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
3083 /* Convert a comparison into something that can be used in a branch or
3084 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3085 being compared and *CODE is the code used to compare them.
3087 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3088 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3089 otherwise any standard branch condition can be used. The standard branch
3092 - EQ/NE between two registers.
3093 - any comparison between a register and zero. */
3096 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
3098 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) == MODE_INT
)
3100 if (!need_eq_ne_p
&& cmp_operands
[1] == const0_rtx
)
3102 *op0
= cmp_operands
[0];
3103 *op1
= cmp_operands
[1];
3105 else if (*code
== EQ
|| *code
== NE
)
3109 *op0
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
3114 *op0
= cmp_operands
[0];
3115 *op1
= force_reg (GET_MODE (*op0
), cmp_operands
[1]);
3120 /* The comparison needs a separate scc instruction. Store the
3121 result of the scc in *OP0 and compare it against zero. */
3122 bool invert
= false;
3123 *op0
= gen_reg_rtx (GET_MODE (cmp_operands
[0]));
3125 mips_emit_int_relational (*code
, &invert
, *op0
,
3126 cmp_operands
[0], cmp_operands
[1]);
3127 *code
= (invert
? EQ
: NE
);
3132 enum rtx_code cmp_code
;
3134 /* Floating-point tests use a separate c.cond.fmt comparison to
3135 set a condition code register. The branch or conditional move
3136 will then compare that register against zero.
3138 Set CMP_CODE to the code of the comparison instruction and
3139 *CODE to the code that the branch or move should use. */
3145 cmp_code
= reverse_condition_maybe_unordered (*code
);
3155 ? gen_reg_rtx (CCmode
)
3156 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
3158 mips_emit_binary (cmp_code
, *op0
, cmp_operands
[0], cmp_operands
[1]);
3162 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3163 Store the result in TARGET and return true if successful.
3165 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3168 mips_emit_scc (enum rtx_code code
, rtx target
)
3170 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) != MODE_INT
)
3173 target
= gen_lowpart (GET_MODE (cmp_operands
[0]), target
);
3174 if (code
== EQ
|| code
== NE
)
3176 rtx zie
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
3177 mips_emit_binary (code
, target
, zie
, const0_rtx
);
3180 mips_emit_int_relational (code
, 0, target
,
3181 cmp_operands
[0], cmp_operands
[1]);
3185 /* Emit the common code for doing conditional branches.
3186 operand[0] is the label to jump to.
3187 The comparison operands are saved away by cmp{si,di,sf,df}. */
3190 gen_conditional_branch (rtx
*operands
, enum rtx_code code
)
3192 rtx op0
, op1
, target
;
3194 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
3195 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3196 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3198 gen_rtx_LABEL_REF (VOIDmode
, operands
[0]),
3200 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, target
));
3203 /* Emit the common code for conditional moves. OPERANDS is the array
3204 of operands passed to the conditional move define_expand. */
3207 gen_conditional_move (rtx
*operands
)
3212 code
= GET_CODE (operands
[1]);
3213 mips_emit_compare (&code
, &op0
, &op1
, true);
3214 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
3215 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
3216 gen_rtx_fmt_ee (code
,
3219 operands
[2], operands
[3])));
3222 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3223 the conditional_trap expander. */
3226 mips_gen_conditional_trap (rtx
*operands
)
3229 enum rtx_code cmp_code
= GET_CODE (operands
[0]);
3230 enum machine_mode mode
= GET_MODE (cmp_operands
[0]);
3232 /* MIPS conditional trap machine instructions don't have GT or LE
3233 flavors, so we must invert the comparison and convert to LT and
3234 GE, respectively. */
3237 case GT
: cmp_code
= LT
; break;
3238 case LE
: cmp_code
= GE
; break;
3239 case GTU
: cmp_code
= LTU
; break;
3240 case LEU
: cmp_code
= GEU
; break;
3243 if (cmp_code
== GET_CODE (operands
[0]))
3245 op0
= cmp_operands
[0];
3246 op1
= cmp_operands
[1];
3250 op0
= cmp_operands
[1];
3251 op1
= cmp_operands
[0];
3253 op0
= force_reg (mode
, op0
);
3254 if (!arith_operand (op1
, mode
))
3255 op1
= force_reg (mode
, op1
);
3257 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
3258 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
),
3262 /* Load function address ADDR into register DEST. SIBCALL_P is true
3263 if the address is needed for a sibling call. */
3266 mips_load_call_address (rtx dest
, rtx addr
, int sibcall_p
)
3268 /* If we're generating PIC, and this call is to a global function,
3269 try to allow its address to be resolved lazily. This isn't
3270 possible for NewABI sibcalls since the value of $gp on entry
3271 to the stub would be our caller's gp, not ours. */
3272 if (TARGET_EXPLICIT_RELOCS
3273 && !(sibcall_p
&& TARGET_NEWABI
)
3274 && global_got_operand (addr
, VOIDmode
))
3276 rtx high
, lo_sum_symbol
;
3278 high
= mips_unspec_offset_high (dest
, pic_offset_table_rtx
,
3279 addr
, SYMBOL_GOTOFF_CALL
);
3280 lo_sum_symbol
= mips_unspec_address (addr
, SYMBOL_GOTOFF_CALL
);
3281 if (Pmode
== SImode
)
3282 emit_insn (gen_load_callsi (dest
, high
, lo_sum_symbol
));
3284 emit_insn (gen_load_calldi (dest
, high
, lo_sum_symbol
));
3287 emit_move_insn (dest
, addr
);
3291 /* Expand a call or call_value instruction. RESULT is where the
3292 result will go (null for calls), ADDR is the address of the
3293 function, ARGS_SIZE is the size of the arguments and AUX is
3294 the value passed to us by mips_function_arg. SIBCALL_P is true
3295 if we are expanding a sibling call, false if we're expanding
3299 mips_expand_call (rtx result
, rtx addr
, rtx args_size
, rtx aux
, int sibcall_p
)
3301 rtx orig_addr
, pattern
, insn
;
3304 if (!call_insn_operand (addr
, VOIDmode
))
3306 addr
= gen_reg_rtx (Pmode
);
3307 mips_load_call_address (addr
, orig_addr
, sibcall_p
);
3311 && mips16_hard_float
3312 && build_mips16_call_stub (result
, addr
, args_size
,
3313 aux
== 0 ? 0 : (int) GET_MODE (aux
)))
3317 pattern
= (sibcall_p
3318 ? gen_sibcall_internal (addr
, args_size
)
3319 : gen_call_internal (addr
, args_size
));
3320 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
3324 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
3325 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
3328 ? gen_sibcall_value_multiple_internal (reg1
, addr
, args_size
, reg2
)
3329 : gen_call_value_multiple_internal (reg1
, addr
, args_size
, reg2
));
3332 pattern
= (sibcall_p
3333 ? gen_sibcall_value_internal (result
, addr
, args_size
)
3334 : gen_call_value_internal (result
, addr
, args_size
));
3336 insn
= emit_call_insn (pattern
);
3338 /* Lazy-binding stubs require $gp to be valid on entry. */
3339 if (global_got_operand (orig_addr
, VOIDmode
))
3340 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3344 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3347 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
3348 tree exp ATTRIBUTE_UNUSED
)
3350 return TARGET_SIBCALLS
;
3353 /* Emit code to move general operand SRC into condition-code
3354 register DEST. SCRATCH is a scratch TFmode float register.
3361 where FP1 and FP2 are single-precision float registers
3362 taken from SCRATCH. */
3365 mips_emit_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
3369 /* Change the source to SFmode. */
3371 src
= adjust_address (src
, SFmode
, 0);
3372 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
3373 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
3375 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
3376 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + FP_INC
);
3378 emit_move_insn (copy_rtx (fp1
), src
);
3379 emit_move_insn (copy_rtx (fp2
), CONST0_RTX (SFmode
));
3380 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
3383 /* Emit code to change the current function's return address to
3384 ADDRESS. SCRATCH is available as a scratch register, if needed.
3385 ADDRESS and SCRATCH are both word-mode GPRs. */
3388 mips_set_return_address (rtx address
, rtx scratch
)
3392 compute_frame_size (get_frame_size ());
3393 gcc_assert ((cfun
->machine
->frame
.mask
>> 31) & 1);
3394 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
3395 cfun
->machine
->frame
.gp_sp_offset
);
3397 emit_move_insn (gen_rtx_MEM (GET_MODE (address
), slot_address
), address
);
3400 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3401 Assume that the areas do not overlap. */
3404 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
3406 HOST_WIDE_INT offset
, delta
;
3407 unsigned HOST_WIDE_INT bits
;
3409 enum machine_mode mode
;
3412 /* Work out how many bits to move at a time. If both operands have
3413 half-word alignment, it is usually better to move in half words.
3414 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3415 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3416 Otherwise move word-sized chunks. */
3417 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
3418 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
3419 bits
= BITS_PER_WORD
/ 2;
3421 bits
= BITS_PER_WORD
;
3423 mode
= mode_for_size (bits
, MODE_INT
, 0);
3424 delta
= bits
/ BITS_PER_UNIT
;
3426 /* Allocate a buffer for the temporary registers. */
3427 regs
= alloca (sizeof (rtx
) * length
/ delta
);
3429 /* Load as many BITS-sized chunks as possible. Use a normal load if
3430 the source has enough alignment, otherwise use left/right pairs. */
3431 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3433 regs
[i
] = gen_reg_rtx (mode
);
3434 if (MEM_ALIGN (src
) >= bits
)
3435 emit_move_insn (regs
[i
], adjust_address (src
, mode
, offset
));
3438 rtx part
= adjust_address (src
, BLKmode
, offset
);
3439 if (!mips_expand_unaligned_load (regs
[i
], part
, bits
, 0))
3444 /* Copy the chunks to the destination. */
3445 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3446 if (MEM_ALIGN (dest
) >= bits
)
3447 emit_move_insn (adjust_address (dest
, mode
, offset
), regs
[i
]);
3450 rtx part
= adjust_address (dest
, BLKmode
, offset
);
3451 if (!mips_expand_unaligned_store (part
, regs
[i
], bits
, 0))
3455 /* Mop up any left-over bytes. */
3456 if (offset
< length
)
3458 src
= adjust_address (src
, BLKmode
, offset
);
3459 dest
= adjust_address (dest
, BLKmode
, offset
);
3460 move_by_pieces (dest
, src
, length
- offset
,
3461 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
3465 #define MAX_MOVE_REGS 4
3466 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3469 /* Helper function for doing a loop-based block operation on memory
3470 reference MEM. Each iteration of the loop will operate on LENGTH
3473 Create a new base register for use within the loop and point it to
3474 the start of MEM. Create a new memory reference that uses this
3475 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3478 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
3479 rtx
*loop_reg
, rtx
*loop_mem
)
3481 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
3483 /* Although the new mem does not refer to a known location,
3484 it does keep up to LENGTH bytes of alignment. */
3485 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
3486 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
3490 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3491 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3492 memory regions do not overlap. */
3495 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
)
3497 rtx label
, src_reg
, dest_reg
, final_src
;
3498 HOST_WIDE_INT leftover
;
3500 leftover
= length
% MAX_MOVE_BYTES
;
3503 /* Create registers and memory references for use within the loop. */
3504 mips_adjust_block_mem (src
, MAX_MOVE_BYTES
, &src_reg
, &src
);
3505 mips_adjust_block_mem (dest
, MAX_MOVE_BYTES
, &dest_reg
, &dest
);
3507 /* Calculate the value that SRC_REG should have after the last iteration
3509 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
3512 /* Emit the start of the loop. */
3513 label
= gen_label_rtx ();
3516 /* Emit the loop body. */
3517 mips_block_move_straight (dest
, src
, MAX_MOVE_BYTES
);
3519 /* Move on to the next block. */
3520 emit_move_insn (src_reg
, plus_constant (src_reg
, MAX_MOVE_BYTES
));
3521 emit_move_insn (dest_reg
, plus_constant (dest_reg
, MAX_MOVE_BYTES
));
3523 /* Emit the loop condition. */
3524 if (Pmode
== DImode
)
3525 emit_insn (gen_cmpdi (src_reg
, final_src
));
3527 emit_insn (gen_cmpsi (src_reg
, final_src
));
3528 emit_jump_insn (gen_bne (label
));
3530 /* Mop up any left-over bytes. */
3532 mips_block_move_straight (dest
, src
, leftover
);
3535 /* Expand a movmemsi instruction. */
3538 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
3540 if (GET_CODE (length
) == CONST_INT
)
3542 if (INTVAL (length
) <= 2 * MAX_MOVE_BYTES
)
3544 mips_block_move_straight (dest
, src
, INTVAL (length
));
3549 mips_block_move_loop (dest
, src
, INTVAL (length
));
3556 /* Argument support functions. */
3558 /* Initialize CUMULATIVE_ARGS for a function. */
3561 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
3562 rtx libname ATTRIBUTE_UNUSED
)
3564 static CUMULATIVE_ARGS zero_cum
;
3565 tree param
, next_param
;
3568 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
3570 /* Determine if this function has variable arguments. This is
3571 indicated by the last argument being 'void_type_mode' if there
3572 are no variable arguments. The standard MIPS calling sequence
3573 passes all arguments in the general purpose registers in this case. */
3575 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
3576 param
!= 0; param
= next_param
)
3578 next_param
= TREE_CHAIN (param
);
3579 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
3580 cum
->gp_reg_found
= 1;
3585 /* Fill INFO with information about a single argument. CUM is the
3586 cumulative state for earlier arguments. MODE is the mode of this
3587 argument and TYPE is its type (if known). NAMED is true if this
3588 is a named (fixed) argument rather than a variable one. */
3591 mips_arg_info (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3592 tree type
, int named
, struct mips_arg_info
*info
)
3594 bool doubleword_aligned_p
;
3595 unsigned int num_bytes
, num_words
, max_regs
;
3597 /* Work out the size of the argument. */
3598 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
3599 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3601 /* Decide whether it should go in a floating-point register, assuming
3602 one is free. Later code checks for availability.
3604 The checks against UNITS_PER_FPVALUE handle the soft-float and
3605 single-float cases. */
3609 /* The EABI conventions have traditionally been defined in terms
3610 of TYPE_MODE, regardless of the actual type. */
3611 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3612 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
3613 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
3618 /* Only leading floating-point scalars are passed in
3619 floating-point registers. We also handle vector floats the same
3620 say, which is OK because they are not covered by the standard ABI. */
3621 info
->fpr_p
= (!cum
->gp_reg_found
3622 && cum
->arg_number
< 2
3623 && (type
== 0 || SCALAR_FLOAT_TYPE_P (type
)
3624 || VECTOR_FLOAT_TYPE_P (type
))
3625 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3626 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
3627 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
3632 /* Scalar and complex floating-point types are passed in
3633 floating-point registers. */
3634 info
->fpr_p
= (named
3635 && (type
== 0 || FLOAT_TYPE_P (type
))
3636 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3637 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
3638 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
3639 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
3641 /* ??? According to the ABI documentation, the real and imaginary
3642 parts of complex floats should be passed in individual registers.
3643 The real and imaginary parts of stack arguments are supposed
3644 to be contiguous and there should be an extra word of padding
3647 This has two problems. First, it makes it impossible to use a
3648 single "void *" va_list type, since register and stack arguments
3649 are passed differently. (At the time of writing, MIPSpro cannot
3650 handle complex float varargs correctly.) Second, it's unclear
3651 what should happen when there is only one register free.
3653 For now, we assume that named complex floats should go into FPRs
3654 if there are two FPRs free, otherwise they should be passed in the
3655 same way as a struct containing two floats. */
3657 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
3658 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
3660 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
3661 info
->fpr_p
= false;
3671 /* See whether the argument has doubleword alignment. */
3672 doubleword_aligned_p
= FUNCTION_ARG_BOUNDARY (mode
, type
) > BITS_PER_WORD
;
3674 /* Set REG_OFFSET to the register count we're interested in.
3675 The EABI allocates the floating-point registers separately,
3676 but the other ABIs allocate them like integer registers. */
3677 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
3681 /* Advance to an even register if the argument is doubleword-aligned. */
3682 if (doubleword_aligned_p
)
3683 info
->reg_offset
+= info
->reg_offset
& 1;
3685 /* Work out the offset of a stack argument. */
3686 info
->stack_offset
= cum
->stack_words
;
3687 if (doubleword_aligned_p
)
3688 info
->stack_offset
+= info
->stack_offset
& 1;
3690 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
3692 /* Partition the argument between registers and stack. */
3693 info
->reg_words
= MIN (num_words
, max_regs
);
3694 info
->stack_words
= num_words
- info
->reg_words
;
3698 /* Implement FUNCTION_ARG_ADVANCE. */
3701 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3702 tree type
, int named
)
3704 struct mips_arg_info info
;
3706 mips_arg_info (cum
, mode
, type
, named
, &info
);
3709 cum
->gp_reg_found
= true;
3711 /* See the comment above the cumulative args structure in mips.h
3712 for an explanation of what this code does. It assumes the O32
3713 ABI, which passes at most 2 arguments in float registers. */
3714 if (cum
->arg_number
< 2 && info
.fpr_p
)
3715 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << ((cum
->arg_number
- 1) * 2);
3717 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
3718 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
3719 else if (info
.reg_words
> 0)
3720 cum
->num_fprs
+= FP_INC
;
3722 if (info
.stack_words
> 0)
3723 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
3728 /* Implement FUNCTION_ARG. */
3731 function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3732 tree type
, int named
)
3734 struct mips_arg_info info
;
3736 /* We will be called with a mode of VOIDmode after the last argument
3737 has been seen. Whatever we return will be passed to the call
3738 insn. If we need a mips16 fp_code, return a REG with the code
3739 stored as the mode. */
3740 if (mode
== VOIDmode
)
3742 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
3743 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
3749 mips_arg_info (cum
, mode
, type
, named
, &info
);
3751 /* Return straight away if the whole argument is passed on the stack. */
3752 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
3756 && TREE_CODE (type
) == RECORD_TYPE
3758 && TYPE_SIZE_UNIT (type
)
3759 && host_integerp (TYPE_SIZE_UNIT (type
), 1)
3762 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3763 structure contains a double in its entirety, then that 64 bit
3764 chunk is passed in a floating point register. */
3767 /* First check to see if there is any such field. */
3768 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3769 if (TREE_CODE (field
) == FIELD_DECL
3770 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3771 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3772 && host_integerp (bit_position (field
), 0)
3773 && int_bit_position (field
) % BITS_PER_WORD
== 0)
3778 /* Now handle the special case by returning a PARALLEL
3779 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3780 chunks are passed in registers. */
3782 HOST_WIDE_INT bitpos
;
3785 /* assign_parms checks the mode of ENTRY_PARM, so we must
3786 use the actual mode here. */
3787 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
3790 field
= TYPE_FIELDS (type
);
3791 for (i
= 0; i
< info
.reg_words
; i
++)
3795 for (; field
; field
= TREE_CHAIN (field
))
3796 if (TREE_CODE (field
) == FIELD_DECL
3797 && int_bit_position (field
) >= bitpos
)
3801 && int_bit_position (field
) == bitpos
3802 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3803 && !TARGET_SOFT_FLOAT
3804 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3805 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
3807 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
3810 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
3811 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3813 bitpos
+= BITS_PER_WORD
;
3819 /* Handle the n32/n64 conventions for passing complex floating-point
3820 arguments in FPR pairs. The real part goes in the lower register
3821 and the imaginary part goes in the upper register. */
3824 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3827 enum machine_mode inner
;
3830 inner
= GET_MODE_INNER (mode
);
3831 reg
= FP_ARG_FIRST
+ info
.reg_offset
;
3832 real
= gen_rtx_EXPR_LIST (VOIDmode
,
3833 gen_rtx_REG (inner
, reg
),
3835 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
3836 gen_rtx_REG (inner
, reg
+ info
.reg_words
/ 2),
3837 GEN_INT (GET_MODE_SIZE (inner
)));
3838 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
3842 return gen_rtx_REG (mode
, GP_ARG_FIRST
+ info
.reg_offset
);
3843 else if (info
.reg_offset
== 1)
3844 /* This code handles the special o32 case in which the second word
3845 of the argument structure is passed in floating-point registers. */
3846 return gen_rtx_REG (mode
, FP_ARG_FIRST
+ FP_INC
);
3848 return gen_rtx_REG (mode
, FP_ARG_FIRST
+ info
.reg_offset
);
3852 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3855 mips_arg_partial_bytes (CUMULATIVE_ARGS
*cum
,
3856 enum machine_mode mode
, tree type
, bool named
)
3858 struct mips_arg_info info
;
3860 mips_arg_info (cum
, mode
, type
, named
, &info
);
3861 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
3865 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3866 PARM_BOUNDARY bits of alignment, but will be given anything up
3867 to STACK_BOUNDARY bits if the type requires it. */
3870 function_arg_boundary (enum machine_mode mode
, tree type
)
3872 unsigned int alignment
;
3874 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
3875 if (alignment
< PARM_BOUNDARY
)
3876 alignment
= PARM_BOUNDARY
;
3877 if (alignment
> STACK_BOUNDARY
)
3878 alignment
= STACK_BOUNDARY
;
3882 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3883 upward rather than downward. In other words, return true if the
3884 first byte of the stack slot has useful data, false if the last
3888 mips_pad_arg_upward (enum machine_mode mode
, tree type
)
3890 /* On little-endian targets, the first byte of every stack argument
3891 is passed in the first byte of the stack slot. */
3892 if (!BYTES_BIG_ENDIAN
)
3895 /* Otherwise, integral types are padded downward: the last byte of a
3896 stack argument is passed in the last byte of the stack slot. */
3898 ? INTEGRAL_TYPE_P (type
) || POINTER_TYPE_P (type
)
3899 : GET_MODE_CLASS (mode
) == MODE_INT
)
3902 /* Big-endian o64 pads floating-point arguments downward. */
3903 if (mips_abi
== ABI_O64
)
3904 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3907 /* Other types are padded upward for o32, o64, n32 and n64. */
3908 if (mips_abi
!= ABI_EABI
)
3911 /* Arguments smaller than a stack slot are padded downward. */
3912 if (mode
!= BLKmode
)
3913 return (GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
);
3915 return (int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
));
3919 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3920 if the least significant byte of the register has useful data. Return
3921 the opposite if the most significant byte does. */
3924 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
3926 /* No shifting is required for floating-point arguments. */
3927 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3928 return !BYTES_BIG_ENDIAN
;
3930 /* Otherwise, apply the same padding to register arguments as we do
3931 to stack arguments. */
3932 return mips_pad_arg_upward (mode
, type
);
3936 mips_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3937 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
3940 CUMULATIVE_ARGS local_cum
;
3941 int gp_saved
, fp_saved
;
3943 /* The caller has advanced CUM up to, but not beyond, the last named
3944 argument. Advance a local copy of CUM past the last "real" named
3945 argument, to find out how many registers are left over. */
3948 FUNCTION_ARG_ADVANCE (local_cum
, mode
, type
, 1);
3950 /* Found out how many registers we need to save. */
3951 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
3952 fp_saved
= (EABI_FLOAT_VARARGS_P
3953 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
3962 ptr
= plus_constant (virtual_incoming_args_rtx
,
3963 REG_PARM_STACK_SPACE (cfun
->decl
)
3964 - gp_saved
* UNITS_PER_WORD
);
3965 mem
= gen_rtx_MEM (BLKmode
, ptr
);
3966 set_mem_alias_set (mem
, get_varargs_alias_set ());
3968 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
3973 /* We can't use move_block_from_reg, because it will use
3975 enum machine_mode mode
;
3978 /* Set OFF to the offset from virtual_incoming_args_rtx of
3979 the first float register. The FP save area lies below
3980 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3981 off
= -gp_saved
* UNITS_PER_WORD
;
3982 off
&= ~(UNITS_PER_FPVALUE
- 1);
3983 off
-= fp_saved
* UNITS_PER_FPREG
;
3985 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
3987 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
; i
+= FP_INC
)
3991 ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
3992 mem
= gen_rtx_MEM (mode
, ptr
);
3993 set_mem_alias_set (mem
, get_varargs_alias_set ());
3994 emit_move_insn (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
3995 off
+= UNITS_PER_HWFPVALUE
;
3999 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
4000 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
4001 + fp_saved
* UNITS_PER_FPREG
);
4004 /* Create the va_list data type.
4005 We keep 3 pointers, and two offsets.
4006 Two pointers are to the overflow area, which starts at the CFA.
4007 One of these is constant, for addressing into the GPR save area below it.
4008 The other is advanced up the stack through the overflow region.
4009 The third pointer is to the GPR save area. Since the FPR save area
4010 is just below it, we can address FPR slots off this pointer.
4011 We also keep two one-byte offsets, which are to be subtracted from the
4012 constant pointers to yield addresses in the GPR and FPR save areas.
4013 These are downcounted as float or non-float arguments are used,
4014 and when they get to zero, the argument must be obtained from the
4016 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4017 pointer is enough. It's started at the GPR save area, and is
4019 Note that the GPR save area is not constant size, due to optimization
4020 in the prologue. Hence, we can't use a design with two pointers
4021 and two offsets, although we could have designed this with two pointers
4022 and three offsets. */
4025 mips_build_builtin_va_list (void)
4027 if (EABI_FLOAT_VARARGS_P
)
4029 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
4032 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
4034 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
4036 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
4038 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
4040 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
4041 unsigned_char_type_node
);
4042 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
4043 unsigned_char_type_node
);
4044 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4045 warn on every user file. */
4046 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
4047 array
= build_array_type (unsigned_char_type_node
,
4048 build_index_type (index
));
4049 f_res
= build_decl (FIELD_DECL
, get_identifier ("__reserved"), array
);
4051 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
4052 DECL_FIELD_CONTEXT (f_gtop
) = record
;
4053 DECL_FIELD_CONTEXT (f_ftop
) = record
;
4054 DECL_FIELD_CONTEXT (f_goff
) = record
;
4055 DECL_FIELD_CONTEXT (f_foff
) = record
;
4056 DECL_FIELD_CONTEXT (f_res
) = record
;
4058 TYPE_FIELDS (record
) = f_ovfl
;
4059 TREE_CHAIN (f_ovfl
) = f_gtop
;
4060 TREE_CHAIN (f_gtop
) = f_ftop
;
4061 TREE_CHAIN (f_ftop
) = f_goff
;
4062 TREE_CHAIN (f_goff
) = f_foff
;
4063 TREE_CHAIN (f_foff
) = f_res
;
4065 layout_type (record
);
4068 else if (TARGET_IRIX
&& TARGET_IRIX6
)
4069 /* On IRIX 6, this type is 'char *'. */
4070 return build_pointer_type (char_type_node
);
4072 /* Otherwise, we use 'void *'. */
4073 return ptr_type_node
;
4076 /* Implement va_start. */
4079 mips_va_start (tree valist
, rtx nextarg
)
4081 if (EABI_FLOAT_VARARGS_P
)
4083 const CUMULATIVE_ARGS
*cum
;
4084 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4085 tree ovfl
, gtop
, ftop
, goff
, foff
;
4087 int gpr_save_area_size
;
4088 int fpr_save_area_size
;
4091 cum
= ¤t_function_args_info
;
4093 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
4095 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
4097 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4098 f_gtop
= TREE_CHAIN (f_ovfl
);
4099 f_ftop
= TREE_CHAIN (f_gtop
);
4100 f_goff
= TREE_CHAIN (f_ftop
);
4101 f_foff
= TREE_CHAIN (f_goff
);
4103 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
4105 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
4107 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
4109 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
4111 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
4114 /* Emit code to initialize OVFL, which points to the next varargs
4115 stack argument. CUM->STACK_WORDS gives the number of stack
4116 words used by named arguments. */
4117 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
4118 if (cum
->stack_words
> 0)
4119 t
= build2 (PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
4120 build_int_cst (NULL_TREE
,
4121 cum
->stack_words
* UNITS_PER_WORD
));
4122 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
4123 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4125 /* Emit code to initialize GTOP, the top of the GPR save area. */
4126 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
4127 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
4128 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4130 /* Emit code to initialize FTOP, the top of the FPR save area.
4131 This address is gpr_save_area_bytes below GTOP, rounded
4132 down to the next fp-aligned boundary. */
4133 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
4134 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
4135 fpr_offset
&= ~(UNITS_PER_FPVALUE
- 1);
4137 t
= build2 (PLUS_EXPR
, TREE_TYPE (ftop
), t
,
4138 build_int_cst (NULL_TREE
, -fpr_offset
));
4139 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
4140 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4142 /* Emit code to initialize GOFF, the offset from GTOP of the
4143 next GPR argument. */
4144 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
4145 build_int_cst (NULL_TREE
, gpr_save_area_size
));
4146 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4148 /* Likewise emit code to initialize FOFF, the offset from FTOP
4149 of the next FPR argument. */
4150 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
4151 build_int_cst (NULL_TREE
, fpr_save_area_size
));
4152 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4156 nextarg
= plus_constant (nextarg
, -cfun
->machine
->varargs_size
);
4157 std_expand_builtin_va_start (valist
, nextarg
);
4161 /* Implement va_arg. */
4164 mips_gimplify_va_arg_expr (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
4166 HOST_WIDE_INT size
, rsize
;
4170 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
4173 type
= build_pointer_type (type
);
4175 size
= int_size_in_bytes (type
);
4176 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4178 if (mips_abi
!= ABI_EABI
|| !EABI_FLOAT_VARARGS_P
)
4179 addr
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
4182 /* Not a simple merged stack. */
4184 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4185 tree ovfl
, top
, off
, align
;
4186 HOST_WIDE_INT osize
;
4189 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4190 f_gtop
= TREE_CHAIN (f_ovfl
);
4191 f_ftop
= TREE_CHAIN (f_gtop
);
4192 f_goff
= TREE_CHAIN (f_ftop
);
4193 f_foff
= TREE_CHAIN (f_goff
);
4195 /* We maintain separate pointers and offsets for floating-point
4196 and integer arguments, but we need similar code in both cases.
4199 TOP be the top of the register save area;
4200 OFF be the offset from TOP of the next register;
4201 ADDR_RTX be the address of the argument;
4202 RSIZE be the number of bytes used to store the argument
4203 when it's in the register save area;
4204 OSIZE be the number of bytes used to store it when it's
4205 in the stack overflow area; and
4206 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4208 The code we want is:
4210 1: off &= -rsize; // round down
4213 4: addr_rtx = top - off;
4218 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4219 10: addr_rtx = ovfl + PADDING;
4223 [1] and [9] can sometimes be optimized away. */
4225 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
4228 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
4229 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
4231 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
4233 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
4236 /* When floating-point registers are saved to the stack,
4237 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4238 of the float's precision. */
4239 rsize
= UNITS_PER_HWFPVALUE
;
4241 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4242 (= PARM_BOUNDARY bits). This can be different from RSIZE
4245 (1) On 32-bit targets when TYPE is a structure such as:
4247 struct s { float f; };
4249 Such structures are passed in paired FPRs, so RSIZE
4250 will be 8 bytes. However, the structure only takes
4251 up 4 bytes of memory, so OSIZE will only be 4.
4253 (2) In combinations such as -mgp64 -msingle-float
4254 -fshort-double. Doubles passed in registers
4255 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4256 but those passed on the stack take up
4257 UNITS_PER_WORD bytes. */
4258 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
4262 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
4264 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
4266 if (rsize
> UNITS_PER_WORD
)
4268 /* [1] Emit code for: off &= -rsize. */
4269 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), off
,
4270 build_int_cst (NULL_TREE
, -rsize
));
4271 t
= build2 (MODIFY_EXPR
, TREE_TYPE (off
), off
, t
);
4272 gimplify_and_add (t
, pre_p
);
4277 /* [2] Emit code to branch if off == 0. */
4278 t
= build2 (NE_EXPR
, boolean_type_node
, off
,
4279 build_int_cst (TREE_TYPE (off
), 0));
4280 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
4282 /* [5] Emit code for: off -= rsize. We do this as a form of
4283 post-increment not available to C. Also widen for the
4284 coming pointer arithmetic. */
4285 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
4286 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
4287 t
= fold_convert (sizetype
, t
);
4288 t
= fold_convert (TREE_TYPE (top
), t
);
4290 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4291 the argument has RSIZE - SIZE bytes of leading padding. */
4292 t
= build2 (MINUS_EXPR
, TREE_TYPE (top
), top
, t
);
4293 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
4295 u
= fold_convert (TREE_TYPE (t
), build_int_cst (NULL_TREE
,
4297 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
4299 COND_EXPR_THEN (addr
) = t
;
4301 if (osize
> UNITS_PER_WORD
)
4303 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4304 u
= fold_convert (TREE_TYPE (ovfl
),
4305 build_int_cst (NULL_TREE
, osize
- 1));
4306 t
= build2 (PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
4307 u
= fold_convert (TREE_TYPE (ovfl
),
4308 build_int_cst (NULL_TREE
, -osize
));
4309 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (ovfl
), t
, u
);
4310 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
4315 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4316 post-increment ovfl by osize. On big-endian machines,
4317 the argument has OSIZE - SIZE bytes of leading padding. */
4318 u
= fold_convert (TREE_TYPE (ovfl
),
4319 build_int_cst (NULL_TREE
, osize
));
4320 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
4321 if (BYTES_BIG_ENDIAN
&& osize
> size
)
4323 u
= fold_convert (TREE_TYPE (t
),
4324 build_int_cst (NULL_TREE
, osize
- size
));
4325 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
4328 /* String [9] and [10,11] together. */
4330 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
4331 COND_EXPR_ELSE (addr
) = t
;
4333 addr
= fold_convert (build_pointer_type (type
), addr
);
4334 addr
= build_va_arg_indirect_ref (addr
);
4338 addr
= build_va_arg_indirect_ref (addr
);
4343 /* Return true if it is possible to use left/right accesses for a
4344 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4345 returning true, update *OP, *LEFT and *RIGHT as follows:
4347 *OP is a BLKmode reference to the whole field.
4349 *LEFT is a QImode reference to the first byte if big endian or
4350 the last byte if little endian. This address can be used in the
4351 left-side instructions (lwl, swl, ldl, sdl).
4353 *RIGHT is a QImode reference to the opposite end of the field and
4354 can be used in the patterning right-side instruction. */
4357 mips_get_unaligned_mem (rtx
*op
, unsigned int width
, int bitpos
,
4358 rtx
*left
, rtx
*right
)
4362 /* Check that the operand really is a MEM. Not all the extv and
4363 extzv predicates are checked. */
4367 /* Check that the size is valid. */
4368 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
4371 /* We can only access byte-aligned values. Since we are always passed
4372 a reference to the first byte of the field, it is not necessary to
4373 do anything with BITPOS after this check. */
4374 if (bitpos
% BITS_PER_UNIT
!= 0)
4377 /* Reject aligned bitfields: we want to use a normal load or store
4378 instead of a left/right pair. */
4379 if (MEM_ALIGN (*op
) >= width
)
4382 /* Adjust *OP to refer to the whole field. This also has the effect
4383 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4384 *op
= adjust_address (*op
, BLKmode
, 0);
4385 set_mem_size (*op
, GEN_INT (width
/ BITS_PER_UNIT
));
4387 /* Get references to both ends of the field. We deliberately don't
4388 use the original QImode *OP for FIRST since the new BLKmode one
4389 might have a simpler address. */
4390 first
= adjust_address (*op
, QImode
, 0);
4391 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
4393 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4394 be the upper word and RIGHT the lower word. */
4395 if (TARGET_BIG_ENDIAN
)
4396 *left
= first
, *right
= last
;
4398 *left
= last
, *right
= first
;
4404 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4405 Return true on success. We only handle cases where zero_extract is
4406 equivalent to sign_extract. */
4409 mips_expand_unaligned_load (rtx dest
, rtx src
, unsigned int width
, int bitpos
)
4411 rtx left
, right
, temp
;
4413 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4414 paradoxical word_mode subreg. This is the only case in which
4415 we allow the destination to be larger than the source. */
4416 if (GET_CODE (dest
) == SUBREG
4417 && GET_MODE (dest
) == DImode
4418 && SUBREG_BYTE (dest
) == 0
4419 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
4420 dest
= SUBREG_REG (dest
);
4422 /* After the above adjustment, the destination must be the same
4423 width as the source. */
4424 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
4427 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
4430 temp
= gen_reg_rtx (GET_MODE (dest
));
4431 if (GET_MODE (dest
) == DImode
)
4433 emit_insn (gen_mov_ldl (temp
, src
, left
));
4434 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
4438 emit_insn (gen_mov_lwl (temp
, src
, left
));
4439 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
4445 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4449 mips_expand_unaligned_store (rtx dest
, rtx src
, unsigned int width
, int bitpos
)
4453 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
4456 src
= gen_lowpart (mode_for_size (width
, MODE_INT
, 0), src
);
4458 if (GET_MODE (src
) == DImode
)
4460 emit_insn (gen_mov_sdl (dest
, src
, left
));
4461 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
4465 emit_insn (gen_mov_swl (dest
, src
, left
));
4466 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
4471 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4472 source of an "ext" instruction or the destination of an "ins"
4473 instruction. OP must be a register operand and the following
4474 conditions must hold:
4476 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4477 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4478 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4480 Also reject lengths equal to a word as they are better handled
4481 by the move patterns. */
4484 mips_use_ins_ext_p (rtx op
, rtx size
, rtx position
)
4486 HOST_WIDE_INT len
, pos
;
4488 if (!ISA_HAS_EXT_INS
4489 || !register_operand (op
, VOIDmode
)
4490 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
4493 len
= INTVAL (size
);
4494 pos
= INTVAL (position
);
4496 if (len
<= 0 || len
>= GET_MODE_BITSIZE (GET_MODE (op
))
4497 || pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (op
)))
4503 /* Set up globals to generate code for the ISA or processor
4504 described by INFO. */
4507 mips_set_architecture (const struct mips_cpu_info
*info
)
4511 mips_arch_info
= info
;
4512 mips_arch
= info
->cpu
;
4513 mips_isa
= info
->isa
;
4518 /* Likewise for tuning. */
4521 mips_set_tune (const struct mips_cpu_info
*info
)
4525 mips_tune_info
= info
;
4526 mips_tune
= info
->cpu
;
4530 /* Implement TARGET_HANDLE_OPTION. */
4533 mips_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
4538 if (strcmp (arg
, "32") == 0)
4540 else if (strcmp (arg
, "o64") == 0)
4542 else if (strcmp (arg
, "n32") == 0)
4544 else if (strcmp (arg
, "64") == 0)
4546 else if (strcmp (arg
, "eabi") == 0)
4547 mips_abi
= ABI_EABI
;
4554 return mips_parse_cpu (arg
) != 0;
4557 mips_isa_info
= mips_parse_cpu (ACONCAT (("mips", arg
, NULL
)));
4558 return mips_isa_info
!= 0;
4560 case OPT_mno_flush_func
:
4561 mips_cache_flush_func
= NULL
;
4569 /* Set up the threshold for data to go into the small data area, instead
4570 of the normal data area, and detect any conflicts in the switches. */
4573 override_options (void)
4575 int i
, start
, regno
;
4576 enum machine_mode mode
;
4578 mips_section_threshold
= g_switch_set
? g_switch_value
: MIPS_DEFAULT_GVALUE
;
4580 /* The following code determines the architecture and register size.
4581 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4582 The GAS and GCC code should be kept in sync as much as possible. */
4584 if (mips_arch_string
!= 0)
4585 mips_set_architecture (mips_parse_cpu (mips_arch_string
));
4587 if (mips_isa_info
!= 0)
4589 if (mips_arch_info
== 0)
4590 mips_set_architecture (mips_isa_info
);
4591 else if (mips_arch_info
->isa
!= mips_isa_info
->isa
)
4592 error ("-%s conflicts with the other architecture options, "
4593 "which specify a %s processor",
4594 mips_isa_info
->name
,
4595 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
4598 if (mips_arch_info
== 0)
4600 #ifdef MIPS_CPU_STRING_DEFAULT
4601 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT
));
4603 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
));
4607 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
4608 error ("-march=%s is not compatible with the selected ABI",
4609 mips_arch_info
->name
);
4611 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4612 if (mips_tune_string
!= 0)
4613 mips_set_tune (mips_parse_cpu (mips_tune_string
));
4615 if (mips_tune_info
== 0)
4616 mips_set_tune (mips_arch_info
);
4618 /* Set cost structure for the processor. */
4619 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
4621 if ((target_flags_explicit
& MASK_64BIT
) != 0)
4623 /* The user specified the size of the integer registers. Make sure
4624 it agrees with the ABI and ISA. */
4625 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
4626 error ("-mgp64 used with a 32-bit processor");
4627 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
4628 error ("-mgp32 used with a 64-bit ABI");
4629 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
4630 error ("-mgp64 used with a 32-bit ABI");
4634 /* Infer the integer register size from the ABI and processor.
4635 Restrict ourselves to 32-bit registers if that's all the
4636 processor has, or if the ABI cannot handle 64-bit registers. */
4637 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
4638 target_flags
&= ~MASK_64BIT
;
4640 target_flags
|= MASK_64BIT
;
4643 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
4645 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4646 only one right answer here. */
4647 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
4648 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4649 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
4650 error ("unsupported combination: %s", "-mgp32 -mfp64");
4651 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
4652 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4656 /* -msingle-float selects 32-bit float registers. Otherwise the
4657 float registers should be the same size as the integer ones. */
4658 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
4659 target_flags
|= MASK_FLOAT64
;
4661 target_flags
&= ~MASK_FLOAT64
;
4664 /* End of code shared with GAS. */
4666 if ((target_flags_explicit
& MASK_LONG64
) == 0)
4668 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
4669 target_flags
|= MASK_LONG64
;
4671 target_flags
&= ~MASK_LONG64
;
4674 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4675 && (target_flags_explicit
& MASK_SOFT_FLOAT
) == 0)
4677 /* For some configurations, it is useful to have -march control
4678 the default setting of MASK_SOFT_FLOAT. */
4679 switch ((int) mips_arch
)
4681 case PROCESSOR_R4100
:
4682 case PROCESSOR_R4111
:
4683 case PROCESSOR_R4120
:
4684 case PROCESSOR_R4130
:
4685 target_flags
|= MASK_SOFT_FLOAT
;
4689 target_flags
&= ~MASK_SOFT_FLOAT
;
4695 flag_pcc_struct_return
= 0;
4697 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
4699 /* If neither -mbranch-likely nor -mno-branch-likely was given
4700 on the command line, set MASK_BRANCHLIKELY based on the target
4703 By default, we enable use of Branch Likely instructions on
4704 all architectures which support them with the following
4705 exceptions: when creating MIPS32 or MIPS64 code, and when
4706 tuning for architectures where their use tends to hurt
4709 The MIPS32 and MIPS64 architecture specifications say "Software
4710 is strongly encouraged to avoid use of Branch Likely
4711 instructions, as they will be removed from a future revision
4712 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4713 issue those instructions unless instructed to do so by
4715 if (ISA_HAS_BRANCHLIKELY
4716 && !(ISA_MIPS32
|| ISA_MIPS32R2
|| ISA_MIPS64
)
4717 && !(TUNE_MIPS5500
|| TUNE_SB1
))
4718 target_flags
|= MASK_BRANCHLIKELY
;
4720 target_flags
&= ~MASK_BRANCHLIKELY
;
4722 if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
4723 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4725 /* The effect of -mabicalls isn't defined for the EABI. */
4726 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
4728 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4729 target_flags
&= ~MASK_ABICALLS
;
4732 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4733 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4734 /* ??? -non_shared turns off pic code generation, but this is not
4736 if (TARGET_ABICALLS
)
4739 if (mips_section_threshold
> 0)
4740 warning (0, "-G is incompatible with PIC code which is the default");
4743 /* mips_split_addresses is a half-way house between explicit
4744 relocations and the traditional assembler macros. It can
4745 split absolute 32-bit symbolic constants into a high/lo_sum
4746 pair but uses macros for other sorts of access.
4748 Like explicit relocation support for REL targets, it relies
4749 on GNU extensions in the assembler and the linker.
4751 Although this code should work for -O0, it has traditionally
4752 been treated as an optimization. */
4753 if (!TARGET_MIPS16
&& TARGET_SPLIT_ADDRESSES
4754 && optimize
&& !flag_pic
4755 && !ABI_HAS_64BIT_SYMBOLS
)
4756 mips_split_addresses
= 1;
4758 mips_split_addresses
= 0;
4760 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4761 faster code, but at the expense of more nops. Enable it at -O3 and
4763 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
4764 target_flags
|= MASK_VR4130_ALIGN
;
4766 /* When compiling for the mips16, we cannot use floating point. We
4767 record the original hard float value in mips16_hard_float. */
4770 if (TARGET_SOFT_FLOAT
)
4771 mips16_hard_float
= 0;
4773 mips16_hard_float
= 1;
4774 target_flags
|= MASK_SOFT_FLOAT
;
4776 /* Don't run the scheduler before reload, since it tends to
4777 increase register pressure. */
4778 flag_schedule_insns
= 0;
4780 /* Don't do hot/cold partitioning. The constant layout code expects
4781 the whole function to be in a single section. */
4782 flag_reorder_blocks_and_partition
= 0;
4784 /* Silently disable -mexplicit-relocs since it doesn't apply
4785 to mips16 code. Even so, it would overly pedantic to warn
4786 about "-mips16 -mexplicit-relocs", especially given that
4787 we use a %gprel() operator. */
4788 target_flags
&= ~MASK_EXPLICIT_RELOCS
;
4791 /* When using explicit relocs, we call dbr_schedule from within
4793 if (TARGET_EXPLICIT_RELOCS
)
4795 mips_flag_delayed_branch
= flag_delayed_branch
;
4796 flag_delayed_branch
= 0;
4799 #ifdef MIPS_TFMODE_FORMAT
4800 REAL_MODE_FORMAT (TFmode
) = &MIPS_TFMODE_FORMAT
;
4803 /* Make sure that the user didn't turn off paired single support when
4804 MIPS-3D support is requested. */
4805 if (TARGET_MIPS3D
&& (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
4806 && !TARGET_PAIRED_SINGLE_FLOAT
)
4807 error ("-mips3d requires -mpaired-single");
4809 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4811 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
4813 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4814 and TARGET_HARD_FLOAT are both true. */
4815 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT
))
4816 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4818 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4820 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_MIPS64
)
4821 error ("-mips3d/-mpaired-single must be used with -mips64");
4823 if (TARGET_MIPS16
&& TARGET_DSP
)
4824 error ("-mips16 and -mdsp cannot be used together");
4826 mips_print_operand_punct
['?'] = 1;
4827 mips_print_operand_punct
['#'] = 1;
4828 mips_print_operand_punct
['/'] = 1;
4829 mips_print_operand_punct
['&'] = 1;
4830 mips_print_operand_punct
['!'] = 1;
4831 mips_print_operand_punct
['*'] = 1;
4832 mips_print_operand_punct
['@'] = 1;
4833 mips_print_operand_punct
['.'] = 1;
4834 mips_print_operand_punct
['('] = 1;
4835 mips_print_operand_punct
[')'] = 1;
4836 mips_print_operand_punct
['['] = 1;
4837 mips_print_operand_punct
[']'] = 1;
4838 mips_print_operand_punct
['<'] = 1;
4839 mips_print_operand_punct
['>'] = 1;
4840 mips_print_operand_punct
['{'] = 1;
4841 mips_print_operand_punct
['}'] = 1;
4842 mips_print_operand_punct
['^'] = 1;
4843 mips_print_operand_punct
['$'] = 1;
4844 mips_print_operand_punct
['+'] = 1;
4845 mips_print_operand_punct
['~'] = 1;
4847 mips_char_to_class
['d'] = TARGET_MIPS16
? M16_REGS
: GR_REGS
;
4848 mips_char_to_class
['t'] = T_REG
;
4849 mips_char_to_class
['f'] = (TARGET_HARD_FLOAT
? FP_REGS
: NO_REGS
);
4850 mips_char_to_class
['h'] = HI_REG
;
4851 mips_char_to_class
['l'] = LO_REG
;
4852 mips_char_to_class
['x'] = MD_REGS
;
4853 mips_char_to_class
['b'] = ALL_REGS
;
4854 mips_char_to_class
['c'] = (TARGET_ABICALLS
? PIC_FN_ADDR_REG
:
4855 TARGET_MIPS16
? M16_NA_REGS
:
4857 mips_char_to_class
['e'] = LEA_REGS
;
4858 mips_char_to_class
['j'] = PIC_FN_ADDR_REG
;
4859 mips_char_to_class
['v'] = V1_REG
;
4860 mips_char_to_class
['y'] = GR_REGS
;
4861 mips_char_to_class
['z'] = ST_REGS
;
4862 mips_char_to_class
['B'] = COP0_REGS
;
4863 mips_char_to_class
['C'] = COP2_REGS
;
4864 mips_char_to_class
['D'] = COP3_REGS
;
4865 mips_char_to_class
['A'] = DSP_ACC_REGS
;
4866 mips_char_to_class
['a'] = ACC_REGS
;
4868 /* Set up array to map GCC register number to debug register number.
4869 Ignore the special purpose register numbers. */
4871 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4872 mips_dbx_regno
[i
] = -1;
4874 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
4875 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
4876 mips_dbx_regno
[i
] = i
+ start
;
4878 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
4879 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
4880 mips_dbx_regno
[i
] = i
+ start
;
4882 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
4883 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
4885 /* Set up array giving whether a given register can hold a given mode. */
4887 for (mode
= VOIDmode
;
4888 mode
!= MAX_MACHINE_MODE
;
4889 mode
= (enum machine_mode
) ((int)mode
+ 1))
4891 register int size
= GET_MODE_SIZE (mode
);
4892 register enum mode_class
class = GET_MODE_CLASS (mode
);
4894 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4898 if (mode
== CCV2mode
)
4901 && (regno
- ST_REG_FIRST
) % 2 == 0);
4903 else if (mode
== CCV4mode
)
4906 && (regno
- ST_REG_FIRST
) % 4 == 0);
4908 else if (mode
== CCmode
)
4911 temp
= (regno
== FPSW_REGNUM
);
4913 temp
= (ST_REG_P (regno
) || GP_REG_P (regno
)
4914 || FP_REG_P (regno
));
4917 else if (GP_REG_P (regno
))
4918 temp
= ((regno
& 1) == 0 || size
<= UNITS_PER_WORD
);
4920 else if (FP_REG_P (regno
))
4921 temp
= ((regno
% FP_INC
) == 0)
4922 && (((class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
4923 || class == MODE_VECTOR_FLOAT
)
4924 && size
<= UNITS_PER_FPVALUE
)
4925 /* Allow integer modes that fit into a single
4926 register. We need to put integers into FPRs
4927 when using instructions like cvt and trunc.
4928 We can't allow sizes smaller than a word,
4929 the FPU has no appropriate load/store
4930 instructions for those. */
4931 || (class == MODE_INT
4932 && size
>= MIN_UNITS_PER_WORD
4933 && size
<= UNITS_PER_FPREG
)
4934 /* Allow TFmode for CCmode reloads. */
4935 || (ISA_HAS_8CC
&& mode
== TFmode
));
4937 else if (ACC_REG_P (regno
))
4938 temp
= (INTEGRAL_MODE_P (mode
)
4939 && (size
<= UNITS_PER_WORD
4940 || (ACC_HI_REG_P (regno
)
4941 && size
== 2 * UNITS_PER_WORD
)));
4943 else if (ALL_COP_REG_P (regno
))
4944 temp
= (class == MODE_INT
&& size
<= UNITS_PER_WORD
);
4948 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
4952 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4953 initialized yet, so we can't use that here. */
4954 gpr_mode
= TARGET_64BIT
? DImode
: SImode
;
4956 /* Provide default values for align_* for 64-bit targets. */
4957 if (TARGET_64BIT
&& !TARGET_MIPS16
)
4959 if (align_loops
== 0)
4961 if (align_jumps
== 0)
4963 if (align_functions
== 0)
4964 align_functions
= 8;
4967 /* Function to allocate machine-dependent function status. */
4968 init_machine_status
= &mips_init_machine_status
;
4970 if (ABI_HAS_64BIT_SYMBOLS
)
4972 if (TARGET_EXPLICIT_RELOCS
)
4974 mips_split_p
[SYMBOL_64_HIGH
] = true;
4975 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
4976 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
4978 mips_split_p
[SYMBOL_64_MID
] = true;
4979 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
4980 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
4982 mips_split_p
[SYMBOL_64_LOW
] = true;
4983 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
4984 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
4986 mips_split_p
[SYMBOL_GENERAL
] = true;
4987 mips_lo_relocs
[SYMBOL_GENERAL
] = "%lo(";
4992 if (TARGET_EXPLICIT_RELOCS
|| mips_split_addresses
)
4994 mips_split_p
[SYMBOL_GENERAL
] = true;
4995 mips_hi_relocs
[SYMBOL_GENERAL
] = "%hi(";
4996 mips_lo_relocs
[SYMBOL_GENERAL
] = "%lo(";
5002 /* The high part is provided by a pseudo copy of $gp. */
5003 mips_split_p
[SYMBOL_SMALL_DATA
] = true;
5004 mips_lo_relocs
[SYMBOL_SMALL_DATA
] = "%gprel(";
5007 if (TARGET_EXPLICIT_RELOCS
)
5009 /* Small data constants are kept whole until after reload,
5010 then lowered by mips_rewrite_small_data. */
5011 mips_lo_relocs
[SYMBOL_SMALL_DATA
] = "%gp_rel(";
5013 mips_split_p
[SYMBOL_GOT_LOCAL
] = true;
5016 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
5017 mips_lo_relocs
[SYMBOL_GOT_LOCAL
] = "%got_ofst(";
5021 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
5022 mips_lo_relocs
[SYMBOL_GOT_LOCAL
] = "%lo(";
5027 /* The HIGH and LO_SUM are matched by special .md patterns. */
5028 mips_split_p
[SYMBOL_GOT_GLOBAL
] = true;
5030 mips_split_p
[SYMBOL_GOTOFF_GLOBAL
] = true;
5031 mips_hi_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got_hi(";
5032 mips_lo_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got_lo(";
5034 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
5035 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
5036 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
5041 mips_lo_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got_disp(";
5043 mips_lo_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got(";
5044 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
5050 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
5051 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
5052 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
5055 /* Thread-local relocation operators. */
5056 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
5057 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
5058 mips_split_p
[SYMBOL_DTPREL
] = 1;
5059 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
5060 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
5061 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
5062 mips_split_p
[SYMBOL_TPREL
] = 1;
5063 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
5064 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
5066 /* We don't have a thread pointer access instruction on MIPS16, or
5067 appropriate TLS relocations. */
5069 targetm
.have_tls
= false;
5071 /* Default to working around R4000 errata only if the processor
5072 was selected explicitly. */
5073 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
5074 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4000"))
5075 target_flags
|= MASK_FIX_R4000
;
5077 /* Default to working around R4400 errata only if the processor
5078 was selected explicitly. */
5079 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
5080 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4400"))
5081 target_flags
|= MASK_FIX_R4400
;
5084 /* Implement CONDITIONAL_REGISTER_USAGE. */
5087 mips_conditional_register_usage (void)
5093 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
5094 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5096 if (!TARGET_HARD_FLOAT
)
5100 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
5101 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5102 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
5103 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5105 else if (! ISA_HAS_8CC
)
5109 /* We only have a single condition code register. We
5110 implement this by hiding all the condition code registers,
5111 and generating RTL that refers directly to ST_REG_FIRST. */
5112 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
5113 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5115 /* In mips16 mode, we permit the $t temporary registers to be used
5116 for reload. We prohibit the unused $s registers, since they
5117 are caller saved, and saving them via a mips16 register would
5118 probably waste more time than just reloading the value. */
5121 fixed_regs
[18] = call_used_regs
[18] = 1;
5122 fixed_regs
[19] = call_used_regs
[19] = 1;
5123 fixed_regs
[20] = call_used_regs
[20] = 1;
5124 fixed_regs
[21] = call_used_regs
[21] = 1;
5125 fixed_regs
[22] = call_used_regs
[22] = 1;
5126 fixed_regs
[23] = call_used_regs
[23] = 1;
5127 fixed_regs
[26] = call_used_regs
[26] = 1;
5128 fixed_regs
[27] = call_used_regs
[27] = 1;
5129 fixed_regs
[30] = call_used_regs
[30] = 1;
5131 /* fp20-23 are now caller saved. */
5132 if (mips_abi
== ABI_64
)
5135 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
5136 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
5138 /* Odd registers from fp21 to fp31 are now caller saved. */
5139 if (mips_abi
== ABI_N32
)
5142 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
5143 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
5147 /* Allocate a chunk of memory for per-function machine-dependent data. */
5148 static struct machine_function
*
5149 mips_init_machine_status (void)
5151 return ((struct machine_function
*)
5152 ggc_alloc_cleared (sizeof (struct machine_function
)));
5155 /* On the mips16, we want to allocate $24 (T_REG) before other
5156 registers for instructions for which it is possible. This helps
5157 avoid shuffling registers around in order to set up for an xor,
5158 encouraging the compiler to use a cmp instead. */
5161 mips_order_regs_for_local_alloc (void)
5165 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5166 reg_alloc_order
[i
] = i
;
5170 /* It really doesn't matter where we put register 0, since it is
5171 a fixed register anyhow. */
5172 reg_alloc_order
[0] = 24;
5173 reg_alloc_order
[24] = 0;
5178 /* The MIPS debug format wants all automatic variables and arguments
5179 to be in terms of the virtual frame pointer (stack pointer before
5180 any adjustment in the function), while the MIPS 3.0 linker wants
5181 the frame pointer to be the stack pointer after the initial
5182 adjustment. So, we do the adjustment here. The arg pointer (which
5183 is eliminated) points to the virtual frame pointer, while the frame
5184 pointer (which may be eliminated) points to the stack pointer after
5185 the initial adjustments. */
5188 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
5190 rtx offset2
= const0_rtx
;
5191 rtx reg
= eliminate_constant_term (addr
, &offset2
);
5194 offset
= INTVAL (offset2
);
5196 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
5197 || reg
== hard_frame_pointer_rtx
)
5199 HOST_WIDE_INT frame_size
= (!cfun
->machine
->frame
.initialized
)
5200 ? compute_frame_size (get_frame_size ())
5201 : cfun
->machine
->frame
.total_size
;
5203 /* MIPS16 frame is smaller */
5204 if (frame_pointer_needed
&& TARGET_MIPS16
)
5205 frame_size
-= cfun
->machine
->frame
.args_size
;
5207 offset
= offset
- frame_size
;
5210 /* sdbout_parms does not want this to crash for unrecognized cases. */
5212 else if (reg
!= arg_pointer_rtx
)
5213 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5220 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5222 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5223 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5224 'h' OP is HIGH, prints %hi(X),
5225 'd' output integer constant in decimal,
5226 'z' if the operand is 0, use $0 instead of normal operand.
5227 'D' print second part of double-word register or memory operand.
5228 'L' print low-order register of double-word register operand.
5229 'M' print high-order register of double-word register operand.
5230 'C' print part of opcode for a branch condition.
5231 'F' print part of opcode for a floating-point branch condition.
5232 'N' print part of opcode for a branch condition, inverted.
5233 'W' print part of opcode for a floating-point branch condition, inverted.
5234 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5235 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5236 't' like 'T', but with the EQ/NE cases reversed
5237 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5238 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5239 'R' print the reloc associated with LO_SUM
5240 'q' print DSP accumulator registers
5242 The punctuation characters are:
5244 '(' Turn on .set noreorder
5245 ')' Turn on .set reorder
5246 '[' Turn on .set noat
5248 '<' Turn on .set nomacro
5249 '>' Turn on .set macro
5250 '{' Turn on .set volatile (not GAS)
5251 '}' Turn on .set novolatile (not GAS)
5252 '&' Turn on .set noreorder if filling delay slots
5253 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5254 '!' Turn on .set nomacro if filling delay slots
5255 '#' Print nop if in a .set noreorder section.
5256 '/' Like '#', but does nothing within a delayed branch sequence
5257 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5258 '@' Print the name of the assembler temporary register (at or $1).
5259 '.' Print the name of the register with a hard-wired zero (zero or $0).
5260 '^' Print the name of the pic call-through register (t9 or $25).
5261 '$' Print the name of the stack pointer register (sp or $29).
5262 '+' Print the name of the gp register (usually gp or $28).
5263 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5266 print_operand (FILE *file
, rtx op
, int letter
)
5268 register enum rtx_code code
;
5270 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
5275 if (mips_branch_likely
)
5280 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
5284 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
5288 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
5292 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
5296 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
5300 if (final_sequence
!= 0 && set_noreorder
++ == 0)
5301 fputs (".set\tnoreorder\n\t", file
);
5305 if (final_sequence
!= 0)
5307 if (set_noreorder
++ == 0)
5308 fputs (".set\tnoreorder\n\t", file
);
5310 if (set_nomacro
++ == 0)
5311 fputs (".set\tnomacro\n\t", file
);
5316 if (final_sequence
!= 0 && set_nomacro
++ == 0)
5317 fputs ("\n\t.set\tnomacro", file
);
5321 if (set_noreorder
!= 0)
5322 fputs ("\n\tnop", file
);
5326 /* Print an extra newline so that the delayed insn is separated
5327 from the following ones. This looks neater and is consistent
5328 with non-nop delayed sequences. */
5329 if (set_noreorder
!= 0 && final_sequence
== 0)
5330 fputs ("\n\tnop\n", file
);
5334 if (set_noreorder
++ == 0)
5335 fputs (".set\tnoreorder\n\t", file
);
5339 if (set_noreorder
== 0)
5340 error ("internal error: %%) found without a %%( in assembler pattern");
5342 else if (--set_noreorder
== 0)
5343 fputs ("\n\t.set\treorder", file
);
5348 if (set_noat
++ == 0)
5349 fputs (".set\tnoat\n\t", file
);
5354 error ("internal error: %%] found without a %%[ in assembler pattern");
5355 else if (--set_noat
== 0)
5356 fputs ("\n\t.set\tat", file
);
5361 if (set_nomacro
++ == 0)
5362 fputs (".set\tnomacro\n\t", file
);
5366 if (set_nomacro
== 0)
5367 error ("internal error: %%> found without a %%< in assembler pattern");
5368 else if (--set_nomacro
== 0)
5369 fputs ("\n\t.set\tmacro", file
);
5374 if (set_volatile
++ == 0)
5375 fputs ("#.set\tvolatile\n\t", file
);
5379 if (set_volatile
== 0)
5380 error ("internal error: %%} found without a %%{ in assembler pattern");
5381 else if (--set_volatile
== 0)
5382 fputs ("\n\t#.set\tnovolatile", file
);
5388 if (align_labels_log
> 0)
5389 ASM_OUTPUT_ALIGN (file
, align_labels_log
);
5394 error ("PRINT_OPERAND: unknown punctuation '%c'", letter
);
5403 error ("PRINT_OPERAND null pointer");
5407 code
= GET_CODE (op
);
5412 case EQ
: fputs ("eq", file
); break;
5413 case NE
: fputs ("ne", file
); break;
5414 case GT
: fputs ("gt", file
); break;
5415 case GE
: fputs ("ge", file
); break;
5416 case LT
: fputs ("lt", file
); break;
5417 case LE
: fputs ("le", file
); break;
5418 case GTU
: fputs ("gtu", file
); break;
5419 case GEU
: fputs ("geu", file
); break;
5420 case LTU
: fputs ("ltu", file
); break;
5421 case LEU
: fputs ("leu", file
); break;
5423 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op
);
5426 else if (letter
== 'N')
5429 case EQ
: fputs ("ne", file
); break;
5430 case NE
: fputs ("eq", file
); break;
5431 case GT
: fputs ("le", file
); break;
5432 case GE
: fputs ("lt", file
); break;
5433 case LT
: fputs ("ge", file
); break;
5434 case LE
: fputs ("gt", file
); break;
5435 case GTU
: fputs ("leu", file
); break;
5436 case GEU
: fputs ("ltu", file
); break;
5437 case LTU
: fputs ("geu", file
); break;
5438 case LEU
: fputs ("gtu", file
); break;
5440 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op
);
5443 else if (letter
== 'F')
5446 case EQ
: fputs ("c1f", file
); break;
5447 case NE
: fputs ("c1t", file
); break;
5449 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op
);
5452 else if (letter
== 'W')
5455 case EQ
: fputs ("c1t", file
); break;
5456 case NE
: fputs ("c1f", file
); break;
5458 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op
);
5461 else if (letter
== 'h')
5463 if (GET_CODE (op
) == HIGH
)
5466 print_operand_reloc (file
, op
, mips_hi_relocs
);
5469 else if (letter
== 'R')
5470 print_operand_reloc (file
, op
, mips_lo_relocs
);
5472 else if (letter
== 'Y')
5474 if (GET_CODE (op
) == CONST_INT
5475 && ((unsigned HOST_WIDE_INT
) INTVAL (op
)
5476 < ARRAY_SIZE (mips_fp_conditions
)))
5477 fputs (mips_fp_conditions
[INTVAL (op
)], file
);
5479 output_operand_lossage ("invalid %%Y value");
5482 else if (letter
== 'Z')
5486 print_operand (file
, op
, 0);
5491 else if (letter
== 'q')
5496 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op
);
5498 regnum
= REGNO (op
);
5499 if (MD_REG_P (regnum
))
5500 fprintf (file
, "$ac0");
5501 else if (DSP_ACC_REG_P (regnum
))
5502 fprintf (file
, "$ac%c", reg_names
[regnum
][3]);
5504 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op
);
5507 else if (code
== REG
|| code
== SUBREG
)
5509 register int regnum
;
5512 regnum
= REGNO (op
);
5514 regnum
= true_regnum (op
);
5516 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
5517 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
5521 fprintf (file
, "%s", reg_names
[regnum
]);
5524 else if (code
== MEM
)
5527 output_address (plus_constant (XEXP (op
, 0), 4));
5529 output_address (XEXP (op
, 0));
5532 else if (letter
== 'x' && GET_CODE (op
) == CONST_INT
)
5533 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, 0xffff & INTVAL(op
));
5535 else if (letter
== 'X' && GET_CODE(op
) == CONST_INT
)
5536 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
5538 else if (letter
== 'd' && GET_CODE(op
) == CONST_INT
)
5539 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (INTVAL(op
)));
5541 else if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
5542 fputs (reg_names
[GP_REG_FIRST
], file
);
5544 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
5545 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5547 else if (letter
== 'T' || letter
== 't')
5549 int truth
= (code
== NE
) == (letter
== 'T');
5550 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
5553 else if (CONST_GP_P (op
))
5554 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
5557 output_addr_const (file
, op
);
5561 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5562 RELOCS is the array of relocations to use. */
5565 print_operand_reloc (FILE *file
, rtx op
, const char **relocs
)
5567 enum mips_symbol_type symbol_type
;
5570 HOST_WIDE_INT offset
;
5572 if (!mips_symbolic_constant_p (op
, &symbol_type
) || relocs
[symbol_type
] == 0)
5573 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op
);
5575 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5576 mips_split_const (op
, &base
, &offset
);
5577 if (UNSPEC_ADDRESS_P (base
))
5578 op
= plus_constant (UNSPEC_ADDRESS (base
), offset
);
5580 fputs (relocs
[symbol_type
], file
);
5581 output_addr_const (file
, op
);
5582 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
5587 /* Output address operand X to FILE. */
5590 print_operand_address (FILE *file
, rtx x
)
5592 struct mips_address_info addr
;
5594 if (mips_classify_address (&addr
, x
, word_mode
, true))
5598 print_operand (file
, addr
.offset
, 0);
5599 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
5602 case ADDRESS_LO_SUM
:
5603 print_operand (file
, addr
.offset
, 'R');
5604 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
5607 case ADDRESS_CONST_INT
:
5608 output_addr_const (file
, x
);
5609 fprintf (file
, "(%s)", reg_names
[0]);
5612 case ADDRESS_SYMBOLIC
:
5613 output_addr_const (file
, x
);
5619 /* When using assembler macros, keep track of all of small-data externs
5620 so that mips_file_end can emit the appropriate declarations for them.
5622 In most cases it would be safe (though pointless) to emit .externs
5623 for other symbols too. One exception is when an object is within
5624 the -G limit but declared by the user to be in a section other
5625 than .sbss or .sdata. */
5628 mips_output_external (FILE *file ATTRIBUTE_UNUSED
, tree decl
, const char *name
)
5630 register struct extern_list
*p
;
5632 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
5634 p
= (struct extern_list
*) ggc_alloc (sizeof (struct extern_list
));
5635 p
->next
= extern_head
;
5637 p
->size
= int_size_in_bytes (TREE_TYPE (decl
));
5641 if (TARGET_IRIX
&& mips_abi
== ABI_32
&& TREE_CODE (decl
) == FUNCTION_DECL
)
5643 p
= (struct extern_list
*) ggc_alloc (sizeof (struct extern_list
));
5644 p
->next
= extern_head
;
5655 irix_output_external_libcall (rtx fun
)
5657 register struct extern_list
*p
;
5659 if (mips_abi
== ABI_32
)
5661 p
= (struct extern_list
*) ggc_alloc (sizeof (struct extern_list
));
5662 p
->next
= extern_head
;
5663 p
->name
= XSTR (fun
, 0);
5670 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5671 put out a MIPS ECOFF file and a stab. */
5674 mips_output_filename (FILE *stream
, const char *name
)
5677 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5679 if (write_symbols
== DWARF2_DEBUG
)
5681 else if (mips_output_filename_first_time
)
5683 mips_output_filename_first_time
= 0;
5684 num_source_filenames
+= 1;
5685 current_function_file
= name
;
5686 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
5687 output_quoted_string (stream
, name
);
5688 putc ('\n', stream
);
5691 /* If we are emitting stabs, let dbxout.c handle this (except for
5692 the mips_output_filename_first_time case). */
5693 else if (write_symbols
== DBX_DEBUG
)
5696 else if (name
!= current_function_file
5697 && strcmp (name
, current_function_file
) != 0)
5699 num_source_filenames
+= 1;
5700 current_function_file
= name
;
5701 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
5702 output_quoted_string (stream
, name
);
5703 putc ('\n', stream
);
5707 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5708 that should be written before the opening quote, such as "\t.ascii\t"
5709 for real string data or "\t# " for a comment. */
5712 mips_output_ascii (FILE *stream
, const char *string_param
, size_t len
,
5717 register const unsigned char *string
=
5718 (const unsigned char *)string_param
;
5720 fprintf (stream
, "%s\"", prefix
);
5721 for (i
= 0; i
< len
; i
++)
5723 register int c
= string
[i
];
5727 if (c
== '\\' || c
== '\"')
5729 putc ('\\', stream
);
5737 fprintf (stream
, "\\%03o", c
);
5741 if (cur_pos
> 72 && i
+1 < len
)
5744 fprintf (stream
, "\"\n%s\"", prefix
);
5747 fprintf (stream
, "\"\n");
5750 /* Implement TARGET_ASM_FILE_START. */
5753 mips_file_start (void)
5755 default_file_start ();
5759 /* Generate a special section to describe the ABI switches used to
5760 produce the resultant binary. This used to be done by the assembler
5761 setting bits in the ELF header's flags field, but we have run out of
5762 bits. GDB needs this information in order to be able to correctly
5763 debug these binaries. See the function mips_gdbarch_init() in
5764 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5765 causes unnecessary IRIX 6 ld warnings. */
5766 const char * abi_string
= NULL
;
5770 case ABI_32
: abi_string
= "abi32"; break;
5771 case ABI_N32
: abi_string
= "abiN32"; break;
5772 case ABI_64
: abi_string
= "abi64"; break;
5773 case ABI_O64
: abi_string
= "abiO64"; break;
5774 case ABI_EABI
: abi_string
= TARGET_64BIT
? "eabi64" : "eabi32"; break;
5778 /* Note - we use fprintf directly rather than calling switch_to_section
5779 because in this way we can avoid creating an allocated section. We
5780 do not want this section to take up any space in the running
5782 fprintf (asm_out_file
, "\t.section .mdebug.%s\n", abi_string
);
5784 /* There is no ELF header flag to distinguish long32 forms of the
5785 EABI from long64 forms. Emit a special section to help tools
5787 if (mips_abi
== ABI_EABI
)
5788 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n",
5789 TARGET_LONG64
? 64 : 32);
5791 /* Restore the default section. */
5792 fprintf (asm_out_file
, "\t.previous\n");
5795 /* Generate the pseudo ops that System V.4 wants. */
5796 if (TARGET_ABICALLS
)
5797 /* ??? but do not want this (or want pic0) if -non-shared? */
5798 fprintf (asm_out_file
, "\t.abicalls\n");
5801 fprintf (asm_out_file
, "\t.set\tmips16\n");
5803 if (flag_verbose_asm
)
5804 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5806 mips_section_threshold
, mips_arch_info
->name
, mips_isa
);
5809 #ifdef BSS_SECTION_ASM_OP
5810 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5811 in the use of sbss. */
5814 mips_output_aligned_bss (FILE *stream
, tree decl
, const char *name
,
5815 unsigned HOST_WIDE_INT size
, int align
)
5817 extern tree last_assemble_variable_decl
;
5819 if (mips_in_small_data_p (decl
))
5820 switch_to_section (get_named_section (NULL
, ".sbss", 0));
5822 switch_to_section (bss_section
);
5823 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
5824 last_assemble_variable_decl
= decl
;
5825 ASM_DECLARE_OBJECT_NAME (stream
, name
, decl
);
5826 ASM_OUTPUT_SKIP (stream
, size
!= 0 ? size
: 1);
5830 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5831 .externs for any small-data variables that turned out to be external. */
5834 mips_file_end (void)
5837 struct extern_list
*p
;
5841 fputs ("\n", asm_out_file
);
5843 for (p
= extern_head
; p
!= 0; p
= p
->next
)
5845 name_tree
= get_identifier (p
->name
);
5847 /* Positively ensure only one .extern for any given symbol. */
5848 if (!TREE_ASM_WRITTEN (name_tree
)
5849 && TREE_SYMBOL_REFERENCED (name_tree
))
5851 TREE_ASM_WRITTEN (name_tree
) = 1;
5852 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5853 `.global name .text' directive for every used but
5854 undefined function. If we don't, the linker may perform
5855 an optimization (skipping over the insns that set $gp)
5856 when it is unsafe. */
5857 if (TARGET_IRIX
&& mips_abi
== ABI_32
&& p
->size
== -1)
5859 fputs ("\t.globl ", asm_out_file
);
5860 assemble_name (asm_out_file
, p
->name
);
5861 fputs (" .text\n", asm_out_file
);
5865 fputs ("\t.extern\t", asm_out_file
);
5866 assemble_name (asm_out_file
, p
->name
);
5867 fprintf (asm_out_file
, ", %d\n", p
->size
);
5874 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5875 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5878 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
5879 unsigned HOST_WIDE_INT size
,
5882 /* If the target wants uninitialized const declarations in
5883 .rdata then don't put them in .comm. */
5884 if (TARGET_EMBEDDED_DATA
&& TARGET_UNINIT_CONST_IN_RODATA
5885 && TREE_CODE (decl
) == VAR_DECL
&& TREE_READONLY (decl
)
5886 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
5888 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
5889 targetm
.asm_out
.globalize_label (stream
, name
);
5891 switch_to_section (readonly_data_section
);
5892 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
5893 mips_declare_object (stream
, name
, "",
5894 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
5898 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
5902 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5903 NAME is the name of the object and ALIGN is the required alignment
5904 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5905 alignment argument. */
5908 mips_declare_common_object (FILE *stream
, const char *name
,
5909 const char *init_string
,
5910 unsigned HOST_WIDE_INT size
,
5911 unsigned int align
, bool takes_alignment_p
)
5913 if (!takes_alignment_p
)
5915 size
+= (align
/ BITS_PER_UNIT
) - 1;
5916 size
-= size
% (align
/ BITS_PER_UNIT
);
5917 mips_declare_object (stream
, name
, init_string
,
5918 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
5921 mips_declare_object (stream
, name
, init_string
,
5922 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
5923 size
, align
/ BITS_PER_UNIT
);
5926 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5927 macros, mark the symbol as written so that mips_file_end won't emit an
5928 .extern for it. STREAM is the output file, NAME is the name of the
5929 symbol, INIT_STRING is the string that should be written before the
5930 symbol and FINAL_STRING is the string that should be written after it.
5931 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5934 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
5935 const char *final_string
, ...)
5939 fputs (init_string
, stream
);
5940 assemble_name (stream
, name
);
5941 va_start (ap
, final_string
);
5942 vfprintf (stream
, final_string
, ap
);
5945 if (!TARGET_EXPLICIT_RELOCS
)
5947 tree name_tree
= get_identifier (name
);
5948 TREE_ASM_WRITTEN (name_tree
) = 1;
5952 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5953 extern int size_directive_output
;
5955 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5956 definitions except that it uses mips_declare_object() to emit the label. */
5959 mips_declare_object_name (FILE *stream
, const char *name
,
5960 tree decl ATTRIBUTE_UNUSED
)
5962 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5963 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
5966 size_directive_output
= 0;
5967 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
5971 size_directive_output
= 1;
5972 size
= int_size_in_bytes (TREE_TYPE (decl
));
5973 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
5976 mips_declare_object (stream
, name
, "", ":\n");
5979 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
5982 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
5986 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
5987 if (!flag_inhibit_size_directive
5988 && DECL_SIZE (decl
) != 0
5989 && !at_end
&& top_level
5990 && DECL_INITIAL (decl
) == error_mark_node
5991 && !size_directive_output
)
5995 size_directive_output
= 1;
5996 size
= int_size_in_bytes (TREE_TYPE (decl
));
5997 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
6002 /* Return true if X is a small data address that can be rewritten
6006 mips_rewrite_small_data_p (rtx x
)
6008 enum mips_symbol_type symbol_type
;
6010 return (TARGET_EXPLICIT_RELOCS
6011 && mips_symbolic_constant_p (x
, &symbol_type
)
6012 && symbol_type
== SYMBOL_SMALL_DATA
);
6016 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6019 mips_small_data_pattern_1 (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
6021 if (GET_CODE (*loc
) == LO_SUM
)
6024 return mips_rewrite_small_data_p (*loc
);
6027 /* Return true if OP refers to small data symbols directly, not through
6031 mips_small_data_pattern_p (rtx op
)
6033 return for_each_rtx (&op
, mips_small_data_pattern_1
, 0);
6036 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6039 mips_rewrite_small_data_1 (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
6041 if (mips_rewrite_small_data_p (*loc
))
6042 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
6044 if (GET_CODE (*loc
) == LO_SUM
)
6050 /* If possible, rewrite OP so that it refers to small data using
6051 explicit relocations. */
6054 mips_rewrite_small_data (rtx op
)
6056 op
= copy_insn (op
);
6057 for_each_rtx (&op
, mips_rewrite_small_data_1
, 0);
6061 /* Return true if the current function has an insn that implicitly
6065 mips_function_has_gp_insn (void)
6067 /* Don't bother rechecking if we found one last time. */
6068 if (!cfun
->machine
->has_gp_insn_p
)
6072 push_topmost_sequence ();
6073 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6075 && GET_CODE (PATTERN (insn
)) != USE
6076 && GET_CODE (PATTERN (insn
)) != CLOBBER
6077 && (get_attr_got (insn
) != GOT_UNSET
6078 || small_data_pattern (PATTERN (insn
), VOIDmode
)))
6080 pop_topmost_sequence ();
6082 cfun
->machine
->has_gp_insn_p
= (insn
!= 0);
6084 return cfun
->machine
->has_gp_insn_p
;
6088 /* Return the register that should be used as the global pointer
6089 within this function. Return 0 if the function doesn't need
6090 a global pointer. */
6093 mips_global_pointer (void)
6097 /* $gp is always available in non-abicalls code. */
6098 if (!TARGET_ABICALLS
)
6099 return GLOBAL_POINTER_REGNUM
;
6101 /* We must always provide $gp when it is used implicitly. */
6102 if (!TARGET_EXPLICIT_RELOCS
)
6103 return GLOBAL_POINTER_REGNUM
;
6105 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6107 if (current_function_profile
)
6108 return GLOBAL_POINTER_REGNUM
;
6110 /* If the function has a nonlocal goto, $gp must hold the correct
6111 global pointer for the target function. */
6112 if (current_function_has_nonlocal_goto
)
6113 return GLOBAL_POINTER_REGNUM
;
6115 /* If the gp is never referenced, there's no need to initialize it.
6116 Note that reload can sometimes introduce constant pool references
6117 into a function that otherwise didn't need them. For example,
6118 suppose we have an instruction like:
6120 (set (reg:DF R1) (float:DF (reg:SI R2)))
6122 If R2 turns out to be constant such as 1, the instruction may have a
6123 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6124 using this constant if R2 doesn't get allocated to a register.
6126 In cases like these, reload will have added the constant to the pool
6127 but no instruction will yet refer to it. */
6128 if (!regs_ever_live
[GLOBAL_POINTER_REGNUM
]
6129 && !current_function_uses_const_pool
6130 && !mips_function_has_gp_insn ())
6133 /* We need a global pointer, but perhaps we can use a call-clobbered
6134 register instead of $gp. */
6135 if (TARGET_NEWABI
&& current_function_is_leaf
)
6136 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
6137 if (!regs_ever_live
[regno
]
6138 && call_used_regs
[regno
]
6139 && !fixed_regs
[regno
]
6140 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
6143 return GLOBAL_POINTER_REGNUM
;
6147 /* Return true if the current function must save REGNO. */
6150 mips_save_reg_p (unsigned int regno
)
6152 /* We only need to save $gp for NewABI PIC. */
6153 if (regno
== GLOBAL_POINTER_REGNUM
)
6154 return (TARGET_ABICALLS
&& TARGET_NEWABI
6155 && cfun
->machine
->global_pointer
== regno
);
6157 /* Check call-saved registers. */
6158 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
6161 /* We need to save the old frame pointer before setting up a new one. */
6162 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
6165 /* We need to save the incoming return address if it is ever clobbered
6166 within the function. */
6167 if (regno
== GP_REG_FIRST
+ 31 && regs_ever_live
[regno
])
6174 return_type
= DECL_RESULT (current_function_decl
);
6176 /* $18 is a special case in mips16 code. It may be used to call
6177 a function which returns a floating point value, but it is
6178 marked in call_used_regs. */
6179 if (regno
== GP_REG_FIRST
+ 18 && regs_ever_live
[regno
])
6182 /* $31 is also a special case. It will be used to copy a return
6183 value into the floating point registers if the return value is
6185 if (regno
== GP_REG_FIRST
+ 31
6186 && mips16_hard_float
6187 && !aggregate_value_p (return_type
, current_function_decl
)
6188 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
6189 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
)
6197 /* Return the bytes needed to compute the frame pointer from the current
6198 stack pointer. SIZE is the size (in bytes) of the local variables.
6200 MIPS stack frames look like:
6202 Before call After call
6203 +-----------------------+ +-----------------------+
6206 | caller's temps. | | caller's temps. |
6208 +-----------------------+ +-----------------------+
6210 | arguments on stack. | | arguments on stack. |
6212 +-----------------------+ +-----------------------+
6213 | 4 words to save | | 4 words to save |
6214 | arguments passed | | arguments passed |
6215 | in registers, even | | in registers, even |
6216 SP->| if not passed. | VFP->| if not passed. |
6217 +-----------------------+ +-----------------------+
6219 | fp register save |
6221 +-----------------------+
6223 | gp register save |
6225 +-----------------------+
6229 +-----------------------+
6231 | alloca allocations |
6233 +-----------------------+
6235 | GP save for V.4 abi |
6237 +-----------------------+
6239 | arguments on stack |
6241 +-----------------------+
6243 | arguments passed |
6244 | in registers, even |
6245 low SP->| if not passed. |
6246 memory +-----------------------+
6251 compute_frame_size (HOST_WIDE_INT size
)
6254 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
6255 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
6256 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
6257 HOST_WIDE_INT cprestore_size
; /* # bytes that the cprestore slot takes up */
6258 HOST_WIDE_INT gp_reg_rounded
; /* # bytes needed to store gp after rounding */
6259 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
6260 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
6261 unsigned int mask
; /* mask of saved gp registers */
6262 unsigned int fmask
; /* mask of saved fp registers */
6264 cfun
->machine
->global_pointer
= mips_global_pointer ();
6270 var_size
= MIPS_STACK_ALIGN (size
);
6271 args_size
= current_function_outgoing_args_size
;
6272 cprestore_size
= MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET
) - args_size
;
6274 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6275 functions. If the function has local variables, we're committed
6276 to allocating it anyway. Otherwise reclaim it here. */
6277 if (var_size
== 0 && current_function_is_leaf
)
6278 cprestore_size
= args_size
= 0;
6280 /* The MIPS 3.0 linker does not like functions that dynamically
6281 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6282 looks like we are trying to create a second frame pointer to the
6283 function, so allocate some stack space to make it happy. */
6285 if (args_size
== 0 && current_function_calls_alloca
)
6286 args_size
= 4 * UNITS_PER_WORD
;
6288 total_size
= var_size
+ args_size
+ cprestore_size
;
6290 /* Calculate space needed for gp registers. */
6291 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
6292 if (mips_save_reg_p (regno
))
6294 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6295 mask
|= 1 << (regno
- GP_REG_FIRST
);
6298 /* We need to restore these for the handler. */
6299 if (current_function_calls_eh_return
)
6304 regno
= EH_RETURN_DATA_REGNO (i
);
6305 if (regno
== INVALID_REGNUM
)
6307 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6308 mask
|= 1 << (regno
- GP_REG_FIRST
);
6312 /* This loop must iterate over the same space as its companion in
6313 save_restore_insns. */
6314 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
6315 regno
>= FP_REG_FIRST
;
6318 if (mips_save_reg_p (regno
))
6320 fp_reg_size
+= FP_INC
* UNITS_PER_FPREG
;
6321 fmask
|= ((1 << FP_INC
) - 1) << (regno
- FP_REG_FIRST
);
6325 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
6326 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
6328 /* Add in the space required for saving incoming register arguments. */
6329 total_size
+= current_function_pretend_args_size
;
6330 total_size
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
6332 /* Save other computed information. */
6333 cfun
->machine
->frame
.total_size
= total_size
;
6334 cfun
->machine
->frame
.var_size
= var_size
;
6335 cfun
->machine
->frame
.args_size
= args_size
;
6336 cfun
->machine
->frame
.cprestore_size
= cprestore_size
;
6337 cfun
->machine
->frame
.gp_reg_size
= gp_reg_size
;
6338 cfun
->machine
->frame
.fp_reg_size
= fp_reg_size
;
6339 cfun
->machine
->frame
.mask
= mask
;
6340 cfun
->machine
->frame
.fmask
= fmask
;
6341 cfun
->machine
->frame
.initialized
= reload_completed
;
6342 cfun
->machine
->frame
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
6343 cfun
->machine
->frame
.num_fp
= fp_reg_size
/ (FP_INC
* UNITS_PER_FPREG
);
6347 HOST_WIDE_INT offset
;
6349 offset
= (args_size
+ cprestore_size
+ var_size
6350 + gp_reg_size
- GET_MODE_SIZE (gpr_mode
));
6351 cfun
->machine
->frame
.gp_sp_offset
= offset
;
6352 cfun
->machine
->frame
.gp_save_offset
= offset
- total_size
;
6356 cfun
->machine
->frame
.gp_sp_offset
= 0;
6357 cfun
->machine
->frame
.gp_save_offset
= 0;
6362 HOST_WIDE_INT offset
;
6364 offset
= (args_size
+ cprestore_size
+ var_size
6365 + gp_reg_rounded
+ fp_reg_size
6366 - FP_INC
* UNITS_PER_FPREG
);
6367 cfun
->machine
->frame
.fp_sp_offset
= offset
;
6368 cfun
->machine
->frame
.fp_save_offset
= offset
- total_size
;
6372 cfun
->machine
->frame
.fp_sp_offset
= 0;
6373 cfun
->machine
->frame
.fp_save_offset
= 0;
6376 /* Ok, we're done. */
6380 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6381 pointer or argument pointer. TO is either the stack pointer or
6382 hard frame pointer. */
6385 mips_initial_elimination_offset (int from
, int to
)
6387 HOST_WIDE_INT offset
;
6389 compute_frame_size (get_frame_size ());
6391 /* Set OFFSET to the offset from the stack pointer. */
6394 case FRAME_POINTER_REGNUM
:
6398 case ARG_POINTER_REGNUM
:
6399 offset
= (cfun
->machine
->frame
.total_size
6400 - current_function_pretend_args_size
);
6407 if (TARGET_MIPS16
&& to
== HARD_FRAME_POINTER_REGNUM
)
6408 offset
-= cfun
->machine
->frame
.args_size
;
6413 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6414 back to a previous frame. */
6416 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
6421 return get_hard_reg_initial_val (Pmode
, GP_REG_FIRST
+ 31);
6424 /* Use FN to save or restore register REGNO. MODE is the register's
6425 mode and OFFSET is the offset of its save slot from the current
6429 mips_save_restore_reg (enum machine_mode mode
, int regno
,
6430 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
6434 mem
= gen_rtx_MEM (mode
, plus_constant (stack_pointer_rtx
, offset
));
6436 fn (gen_rtx_REG (mode
, regno
), mem
);
6440 /* Call FN for each register that is saved by the current function.
6441 SP_OFFSET is the offset of the current stack pointer from the start
6445 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
6447 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6449 enum machine_mode fpr_mode
;
6450 HOST_WIDE_INT offset
;
6453 /* Save registers starting from high to low. The debuggers prefer at least
6454 the return register be stored at func+4, and also it allows us not to
6455 need a nop in the epilog if at least one register is reloaded in
6456 addition to return address. */
6457 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
6458 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
6459 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
6461 mips_save_restore_reg (gpr_mode
, regno
, offset
, fn
);
6462 offset
-= GET_MODE_SIZE (gpr_mode
);
6465 /* This loop must iterate over the same space as its companion in
6466 compute_frame_size. */
6467 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
6468 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
6469 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
6470 regno
>= FP_REG_FIRST
;
6472 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
6474 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
6475 offset
-= GET_MODE_SIZE (fpr_mode
);
6480 /* If we're generating n32 or n64 abicalls, and the current function
6481 does not use $28 as its global pointer, emit a cplocal directive.
6482 Use pic_offset_table_rtx as the argument to the directive. */
6485 mips_output_cplocal (void)
6487 if (!TARGET_EXPLICIT_RELOCS
6488 && cfun
->machine
->global_pointer
> 0
6489 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
6490 output_asm_insn (".cplocal %+", 0);
6493 /* If we're generating n32 or n64 abicalls, emit instructions
6494 to set up the global pointer. */
6497 mips_emit_loadgp (void)
6499 if (TARGET_ABICALLS
&& TARGET_NEWABI
&& cfun
->machine
->global_pointer
> 0)
6501 rtx addr
, offset
, incoming_address
;
6503 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
6504 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
6505 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
6506 emit_insn (gen_loadgp (offset
, incoming_address
));
6507 if (!TARGET_EXPLICIT_RELOCS
)
6508 emit_insn (gen_loadgp_blockage ());
6512 /* Set up the stack and frame (if desired) for the function. */
6515 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
6518 HOST_WIDE_INT tsize
= cfun
->machine
->frame
.total_size
;
6520 #ifdef SDB_DEBUGGING_INFO
6521 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
6522 SDB_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
6525 /* In mips16 mode, we may need to generate a 32 bit to handle
6526 floating point arguments. The linker will arrange for any 32 bit
6527 functions to call this stub, which will then jump to the 16 bit
6529 if (TARGET_MIPS16
&& !TARGET_SOFT_FLOAT
6530 && current_function_args_info
.fp_code
!= 0)
6531 build_mips16_function_stub (file
);
6533 if (!FUNCTION_NAME_ALREADY_DECLARED
)
6535 /* Get the function name the same way that toplev.c does before calling
6536 assemble_start_function. This is needed so that the name used here
6537 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6538 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
6540 if (!flag_inhibit_size_directive
)
6542 fputs ("\t.ent\t", file
);
6543 assemble_name (file
, fnname
);
6547 assemble_name (file
, fnname
);
6548 fputs (":\n", file
);
6551 /* Stop mips_file_end from treating this function as external. */
6552 if (TARGET_IRIX
&& mips_abi
== ABI_32
)
6553 TREE_ASM_WRITTEN (DECL_NAME (cfun
->decl
)) = 1;
6555 if (!flag_inhibit_size_directive
)
6557 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6559 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
6560 "# vars= " HOST_WIDE_INT_PRINT_DEC
", regs= %d/%d"
6561 ", args= " HOST_WIDE_INT_PRINT_DEC
6562 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
6563 (reg_names
[(frame_pointer_needed
)
6564 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
]),
6565 ((frame_pointer_needed
&& TARGET_MIPS16
)
6566 ? tsize
- cfun
->machine
->frame
.args_size
6568 reg_names
[GP_REG_FIRST
+ 31],
6569 cfun
->machine
->frame
.var_size
,
6570 cfun
->machine
->frame
.num_gp
,
6571 cfun
->machine
->frame
.num_fp
,
6572 cfun
->machine
->frame
.args_size
,
6573 cfun
->machine
->frame
.cprestore_size
);
6575 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6576 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
6577 cfun
->machine
->frame
.mask
,
6578 cfun
->machine
->frame
.gp_save_offset
);
6579 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
6580 cfun
->machine
->frame
.fmask
,
6581 cfun
->machine
->frame
.fp_save_offset
);
6584 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6585 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6588 if (TARGET_ABICALLS
&& !TARGET_NEWABI
&& cfun
->machine
->global_pointer
> 0)
6590 /* Handle the initialization of $gp for SVR4 PIC. */
6591 if (!cfun
->machine
->all_noreorder_p
)
6592 output_asm_insn ("%(.cpload\t%^%)", 0);
6594 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6596 else if (cfun
->machine
->all_noreorder_p
)
6597 output_asm_insn ("%(%<", 0);
6599 /* Tell the assembler which register we're using as the global
6600 pointer. This is needed for thunks, since they can use either
6601 explicit relocs or assembler macros. */
6602 mips_output_cplocal ();
6605 /* Make the last instruction frame related and note that it performs
6606 the operation described by FRAME_PATTERN. */
6609 mips_set_frame_expr (rtx frame_pattern
)
6613 insn
= get_last_insn ();
6614 RTX_FRAME_RELATED_P (insn
) = 1;
6615 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6621 /* Return a frame-related rtx that stores REG at MEM.
6622 REG must be a single register. */
6625 mips_frame_set (rtx mem
, rtx reg
)
6629 /* If we're saving the return address register and the dwarf return
6630 address column differs from the hard register number, adjust the
6631 note reg to refer to the former. */
6632 if (REGNO (reg
) == GP_REG_FIRST
+ 31
6633 && DWARF_FRAME_RETURN_COLUMN
!= GP_REG_FIRST
+ 31)
6634 reg
= gen_rtx_REG (GET_MODE (reg
), DWARF_FRAME_RETURN_COLUMN
);
6636 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
6637 RTX_FRAME_RELATED_P (set
) = 1;
6643 /* Save register REG to MEM. Make the instruction frame-related. */
6646 mips_save_reg (rtx reg
, rtx mem
)
6648 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
6652 if (mips_split_64bit_move_p (mem
, reg
))
6653 mips_split_64bit_move (mem
, reg
);
6655 emit_move_insn (mem
, reg
);
6657 x1
= mips_frame_set (mips_subword (mem
, 0), mips_subword (reg
, 0));
6658 x2
= mips_frame_set (mips_subword (mem
, 1), mips_subword (reg
, 1));
6659 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
6664 && REGNO (reg
) != GP_REG_FIRST
+ 31
6665 && !M16_REG_P (REGNO (reg
)))
6667 /* Save a non-mips16 register by moving it through a temporary.
6668 We don't need to do this for $31 since there's a special
6669 instruction for it. */
6670 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg
)), reg
);
6671 emit_move_insn (mem
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
6674 emit_move_insn (mem
, reg
);
6676 mips_set_frame_expr (mips_frame_set (mem
, reg
));
6681 /* Expand the prologue into a bunch of separate insns. */
6684 mips_expand_prologue (void)
6688 if (cfun
->machine
->global_pointer
> 0)
6689 REGNO (pic_offset_table_rtx
) = cfun
->machine
->global_pointer
;
6691 size
= compute_frame_size (get_frame_size ());
6693 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6694 bytes beforehand; this is enough to cover the register save area
6695 without going out of range. */
6696 if ((cfun
->machine
->frame
.mask
| cfun
->machine
->frame
.fmask
) != 0)
6698 HOST_WIDE_INT step1
;
6700 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
6701 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
6703 GEN_INT (-step1
)))) = 1;
6705 mips_for_each_saved_reg (size
, mips_save_reg
);
6708 /* Allocate the rest of the frame. */
6711 if (SMALL_OPERAND (-size
))
6712 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
6714 GEN_INT (-size
)))) = 1;
6717 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
6720 /* There are no instructions to add or subtract registers
6721 from the stack pointer, so use the frame pointer as a
6722 temporary. We should always be using a frame pointer
6723 in this case anyway. */
6724 gcc_assert (frame_pointer_needed
);
6725 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
6726 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
6727 hard_frame_pointer_rtx
,
6728 MIPS_PROLOGUE_TEMP (Pmode
)));
6729 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
6732 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
6734 MIPS_PROLOGUE_TEMP (Pmode
)));
6736 /* Describe the combined effect of the previous instructions. */
6738 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
6739 plus_constant (stack_pointer_rtx
, -size
)));
6743 /* Set up the frame pointer, if we're using one. In mips16 code,
6744 we point the frame pointer ahead of the outgoing argument area.
6745 This should allow more variables & incoming arguments to be
6746 accessed with unextended instructions. */
6747 if (frame_pointer_needed
)
6749 if (TARGET_MIPS16
&& cfun
->machine
->frame
.args_size
!= 0)
6751 rtx offset
= GEN_INT (cfun
->machine
->frame
.args_size
);
6752 if (SMALL_OPERAND (cfun
->machine
->frame
.args_size
))
6754 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
6759 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode
), offset
);
6760 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
6761 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
6762 hard_frame_pointer_rtx
,
6763 MIPS_PROLOGUE_TEMP (Pmode
)));
6765 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
6766 plus_constant (stack_pointer_rtx
,
6767 cfun
->machine
->frame
.args_size
)));
6771 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx
,
6772 stack_pointer_rtx
)) = 1;
6775 /* If generating o32/o64 abicalls, save $gp on the stack. */
6776 if (TARGET_ABICALLS
&& !TARGET_NEWABI
&& !current_function_is_leaf
)
6777 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size
)));
6779 mips_emit_loadgp ();
6781 /* If we are profiling, make sure no instructions are scheduled before
6782 the call to mcount. */
6784 if (current_function_profile
)
6785 emit_insn (gen_blockage ());
6788 /* Do any necessary cleanup after a function to restore stack, frame,
6791 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6794 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
6795 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
6797 /* Reinstate the normal $gp. */
6798 REGNO (pic_offset_table_rtx
) = GLOBAL_POINTER_REGNUM
;
6799 mips_output_cplocal ();
6801 if (cfun
->machine
->all_noreorder_p
)
6803 /* Avoid using %>%) since it adds excess whitespace. */
6804 output_asm_insn (".set\tmacro", 0);
6805 output_asm_insn (".set\treorder", 0);
6806 set_noreorder
= set_nomacro
= 0;
6809 if (!FUNCTION_NAME_ALREADY_DECLARED
&& !flag_inhibit_size_directive
)
6813 /* Get the function name the same way that toplev.c does before calling
6814 assemble_start_function. This is needed so that the name used here
6815 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6816 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
6817 fputs ("\t.end\t", file
);
6818 assemble_name (file
, fnname
);
6823 /* Emit instructions to restore register REG from slot MEM. */
6826 mips_restore_reg (rtx reg
, rtx mem
)
6828 /* There's no mips16 instruction to load $31 directly. Load into
6829 $7 instead and adjust the return insn appropriately. */
6830 if (TARGET_MIPS16
&& REGNO (reg
) == GP_REG_FIRST
+ 31)
6831 reg
= gen_rtx_REG (GET_MODE (reg
), 7);
6833 if (TARGET_MIPS16
&& !M16_REG_P (REGNO (reg
)))
6835 /* Can't restore directly; move through a temporary. */
6836 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg
)), mem
);
6837 emit_move_insn (reg
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
6840 emit_move_insn (reg
, mem
);
6844 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6845 if this epilogue precedes a sibling call, false if it is for a normal
6846 "epilogue" pattern. */
6849 mips_expand_epilogue (int sibcall_p
)
6851 HOST_WIDE_INT step1
, step2
;
6854 if (!sibcall_p
&& mips_can_use_return_insn ())
6856 emit_jump_insn (gen_return ());
6860 /* Split the frame into two. STEP1 is the amount of stack we should
6861 deallocate before restoring the registers. STEP2 is the amount we
6862 should deallocate afterwards.
6864 Start off by assuming that no registers need to be restored. */
6865 step1
= cfun
->machine
->frame
.total_size
;
6868 /* Work out which register holds the frame address. Account for the
6869 frame pointer offset used by mips16 code. */
6870 if (!frame_pointer_needed
)
6871 base
= stack_pointer_rtx
;
6874 base
= hard_frame_pointer_rtx
;
6876 step1
-= cfun
->machine
->frame
.args_size
;
6879 /* If we need to restore registers, deallocate as much stack as
6880 possible in the second step without going out of range. */
6881 if ((cfun
->machine
->frame
.mask
| cfun
->machine
->frame
.fmask
) != 0)
6883 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
6887 /* Set TARGET to BASE + STEP1. */
6893 /* Get an rtx for STEP1 that we can add to BASE. */
6894 adjust
= GEN_INT (step1
);
6895 if (!SMALL_OPERAND (step1
))
6897 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
6898 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
6901 /* Normal mode code can copy the result straight into $sp. */
6903 target
= stack_pointer_rtx
;
6905 emit_insn (gen_add3_insn (target
, base
, adjust
));
6908 /* Copy TARGET into the stack pointer. */
6909 if (target
!= stack_pointer_rtx
)
6910 emit_move_insn (stack_pointer_rtx
, target
);
6912 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6913 implicitly used by all SYMBOL_REFs. We must emit a blockage
6914 insn before restoring it. */
6915 if (TARGET_ABICALLS
&& TARGET_NEWABI
&& !TARGET_EXPLICIT_RELOCS
)
6916 emit_insn (gen_blockage ());
6918 /* Restore the registers. */
6919 mips_for_each_saved_reg (cfun
->machine
->frame
.total_size
- step2
,
6922 /* Deallocate the final bit of the frame. */
6924 emit_insn (gen_add3_insn (stack_pointer_rtx
,
6928 /* Add in the __builtin_eh_return stack adjustment. We need to
6929 use a temporary in mips16 code. */
6930 if (current_function_calls_eh_return
)
6934 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
6935 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
6936 MIPS_EPILOGUE_TEMP (Pmode
),
6937 EH_RETURN_STACKADJ_RTX
));
6938 emit_move_insn (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
6941 emit_insn (gen_add3_insn (stack_pointer_rtx
,
6943 EH_RETURN_STACKADJ_RTX
));
6948 /* The mips16 loads the return address into $7, not $31. */
6949 if (TARGET_MIPS16
&& (cfun
->machine
->frame
.mask
& RA_MASK
) != 0)
6950 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
,
6951 GP_REG_FIRST
+ 7)));
6953 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
,
6954 GP_REG_FIRST
+ 31)));
6958 /* Return nonzero if this function is known to have a null epilogue.
6959 This allows the optimizer to omit jumps to jumps if no stack
6963 mips_can_use_return_insn (void)
6967 if (! reload_completed
)
6970 if (regs_ever_live
[31] || current_function_profile
)
6973 return_type
= DECL_RESULT (current_function_decl
);
6975 /* In mips16 mode, a function which returns a floating point value
6976 needs to arrange to copy the return value into the floating point
6979 && mips16_hard_float
6980 && ! aggregate_value_p (return_type
, current_function_decl
)
6981 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
6982 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
)
6985 if (cfun
->machine
->frame
.initialized
)
6986 return cfun
->machine
->frame
.total_size
== 0;
6988 return compute_frame_size (get_frame_size ()) == 0;
6991 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
6992 in order to avoid duplicating too much logic from elsewhere. */
6995 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
6996 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
6999 rtx
this, temp1
, temp2
, insn
, fnaddr
;
7001 /* Pretend to be a post-reload pass while generating rtl. */
7003 reload_completed
= 1;
7004 reset_block_changes ();
7006 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7007 for TARGET_NEWABI since the latter is a call-saved register. */
7008 if (TARGET_ABICALLS
)
7009 cfun
->machine
->global_pointer
7010 = REGNO (pic_offset_table_rtx
)
7011 = TARGET_NEWABI
? 15 : GLOBAL_POINTER_REGNUM
;
7013 /* Set up the global pointer for n32 or n64 abicalls. */
7014 mips_emit_loadgp ();
7016 /* We need two temporary registers in some cases. */
7017 temp1
= gen_rtx_REG (Pmode
, 2);
7018 temp2
= gen_rtx_REG (Pmode
, 3);
7020 /* Find out which register contains the "this" pointer. */
7021 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
7022 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
7024 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
7026 /* Add DELTA to THIS. */
7029 rtx offset
= GEN_INT (delta
);
7030 if (!SMALL_OPERAND (delta
))
7032 emit_move_insn (temp1
, offset
);
7035 emit_insn (gen_add3_insn (this, this, offset
));
7038 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7039 if (vcall_offset
!= 0)
7043 /* Set TEMP1 to *THIS. */
7044 emit_move_insn (temp1
, gen_rtx_MEM (Pmode
, this));
7046 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7047 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
7049 /* Load the offset and add it to THIS. */
7050 emit_move_insn (temp1
, gen_rtx_MEM (Pmode
, addr
));
7051 emit_insn (gen_add3_insn (this, this, temp1
));
7054 /* Jump to the target function. Use a sibcall if direct jumps are
7055 allowed, otherwise load the address into a register first. */
7056 fnaddr
= XEXP (DECL_RTL (function
), 0);
7057 if (TARGET_MIPS16
|| TARGET_ABICALLS
|| TARGET_LONG_CALLS
)
7059 /* This is messy. gas treats "la $25,foo" as part of a call
7060 sequence and may allow a global "foo" to be lazily bound.
7061 The general move patterns therefore reject this combination.
7063 In this context, lazy binding would actually be OK for o32 and o64,
7064 but it's still wrong for n32 and n64; see mips_load_call_address.
7065 We must therefore load the address via a temporary register if
7066 mips_dangerous_for_la25_p.
7068 If we jump to the temporary register rather than $25, the assembler
7069 can use the move insn to fill the jump's delay slot. */
7070 if (TARGET_ABICALLS
&& !mips_dangerous_for_la25_p (fnaddr
))
7071 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
7072 mips_load_call_address (temp1
, fnaddr
, true);
7074 if (TARGET_ABICALLS
&& REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
7075 emit_move_insn (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
7076 emit_jump_insn (gen_indirect_jump (temp1
));
7080 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
7081 SIBLING_CALL_P (insn
) = 1;
7084 /* Run just enough of rest_of_compilation. This sequence was
7085 "borrowed" from alpha.c. */
7086 insn
= get_insns ();
7087 insn_locators_initialize ();
7088 split_all_insns_noflow ();
7090 mips16_lay_out_constants ();
7091 shorten_branches (insn
);
7092 final_start_function (insn
, file
, 1);
7093 final (insn
, file
, 1);
7094 final_end_function ();
7096 /* Clean up the vars set above. Note that final_end_function resets
7097 the global pointer for us. */
7098 reload_completed
= 0;
7102 /* Returns nonzero if X contains a SYMBOL_REF. */
7105 symbolic_expression_p (rtx x
)
7107 if (GET_CODE (x
) == SYMBOL_REF
)
7110 if (GET_CODE (x
) == CONST
)
7111 return symbolic_expression_p (XEXP (x
, 0));
7114 return symbolic_expression_p (XEXP (x
, 0));
7116 if (ARITHMETIC_P (x
))
7117 return (symbolic_expression_p (XEXP (x
, 0))
7118 || symbolic_expression_p (XEXP (x
, 1)));
7123 /* Choose the section to use for the constant rtx expression X that has
7127 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
7128 unsigned HOST_WIDE_INT align
)
7132 /* In mips16 mode, the constant table always goes in the same section
7133 as the function, so that constants can be loaded using PC relative
7135 return function_section (current_function_decl
);
7137 else if (TARGET_EMBEDDED_DATA
)
7139 /* For embedded applications, always put constants in read-only data,
7140 in order to reduce RAM usage. */
7141 return mergeable_constant_section (mode
, align
, 0);
7145 /* For hosted applications, always put constants in small data if
7146 possible, as this gives the best performance. */
7147 /* ??? Consider using mergeable small data sections. */
7149 if (GET_MODE_SIZE (mode
) <= (unsigned) mips_section_threshold
7150 && mips_section_threshold
> 0)
7151 return get_named_section (NULL
, ".sdata", 0);
7152 else if (flag_pic
&& symbolic_expression_p (x
))
7153 return get_named_section (NULL
, ".data.rel.ro", 3);
7155 return mergeable_constant_section (mode
, align
, 0);
7159 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7161 The complication here is that, with the combination TARGET_ABICALLS
7162 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7163 therefore not be included in the read-only part of a DSO. Handle such
7164 cases by selecting a normal data section instead of a read-only one.
7165 The logic apes that in default_function_rodata_section. */
7168 mips_function_rodata_section (tree decl
)
7170 if (!TARGET_ABICALLS
|| TARGET_GPWORD
)
7171 return default_function_rodata_section (decl
);
7173 if (decl
&& DECL_SECTION_NAME (decl
))
7175 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7176 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
7178 char *rname
= ASTRDUP (name
);
7180 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
7182 else if (flag_function_sections
&& flag_data_sections
7183 && strncmp (name
, ".text.", 6) == 0)
7185 char *rname
= ASTRDUP (name
);
7186 memcpy (rname
+ 1, "data", 4);
7187 return get_section (rname
, SECTION_WRITE
, decl
);
7190 return data_section
;
7193 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7194 access DECL using %gp_rel(...)($gp). */
7197 mips_in_small_data_p (tree decl
)
7201 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
7204 /* We don't yet generate small-data references for -mabicalls. See related
7205 -G handling in override_options. */
7206 if (TARGET_ABICALLS
)
7209 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
7213 /* Reject anything that isn't in a known small-data section. */
7214 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7215 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
7218 /* If a symbol is defined externally, the assembler will use the
7219 usual -G rules when deciding how to implement macros. */
7220 if (TARGET_EXPLICIT_RELOCS
|| !DECL_EXTERNAL (decl
))
7223 else if (TARGET_EMBEDDED_DATA
)
7225 /* Don't put constants into the small data section: we want them
7226 to be in ROM rather than RAM. */
7227 if (TREE_CODE (decl
) != VAR_DECL
)
7230 if (TREE_READONLY (decl
)
7231 && !TREE_SIDE_EFFECTS (decl
)
7232 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
7236 size
= int_size_in_bytes (TREE_TYPE (decl
));
7237 return (size
> 0 && size
<= mips_section_threshold
);
7240 /* See whether VALTYPE is a record whose fields should be returned in
7241 floating-point registers. If so, return the number of fields and
7242 list them in FIELDS (which should have two elements). Return 0
7245 For n32 & n64, a structure with one or two fields is returned in
7246 floating-point registers as long as every field has a floating-point
7250 mips_fpr_return_fields (tree valtype
, tree
*fields
)
7258 if (TREE_CODE (valtype
) != RECORD_TYPE
)
7262 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= TREE_CHAIN (field
))
7264 if (TREE_CODE (field
) != FIELD_DECL
)
7267 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
)
7273 fields
[i
++] = field
;
7279 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7280 a value in the most significant part of $2/$3 if:
7282 - the target is big-endian;
7284 - the value has a structure or union type (we generalize this to
7285 cover aggregates from other languages too); and
7287 - the structure is not returned in floating-point registers. */
7290 mips_return_in_msb (tree valtype
)
7294 return (TARGET_NEWABI
7295 && TARGET_BIG_ENDIAN
7296 && AGGREGATE_TYPE_P (valtype
)
7297 && mips_fpr_return_fields (valtype
, fields
) == 0);
7301 /* Return a composite value in a pair of floating-point registers.
7302 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7303 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7306 For n32 & n64, $f0 always holds the first value and $f2 the second.
7307 Otherwise the values are packed together as closely as possible. */
7310 mips_return_fpr_pair (enum machine_mode mode
,
7311 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
7312 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
7316 inc
= (TARGET_NEWABI
? 2 : FP_INC
);
7317 return gen_rtx_PARALLEL
7320 gen_rtx_EXPR_LIST (VOIDmode
,
7321 gen_rtx_REG (mode1
, FP_RETURN
),
7323 gen_rtx_EXPR_LIST (VOIDmode
,
7324 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
7325 GEN_INT (offset2
))));
7330 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7331 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7332 VALTYPE is null and MODE is the mode of the return value. */
7335 mips_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
7336 enum machine_mode mode
)
7343 mode
= TYPE_MODE (valtype
);
7344 unsignedp
= TYPE_UNSIGNED (valtype
);
7346 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7347 true, we must promote the mode just as PROMOTE_MODE does. */
7348 mode
= promote_mode (valtype
, mode
, &unsignedp
, 1);
7350 /* Handle structures whose fields are returned in $f0/$f2. */
7351 switch (mips_fpr_return_fields (valtype
, fields
))
7354 return gen_rtx_REG (mode
, FP_RETURN
);
7357 return mips_return_fpr_pair (mode
,
7358 TYPE_MODE (TREE_TYPE (fields
[0])),
7359 int_byte_position (fields
[0]),
7360 TYPE_MODE (TREE_TYPE (fields
[1])),
7361 int_byte_position (fields
[1]));
7364 /* If a value is passed in the most significant part of a register, see
7365 whether we have to round the mode up to a whole number of words. */
7366 if (mips_return_in_msb (valtype
))
7368 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
7369 if (size
% UNITS_PER_WORD
!= 0)
7371 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
7372 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
7376 /* For EABI, the class of return register depends entirely on MODE.
7377 For example, "struct { some_type x; }" and "union { some_type x; }"
7378 are returned in the same way as a bare "some_type" would be.
7379 Other ABIs only use FPRs for scalar, complex or vector types. */
7380 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
7381 return gen_rtx_REG (mode
, GP_RETURN
);
7384 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
7385 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
7386 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
)
7387 return gen_rtx_REG (mode
, FP_RETURN
);
7389 /* Handle long doubles for n32 & n64. */
7391 return mips_return_fpr_pair (mode
,
7393 DImode
, GET_MODE_SIZE (mode
) / 2);
7395 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7396 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
* 2)
7397 return mips_return_fpr_pair (mode
,
7398 GET_MODE_INNER (mode
), 0,
7399 GET_MODE_INNER (mode
),
7400 GET_MODE_SIZE (mode
) / 2);
7402 return gen_rtx_REG (mode
, GP_RETURN
);
7405 /* Return nonzero when an argument must be passed by reference. */
7408 mips_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
7409 enum machine_mode mode
, tree type
,
7410 bool named ATTRIBUTE_UNUSED
)
7412 if (mips_abi
== ABI_EABI
)
7416 /* ??? How should SCmode be handled? */
7417 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
7420 size
= int_size_in_bytes (type
);
7421 return size
== -1 || size
> UNITS_PER_WORD
;
7425 /* If we have a variable-sized parameter, we have no choice. */
7426 return targetm
.calls
.must_pass_in_stack (mode
, type
);
7431 mips_callee_copies (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
7432 enum machine_mode mode ATTRIBUTE_UNUSED
,
7433 tree type ATTRIBUTE_UNUSED
, bool named
)
7435 return mips_abi
== ABI_EABI
&& named
;
7438 /* Return true if registers of class CLASS cannot change from mode FROM
7442 mips_cannot_change_mode_class (enum machine_mode from
,
7443 enum machine_mode to
, enum reg_class
class)
7445 if (MIN (GET_MODE_SIZE (from
), GET_MODE_SIZE (to
)) <= UNITS_PER_WORD
7446 && MAX (GET_MODE_SIZE (from
), GET_MODE_SIZE (to
)) > UNITS_PER_WORD
)
7448 if (TARGET_BIG_ENDIAN
)
7450 /* When a multi-word value is stored in paired floating-point
7451 registers, the first register always holds the low word.
7452 We therefore can't allow FPRs to change between single-word
7453 and multi-word modes. */
7454 if (FP_INC
> 1 && reg_classes_intersect_p (FP_REGS
, class))
7459 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7460 in LO and HI, the high word always comes first. We therefore
7461 can't allow values stored in HI to change between single-word
7462 and multi-word modes.
7463 This rule applies to both the original HI/LO pair and the new
7464 DSP accumulators. */
7465 if (reg_classes_intersect_p (ACC_REGS
, class))
7469 /* Loading a 32-bit value into a 64-bit floating-point register
7470 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7471 We can't allow 64-bit float registers to change from SImode to
7475 && GET_MODE_SIZE (to
) >= UNITS_PER_WORD
7476 && reg_classes_intersect_p (FP_REGS
, class))
7481 /* Return true if X should not be moved directly into register $25.
7482 We need this because many versions of GAS will treat "la $25,foo" as
7483 part of a call sequence and so allow a global "foo" to be lazily bound. */
7486 mips_dangerous_for_la25_p (rtx x
)
7488 HOST_WIDE_INT offset
;
7490 if (TARGET_EXPLICIT_RELOCS
)
7493 mips_split_const (x
, &x
, &offset
);
7494 return global_got_operand (x
, VOIDmode
);
7497 /* Implement PREFERRED_RELOAD_CLASS. */
7500 mips_preferred_reload_class (rtx x
, enum reg_class
class)
7502 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, class))
7505 if (TARGET_HARD_FLOAT
7506 && FLOAT_MODE_P (GET_MODE (x
))
7507 && reg_class_subset_p (FP_REGS
, class))
7510 if (reg_class_subset_p (GR_REGS
, class))
7513 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, class))
7519 /* This function returns the register class required for a secondary
7520 register when copying between one of the registers in CLASS, and X,
7521 using MODE. If IN_P is nonzero, the copy is going from X to the
7522 register, otherwise the register is the source. A return value of
7523 NO_REGS means that no secondary register is required. */
7526 mips_secondary_reload_class (enum reg_class
class,
7527 enum machine_mode mode
, rtx x
, int in_p
)
7529 enum reg_class gr_regs
= TARGET_MIPS16
? M16_REGS
: GR_REGS
;
7533 if (REG_P (x
)|| GET_CODE (x
) == SUBREG
)
7534 regno
= true_regnum (x
);
7536 gp_reg_p
= TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
7538 if (mips_dangerous_for_la25_p (x
))
7541 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], 25))
7545 /* Copying from HI or LO to anywhere other than a general register
7546 requires a general register.
7547 This rule applies to both the original HI/LO pair and the new
7548 DSP accumulators. */
7549 if (reg_class_subset_p (class, ACC_REGS
))
7551 if (TARGET_MIPS16
&& in_p
)
7553 /* We can't really copy to HI or LO at all in mips16 mode. */
7556 return gp_reg_p
? NO_REGS
: gr_regs
;
7558 if (ACC_REG_P (regno
))
7560 if (TARGET_MIPS16
&& ! in_p
)
7562 /* We can't really copy to HI or LO at all in mips16 mode. */
7565 return class == gr_regs
? NO_REGS
: gr_regs
;
7568 /* We can only copy a value to a condition code register from a
7569 floating point register, and even then we require a scratch
7570 floating point register. We can only copy a value out of a
7571 condition code register into a general register. */
7572 if (class == ST_REGS
)
7576 return gp_reg_p
? NO_REGS
: gr_regs
;
7578 if (ST_REG_P (regno
))
7582 return class == gr_regs
? NO_REGS
: gr_regs
;
7585 if (class == FP_REGS
)
7589 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7592 else if (CONSTANT_P (x
) && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
7594 /* We can use the l.s and l.d macros to load floating-point
7595 constants. ??? For l.s, we could probably get better
7596 code by returning GR_REGS here. */
7599 else if (gp_reg_p
|| x
== CONST0_RTX (mode
))
7601 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7604 else if (FP_REG_P (regno
))
7606 /* In this case we can use mov.s or mov.d. */
7611 /* Otherwise, we need to reload through an integer register. */
7616 /* In mips16 mode, going between memory and anything but M16_REGS
7617 requires an M16_REG. */
7620 if (class != M16_REGS
&& class != M16_NA_REGS
)
7628 if (class == M16_REGS
|| class == M16_NA_REGS
)
7637 /* Implement CLASS_MAX_NREGS.
7639 Usually all registers are word-sized. The only supported exception
7640 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7641 registers. A word-based calculation is correct even in that case,
7642 since -msingle-float disallows multi-FPR values.
7644 The FP status registers are an exception to this rule. They are always
7645 4 bytes wide as they only hold condition code modes, and CCmode is always
7646 considered to be 4 bytes wide. */
7649 mips_class_max_nregs (enum reg_class
class ATTRIBUTE_UNUSED
,
7650 enum machine_mode mode
)
7652 if (class == ST_REGS
)
7653 return (GET_MODE_SIZE (mode
) + 3) / 4;
7655 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7659 mips_valid_pointer_mode (enum machine_mode mode
)
7661 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
7664 /* Target hook for vector_mode_supported_p. */
7667 mips_vector_mode_supported_p (enum machine_mode mode
)
7672 return TARGET_PAIRED_SINGLE_FLOAT
;
7683 /* If we can access small data directly (using gp-relative relocation
7684 operators) return the small data pointer, otherwise return null.
7686 For each mips16 function which refers to GP relative symbols, we
7687 use a pseudo register, initialized at the start of the function, to
7688 hold the $gp value. */
7691 mips16_gp_pseudo_reg (void)
7693 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
7698 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
7700 /* We want to initialize this to a value which gcc will believe
7703 unspec
= gen_rtx_UNSPEC (VOIDmode
, gen_rtvec (1, const0_rtx
), UNSPEC_GP
);
7704 emit_move_insn (cfun
->machine
->mips16_gp_pseudo_rtx
,
7705 gen_rtx_CONST (Pmode
, unspec
));
7706 insn
= get_insns ();
7709 push_topmost_sequence ();
7710 /* We need to emit the initialization after the FUNCTION_BEG
7711 note, so that it will be integrated. */
7712 for (scan
= get_insns (); scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
7714 && NOTE_LINE_NUMBER (scan
) == NOTE_INSN_FUNCTION_BEG
)
7716 if (scan
== NULL_RTX
)
7717 scan
= get_insns ();
7718 insn
= emit_insn_after (insn
, scan
);
7719 pop_topmost_sequence ();
7722 return cfun
->machine
->mips16_gp_pseudo_rtx
;
7725 /* Write out code to move floating point arguments in or out of
7726 general registers. Output the instructions to FILE. FP_CODE is
7727 the code describing which arguments are present (see the comment at
7728 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7729 we are copying from the floating point registers. */
7732 mips16_fp_args (FILE *file
, int fp_code
, int from_fp_p
)
7738 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7739 gcc_assert (TARGET_OLDABI
);
7745 gparg
= GP_ARG_FIRST
;
7746 fparg
= FP_ARG_FIRST
;
7747 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7751 if ((fparg
& 1) != 0)
7753 fprintf (file
, "\t%s\t%s,%s\n", s
,
7754 reg_names
[gparg
], reg_names
[fparg
]);
7756 else if ((f
& 3) == 2)
7759 fprintf (file
, "\td%s\t%s,%s\n", s
,
7760 reg_names
[gparg
], reg_names
[fparg
]);
7763 if ((fparg
& 1) != 0)
7765 if (TARGET_BIG_ENDIAN
)
7766 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
7767 reg_names
[gparg
], reg_names
[fparg
+ 1], s
,
7768 reg_names
[gparg
+ 1], reg_names
[fparg
]);
7770 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
7771 reg_names
[gparg
], reg_names
[fparg
], s
,
7772 reg_names
[gparg
+ 1], reg_names
[fparg
+ 1]);
7785 /* Build a mips16 function stub. This is used for functions which
7786 take arguments in the floating point registers. It is 32 bit code
7787 that moves the floating point args into the general registers, and
7788 then jumps to the 16 bit code. */
7791 build_mips16_function_stub (FILE *file
)
7794 char *secname
, *stubname
;
7795 tree stubid
, stubdecl
;
7799 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7800 secname
= (char *) alloca (strlen (fnname
) + 20);
7801 sprintf (secname
, ".mips16.fn.%s", fnname
);
7802 stubname
= (char *) alloca (strlen (fnname
) + 20);
7803 sprintf (stubname
, "__fn_stub_%s", fnname
);
7804 stubid
= get_identifier (stubname
);
7805 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
7806 build_function_type (void_type_node
, NULL_TREE
));
7807 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
7809 fprintf (file
, "\t# Stub function for %s (", current_function_name ());
7811 for (f
= (unsigned int) current_function_args_info
.fp_code
; f
!= 0; f
>>= 2)
7813 fprintf (file
, "%s%s",
7814 need_comma
? ", " : "",
7815 (f
& 3) == 1 ? "float" : "double");
7818 fprintf (file
, ")\n");
7820 fprintf (file
, "\t.set\tnomips16\n");
7821 switch_to_section (function_section (stubdecl
));
7822 ASM_OUTPUT_ALIGN (file
, floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
7824 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7825 within a .ent, and we cannot emit another .ent. */
7826 if (!FUNCTION_NAME_ALREADY_DECLARED
)
7828 fputs ("\t.ent\t", file
);
7829 assemble_name (file
, stubname
);
7833 assemble_name (file
, stubname
);
7834 fputs (":\n", file
);
7836 /* We don't want the assembler to insert any nops here. */
7837 fprintf (file
, "\t.set\tnoreorder\n");
7839 mips16_fp_args (file
, current_function_args_info
.fp_code
, 1);
7841 fprintf (asm_out_file
, "\t.set\tnoat\n");
7842 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
7843 assemble_name (file
, fnname
);
7844 fprintf (file
, "\n");
7845 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
7846 fprintf (asm_out_file
, "\t.set\tat\n");
7848 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7849 with one of the mfc1 instructions, because the result is not
7850 available for one instruction, so if the very first instruction
7851 in the function refers to the register, it will see the wrong
7853 fprintf (file
, "\tnop\n");
7855 fprintf (file
, "\t.set\treorder\n");
7857 if (!FUNCTION_NAME_ALREADY_DECLARED
)
7859 fputs ("\t.end\t", file
);
7860 assemble_name (file
, stubname
);
7864 fprintf (file
, "\t.set\tmips16\n");
7866 switch_to_section (function_section (current_function_decl
));
7869 /* We keep a list of functions for which we have already built stubs
7870 in build_mips16_call_stub. */
7874 struct mips16_stub
*next
;
7879 static struct mips16_stub
*mips16_stubs
;
7881 /* Build a call stub for a mips16 call. A stub is needed if we are
7882 passing any floating point values which should go into the floating
7883 point registers. If we are, and the call turns out to be to a 32
7884 bit function, the stub will be used to move the values into the
7885 floating point registers before calling the 32 bit function. The
7886 linker will magically adjust the function call to either the 16 bit
7887 function or the 32 bit stub, depending upon where the function call
7888 is actually defined.
7890 Similarly, we need a stub if the return value might come back in a
7891 floating point register.
7893 RETVAL is the location of the return value, or null if this is
7894 a call rather than a call_value. FN is the address of the
7895 function and ARG_SIZE is the size of the arguments. FP_CODE
7896 is the code built by function_arg. This function returns a nonzero
7897 value if it builds the call instruction itself. */
7900 build_mips16_call_stub (rtx retval
, rtx fn
, rtx arg_size
, int fp_code
)
7904 char *secname
, *stubname
;
7905 struct mips16_stub
*l
;
7906 tree stubid
, stubdecl
;
7910 /* We don't need to do anything if we aren't in mips16 mode, or if
7911 we were invoked with the -msoft-float option. */
7912 if (! TARGET_MIPS16
|| ! mips16_hard_float
)
7915 /* Figure out whether the value might come back in a floating point
7917 fpret
= (retval
!= 0
7918 && GET_MODE_CLASS (GET_MODE (retval
)) == MODE_FLOAT
7919 && GET_MODE_SIZE (GET_MODE (retval
)) <= UNITS_PER_FPVALUE
);
7921 /* We don't need to do anything if there were no floating point
7922 arguments and the value will not be returned in a floating point
7924 if (fp_code
== 0 && ! fpret
)
7927 /* We don't need to do anything if this is a call to a special
7928 mips16 support function. */
7929 if (GET_CODE (fn
) == SYMBOL_REF
7930 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
7933 /* This code will only work for o32 and o64 abis. The other ABI's
7934 require more sophisticated support. */
7935 gcc_assert (TARGET_OLDABI
);
7937 /* We can only handle SFmode and DFmode floating point return
7940 gcc_assert (GET_MODE (retval
) == SFmode
|| GET_MODE (retval
) == DFmode
);
7942 /* If we're calling via a function pointer, then we must always call
7943 via a stub. There are magic stubs provided in libgcc.a for each
7944 of the required cases. Each of them expects the function address
7945 to arrive in register $2. */
7947 if (GET_CODE (fn
) != SYMBOL_REF
)
7953 /* ??? If this code is modified to support other ABI's, we need
7954 to handle PARALLEL return values here. */
7956 sprintf (buf
, "__mips16_call_stub_%s%d",
7958 ? (GET_MODE (retval
) == SFmode
? "sf_" : "df_")
7961 id
= get_identifier (buf
);
7962 stub_fn
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (id
));
7964 emit_move_insn (gen_rtx_REG (Pmode
, 2), fn
);
7966 if (retval
== NULL_RTX
)
7967 insn
= gen_call_internal (stub_fn
, arg_size
);
7969 insn
= gen_call_value_internal (retval
, stub_fn
, arg_size
);
7970 insn
= emit_call_insn (insn
);
7972 /* Put the register usage information on the CALL. */
7973 CALL_INSN_FUNCTION_USAGE (insn
) =
7974 gen_rtx_EXPR_LIST (VOIDmode
,
7975 gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 2)),
7976 CALL_INSN_FUNCTION_USAGE (insn
));
7978 /* If we are handling a floating point return value, we need to
7979 save $18 in the function prologue. Putting a note on the
7980 call will mean that regs_ever_live[$18] will be true if the
7981 call is not eliminated, and we can check that in the prologue
7984 CALL_INSN_FUNCTION_USAGE (insn
) =
7985 gen_rtx_EXPR_LIST (VOIDmode
,
7986 gen_rtx_USE (VOIDmode
,
7987 gen_rtx_REG (word_mode
, 18)),
7988 CALL_INSN_FUNCTION_USAGE (insn
));
7990 /* Return 1 to tell the caller that we've generated the call
7995 /* We know the function we are going to call. If we have already
7996 built a stub, we don't need to do anything further. */
7998 fnname
= XSTR (fn
, 0);
7999 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
8000 if (strcmp (l
->name
, fnname
) == 0)
8005 /* Build a special purpose stub. When the linker sees a
8006 function call in mips16 code, it will check where the target
8007 is defined. If the target is a 32 bit call, the linker will
8008 search for the section defined here. It can tell which
8009 symbol this section is associated with by looking at the
8010 relocation information (the name is unreliable, since this
8011 might be a static function). If such a section is found, the
8012 linker will redirect the call to the start of the magic
8015 If the function does not return a floating point value, the
8016 special stub section is named
8019 If the function does return a floating point value, the stub
8021 .mips16.call.fp.FNNAME
8024 secname
= (char *) alloca (strlen (fnname
) + 40);
8025 sprintf (secname
, ".mips16.call.%s%s",
8028 stubname
= (char *) alloca (strlen (fnname
) + 20);
8029 sprintf (stubname
, "__call_stub_%s%s",
8032 stubid
= get_identifier (stubname
);
8033 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
8034 build_function_type (void_type_node
, NULL_TREE
));
8035 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
8037 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
8039 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
8043 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
8045 fprintf (asm_out_file
, "%s%s",
8046 need_comma
? ", " : "",
8047 (f
& 3) == 1 ? "float" : "double");
8050 fprintf (asm_out_file
, ")\n");
8052 fprintf (asm_out_file
, "\t.set\tnomips16\n");
8053 assemble_start_function (stubdecl
, stubname
);
8055 if (!FUNCTION_NAME_ALREADY_DECLARED
)
8057 fputs ("\t.ent\t", asm_out_file
);
8058 assemble_name (asm_out_file
, stubname
);
8059 fputs ("\n", asm_out_file
);
8061 assemble_name (asm_out_file
, stubname
);
8062 fputs (":\n", asm_out_file
);
8065 /* We build the stub code by hand. That's the only way we can
8066 do it, since we can't generate 32 bit code during a 16 bit
8069 /* We don't want the assembler to insert any nops here. */
8070 fprintf (asm_out_file
, "\t.set\tnoreorder\n");
8072 mips16_fp_args (asm_out_file
, fp_code
, 0);
8076 fprintf (asm_out_file
, "\t.set\tnoat\n");
8077 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
8079 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
8080 fprintf (asm_out_file
, "\t.set\tat\n");
8081 /* Unfortunately, we can't fill the jump delay slot. We
8082 can't fill with one of the mtc1 instructions, because the
8083 result is not available for one instruction, so if the
8084 very first instruction in the function refers to the
8085 register, it will see the wrong value. */
8086 fprintf (asm_out_file
, "\tnop\n");
8090 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
8091 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
8092 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
8093 /* As above, we can't fill the delay slot. */
8094 fprintf (asm_out_file
, "\tnop\n");
8095 if (GET_MODE (retval
) == SFmode
)
8096 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8097 reg_names
[GP_REG_FIRST
+ 2], reg_names
[FP_REG_FIRST
+ 0]);
8100 if (TARGET_BIG_ENDIAN
)
8102 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8103 reg_names
[GP_REG_FIRST
+ 2],
8104 reg_names
[FP_REG_FIRST
+ 1]);
8105 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8106 reg_names
[GP_REG_FIRST
+ 3],
8107 reg_names
[FP_REG_FIRST
+ 0]);
8111 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8112 reg_names
[GP_REG_FIRST
+ 2],
8113 reg_names
[FP_REG_FIRST
+ 0]);
8114 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8115 reg_names
[GP_REG_FIRST
+ 3],
8116 reg_names
[FP_REG_FIRST
+ 1]);
8119 fprintf (asm_out_file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
8120 /* As above, we can't fill the delay slot. */
8121 fprintf (asm_out_file
, "\tnop\n");
8124 fprintf (asm_out_file
, "\t.set\treorder\n");
8126 #ifdef ASM_DECLARE_FUNCTION_SIZE
8127 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
8130 if (!FUNCTION_NAME_ALREADY_DECLARED
)
8132 fputs ("\t.end\t", asm_out_file
);
8133 assemble_name (asm_out_file
, stubname
);
8134 fputs ("\n", asm_out_file
);
8137 fprintf (asm_out_file
, "\t.set\tmips16\n");
8139 /* Record this stub. */
8140 l
= (struct mips16_stub
*) xmalloc (sizeof *l
);
8141 l
->name
= xstrdup (fnname
);
8143 l
->next
= mips16_stubs
;
8147 /* If we expect a floating point return value, but we've built a
8148 stub which does not expect one, then we're in trouble. We can't
8149 use the existing stub, because it won't handle the floating point
8150 value. We can't build a new stub, because the linker won't know
8151 which stub to use for the various calls in this object file.
8152 Fortunately, this case is illegal, since it means that a function
8153 was declared in two different ways in a single compilation. */
8154 if (fpret
&& ! l
->fpret
)
8155 error ("cannot handle inconsistent calls to %qs", fnname
);
8157 /* If we are calling a stub which handles a floating point return
8158 value, we need to arrange to save $18 in the prologue. We do
8159 this by marking the function call as using the register. The
8160 prologue will later see that it is used, and emit code to save
8167 if (retval
== NULL_RTX
)
8168 insn
= gen_call_internal (fn
, arg_size
);
8170 insn
= gen_call_value_internal (retval
, fn
, arg_size
);
8171 insn
= emit_call_insn (insn
);
8173 CALL_INSN_FUNCTION_USAGE (insn
) =
8174 gen_rtx_EXPR_LIST (VOIDmode
,
8175 gen_rtx_USE (VOIDmode
, gen_rtx_REG (word_mode
, 18)),
8176 CALL_INSN_FUNCTION_USAGE (insn
));
8178 /* Return 1 to tell the caller that we've generated the call
8183 /* Return 0 to let the caller generate the call insn. */
8187 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8188 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8190 struct mips16_constant
{
8191 struct mips16_constant
*next
;
8194 enum machine_mode mode
;
8197 /* Information about an incomplete mips16 constant pool. FIRST is the
8198 first constant, HIGHEST_ADDRESS is the highest address that the first
8199 byte of the pool can have, and INSN_ADDRESS is the current instruction
8202 struct mips16_constant_pool
{
8203 struct mips16_constant
*first
;
8204 int highest_address
;
8208 /* Add constant VALUE to POOL and return its label. MODE is the
8209 value's mode (used for CONST_INTs, etc.). */
8212 add_constant (struct mips16_constant_pool
*pool
,
8213 rtx value
, enum machine_mode mode
)
8215 struct mips16_constant
**p
, *c
;
8216 bool first_of_size_p
;
8218 /* See whether the constant is already in the pool. If so, return the
8219 existing label, otherwise leave P pointing to the place where the
8220 constant should be added.
8222 Keep the pool sorted in increasing order of mode size so that we can
8223 reduce the number of alignments needed. */
8224 first_of_size_p
= true;
8225 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
8227 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
8229 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
8231 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
8232 first_of_size_p
= false;
8235 /* In the worst case, the constant needed by the earliest instruction
8236 will end up at the end of the pool. The entire pool must then be
8237 accessible from that instruction.
8239 When adding the first constant, set the pool's highest address to
8240 the address of the first out-of-range byte. Adjust this address
8241 downwards each time a new constant is added. */
8242 if (pool
->first
== 0)
8243 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8244 is the address of the instruction with the lowest two bits clear.
8245 The base PC value for ld has the lowest three bits clear. Assume
8246 the worst case here. */
8247 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
8248 pool
->highest_address
-= GET_MODE_SIZE (mode
);
8249 if (first_of_size_p
)
8250 /* Take into account the worst possible padding due to alignment. */
8251 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
8253 /* Create a new entry. */
8254 c
= (struct mips16_constant
*) xmalloc (sizeof *c
);
8257 c
->label
= gen_label_rtx ();
8264 /* Output constant VALUE after instruction INSN and return the last
8265 instruction emitted. MODE is the mode of the constant. */
8268 dump_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
8270 switch (GET_MODE_CLASS (mode
))
8274 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
8275 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
8279 return emit_insn_after (gen_consttable_float (value
), insn
);
8281 case MODE_VECTOR_FLOAT
:
8282 case MODE_VECTOR_INT
:
8285 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
8286 insn
= dump_constants_1 (GET_MODE_INNER (mode
),
8287 CONST_VECTOR_ELT (value
, i
), insn
);
8297 /* Dump out the constants in CONSTANTS after INSN. */
8300 dump_constants (struct mips16_constant
*constants
, rtx insn
)
8302 struct mips16_constant
*c
, *next
;
8306 for (c
= constants
; c
!= NULL
; c
= next
)
8308 /* If necessary, increase the alignment of PC. */
8309 if (align
< GET_MODE_SIZE (c
->mode
))
8311 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
8312 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
8314 align
= GET_MODE_SIZE (c
->mode
);
8316 insn
= emit_label_after (c
->label
, insn
);
8317 insn
= dump_constants_1 (c
->mode
, c
->value
, insn
);
8323 emit_barrier_after (insn
);
8326 /* Return the length of instruction INSN. */
8329 mips16_insn_length (rtx insn
)
8333 rtx body
= PATTERN (insn
);
8334 if (GET_CODE (body
) == ADDR_VEC
)
8335 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
8336 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
8337 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
8339 return get_attr_length (insn
);
8342 /* Rewrite *X so that constant pool references refer to the constant's
8343 label instead. DATA points to the constant pool structure. */
8346 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
8348 struct mips16_constant_pool
*pool
= data
;
8349 if (GET_CODE (*x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (*x
))
8350 *x
= gen_rtx_LABEL_REF (Pmode
, add_constant (pool
,
8351 get_pool_constant (*x
),
8352 get_pool_mode (*x
)));
8356 /* Build MIPS16 constant pools. */
8359 mips16_lay_out_constants (void)
8361 struct mips16_constant_pool pool
;
8365 memset (&pool
, 0, sizeof (pool
));
8366 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8368 /* Rewrite constant pool references in INSN. */
8370 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &pool
);
8372 pool
.insn_address
+= mips16_insn_length (insn
);
8374 if (pool
.first
!= NULL
)
8376 /* If there are no natural barriers between the first user of
8377 the pool and the highest acceptable address, we'll need to
8378 create a new instruction to jump around the constant pool.
8379 In the worst case, this instruction will be 4 bytes long.
8381 If it's too late to do this transformation after INSN,
8382 do it immediately before INSN. */
8383 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
8387 label
= gen_label_rtx ();
8389 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
8390 JUMP_LABEL (jump
) = label
;
8391 LABEL_NUSES (label
) = 1;
8392 barrier
= emit_barrier_after (jump
);
8394 emit_label_after (label
, barrier
);
8395 pool
.insn_address
+= 4;
8398 /* See whether the constant pool is now out of range of the first
8399 user. If so, output the constants after the previous barrier.
8400 Note that any instructions between BARRIER and INSN (inclusive)
8401 will use negative offsets to refer to the pool. */
8402 if (pool
.insn_address
> pool
.highest_address
)
8404 dump_constants (pool
.first
, barrier
);
8408 else if (BARRIER_P (insn
))
8412 dump_constants (pool
.first
, get_last_insn ());
8415 /* A temporary variable used by for_each_rtx callbacks, etc. */
8416 static rtx mips_sim_insn
;
8418 /* A structure representing the state of the processor pipeline.
8419 Used by the mips_sim_* family of functions. */
8421 /* The maximum number of instructions that can be issued in a cycle.
8422 (Caches mips_issue_rate.) */
8423 unsigned int issue_rate
;
8425 /* The current simulation time. */
8428 /* How many more instructions can be issued in the current cycle. */
8429 unsigned int insns_left
;
8431 /* LAST_SET[X].INSN is the last instruction to set register X.
8432 LAST_SET[X].TIME is the time at which that instruction was issued.
8433 INSN is null if no instruction has yet set register X. */
8437 } last_set
[FIRST_PSEUDO_REGISTER
];
8439 /* The pipeline's current DFA state. */
8443 /* Reset STATE to the initial simulation state. */
8446 mips_sim_reset (struct mips_sim
*state
)
8449 state
->insns_left
= state
->issue_rate
;
8450 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
8451 state_reset (state
->dfa_state
);
8454 /* Initialize STATE before its first use. DFA_STATE points to an
8455 allocated but uninitialized DFA state. */
8458 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
8460 state
->issue_rate
= mips_issue_rate ();
8461 state
->dfa_state
= dfa_state
;
8462 mips_sim_reset (state
);
8465 /* Advance STATE by one clock cycle. */
8468 mips_sim_next_cycle (struct mips_sim
*state
)
8471 state
->insns_left
= state
->issue_rate
;
8472 state_transition (state
->dfa_state
, 0);
8475 /* Advance simulation state STATE until instruction INSN can read
8479 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
8483 for (i
= 0; i
< HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)); i
++)
8484 if (state
->last_set
[REGNO (reg
) + i
].insn
!= 0)
8488 t
= state
->last_set
[REGNO (reg
) + i
].time
;
8489 t
+= insn_latency (state
->last_set
[REGNO (reg
) + i
].insn
, insn
);
8490 while (state
->time
< t
)
8491 mips_sim_next_cycle (state
);
8495 /* A for_each_rtx callback. If *X is a register, advance simulation state
8496 DATA until mips_sim_insn can read the register's value. */
8499 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
8502 mips_sim_wait_reg (data
, mips_sim_insn
, *x
);
8506 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8509 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
8511 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
8514 /* Advance simulation state STATE until all of INSN's register
8515 dependencies are satisfied. */
8518 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
8520 mips_sim_insn
= insn
;
8521 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
8524 /* Advance simulation state STATE until the units required by
8525 instruction INSN are available. */
8528 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
8532 tmp_state
= alloca (state_size ());
8533 while (state
->insns_left
== 0
8534 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
8535 state_transition (tmp_state
, insn
) >= 0))
8536 mips_sim_next_cycle (state
);
8539 /* Advance simulation state STATE until INSN is ready to issue. */
8542 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
8544 mips_sim_wait_regs (state
, insn
);
8545 mips_sim_wait_units (state
, insn
);
8548 /* mips_sim_insn has just set X. Update the LAST_SET array
8549 in simulation state DATA. */
8552 mips_sim_record_set (rtx x
, rtx pat ATTRIBUTE_UNUSED
, void *data
)
8554 struct mips_sim
*state
;
8559 for (i
= 0; i
< HARD_REGNO_NREGS (REGNO (x
), GET_MODE (x
)); i
++)
8561 state
->last_set
[REGNO (x
) + i
].insn
= mips_sim_insn
;
8562 state
->last_set
[REGNO (x
) + i
].time
= state
->time
;
8566 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8567 can issue immediately (i.e., that mips_sim_wait_insn has already
8571 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
8573 state_transition (state
->dfa_state
, insn
);
8574 state
->insns_left
--;
8576 mips_sim_insn
= insn
;
8577 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
8580 /* Simulate issuing a NOP in state STATE. */
8583 mips_sim_issue_nop (struct mips_sim
*state
)
8585 if (state
->insns_left
== 0)
8586 mips_sim_next_cycle (state
);
8587 state
->insns_left
--;
8590 /* Update simulation state STATE so that it's ready to accept the instruction
8591 after INSN. INSN should be part of the main rtl chain, not a member of a
8595 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
8597 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8599 mips_sim_issue_nop (state
);
8601 switch (GET_CODE (SEQ_BEGIN (insn
)))
8605 /* We can't predict the processor state after a call or label. */
8606 mips_sim_reset (state
);
8610 /* The delay slots of branch likely instructions are only executed
8611 when the branch is taken. Therefore, if the caller has simulated
8612 the delay slot instruction, STATE does not really reflect the state
8613 of the pipeline for the instruction after the delay slot. Also,
8614 branch likely instructions tend to incur a penalty when not taken,
8615 so there will probably be an extra delay between the branch and
8616 the instruction after the delay slot. */
8617 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
8618 mips_sim_reset (state
);
8626 /* The VR4130 pipeline issues aligned pairs of instructions together,
8627 but it stalls the second instruction if it depends on the first.
8628 In order to cut down the amount of logic required, this dependence
8629 check is not based on a full instruction decode. Instead, any non-SPECIAL
8630 instruction is assumed to modify the register specified by bits 20-16
8631 (which is usually the "rt" field).
8633 In beq, beql, bne and bnel instructions, the rt field is actually an
8634 input, so we can end up with a false dependence between the branch
8635 and its delay slot. If this situation occurs in instruction INSN,
8636 try to avoid it by swapping rs and rt. */
8639 vr4130_avoid_branch_rt_conflict (rtx insn
)
8643 first
= SEQ_BEGIN (insn
);
8644 second
= SEQ_END (insn
);
8646 && NONJUMP_INSN_P (second
)
8647 && GET_CODE (PATTERN (first
)) == SET
8648 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
8649 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
8651 /* Check for the right kind of condition. */
8652 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
8653 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8654 && REG_P (XEXP (cond
, 0))
8655 && REG_P (XEXP (cond
, 1))
8656 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
8657 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
8659 /* SECOND mentions the rt register but not the rs register. */
8660 rtx tmp
= XEXP (cond
, 0);
8661 XEXP (cond
, 0) = XEXP (cond
, 1);
8662 XEXP (cond
, 1) = tmp
;
8667 /* Implement -mvr4130-align. Go through each basic block and simulate the
8668 processor pipeline. If we find that a pair of instructions could execute
8669 in parallel, and the first of those instruction is not 8-byte aligned,
8670 insert a nop to make it aligned. */
8673 vr4130_align_insns (void)
8675 struct mips_sim state
;
8676 rtx insn
, subinsn
, last
, last2
, next
;
8681 /* LAST is the last instruction before INSN to have a nonzero length.
8682 LAST2 is the last such instruction before LAST. */
8686 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8689 mips_sim_init (&state
, alloca (state_size ()));
8690 for (insn
= get_insns (); insn
!= 0; insn
= next
)
8692 unsigned int length
;
8694 next
= NEXT_INSN (insn
);
8696 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8697 This isn't really related to the alignment pass, but we do it on
8698 the fly to avoid a separate instruction walk. */
8699 vr4130_avoid_branch_rt_conflict (insn
);
8701 if (USEFUL_INSN_P (insn
))
8702 FOR_EACH_SUBINSN (subinsn
, insn
)
8704 mips_sim_wait_insn (&state
, subinsn
);
8706 /* If we want this instruction to issue in parallel with the
8707 previous one, make sure that the previous instruction is
8708 aligned. There are several reasons why this isn't worthwhile
8709 when the second instruction is a call:
8711 - Calls are less likely to be performance critical,
8712 - There's a good chance that the delay slot can execute
8713 in parallel with the call.
8714 - The return address would then be unaligned.
8716 In general, if we're going to insert a nop between instructions
8717 X and Y, it's better to insert it immediately after X. That
8718 way, if the nop makes Y aligned, it will also align any labels
8720 if (state
.insns_left
!= state
.issue_rate
8721 && !CALL_P (subinsn
))
8723 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
8725 /* SUBINSN is the first instruction in INSN and INSN is
8726 aligned. We want to align the previous instruction
8727 instead, so insert a nop between LAST2 and LAST.
8729 Note that LAST could be either a single instruction
8730 or a branch with a delay slot. In the latter case,
8731 LAST, like INSN, is already aligned, but the delay
8732 slot must have some extra delay that stops it from
8733 issuing at the same time as the branch. We therefore
8734 insert a nop before the branch in order to align its
8736 emit_insn_after (gen_nop (), last2
);
8739 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
8741 /* SUBINSN is the delay slot of INSN, but INSN is
8742 currently unaligned. Insert a nop between
8743 LAST and INSN to align it. */
8744 emit_insn_after (gen_nop (), last
);
8748 mips_sim_issue_insn (&state
, subinsn
);
8750 mips_sim_finish_insn (&state
, insn
);
8752 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8753 length
= get_attr_length (insn
);
8756 /* If the instruction is an asm statement or multi-instruction
8757 mips.md patern, the length is only an estimate. Insert an
8758 8 byte alignment after it so that the following instructions
8759 can be handled correctly. */
8760 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
8761 && (recog_memoized (insn
) < 0 || length
>= 8))
8763 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
8764 next
= NEXT_INSN (next
);
8765 mips_sim_next_cycle (&state
);
8768 else if (length
& 4)
8769 aligned_p
= !aligned_p
;
8774 /* See whether INSN is an aligned label. */
8775 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
8781 /* Subroutine of mips_reorg. If there is a hazard between INSN
8782 and a previous instruction, avoid it by inserting nops after
8785 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8786 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8787 before using the value of that register. *HILO_DELAY counts the
8788 number of instructions since the last hilo hazard (that is,
8789 the number of instructions since the last mflo or mfhi).
8791 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8792 for the next instruction.
8794 LO_REG is an rtx for the LO register, used in dependence checking. */
8797 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
8798 rtx
*delayed_reg
, rtx lo_reg
)
8806 pattern
= PATTERN (insn
);
8808 /* Do not put the whole function in .set noreorder if it contains
8809 an asm statement. We don't know whether there will be hazards
8810 between the asm statement and the gcc-generated code. */
8811 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
8812 cfun
->machine
->all_noreorder_p
= false;
8814 /* Ignore zero-length instructions (barriers and the like). */
8815 ninsns
= get_attr_length (insn
) / 4;
8819 /* Work out how many nops are needed. Note that we only care about
8820 registers that are explicitly mentioned in the instruction's pattern.
8821 It doesn't matter that calls use the argument registers or that they
8822 clobber hi and lo. */
8823 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
8824 nops
= 2 - *hilo_delay
;
8825 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
8830 /* Insert the nops between this instruction and the previous one.
8831 Each new nop takes us further from the last hilo hazard. */
8832 *hilo_delay
+= nops
;
8834 emit_insn_after (gen_hazard_nop (), after
);
8836 /* Set up the state for the next instruction. */
8837 *hilo_delay
+= ninsns
;
8839 if (INSN_CODE (insn
) >= 0)
8840 switch (get_attr_hazard (insn
))
8850 set
= single_set (insn
);
8851 gcc_assert (set
!= 0);
8852 *delayed_reg
= SET_DEST (set
);
8858 /* Go through the instruction stream and insert nops where necessary.
8859 See if the whole function can then be put into .set noreorder &
8863 mips_avoid_hazards (void)
8865 rtx insn
, last_insn
, lo_reg
, delayed_reg
;
8868 /* Force all instructions to be split into their final form. */
8869 split_all_insns_noflow ();
8871 /* Recalculate instruction lengths without taking nops into account. */
8872 cfun
->machine
->ignore_hazard_length_p
= true;
8873 shorten_branches (get_insns ());
8875 cfun
->machine
->all_noreorder_p
= true;
8877 /* Profiled functions can't be all noreorder because the profiler
8878 support uses assembler macros. */
8879 if (current_function_profile
)
8880 cfun
->machine
->all_noreorder_p
= false;
8882 /* Code compiled with -mfix-vr4120 can't be all noreorder because
8883 we rely on the assembler to work around some errata. */
8884 if (TARGET_FIX_VR4120
)
8885 cfun
->machine
->all_noreorder_p
= false;
8887 /* The same is true for -mfix-vr4130 if we might generate mflo or
8888 mfhi instructions. Note that we avoid using mflo and mfhi if
8889 the VR4130 macc and dmacc instructions are available instead;
8890 see the *mfhilo_{si,di}_macc patterns. */
8891 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
8892 cfun
->machine
->all_noreorder_p
= false;
8897 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
8899 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
8902 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
8903 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
8904 mips_avoid_hazard (last_insn
, XVECEXP (PATTERN (insn
), 0, i
),
8905 &hilo_delay
, &delayed_reg
, lo_reg
);
8907 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
8908 &delayed_reg
, lo_reg
);
8915 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8921 mips16_lay_out_constants ();
8922 else if (TARGET_EXPLICIT_RELOCS
)
8924 if (mips_flag_delayed_branch
)
8925 dbr_schedule (get_insns (), dump_file
);
8926 mips_avoid_hazards ();
8927 if (TUNE_MIPS4130
&& TARGET_VR4130_ALIGN
)
8928 vr4130_align_insns ();
8932 /* This function does three things:
8934 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
8935 - Register the mips16 hardware floating point stubs.
8936 - Register the gofast functions if selected using --enable-gofast. */
8938 #include "config/gofast.h"
8941 mips_init_libfuncs (void)
8943 if (TARGET_FIX_VR4120
)
8945 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
8946 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
8949 if (TARGET_MIPS16
&& mips16_hard_float
)
8951 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
8952 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
8953 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
8954 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
8956 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
8957 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
8958 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
8959 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
8960 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
8961 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
8963 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
8964 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
8966 if (TARGET_DOUBLE_FLOAT
)
8968 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
8969 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
8970 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
8971 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
8973 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
8974 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
8975 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
8976 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
8977 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
8978 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
8980 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__mips16_extendsfdf2");
8981 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__mips16_truncdfsf2");
8983 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__mips16_fix_truncdfsi");
8984 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__mips16_floatsidf");
8988 gofast_maybe_init_libfuncs ();
8991 /* Return a number assessing the cost of moving a register in class
8992 FROM to class TO. The classes are expressed using the enumeration
8993 values such as `GENERAL_REGS'. A value of 2 is the default; other
8994 values are interpreted relative to that.
8996 It is not required that the cost always equal 2 when FROM is the
8997 same as TO; on some machines it is expensive to move between
8998 registers if they are not general registers.
9000 If reload sees an insn consisting of a single `set' between two
9001 hard registers, and if `REGISTER_MOVE_COST' applied to their
9002 classes returns a value of 2, reload does not check to ensure that
9003 the constraints of the insn are met. Setting a cost of other than
9004 2 will allow reload to verify that the constraints are met. You
9005 should do this if the `movM' pattern's constraints do not allow
9008 ??? We make the cost of moving from HI/LO into general
9009 registers the same as for one of moving general registers to
9010 HI/LO for TARGET_MIPS16 in order to prevent allocating a
9011 pseudo to HI/LO. This might hurt optimizations though, it
9012 isn't clear if it is wise. And it might not work in all cases. We
9013 could solve the DImode LO reg problem by using a multiply, just
9014 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9015 problem by using divide instructions. divu puts the remainder in
9016 the HI reg, so doing a divide by -1 will move the value in the HI
9017 reg for all values except -1. We could handle that case by using a
9018 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9019 a compare/branch to test the input value to see which instruction
9020 we need to use. This gets pretty messy, but it is feasible. */
9023 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
9024 enum reg_class to
, enum reg_class from
)
9026 if (from
== M16_REGS
&& GR_REG_CLASS_P (to
))
9028 else if (from
== M16_NA_REGS
&& GR_REG_CLASS_P (to
))
9030 else if (GR_REG_CLASS_P (from
))
9034 else if (to
== M16_NA_REGS
)
9036 else if (GR_REG_CLASS_P (to
))
9043 else if (to
== FP_REGS
)
9045 else if (reg_class_subset_p (to
, ACC_REGS
))
9052 else if (COP_REG_CLASS_P (to
))
9057 else if (from
== FP_REGS
)
9059 if (GR_REG_CLASS_P (to
))
9061 else if (to
== FP_REGS
)
9063 else if (to
== ST_REGS
)
9066 else if (reg_class_subset_p (from
, ACC_REGS
))
9068 if (GR_REG_CLASS_P (to
))
9076 else if (from
== ST_REGS
&& GR_REG_CLASS_P (to
))
9078 else if (COP_REG_CLASS_P (from
))
9084 ??? What cases are these? Shouldn't we return 2 here? */
9089 /* Return the length of INSN. LENGTH is the initial length computed by
9090 attributes in the machine-description file. */
9093 mips_adjust_insn_length (rtx insn
, int length
)
9095 /* A unconditional jump has an unfilled delay slot if it is not part
9096 of a sequence. A conditional jump normally has a delay slot, but
9097 does not on MIPS16. */
9098 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
9101 /* See how many nops might be needed to avoid hardware hazards. */
9102 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
9103 switch (get_attr_hazard (insn
))
9117 /* All MIPS16 instructions are a measly two bytes. */
9125 /* Return an asm sequence to start a noat block and load the address
9126 of a label into $1. */
9129 mips_output_load_label (void)
9131 if (TARGET_EXPLICIT_RELOCS
)
9135 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9138 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9141 if (ISA_HAS_LOAD_DELAY
)
9142 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9143 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9147 if (Pmode
== DImode
)
9148 return "%[dla\t%@,%0";
9150 return "%[la\t%@,%0";
9155 /* Output assembly instructions to peform a conditional branch.
9157 INSN is the branch instruction. OPERANDS[0] is the condition.
9158 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9159 of the first operand to the condition. If TWO_OPERANDS_P is
9160 nonzero the comparison takes two operands; OPERANDS[3] will be the
9163 If INVERTED_P is nonzero we are to branch if the condition does
9164 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
9166 LENGTH is the length (in bytes) of the sequence we are to generate.
9167 That tells us whether to generate a simple conditional branch, or a
9168 reversed conditional branch around a `jr' instruction. */
9170 mips_output_conditional_branch (rtx insn
, rtx
*operands
, int two_operands_p
,
9171 int float_p
, int inverted_p
, int length
)
9173 static char buffer
[200];
9174 /* The kind of comparison we are doing. */
9175 enum rtx_code code
= GET_CODE (operands
[0]);
9176 /* Nonzero if the opcode for the comparison needs a `z' indicating
9177 that it is a comparison against zero. */
9179 /* A string to use in the assembly output to represent the first
9181 const char *op1
= "%z2";
9182 /* A string to use in the assembly output to represent the second
9183 operand. Use the hard-wired zero register if there's no second
9185 const char *op2
= (two_operands_p
? ",%z3" : ",%.");
9186 /* The operand-printing string for the comparison. */
9187 const char *const comp
= (float_p
? "%F0" : "%C0");
9188 /* The operand-printing string for the inverted comparison. */
9189 const char *const inverted_comp
= (float_p
? "%W0" : "%N0");
9191 /* The MIPS processors (for levels of the ISA at least two), have
9192 "likely" variants of each branch instruction. These instructions
9193 annul the instruction in the delay slot if the branch is not
9195 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
9197 if (!two_operands_p
)
9199 /* To compute whether than A > B, for example, we normally
9200 subtract B from A and then look at the sign bit. But, if we
9201 are doing an unsigned comparison, and B is zero, we don't
9202 have to do the subtraction. Instead, we can just check to
9203 see if A is nonzero. Thus, we change the CODE here to
9204 reflect the simpler comparison operation. */
9216 /* A condition which will always be true. */
9222 /* A condition which will always be false. */
9228 /* Not a special case. */
9233 /* Relative comparisons are always done against zero. But
9234 equality comparisons are done between two operands, and therefore
9235 do not require a `z' in the assembly language output. */
9236 need_z_p
= (!float_p
&& code
!= EQ
&& code
!= NE
);
9237 /* For comparisons against zero, the zero is not provided
9242 /* Begin by terminating the buffer. That way we can always use
9243 strcat to add to it. */
9250 /* Just a simple conditional branch. */
9252 sprintf (buffer
, "%%*b%s%%?\t%%Z2%%1%%/",
9253 inverted_p
? inverted_comp
: comp
);
9255 sprintf (buffer
, "%%*b%s%s%%?\t%s%s,%%1%%/",
9256 inverted_p
? inverted_comp
: comp
,
9257 need_z_p
? "z" : "",
9267 /* Generate a reversed conditional branch around ` j'
9280 If the original branch was a likely branch, the delay slot
9281 must be executed only if the branch is taken, so generate:
9293 When generating PIC, instead of:
9306 rtx target
= gen_label_rtx ();
9308 orig_target
= operands
[1];
9309 operands
[1] = target
;
9310 /* Generate the reversed comparison. This takes four
9313 sprintf (buffer
, "%%*b%s\t%%Z2%%1",
9314 inverted_p
? comp
: inverted_comp
);
9316 sprintf (buffer
, "%%*b%s%s\t%s%s,%%1",
9317 inverted_p
? comp
: inverted_comp
,
9318 need_z_p
? "z" : "",
9321 output_asm_insn (buffer
, operands
);
9323 if (length
!= 16 && length
!= 28 && ! mips_branch_likely
)
9325 /* Output delay slot instruction. */
9326 rtx insn
= final_sequence
;
9327 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
,
9329 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
9332 output_asm_insn ("%#", 0);
9335 output_asm_insn ("j\t%0", &orig_target
);
9338 output_asm_insn (mips_output_load_label (), &orig_target
);
9339 output_asm_insn ("jr\t%@%]", 0);
9342 if (length
!= 16 && length
!= 28 && mips_branch_likely
)
9344 /* Output delay slot instruction. */
9345 rtx insn
= final_sequence
;
9346 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
,
9348 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
9351 output_asm_insn ("%#", 0);
9353 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
9354 CODE_LABEL_NUMBER (target
));
9367 /* Used to output div or ddiv instruction DIVISION, which has the operands
9368 given by OPERANDS. Add in a divide-by-zero check if needed.
9370 When working around R4000 and R4400 errata, we need to make sure that
9371 the division is not immediately followed by a shift[1][2]. We also
9372 need to stop the division from being put into a branch delay slot[3].
9373 The easiest way to avoid both problems is to add a nop after the
9374 division. When a divide-by-zero check is needed, this nop can be
9375 used to fill the branch delay slot.
9377 [1] If a double-word or a variable shift executes immediately
9378 after starting an integer division, the shift may give an
9379 incorrect result. See quotations of errata #16 and #28 from
9380 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9381 in mips.md for details.
9383 [2] A similar bug to [1] exists for all revisions of the
9384 R4000 and the R4400 when run in an MC configuration.
9385 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9387 "19. In this following sequence:
9389 ddiv (or ddivu or div or divu)
9390 dsll32 (or dsrl32, dsra32)
9392 if an MPT stall occurs, while the divide is slipping the cpu
9393 pipeline, then the following double shift would end up with an
9396 Workaround: The compiler needs to avoid generating any
9397 sequence with divide followed by extended double shift."
9399 This erratum is also present in "MIPS R4400MC Errata, Processor
9400 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9401 & 3.0" as errata #10 and #4, respectively.
9403 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9404 (also valid for MIPS R4000MC processors):
9406 "52. R4000SC: This bug does not apply for the R4000PC.
9408 There are two flavors of this bug:
9410 1) If the instruction just after divide takes an RF exception
9411 (tlb-refill, tlb-invalid) and gets an instruction cache
9412 miss (both primary and secondary) and the line which is
9413 currently in secondary cache at this index had the first
9414 data word, where the bits 5..2 are set, then R4000 would
9415 get a wrong result for the div.
9420 ------------------- # end-of page. -tlb-refill
9425 ------------------- # end-of page. -tlb-invalid
9428 2) If the divide is in the taken branch delay slot, where the
9429 target takes RF exception and gets an I-cache miss for the
9430 exception vector or where I-cache miss occurs for the
9431 target address, under the above mentioned scenarios, the
9432 div would get wrong results.
9435 j r2 # to next page mapped or unmapped
9436 div r8,r9 # this bug would be there as long
9437 # as there is an ICache miss and
9438 nop # the "data pattern" is present
9441 beq r0, r0, NextPage # to Next page
9445 This bug is present for div, divu, ddiv, and ddivu
9448 Workaround: For item 1), OS could make sure that the next page
9449 after the divide instruction is also mapped. For item 2), the
9450 compiler could make sure that the divide instruction is not in
9451 the branch delay slot."
9453 These processors have PRId values of 0x00004220 and 0x00004300 for
9454 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9457 mips_output_division (const char *division
, rtx
*operands
)
9462 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
9464 output_asm_insn (s
, operands
);
9467 if (TARGET_CHECK_ZERO_DIV
)
9471 output_asm_insn (s
, operands
);
9472 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
9474 else if (GENERATE_DIVIDE_TRAPS
)
9476 output_asm_insn (s
, operands
);
9481 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
9482 output_asm_insn (s
, operands
);
9483 s
= "break\t7%)\n1:";
9489 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9490 with a final "000" replaced by "k". Ignore case.
9492 Note: this function is shared between GCC and GAS. */
9495 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
9497 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
9498 given
++, canonical
++;
9500 return ((*given
== 0 && *canonical
== 0)
9501 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
9505 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9506 CPU name. We've traditionally allowed a lot of variation here.
9508 Note: this function is shared between GCC and GAS. */
9511 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
9513 /* First see if the name matches exactly, or with a final "000"
9515 if (mips_strict_matching_cpu_name_p (canonical
, given
))
9518 /* If not, try comparing based on numerical designation alone.
9519 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9520 if (TOLOWER (*given
) == 'r')
9522 if (!ISDIGIT (*given
))
9525 /* Skip over some well-known prefixes in the canonical name,
9526 hoping to find a number there too. */
9527 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
9529 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
9531 else if (TOLOWER (canonical
[0]) == 'r')
9534 return mips_strict_matching_cpu_name_p (canonical
, given
);
9538 /* Return the mips_cpu_info entry for the processor or ISA given
9539 by CPU_STRING. Return null if the string isn't recognized.
9541 A similar function exists in GAS. */
9543 static const struct mips_cpu_info
*
9544 mips_parse_cpu (const char *cpu_string
)
9546 const struct mips_cpu_info
*p
;
9549 /* In the past, we allowed upper-case CPU names, but it doesn't
9550 work well with the multilib machinery. */
9551 for (s
= cpu_string
; *s
!= 0; s
++)
9554 warning (0, "the cpu name must be lower case");
9558 /* 'from-abi' selects the most compatible architecture for the given
9559 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9560 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9561 version. Look first at the -mgp options, if given, otherwise base
9562 the choice on MASK_64BIT in TARGET_DEFAULT. */
9563 if (strcasecmp (cpu_string
, "from-abi") == 0)
9564 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
9565 : ABI_NEEDS_64BIT_REGS
? 3
9566 : (TARGET_64BIT
? 3 : 1));
9568 /* 'default' has traditionally been a no-op. Probably not very useful. */
9569 if (strcasecmp (cpu_string
, "default") == 0)
9572 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
9573 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
9580 /* Return the processor associated with the given ISA level, or null
9581 if the ISA isn't valid. */
9583 static const struct mips_cpu_info
*
9584 mips_cpu_info_from_isa (int isa
)
9586 const struct mips_cpu_info
*p
;
9588 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
9595 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9596 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9597 they only hold condition code modes, and CCmode is always considered to
9598 be 4 bytes wide. All other registers are word sized. */
9601 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
9603 if (ST_REG_P (regno
))
9604 return ((GET_MODE_SIZE (mode
) + 3) / 4);
9605 else if (! FP_REG_P (regno
))
9606 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
9608 return ((GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
);
9611 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9612 all BLKmode objects are returned in memory. Under the new (N32 and
9613 64-bit MIPS ABIs) small structures are returned in a register.
9614 Objects with varying size must still be returned in memory, of
9618 mips_return_in_memory (tree type
, tree fndecl ATTRIBUTE_UNUSED
)
9621 return (TYPE_MODE (type
) == BLKmode
);
9623 return ((int_size_in_bytes (type
) > (2 * UNITS_PER_WORD
))
9624 || (int_size_in_bytes (type
) == -1));
9628 mips_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
9630 return !TARGET_OLDABI
;
9633 /* Return true if INSN is a multiply-add or multiply-subtract
9634 instruction and PREV assigns to the accumulator operand. */
9637 mips_linked_madd_p (rtx prev
, rtx insn
)
9641 x
= single_set (insn
);
9647 if (GET_CODE (x
) == PLUS
9648 && GET_CODE (XEXP (x
, 0)) == MULT
9649 && reg_set_p (XEXP (x
, 1), prev
))
9652 if (GET_CODE (x
) == MINUS
9653 && GET_CODE (XEXP (x
, 1)) == MULT
9654 && reg_set_p (XEXP (x
, 0), prev
))
9660 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9661 that may clobber hi or lo. */
9663 static rtx mips_macc_chains_last_hilo
;
9665 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9666 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9669 mips_macc_chains_record (rtx insn
)
9671 if (get_attr_may_clobber_hilo (insn
))
9672 mips_macc_chains_last_hilo
= insn
;
9675 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9676 has NREADY elements, looking for a multiply-add or multiply-subtract
9677 instruction that is cumulative with mips_macc_chains_last_hilo.
9678 If there is one, promote it ahead of anything else that might
9679 clobber hi or lo. */
9682 mips_macc_chains_reorder (rtx
*ready
, int nready
)
9686 if (mips_macc_chains_last_hilo
!= 0)
9687 for (i
= nready
- 1; i
>= 0; i
--)
9688 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
9690 for (j
= nready
- 1; j
> i
; j
--)
9691 if (recog_memoized (ready
[j
]) >= 0
9692 && get_attr_may_clobber_hilo (ready
[j
]))
9694 mips_promote_ready (ready
, i
, j
);
9701 /* The last instruction to be scheduled. */
9703 static rtx vr4130_last_insn
;
9705 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9706 points to an rtx that is initially an instruction. Nullify the rtx
9707 if the instruction uses the value of register X. */
9710 vr4130_true_reg_dependence_p_1 (rtx x
, rtx pat ATTRIBUTE_UNUSED
, void *data
)
9712 rtx
*insn_ptr
= data
;
9715 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
9719 /* Return true if there is true register dependence between vr4130_last_insn
9723 vr4130_true_reg_dependence_p (rtx insn
)
9725 note_stores (PATTERN (vr4130_last_insn
),
9726 vr4130_true_reg_dependence_p_1
, &insn
);
9730 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9731 the ready queue and that INSN2 is the instruction after it, return
9732 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9733 in which INSN1 and INSN2 can probably issue in parallel, but for
9734 which (INSN2, INSN1) should be less sensitive to instruction
9735 alignment than (INSN1, INSN2). See 4130.md for more details. */
9738 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
9742 /* Check for the following case:
9744 1) there is some other instruction X with an anti dependence on INSN1;
9745 2) X has a higher priority than INSN2; and
9746 3) X is an arithmetic instruction (and thus has no unit restrictions).
9748 If INSN1 is the last instruction blocking X, it would better to
9749 choose (INSN1, X) over (INSN2, INSN1). */
9750 for (dep
= INSN_DEPEND (insn1
); dep
!= 0; dep
= XEXP (dep
, 1))
9751 if (REG_NOTE_KIND (dep
) == REG_DEP_ANTI
9752 && INSN_PRIORITY (XEXP (dep
, 0)) > INSN_PRIORITY (insn2
)
9753 && recog_memoized (XEXP (dep
, 0)) >= 0
9754 && get_attr_vr4130_class (XEXP (dep
, 0)) == VR4130_CLASS_ALU
)
9757 if (vr4130_last_insn
!= 0
9758 && recog_memoized (insn1
) >= 0
9759 && recog_memoized (insn2
) >= 0)
9761 /* See whether INSN1 and INSN2 use different execution units,
9762 or if they are both ALU-type instructions. If so, they can
9763 probably execute in parallel. */
9764 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
9765 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
9766 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
9768 /* If only one of the instructions has a dependence on
9769 vr4130_last_insn, prefer to schedule the other one first. */
9770 bool dep1
= vr4130_true_reg_dependence_p (insn1
);
9771 bool dep2
= vr4130_true_reg_dependence_p (insn2
);
9775 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9776 is not an ALU-type instruction and if INSN1 uses the same
9777 execution unit. (Note that if this condition holds, we already
9778 know that INSN2 uses a different execution unit.) */
9779 if (class1
!= VR4130_CLASS_ALU
9780 && recog_memoized (vr4130_last_insn
) >= 0
9781 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
9788 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9789 queue with at least two instructions. Swap the first two if
9790 vr4130_swap_insns_p says that it could be worthwhile. */
9793 vr4130_reorder (rtx
*ready
, int nready
)
9795 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
9796 mips_promote_ready (ready
, nready
- 2, nready
- 1);
9799 /* Remove the instruction at index LOWER from ready queue READY and
9800 reinsert it in front of the instruction at index HIGHER. LOWER must
9804 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
9809 new_head
= ready
[lower
];
9810 for (i
= lower
; i
< higher
; i
++)
9811 ready
[i
] = ready
[i
+ 1];
9812 ready
[i
] = new_head
;
9815 /* Implement TARGET_SCHED_REORDER. */
9818 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9819 rtx
*ready
, int *nreadyp
, int cycle
)
9821 if (!reload_completed
&& TUNE_MACC_CHAINS
)
9824 mips_macc_chains_last_hilo
= 0;
9826 mips_macc_chains_reorder (ready
, *nreadyp
);
9828 if (reload_completed
&& TUNE_MIPS4130
&& !TARGET_VR4130_ALIGN
)
9831 vr4130_last_insn
= 0;
9833 vr4130_reorder (ready
, *nreadyp
);
9835 return mips_issue_rate ();
9838 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9841 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9844 switch (GET_CODE (PATTERN (insn
)))
9848 /* Don't count USEs and CLOBBERs against the issue rate. */
9853 if (!reload_completed
&& TUNE_MACC_CHAINS
)
9854 mips_macc_chains_record (insn
);
9855 vr4130_last_insn
= insn
;
9861 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9862 dependencies have no cost. */
9865 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
9866 rtx dep ATTRIBUTE_UNUSED
, int cost
)
9868 if (REG_NOTE_KIND (link
) != 0)
9873 /* Return the number of instructions that can be issued per cycle. */
9876 mips_issue_rate (void)
9880 case PROCESSOR_R4130
:
9881 case PROCESSOR_R5400
:
9882 case PROCESSOR_R5500
:
9883 case PROCESSOR_R7000
:
9884 case PROCESSOR_R9000
:
9888 /* This is actually 4, but we get better performance if we claim 3.
9889 This is partly because of unwanted speculative code motion with the
9890 larger number, and partly because in most common cases we can't
9891 reach the theoretical max of 4. */
9899 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9900 be as wide as the scheduling freedom in the DFA. */
9903 mips_multipass_dfa_lookahead (void)
9905 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9906 if (mips_tune
== PROCESSOR_SB1
)
9912 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9913 return the first operand of the associated "pref" or "prefx" insn. */
9916 mips_prefetch_cookie (rtx write
, rtx locality
)
9918 /* store_streamed / load_streamed. */
9919 if (INTVAL (locality
) <= 0)
9920 return GEN_INT (INTVAL (write
) + 4);
9923 if (INTVAL (locality
) <= 2)
9926 /* store_retained / load_retained. */
9927 return GEN_INT (INTVAL (write
) + 6);
9930 /* MIPS builtin function support. */
9932 struct builtin_description
9934 /* The code of the main .md file instruction. See mips_builtin_type
9935 for more information. */
9936 enum insn_code icode
;
9938 /* The floating-point comparison code to use with ICODE, if any. */
9939 enum mips_fp_condition cond
;
9941 /* The name of the builtin function. */
9944 /* Specifies how the function should be expanded. */
9945 enum mips_builtin_type builtin_type
;
9947 /* The function's prototype. */
9948 enum mips_function_type function_type
;
9950 /* The target flags required for this function. */
9954 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9955 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9956 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9957 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9958 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9960 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9962 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9963 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9964 "__builtin_mips_" #INSN "_" #COND "_s", \
9965 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9966 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9967 "__builtin_mips_" #INSN "_" #COND "_d", \
9968 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9970 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9971 The lower and upper forms require TARGET_FLAGS while the any and all
9972 forms require MASK_MIPS3D. */
9973 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9974 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9975 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9976 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9977 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9978 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
9979 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9980 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9981 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
9982 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9983 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9984 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
9985 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
9987 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
9988 require MASK_MIPS3D. */
9989 #define CMP_4S_BUILTINS(INSN, COND) \
9990 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9991 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
9992 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9994 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9995 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
9996 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9999 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10000 instruction requires TARGET_FLAGS. */
10001 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10002 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10003 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10004 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10006 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10007 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10008 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10011 /* Define all the builtins related to c.cond.fmt condition COND. */
10012 #define CMP_BUILTINS(COND) \
10013 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10014 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10015 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10016 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10017 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10018 CMP_4S_BUILTINS (c, COND), \
10019 CMP_4S_BUILTINS (cabs, COND)
10021 /* __builtin_mips_abs_ps() maps to the standard absM2 pattern. */
10022 #define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
10024 static const struct builtin_description mips_bdesc
[] =
10026 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10027 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10028 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10029 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10030 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, MASK_PAIRED_SINGLE_FLOAT
),
10031 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10032 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10033 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10035 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
,
10036 MASK_PAIRED_SINGLE_FLOAT
),
10037 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10038 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10039 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10040 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10042 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
10043 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
10044 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10045 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
10046 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
10047 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10049 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
10050 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
10051 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10052 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
10053 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
10054 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10056 MIPS_FP_CONDITIONS (CMP_BUILTINS
)
10059 /* Builtin functions for the SB-1 processor. */
10061 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10063 static const struct builtin_description sb1_bdesc
[] =
10065 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
)
10068 /* Builtin functions for DSP ASE. */
10070 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10071 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10072 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10073 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10075 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10076 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10077 builtin_description fields. */
10078 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10079 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10080 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10082 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10083 branch instruction. TARGET_FLAGS is a builtin_description field. */
10084 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10085 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10086 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10088 static const struct builtin_description dsp_bdesc
[] =
10090 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10091 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10092 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10093 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10094 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10095 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10096 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10097 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10098 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10099 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10100 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10101 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10102 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10103 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, MASK_DSP
),
10104 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, MASK_DSP
),
10105 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10106 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10107 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, MASK_DSP
),
10108 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, MASK_DSP
),
10109 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10110 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, MASK_DSP
),
10111 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, MASK_DSP
),
10112 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10113 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10114 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10115 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10116 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10117 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10118 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10119 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10120 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSP
),
10121 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10122 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10123 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10124 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSP
),
10125 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10126 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10127 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10128 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, MASK_DSP
),
10129 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, MASK_DSP
),
10130 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10131 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10132 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10133 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10134 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10135 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10136 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10137 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10138 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10139 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10140 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSP
),
10141 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSP
),
10142 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10143 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10144 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10145 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10146 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10147 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10148 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, MASK_DSP
),
10149 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, MASK_DSP
),
10150 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10151 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10152 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10153 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10154 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10155 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10156 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10157 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10158 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10159 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10160 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10161 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10162 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10163 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10164 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10165 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10166 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10167 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10168 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, MASK_DSP
),
10169 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, MASK_DSP
),
10170 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, MASK_DSP
),
10171 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10172 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_PTR_SI
, MASK_DSP
),
10173 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_PTR_SI
, MASK_DSP
),
10174 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_PTR_SI
, MASK_DSP
),
10175 BPOSGE_BUILTIN (32, MASK_DSP
)
10178 /* This helps provide a mapping from builtin function codes to bdesc
10183 /* The builtin function table that this entry describes. */
10184 const struct builtin_description
*bdesc
;
10186 /* The number of entries in the builtin function table. */
10189 /* The target processor that supports these builtin functions.
10190 PROCESSOR_MAX means we enable them for all processors. */
10191 enum processor_type proc
;
10194 static const struct bdesc_map bdesc_arrays
[] =
10196 { mips_bdesc
, ARRAY_SIZE (mips_bdesc
), PROCESSOR_MAX
},
10197 { sb1_bdesc
, ARRAY_SIZE (sb1_bdesc
), PROCESSOR_SB1
},
10198 { dsp_bdesc
, ARRAY_SIZE (dsp_bdesc
), PROCESSOR_MAX
}
10201 /* Take the head of argument list *ARGLIST and convert it into a form
10202 suitable for input operand OP of instruction ICODE. Return the value
10203 and point *ARGLIST at the next element of the list. */
10206 mips_prepare_builtin_arg (enum insn_code icode
,
10207 unsigned int op
, tree
*arglist
)
10210 enum machine_mode mode
;
10212 value
= expand_normal (TREE_VALUE (*arglist
));
10213 mode
= insn_data
[icode
].operand
[op
].mode
;
10214 if (!insn_data
[icode
].operand
[op
].predicate (value
, mode
))
10216 value
= copy_to_mode_reg (mode
, value
);
10217 /* Check the predicate again. */
10218 if (!insn_data
[icode
].operand
[op
].predicate (value
, mode
))
10220 error ("invalid argument to builtin function");
10225 *arglist
= TREE_CHAIN (*arglist
);
10229 /* Return an rtx suitable for output operand OP of instruction ICODE.
10230 If TARGET is non-null, try to use it where possible. */
10233 mips_prepare_builtin_target (enum insn_code icode
, unsigned int op
, rtx target
)
10235 enum machine_mode mode
;
10237 mode
= insn_data
[icode
].operand
[op
].mode
;
10238 if (target
== 0 || !insn_data
[icode
].operand
[op
].predicate (target
, mode
))
10239 target
= gen_reg_rtx (mode
);
10244 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10247 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10248 enum machine_mode mode ATTRIBUTE_UNUSED
,
10249 int ignore ATTRIBUTE_UNUSED
)
10251 enum insn_code icode
;
10252 enum mips_builtin_type type
;
10253 tree fndecl
, arglist
;
10254 unsigned int fcode
;
10255 const struct builtin_description
*bdesc
;
10256 const struct bdesc_map
*m
;
10258 fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
10259 arglist
= TREE_OPERAND (exp
, 1);
10260 fcode
= DECL_FUNCTION_CODE (fndecl
);
10263 for (m
= bdesc_arrays
; m
< &bdesc_arrays
[ARRAY_SIZE (bdesc_arrays
)]; m
++)
10265 if (fcode
< m
->size
)
10268 icode
= bdesc
[fcode
].icode
;
10269 type
= bdesc
[fcode
].builtin_type
;
10279 case MIPS_BUILTIN_DIRECT
:
10280 return mips_expand_builtin_direct (icode
, target
, arglist
, true);
10282 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
10283 return mips_expand_builtin_direct (icode
, target
, arglist
, false);
10285 case MIPS_BUILTIN_MOVT
:
10286 case MIPS_BUILTIN_MOVF
:
10287 return mips_expand_builtin_movtf (type
, icode
, bdesc
[fcode
].cond
,
10290 case MIPS_BUILTIN_CMP_ANY
:
10291 case MIPS_BUILTIN_CMP_ALL
:
10292 case MIPS_BUILTIN_CMP_UPPER
:
10293 case MIPS_BUILTIN_CMP_LOWER
:
10294 case MIPS_BUILTIN_CMP_SINGLE
:
10295 return mips_expand_builtin_compare (type
, icode
, bdesc
[fcode
].cond
,
10298 case MIPS_BUILTIN_BPOSGE32
:
10299 return mips_expand_builtin_bposge (type
, target
);
10306 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10309 mips_init_builtins (void)
10311 const struct builtin_description
*d
;
10312 const struct bdesc_map
*m
;
10313 tree types
[(int) MIPS_MAX_FTYPE_MAX
];
10314 tree V2SF_type_node
;
10315 tree V2HI_type_node
;
10316 tree V4QI_type_node
;
10317 unsigned int offset
;
10319 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10320 if (!TARGET_PAIRED_SINGLE_FLOAT
&& !TARGET_DSP
)
10323 if (TARGET_PAIRED_SINGLE_FLOAT
)
10325 V2SF_type_node
= build_vector_type_for_mode (float_type_node
, V2SFmode
);
10327 types
[MIPS_V2SF_FTYPE_V2SF
]
10328 = build_function_type_list (V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
10330 types
[MIPS_V2SF_FTYPE_V2SF_V2SF
]
10331 = build_function_type_list (V2SF_type_node
,
10332 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
10334 types
[MIPS_V2SF_FTYPE_V2SF_V2SF_INT
]
10335 = build_function_type_list (V2SF_type_node
,
10336 V2SF_type_node
, V2SF_type_node
,
10337 integer_type_node
, NULL_TREE
);
10339 types
[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF
]
10340 = build_function_type_list (V2SF_type_node
,
10341 V2SF_type_node
, V2SF_type_node
,
10342 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
10344 types
[MIPS_V2SF_FTYPE_SF_SF
]
10345 = build_function_type_list (V2SF_type_node
,
10346 float_type_node
, float_type_node
, NULL_TREE
);
10348 types
[MIPS_INT_FTYPE_V2SF_V2SF
]
10349 = build_function_type_list (integer_type_node
,
10350 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
10352 types
[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF
]
10353 = build_function_type_list (integer_type_node
,
10354 V2SF_type_node
, V2SF_type_node
,
10355 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
10357 types
[MIPS_INT_FTYPE_SF_SF
]
10358 = build_function_type_list (integer_type_node
,
10359 float_type_node
, float_type_node
, NULL_TREE
);
10361 types
[MIPS_INT_FTYPE_DF_DF
]
10362 = build_function_type_list (integer_type_node
,
10363 double_type_node
, double_type_node
, NULL_TREE
);
10365 types
[MIPS_SF_FTYPE_V2SF
]
10366 = build_function_type_list (float_type_node
, V2SF_type_node
, NULL_TREE
);
10368 types
[MIPS_SF_FTYPE_SF
]
10369 = build_function_type_list (float_type_node
,
10370 float_type_node
, NULL_TREE
);
10372 types
[MIPS_SF_FTYPE_SF_SF
]
10373 = build_function_type_list (float_type_node
,
10374 float_type_node
, float_type_node
, NULL_TREE
);
10376 types
[MIPS_DF_FTYPE_DF
]
10377 = build_function_type_list (double_type_node
,
10378 double_type_node
, NULL_TREE
);
10380 types
[MIPS_DF_FTYPE_DF_DF
]
10381 = build_function_type_list (double_type_node
,
10382 double_type_node
, double_type_node
, NULL_TREE
);
10387 V2HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V2HImode
);
10388 V4QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V4QImode
);
10390 types
[MIPS_V2HI_FTYPE_V2HI_V2HI
]
10391 = build_function_type_list (V2HI_type_node
,
10392 V2HI_type_node
, V2HI_type_node
,
10395 types
[MIPS_SI_FTYPE_SI_SI
]
10396 = build_function_type_list (intSI_type_node
,
10397 intSI_type_node
, intSI_type_node
,
10400 types
[MIPS_V4QI_FTYPE_V4QI_V4QI
]
10401 = build_function_type_list (V4QI_type_node
,
10402 V4QI_type_node
, V4QI_type_node
,
10405 types
[MIPS_SI_FTYPE_V4QI
]
10406 = build_function_type_list (intSI_type_node
,
10410 types
[MIPS_V2HI_FTYPE_V2HI
]
10411 = build_function_type_list (V2HI_type_node
,
10415 types
[MIPS_SI_FTYPE_SI
]
10416 = build_function_type_list (intSI_type_node
,
10420 types
[MIPS_V4QI_FTYPE_V2HI_V2HI
]
10421 = build_function_type_list (V4QI_type_node
,
10422 V2HI_type_node
, V2HI_type_node
,
10425 types
[MIPS_V2HI_FTYPE_SI_SI
]
10426 = build_function_type_list (V2HI_type_node
,
10427 intSI_type_node
, intSI_type_node
,
10430 types
[MIPS_SI_FTYPE_V2HI
]
10431 = build_function_type_list (intSI_type_node
,
10435 types
[MIPS_V2HI_FTYPE_V4QI
]
10436 = build_function_type_list (V2HI_type_node
,
10440 types
[MIPS_V4QI_FTYPE_V4QI_SI
]
10441 = build_function_type_list (V4QI_type_node
,
10442 V4QI_type_node
, intSI_type_node
,
10445 types
[MIPS_V2HI_FTYPE_V2HI_SI
]
10446 = build_function_type_list (V2HI_type_node
,
10447 V2HI_type_node
, intSI_type_node
,
10450 types
[MIPS_V2HI_FTYPE_V4QI_V2HI
]
10451 = build_function_type_list (V2HI_type_node
,
10452 V4QI_type_node
, V2HI_type_node
,
10455 types
[MIPS_SI_FTYPE_V2HI_V2HI
]
10456 = build_function_type_list (intSI_type_node
,
10457 V2HI_type_node
, V2HI_type_node
,
10460 types
[MIPS_DI_FTYPE_DI_V4QI_V4QI
]
10461 = build_function_type_list (intDI_type_node
,
10462 intDI_type_node
, V4QI_type_node
, V4QI_type_node
,
10465 types
[MIPS_DI_FTYPE_DI_V2HI_V2HI
]
10466 = build_function_type_list (intDI_type_node
,
10467 intDI_type_node
, V2HI_type_node
, V2HI_type_node
,
10470 types
[MIPS_DI_FTYPE_DI_SI_SI
]
10471 = build_function_type_list (intDI_type_node
,
10472 intDI_type_node
, intSI_type_node
, intSI_type_node
,
10475 types
[MIPS_V4QI_FTYPE_SI
]
10476 = build_function_type_list (V4QI_type_node
,
10480 types
[MIPS_V2HI_FTYPE_SI
]
10481 = build_function_type_list (V2HI_type_node
,
10485 types
[MIPS_VOID_FTYPE_V4QI_V4QI
]
10486 = build_function_type_list (void_type_node
,
10487 V4QI_type_node
, V4QI_type_node
,
10490 types
[MIPS_SI_FTYPE_V4QI_V4QI
]
10491 = build_function_type_list (intSI_type_node
,
10492 V4QI_type_node
, V4QI_type_node
,
10495 types
[MIPS_VOID_FTYPE_V2HI_V2HI
]
10496 = build_function_type_list (void_type_node
,
10497 V2HI_type_node
, V2HI_type_node
,
10500 types
[MIPS_SI_FTYPE_DI_SI
]
10501 = build_function_type_list (intSI_type_node
,
10502 intDI_type_node
, intSI_type_node
,
10505 types
[MIPS_DI_FTYPE_DI_SI
]
10506 = build_function_type_list (intDI_type_node
,
10507 intDI_type_node
, intSI_type_node
,
10510 types
[MIPS_VOID_FTYPE_SI_SI
]
10511 = build_function_type_list (void_type_node
,
10512 intSI_type_node
, intSI_type_node
,
10515 types
[MIPS_SI_FTYPE_PTR_SI
]
10516 = build_function_type_list (intSI_type_node
,
10517 ptr_type_node
, intSI_type_node
,
10520 types
[MIPS_SI_FTYPE_VOID
]
10521 = build_function_type (intSI_type_node
, void_list_node
);
10524 /* Iterate through all of the bdesc arrays, initializing all of the
10525 builtin functions. */
10528 for (m
= bdesc_arrays
; m
< &bdesc_arrays
[ARRAY_SIZE (bdesc_arrays
)]; m
++)
10530 if (m
->proc
== PROCESSOR_MAX
|| (m
->proc
== mips_arch
))
10531 for (d
= m
->bdesc
; d
< &m
->bdesc
[m
->size
]; d
++)
10532 if ((d
->target_flags
& target_flags
) == d
->target_flags
)
10533 lang_hooks
.builtin_function (d
->name
, types
[d
->function_type
],
10534 d
- m
->bdesc
+ offset
,
10535 BUILT_IN_MD
, NULL
, NULL
);
10540 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10541 .md pattern and ARGLIST is the list of function arguments. TARGET,
10542 if nonnull, suggests a good place to put the result.
10543 HAS_TARGET indicates the function must return something. */
10546 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree arglist
,
10549 rtx ops
[MAX_RECOG_OPERANDS
];
10554 /* We save target to ops[0]. */
10555 ops
[0] = mips_prepare_builtin_target (icode
, 0, target
);
10559 /* We need to test if arglist is not zero. Some instructions have extra
10560 clobber registers. */
10561 for (; i
< insn_data
[icode
].n_operands
&& arglist
!= 0; i
++)
10562 ops
[i
] = mips_prepare_builtin_arg (icode
, i
, &arglist
);
10567 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1]));
10571 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2]));
10575 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2], ops
[3]));
10579 gcc_unreachable ();
10584 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10585 function (TYPE says which). ARGLIST is the list of arguments to the
10586 function, ICODE is the instruction that should be used to compare
10587 the first two arguments, and COND is the condition it should test.
10588 TARGET, if nonnull, suggests a good place to put the result. */
10591 mips_expand_builtin_movtf (enum mips_builtin_type type
,
10592 enum insn_code icode
, enum mips_fp_condition cond
,
10593 rtx target
, tree arglist
)
10595 rtx cmp_result
, op0
, op1
;
10597 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
10598 op0
= mips_prepare_builtin_arg (icode
, 1, &arglist
);
10599 op1
= mips_prepare_builtin_arg (icode
, 2, &arglist
);
10600 emit_insn (GEN_FCN (icode
) (cmp_result
, op0
, op1
, GEN_INT (cond
)));
10602 icode
= CODE_FOR_mips_cond_move_tf_ps
;
10603 target
= mips_prepare_builtin_target (icode
, 0, target
);
10604 if (type
== MIPS_BUILTIN_MOVT
)
10606 op1
= mips_prepare_builtin_arg (icode
, 2, &arglist
);
10607 op0
= mips_prepare_builtin_arg (icode
, 1, &arglist
);
10611 op0
= mips_prepare_builtin_arg (icode
, 1, &arglist
);
10612 op1
= mips_prepare_builtin_arg (icode
, 2, &arglist
);
10614 emit_insn (gen_mips_cond_move_tf_ps (target
, op0
, op1
, cmp_result
));
10618 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10619 of the comparison instruction and COND is the condition it should test.
10620 ARGLIST is the list of function arguments and TARGET, if nonnull,
10621 suggests a good place to put the boolean result. */
10624 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
10625 enum insn_code icode
, enum mips_fp_condition cond
,
10626 rtx target
, tree arglist
)
10628 rtx label1
, label2
, if_then_else
;
10629 rtx pat
, cmp_result
, ops
[MAX_RECOG_OPERANDS
];
10630 rtx target_if_equal
, target_if_unequal
;
10633 if (target
== 0 || GET_MODE (target
) != SImode
)
10634 target
= gen_reg_rtx (SImode
);
10636 /* Prepare the operands to the comparison. */
10637 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
10638 for (i
= 1; i
< insn_data
[icode
].n_operands
- 1; i
++)
10639 ops
[i
] = mips_prepare_builtin_arg (icode
, i
, &arglist
);
10641 switch (insn_data
[icode
].n_operands
)
10644 pat
= GEN_FCN (icode
) (cmp_result
, ops
[1], ops
[2], GEN_INT (cond
));
10648 pat
= GEN_FCN (icode
) (cmp_result
, ops
[1], ops
[2],
10649 ops
[3], ops
[4], GEN_INT (cond
));
10653 gcc_unreachable ();
10656 /* If the comparison sets more than one register, we define the result
10657 to be 0 if all registers are false and -1 if all registers are true.
10658 The value of the complete result is indeterminate otherwise. It is
10659 possible to test individual registers using SUBREGs.
10661 Set up CMP_RESULT, CMP_VALUE, TARGET_IF_EQUAL and TARGET_IF_UNEQUAL so
10662 that the result should be TARGET_IF_EQUAL if (EQ CMP_RESULT CMP_VALUE)
10663 and TARGET_IF_UNEQUAL otherwise. */
10664 if (builtin_type
== MIPS_BUILTIN_CMP_ALL
)
10667 target_if_equal
= const1_rtx
;
10668 target_if_unequal
= const0_rtx
;
10673 target_if_equal
= const0_rtx
;
10674 target_if_unequal
= const1_rtx
;
10675 if (builtin_type
== MIPS_BUILTIN_CMP_UPPER
)
10676 cmp_result
= simplify_gen_subreg (CCmode
, cmp_result
, CCV2mode
, 4);
10677 else if (builtin_type
== MIPS_BUILTIN_CMP_LOWER
)
10678 cmp_result
= simplify_gen_subreg (CCmode
, cmp_result
, CCV2mode
, 0);
10681 /* First assume that CMP_RESULT == CMP_VALUE. */
10682 emit_move_insn (target
, target_if_equal
);
10684 /* Branch to LABEL1 if CMP_RESULT != CMP_VALUE. */
10686 label1
= gen_label_rtx ();
10687 label2
= gen_label_rtx ();
10689 = gen_rtx_IF_THEN_ELSE (VOIDmode
,
10690 gen_rtx_fmt_ee (NE
, GET_MODE (cmp_result
),
10691 cmp_result
, GEN_INT (cmp_value
)),
10692 gen_rtx_LABEL_REF (VOIDmode
, label1
), pc_rtx
);
10693 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_then_else
));
10694 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
10695 gen_rtx_LABEL_REF (VOIDmode
, label2
)));
10697 emit_label (label1
);
10699 /* Fix TARGET for CMP_RESULT != CMP_VALUE. */
10700 emit_move_insn (target
, target_if_unequal
);
10701 emit_label (label2
);
10706 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10707 suggests a good place to put the boolean result.
10709 The sequence we want is
10719 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
10721 rtx label1
, label2
, if_then_else
;
10725 if (target
== 0 || GET_MODE (target
) != SImode
)
10726 target
= gen_reg_rtx (SImode
);
10728 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
10730 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
10735 /* Move 0 to target */
10736 emit_move_insn (target
, const0_rtx
);
10738 /* Generate two labels */
10739 label1
= gen_label_rtx ();
10740 label2
= gen_label_rtx ();
10742 /* Generate if_then_else */
10744 = gen_rtx_IF_THEN_ELSE (VOIDmode
,
10745 gen_rtx_fmt_ee (GE
, CCDSPmode
,
10746 cmp_result
, GEN_INT (cmp_value
)),
10747 gen_rtx_LABEL_REF (VOIDmode
, label1
), pc_rtx
);
10749 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_then_else
));
10750 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
10751 gen_rtx_LABEL_REF (VOIDmode
, label2
)));
10753 emit_label (label1
);
10754 emit_move_insn (target
, const1_rtx
);
10755 emit_label (label2
);
10760 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10761 FIRST is true if this is the first time handling this decl. */
10764 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
10766 default_encode_section_info (decl
, rtl
, first
);
10768 if (TREE_CODE (decl
) == FUNCTION_DECL
10769 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
10771 rtx symbol
= XEXP (rtl
, 0);
10772 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
10776 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. TARGET_ABICALLS makes
10777 PIC_FUNCTION_ADDR_REGNUM live on entry to a function. */
10780 mips_extra_live_on_entry (bitmap regs
)
10782 if (!TARGET_ABICALLS
)
10783 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10787 #include "gt-mips.h"