1 /* Intrinsic definitions of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
29 /* Attribute of a interrupt or exception handler:
31 NDS32_READY_NESTED: This handler is interruptible if user re-enable GIE bit.
32 NDS32_NESTED : This handler is interruptible. This is not suitable
34 NDS32_NOT_NESTED : This handler is NOT interruptible. Users have to do
35 some work if nested is wanted
36 NDS32_CRITICAL : This handler is critical ISR, which means it is small
38 #define NDS32_READY_NESTED 0
39 #define NDS32_NESTED 1
40 #define NDS32_NOT_NESTED 2
41 #define NDS32_CRITICAL 3
43 /* Attribute of a interrupt or exception handler:
45 NDS32_SAVE_ALL_REGS : Save all registers in a table.
46 NDS32_SAVE_PARTIAL_REGS: Save partial registers. */
47 #define NDS32_SAVE_CALLER_REGS 0
48 #define NDS32_SAVE_ALL_REGS 1
50 /* There are two version of Register table for interrupt and exception handler,
51 one for 16-register CPU the other for 32-register CPU. These structures are
52 used for context switching or system call handling. The address of this
53 data can be get from the input argument of the handler functions.
55 For system call handling, r0 to r5 are used to pass arguments. If more
56 arguments are used they are put into the stack and its starting address is
57 in sp. Return value of system call can be put into r0 and r1 upon exit from
58 system call handler. System call ID is in a system register and it can be
59 fetched via intrinsic function. For more information please read ABI and
60 other related documents.
62 For context switching, at least 2 values need to saved in kernel. One is
63 IPC and the other is the stack address of current task. Use intrinsic
64 function to get IPC and the input argument of the handler functions + 8 to
65 get stack address of current task. To do context switching, you replace
66 new_sp with the stack address of new task and replace IPC system register
67 with IPC of new task, then, just return from handler. The context switching
70 /* Register table for exception handler; 32-register version. */
107 /* Register table for exception handler; 16-register version. */
129 /* Use NDS32_REG32_TAB or NDS32_REG16_TAB in your program to
130 access register table. */
406 #if defined(NDS32_EXT_FPU_CONFIG_0)
408 #elif defined(NDS32_EXT_FPU_CONFIG_1)
410 #elif defined(NDS32_EXT_FPU_CONFIG_2)
412 #elif defined(NDS32_EXT_FPU_CONFIG_3)
415 #if __NDS32_DX_REGS__
418 #if __NDS32_EXT_IFC__
422 #if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
429 /* Predefined Vector Definition.
431 For IVIC Mode: 9 to 14 are for hardware interrupt
432 and 15 is for software interrupt.
433 For EVIC Mode: 9 to 72 are for hardware interrupt
434 and software interrupt can be routed to any one of them.
436 You may want to define your hardware interrupts in the following way
437 for easy maintainance.
440 #define MY_HW_IVIC_TIMER NDS32_VECTOR_INTERRUPT_HW0 + 1
441 #define MY_HW_IVIC_USB NDS32_VECTOR_INTERRUPT_HW0 + 3
443 #define MY_HW_EVIC_DMA NDS32_VECTOR_INTERRUPT_HW0 + 2
444 #define MY_HW_EVIC_SWI NDS32_VECTOR_INTERRUPT_HW0 + 10 */
445 #define NDS32_VECTOR_RESET 0
446 #define NDS32_VECTOR_TLB_FILL 1
447 #define NDS32_VECTOR_PTE_NOT_PRESENT 2
448 #define NDS32_VECTOR_TLB_MISC 3
449 #define NDS32_VECTOR_TLB_VLPT_MISS 4
450 #define NDS32_VECTOR_MACHINE_ERROR 5
451 #define NDS32_VECTOR_DEBUG_RELATED 6
452 #define NDS32_VECTOR_GENERAL_EXCEPTION 7
453 #define NDS32_VECTOR_SYSCALL 8
454 #define NDS32_VECTOR_INTERRUPT_HW0 9
455 #define NDS32_VECTOR_INTERRUPT_HW1 10
456 #define NDS32_VECTOR_INTERRUPT_HW2 11
457 #define NDS32_VECTOR_INTERRUPT_HW3 12
458 #define NDS32_VECTOR_INTERRUPT_HW4 13
459 #define NDS32_VECTOR_INTERRUPT_HW5 14
460 #define NDS32_VECTOR_INTERRUPT_HW6 15
461 #define NDS32_VECTOR_SWI 15 /* THIS IS FOR IVIC MODE ONLY */
462 #define NDS32_VECTOR_INTERRUPT_HW7 16
463 #define NDS32_VECTOR_INTERRUPT_HW8 17
464 #define NDS32_VECTOR_INTERRUPT_HW9 18
465 #define NDS32_VECTOR_INTERRUPT_HW10 19
466 #define NDS32_VECTOR_INTERRUPT_HW11 20
467 #define NDS32_VECTOR_INTERRUPT_HW12 21
468 #define NDS32_VECTOR_INTERRUPT_HW13 22
469 #define NDS32_VECTOR_INTERRUPT_HW14 23
470 #define NDS32_VECTOR_INTERRUPT_HW15 24
471 #define NDS32_VECTOR_INTERRUPT_HW16 25
472 #define NDS32_VECTOR_INTERRUPT_HW17 26
473 #define NDS32_VECTOR_INTERRUPT_HW18 27
474 #define NDS32_VECTOR_INTERRUPT_HW19 28
475 #define NDS32_VECTOR_INTERRUPT_HW20 29
476 #define NDS32_VECTOR_INTERRUPT_HW21 30
477 #define NDS32_VECTOR_INTERRUPT_HW22 31
478 #define NDS32_VECTOR_INTERRUPT_HW23 32
479 #define NDS32_VECTOR_INTERRUPT_HW24 33
480 #define NDS32_VECTOR_INTERRUPT_HW25 34
481 #define NDS32_VECTOR_INTERRUPT_HW26 35
482 #define NDS32_VECTOR_INTERRUPT_HW27 36
483 #define NDS32_VECTOR_INTERRUPT_HW28 37
484 #define NDS32_VECTOR_INTERRUPT_HW29 38
485 #define NDS32_VECTOR_INTERRUPT_HW30 39
486 #define NDS32_VECTOR_INTERRUPT_HW31 40
487 #define NDS32_VECTOR_INTERRUPT_HW32 41
488 #define NDS32_VECTOR_INTERRUPT_HW33 42
489 #define NDS32_VECTOR_INTERRUPT_HW34 43
490 #define NDS32_VECTOR_INTERRUPT_HW35 44
491 #define NDS32_VECTOR_INTERRUPT_HW36 45
492 #define NDS32_VECTOR_INTERRUPT_HW37 46
493 #define NDS32_VECTOR_INTERRUPT_HW38 47
494 #define NDS32_VECTOR_INTERRUPT_HW39 48
495 #define NDS32_VECTOR_INTERRUPT_HW40 49
496 #define NDS32_VECTOR_INTERRUPT_HW41 50
497 #define NDS32_VECTOR_INTERRUPT_HW42 51
498 #define NDS32_VECTOR_INTERRUPT_HW43 52
499 #define NDS32_VECTOR_INTERRUPT_HW44 53
500 #define NDS32_VECTOR_INTERRUPT_HW45 54
501 #define NDS32_VECTOR_INTERRUPT_HW46 55
502 #define NDS32_VECTOR_INTERRUPT_HW47 56
503 #define NDS32_VECTOR_INTERRUPT_HW48 57
504 #define NDS32_VECTOR_INTERRUPT_HW49 58
505 #define NDS32_VECTOR_INTERRUPT_HW50 59
506 #define NDS32_VECTOR_INTERRUPT_HW51 60
507 #define NDS32_VECTOR_INTERRUPT_HW52 61
508 #define NDS32_VECTOR_INTERRUPT_HW53 62
509 #define NDS32_VECTOR_INTERRUPT_HW54 63
510 #define NDS32_VECTOR_INTERRUPT_HW55 64
511 #define NDS32_VECTOR_INTERRUPT_HW56 65
512 #define NDS32_VECTOR_INTERRUPT_HW57 66
513 #define NDS32_VECTOR_INTERRUPT_HW58 67
514 #define NDS32_VECTOR_INTERRUPT_HW59 68
515 #define NDS32_VECTOR_INTERRUPT_HW60 69
516 #define NDS32_VECTOR_INTERRUPT_HW61 70
517 #define NDS32_VECTOR_INTERRUPT_HW62 71
518 #define NDS32_VECTOR_INTERRUPT_HW63 72
520 #define NDS32ATTR_RESET(option) __attribute__((reset(option)))
521 #define NDS32ATTR_EXCEPT(type) __attribute__((exception(type)))
522 #define NDS32ATTR_EXCEPTION(type) __attribute__((exception(type)))
523 #define NDS32ATTR_INTERRUPT(type) __attribute__((interrupt(type)))
524 #define NDS32ATTR_ISR(type) __attribute__((interrupt(type)))
526 #endif /* nds32_isr.h */