1 ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 ;; Contributed by Andes Technology Corporation.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
22 ;; ------------------------------------------------------------------------
23 ;; Define N13 pipeline settings.
24 ;; ------------------------------------------------------------------------
26 (define_automaton "nds32_n13_machine")
28 ;; ------------------------------------------------------------------------
30 ;; ------------------------------------------------------------------------
31 ;; F1 - Instruction Fetch First
32 ;; Instruction Tag/Data Arrays
33 ;; ITLB Address Translation
34 ;; Branch Target Buffer Prediction
35 ;; F2 - Instruction Fetch Second
36 ;; Instruction Cache Hit Detection
37 ;; Cache Way Selection
38 ;; Inustruction Alignment
39 ;; I1 - Instruction Issue First / Instruction Decode
40 ;; Instruction Cache Replay Triggering
41 ;; 32/16-Bit Instruction Decode
42 ;; Return Address Stack Prediction
43 ;; I2 - Instruction Issue Second / Register File Access
44 ;; Instruction Issue Logic
45 ;; Register File Access
46 ;; E1 - Instruction Execute First / Address Generation / MAC First
47 ;; Data Access Address generation
49 ;; E2 - Instruction Execute Second / Data Access First / MAC Second /
52 ;; Branch/Jump/Return Resolution
53 ;; Data Tag/Data arrays
54 ;; DTLB address translation
55 ;; Accumulation Operation
56 ;; E3 - Instruction Execute Third / Data Access Second
57 ;; Data Cache Hit Detection
58 ;; Cache Way Selection
60 ;; E4 - Instruction Execute Fourth / Write Back
61 ;; Interruption Resolution
63 ;; Register File Write Back
65 (define_cpu_unit "n13_i1" "nds32_n13_machine")
66 (define_cpu_unit "n13_i2" "nds32_n13_machine")
67 (define_cpu_unit "n13_e1" "nds32_n13_machine")
68 (define_cpu_unit "n13_e2" "nds32_n13_machine")
69 (define_cpu_unit "n13_e3" "nds32_n13_machine")
70 (define_cpu_unit "n13_e4" "nds32_n13_machine")
72 (define_insn_reservation "nds_n13_unknown" 1
73 (and (eq_attr "type" "unknown")
74 (eq_attr "pipeline_model" "n13"))
75 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
77 (define_insn_reservation "nds_n13_misc" 1
78 (and (eq_attr "type" "misc")
79 (eq_attr "pipeline_model" "n13"))
80 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
82 (define_insn_reservation "nds_n13_mmu" 1
83 (and (eq_attr "type" "mmu")
84 (eq_attr "pipeline_model" "n13"))
85 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
87 (define_insn_reservation "nds_n13_alu" 1
88 (and (eq_attr "type" "alu")
89 (eq_attr "pipeline_model" "n13"))
90 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
92 (define_insn_reservation "nds_n13_alu_shift" 1
93 (and (eq_attr "type" "alu_shift")
94 (eq_attr "pipeline_model" "n13"))
95 "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4")
97 (define_insn_reservation "nds_n13_pbsad" 1
98 (and (eq_attr "type" "pbsad")
99 (eq_attr "pipeline_model" "n13"))
100 "n13_i1, n13_i2, n13_e1, n13_e2*2, n13_e3, n13_e4")
102 (define_insn_reservation "nds_n13_pbsada" 1
103 (and (eq_attr "type" "pbsada")
104 (eq_attr "pipeline_model" "n13"))
105 "n13_i1, n13_i2, n13_e1, n13_e2*3, n13_e3, n13_e4")
107 (define_insn_reservation "nds_n13_load" 1
108 (and (match_test "nds32::load_single_p (insn)")
109 (eq_attr "pipeline_model" "n13"))
110 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
112 (define_insn_reservation "nds_n13_store" 1
113 (and (match_test "nds32::store_single_p (insn)")
114 (eq_attr "pipeline_model" "n13"))
115 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
117 (define_insn_reservation "nds_n13_load_multiple_1" 1
118 (and (and (eq_attr "type" "load_multiple")
119 (eq_attr "combo" "1"))
120 (eq_attr "pipeline_model" "n13"))
121 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
123 (define_insn_reservation "nds_n13_load_multiple_2" 1
124 (and (ior (and (eq_attr "type" "load_multiple")
125 (eq_attr "combo" "2"))
126 (match_test "nds32::load_double_p (insn)"))
127 (eq_attr "pipeline_model" "n13"))
128 "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4")
130 (define_insn_reservation "nds_n13_load_multiple_3" 1
131 (and (and (eq_attr "type" "load_multiple")
132 (eq_attr "combo" "3"))
133 (eq_attr "pipeline_model" "n13"))
134 "n13_i1, n13_i2+n13_i2, n13_i1+n13_i2+n13_e1, n13_i2+n13_e1+n13_e2, n13_e1+n13_e2+n13_e3, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
136 (define_insn_reservation "nds_n13_load_multiple_4" 1
137 (and (and (eq_attr "type" "load_multiple")
138 (eq_attr "combo" "4"))
139 (eq_attr "pipeline_model" "n13"))
140 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i2+n13_e1+n13_e2+n13_e3, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
142 (define_insn_reservation "nds_n13_load_multiple_5" 1
143 (and (and (eq_attr "type" "load_multiple")
144 (eq_attr "combo" "5"))
145 (eq_attr "pipeline_model" "n13"))
146 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
148 (define_insn_reservation "nds_n13_load_multiple_6" 1
149 (and (and (eq_attr "type" "load_multiple")
150 (eq_attr "combo" "6"))
151 (eq_attr "pipeline_model" "n13"))
152 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
154 (define_insn_reservation "nds_n13_load_multiple_7" 1
155 (and (and (eq_attr "type" "load_multiple")
156 (eq_attr "combo" "7"))
157 (eq_attr "pipeline_model" "n13"))
158 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*2, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
160 (define_insn_reservation "nds_n13_load_multiple_8" 1
161 (and (and (eq_attr "type" "load_multiple")
162 (eq_attr "combo" "8"))
163 (eq_attr "pipeline_model" "n13"))
164 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
166 (define_insn_reservation "nds_n13_load_multiple_12" 1
167 (and (and (eq_attr "type" "load_multiple")
168 (eq_attr "combo" "12"))
169 (eq_attr "pipeline_model" "n13"))
170 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*7, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
172 (define_insn_reservation "nds_n13_store_multiple_1" 1
173 (and (and (eq_attr "type" "store_multiple")
174 (eq_attr "combo" "1"))
175 (eq_attr "pipeline_model" "n13"))
176 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
178 (define_insn_reservation "nds_n13_store_multiple_2" 1
179 (and (ior (and (eq_attr "type" "store_multiple")
180 (eq_attr "combo" "2"))
181 (match_test "nds32::store_double_p (insn)"))
182 (eq_attr "pipeline_model" "n13"))
183 "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4")
185 (define_insn_reservation "nds_n13_store_multiple_3" 1
186 (and (and (eq_attr "type" "store_multiple")
187 (eq_attr "combo" "3"))
188 (eq_attr "pipeline_model" "n13"))
189 "n13_i1, n13_i2+n13_i2, n13_i1+n13_i2+n13_e1, n13_i2+n13_e1+n13_e2, n13_e1+n13_e2+n13_e3, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
191 (define_insn_reservation "nds_n13_store_multiple_4" 1
192 (and (and (eq_attr "type" "store_multiple")
193 (eq_attr "combo" "4"))
194 (eq_attr "pipeline_model" "n13"))
195 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i2+n13_e1+n13_e2+n13_e3, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
197 (define_insn_reservation "nds_n13_store_multiple_5" 1
198 (and (and (eq_attr "type" "store_multiple")
199 (eq_attr "combo" "5"))
200 (eq_attr "pipeline_model" "n13"))
201 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
203 (define_insn_reservation "nds_n13_store_multiple_6" 1
204 (and (and (eq_attr "type" "store_multiple")
205 (eq_attr "combo" "6"))
206 (eq_attr "pipeline_model" "n13"))
207 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
209 (define_insn_reservation "nds_n13_store_multiple_7" 1
210 (and (and (eq_attr "type" "store_multiple")
211 (eq_attr "combo" "7"))
212 (eq_attr "pipeline_model" "n13"))
213 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*2, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
215 (define_insn_reservation "nds_n13_store_multiple_8" 1
216 (and (and (eq_attr "type" "store_multiple")
217 (eq_attr "combo" "8"))
218 (eq_attr "pipeline_model" "n13"))
219 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
221 (define_insn_reservation "nds_n13_store_multiple_12" 1
222 (and (and (eq_attr "type" "store_multiple")
223 (eq_attr "combo" "12"))
224 (eq_attr "pipeline_model" "n13"))
225 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*7, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
227 ;; The multiplier at E1 takes two cycles.
228 (define_insn_reservation "nds_n13_mul" 1
229 (and (eq_attr "type" "mul")
230 (eq_attr "pipeline_model" "n13"))
231 "n13_i1, n13_i2, n13_e1*2, n13_e2, n13_e3, n13_e4")
233 (define_insn_reservation "nds_n13_mac" 1
234 (and (eq_attr "type" "mac")
235 (eq_attr "pipeline_model" "n13"))
236 "n13_i1, n13_i2, n13_e1*2, n13_e2, n13_e3, n13_e4")
238 ;; The cycles consumed at E2 are 32 - CLZ(abs(Ra)) + 2,
239 ;; so the worst case is 34.
240 (define_insn_reservation "nds_n13_div" 1
241 (and (eq_attr "type" "div")
242 (eq_attr "pipeline_model" "n13"))
243 "n13_i1, n13_i2, n13_e1, n13_e2*34, n13_e3, n13_e4")
245 (define_insn_reservation "nds_n13_branch" 1
246 (and (eq_attr "type" "branch")
247 (eq_attr "pipeline_model" "n13"))
248 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
250 ;; ------------------------------------------------------------------------
251 ;; Comment Notations and Bypass Rules
252 ;; ------------------------------------------------------------------------
255 ;; Load data from the memory and produce the loaded data. The result is
258 ;; There are N micro-operations within an instruction that loads multiple
259 ;; words. The result produced by the M-th micro-operation is sent to
260 ;; consumers. The result is ready at E3.
262 ;; Most load/store instructions can produce an address output if updating
263 ;; the base register is required. The result is ready at E2, which is
265 ;; ALU, ALU_SHIFT, SIMD
266 ;; Compute data in ALU and produce the data. The result is ready at E2.
268 ;; Compute data in the multiply-adder and produce the data. The result
271 ;; Compute data in the divider and produce the data. The result is ready
274 ;; Branch-with-link instructions produces a result containing the return
275 ;; address. The result is ready at E2.
279 ;; General ALU instructions require operands at E2.
281 ;; Some special ALU instructions, such as BSE, BSP and MOVD44, require
283 ;; MUL, DIV, PBSAD, MMU
284 ;; Operands are required at E1.
285 ;; PBSADA_Rt, PBSADA_RaRb
286 ;; Operands Ra and Rb are required at E1, and the operand Rt is required
289 ;; An ALU-SHIFT instruction consists of a shift micro-operation followed
290 ;; by an arithmetic micro-operation. The operand Rb is used by the first
291 ;; micro-operation, and there are some latencies if data dependency occurs.
293 ;; A MAC instruction does multiplication at E1 and does accumulation at E2,
294 ;; so the operand Rt is required at E2, and operands Ra and Rb are required
297 ;; If an instruction requires an address as its input operand, the address
298 ;; is required at E1.
300 ;; A store instruction requires its data at E2.
302 ;; There are N micro-operations within an instruction that stores multiple
303 ;; words. Each M-th micro-operation requires its data at E2.
305 ;; If a branch instruction is conditional, its input data is required at E2.
307 ;; LD -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
310 "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
311 nds_n13_mul, nds_n13_mac, nds_n13_div,\
313 nds_n13_load, nds_n13_store,\
314 nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
315 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
316 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
317 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
318 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
319 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
320 "nds32_n13_load_to_e1_p"
323 ;; LD -> ALU, ALU_SHIFT_Rb, PBSADA_Rt, BR, ST, SMW(N, 1)
326 "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsada, nds_n13_branch, nds_n13_store,\
327 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
328 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
329 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
330 "nds32_n13_load_to_e2_p"
333 ;; LMW(N, N) -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
335 "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
336 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
337 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12"
338 "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
339 nds_n13_mul, nds_n13_mac, nds_n13_div,\
341 nds_n13_load, nds_n13_store,\
342 nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
343 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
344 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
345 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
346 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
347 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
348 "nds32_n13_last_load_to_e1_p")
350 ;; LMW(N, N) -> ALU, ALU_SHIFT_Rb, PBSADA_Rt, BR, ST, SMW(N, 1)
352 "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
353 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
354 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12"
355 "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsada, nds_n13_branch, nds_n13_store,\
356 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
357 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
358 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
359 "nds32_n13_last_load_to_e2_p"
362 ;; LMW(N, N - 1) -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
364 "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
365 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
366 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12"
367 "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
368 nds_n13_mul, nds_n13_mac, nds_n13_div,\
370 nds_n13_load, nds_n13_store,\
371 nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
372 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
373 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
374 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
375 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
376 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
377 "nds32_n13_last_two_load_to_e1_p")
379 ;; ALU, ALU_SHIFT, SIMD, BR, MUL, MAC, DIV, ADDR_OUT
380 ;; -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
382 "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsad, nds_n13_pbsada, nds_n13_branch,\
383 nds_n13_mul, nds_n13_mac, nds_n13_div,\
384 nds_n13_load, nds_n13_store,\
385 nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
386 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
387 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
388 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
389 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
390 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
391 "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
392 nds_n13_mul, nds_n13_mac, nds_n13_div,\
394 nds_n13_load, nds_n13_store,\
395 nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
396 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
397 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
398 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
399 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
400 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
401 "nds32_n13_e2_to_e1_p")