gcc/config/powerpcspe/powerpcspe-modes.def

   1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
   2    Copyright (C) 2002-2018 Free Software Foundation, Inc.
   3    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* IBM 128-bit floating point.  IFmode and KFmode use the fractional float
  22    support in order to declare 3 128-bit floating point types.  */
  23 FRACTIONAL_FLOAT_MODE (IF, 106, 16, ibm_extended_format);
  24
  25 /* Explicit IEEE 128-bit floating point.  */
  26 FRACTIONAL_FLOAT_MODE (KF, 113, 16, ieee_quad_format);
  27
  28 /* 128-bit floating point.  ABI_V4 uses IEEE quad, AIX/Darwin
  29    adjust this in rs6000_option_override_internal.  */
  30 FLOAT_MODE (TF, 16, ieee_quad_format);
  31
  32 /* Add any extra modes needed to represent the condition code.
  33
  34    For the RS/6000, we need separate modes when unsigned (logical) comparisons
  35    are being done and we need a separate mode for floating-point.  We also
  36    use a mode for the case when we are comparing the results of two
  37    comparisons, as then only the EQ bit is valid in the register.  */
  38
  39 CC_MODE (CCUNS);
  40 CC_MODE (CCFP);
  41 CC_MODE (CCEQ);
  42
  43 /* Vector modes.  */
  44 VECTOR_MODES (INT, 8);        /*       V8QI  V4HI V2SI */
  45 VECTOR_MODES (INT, 16);       /* V16QI V8HI  V4SI V2DI */
  46 VECTOR_MODES (INT, 32);       /* V32QI V16HI V8SI V4DI */
  47 VECTOR_MODE (INT, DI, 1);
  48 VECTOR_MODE (INT, TI, 1);
  49 VECTOR_MODES (FLOAT, 8);      /*             V4HF V2SF */
  50 VECTOR_MODES (FLOAT, 16);     /*       V8HF  V4SF V2DF */
  51 VECTOR_MODES (FLOAT, 32);     /*       V16HF V8SF V4DF */
  52
  53 /* Replacement for TImode that only is allowed in GPRs.  We also use PTImode
  54    for quad memory atomic operations to force getting an even/odd register
  55    combination.  */
  56 PARTIAL_INT_MODE (TI, 128, PTI);