| blob | 82afd7fee50402d4286e09785a267d5df19a441b |
1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987-2014 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
42 #if SWITCHABLE_TARGET
44 #endif
50 rtx);
53 rtx);
58 rtx);
72 /* Return a constant integer mask value of mode MODE with BITSIZE ones
73 followed by BITPOS zeros, or the complement of that if COMPLEMENT.
74 The mask is truncated if necessary to the width of mode MODE. The
75 mask is zero-extended if BITSIZE+BITPOS is too small for MODE. */
79 {
80 return immed_wide_int_const
83 }
85 /* Test whether a value is zero of a power of two. */
86 #define EXACT_POWER_OF_2_OR_ZERO_P(x) \
87 (((x) & ((x) - (unsigned HOST_WIDE_INT) 1)) == 0)
89 struct init_expmed_rtl
90 {
91 rtx reg;
92 rtx plus;
93 rtx neg;
94 rtx mult;
95 rtx sdiv;
96 rtx udiv;
97 rtx sdiv_32;
98 rtx smod_32;
99 rtx wide_mult;
100 rtx wide_lshr;
101 rtx wide_trunc;
102 rtx shift;
103 rtx shift_mult;
104 rtx shift_add;
105 rtx shift_sub0;
106 rtx shift_sub1;
107 rtx zext;
108 rtx trunc;
112 };
114 static void
117 {
119 rtx which;
124 /* Most partial integers have a precision less than the "full"
125 integer it requires for storage. In case one doesn't, for
126 comparison purposes here, reduce the bit size by one in that
127 case. */
130 to_size --;
133 from_size --;
135 /* Assume cost of zero-extend and sign-extend is the same. */
140 }
142 static void
145 {
180 {
185 }
189 {
197 }
200 {
204 }
206 {
209 {
219 }
220 }
221 }
223 void
225 {
232 {
235 }
237 /* Avoid using hard regs in ways which may be unsupported. */
258 {
275 }
278 {
281 }
282 else
304 }
306 /* Return an rtx representing minus the value of X.
307 MODE is the intended mode of the result,
308 useful if X is a CONST_INT. */
310 rtx
312 {
319 }
321 /* Adjust bitfield memory MEM so that it points to the first unit of mode
322 MODE that contains a bitfield of size BITSIZE at bit position BITNUM.
323 If MODE is BLKmode, return a reference to every byte in the bitfield.
324 Set *NEW_BITNUM to the bit position of the field within the new memory. */
326 static rtx
331 {
333 {
339 }
340 else
341 {
346 }
347 }
349 /* The caller wants to perform insertion or extraction PATTERN on a
350 bitfield of size BITSIZE at BITNUM bits into memory operand OP0.
351 BITREGION_START and BITREGION_END are as for store_bit_field
352 and FIELDMODE is the natural mode of the field.
354 Search for a mode that is compatible with the memory access
355 restrictions and (where applicable) with a register insertion or
356 extraction. Return the new memory on success, storing the adjusted
357 bit position in *NEW_BITNUM. Return null otherwise. */
359 static rtx
362 HOST_WIDE_INT bitnum,
367 {
373 {
374 /* We can use a memory in BEST_MODE. See whether this is true for
375 any wider modes. All other things being equal, we prefer to
376 use the widest mode possible because it tends to expose more
377 CSE opportunities. */
379 {
380 /* Limit the search to the mode required by the corresponding
381 register insertion or extraction instruction, if any. */
383 extraction_insn insn;
386 fieldmode))
393 }
395 new_bitnum);
396 }
398 }
400 /* Return true if a bitfield of size BITSIZE at bit number BITNUM within
401 a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg
402 offset is then BITNUM / BITS_PER_UNIT. */
404 static bool
408 {
413 else
415 }
417 /* Return true if -fstrict-volatile-bitfields applies to an access of OP0
418 containing BITSIZE bits starting at BITNUM, with field mode FIELDMODE.
419 Return false if the access would touch memory outside the range
420 BITREGION_START to BITREGION_END for conformance to the C++ memory
421 model. */
423 static bool
429 {
432 /* -fstrict-volatile-bitfields must be enabled and we must have a
433 volatile MEM. */
439 /* Non-integral modes likely only happen with packed structures.
440 Punt. */
444 /* The bit size must not be larger than the field mode, and
445 the field mode must not be larger than a word. */
449 /* Check for cases of unaligned fields that must be split. */
451 || (STRICT_ALIGNMENT
455 /* Check for cases where the C++ memory model applies. */
462 }
464 /* Return true if OP is a memory and if a bitfield of size BITSIZE at
465 bit number BITNUM can be treated as a simple value of mode MODE. */
467 static bool
470 {
477 }
478 \f
479 /* Try to use instruction INSV to store VALUE into a field of OP0.
480 BITSIZE and BITNUM are as for store_bit_field. */
482 static bool
486 rtx value)
487 {
489 rtx value1;
500 /* Get a reference to the first byte of the field. */
503 else
504 {
505 /* Convert from counting within OP0 to counting in OP_MODE. */
509 /* If xop0 is a register, we need it in OP_MODE
510 to make it acceptable to the format of insv. */
512 /* We can't just change the mode, because this might clobber op0,
513 and we will need the original value of op0 if insv fails. */
517 }
519 /* If the destination is a paradoxical subreg such that we need a
520 truncate to the inner mode, perform the insertion on a temporary and
521 truncate the result to the original destination. Note that we can't
522 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
523 X) 0)) is (reg:N X). */
527 op_mode))
528 {
533 }
535 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
536 "backwards" from the size of the unit we are inserting into.
537 Otherwise, we count bits from the most significant on a
538 BYTES/BITS_BIG_ENDIAN machine. */
543 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
546 {
548 {
549 /* Optimization: Don't bother really extending VALUE
550 if it has all the bits we will actually use. However,
551 if we must narrow it, be sure we do it correctly. */
554 {
555 rtx tmp;
561 value1),
564 }
565 else
567 }
570 else
571 /* Parse phase is supposed to make VALUE's data type
572 match that of the component reference, which is a type
573 at least as wide as the field; so VALUE should have
574 a mode that corresponds to that type. */
576 }
583 {
587 }
590 }
592 /* A subroutine of store_bit_field, with the same arguments. Return true
593 if the operation could be implemented.
595 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
596 no other way of implementing the operation. If FALLBACK_P is false,
597 return false instead. */
599 static bool
606 {
608 rtx orig_value;
611 {
612 /* The following line once was done only if WORDS_BIG_ENDIAN,
613 but I think that is a mistake. WORDS_BIG_ENDIAN is
614 meaningful at a much higher level; when structures are copied
615 between memory and regs, the higher-numbered regs
616 always get higher addresses. */
621 /* Paradoxical subregs need special handling on big endian machines. */
623 {
630 }
631 else
636 }
638 /* No action is needed if the target is a register and if the field
639 lies completely outside that register. This can occur if the source
640 code contains an out-of-bounds access to a small array. */
644 /* Use vec_set patterns for inserting parts of vectors whenever
645 available. */
652 {
664 }
666 /* If the target is a register, overwriting the entire object, or storing
667 a full-word or multi-word field can be done with just a SUBREG. */
672 {
673 /* Use the subreg machinery either to narrow OP0 to the required
674 words or to cope with mode punning between equal-sized modes.
675 In the latter case, use subreg on the rhs side, not lhs. */
676 rtx sub;
679 {
682 {
685 }
686 }
687 else
688 {
692 {
695 }
696 }
697 }
699 /* If the target is memory, storing any naturally aligned field can be
700 done with a simple store. For targets that support fast unaligned
701 memory, any naturally sized, unit aligned field can be done directly. */
703 {
707 }
709 /* Make sure we are playing with integral modes. Pun with subregs
710 if we aren't. This must come after the entire register case above,
711 since that case is valid for any mode. The following cases are only
712 valid for integral modes. */
713 {
716 {
719 else
720 {
723 }
724 }
725 }
727 /* Storing an lsb-aligned field in a register
728 can be done with a movstrict instruction. */
734 {
741 {
742 /* Else we've got some float mode source being extracted into
743 a different float mode destination -- this combination of
744 subregs results in Severe Tire Damage. */
749 }
753 {
757 /* Shrink the source operand to FIELDMODE. */
761 }
762 }
764 /* Handle fields bigger than a word. */
767 {
768 /* Here we transfer the words of the field
769 in the order least significant first.
770 This is because the most significant word is the one which may
771 be less than full.
772 However, only do that if the value is not BLKmode. */
779 /* This is the mode we must force value to, so that there will be enough
780 subwords to extract. Note that fieldmode will often (always?) be
781 VOIDmode, because that is what store_field uses to indicate that this
782 is a bit field, but passing VOIDmode to operand_subword_force
783 is not allowed. */
790 {
791 /* If I is 0, use the low-order word in both field and target;
792 if I is 1, use the next to lowest word; and so on. */
806 /* If the remaining chunk doesn't have full wordsize we have
807 to make sure that for big endian machines the higher order
808 bits are used. */
811 value_word,
815 OPTAB_LIB_WIDEN);
820 word_mode,
822 {
825 }
826 }
828 }
830 /* If VALUE has a floating-point or complex mode, access it as an
831 integer of the corresponding size. This can occur on a machine
832 with 64 bit registers that uses SFmode for float. It can also
833 occur for unaligned float or complex fields. */
838 {
841 }
843 /* If OP0 is a multi-word register, narrow it to the affected word.
844 If the region spans two words, defer to store_split_bit_field. */
846 {
852 {
859 }
860 }
862 /* From here on we can assume that the field to be stored in fits
863 within a word. If the destination is a register, it too fits
864 in a word. */
866 extraction_insn insv;
870 fieldmode)
874 /* If OP0 is a memory, try copying it to a register and seeing if a
875 cheap register alternative is available. */
877 {
879 fieldmode)
885 /* Try loading part of OP0 into a register, inserting the bitfield
886 into that, and then copying the result back to OP0. */
892 {
897 {
900 }
902 }
903 }
911 }
913 /* Generate code to store value from rtx VALUE
914 into a bit-field within structure STR_RTX
915 containing BITSIZE bits starting at bit BITNUM.
917 BITREGION_START is bitpos of the first bitfield in this region.
918 BITREGION_END is the bitpos of the ending bitfield in this region.
919 These two fields are 0, if the C++ memory model does not apply,
920 or we are not interested in keeping track of bitfield regions.
922 FIELDMODE is the machine-mode of the FIELD_DECL node for this field. */
924 void
930 rtx value)
931 {
932 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
935 {
936 /* Storing any naturally aligned field can be done with a simple
937 store. For targets that support fast unaligned memory, any
938 naturally sized, unit aligned field can be done directly. */
940 {
944 }
945 else
946 {
949 /* Explicitly override the C/C++ memory model; ignore the
950 bit range so that we can do the access in the mode mandated
951 by -fstrict-volatile-bitfields instead. */
953 }
956 }
958 /* Under the C++0x memory model, we must not touch bits outside the
959 bit region. Adjust the address to start at the beginning of the
960 bit region. */
962 {
978 }
984 }
985 \f
986 /* Use shifts and boolean operations to store VALUE into a bit field of
987 width BITSIZE in OP0, starting at bit BITNUM. */
989 static void
994 rtx value)
995 {
996 /* There is a case not handled here:
997 a structure with a known alignment of just a halfword
998 and a field split across two aligned halfwords within the structure.
999 Or likewise a structure with a known alignment of just a byte
1000 and a field split across two bytes.
1001 Such cases are not supposed to be able to occur. */
1004 {
1013 {
1014 /* The only way this should occur is if the field spans word
1015 boundaries. */
1019 }
1022 }
1025 }
1027 /* Helper function for store_fixed_bit_field, stores
1028 the bit field always using the MODE of OP0. */
1030 static void
1033 rtx value)
1034 {
1036 rtx temp;
1043 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1044 for invalid input, such as f5 from gcc.dg/pr48335-2.c. */
1047 /* BITNUM is the distance between our msb
1048 and that of the containing datum.
1049 Convert it to the distance from the lsb. */
1052 /* Now BITNUM is always the distance between our lsb
1053 and that of OP0. */
1055 /* Shift VALUE left by BITNUM bits. If VALUE is not constant,
1056 we must first convert its mode to MODE. */
1059 {
1074 }
1075 else
1076 {
1090 }
1092 /* Now clear the chosen bits in OP0,
1093 except that if VALUE is -1 we need not bother. */
1094 /* We keep the intermediates in registers to allow CSE to combine
1095 consecutive bitfield assignments. */
1100 {
1105 }
1107 /* Now logical-or VALUE into OP0, unless it is zero. */
1110 {
1114 }
1117 {
1120 }
1121 }
1122 \f
1123 /* Store a bit field that is split across multiple accessible memory objects.
1125 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1126 BITSIZE is the field width; BITPOS the position of its first bit
1127 (within the word).
1128 VALUE is the value to store.
1130 This does not yet handle fields wider than BITS_PER_WORD. */
1132 static void
1137 rtx value)
1138 {
1142 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1143 much at a time. */
1146 else
1149 /* If OP0 is a memory with a mode, then UNIT must not be larger than
1150 OP0's mode as well. Otherwise, store_fixed_bit_field will call us
1151 again, and we will mutually recurse forever. */
1155 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1156 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1157 that VALUE might be a floating-point constant. */
1159 {
1164 else
1169 }
1172 {
1181 /* When region of bytes we can touch is restricted, decrease
1182 UNIT close to the end of the region as needed. If op0 is a REG
1183 or SUBREG of REG, don't do this, as there can't be data races
1184 on a register and we can expand shorter code in some cases. */
1190 {
1193 }
1195 /* THISSIZE must not overrun a word boundary. Otherwise,
1196 store_fixed_bit_field will call us again, and we will mutually
1197 recurse forever. */
1202 {
1203 /* Fetch successively less significant portions. */
1208 else
1209 {
1211 /* The args are chosen so that the last part includes the
1212 lsb. Give extract_bit_field the value it needs (with
1213 endianness compensation) to fetch the piece we want. */
1217 }
1218 }
1219 else
1220 {
1221 /* Fetch successively more significant portions. */
1226 else
1229 }
1231 /* If OP0 is a register, then handle OFFSET here.
1233 When handling multiword bitfields, extract_bit_field may pass
1234 down a word_mode SUBREG of a larger REG for a bitfield that actually
1235 crosses a word boundary. Thus, for a SUBREG, we must find
1236 the current word starting from the base register. */
1238 {
1244 else
1248 }
1250 {
1254 else
1258 }
1259 else
1262 /* OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
1263 it is just an out-of-bounds access. Ignore it. */
1268 }
1269 }
1270 \f
1271 /* A subroutine of extract_bit_field_1 that converts return value X
1272 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1273 to extract_bit_field. */
1275 static rtx
1278 {
1282 /* If the x mode is not a scalar integral, first convert to the
1283 integer mode of that size and then access it as a floating-point
1284 value via a SUBREG. */
1286 {
1293 }
1296 }
1298 /* Try to use an ext(z)v pattern to extract a field from OP0.
1299 Return the extracted value on success, otherwise return null.
1300 EXT_MODE is the mode of the extraction and the other arguments
1301 are as for extract_bit_field. */
1303 static rtx
1309 {
1320 /* Get a reference to the first byte of the field. */
1323 else
1324 {
1325 /* Convert from counting within OP0 to counting in EXT_MODE. */
1329 /* If op0 is a register, we need it in EXT_MODE to make it
1330 acceptable to the format of ext(z)v. */
1335 }
1337 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1338 "backwards" from the size of the unit we are extracting from.
1339 Otherwise, we count bits from the most significant on a
1340 BYTES/BITS_BIG_ENDIAN machine. */
1349 {
1350 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1351 between the mode of the extraction (word_mode) and the target
1352 mode. Instead, create a temporary and use convert_move to set
1353 the target. */
1356 {
1361 }
1362 else
1364 }
1371 {
1378 }
1380 }
1382 /* A subroutine of extract_bit_field, with the same arguments.
1383 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1384 if we can find no other means of implementing the operation.
1385 if FALLBACK_P is false, return NULL instead. */
1387 static rtx
1392 {
1401 {
1404 }
1406 /* If we have an out-of-bounds access to a register, just return an
1407 uninitialized register of the required mode. This can occur if the
1408 source code contains an out-of-bounds access to a small array. */
1416 {
1417 /* We're trying to extract a full register from itself. */
1419 }
1421 /* See if we can get a better vector mode before extracting. */
1425 {
1438 else
1447 }
1449 /* Use vec_extract patterns for extracting parts of vectors whenever
1450 available. */
1456 {
1467 {
1472 }
1473 }
1475 /* Make sure we are playing with integral modes. Pun with subregs
1476 if we aren't. */
1477 {
1480 {
1484 {
1487 /* If we got a SUBREG, force it into a register since we
1488 aren't going to be able to do another SUBREG on it. */
1491 }
1493 {
1496 MODE_INT);
1502 }
1503 else
1504 {
1509 }
1510 }
1511 }
1513 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1514 If that's wrong, the solution is to test for it and set TARGET to 0
1515 if needed. */
1517 /* Get the mode of the field to use for atomic access or subreg
1518 conversion. */
1521 {
1526 }
1529 /* Extraction of a full MODE1 value can be done with a subreg as long
1530 as the least significant bit of the value is the least significant
1531 bit of either OP0 or a word of OP0. */
1536 {
1541 }
1543 /* Extraction of a full MODE1 value can be done with a load as long as
1544 the field is on a byte boundary and is sufficiently aligned. */
1546 {
1549 }
1551 /* Handle fields bigger than a word. */
1554 {
1555 /* Here we transfer the words of the field
1556 in the order least significant first.
1557 This is because the most significant word is the one which may
1558 be less than full. */
1568 /* Indicate for flow that the entire target reg is being set. */
1573 {
1574 /* If I is 0, use the low-order word in both field and target;
1575 if I is 1, use the next to lowest word; and so on. */
1576 /* Word number in TARGET to use. */
1577 unsigned int wordnum
1578 = (backwards
1581 /* Offset from start of field in OP0. */
1588 rtx result_part
1596 {
1599 }
1603 }
1606 {
1607 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1608 need to be zero'd out. */
1610 {
1615 emit_move_insn
1619 const0_rtx);
1620 }
1622 }
1624 /* Signed bit field: sign-extend with two arithmetic shifts. */
1629 }
1631 /* If OP0 is a multi-word register, narrow it to the affected word.
1632 If the region spans two words, defer to extract_split_bit_field. */
1634 {
1639 {
1644 }
1645 }
1647 /* From here on we know the desired field is smaller than a word.
1648 If OP0 is a register, it too fits within a word. */
1650 extraction_insn extv;
1652 /* ??? We could limit the structure size to the part of OP0 that
1653 contains the field, with appropriate checks for endianness
1654 and TRULY_NOOP_TRUNCATION. */
1657 tmode))
1658 {
1661 tmode);
1664 }
1666 /* If OP0 is a memory, try copying it to a register and seeing if a
1667 cheap register alternative is available. */
1669 {
1671 tmode))
1672 {
1676 tmode);
1679 }
1683 /* Try loading part of OP0 into a register and extracting the
1684 bitfield from that. */
1689 {
1697 }
1698 }
1703 /* Find a correspondingly-sized integer field, so we can apply
1704 shifts and masks to it. */
1708 /* Should probably push op0 out to memory and then do a load. */
1714 }
1716 /* Generate code to extract a byte-field from STR_RTX
1717 containing BITSIZE bits, starting at BITNUM,
1718 and put it in TARGET if possible (if TARGET is nonzero).
1719 Regardless of TARGET, we return the rtx for where the value is placed.
1721 STR_RTX is the structure containing the byte (a REG or MEM).
1722 UNSIGNEDP is nonzero if this is an unsigned bit field.
1723 MODE is the natural mode of the field value once extracted.
1724 TMODE is the mode the caller would like the value to have;
1725 but the value may be returned with type MODE instead.
1727 If a TARGET is specified and we can store in it at no extra cost,
1728 we do so, and return TARGET.
1729 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1730 if they are equally easy. */
1732 rtx
1736 {
1739 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
1744 else
1748 {
1749 rtx result;
1751 /* Extraction of a full MODE1 value can be done with a load as long as
1752 the field is on a byte boundary and is sufficiently aligned. */
1756 else
1757 {
1762 }
1765 }
1769 }
1770 \f
1771 /* Use shifts and boolean operations to extract a field of BITSIZE bits
1772 from bit BITNUM of OP0.
1774 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1775 If TARGET is nonzero, attempts to store the value there
1776 and return TARGET, but this is not guaranteed.
1777 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1779 static rtx
1784 {
1786 {
1787 enum machine_mode mode
1792 /* The only way this should occur is if the field spans word
1793 boundaries. */
1797 }
1801 }
1803 /* Helper function for extract_fixed_bit_field, extracts
1804 the bit field always using the MODE of OP0. */
1806 static rtx
1811 {
1815 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1816 for invalid input, such as extract equivalent of f5 from
1817 gcc.dg/pr48335-2.c. */
1820 /* BITNUM is the distance between our msb and that of OP0.
1821 Convert it to the distance from the lsb. */
1824 /* Now BITNUM is always the distance between the field's lsb and that of OP0.
1825 We have reduced the big-endian case to the little-endian case. */
1828 {
1830 {
1831 /* If the field does not already start at the lsb,
1832 shift it so it does. */
1833 /* Maybe propagate the target for the shift. */
1838 }
1839 /* Convert the value to the desired mode. */
1843 /* Unless the msb of the field used to be the msb when we shifted,
1844 mask out the upper bits. */
1851 }
1853 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1854 then arithmetic-shift its lsb to the lsb of the word. */
1857 /* Find the narrowest integer mode that contains the field. */
1862 {
1865 }
1871 {
1873 /* Maybe propagate the target for the shift. */
1876 }
1880 }
1882 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1883 VALUE << BITPOS. */
1885 static rtx
1888 {
1890 }
1891 \f
1892 /* Extract a bit field that is split across two words
1893 and return an RTX for the result.
1895 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1896 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1897 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1899 static rtx
1902 {
1908 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1909 much at a time. */
1912 else
1916 {
1925 /* THISSIZE must not overrun a word boundary. Otherwise,
1926 extract_fixed_bit_field will call us again, and we will mutually
1927 recurse forever. */
1931 /* If OP0 is a register, then handle OFFSET here.
1933 When handling multiword bitfields, extract_bit_field may pass
1934 down a word_mode SUBREG of a larger REG for a bitfield that actually
1935 crosses a word boundary. Thus, for a SUBREG, we must find
1936 the current word starting from the base register. */
1938 {
1943 }
1945 {
1948 }
1949 else
1952 /* Extract the parts in bit-counting order,
1953 whose meaning is determined by BYTES_PER_UNIT.
1954 OFFSET is in UNITs, and UNIT is in bits. */
1959 /* Shift this part into place for the result. */
1961 {
1965 }
1966 else
1967 {
1971 }
1975 else
1976 /* Combine the parts with bitwise or. This works
1977 because we extracted each part as an unsigned bit field. */
1979 OPTAB_LIB_WIDEN);
1982 }
1984 /* Unsigned bit field: we are done. */
1987 /* Signed bit field: sign-extend with two arithmetic shifts. */
1992 }
1993 \f
1994 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
1995 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
1996 MODE, fill the upper bits with zeros. Fail if the layout of either
1997 mode is unknown (as for CC modes) or if the extraction would involve
1998 unprofitable mode punning. Return the value on success, otherwise
1999 return null.
2001 This is different from gen_lowpart* in these respects:
2003 - the returned value must always be considered an rvalue
2005 - when MODE is wider than SRC_MODE, the extraction involves
2006 a zero extension
2008 - when MODE is smaller than SRC_MODE, the extraction involves
2009 a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
2011 In other words, this routine performs a computation, whereas the
2012 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2013 operations. */
2015 rtx
2017 {
2024 {
2025 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2026 fails, it will happily create (subreg (symbol_ref)) or similar
2027 invalid SUBREGs. */
2039 }
2046 {
2050 }
2066 }
2067 \f
2068 /* Add INC into TARGET. */
2070 void
2072 {
2078 }
2080 /* Subtract DEC from TARGET. */
2082 void
2084 {
2090 }
2091 \f
2092 /* Output a shift instruction for expression code CODE,
2093 with SHIFTED being the rtx for the value to shift,
2094 and AMOUNT the rtx for the amount to shift by.
2095 Store the result in the rtx TARGET, if that is convenient.
2096 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2097 Return the rtx for where the value is. */
2099 static rtx
2102 {
2121 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2122 shift amount is a vector, use the vector/vector shift patterns. */
2124 {
2130 }
2132 /* Previously detected shift-counts computed by NEGATE_EXPR
2133 and shifted in the other direction; but that does not work
2134 on all machines. */
2137 {
2148 }
2150 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
2151 prefer left rotation, if op1 is from bitsize / 2 + 1 to
2152 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
2153 amount instead. */
2158 {
2162 }
2167 /* Check whether its cheaper to implement a left shift by a constant
2168 bit count by a sequence of additions. */
2177 {
2180 {
2184 }
2186 }
2189 {
2196 else
2200 {
2201 /* Widening does not work for rotation. */
2205 {
2206 /* If we have been unable to open-code this by a rotation,
2207 do it as the IOR of two shifts. I.e., to rotate A
2208 by N bits, compute
2209 (A << N) | ((unsigned) A >> ((-N) & (C - 1)))
2210 where C is the bitsize of A.
2212 It is theoretically possible that the target machine might
2213 not be able to perform either shift and hence we would
2214 be making two libcalls rather than just the one for the
2215 shift (similarly if IOR could not be done). We will allow
2216 this extremely unlikely lossage to avoid complicating the
2217 code below. */
2221 rtx temp1;
2229 else
2230 {
2231 other_amount
2235 other_amount
2238 }
2249 }
2254 }
2260 /* Do arithmetic shifts.
2261 Also, if we are going to widen the operand, we can just as well
2262 use an arithmetic right-shift instead of a logical one. */
2265 {
2268 /* If trying to widen a log shift to an arithmetic shift,
2269 don't accept an arithmetic shift of the same size. */
2273 /* Arithmetic shift */
2278 }
2280 /* We used to try extzv here for logical right shifts, but that was
2281 only useful for one machine, the VAX, and caused poor code
2282 generation there for lshrdi3, so the code was deleted and a
2283 define_expand for lshrsi3 was added to vax.md. */
2284 }
2288 }
2290 /* Output a shift instruction for expression code CODE,
2291 with SHIFTED being the rtx for the value to shift,
2292 and AMOUNT the amount to shift by.
2293 Store the result in the rtx TARGET, if that is convenient.
2294 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2295 Return the rtx for where the value is. */
2297 rtx
2300 {
2303 }
2305 /* Output a shift instruction for expression code CODE,
2306 with SHIFTED being the rtx for the value to shift,
2307 and AMOUNT the tree for the amount to shift by.
2308 Store the result in the rtx TARGET, if that is convenient.
2309 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2310 Return the rtx for where the value is. */
2312 rtx
2315 {
2318 }
2320 \f
2321 /* Indicates the type of fixup needed after a constant multiplication.
2322 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2323 the result should be negated, and ADD_VARIANT means that the
2324 multiplicand should be added to the result. */
2338 /* Compute and return the best algorithm for multiplying by T.
2339 The algorithm must cost less than cost_limit
2340 If retval.cost >= COST_LIMIT, no algorithm was found and all
2341 other field of the returned struct are undefined.
2342 MODE is the machine mode of the multiplication. */
2344 static void
2347 {
2362 /* Indicate that no algorithm is yet found. If no algorithm
2363 is found, this value will be returned and indicate failure. */
2371 /* Be prepared for vector modes. */
2378 /* Restrict the bits of "t" to the multiplication's mode. */
2381 /* t == 1 can be done in zero cost. */
2383 {
2389 }
2391 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2392 fail now. */
2394 {
2397 else
2398 {
2404 }
2405 }
2407 /* We'll be needing a couple extra algorithm structures now. */
2413 /* Compute the hash index. */
2416 /* See if we already know what to do for T. */
2423 {
2427 {
2428 /* The cache tells us that it's impossible to synthesize
2429 multiplication by T within entry_ptr->cost. */
2431 /* COST_LIMIT is at least as restrictive as the one
2432 recorded in the hash table, in which case we have no
2433 hope of synthesizing a multiplication. Just
2434 return. */
2437 /* If we get here, COST_LIMIT is less restrictive than the
2438 one recorded in the hash table, so we may be able to
2439 synthesize a multiplication. Proceed as if we didn't
2440 have the cache entry. */
2441 }
2442 else
2443 {
2445 /* The cached algorithm shows that this multiplication
2446 requires more cost than COST_LIMIT. Just return. This
2447 way, we don't clobber this cache entry with
2448 alg_impossible but retain useful information. */
2454 {
2474 }
2475 }
2476 }
2478 /* If we have a group of zero bits at the low-order part of T, try
2479 multiplying by the remaining bits and then doing a shift. */
2482 {
2483 do_alg_shift:
2486 {
2488 /* The function expand_shift will choose between a shift and
2489 a sequence of additions, so the observed cost is given as
2490 MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). */
2501 {
2507 }
2509 /* See if treating ORIG_T as a signed number yields a better
2510 sequence. Try this sequence only for a negative ORIG_T
2511 as it would be useless for a non-negative ORIG_T. */
2513 {
2514 /* Shift ORIG_T as follows because a right shift of a
2515 negative-valued signed type is implementation
2516 defined. */
2518 /* The function expand_shift will choose between a shift
2519 and a sequence of additions, so the observed cost is
2520 given as MIN (m * add_cost(speed, mode),
2521 shift_cost(speed, mode, m)). */
2532 {
2538 }
2539 }
2540 }
2543 }
2545 /* If we have an odd number, add or subtract one. */
2547 {
2550 do_alg_addsub_t_m2:
2552 ;
2553 /* If T was -1, then W will be zero after the loop. This is another
2554 case where T ends with ...111. Handling this with (T + 1) and
2555 subtract 1 produces slightly better code and results in algorithm
2556 selection much faster than treating it like the ...0111 case
2557 below. */
2560 /* Reject the case where t is 3.
2561 Thus we prefer addition in that case. */
2563 {
2564 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2574 {
2580 }
2581 }
2582 else
2583 {
2584 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2594 {
2600 }
2601 }
2603 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2604 quickly with a - a * n for some appropriate constant n. */
2607 {
2617 {
2623 }
2624 }
2628 }
2630 /* Look for factors of t of the form
2631 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2632 If we find such a factor, we can multiply by t using an algorithm that
2633 multiplies by q, shift the result by m and add/subtract it to itself.
2635 We search for large factors first and loop down, even if large factors
2636 are less probable than small; if we find a large factor we will find a
2637 good sequence quickly, and therefore be able to prune (by decreasing
2638 COST_LIMIT) the search. */
2640 do_alg_addsub_factor:
2642 {
2648 {
2649 /* If the target has a cheap shift-and-add instruction use
2650 that in preference to a shift insn followed by an add insn.
2651 Assume that the shift-and-add is "atomic" with a latency
2652 equal to its cost, otherwise assume that on superscalar
2653 hardware the shift may be executed concurrently with the
2654 earlier steps in the algorithm. */
2657 {
2660 }
2661 else
2673 {
2679 }
2680 /* Other factors will have been taken care of in the recursion. */
2682 }
2687 {
2688 /* If the target has a cheap shift-and-subtract insn use
2689 that in preference to a shift insn followed by a sub insn.
2690 Assume that the shift-and-sub is "atomic" with a latency
2691 equal to it's cost, otherwise assume that on superscalar
2692 hardware the shift may be executed concurrently with the
2693 earlier steps in the algorithm. */
2696 {
2699 }
2700 else
2712 {
2718 }
2720 }
2721 }
2725 /* Try shift-and-add (load effective address) instructions,
2726 i.e. do a*3, a*5, a*9. */
2728 {
2729 do_alg_add_t2_m:
2734 {
2743 {
2749 }
2750 }
2754 do_alg_sub_t2_m:
2759 {
2768 {
2774 }
2775 }
2778 }
2780 done:
2781 /* If best_cost has not decreased, we have not found any algorithm. */
2783 {
2784 /* We failed to find an algorithm. Record alg_impossible for
2785 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2786 we are asked to find an algorithm for T within the same or
2787 lower COST_LIMIT, we can immediately return to the
2788 caller. */
2795 }
2797 /* Cache the result. */
2799 {
2806 }
2808 /* If we are getting a too long sequence for `struct algorithm'
2809 to record, make this search fail. */
2813 /* Copy the algorithm from temporary space to the space at alg_out.
2814 We avoid using structure assignment because the majority of
2815 best_alg is normally undefined, and this is a critical function. */
2822 }
2823 \f
2824 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2825 Try three variations:
2827 - a shift/add sequence based on VAL itself
2828 - a shift/add sequence based on -VAL, followed by a negation
2829 - a shift/add sequence based on VAL - 1, followed by an addition.
2831 Return true if the cheapest of these cost less than MULT_COST,
2832 describing the algorithm in *ALG and final fixup in *VARIANT. */
2834 static bool
2838 {
2844 /* Fail quickly for impossible bounds. */
2848 /* Ensure that mult_cost provides a reasonable upper bound.
2849 Any constant multiplication can be performed with less
2850 than 2 * bits additions. */
2860 /* This works only if the inverted value actually fits in an
2861 `unsigned int' */
2863 {
2866 {
2869 }
2870 else
2871 {
2874 }
2881 }
2883 /* This proves very useful for division-by-constant. */
2886 {
2889 }
2890 else
2891 {
2894 }
2903 }
2905 /* A subroutine of expand_mult, used for constant multiplications.
2906 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2907 convenient. Use the shift/add sequence described by ALG and apply
2908 the final fixup specified by VARIANT. */
2910 static rtx
2914 {
2915 HOST_WIDE_INT val_so_far;
2921 /* Avoid referencing memory over and over and invalid sharing
2922 on SUBREGs. */
2925 /* ACCUM starts out either as OP0 or as a zero, depending on
2926 the first operation. */
2929 {
2932 }
2934 {
2937 }
2938 else
2942 {
2945 rtx add_target
2950 rtx accum_inner;
2953 {
2956 /* REG_EQUAL note will be attached to the following insn. */
3001 (add_target
3008 }
3011 {
3012 /* Write a REG_EQUAL note on the last insn so that we can cse
3013 multiplication sequences. Note that if ACCUM is a SUBREG,
3014 we've set the inner register and must properly indicate that. */
3018 {
3022 }
3028 accum_inner);
3029 }
3030 }
3033 {
3036 }
3038 {
3041 }
3043 /* Compare only the bits of val and val_so_far that are significant
3044 in the result mode, to avoid sign-/zero-extension confusion. */
3053 }
3055 /* Perform a multiplication and return an rtx for the result.
3056 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3057 TARGET is a suggestion for where to store the result (an rtx).
3059 We check specially for a constant integer as OP1.
3060 If you want this check for OP0 as well, then before calling
3061 you should swap the two operands if OP0 would be constant. */
3063 rtx
3066 {
3069 rtx scalar_op1;
3075 {
3079 }
3081 /* For vectors, there are several simplifications that can be made if
3082 all elements of the vector constant are identical. */
3085 {
3091 }
3094 {
3095 rtx fake_reg;
3096 HOST_WIDE_INT coeff;
3111 /* If mode is integer vector mode, check if the backend supports
3112 vector lshift (by scalar or vector) at all. If not, we can't use
3113 synthetized multiply. */
3119 /* These are the operations that are potentially turned into
3120 a sequence of shifts and additions. */
3123 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3124 less than or equal in size to `unsigned int' this doesn't matter.
3125 If the mode is larger than `unsigned int', then synth_mult works
3126 only if the constant value exactly fits in an `unsigned int' without
3127 any truncation. This means that multiplying by negative values does
3128 not work; results are off by 2^32 on a 32 bit machine. */
3130 {
3133 }
3134 #if TARGET_SUPPORTS_WIDE_INT
3136 #else
3138 #endif
3139 {
3141 /* Perfect power of 2 (other than 1, which is handled above). */
3145 else
3147 }
3148 else
3151 /* We used to test optimize here, on the grounds that it's better to
3152 produce a smaller program when -O is not used. But this causes
3153 such a terrible slowdown sometimes that it seems better to always
3154 use synth_mult. */
3156 /* Special case powers of two. */
3164 /* Attempt to handle multiplication of DImode values by negative
3165 coefficients, by performing the multiplication by a positive
3166 multiplier and then inverting the result. */
3168 {
3169 /* Its safe to use -coeff even for INT_MIN, as the
3170 result is interpreted as an unsigned coefficient.
3171 Exclude cost of op0 from max_cost to match the cost
3172 calculation of the synth_mult. */
3179 /* Special case powers of two. */
3181 {
3185 }
3188 max_cost))
3189 {
3193 }
3195 }
3197 /* Exclude cost of op0 from max_cost to match the cost
3198 calculation of the synth_mult. */
3203 }
3204 skip_synth:
3206 /* Expand x*2.0 as x+x. */
3208 {
3209 REAL_VALUE_TYPE d;
3213 {
3217 }
3218 }
3219 skip_scalar:
3221 /* This used to use umul_optab if unsigned, but for non-widening multiply
3222 there is no difference between signed and unsigned. */
3227 }
3229 /* Return a cost estimate for multiplying a register by the given
3230 COEFFicient in the given MODE and SPEED. */
3232 int
3234 {
3243 else
3245 }
3247 /* Perform a widening multiplication and return an rtx for the result.
3248 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3249 TARGET is a suggestion for where to store the result (an rtx).
3250 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3251 or smul_widen_optab.
3253 We check specially for a constant integer as OP1, comparing the
3254 cost of a widening multiply against the cost of a sequence of shifts
3255 and adds. */
3257 rtx
3260 {
3262 rtx cop1;
3271 {
3277 /* Special case powers of two. */
3279 {
3283 }
3285 /* Exclude cost of op0 from max_cost to match the cost
3286 calculation of the synth_mult. */
3289 max_cost))
3290 {
3294 }
3295 }
3298 }
3299 \f
3300 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3301 replace division by D, and put the least significant N bits of the result
3302 in *MULTIPLIER_PTR and return the most significant bit.
3304 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3305 needed precision is in PRECISION (should be <= N).
3307 PRECISION should be as small as possible so this function can choose
3308 multiplier more freely.
3310 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3311 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3313 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3314 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3316 unsigned HOST_WIDE_INT
3320 {
3324 /* lgup = ceil(log2(divisor)); */
3332 /* mlow = 2^(N + lgup)/d */
3336 /* mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d */
3340 /* If precision == N, then mlow, mhigh exceed 2^N
3341 (but they do not exceed 2^(N+1)). */
3343 /* Reduce to lowest terms. */
3345 {
3347 HOST_BITS_PER_WIDE_INT);
3349 HOST_BITS_PER_WIDE_INT);
3355 }
3360 {
3364 }
3365 else
3366 {
3369 }
3370 }
3372 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3373 congruent to 1 (mod 2**N). */
3375 static unsigned HOST_WIDE_INT
3377 {
3378 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3380 /* The algorithm notes that the choice y = x satisfies
3381 x*y == 1 mod 2^3, since x is assumed odd.
3382 Each iteration doubles the number of bits of significance in y. */
3393 {
3396 }
3398 }
3400 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3401 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3402 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3403 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3404 become signed.
3406 The result is put in TARGET if that is convenient.
3408 MODE is the mode of operation. */
3410 rtx
3413 {
3414 rtx tem;
3420 adj_operand
3422 adj_operand);
3428 target);
3431 }
3433 /* Subroutine of expmed_mult_highpart. Return the MODE high part of OP. */
3435 static rtx
3437 {
3449 }
3451 /* Like expmed_mult_highpart, but only consider using a multiplication
3452 optab. OP1 is an rtx for the constant operand. */
3454 static rtx
3457 {
3460 optab moptab;
3461 rtx tem;
3470 /* Firstly, try using a multiplication insn that only generates the needed
3471 high part of the product, and in the sign flavor of unsignedp. */
3473 {
3479 }
3481 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3482 Need to adjust the result after the multiplication. */
3487 {
3492 /* We used the wrong signedness. Adjust the result. */
3495 }
3497 /* Try widening multiplication. */
3501 {
3506 }
3508 /* Try widening the mode and perform a non-widening multiplication. */
3513 {
3517 /* We need to widen the operands, for example to ensure the
3518 constant multiplier is correctly sign or zero extended.
3519 Use a sequence to clean-up any instructions emitted by
3520 the conversions if things don't work out. */
3530 {
3533 }
3534 }
3536 /* Try widening multiplication of opposite signedness, and adjust. */
3543 {
3547 {
3549 /* We used the wrong signedness. Adjust the result. */
3552 }
3553 }
3556 }
3558 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3559 putting the high half of the result in TARGET if that is convenient,
3560 and return where the result is. If the operation can not be performed,
3561 0 is returned.
3563 MODE is the mode of operation and result.
3565 UNSIGNEDP nonzero means unsigned multiply.
3567 MAX_COST is the total allowed cost for the expanded RTL. */
3569 static rtx
3572 {
3579 rtx tem;
3583 /* We can't support modes wider than HOST_BITS_PER_INT. */
3588 /* We can't optimize modes wider than BITS_PER_WORD.
3589 ??? We might be able to perform double-word arithmetic if
3590 mode == word_mode, however all the cost calculations in
3591 synth_mult etc. assume single-word operations. */
3598 /* Check whether we try to multiply by a negative constant. */
3600 {
3603 }
3605 /* See whether shift/add multiplication is cheap enough. */
3608 {
3609 /* See whether the specialized multiplication optabs are
3610 cheaper than the shift/add version. */
3620 /* Adjust result for signedness. */
3625 }
3628 }
3631 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3633 static rtx
3635 {
3644 /* Avoid conditional branches when they're expensive. */
3647 {
3651 {
3656 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3657 which instruction sequence to use. If logical right shifts
3658 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3659 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3665 {
3677 }
3678 else
3679 {
3691 }
3693 }
3694 }
3696 /* Mask contains the mode's signbit and the significant bits of the
3697 modulus. By including the signbit in the operation, many targets
3698 can avoid an explicit compare operation in the following comparison
3699 against zero. */
3725 }
3727 /* Expand signed division of OP0 by a power of two D in mode MODE.
3728 This routine is only called for positive values of D. */
3730 static rtx
3732 {
3733 rtx temp;
3742 {
3748 }
3750 #ifdef HAVE_conditional_move
3753 {
3754 rtx temp2;
3762 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3766 {
3771 }
3773 }
3774 #endif
3778 {
3788 else
3794 }
3802 }
3803 \f
3804 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3805 if that is convenient, and returning where the result is.
3806 You may request either the quotient or the remainder as the result;
3807 specify REM_FLAG nonzero to get the remainder.
3809 CODE is the expression code for which kind of division this is;
3810 it controls how rounding is done. MODE is the machine mode to use.
3811 UNSIGNEDP nonzero means do unsigned division. */
3813 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3814 and then correct it by or'ing in missing high bits
3815 if result of ANDI is nonzero.
3816 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3817 This could optimize to a bfexts instruction.
3818 But C doesn't use these operations, so their optimizations are
3819 left for later. */
3820 /* ??? For modulo, we don't actually need the highpart of the first product,
3821 the low part will do nicely. And for small divisors, the second multiply
3822 can also be a low-part only multiply or even be completely left out.
3823 E.g. to calculate the remainder of a division by 3 with a 32 bit
3824 multiply, multiply with 0x55555556 and extract the upper two bits;
3825 the result is exact for inputs up to 0x1fffffff.
3826 The input range can be reduced by using cross-sum rules.
3827 For odd divisors >= 3, the following table gives right shift counts
3828 so that if a number is shifted by an integer multiple of the given
3829 amount, the remainder stays the same:
3830 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3831 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3832 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3833 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3834 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3836 Cross-sum rules for even numbers can be derived by leaving as many bits
3837 to the right alone as the divisor has zeros to the right.
3838 E.g. if x is an unsigned 32 bit number:
3839 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3840 */
3842 rtx
3845 {
3847 rtx tquotient;
3860 {
3866 }
3868 /*
3869 This is the structure of expand_divmod:
3871 First comes code to fix up the operands so we can perform the operations
3872 correctly and efficiently.
3874 Second comes a switch statement with code specific for each rounding mode.
3875 For some special operands this code emits all RTL for the desired
3876 operation, for other cases, it generates only a quotient and stores it in
3877 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3878 to indicate that it has not done anything.
3880 Last comes code that finishes the operation. If QUOTIENT is set and
3881 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3882 QUOTIENT is not set, it is computed using trunc rounding.
3884 We try to generate special code for division and remainder when OP1 is a
3885 constant. If |OP1| = 2**n we can use shifts and some other fast
3886 operations. For other values of OP1, we compute a carefully selected
3887 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3888 by m.
3890 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3891 half of the product. Different strategies for generating the product are
3892 implemented in expmed_mult_highpart.
3894 If what we actually want is the remainder, we generate that by another
3895 by-constant multiplication and a subtraction. */
3897 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3898 code below will malfunction if we are, so check here and handle
3899 the special case if so. */
3903 /* When dividing by -1, we could get an overflow.
3904 negv_optab can handle overflows. */
3906 {
3911 }
3914 /* Don't use the function value register as a target
3915 since we have to read it as well as write it,
3916 and function-inlining gets confused by this. */
3918 /* Don't clobber an operand while doing a multi-step calculation. */
3926 /* Get the mode in which to perform this computation. Normally it will
3927 be MODE, but sometimes we can't do the desired operation in MODE.
3928 If so, pick a wider mode in which we can do the operation. Convert
3929 to that mode at the start to avoid repeated conversions.
3931 First see what operations we need. These depend on the expression
3932 we are evaluating. (We assume that divxx3 insns exist under the
3933 same conditions that modxx3 insns and that these insns don't normally
3934 fail. If these assumptions are not correct, we may generate less
3935 efficient code in some cases.)
3937 Then see if we find a mode in which we can open-code that operation
3938 (either a division, modulus, or shift). Finally, check for the smallest
3939 mode for which we can do the operation with a library call. */
3941 /* We might want to refine this now that we have division-by-constant
3942 optimization. Since expmed_mult_highpart tries so many variants, it is
3943 not straightforward to generalize this. Maybe we should make an array
3944 of possible modes in init_expmed? Save this for GCC 2.7. */
3950 ? optab1
3966 /* If we still couldn't find a mode, use MODE, but expand_binop will
3967 probably die. */
3973 else
3977 #if 0
3978 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3979 (mode), and thereby get better code when OP1 is a constant. Do that
3980 later. It will require going over all usages of SIZE below. */
3982 #endif
3984 /* Only deduct something for a REM if the last divide done was
3985 for a different constant. Then set the constant of the last
3986 divide. */
3987 max_cost = (unsignedp
3997 /* Now convert to the best mode to use. */
3999 {
4003 /* convert_modes may have placed op1 into a register, so we
4004 must recompute the following. */
4006 op1_is_pow2 = (op1_is_constant
4008 || (! unsignedp
4010 }
4012 /* If one of the operands is a volatile MEM, copy it into a register. */
4019 /* If we need the remainder or if OP1 is constant, we need to
4020 put OP0 in a register in case it has any queued subexpressions. */
4026 /* Promote floor rounding to trunc rounding for unsigned operations. */
4028 {
4035 }
4039 {
4043 {
4045 {
4053 {
4056 {
4057 unsigned HOST_WIDE_INT mask
4059 remainder
4063 OPTAB_LIB_WIDEN);
4066 }
4069 }
4071 {
4073 {
4074 /* Most significant bit of divisor is set; emit an scc
4075 insn. */
4078 }
4079 else
4080 {
4081 /* Find a suitable multiplier and right shift count
4082 instead of multiplying with D. */
4087 /* If the suggested multiplier is more than SIZE bits,
4088 we can do better for even divisors, using an
4089 initial right shift. */
4091 {
4097 }
4098 else
4102 {
4108 extra_cost
4112 t1 = expmed_mult_highpart
4120 NULL_RTX);
4125 NULL_RTX);
4126 quotient = expand_shift
4129 }
4130 else
4131 {
4138 t1 = expand_shift
4141 extra_cost
4144 t2 = expmed_mult_highpart
4150 quotient = expand_shift
4153 }
4154 }
4155 }
4163 quotient);
4164 }
4166 {
4169 rtx mlr;
4173 /* Since d might be INT_MIN, we have to cast to
4174 unsigned HOST_WIDE_INT before negating to avoid
4175 undefined signed overflow. */
4180 /* n rem d = n rem -d */
4182 {
4185 }
4194 {
4195 /* This case is not handled correctly below. */
4200 }
4202 && (rem_flag
4205 /* We assume that cheap metric is true if the
4206 optab has an expander for this mode. */
4209 compute_mode)
4212 compute_mode)
4214 ;
4216 {
4218 {
4222 }
4232 compute_mode),
4234 else
4237 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4238 negate the quotient. */
4240 {
4247 gen_int_mode
4249 compute_mode)),
4250 quotient);
4254 }
4255 }
4257 {
4261 {
4271 t1 = expmed_mult_highpart
4276 t2 = expand_shift
4279 t3 = expand_shift
4283 quotient
4286 tquotient);
4287 else
4288 quotient
4291 tquotient);
4292 }
4293 else
4294 {
4313 NULL_RTX);
4314 t3 = expand_shift
4317 t4 = expand_shift
4321 quotient
4324 tquotient);
4325 else
4326 quotient
4329 tquotient);
4330 }
4331 }
4339 quotient);
4340 }
4342 }
4343 fail1:
4349 /* We will come here only for signed operations. */
4351 {
4357 {
4358 /* We could just as easily deal with negative constants here,
4359 but it does not seem worth the trouble for GCC 2.6. */
4361 {
4364 {
4365 unsigned HOST_WIDE_INT mask
4367 remainder = expand_binop
4373 }
4374 quotient = expand_shift
4377 }
4378 else
4379 {
4388 {
4389 t1 = expand_shift
4397 t3 = expmed_mult_highpart
4401 {
4402 t4 = expand_shift
4407 OPTAB_WIDEN);
4408 }
4409 }
4410 }
4411 }
4412 else
4413 {
4419 nsign = expand_shift
4423 NULL_RTX);
4427 {
4428 rtx t5;
4433 tquotient);
4434 }
4435 }
4436 }
4442 /* Try using an instruction that produces both the quotient and
4443 remainder, using truncation. We can easily compensate the quotient
4444 or remainder to get floor rounding, once we have the remainder.
4445 Notice that we compute also the final remainder value here,
4446 and return the result right away. */
4451 {
4452 remainder
4455 }
4456 else
4457 {
4458 quotient
4461 }
4465 {
4466 /* This could be computed with a branch-less sequence.
4467 Save that for later. */
4468 rtx tem;
4478 }
4480 /* No luck with division elimination or divmod. Have to do it
4481 by conditionally adjusting op0 *and* the result. */
4482 {
4484 rtx adjusted_op0;
4485 rtx tem;
4523 }
4529 {
4531 {
4543 {
4550 }
4551 else
4554 tquotient);
4556 }
4558 /* Try using an instruction that produces both the quotient and
4559 remainder, using truncation. We can easily compensate the
4560 quotient or remainder to get ceiling rounding, once we have the
4561 remainder. Notice that we compute also the final remainder
4562 value here, and return the result right away. */
4567 {
4571 }
4572 else
4573 {
4577 }
4581 {
4582 /* This could be computed with a branch-less sequence.
4583 Save that for later. */
4591 }
4593 /* No luck with division elimination or divmod. Have to do it
4594 by conditionally adjusting op0 *and* the result. */
4595 {
4616 }
4617 }
4619 {
4622 {
4623 /* This is extremely similar to the code for the unsigned case
4624 above. For 2.7 we should merge these variants, but for
4625 2.6.1 I don't want to touch the code for unsigned since that
4626 get used in C. The signed case will only be used by other
4627 languages (Ada). */
4640 {
4647 }
4648 else
4651 tquotient);
4653 }
4655 /* Try using an instruction that produces both the quotient and
4656 remainder, using truncation. We can easily compensate the
4657 quotient or remainder to get ceiling rounding, once we have the
4658 remainder. Notice that we compute also the final remainder
4659 value here, and return the result right away. */
4663 {
4667 }
4668 else
4669 {
4673 }
4677 {
4678 /* This could be computed with a branch-less sequence.
4679 Save that for later. */
4680 rtx tem;
4691 }
4693 /* No luck with division elimination or divmod. Have to do it
4694 by conditionally adjusting op0 *and* the result. */
4695 {
4697 rtx adjusted_op0;
4698 rtx tem;
4738 }
4739 }
4744 {
4748 rtx t1;
4762 quotient);
4763 }
4769 {
4770 rtx tem;
4776 {
4777 rtx tem;
4783 }
4790 }
4791 else
4792 {
4799 {
4800 rtx tem;
4806 }
4827 }
4832 }
4835 {
4840 {
4841 /* Try to produce the remainder without producing the quotient.
4842 If we seem to have a divmod pattern that does not require widening,
4843 don't try widening here. We should really have a WIDEN argument
4844 to expand_twoval_binop, since what we'd really like to do here is
4845 1) try a mod insn in compute_mode
4846 2) try a divmod insn in compute_mode
4847 3) try a div insn in compute_mode and multiply-subtract to get
4848 remainder
4849 4) try the same things with widening allowed. */
4850 remainder
4853 unsignedp,
4858 {
4859 /* No luck there. Can we do remainder and divide at once
4860 without a library call? */
4863 ? udivmod_optab
4868 }
4872 }
4874 /* Produce the quotient. Try a quotient insn, but not a library call.
4875 If we have a divmod in this mode, use it in preference to widening
4876 the div (for this test we assume it will not fail). Note that optab2
4877 is set to the one of the two optabs that the call below will use. */
4878 quotient
4881 unsignedp,
4887 {
4888 /* No luck there. Try a quotient-and-remainder insn,
4889 keeping the quotient alone. */
4894 {
4897 /* Still no luck. If we are not computing the remainder,
4898 use a library call for the quotient. */
4903 }
4904 }
4905 }
4908 {
4913 {
4914 /* No divide instruction either. Use library for remainder. */
4918 /* No remainder function. Try a quotient-and-remainder
4919 function, keeping the remainder. */
4921 {
4929 }
4930 }
4931 else
4932 {
4933 /* We divided. Now finish doing X - Y * (X / Y). */
4938 OPTAB_LIB_WIDEN);
4939 }
4940 }
4943 }
4944 \f
4945 /* Return a tree node with data type TYPE, describing the value of X.
4946 Usually this is an VAR_DECL, if there is no obvious better choice.
4947 X may be an expression, however we only support those expressions
4948 generated by loop.c. */
4950 tree
4952 {
4953 tree t;
4956 {
4968 else
4969 {
4970 REAL_VALUE_TYPE d;
4974 }
4979 {
4985 /* Build a tree with vector elements. */
4988 {
4991 }
4994 }
5030 else
5055 /* else fall through. */
5060 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5061 address mode to pointer mode. */
5063 x = convert_memory_address_addr_space
5066 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5067 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5071 }
5072 }
5073 \f
5074 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5075 and returning TARGET.
5077 If TARGET is 0, a pseudo-register or constant is returned. */
5079 rtx
5081 {
5094 }
5096 /* Helper function for emit_store_flag. */
5097 static rtx
5102 {
5112 {
5115 }
5129 {
5132 }
5135 /* If we are converting to a wider mode, first convert to
5136 TARGET_MODE, then normalize. This produces better combining
5137 opportunities on machines that have a SIGN_EXTRACT when we are
5138 testing a single bit. This mostly benefits the 68k.
5140 If STORE_FLAG_VALUE does not have the sign bit set when
5141 interpreted in MODE, we can do this conversion as unsigned, which
5142 is usually more efficient. */
5144 {
5147 STORE_FLAG_VALUE));
5150 }
5151 else
5154 /* If we want to keep subexpressions around, don't reuse our last
5155 target. */
5159 /* Now normalize to the proper value in MODE. Sometimes we don't
5160 have to do anything. */
5162 ;
5163 /* STORE_FLAG_VALUE might be the most negative number, so write
5164 the comparison this way to avoid a compiler-time warning. */
5168 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5169 it hard to use a value of just the sign bit due to ANSI integer
5170 constant typing rules. */
5175 else
5176 {
5182 }
5184 /* If we were converting to a smaller mode, do the conversion now. */
5186 {
5189 }
5190 else
5192 }
5195 /* A subroutine of emit_store_flag only including "tricks" that do not
5196 need a recursive call. These are kept separate to avoid infinite
5197 loops. */
5199 static rtx
5203 {
5204 rtx subtarget;
5209 rtx tem;
5215 /* If one operand is constant, make it the second one. Only do this
5216 if the other operand is not constant as well. */
5219 {
5224 }
5229 /* For some comparisons with 1 and -1, we can convert this to
5230 comparisons with zero. This will often produce more opportunities for
5231 store-flag insns. */
5234 {
5261 }
5263 /* If we are comparing a double-word integer with zero or -1, we can
5264 convert the comparison into one involving a single word. */
5268 {
5271 {
5274 /* Do a logical OR or AND of the two words and compare the
5275 result. */
5281 OPTAB_DIRECT);
5286 }
5288 {
5289 rtx op0h;
5291 /* If testing the sign bit, can just test on high word. */
5294 mode));
5297 }
5298 else
5302 {
5313 }
5314 }
5316 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5317 complement of A (for GE) and shifting the sign bit to the low bit. */
5322 {
5328 /* If the result is to be wider than OP0, it is best to convert it
5329 first. If it is to be narrower, it is *incorrect* to convert it
5330 first. */
5332 {
5335 }
5346 /* If we are supposed to produce a 0/1 value, we want to do
5347 a logical shift from the sign bit to the low-order bit; for
5348 a -1/0 value, we do an arithmetic shift. */
5357 }
5362 {
5366 {
5374 {
5379 }
5381 }
5382 }
5385 }
5387 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5388 and storing in TARGET. Normally return TARGET.
5389 Return 0 if that cannot be done.
5391 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5392 it is VOIDmode, they cannot both be CONST_INT.
5394 UNSIGNEDP is for the case where we have to widen the operands
5395 to perform the operation. It says to use zero-extension.
5397 NORMALIZEP is 1 if we should convert the result to be either zero
5398 or one. Normalize is -1 if we should convert the result to be
5399 either zero or -1. If NORMALIZEP is zero, the result will be left
5400 "raw" out of the scc insn. */
5402 rtx
5405 {
5408 rtx subtarget;
5412 /* If we compare constants, we shouldn't use a store-flag operation,
5413 but a constant load. We can get there via the vanilla route that
5414 usually generates a compare-branch sequence, but will in this case
5415 fold the comparison to a constant, and thus elide the branch. */
5420 target_mode);
5424 /* If we reached here, we can't do this with a scc insn, however there
5425 are some comparisons that can be done in other ways. Don't do any
5426 of these cases if branches are very cheap. */
5430 /* See what we need to return. We can only return a 1, -1, or the
5431 sign bit. */
5434 {
5439 ;
5440 else
5442 }
5446 /* If optimizing, use different pseudo registers for each insn, instead
5447 of reusing the same pseudo. This leads to better CSE, but slows
5448 down the compiler, since there are more pseudos */
5449 subtarget = (!optimize
5453 /* For floating-point comparisons, try the reverse comparison or try
5454 changing the "orderedness" of the comparison. */
5456 {
5465 {
5469 /* For the reverse comparison, use either an addition or a XOR. */
5473 {
5480 }
5484 {
5490 }
5491 }
5495 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5501 /* If there are no NaNs, the first comparison should always fall through.
5502 Effectively change the comparison to the other one. */
5504 {
5507 target_mode);
5508 }
5510 #ifdef HAVE_conditional_move
5511 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5512 conditional move. */
5521 else
5528 #else
5530 #endif
5531 }
5533 /* The remaining tricks only apply to integer comparisons. */
5538 /* If this is an equality comparison of integers, we can try to exclusive-or
5539 (or subtract) the two operands and use a recursive call to try the
5540 comparison with zero. Don't do any of these cases if branches are
5541 very cheap. */
5544 {
5546 OPTAB_WIDEN);
5550 OPTAB_WIDEN);
5558 }
5560 /* For integer comparisons, try the reverse comparison. However, for
5561 small X and if we'd have anyway to extend, implementing "X != 0"
5562 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5569 {
5573 /* Again, for the reverse comparison, use either an addition or a XOR. */
5577 {
5584 }
5588 {
5594 }
5599 }
5601 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5602 the constant zero. Reject all other comparisons at this point. Only
5603 do LE and GT if branches are expensive since they are expensive on
5604 2-operand machines. */
5612 /* Try to put the result of the comparison in the sign bit. Assume we can't
5613 do the necessary operation below. */
5617 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5618 the sign bit set. */
5621 {
5622 /* This is destructive, so SUBTARGET can't be OP0. */
5627 OPTAB_WIDEN);
5630 OPTAB_WIDEN);
5631 }
5633 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5634 number of bits in the mode of OP0, minus one. */
5637 {
5645 OPTAB_WIDEN);
5646 }
5649 {
5650 /* For EQ or NE, one way to do the comparison is to apply an operation
5651 that converts the operand into a positive number if it is nonzero
5652 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5653 for NE we negate. This puts the result in the sign bit. Then we
5654 normalize with a shift, if needed.
5656 Two operations that can do the above actions are ABS and FFS, so try
5657 them. If that doesn't work, and MODE is smaller than a full word,
5658 we can use zero-extension to the wider mode (an unsigned conversion)
5659 as the operation. */
5661 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5662 that is compensated by the subsequent overflow when subtracting
5663 one / negating. */
5670 {
5673 }
5676 {
5680 else
5682 }
5684 /* If we couldn't do it that way, for NE we can "or" the two's complement
5685 of the value with itself. For EQ, we take the one's complement of
5686 that "or", which is an extra insn, so we only handle EQ if branches
5687 are expensive. */
5693 {
5699 OPTAB_WIDEN);
5703 }
5704 }
5712 {
5714 ;
5716 {
5719 }
5721 {
5724 }
5725 }
5726 else
5730 }
5732 /* Like emit_store_flag, but always succeeds. */
5734 rtx
5737 {
5738 rtx tem;
5742 /* First see if emit_store_flag can do the job. */
5750 /* If this failed, we have to do this with set/compare/jump/set code.
5751 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5758 {
5765 }
5771 /* Jump in the right direction if the target cannot implement CODE
5772 but can jump on its reverse condition. */
5779 {
5783 else
5786 /* Canonicalize to UNORDERED for the libcall. */
5789 {
5793 }
5794 }
5805 }
5806 \f
5807 /* Perform possibly multi-word comparison and conditional jump to LABEL
5808 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
5809 now a thin wrapper around do_compare_rtx_and_jump. */
5811 static void
5814 {
5818 }