1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
27 [(UNSPEC_LOAD_DF_LOW 0)
28 (UNSPEC_LOAD_DF_HIGH 1)
29 (UNSPEC_STORE_DF_HIGH 2)
33 (UNSPEC_NONLOCAL_GOTO_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
52 (UNSPEC_CLEAR_HAZARD 33)
56 (UNSPEC_COMPARE_AND_SWAP 37)
57 (UNSPEC_SYNC_OLD_OP 38)
58 (UNSPEC_SYNC_NEW_OP 39)
59 (UNSPEC_SYNC_EXCHANGE 40)
61 (UNSPEC_ADDRESS_FIRST 100)
65 ;; For MIPS Paired-Singled Floating Point Instructions.
67 (UNSPEC_MOVE_TF_PS 200)
70 ;; MIPS64/MIPS32R2 alnv.ps
73 ;; MIPS-3D instructions
77 (UNSPEC_CVT_PW_PS 205)
78 (UNSPEC_CVT_PS_PW 206)
86 (UNSPEC_SINGLE_CC 213)
89 ;; MIPS DSP ASE Revision 0.98 3/24/2005
97 (UNSPEC_RADDU_W_QB 307)
99 (UNSPEC_PRECRQ_QB_PH 309)
100 (UNSPEC_PRECRQ_PH_W 310)
101 (UNSPEC_PRECRQ_RS_PH_W 311)
102 (UNSPEC_PRECRQU_S_QB_PH 312)
103 (UNSPEC_PRECEQ_W_PHL 313)
104 (UNSPEC_PRECEQ_W_PHR 314)
105 (UNSPEC_PRECEQU_PH_QBL 315)
106 (UNSPEC_PRECEQU_PH_QBR 316)
107 (UNSPEC_PRECEQU_PH_QBLA 317)
108 (UNSPEC_PRECEQU_PH_QBRA 318)
109 (UNSPEC_PRECEU_PH_QBL 319)
110 (UNSPEC_PRECEU_PH_QBR 320)
111 (UNSPEC_PRECEU_PH_QBLA 321)
112 (UNSPEC_PRECEU_PH_QBRA 322)
118 (UNSPEC_MULEU_S_PH_QBL 328)
119 (UNSPEC_MULEU_S_PH_QBR 329)
120 (UNSPEC_MULQ_RS_PH 330)
121 (UNSPEC_MULEQ_S_W_PHL 331)
122 (UNSPEC_MULEQ_S_W_PHR 332)
123 (UNSPEC_DPAU_H_QBL 333)
124 (UNSPEC_DPAU_H_QBR 334)
125 (UNSPEC_DPSU_H_QBL 335)
126 (UNSPEC_DPSU_H_QBR 336)
127 (UNSPEC_DPAQ_S_W_PH 337)
128 (UNSPEC_DPSQ_S_W_PH 338)
129 (UNSPEC_MULSAQ_S_W_PH 339)
130 (UNSPEC_DPAQ_SA_L_W 340)
131 (UNSPEC_DPSQ_SA_L_W 341)
132 (UNSPEC_MAQ_S_W_PHL 342)
133 (UNSPEC_MAQ_S_W_PHR 343)
134 (UNSPEC_MAQ_SA_W_PHL 344)
135 (UNSPEC_MAQ_SA_W_PHR 345)
143 (UNSPEC_CMPGU_EQ_QB 353)
144 (UNSPEC_CMPGU_LT_QB 354)
145 (UNSPEC_CMPGU_LE_QB 355)
147 (UNSPEC_PACKRL_PH 357)
149 (UNSPEC_EXTR_R_W 359)
150 (UNSPEC_EXTR_RS_W 360)
151 (UNSPEC_EXTR_S_H 361)
159 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
160 (UNSPEC_ABSQ_S_QB 400)
162 (UNSPEC_ADDU_S_PH 402)
163 (UNSPEC_ADDUH_QB 403)
164 (UNSPEC_ADDUH_R_QB 404)
167 (UNSPEC_CMPGDU_EQ_QB 407)
168 (UNSPEC_CMPGDU_LT_QB 408)
169 (UNSPEC_CMPGDU_LE_QB 409)
170 (UNSPEC_DPA_W_PH 410)
171 (UNSPEC_DPS_W_PH 411)
177 (UNSPEC_MUL_S_PH 417)
178 (UNSPEC_MULQ_RS_W 418)
179 (UNSPEC_MULQ_S_PH 419)
180 (UNSPEC_MULQ_S_W 420)
181 (UNSPEC_MULSA_W_PH 421)
184 (UNSPEC_PRECR_QB_PH 424)
185 (UNSPEC_PRECR_SRA_PH_W 425)
186 (UNSPEC_PRECR_SRA_R_PH_W 426)
189 (UNSPEC_SHRA_R_QB 429)
192 (UNSPEC_SUBU_S_PH 432)
193 (UNSPEC_SUBUH_QB 433)
194 (UNSPEC_SUBUH_R_QB 434)
195 (UNSPEC_ADDQH_PH 435)
196 (UNSPEC_ADDQH_R_PH 436)
198 (UNSPEC_ADDQH_R_W 438)
199 (UNSPEC_SUBQH_PH 439)
200 (UNSPEC_SUBQH_R_PH 440)
202 (UNSPEC_SUBQH_R_W 442)
203 (UNSPEC_DPAX_W_PH 443)
204 (UNSPEC_DPSX_W_PH 444)
205 (UNSPEC_DPAQX_S_W_PH 445)
206 (UNSPEC_DPAQX_SA_W_PH 446)
207 (UNSPEC_DPSQX_S_W_PH 447)
208 (UNSPEC_DPSQX_SA_W_PH 448)
212 (include "predicates.md")
213 (include "constraints.md")
215 ;; ....................
219 ;; ....................
221 (define_attr "got" "unset,xgot_high,load"
222 (const_string "unset"))
224 ;; For jal instructions, this attribute is DIRECT when the target address
225 ;; is symbolic and INDIRECT when it is a register.
226 (define_attr "jal" "unset,direct,indirect"
227 (const_string "unset"))
229 ;; This attribute is YES if the instruction is a jal macro (not a
230 ;; real jal instruction).
232 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
233 ;; an instruction to restore $gp. Direct jals are also macros for
234 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
235 ;; the target address into a register.
236 (define_attr "jal_macro" "no,yes"
237 (cond [(eq_attr "jal" "direct")
238 (symbol_ref "TARGET_CALL_CLOBBERED_GP
239 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
240 (eq_attr "jal" "indirect")
241 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
242 (const_string "no")))
244 ;; Classification of each insn.
245 ;; branch conditional branch
246 ;; jump unconditional jump
247 ;; call unconditional call
248 ;; load load instruction(s)
249 ;; fpload floating point load
250 ;; fpidxload floating point indexed load
251 ;; store store instruction(s)
252 ;; fpstore floating point store
253 ;; fpidxstore floating point indexed store
254 ;; prefetch memory prefetch (register + offset)
255 ;; prefetchx memory indexed prefetch (register + register)
256 ;; condmove conditional moves
257 ;; mfc transfer from coprocessor
258 ;; mtc transfer to coprocessor
259 ;; mthilo transfer to hi/lo registers
260 ;; mfhilo transfer from hi/lo registers
261 ;; const load constant
262 ;; arith integer arithmetic instructions
263 ;; logical integer logical instructions
264 ;; shift integer shift instructions
265 ;; slt set less than instructions
266 ;; signext sign extend instructions
267 ;; clz the clz and clo instructions
268 ;; trap trap if instructions
269 ;; imul integer multiply 2 operands
270 ;; imul3 integer multiply 3 operands
271 ;; imadd integer multiply-add
272 ;; idiv integer divide
273 ;; move integer register move ({,D}ADD{,U} with rt = 0)
274 ;; fmove floating point register move
275 ;; fadd floating point add/subtract
276 ;; fmul floating point multiply
277 ;; fmadd floating point multiply-add
278 ;; fdiv floating point divide
279 ;; frdiv floating point reciprocal divide
280 ;; frdiv1 floating point reciprocal divide step 1
281 ;; frdiv2 floating point reciprocal divide step 2
282 ;; fabs floating point absolute value
283 ;; fneg floating point negation
284 ;; fcmp floating point compare
285 ;; fcvt floating point convert
286 ;; fsqrt floating point square root
287 ;; frsqrt floating point reciprocal square root
288 ;; frsqrt1 floating point reciprocal square root step1
289 ;; frsqrt2 floating point reciprocal square root step2
290 ;; multi multiword sequence (or user asm statements)
293 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,logical,shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
294 (cond [(eq_attr "jal" "!unset") (const_string "call")
295 (eq_attr "got" "load") (const_string "load")]
296 (const_string "unknown")))
298 ;; Main data type used by the insn
299 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
300 (const_string "unknown"))
302 ;; Mode for conversion types (fcvt)
303 ;; I2S integer to float single (SI/DI to SF)
304 ;; I2D integer to float double (SI/DI to DF)
305 ;; S2I float to integer (SF to SI/DI)
306 ;; D2I float to integer (DF to SI/DI)
307 ;; D2S double to float single
308 ;; S2D float single to double
310 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
311 (const_string "unknown"))
313 ;; Is this an extended instruction in mips16 mode?
314 (define_attr "extended_mips16" "no,yes"
317 ;; Length of instruction in bytes.
318 (define_attr "length" ""
319 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
320 ;; If a branch is outside this range, we have a choice of two
321 ;; sequences. For PIC, an out-of-range branch like:
326 ;; becomes the equivalent of:
335 ;; where the load address can be up to three instructions long
338 ;; The non-PIC case is similar except that we use a direct
339 ;; jump instead of an la/jr pair. Since the target of this
340 ;; jump is an absolute 28-bit bit address (the other bits
341 ;; coming from the address of the delay slot) this form cannot
342 ;; cross a 256MB boundary. We could provide the option of
343 ;; using la/jr in this case too, but we do not do so at
346 ;; Note that this value does not account for the delay slot
347 ;; instruction, whose length is added separately. If the RTL
348 ;; pattern has no explicit delay slot, mips_adjust_insn_length
349 ;; will add the length of the implicit nop. The values for
350 ;; forward and backward branches will be different as well.
351 (eq_attr "type" "branch")
352 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
353 (le (minus (pc) (match_dup 1)) (const_int 131068)))
355 (ne (symbol_ref "flag_pic") (const_int 0))
359 (eq_attr "got" "load")
361 (eq_attr "got" "xgot_high")
364 (eq_attr "type" "const")
365 (symbol_ref "mips_const_insns (operands[1]) * 4")
366 (eq_attr "type" "load,fpload")
367 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
368 (eq_attr "type" "store,fpstore")
369 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
371 ;; In the worst case, a call macro will take 8 instructions:
373 ;; lui $25,%call_hi(FOO)
375 ;; lw $25,%call_lo(FOO)($25)
381 (eq_attr "jal_macro" "yes")
384 (and (eq_attr "extended_mips16" "yes")
385 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
388 ;; Various VR4120 errata require a nop to be inserted after a macc
389 ;; instruction. The assembler does this for us, so account for
390 ;; the worst-case length here.
391 (and (eq_attr "type" "imadd")
392 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
395 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
396 ;; the result of the second one is missed. The assembler should work
397 ;; around this by inserting a nop after the first dmult.
398 (and (eq_attr "type" "imul,imul3")
399 (and (eq_attr "mode" "DI")
400 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
403 (eq_attr "type" "idiv")
404 (symbol_ref "mips_idiv_insns () * 4")
407 ;; Attribute describing the processor. This attribute must match exactly
408 ;; with the processor_type enumeration in mips.h.
410 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
411 (const (symbol_ref "mips_tune")))
413 ;; The type of hardware hazard associated with this instruction.
414 ;; DELAY means that the next instruction cannot read the result
415 ;; of this one. HILO means that the next two instructions cannot
416 ;; write to HI or LO.
417 (define_attr "hazard" "none,delay,hilo"
418 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
419 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
420 (const_string "delay")
422 (and (eq_attr "type" "mfc,mtc")
423 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
424 (const_string "delay")
426 (and (eq_attr "type" "fcmp")
427 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
428 (const_string "delay")
430 ;; The r4000 multiplication patterns include an mflo instruction.
431 (and (eq_attr "type" "imul")
432 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
433 (const_string "hilo")
435 (and (eq_attr "type" "mfhilo")
436 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
437 (const_string "hilo")]
438 (const_string "none")))
440 ;; Is it a single instruction?
441 (define_attr "single_insn" "no,yes"
442 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
444 ;; Can the instruction be put into a delay slot?
445 (define_attr "can_delay" "no,yes"
446 (if_then_else (and (eq_attr "type" "!branch,call,jump")
447 (and (eq_attr "hazard" "none")
448 (eq_attr "single_insn" "yes")))
450 (const_string "no")))
452 ;; Attribute defining whether or not we can use the branch-likely instructions
453 (define_attr "branch_likely" "no,yes"
455 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
457 (const_string "no"))))
459 ;; True if an instruction might assign to hi or lo when reloaded.
460 ;; This is used by the TUNE_MACC_CHAINS code.
461 (define_attr "may_clobber_hilo" "no,yes"
462 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
464 (const_string "no")))
466 ;; Describe a user's asm statement.
467 (define_asm_attributes
468 [(set_attr "type" "multi")
469 (set_attr "can_delay" "no")])
471 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
472 ;; from the same template.
473 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
475 ;; This mode iterator allows :P to be used for patterns that operate on
476 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
477 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
479 ;; This mode iterator allows :MOVECC to be used anywhere that a
480 ;; conditional-move-type condition is needed.
481 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
483 ;; This mode iterator allows the QI and HI extension patterns to be defined from
484 ;; the same template.
485 (define_mode_iterator SHORT [QI HI])
487 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
488 ;; floating-point mode is allowed.
489 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
490 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
491 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
493 ;; Like ANYF, but only applies to scalar modes.
494 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
495 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
497 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
498 ;; 32-bit version and "dsubu" in the 64-bit version.
499 (define_mode_attr d [(SI "") (DI "d")])
501 ;; This attribute gives the length suffix for a sign- or zero-extension
503 (define_mode_attr size [(QI "b") (HI "h")])
505 ;; This attributes gives the mode mask of a SHORT.
506 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
508 ;; Mode attributes for GPR loads and stores.
509 (define_mode_attr load [(SI "lw") (DI "ld")])
510 (define_mode_attr store [(SI "sw") (DI "sd")])
512 ;; Similarly for MIPS IV indexed FPR loads and stores.
513 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
514 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
516 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
517 ;; are different. Some forms of unextended addiu have an 8-bit immediate
518 ;; field but the equivalent daddiu has only a 5-bit field.
519 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
521 ;; This attribute gives the best constraint to use for registers of
523 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
525 ;; This attribute gives the format suffix for floating-point operations.
526 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
528 ;; This attribute gives the upper-case mode name for one unit of a
529 ;; floating-point mode.
530 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
532 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
534 ;; In certain cases, div.s and div.ps may have a rounding error
535 ;; and/or wrong inexact flag.
537 ;; Therefore, we only allow div.s if not working around SB-1 rev2
538 ;; errata or if a slight loss of precision is OK.
539 (define_mode_attr divide_condition
540 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
541 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
543 ; This attribute gives the condition for which sqrt instructions exist.
544 (define_mode_attr sqrt_condition
545 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
547 ; This attribute gives the condition for which recip and rsqrt instructions
549 (define_mode_attr recip_condition
550 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
552 ;; This code iterator allows all branch instructions to be generated from
553 ;; a single define_expand template.
554 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
555 eq ne gt ge lt le gtu geu ltu leu])
557 ;; This code iterator allows signed and unsigned widening multiplications
558 ;; to use the same template.
559 (define_code_iterator any_extend [sign_extend zero_extend])
561 ;; This code iterator allows the three shift instructions to be generated
562 ;; from the same template.
563 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
565 ;; This code iterator allows all native floating-point comparisons to be
566 ;; generated from the same template.
567 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
569 ;; This code iterator is used for comparisons that can be implemented
570 ;; by swapping the operands.
571 (define_code_iterator swapped_fcond [ge gt unge ungt])
573 ;; <u> expands to an empty string when doing a signed operation and
574 ;; "u" when doing an unsigned operation.
575 (define_code_attr u [(sign_extend "") (zero_extend "u")])
577 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
578 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
580 ;; <optab> expands to the name of the optab for a particular code.
581 (define_code_attr optab [(ashift "ashl")
588 ;; <insn> expands to the name of the insn that implements a particular code.
589 (define_code_attr insn [(ashift "sll")
596 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
597 (define_code_attr fcond [(unordered "un")
605 ;; Similar, but for swapped conditions.
606 (define_code_attr swapped_fcond [(ge "le")
611 ;; Atomic fetch bitwise operations.
612 (define_code_macro fetchop_bit [ior xor and])
614 ;; <immediate_insn> expands to the name of the insn that implements
615 ;; a particular code to operate in immediate values.
616 (define_code_attr immediate_insn [(ior "ori") (xor "xori") (and "andi")])
619 ;; .........................
621 ;; Branch, call and jump delay slots
623 ;; .........................
625 (define_delay (and (eq_attr "type" "branch")
626 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
627 [(eq_attr "can_delay" "yes")
629 (and (eq_attr "branch_likely" "yes")
630 (eq_attr "can_delay" "yes"))])
632 (define_delay (eq_attr "type" "jump")
633 [(eq_attr "can_delay" "yes")
637 (define_delay (and (eq_attr "type" "call")
638 (eq_attr "jal_macro" "no"))
639 [(eq_attr "can_delay" "yes")
643 ;; Pipeline descriptions.
645 ;; generic.md provides a fallback for processors without a specific
646 ;; pipeline description. It is derived from the old define_function_unit
647 ;; version and uses the "alu" and "imuldiv" units declared below.
649 ;; Some of the processor-specific files are also derived from old
650 ;; define_function_unit descriptions and simply override the parts of
651 ;; generic.md that don't apply. The other processor-specific files
652 ;; are self-contained.
653 (define_automaton "alu,imuldiv")
655 (define_cpu_unit "alu" "alu")
656 (define_cpu_unit "imuldiv" "imuldiv")
677 (include "generic.md")
680 ;; ....................
684 ;; ....................
688 [(trap_if (const_int 1) (const_int 0))]
691 if (ISA_HAS_COND_TRAP)
693 else if (TARGET_MIPS16)
698 [(set_attr "type" "trap")])
700 (define_expand "conditional_trap"
701 [(trap_if (match_operator 0 "comparison_operator"
702 [(match_dup 2) (match_dup 3)])
703 (match_operand 1 "const_int_operand"))]
706 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
707 && operands[1] == const0_rtx)
709 mips_gen_conditional_trap (operands);
716 (define_insn "*conditional_trap<mode>"
717 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
718 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
719 (match_operand:GPR 2 "arith_operand" "dI")])
723 [(set_attr "type" "trap")])
726 ;; ....................
730 ;; ....................
733 (define_insn "add<mode>3"
734 [(set (match_operand:ANYF 0 "register_operand" "=f")
735 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
736 (match_operand:ANYF 2 "register_operand" "f")))]
738 "add.<fmt>\t%0,%1,%2"
739 [(set_attr "type" "fadd")
740 (set_attr "mode" "<UNITMODE>")])
742 (define_expand "add<mode>3"
743 [(set (match_operand:GPR 0 "register_operand")
744 (plus:GPR (match_operand:GPR 1 "register_operand")
745 (match_operand:GPR 2 "arith_operand")))]
748 (define_insn "*add<mode>3"
749 [(set (match_operand:GPR 0 "register_operand" "=d,d")
750 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
751 (match_operand:GPR 2 "arith_operand" "d,Q")))]
756 [(set_attr "type" "arith")
757 (set_attr "mode" "<MODE>")])
759 (define_insn "*add<mode>3_mips16"
760 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
761 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
762 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
770 [(set_attr "type" "arith")
771 (set_attr "mode" "<MODE>")
772 (set_attr_alternative "length"
773 [(if_then_else (match_operand 2 "m16_simm8_8")
776 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
779 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
782 (if_then_else (match_operand 2 "m16_simm4_1")
787 ;; On the mips16, we can sometimes split an add of a constant which is
788 ;; a 4 byte instruction into two adds which are both 2 byte
789 ;; instructions. There are two cases: one where we are adding a
790 ;; constant plus a register to another register, and one where we are
791 ;; simply adding a constant to a register.
794 [(set (match_operand:SI 0 "register_operand")
795 (plus:SI (match_dup 0)
796 (match_operand:SI 1 "const_int_operand")))]
797 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
798 && REG_P (operands[0])
799 && M16_REG_P (REGNO (operands[0]))
800 && GET_CODE (operands[1]) == CONST_INT
801 && ((INTVAL (operands[1]) > 0x7f
802 && INTVAL (operands[1]) <= 0x7f + 0x7f)
803 || (INTVAL (operands[1]) < - 0x80
804 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
805 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
806 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
808 HOST_WIDE_INT val = INTVAL (operands[1]);
812 operands[1] = GEN_INT (0x7f);
813 operands[2] = GEN_INT (val - 0x7f);
817 operands[1] = GEN_INT (- 0x80);
818 operands[2] = GEN_INT (val + 0x80);
823 [(set (match_operand:SI 0 "register_operand")
824 (plus:SI (match_operand:SI 1 "register_operand")
825 (match_operand:SI 2 "const_int_operand")))]
826 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
827 && REG_P (operands[0])
828 && M16_REG_P (REGNO (operands[0]))
829 && REG_P (operands[1])
830 && M16_REG_P (REGNO (operands[1]))
831 && REGNO (operands[0]) != REGNO (operands[1])
832 && GET_CODE (operands[2]) == CONST_INT
833 && ((INTVAL (operands[2]) > 0x7
834 && INTVAL (operands[2]) <= 0x7 + 0x7f)
835 || (INTVAL (operands[2]) < - 0x8
836 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
837 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
838 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
840 HOST_WIDE_INT val = INTVAL (operands[2]);
844 operands[2] = GEN_INT (0x7);
845 operands[3] = GEN_INT (val - 0x7);
849 operands[2] = GEN_INT (- 0x8);
850 operands[3] = GEN_INT (val + 0x8);
855 [(set (match_operand:DI 0 "register_operand")
856 (plus:DI (match_dup 0)
857 (match_operand:DI 1 "const_int_operand")))]
858 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
859 && REG_P (operands[0])
860 && M16_REG_P (REGNO (operands[0]))
861 && GET_CODE (operands[1]) == CONST_INT
862 && ((INTVAL (operands[1]) > 0xf
863 && INTVAL (operands[1]) <= 0xf + 0xf)
864 || (INTVAL (operands[1]) < - 0x10
865 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
866 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
867 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
869 HOST_WIDE_INT val = INTVAL (operands[1]);
873 operands[1] = GEN_INT (0xf);
874 operands[2] = GEN_INT (val - 0xf);
878 operands[1] = GEN_INT (- 0x10);
879 operands[2] = GEN_INT (val + 0x10);
884 [(set (match_operand:DI 0 "register_operand")
885 (plus:DI (match_operand:DI 1 "register_operand")
886 (match_operand:DI 2 "const_int_operand")))]
887 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
888 && REG_P (operands[0])
889 && M16_REG_P (REGNO (operands[0]))
890 && REG_P (operands[1])
891 && M16_REG_P (REGNO (operands[1]))
892 && REGNO (operands[0]) != REGNO (operands[1])
893 && GET_CODE (operands[2]) == CONST_INT
894 && ((INTVAL (operands[2]) > 0x7
895 && INTVAL (operands[2]) <= 0x7 + 0xf)
896 || (INTVAL (operands[2]) < - 0x8
897 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
898 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
899 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
901 HOST_WIDE_INT val = INTVAL (operands[2]);
905 operands[2] = GEN_INT (0x7);
906 operands[3] = GEN_INT (val - 0x7);
910 operands[2] = GEN_INT (- 0x8);
911 operands[3] = GEN_INT (val + 0x8);
915 (define_insn "*addsi3_extended"
916 [(set (match_operand:DI 0 "register_operand" "=d,d")
918 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
919 (match_operand:SI 2 "arith_operand" "d,Q"))))]
920 "TARGET_64BIT && !TARGET_MIPS16"
924 [(set_attr "type" "arith")
925 (set_attr "mode" "SI")])
927 ;; Split this insn so that the addiu splitters can have a crack at it.
928 ;; Use a conservative length estimate until the split.
929 (define_insn_and_split "*addsi3_extended_mips16"
930 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
932 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
933 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
934 "TARGET_64BIT && TARGET_MIPS16"
936 "&& reload_completed"
937 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
938 { operands[3] = gen_lowpart (SImode, operands[0]); }
939 [(set_attr "type" "arith")
940 (set_attr "mode" "SI")
941 (set_attr "extended_mips16" "yes")])
944 ;; ....................
948 ;; ....................
951 (define_insn "sub<mode>3"
952 [(set (match_operand:ANYF 0 "register_operand" "=f")
953 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
954 (match_operand:ANYF 2 "register_operand" "f")))]
956 "sub.<fmt>\t%0,%1,%2"
957 [(set_attr "type" "fadd")
958 (set_attr "mode" "<UNITMODE>")])
960 (define_insn "sub<mode>3"
961 [(set (match_operand:GPR 0 "register_operand" "=d")
962 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
963 (match_operand:GPR 2 "register_operand" "d")))]
966 [(set_attr "type" "arith")
967 (set_attr "mode" "<MODE>")])
969 (define_insn "*subsi3_extended"
970 [(set (match_operand:DI 0 "register_operand" "=d")
972 (minus:SI (match_operand:SI 1 "register_operand" "d")
973 (match_operand:SI 2 "register_operand" "d"))))]
976 [(set_attr "type" "arith")
977 (set_attr "mode" "DI")])
980 ;; ....................
984 ;; ....................
987 (define_expand "mul<mode>3"
988 [(set (match_operand:SCALARF 0 "register_operand")
989 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
990 (match_operand:SCALARF 2 "register_operand")))]
994 (define_insn "*mul<mode>3"
995 [(set (match_operand:SCALARF 0 "register_operand" "=f")
996 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
997 (match_operand:SCALARF 2 "register_operand" "f")))]
998 "!TARGET_4300_MUL_FIX"
999 "mul.<fmt>\t%0,%1,%2"
1000 [(set_attr "type" "fmul")
1001 (set_attr "mode" "<MODE>")])
1003 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1004 ;; operands may corrupt immediately following multiplies. This is a
1005 ;; simple fix to insert NOPs.
1007 (define_insn "*mul<mode>3_r4300"
1008 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1009 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1010 (match_operand:SCALARF 2 "register_operand" "f")))]
1011 "TARGET_4300_MUL_FIX"
1012 "mul.<fmt>\t%0,%1,%2\;nop"
1013 [(set_attr "type" "fmul")
1014 (set_attr "mode" "<MODE>")
1015 (set_attr "length" "8")])
1017 (define_insn "mulv2sf3"
1018 [(set (match_operand:V2SF 0 "register_operand" "=f")
1019 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1020 (match_operand:V2SF 2 "register_operand" "f")))]
1021 "TARGET_PAIRED_SINGLE_FLOAT"
1023 [(set_attr "type" "fmul")
1024 (set_attr "mode" "SF")])
1026 ;; The original R4000 has a cpu bug. If a double-word or a variable
1027 ;; shift executes while an integer multiplication is in progress, the
1028 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1029 ;; with the mult on the R4000.
1031 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1032 ;; (also valid for MIPS R4000MC processors):
1034 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1035 ;; this errata description.
1036 ;; The following code sequence causes the R4000 to incorrectly
1037 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1038 ;; instruction. If the dsra32 instruction is executed during an
1039 ;; integer multiply, the dsra32 will only shift by the amount in
1040 ;; specified in the instruction rather than the amount plus 32
1042 ;; instruction 1: mult rs,rt integer multiply
1043 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1044 ;; right arithmetic + 32
1045 ;; Workaround: A dsra32 instruction placed after an integer
1046 ;; multiply should not be one of the 11 instructions after the
1047 ;; multiply instruction."
1051 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1052 ;; the following description.
1053 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1054 ;; 64-bit versions) may produce incorrect results under the
1055 ;; following conditions:
1056 ;; 1) An integer multiply is currently executing
1057 ;; 2) These types of shift instructions are executed immediately
1058 ;; following an integer divide instruction.
1060 ;; 1) Make sure no integer multiply is running wihen these
1061 ;; instruction are executed. If this cannot be predicted at
1062 ;; compile time, then insert a "mfhi" to R0 instruction
1063 ;; immediately after the integer multiply instruction. This
1064 ;; will cause the integer multiply to complete before the shift
1066 ;; 2) Separate integer divide and these two classes of shift
1067 ;; instructions by another instruction or a noop."
1069 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1072 (define_expand "mulsi3"
1073 [(set (match_operand:SI 0 "register_operand")
1074 (mult:SI (match_operand:SI 1 "register_operand")
1075 (match_operand:SI 2 "register_operand")))]
1079 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1080 else if (TARGET_FIX_R4000)
1081 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1083 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1087 (define_expand "muldi3"
1088 [(set (match_operand:DI 0 "register_operand")
1089 (mult:DI (match_operand:DI 1 "register_operand")
1090 (match_operand:DI 2 "register_operand")))]
1093 if (TARGET_FIX_R4000)
1094 emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
1096 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1100 (define_insn "mulsi3_mult3"
1101 [(set (match_operand:SI 0 "register_operand" "=d,l")
1102 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1103 (match_operand:SI 2 "register_operand" "d,d")))
1104 (clobber (match_scratch:SI 3 "=h,h"))
1105 (clobber (match_scratch:SI 4 "=l,X"))]
1108 if (which_alternative == 1)
1109 return "mult\t%1,%2";
1110 if (TARGET_MIPS3900)
1111 return "mult\t%0,%1,%2";
1112 return "mul\t%0,%1,%2";
1114 [(set_attr "type" "imul3,imul")
1115 (set_attr "mode" "SI")])
1117 ;; If a register gets allocated to LO, and we spill to memory, the reload
1118 ;; will include a move from LO to a GPR. Merge it into the multiplication
1119 ;; if it can set the GPR directly.
1122 ;; Operand 1: GPR (1st multiplication operand)
1123 ;; Operand 2: GPR (2nd multiplication operand)
1125 ;; Operand 4: GPR (destination)
1128 [(set (match_operand:SI 0 "register_operand")
1129 (mult:SI (match_operand:SI 1 "register_operand")
1130 (match_operand:SI 2 "register_operand")))
1131 (clobber (match_operand:SI 3 "register_operand"))
1132 (clobber (scratch:SI))])
1133 (set (match_operand:SI 4 "register_operand")
1134 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1135 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1138 (mult:SI (match_dup 1)
1140 (clobber (match_dup 3))
1141 (clobber (match_dup 0))])])
1143 (define_insn "mul<mode>3_internal"
1144 [(set (match_operand:GPR 0 "register_operand" "=l")
1145 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1146 (match_operand:GPR 2 "register_operand" "d")))
1147 (clobber (match_scratch:GPR 3 "=h"))]
1150 [(set_attr "type" "imul")
1151 (set_attr "mode" "<MODE>")])
1153 (define_insn "mul<mode>3_r4000"
1154 [(set (match_operand:GPR 0 "register_operand" "=d")
1155 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1156 (match_operand:GPR 2 "register_operand" "d")))
1157 (clobber (match_scratch:GPR 3 "=h"))
1158 (clobber (match_scratch:GPR 4 "=l"))]
1160 "<d>mult\t%1,%2\;mflo\t%0"
1161 [(set_attr "type" "imul")
1162 (set_attr "mode" "<MODE>")
1163 (set_attr "length" "8")])
1165 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1166 ;; of "mult; mflo". They have the same latency, but the first form gives
1167 ;; us an extra cycle to compute the operands.
1170 ;; Operand 1: GPR (1st multiplication operand)
1171 ;; Operand 2: GPR (2nd multiplication operand)
1173 ;; Operand 4: GPR (destination)
1176 [(set (match_operand:SI 0 "register_operand")
1177 (mult:SI (match_operand:SI 1 "register_operand")
1178 (match_operand:SI 2 "register_operand")))
1179 (clobber (match_operand:SI 3 "register_operand"))])
1180 (set (match_operand:SI 4 "register_operand")
1181 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1182 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1187 (plus:SI (mult:SI (match_dup 1)
1191 (plus:SI (mult:SI (match_dup 1)
1194 (clobber (match_dup 3))])])
1196 ;; Multiply-accumulate patterns
1198 ;; For processors that can copy the output to a general register:
1200 ;; The all-d alternative is needed because the combiner will find this
1201 ;; pattern and then register alloc/reload will move registers around to
1202 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1204 ;; The last alternative should be made slightly less desirable, but adding
1205 ;; "?" to the constraint is too strong, and causes values to be loaded into
1206 ;; LO even when that's more costly. For now, using "*d" mostly does the
1208 (define_insn "*mul_acc_si"
1209 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1210 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1211 (match_operand:SI 2 "register_operand" "d,d,d"))
1212 (match_operand:SI 3 "register_operand" "0,l,*d")))
1213 (clobber (match_scratch:SI 4 "=h,h,h"))
1214 (clobber (match_scratch:SI 5 "=X,3,l"))
1215 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1217 || GENERATE_MADD_MSUB)
1220 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1221 if (which_alternative == 2)
1223 if (GENERATE_MADD_MSUB && which_alternative != 0)
1225 return madd[which_alternative];
1227 [(set_attr "type" "imadd")
1228 (set_attr "mode" "SI")
1229 (set_attr "length" "4,4,8")])
1231 ;; Split the above insn if we failed to get LO allocated.
1233 [(set (match_operand:SI 0 "register_operand")
1234 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1235 (match_operand:SI 2 "register_operand"))
1236 (match_operand:SI 3 "register_operand")))
1237 (clobber (match_scratch:SI 4))
1238 (clobber (match_scratch:SI 5))
1239 (clobber (match_scratch:SI 6))]
1240 "reload_completed && !TARGET_DEBUG_D_MODE
1241 && GP_REG_P (true_regnum (operands[0]))
1242 && GP_REG_P (true_regnum (operands[3]))"
1243 [(parallel [(set (match_dup 6)
1244 (mult:SI (match_dup 1) (match_dup 2)))
1245 (clobber (match_dup 4))
1246 (clobber (match_dup 5))])
1247 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1250 ;; Splitter to copy result of MADD to a general register
1252 [(set (match_operand:SI 0 "register_operand")
1253 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1254 (match_operand:SI 2 "register_operand"))
1255 (match_operand:SI 3 "register_operand")))
1256 (clobber (match_scratch:SI 4))
1257 (clobber (match_scratch:SI 5))
1258 (clobber (match_scratch:SI 6))]
1259 "reload_completed && !TARGET_DEBUG_D_MODE
1260 && GP_REG_P (true_regnum (operands[0]))
1261 && true_regnum (operands[3]) == LO_REGNUM"
1262 [(parallel [(set (match_dup 3)
1263 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1265 (clobber (match_dup 4))
1266 (clobber (match_dup 5))
1267 (clobber (match_dup 6))])
1268 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1271 (define_insn "*macc"
1272 [(set (match_operand:SI 0 "register_operand" "=l,d")
1273 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1274 (match_operand:SI 2 "register_operand" "d,d"))
1275 (match_operand:SI 3 "register_operand" "0,l")))
1276 (clobber (match_scratch:SI 4 "=h,h"))
1277 (clobber (match_scratch:SI 5 "=X,3"))]
1280 if (which_alternative == 1)
1281 return "macc\t%0,%1,%2";
1282 else if (TARGET_MIPS5500)
1283 return "madd\t%1,%2";
1285 /* The VR4130 assumes that there is a two-cycle latency between a macc
1286 that "writes" to $0 and an instruction that reads from it. We avoid
1287 this by assigning to $1 instead. */
1288 return "%[macc\t%@,%1,%2%]";
1290 [(set_attr "type" "imadd")
1291 (set_attr "mode" "SI")])
1293 (define_insn "*msac"
1294 [(set (match_operand:SI 0 "register_operand" "=l,d")
1295 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1296 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1297 (match_operand:SI 3 "register_operand" "d,d"))))
1298 (clobber (match_scratch:SI 4 "=h,h"))
1299 (clobber (match_scratch:SI 5 "=X,1"))]
1302 if (which_alternative == 1)
1303 return "msac\t%0,%2,%3";
1304 else if (TARGET_MIPS5500)
1305 return "msub\t%2,%3";
1307 return "msac\t$0,%2,%3";
1309 [(set_attr "type" "imadd")
1310 (set_attr "mode" "SI")])
1312 ;; An msac-like instruction implemented using negation and a macc.
1313 (define_insn_and_split "*msac_using_macc"
1314 [(set (match_operand:SI 0 "register_operand" "=l,d")
1315 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1316 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1317 (match_operand:SI 3 "register_operand" "d,d"))))
1318 (clobber (match_scratch:SI 4 "=h,h"))
1319 (clobber (match_scratch:SI 5 "=X,1"))
1320 (clobber (match_scratch:SI 6 "=d,d"))]
1321 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1323 "&& reload_completed"
1325 (neg:SI (match_dup 3)))
1328 (plus:SI (mult:SI (match_dup 2)
1331 (clobber (match_dup 4))
1332 (clobber (match_dup 5))])]
1334 [(set_attr "type" "imadd")
1335 (set_attr "length" "8")])
1337 ;; Patterns generated by the define_peephole2 below.
1339 (define_insn "*macc2"
1340 [(set (match_operand:SI 0 "register_operand" "=l")
1341 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1342 (match_operand:SI 2 "register_operand" "d"))
1344 (set (match_operand:SI 3 "register_operand" "=d")
1345 (plus:SI (mult:SI (match_dup 1)
1348 (clobber (match_scratch:SI 4 "=h"))]
1349 "ISA_HAS_MACC && reload_completed"
1351 [(set_attr "type" "imadd")
1352 (set_attr "mode" "SI")])
1354 (define_insn "*msac2"
1355 [(set (match_operand:SI 0 "register_operand" "=l")
1356 (minus:SI (match_dup 0)
1357 (mult:SI (match_operand:SI 1 "register_operand" "d")
1358 (match_operand:SI 2 "register_operand" "d"))))
1359 (set (match_operand:SI 3 "register_operand" "=d")
1360 (minus:SI (match_dup 0)
1361 (mult:SI (match_dup 1)
1363 (clobber (match_scratch:SI 4 "=h"))]
1364 "ISA_HAS_MSAC && reload_completed"
1366 [(set_attr "type" "imadd")
1367 (set_attr "mode" "SI")])
1369 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1373 ;; Operand 1: macc/msac
1375 ;; Operand 3: GPR (destination)
1378 [(set (match_operand:SI 0 "register_operand")
1379 (match_operand:SI 1 "macc_msac_operand"))
1380 (clobber (match_operand:SI 2 "register_operand"))
1381 (clobber (scratch:SI))])
1382 (set (match_operand:SI 3 "register_operand")
1383 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1385 [(parallel [(set (match_dup 0)
1389 (clobber (match_dup 2))])]
1392 ;; When we have a three-address multiplication instruction, it should
1393 ;; be faster to do a separate multiply and add, rather than moving
1394 ;; something into LO in order to use a macc instruction.
1396 ;; This peephole needs a scratch register to cater for the case when one
1397 ;; of the multiplication operands is the same as the destination.
1399 ;; Operand 0: GPR (scratch)
1401 ;; Operand 2: GPR (addend)
1402 ;; Operand 3: GPR (destination)
1403 ;; Operand 4: macc/msac
1405 ;; Operand 6: new multiplication
1406 ;; Operand 7: new addition/subtraction
1408 [(match_scratch:SI 0 "d")
1409 (set (match_operand:SI 1 "register_operand")
1410 (match_operand:SI 2 "register_operand"))
1413 [(set (match_operand:SI 3 "register_operand")
1414 (match_operand:SI 4 "macc_msac_operand"))
1415 (clobber (match_operand:SI 5 "register_operand"))
1416 (clobber (match_dup 1))])]
1418 && true_regnum (operands[1]) == LO_REGNUM
1419 && peep2_reg_dead_p (2, operands[1])
1420 && GP_REG_P (true_regnum (operands[3]))"
1421 [(parallel [(set (match_dup 0)
1423 (clobber (match_dup 5))
1424 (clobber (match_dup 1))])
1428 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1429 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1430 operands[2], operands[0]);
1433 ;; Same as above, except LO is the initial target of the macc.
1435 ;; Operand 0: GPR (scratch)
1437 ;; Operand 2: GPR (addend)
1438 ;; Operand 3: macc/msac
1440 ;; Operand 5: GPR (destination)
1441 ;; Operand 6: new multiplication
1442 ;; Operand 7: new addition/subtraction
1444 [(match_scratch:SI 0 "d")
1445 (set (match_operand:SI 1 "register_operand")
1446 (match_operand:SI 2 "register_operand"))
1450 (match_operand:SI 3 "macc_msac_operand"))
1451 (clobber (match_operand:SI 4 "register_operand"))
1452 (clobber (scratch:SI))])
1454 (set (match_operand:SI 5 "register_operand")
1455 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1456 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1457 [(parallel [(set (match_dup 0)
1459 (clobber (match_dup 4))
1460 (clobber (match_dup 1))])
1464 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1465 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1466 operands[2], operands[0]);
1469 (define_insn "*mul_sub_si"
1470 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1471 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1472 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1473 (match_operand:SI 3 "register_operand" "d,d,d"))))
1474 (clobber (match_scratch:SI 4 "=h,h,h"))
1475 (clobber (match_scratch:SI 5 "=X,1,l"))
1476 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1477 "GENERATE_MADD_MSUB"
1482 [(set_attr "type" "imadd")
1483 (set_attr "mode" "SI")
1484 (set_attr "length" "4,8,8")])
1486 ;; Split the above insn if we failed to get LO allocated.
1488 [(set (match_operand:SI 0 "register_operand")
1489 (minus:SI (match_operand:SI 1 "register_operand")
1490 (mult:SI (match_operand:SI 2 "register_operand")
1491 (match_operand:SI 3 "register_operand"))))
1492 (clobber (match_scratch:SI 4))
1493 (clobber (match_scratch:SI 5))
1494 (clobber (match_scratch:SI 6))]
1495 "reload_completed && !TARGET_DEBUG_D_MODE
1496 && GP_REG_P (true_regnum (operands[0]))
1497 && GP_REG_P (true_regnum (operands[1]))"
1498 [(parallel [(set (match_dup 6)
1499 (mult:SI (match_dup 2) (match_dup 3)))
1500 (clobber (match_dup 4))
1501 (clobber (match_dup 5))])
1502 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1505 ;; Splitter to copy result of MSUB to a general register
1507 [(set (match_operand:SI 0 "register_operand")
1508 (minus:SI (match_operand:SI 1 "register_operand")
1509 (mult:SI (match_operand:SI 2 "register_operand")
1510 (match_operand:SI 3 "register_operand"))))
1511 (clobber (match_scratch:SI 4))
1512 (clobber (match_scratch:SI 5))
1513 (clobber (match_scratch:SI 6))]
1514 "reload_completed && !TARGET_DEBUG_D_MODE
1515 && GP_REG_P (true_regnum (operands[0]))
1516 && true_regnum (operands[1]) == LO_REGNUM"
1517 [(parallel [(set (match_dup 1)
1518 (minus:SI (match_dup 1)
1519 (mult:SI (match_dup 2) (match_dup 3))))
1520 (clobber (match_dup 4))
1521 (clobber (match_dup 5))
1522 (clobber (match_dup 6))])
1523 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1526 (define_insn "*muls"
1527 [(set (match_operand:SI 0 "register_operand" "=l,d")
1528 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1529 (match_operand:SI 2 "register_operand" "d,d"))))
1530 (clobber (match_scratch:SI 3 "=h,h"))
1531 (clobber (match_scratch:SI 4 "=X,l"))]
1536 [(set_attr "type" "imul,imul3")
1537 (set_attr "mode" "SI")])
1539 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1541 (define_expand "<u>mulsidi3"
1543 [(set (match_operand:DI 0 "register_operand")
1544 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1545 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1546 (clobber (scratch:DI))
1547 (clobber (scratch:DI))
1548 (clobber (scratch:DI))])]
1549 "!TARGET_64BIT || !TARGET_FIX_R4000"
1553 if (!TARGET_FIX_R4000)
1554 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1557 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1563 (define_insn "<u>mulsidi3_32bit_internal"
1564 [(set (match_operand:DI 0 "register_operand" "=x")
1565 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1566 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1567 "!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
1569 [(set_attr "type" "imul")
1570 (set_attr "mode" "SI")])
1572 (define_insn "<u>mulsidi3_32bit_r4000"
1573 [(set (match_operand:DI 0 "register_operand" "=d")
1574 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1575 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1576 (clobber (match_scratch:DI 3 "=x"))]
1577 "!TARGET_64BIT && TARGET_FIX_R4000"
1578 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1579 [(set_attr "type" "imul")
1580 (set_attr "mode" "SI")
1581 (set_attr "length" "12")])
1583 (define_insn_and_split "*<u>mulsidi3_64bit"
1584 [(set (match_operand:DI 0 "register_operand" "=d")
1585 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1586 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1587 (clobber (match_scratch:DI 3 "=l"))
1588 (clobber (match_scratch:DI 4 "=h"))
1589 (clobber (match_scratch:DI 5 "=d"))]
1590 "TARGET_64BIT && !TARGET_FIX_R4000"
1592 "&& reload_completed"
1596 (mult:SI (match_dup 1)
1600 (mult:DI (any_extend:DI (match_dup 1))
1601 (any_extend:DI (match_dup 2)))
1604 ;; OP5 <- LO, OP0 <- HI
1605 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1606 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1610 (ashift:DI (match_dup 5)
1613 (lshiftrt:DI (match_dup 5)
1616 ;; Shift OP0 into place.
1618 (ashift:DI (match_dup 0)
1621 ;; OR the two halves together
1623 (ior:DI (match_dup 0)
1626 [(set_attr "type" "imul")
1627 (set_attr "mode" "SI")
1628 (set_attr "length" "24")])
1630 (define_insn "*<u>mulsidi3_64bit_parts"
1631 [(set (match_operand:DI 0 "register_operand" "=l")
1633 (mult:SI (match_operand:SI 2 "register_operand" "d")
1634 (match_operand:SI 3 "register_operand" "d"))))
1635 (set (match_operand:DI 1 "register_operand" "=h")
1637 (mult:DI (any_extend:DI (match_dup 2))
1638 (any_extend:DI (match_dup 3)))
1640 "TARGET_64BIT && !TARGET_FIX_R4000"
1642 [(set_attr "type" "imul")
1643 (set_attr "mode" "SI")])
1645 ;; Widening multiply with negation.
1646 (define_insn "*muls<u>_di"
1647 [(set (match_operand:DI 0 "register_operand" "=x")
1650 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1651 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1652 "!TARGET_64BIT && ISA_HAS_MULS"
1654 [(set_attr "type" "imul")
1655 (set_attr "mode" "SI")])
1657 (define_insn "<u>msubsidi4"
1658 [(set (match_operand:DI 0 "register_operand" "=ka")
1660 (match_operand:DI 3 "register_operand" "0")
1662 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1663 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1664 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || TARGET_DSPR2)"
1667 return "msub<u>\t%q0,%1,%2";
1668 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1669 return "msub<u>\t%1,%2";
1671 return "msac<u>\t$0,%1,%2";
1673 [(set_attr "type" "imadd")
1674 (set_attr "mode" "SI")])
1676 ;; _highpart patterns
1678 (define_expand "<su>mulsi3_highpart"
1679 [(set (match_operand:SI 0 "register_operand")
1682 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1683 (any_extend:DI (match_operand:SI 2 "register_operand")))
1685 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1688 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1692 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1697 (define_insn "<su>mulsi3_highpart_internal"
1698 [(set (match_operand:SI 0 "register_operand" "=h")
1701 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1702 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1704 (clobber (match_scratch:SI 3 "=l"))]
1705 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1707 [(set_attr "type" "imul")
1708 (set_attr "mode" "SI")])
1710 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1711 [(set (match_operand:SI 0 "register_operand" "=h,d")
1715 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1716 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1718 (clobber (match_scratch:SI 3 "=l,l"))
1719 (clobber (match_scratch:SI 4 "=X,h"))]
1724 [(set_attr "type" "imul,imul3")
1725 (set_attr "mode" "SI")])
1727 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1728 [(set (match_operand:SI 0 "register_operand" "=h,d")
1733 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1734 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1736 (clobber (match_scratch:SI 3 "=l,l"))
1737 (clobber (match_scratch:SI 4 "=X,h"))]
1741 mulshi<u>\t%0,%1,%2"
1742 [(set_attr "type" "imul,imul3")
1743 (set_attr "mode" "SI")])
1745 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1746 ;; errata MD(0), which says that dmultu does not always produce the
1748 (define_insn "<su>muldi3_highpart"
1749 [(set (match_operand:DI 0 "register_operand" "=h")
1753 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1754 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1756 (clobber (match_scratch:DI 3 "=l"))]
1757 "TARGET_64BIT && !TARGET_FIX_R4000
1758 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1760 [(set_attr "type" "imul")
1761 (set_attr "mode" "DI")])
1763 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
1764 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
1766 (define_insn "madsi"
1767 [(set (match_operand:SI 0 "register_operand" "+l")
1768 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1769 (match_operand:SI 2 "register_operand" "d"))
1771 (clobber (match_scratch:SI 3 "=h"))]
1774 [(set_attr "type" "imadd")
1775 (set_attr "mode" "SI")])
1777 (define_insn "<u>maddsidi4"
1778 [(set (match_operand:DI 0 "register_operand" "=ka")
1780 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1781 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1782 (match_operand:DI 3 "register_operand" "0")))]
1783 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || TARGET_DSPR2)
1787 return "mad<u>\t%1,%2";
1788 else if (TARGET_DSPR2)
1789 return "madd<u>\t%q0,%1,%2";
1790 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
1791 return "madd<u>\t%1,%2";
1793 /* See comment in *macc. */
1794 return "%[macc<u>\t%@,%1,%2%]";
1796 [(set_attr "type" "imadd")
1797 (set_attr "mode" "SI")])
1799 ;; Floating point multiply accumulate instructions.
1801 (define_insn "*madd<mode>"
1802 [(set (match_operand:ANYF 0 "register_operand" "=f")
1803 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1804 (match_operand:ANYF 2 "register_operand" "f"))
1805 (match_operand:ANYF 3 "register_operand" "f")))]
1806 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1807 "madd.<fmt>\t%0,%3,%1,%2"
1808 [(set_attr "type" "fmadd")
1809 (set_attr "mode" "<UNITMODE>")])
1811 (define_insn "*msub<mode>"
1812 [(set (match_operand:ANYF 0 "register_operand" "=f")
1813 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1814 (match_operand:ANYF 2 "register_operand" "f"))
1815 (match_operand:ANYF 3 "register_operand" "f")))]
1816 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1817 "msub.<fmt>\t%0,%3,%1,%2"
1818 [(set_attr "type" "fmadd")
1819 (set_attr "mode" "<UNITMODE>")])
1821 (define_insn "*nmadd<mode>"
1822 [(set (match_operand:ANYF 0 "register_operand" "=f")
1823 (neg:ANYF (plus:ANYF
1824 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1825 (match_operand:ANYF 2 "register_operand" "f"))
1826 (match_operand:ANYF 3 "register_operand" "f"))))]
1827 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1828 && HONOR_SIGNED_ZEROS (<MODE>mode)
1829 && !HONOR_NANS (<MODE>mode)"
1830 "nmadd.<fmt>\t%0,%3,%1,%2"
1831 [(set_attr "type" "fmadd")
1832 (set_attr "mode" "<UNITMODE>")])
1834 (define_insn "*nmadd<mode>_fastmath"
1835 [(set (match_operand:ANYF 0 "register_operand" "=f")
1837 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1838 (match_operand:ANYF 2 "register_operand" "f"))
1839 (match_operand:ANYF 3 "register_operand" "f")))]
1840 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1841 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1842 && !HONOR_NANS (<MODE>mode)"
1843 "nmadd.<fmt>\t%0,%3,%1,%2"
1844 [(set_attr "type" "fmadd")
1845 (set_attr "mode" "<UNITMODE>")])
1847 (define_insn "*nmsub<mode>"
1848 [(set (match_operand:ANYF 0 "register_operand" "=f")
1849 (neg:ANYF (minus:ANYF
1850 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1851 (match_operand:ANYF 3 "register_operand" "f"))
1852 (match_operand:ANYF 1 "register_operand" "f"))))]
1853 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1854 && HONOR_SIGNED_ZEROS (<MODE>mode)
1855 && !HONOR_NANS (<MODE>mode)"
1856 "nmsub.<fmt>\t%0,%1,%2,%3"
1857 [(set_attr "type" "fmadd")
1858 (set_attr "mode" "<UNITMODE>")])
1860 (define_insn "*nmsub<mode>_fastmath"
1861 [(set (match_operand:ANYF 0 "register_operand" "=f")
1863 (match_operand:ANYF 1 "register_operand" "f")
1864 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1865 (match_operand:ANYF 3 "register_operand" "f"))))]
1866 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1867 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1868 && !HONOR_NANS (<MODE>mode)"
1869 "nmsub.<fmt>\t%0,%1,%2,%3"
1870 [(set_attr "type" "fmadd")
1871 (set_attr "mode" "<UNITMODE>")])
1874 ;; ....................
1876 ;; DIVISION and REMAINDER
1878 ;; ....................
1881 (define_expand "div<mode>3"
1882 [(set (match_operand:ANYF 0 "register_operand")
1883 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1884 (match_operand:ANYF 2 "register_operand")))]
1885 "<divide_condition>"
1887 if (const_1_operand (operands[1], <MODE>mode))
1888 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1889 operands[1] = force_reg (<MODE>mode, operands[1]);
1892 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1894 ;; If an mfc1 or dmfc1 happens to access the floating point register
1895 ;; file at the same time a long latency operation (div, sqrt, recip,
1896 ;; sqrt) iterates an intermediate result back through the floating
1897 ;; point register file bypass, then instead returning the correct
1898 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1899 ;; result of the long latency operation.
1901 ;; The workaround is to insert an unconditional 'mov' from/to the
1902 ;; long latency op destination register.
1904 (define_insn "*div<mode>3"
1905 [(set (match_operand:ANYF 0 "register_operand" "=f")
1906 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1907 (match_operand:ANYF 2 "register_operand" "f")))]
1908 "<divide_condition>"
1911 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1913 return "div.<fmt>\t%0,%1,%2";
1915 [(set_attr "type" "fdiv")
1916 (set_attr "mode" "<UNITMODE>")
1917 (set (attr "length")
1918 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1922 (define_insn "*recip<mode>3"
1923 [(set (match_operand:ANYF 0 "register_operand" "=f")
1924 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1925 (match_operand:ANYF 2 "register_operand" "f")))]
1926 "<recip_condition> && flag_unsafe_math_optimizations"
1929 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1931 return "recip.<fmt>\t%0,%2";
1933 [(set_attr "type" "frdiv")
1934 (set_attr "mode" "<UNITMODE>")
1935 (set (attr "length")
1936 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1940 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1941 ;; with negative operands. We use special libgcc functions instead.
1942 (define_insn "divmod<mode>4"
1943 [(set (match_operand:GPR 0 "register_operand" "=l")
1944 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1945 (match_operand:GPR 2 "register_operand" "d")))
1946 (set (match_operand:GPR 3 "register_operand" "=h")
1947 (mod:GPR (match_dup 1)
1949 "!TARGET_FIX_VR4120"
1950 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1951 [(set_attr "type" "idiv")
1952 (set_attr "mode" "<MODE>")])
1954 (define_insn "udivmod<mode>4"
1955 [(set (match_operand:GPR 0 "register_operand" "=l")
1956 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
1957 (match_operand:GPR 2 "register_operand" "d")))
1958 (set (match_operand:GPR 3 "register_operand" "=h")
1959 (umod:GPR (match_dup 1)
1962 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
1963 [(set_attr "type" "idiv")
1964 (set_attr "mode" "<MODE>")])
1967 ;; ....................
1971 ;; ....................
1973 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
1974 ;; "*div[sd]f3" comment for details).
1976 (define_insn "sqrt<mode>2"
1977 [(set (match_operand:ANYF 0 "register_operand" "=f")
1978 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1982 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
1984 return "sqrt.<fmt>\t%0,%1";
1986 [(set_attr "type" "fsqrt")
1987 (set_attr "mode" "<UNITMODE>")
1988 (set (attr "length")
1989 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1993 (define_insn "*rsqrt<mode>a"
1994 [(set (match_operand:ANYF 0 "register_operand" "=f")
1995 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1996 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
1997 "<recip_condition> && flag_unsafe_math_optimizations"
2000 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2002 return "rsqrt.<fmt>\t%0,%2";
2004 [(set_attr "type" "frsqrt")
2005 (set_attr "mode" "<UNITMODE>")
2006 (set (attr "length")
2007 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2011 (define_insn "*rsqrt<mode>b"
2012 [(set (match_operand:ANYF 0 "register_operand" "=f")
2013 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2014 (match_operand:ANYF 2 "register_operand" "f"))))]
2015 "<recip_condition> && flag_unsafe_math_optimizations"
2018 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2020 return "rsqrt.<fmt>\t%0,%2";
2022 [(set_attr "type" "frsqrt")
2023 (set_attr "mode" "<UNITMODE>")
2024 (set (attr "length")
2025 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2030 ;; ....................
2034 ;; ....................
2036 ;; Do not use the integer abs macro instruction, since that signals an
2037 ;; exception on -2147483648 (sigh).
2039 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2040 ;; invalid; it does not clear their sign bits. We therefore can't use
2041 ;; abs.fmt if the signs of NaNs matter.
2043 (define_insn "abs<mode>2"
2044 [(set (match_operand:ANYF 0 "register_operand" "=f")
2045 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2046 "!HONOR_NANS (<MODE>mode)"
2048 [(set_attr "type" "fabs")
2049 (set_attr "mode" "<UNITMODE>")])
2052 ;; ...................
2054 ;; Count leading zeroes.
2056 ;; ...................
2059 (define_insn "clz<mode>2"
2060 [(set (match_operand:GPR 0 "register_operand" "=d")
2061 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2064 [(set_attr "type" "clz")
2065 (set_attr "mode" "<MODE>")])
2068 ;; ....................
2070 ;; NEGATION and ONE'S COMPLEMENT
2072 ;; ....................
2074 (define_insn "negsi2"
2075 [(set (match_operand:SI 0 "register_operand" "=d")
2076 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2080 return "neg\t%0,%1";
2082 return "subu\t%0,%.,%1";
2084 [(set_attr "type" "arith")
2085 (set_attr "mode" "SI")])
2087 (define_insn "negdi2"
2088 [(set (match_operand:DI 0 "register_operand" "=d")
2089 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2090 "TARGET_64BIT && !TARGET_MIPS16"
2092 [(set_attr "type" "arith")
2093 (set_attr "mode" "DI")])
2095 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2096 ;; invalid; it does not flip their sign bit. We therefore can't use
2097 ;; neg.fmt if the signs of NaNs matter.
2099 (define_insn "neg<mode>2"
2100 [(set (match_operand:ANYF 0 "register_operand" "=f")
2101 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2102 "!HONOR_NANS (<MODE>mode)"
2104 [(set_attr "type" "fneg")
2105 (set_attr "mode" "<UNITMODE>")])
2107 (define_insn "one_cmpl<mode>2"
2108 [(set (match_operand:GPR 0 "register_operand" "=d")
2109 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2113 return "not\t%0,%1";
2115 return "nor\t%0,%.,%1";
2117 [(set_attr "type" "logical")
2118 (set_attr "mode" "<MODE>")])
2121 ;; ....................
2125 ;; ....................
2128 ;; Many of these instructions use trivial define_expands, because we
2129 ;; want to use a different set of constraints when TARGET_MIPS16.
2131 (define_expand "and<mode>3"
2132 [(set (match_operand:GPR 0 "register_operand")
2133 (and:GPR (match_operand:GPR 1 "register_operand")
2134 (match_operand:GPR 2 "uns_arith_operand")))]
2138 operands[2] = force_reg (<MODE>mode, operands[2]);
2141 (define_insn "*and<mode>3"
2142 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2143 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2144 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2149 [(set_attr "type" "logical")
2150 (set_attr "mode" "<MODE>")])
2152 (define_insn "*and<mode>3_mips16"
2153 [(set (match_operand:GPR 0 "register_operand" "=d")
2154 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2155 (match_operand:GPR 2 "register_operand" "d")))]
2158 [(set_attr "type" "logical")
2159 (set_attr "mode" "<MODE>")])
2161 (define_expand "ior<mode>3"
2162 [(set (match_operand:GPR 0 "register_operand")
2163 (ior:GPR (match_operand:GPR 1 "register_operand")
2164 (match_operand:GPR 2 "uns_arith_operand")))]
2168 operands[2] = force_reg (<MODE>mode, operands[2]);
2171 (define_insn "*ior<mode>3"
2172 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2173 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2174 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2179 [(set_attr "type" "logical")
2180 (set_attr "mode" "<MODE>")])
2182 (define_insn "*ior<mode>3_mips16"
2183 [(set (match_operand:GPR 0 "register_operand" "=d")
2184 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2185 (match_operand:GPR 2 "register_operand" "d")))]
2188 [(set_attr "type" "logical")
2189 (set_attr "mode" "<MODE>")])
2191 (define_expand "xor<mode>3"
2192 [(set (match_operand:GPR 0 "register_operand")
2193 (xor:GPR (match_operand:GPR 1 "register_operand")
2194 (match_operand:GPR 2 "uns_arith_operand")))]
2199 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2200 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2201 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2206 [(set_attr "type" "logical")
2207 (set_attr "mode" "<MODE>")])
2210 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2211 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2212 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2218 [(set_attr "type" "logical,arith,arith")
2219 (set_attr "mode" "<MODE>")
2220 (set_attr_alternative "length"
2222 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2227 (define_insn "*nor<mode>3"
2228 [(set (match_operand:GPR 0 "register_operand" "=d")
2229 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2230 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2233 [(set_attr "type" "logical")
2234 (set_attr "mode" "<MODE>")])
2237 ;; ....................
2241 ;; ....................
2245 (define_insn "truncdfsf2"
2246 [(set (match_operand:SF 0 "register_operand" "=f")
2247 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2248 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2250 [(set_attr "type" "fcvt")
2251 (set_attr "cnv_mode" "D2S")
2252 (set_attr "mode" "SF")])
2254 ;; Integer truncation patterns. Truncating SImode values to smaller
2255 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2256 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2257 ;; need to make sure that the lower 32 bits are properly sign-extended
2258 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2259 ;; smaller than SImode is equivalent to two separate truncations:
2262 ;; DI ---> HI == DI ---> SI ---> HI
2263 ;; DI ---> QI == DI ---> SI ---> QI
2265 ;; Step A needs a real instruction but step B does not.
2267 (define_insn "truncdisi2"
2268 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2269 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2274 [(set_attr "type" "shift,store")
2275 (set_attr "mode" "SI")
2276 (set_attr "extended_mips16" "yes,*")])
2278 (define_insn "truncdihi2"
2279 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2280 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2285 [(set_attr "type" "shift,store")
2286 (set_attr "mode" "SI")
2287 (set_attr "extended_mips16" "yes,*")])
2289 (define_insn "truncdiqi2"
2290 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2291 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2296 [(set_attr "type" "shift,store")
2297 (set_attr "mode" "SI")
2298 (set_attr "extended_mips16" "yes,*")])
2300 ;; Combiner patterns to optimize shift/truncate combinations.
2303 [(set (match_operand:SI 0 "register_operand" "=d")
2305 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2306 (match_operand:DI 2 "const_arith_operand" ""))))]
2307 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2309 [(set_attr "type" "shift")
2310 (set_attr "mode" "SI")])
2313 [(set (match_operand:SI 0 "register_operand" "=d")
2314 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2316 "TARGET_64BIT && !TARGET_MIPS16"
2318 [(set_attr "type" "shift")
2319 (set_attr "mode" "SI")])
2322 ;; Combiner patterns for truncate/sign_extend combinations. They use
2323 ;; the shift/truncate patterns above.
2325 (define_insn_and_split ""
2326 [(set (match_operand:SI 0 "register_operand" "=d")
2328 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2329 "TARGET_64BIT && !TARGET_MIPS16"
2331 "&& reload_completed"
2333 (ashift:DI (match_dup 1)
2336 (truncate:SI (ashiftrt:DI (match_dup 2)
2338 { operands[2] = gen_lowpart (DImode, operands[0]); })
2340 (define_insn_and_split ""
2341 [(set (match_operand:SI 0 "register_operand" "=d")
2343 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2344 "TARGET_64BIT && !TARGET_MIPS16"
2346 "&& reload_completed"
2348 (ashift:DI (match_dup 1)
2351 (truncate:SI (ashiftrt:DI (match_dup 2)
2353 { operands[2] = gen_lowpart (DImode, operands[0]); })
2356 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2359 [(set (match_operand:SI 0 "register_operand" "=d")
2360 (zero_extend:SI (truncate:HI
2361 (match_operand:DI 1 "register_operand" "d"))))]
2362 "TARGET_64BIT && !TARGET_MIPS16"
2363 "andi\t%0,%1,0xffff"
2364 [(set_attr "type" "logical")
2365 (set_attr "mode" "SI")])
2368 [(set (match_operand:SI 0 "register_operand" "=d")
2369 (zero_extend:SI (truncate:QI
2370 (match_operand:DI 1 "register_operand" "d"))))]
2371 "TARGET_64BIT && !TARGET_MIPS16"
2373 [(set_attr "type" "logical")
2374 (set_attr "mode" "SI")])
2377 [(set (match_operand:HI 0 "register_operand" "=d")
2378 (zero_extend:HI (truncate:QI
2379 (match_operand:DI 1 "register_operand" "d"))))]
2380 "TARGET_64BIT && !TARGET_MIPS16"
2382 [(set_attr "type" "logical")
2383 (set_attr "mode" "HI")])
2386 ;; ....................
2390 ;; ....................
2394 (define_insn_and_split "zero_extendsidi2"
2395 [(set (match_operand:DI 0 "register_operand" "=d,d")
2396 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2401 "&& reload_completed && REG_P (operands[1])"
2403 (ashift:DI (match_dup 1) (const_int 32)))
2405 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2406 { operands[1] = gen_lowpart (DImode, operands[1]); }
2407 [(set_attr "type" "multi,load")
2408 (set_attr "mode" "DI")
2409 (set_attr "length" "8,*")])
2411 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2412 ;; because of TRULY_NOOP_TRUNCATION.
2414 (define_insn_and_split "*clear_upper32"
2415 [(set (match_operand:DI 0 "register_operand" "=d,d")
2416 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2417 (const_int 4294967295)))]
2420 if (which_alternative == 0)
2423 operands[1] = gen_lowpart (SImode, operands[1]);
2424 return "lwu\t%0,%1";
2426 "&& reload_completed && REG_P (operands[1])"
2428 (ashift:DI (match_dup 1) (const_int 32)))
2430 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2432 [(set_attr "type" "multi,load")
2433 (set_attr "mode" "DI")
2434 (set_attr "length" "8,*")])
2436 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2437 [(set (match_operand:GPR 0 "register_operand")
2438 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2441 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2442 && !memory_operand (operands[1], <SHORT:MODE>mode))
2444 emit_insn (gen_and<GPR:mode>3 (operands[0],
2445 gen_lowpart (<GPR:MODE>mode, operands[1]),
2446 force_reg (<GPR:MODE>mode,
2447 GEN_INT (<SHORT:mask>))));
2452 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2453 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2455 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2458 andi\t%0,%1,<SHORT:mask>
2459 l<SHORT:size>u\t%0,%1"
2460 [(set_attr "type" "logical,load")
2461 (set_attr "mode" "<GPR:MODE>")])
2463 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2464 [(set (match_operand:GPR 0 "register_operand" "=d")
2465 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2467 "ze<SHORT:size>\t%0"
2468 [(set_attr "type" "arith")
2469 (set_attr "mode" "<GPR:MODE>")])
2471 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2472 [(set (match_operand:GPR 0 "register_operand" "=d")
2473 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2475 "l<SHORT:size>u\t%0,%1"
2476 [(set_attr "type" "load")
2477 (set_attr "mode" "<GPR:MODE>")])
2479 (define_expand "zero_extendqihi2"
2480 [(set (match_operand:HI 0 "register_operand")
2481 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2484 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2486 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2492 (define_insn "*zero_extendqihi2"
2493 [(set (match_operand:HI 0 "register_operand" "=d,d")
2494 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2499 [(set_attr "type" "logical,load")
2500 (set_attr "mode" "HI")])
2502 (define_insn "*zero_extendqihi2_mips16"
2503 [(set (match_operand:HI 0 "register_operand" "=d")
2504 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2507 [(set_attr "type" "load")
2508 (set_attr "mode" "HI")])
2511 ;; ....................
2515 ;; ....................
2518 ;; Those for integer source operand are ordered widest source type first.
2520 ;; When TARGET_64BIT, all SImode integer registers should already be in
2521 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2522 ;; therefore get rid of register->register instructions if we constrain
2523 ;; the source to be in the same register as the destination.
2525 ;; The register alternative has type "arith" so that the pre-reload
2526 ;; scheduler will treat it as a move. This reflects what happens if
2527 ;; the register alternative needs a reload.
2528 (define_insn_and_split "extendsidi2"
2529 [(set (match_operand:DI 0 "register_operand" "=d,d")
2530 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2535 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2538 emit_note (NOTE_INSN_DELETED);
2541 [(set_attr "type" "arith,load")
2542 (set_attr "mode" "DI")])
2544 (define_expand "extend<SHORT:mode><GPR:mode>2"
2545 [(set (match_operand:GPR 0 "register_operand")
2546 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2549 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2550 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2551 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2555 l<SHORT:size>\t%0,%1"
2556 [(set_attr "type" "signext,load")
2557 (set_attr "mode" "<GPR:MODE>")])
2559 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2560 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2562 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2563 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2566 l<SHORT:size>\t%0,%1"
2567 "&& reload_completed && REG_P (operands[1])"
2568 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2569 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2571 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2572 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2573 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2575 [(set_attr "type" "arith,load")
2576 (set_attr "mode" "<GPR:MODE>")
2577 (set_attr "length" "8,*")])
2579 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2580 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2582 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2585 se<SHORT:size>\t%0,%1
2586 l<SHORT:size>\t%0,%1"
2587 [(set_attr "type" "signext,load")
2588 (set_attr "mode" "<GPR:MODE>")])
2590 (define_expand "extendqihi2"
2591 [(set (match_operand:HI 0 "register_operand")
2592 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2595 (define_insn "*extendqihi2_mips16e"
2596 [(set (match_operand:HI 0 "register_operand" "=d,d")
2597 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
2602 [(set_attr "type" "signext,load")
2603 (set_attr "mode" "SI")])
2605 (define_insn_and_split "*extendqihi2"
2606 [(set (match_operand:HI 0 "register_operand" "=d,d")
2608 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2609 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2613 "&& reload_completed && REG_P (operands[1])"
2614 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
2615 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
2617 operands[0] = gen_lowpart (SImode, operands[0]);
2618 operands[1] = gen_lowpart (SImode, operands[1]);
2619 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
2620 - GET_MODE_BITSIZE (QImode));
2622 [(set_attr "type" "multi,load")
2623 (set_attr "mode" "SI")
2624 (set_attr "length" "8,*")])
2626 (define_insn "*extendqihi2_seb"
2627 [(set (match_operand:HI 0 "register_operand" "=d,d")
2629 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2634 [(set_attr "type" "signext,load")
2635 (set_attr "mode" "SI")])
2637 (define_insn "extendsfdf2"
2638 [(set (match_operand:DF 0 "register_operand" "=f")
2639 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2640 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2642 [(set_attr "type" "fcvt")
2643 (set_attr "cnv_mode" "S2D")
2644 (set_attr "mode" "DF")])
2647 ;; ....................
2651 ;; ....................
2653 (define_expand "fix_truncdfsi2"
2654 [(set (match_operand:SI 0 "register_operand")
2655 (fix:SI (match_operand:DF 1 "register_operand")))]
2656 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2658 if (!ISA_HAS_TRUNC_W)
2660 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2665 (define_insn "fix_truncdfsi2_insn"
2666 [(set (match_operand:SI 0 "register_operand" "=f")
2667 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2668 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2670 [(set_attr "type" "fcvt")
2671 (set_attr "mode" "DF")
2672 (set_attr "cnv_mode" "D2I")
2673 (set_attr "length" "4")])
2675 (define_insn "fix_truncdfsi2_macro"
2676 [(set (match_operand:SI 0 "register_operand" "=f")
2677 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2678 (clobber (match_scratch:DF 2 "=d"))]
2679 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2682 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2684 return "trunc.w.d %0,%1,%2";
2686 [(set_attr "type" "fcvt")
2687 (set_attr "mode" "DF")
2688 (set_attr "cnv_mode" "D2I")
2689 (set_attr "length" "36")])
2691 (define_expand "fix_truncsfsi2"
2692 [(set (match_operand:SI 0 "register_operand")
2693 (fix:SI (match_operand:SF 1 "register_operand")))]
2696 if (!ISA_HAS_TRUNC_W)
2698 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2703 (define_insn "fix_truncsfsi2_insn"
2704 [(set (match_operand:SI 0 "register_operand" "=f")
2705 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2706 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2708 [(set_attr "type" "fcvt")
2709 (set_attr "mode" "SF")
2710 (set_attr "cnv_mode" "S2I")
2711 (set_attr "length" "4")])
2713 (define_insn "fix_truncsfsi2_macro"
2714 [(set (match_operand:SI 0 "register_operand" "=f")
2715 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2716 (clobber (match_scratch:SF 2 "=d"))]
2717 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2720 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2722 return "trunc.w.s %0,%1,%2";
2724 [(set_attr "type" "fcvt")
2725 (set_attr "mode" "SF")
2726 (set_attr "cnv_mode" "S2I")
2727 (set_attr "length" "36")])
2730 (define_insn "fix_truncdfdi2"
2731 [(set (match_operand:DI 0 "register_operand" "=f")
2732 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2733 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2735 [(set_attr "type" "fcvt")
2736 (set_attr "mode" "DF")
2737 (set_attr "cnv_mode" "D2I")
2738 (set_attr "length" "4")])
2741 (define_insn "fix_truncsfdi2"
2742 [(set (match_operand:DI 0 "register_operand" "=f")
2743 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2744 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2746 [(set_attr "type" "fcvt")
2747 (set_attr "mode" "SF")
2748 (set_attr "cnv_mode" "S2I")
2749 (set_attr "length" "4")])
2752 (define_insn "floatsidf2"
2753 [(set (match_operand:DF 0 "register_operand" "=f")
2754 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2755 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2757 [(set_attr "type" "fcvt")
2758 (set_attr "mode" "DF")
2759 (set_attr "cnv_mode" "I2D")
2760 (set_attr "length" "4")])
2763 (define_insn "floatdidf2"
2764 [(set (match_operand:DF 0 "register_operand" "=f")
2765 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2766 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2768 [(set_attr "type" "fcvt")
2769 (set_attr "mode" "DF")
2770 (set_attr "cnv_mode" "I2D")
2771 (set_attr "length" "4")])
2774 (define_insn "floatsisf2"
2775 [(set (match_operand:SF 0 "register_operand" "=f")
2776 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2779 [(set_attr "type" "fcvt")
2780 (set_attr "mode" "SF")
2781 (set_attr "cnv_mode" "I2S")
2782 (set_attr "length" "4")])
2785 (define_insn "floatdisf2"
2786 [(set (match_operand:SF 0 "register_operand" "=f")
2787 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2788 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2790 [(set_attr "type" "fcvt")
2791 (set_attr "mode" "SF")
2792 (set_attr "cnv_mode" "I2S")
2793 (set_attr "length" "4")])
2796 (define_expand "fixuns_truncdfsi2"
2797 [(set (match_operand:SI 0 "register_operand")
2798 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2799 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2801 rtx reg1 = gen_reg_rtx (DFmode);
2802 rtx reg2 = gen_reg_rtx (DFmode);
2803 rtx reg3 = gen_reg_rtx (SImode);
2804 rtx label1 = gen_label_rtx ();
2805 rtx label2 = gen_label_rtx ();
2806 REAL_VALUE_TYPE offset;
2808 real_2expN (&offset, 31);
2810 if (reg1) /* Turn off complaints about unreached code. */
2812 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2813 do_pending_stack_adjust ();
2815 emit_insn (gen_cmpdf (operands[1], reg1));
2816 emit_jump_insn (gen_bge (label1));
2818 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2819 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2820 gen_rtx_LABEL_REF (VOIDmode, label2)));
2823 emit_label (label1);
2824 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2825 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2826 (BITMASK_HIGH, SImode)));
2828 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2829 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2831 emit_label (label2);
2833 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2834 fields, and can't be used for REG_NOTES anyway). */
2835 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2841 (define_expand "fixuns_truncdfdi2"
2842 [(set (match_operand:DI 0 "register_operand")
2843 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2844 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2846 rtx reg1 = gen_reg_rtx (DFmode);
2847 rtx reg2 = gen_reg_rtx (DFmode);
2848 rtx reg3 = gen_reg_rtx (DImode);
2849 rtx label1 = gen_label_rtx ();
2850 rtx label2 = gen_label_rtx ();
2851 REAL_VALUE_TYPE offset;
2853 real_2expN (&offset, 63);
2855 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2856 do_pending_stack_adjust ();
2858 emit_insn (gen_cmpdf (operands[1], reg1));
2859 emit_jump_insn (gen_bge (label1));
2861 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2862 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2863 gen_rtx_LABEL_REF (VOIDmode, label2)));
2866 emit_label (label1);
2867 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2868 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
2869 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2871 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2872 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2874 emit_label (label2);
2876 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2877 fields, and can't be used for REG_NOTES anyway). */
2878 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2883 (define_expand "fixuns_truncsfsi2"
2884 [(set (match_operand:SI 0 "register_operand")
2885 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2888 rtx reg1 = gen_reg_rtx (SFmode);
2889 rtx reg2 = gen_reg_rtx (SFmode);
2890 rtx reg3 = gen_reg_rtx (SImode);
2891 rtx label1 = gen_label_rtx ();
2892 rtx label2 = gen_label_rtx ();
2893 REAL_VALUE_TYPE offset;
2895 real_2expN (&offset, 31);
2897 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2898 do_pending_stack_adjust ();
2900 emit_insn (gen_cmpsf (operands[1], reg1));
2901 emit_jump_insn (gen_bge (label1));
2903 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2904 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2905 gen_rtx_LABEL_REF (VOIDmode, label2)));
2908 emit_label (label1);
2909 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2910 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2911 (BITMASK_HIGH, SImode)));
2913 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2914 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2916 emit_label (label2);
2918 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2919 fields, and can't be used for REG_NOTES anyway). */
2920 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2925 (define_expand "fixuns_truncsfdi2"
2926 [(set (match_operand:DI 0 "register_operand")
2927 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2928 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2930 rtx reg1 = gen_reg_rtx (SFmode);
2931 rtx reg2 = gen_reg_rtx (SFmode);
2932 rtx reg3 = gen_reg_rtx (DImode);
2933 rtx label1 = gen_label_rtx ();
2934 rtx label2 = gen_label_rtx ();
2935 REAL_VALUE_TYPE offset;
2937 real_2expN (&offset, 63);
2939 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2940 do_pending_stack_adjust ();
2942 emit_insn (gen_cmpsf (operands[1], reg1));
2943 emit_jump_insn (gen_bge (label1));
2945 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2946 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2947 gen_rtx_LABEL_REF (VOIDmode, label2)));
2950 emit_label (label1);
2951 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2952 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
2953 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2955 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2956 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2958 emit_label (label2);
2960 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2961 fields, and can't be used for REG_NOTES anyway). */
2962 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2967 ;; ....................
2971 ;; ....................
2973 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
2975 (define_expand "extv"
2976 [(set (match_operand 0 "register_operand")
2977 (sign_extract (match_operand:QI 1 "memory_operand")
2978 (match_operand 2 "immediate_operand")
2979 (match_operand 3 "immediate_operand")))]
2982 if (mips_expand_unaligned_load (operands[0], operands[1],
2983 INTVAL (operands[2]),
2984 INTVAL (operands[3])))
2990 (define_expand "extzv"
2991 [(set (match_operand 0 "register_operand")
2992 (zero_extract (match_operand 1 "nonimmediate_operand")
2993 (match_operand 2 "immediate_operand")
2994 (match_operand 3 "immediate_operand")))]
2997 if (mips_expand_unaligned_load (operands[0], operands[1],
2998 INTVAL (operands[2]),
2999 INTVAL (operands[3])))
3001 else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
3003 if (GET_MODE (operands[0]) == DImode)
3004 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3007 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3015 (define_insn "extzv<mode>"
3016 [(set (match_operand:GPR 0 "register_operand" "=d")
3017 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3018 (match_operand:SI 2 "immediate_operand" "I")
3019 (match_operand:SI 3 "immediate_operand" "I")))]
3020 "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
3021 "<d>ext\t%0,%1,%3,%2"
3022 [(set_attr "type" "arith")
3023 (set_attr "mode" "<MODE>")])
3026 (define_expand "insv"
3027 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3028 (match_operand 1 "immediate_operand")
3029 (match_operand 2 "immediate_operand"))
3030 (match_operand 3 "reg_or_0_operand"))]
3033 if (mips_expand_unaligned_store (operands[0], operands[3],
3034 INTVAL (operands[1]),
3035 INTVAL (operands[2])))
3037 else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
3039 if (GET_MODE (operands[0]) == DImode)
3040 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3043 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3051 (define_insn "insv<mode>"
3052 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3053 (match_operand:SI 1 "immediate_operand" "I")
3054 (match_operand:SI 2 "immediate_operand" "I"))
3055 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3056 "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
3057 "<d>ins\t%0,%z3,%2,%1"
3058 [(set_attr "type" "arith")
3059 (set_attr "mode" "<MODE>")])
3061 ;; Unaligned word moves generated by the bit field patterns.
3063 ;; As far as the rtl is concerned, both the left-part and right-part
3064 ;; instructions can access the whole field. However, the real operand
3065 ;; refers to just the first or the last byte (depending on endianness).
3066 ;; We therefore use two memory operands to each instruction, one to
3067 ;; describe the rtl effect and one to use in the assembly output.
3069 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3070 ;; This allows us to use the standard length calculations for the "load"
3071 ;; and "store" type attributes.
3073 (define_insn "mov_<load>l"
3074 [(set (match_operand:GPR 0 "register_operand" "=d")
3075 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3076 (match_operand:QI 2 "memory_operand" "m")]
3078 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3080 [(set_attr "type" "load")
3081 (set_attr "mode" "<MODE>")])
3083 (define_insn "mov_<load>r"
3084 [(set (match_operand:GPR 0 "register_operand" "=d")
3085 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3086 (match_operand:QI 2 "memory_operand" "m")
3087 (match_operand:GPR 3 "register_operand" "0")]
3088 UNSPEC_LOAD_RIGHT))]
3089 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3091 [(set_attr "type" "load")
3092 (set_attr "mode" "<MODE>")])
3094 (define_insn "mov_<store>l"
3095 [(set (match_operand:BLK 0 "memory_operand" "=m")
3096 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3097 (match_operand:QI 2 "memory_operand" "m")]
3098 UNSPEC_STORE_LEFT))]
3099 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3101 [(set_attr "type" "store")
3102 (set_attr "mode" "<MODE>")])
3104 (define_insn "mov_<store>r"
3105 [(set (match_operand:BLK 0 "memory_operand" "+m")
3106 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3107 (match_operand:QI 2 "memory_operand" "m")
3109 UNSPEC_STORE_RIGHT))]
3110 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3112 [(set_attr "type" "store")
3113 (set_attr "mode" "<MODE>")])
3115 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3116 ;; The required value is:
3118 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3120 ;; which translates to:
3122 ;; lui op0,%highest(op1)
3123 ;; daddiu op0,op0,%higher(op1)
3125 ;; daddiu op0,op0,%hi(op1)
3128 ;; The split is deferred until after flow2 to allow the peephole2 below
3130 (define_insn_and_split "*lea_high64"
3131 [(set (match_operand:DI 0 "register_operand" "=d")
3132 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3133 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3135 "&& epilogue_completed"
3136 [(set (match_dup 0) (high:DI (match_dup 2)))
3137 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3138 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3139 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3140 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3142 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3143 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3145 [(set_attr "length" "20")])
3147 ;; Use a scratch register to reduce the latency of the above pattern
3148 ;; on superscalar machines. The optimized sequence is:
3150 ;; lui op1,%highest(op2)
3152 ;; daddiu op1,op1,%higher(op2)
3154 ;; daddu op1,op1,op0
3156 [(set (match_operand:DI 1 "register_operand")
3157 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3158 (match_scratch:DI 0 "d")]
3159 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3160 [(set (match_dup 1) (high:DI (match_dup 3)))
3161 (set (match_dup 0) (high:DI (match_dup 4)))
3162 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3163 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3164 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3166 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3167 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3170 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3171 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3172 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3173 ;; used once. We can then use the sequence:
3175 ;; lui op0,%highest(op1)
3177 ;; daddiu op0,op0,%higher(op1)
3178 ;; daddiu op2,op2,%lo(op1)
3180 ;; daddu op0,op0,op2
3182 ;; which takes 4 cycles on most superscalar targets.
3183 (define_insn_and_split "*lea64"
3184 [(set (match_operand:DI 0 "register_operand" "=d")
3185 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3186 (clobber (match_scratch:DI 2 "=&d"))]
3187 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3189 "&& reload_completed"
3190 [(set (match_dup 0) (high:DI (match_dup 3)))
3191 (set (match_dup 2) (high:DI (match_dup 4)))
3192 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3193 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3194 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3195 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3197 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3198 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3200 [(set_attr "length" "24")])
3202 ;; Split HIGHs into:
3207 ;; on MIPS16 targets.
3209 [(set (match_operand:SI 0 "register_operand" "=d")
3210 (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))]
3211 "TARGET_MIPS16 && reload_completed"
3212 [(set (match_dup 0) (match_dup 2))
3213 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3215 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3218 ;; Insns to fetch a symbol from a big GOT.
3220 (define_insn_and_split "*xgot_hi<mode>"
3221 [(set (match_operand:P 0 "register_operand" "=d")
3222 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3223 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3225 "&& reload_completed"
3226 [(set (match_dup 0) (high:P (match_dup 2)))
3227 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3229 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3230 operands[3] = pic_offset_table_rtx;
3232 [(set_attr "got" "xgot_high")
3233 (set_attr "mode" "<MODE>")])
3235 (define_insn_and_split "*xgot_lo<mode>"
3236 [(set (match_operand:P 0 "register_operand" "=d")
3237 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3238 (match_operand:P 2 "got_disp_operand" "")))]
3239 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3241 "&& reload_completed"
3243 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3244 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3245 [(set_attr "got" "load")
3246 (set_attr "mode" "<MODE>")])
3248 ;; Insns to fetch a symbol from a normal GOT.
3250 (define_insn_and_split "*got_disp<mode>"
3251 [(set (match_operand:P 0 "register_operand" "=d")
3252 (match_operand:P 1 "got_disp_operand" ""))]
3253 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3255 "&& reload_completed"
3257 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3259 operands[2] = pic_offset_table_rtx;
3260 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3262 [(set_attr "got" "load")
3263 (set_attr "mode" "<MODE>")])
3265 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3267 (define_insn_and_split "*got_page<mode>"
3268 [(set (match_operand:P 0 "register_operand" "=d")
3269 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3270 "TARGET_EXPLICIT_RELOCS"
3272 "&& reload_completed"
3274 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3276 operands[2] = pic_offset_table_rtx;
3277 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3279 [(set_attr "got" "load")
3280 (set_attr "mode" "<MODE>")])
3282 ;; Lower-level instructions for loading an address from the GOT.
3283 ;; We could use MEMs, but an unspec gives more optimization
3286 (define_insn "load_got<mode>"
3287 [(set (match_operand:P 0 "register_operand" "=d")
3288 (unspec:P [(match_operand:P 1 "register_operand" "d")
3289 (match_operand:P 2 "immediate_operand" "")]
3292 "<load>\t%0,%R2(%1)"
3293 [(set_attr "type" "load")
3294 (set_attr "mode" "<MODE>")
3295 (set_attr "length" "4")])
3297 ;; Instructions for adding the low 16 bits of an address to a register.
3298 ;; Operand 2 is the address: print_operand works out which relocation
3299 ;; should be applied.
3301 (define_insn "*low<mode>"
3302 [(set (match_operand:P 0 "register_operand" "=d")
3303 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3304 (match_operand:P 2 "immediate_operand" "")))]
3306 "<d>addiu\t%0,%1,%R2"
3307 [(set_attr "type" "arith")
3308 (set_attr "mode" "<MODE>")])
3310 (define_insn "*low<mode>_mips16"
3311 [(set (match_operand:P 0 "register_operand" "=d")
3312 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3313 (match_operand:P 2 "immediate_operand" "")))]
3316 [(set_attr "type" "arith")
3317 (set_attr "mode" "<MODE>")
3318 (set_attr "length" "8")])
3320 ;; Allow combine to split complex const_int load sequences, using operand 2
3321 ;; to store the intermediate results. See move_operand for details.
3323 [(set (match_operand:GPR 0 "register_operand")
3324 (match_operand:GPR 1 "splittable_const_int_operand"))
3325 (clobber (match_operand:GPR 2 "register_operand"))]
3329 mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
3333 ;; Likewise, for symbolic operands.
3335 [(set (match_operand:P 0 "register_operand")
3336 (match_operand:P 1))
3337 (clobber (match_operand:P 2 "register_operand"))]
3338 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3339 [(set (match_dup 0) (match_dup 3))]
3341 mips_split_symbol (operands[2], operands[1],
3342 MAX_MACHINE_MODE, &operands[3]);
3345 ;; 64-bit integer moves
3347 ;; Unlike most other insns, the move insns can't be split with
3348 ;; different predicates, because register spilling and other parts of
3349 ;; the compiler, have memoized the insn number already.
3351 (define_expand "movdi"
3352 [(set (match_operand:DI 0 "")
3353 (match_operand:DI 1 ""))]
3356 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3360 ;; For mips16, we need a special case to handle storing $31 into
3361 ;; memory, since we don't have a constraint to match $31. This
3362 ;; instruction can be generated by save_restore_insns.
3364 (define_insn "*mov<mode>_ra"
3365 [(set (match_operand:GPR 0 "stack_operand" "=m")
3369 [(set_attr "type" "store")
3370 (set_attr "mode" "<MODE>")])
3372 (define_insn "*movdi_32bit"
3373 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3374 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3375 "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
3376 && (register_operand (operands[0], DImode)
3377 || reg_or_0_operand (operands[1], DImode))"
3378 { return mips_output_move (operands[0], operands[1]); }
3379 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store")
3380 (set_attr "mode" "DI")
3381 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3383 (define_insn "*movdi_gp32_fp64"
3384 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*f,*d,*m")
3385 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*f,*J*d,*m,*f,*f"))]
3386 "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
3387 && (register_operand (operands[0], DImode)
3388 || reg_or_0_operand (operands[1], DImode))"
3389 { return mips_output_move (operands[0], operands[1]); }
3390 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
3391 (set_attr "mode" "DI")
3392 (set_attr "length" "8,16,*,*,8,8,4,8,*,8,*")])
3394 (define_insn "*movdi_32bit_mips16"
3395 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3396 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3397 "!TARGET_64BIT && TARGET_MIPS16
3398 && (register_operand (operands[0], DImode)
3399 || register_operand (operands[1], DImode))"
3400 { return mips_output_move (operands[0], operands[1]); }
3401 [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo")
3402 (set_attr "mode" "DI")
3403 (set_attr "length" "8,8,8,8,12,*,*,8")])
3405 (define_insn "*movdi_64bit"
3406 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3407 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3408 "TARGET_64BIT && !TARGET_MIPS16
3409 && (register_operand (operands[0], DImode)
3410 || reg_or_0_operand (operands[1], DImode))"
3411 { return mips_output_move (operands[0], operands[1]); }
3412 [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
3413 (set_attr "mode" "DI")
3414 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
3416 (define_insn "*movdi_64bit_mips16"
3417 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3418 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3419 "TARGET_64BIT && TARGET_MIPS16
3420 && (register_operand (operands[0], DImode)
3421 || register_operand (operands[1], DImode))"
3422 { return mips_output_move (operands[0], operands[1]); }
3423 [(set_attr "type" "move,move,move,arith,arith,const,load,store")
3424 (set_attr "mode" "DI")
3425 (set_attr_alternative "length"
3429 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3432 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3437 (const_string "*")])])
3440 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3441 ;; when the original load is a 4 byte instruction but the add and the
3442 ;; load are 2 2 byte instructions.
3445 [(set (match_operand:DI 0 "register_operand")
3446 (mem:DI (plus:DI (match_dup 0)
3447 (match_operand:DI 1 "const_int_operand"))))]
3448 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3449 && !TARGET_DEBUG_D_MODE
3450 && REG_P (operands[0])
3451 && M16_REG_P (REGNO (operands[0]))
3452 && GET_CODE (operands[1]) == CONST_INT
3453 && ((INTVAL (operands[1]) < 0
3454 && INTVAL (operands[1]) >= -0x10)
3455 || (INTVAL (operands[1]) >= 32 * 8
3456 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3457 || (INTVAL (operands[1]) >= 0
3458 && INTVAL (operands[1]) < 32 * 8
3459 && (INTVAL (operands[1]) & 7) != 0))"
3460 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3461 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3463 HOST_WIDE_INT val = INTVAL (operands[1]);
3466 operands[2] = const0_rtx;
3467 else if (val >= 32 * 8)
3471 operands[1] = GEN_INT (0x8 + off);
3472 operands[2] = GEN_INT (val - off - 0x8);
3478 operands[1] = GEN_INT (off);
3479 operands[2] = GEN_INT (val - off);
3483 ;; 32-bit Integer moves
3485 ;; Unlike most other insns, the move insns can't be split with
3486 ;; different predicates, because register spilling and other parts of
3487 ;; the compiler, have memoized the insn number already.
3489 (define_expand "movsi"
3490 [(set (match_operand:SI 0 "")
3491 (match_operand:SI 1 ""))]
3494 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3498 ;; The difference between these two is whether or not ints are allowed
3499 ;; in FP registers (off by default, use -mdebugh to enable).
3501 (define_insn "*movsi_internal"
3502 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3503 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3505 && (register_operand (operands[0], SImode)
3506 || reg_or_0_operand (operands[1], SImode))"
3507 { return mips_output_move (operands[0], operands[1]); }
3508 [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
3509 (set_attr "mode" "SI")
3510 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
3512 (define_insn "*movsi_mips16"
3513 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3514 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3516 && (register_operand (operands[0], SImode)
3517 || register_operand (operands[1], SImode))"
3518 { return mips_output_move (operands[0], operands[1]); }
3519 [(set_attr "type" "move,move,move,arith,arith,const,load,store")
3520 (set_attr "mode" "SI")
3521 (set_attr_alternative "length"
3525 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3528 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3533 (const_string "*")])])
3535 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3536 ;; when the original load is a 4 byte instruction but the add and the
3537 ;; load are 2 2 byte instructions.
3540 [(set (match_operand:SI 0 "register_operand")
3541 (mem:SI (plus:SI (match_dup 0)
3542 (match_operand:SI 1 "const_int_operand"))))]
3543 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3544 && REG_P (operands[0])
3545 && M16_REG_P (REGNO (operands[0]))
3546 && GET_CODE (operands[1]) == CONST_INT
3547 && ((INTVAL (operands[1]) < 0
3548 && INTVAL (operands[1]) >= -0x80)
3549 || (INTVAL (operands[1]) >= 32 * 4
3550 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3551 || (INTVAL (operands[1]) >= 0
3552 && INTVAL (operands[1]) < 32 * 4
3553 && (INTVAL (operands[1]) & 3) != 0))"
3554 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3555 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3557 HOST_WIDE_INT val = INTVAL (operands[1]);
3560 operands[2] = const0_rtx;
3561 else if (val >= 32 * 4)
3565 operands[1] = GEN_INT (0x7c + off);
3566 operands[2] = GEN_INT (val - off - 0x7c);
3572 operands[1] = GEN_INT (off);
3573 operands[2] = GEN_INT (val - off);
3577 ;; On the mips16, we can split a load of certain constants into a load
3578 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3582 [(set (match_operand:SI 0 "register_operand")
3583 (match_operand:SI 1 "const_int_operand"))]
3584 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3585 && REG_P (operands[0])
3586 && M16_REG_P (REGNO (operands[0]))
3587 && GET_CODE (operands[1]) == CONST_INT
3588 && INTVAL (operands[1]) >= 0x100
3589 && INTVAL (operands[1]) <= 0xff + 0x7f"
3590 [(set (match_dup 0) (match_dup 1))
3591 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3593 int val = INTVAL (operands[1]);
3595 operands[1] = GEN_INT (0xff);
3596 operands[2] = GEN_INT (val - 0xff);
3599 ;; This insn handles moving CCmode values. It's really just a
3600 ;; slightly simplified copy of movsi_internal2, with additional cases
3601 ;; to move a condition register to a general register and to move
3602 ;; between the general registers and the floating point registers.
3604 (define_insn "movcc"
3605 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3606 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3607 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3608 { return mips_output_move (operands[0], operands[1]); }
3609 [(set_attr "type" "multi,move,load,store,mfc,mtc,fmove,fpload,fpstore")
3610 (set_attr "mode" "SI")
3611 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3613 ;; Reload condition code registers. reload_incc and reload_outcc
3614 ;; both handle moves from arbitrary operands into condition code
3615 ;; registers. reload_incc handles the more common case in which
3616 ;; a source operand is constrained to be in a condition-code
3617 ;; register, but has not been allocated to one.
3619 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3620 ;; constraints do not include 'z'. reload_outcc handles the case
3621 ;; when such an operand is allocated to a condition-code register.
3623 ;; Note that reloads from a condition code register to some
3624 ;; other location can be done using ordinary moves. Moving
3625 ;; into a GPR takes a single movcc, moving elsewhere takes
3626 ;; two. We can leave these cases to the generic reload code.
3627 (define_expand "reload_incc"
3628 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3629 (match_operand:CC 1 "general_operand" ""))
3630 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3631 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3633 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3637 (define_expand "reload_outcc"
3638 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3639 (match_operand:CC 1 "register_operand" ""))
3640 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3641 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3643 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3647 ;; MIPS4 supports loading and storing a floating point register from
3648 ;; the sum of two general registers. We use two versions for each of
3649 ;; these four instructions: one where the two general registers are
3650 ;; SImode, and one where they are DImode. This is because general
3651 ;; registers will be in SImode when they hold 32-bit values, but,
3652 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
3653 ;; instructions will still work correctly.
3655 ;; ??? Perhaps it would be better to support these instructions by
3656 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3657 ;; these instructions can only be used to load and store floating
3658 ;; point registers, that would probably cause trouble in reload.
3660 (define_insn "*<ANYF:loadx>_<P:mode>"
3661 [(set (match_operand:ANYF 0 "register_operand" "=f")
3662 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3663 (match_operand:P 2 "register_operand" "d"))))]
3665 "<ANYF:loadx>\t%0,%1(%2)"
3666 [(set_attr "type" "fpidxload")
3667 (set_attr "mode" "<ANYF:UNITMODE>")])
3669 (define_insn "*<ANYF:storex>_<P:mode>"
3670 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3671 (match_operand:P 2 "register_operand" "d")))
3672 (match_operand:ANYF 0 "register_operand" "f"))]
3674 "<ANYF:storex>\t%0,%1(%2)"
3675 [(set_attr "type" "fpidxstore")
3676 (set_attr "mode" "<ANYF:UNITMODE>")])
3678 ;; Scaled indexed address load.
3679 ;; Per md.texi, we only need to look for a pattern with multiply in the
3680 ;; address expression, not shift.
3682 (define_insn "*lwxs"
3683 [(set (match_operand:SI 0 "register_operand" "=d")
3684 (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
3686 (match_operand:SI 2 "register_operand" "d"))))]
3689 [(set_attr "type" "load")
3690 (set_attr "mode" "SI")
3691 (set_attr "length" "4")])
3693 ;; 16-bit Integer moves
3695 ;; Unlike most other insns, the move insns can't be split with
3696 ;; different predicates, because register spilling and other parts of
3697 ;; the compiler, have memoized the insn number already.
3698 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3700 (define_expand "movhi"
3701 [(set (match_operand:HI 0 "")
3702 (match_operand:HI 1 ""))]
3705 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3709 (define_insn "*movhi_internal"
3710 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3711 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3713 && (register_operand (operands[0], HImode)
3714 || reg_or_0_operand (operands[1], HImode))"
3724 [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
3725 (set_attr "mode" "HI")
3726 (set_attr "length" "4,4,*,*,4,4,4,4")])
3728 (define_insn "*movhi_mips16"
3729 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3730 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3732 && (register_operand (operands[0], HImode)
3733 || register_operand (operands[1], HImode))"
3742 [(set_attr "type" "move,move,move,arith,arith,load,store")
3743 (set_attr "mode" "HI")
3744 (set_attr_alternative "length"
3748 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3751 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3755 (const_string "*")])])
3758 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3759 ;; when the original load is a 4 byte instruction but the add and the
3760 ;; load are 2 2 byte instructions.
3763 [(set (match_operand:HI 0 "register_operand")
3764 (mem:HI (plus:SI (match_dup 0)
3765 (match_operand:SI 1 "const_int_operand"))))]
3766 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3767 && REG_P (operands[0])
3768 && M16_REG_P (REGNO (operands[0]))
3769 && GET_CODE (operands[1]) == CONST_INT
3770 && ((INTVAL (operands[1]) < 0
3771 && INTVAL (operands[1]) >= -0x80)
3772 || (INTVAL (operands[1]) >= 32 * 2
3773 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3774 || (INTVAL (operands[1]) >= 0
3775 && INTVAL (operands[1]) < 32 * 2
3776 && (INTVAL (operands[1]) & 1) != 0))"
3777 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3778 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3780 HOST_WIDE_INT val = INTVAL (operands[1]);
3783 operands[2] = const0_rtx;
3784 else if (val >= 32 * 2)
3788 operands[1] = GEN_INT (0x7e + off);
3789 operands[2] = GEN_INT (val - off - 0x7e);
3795 operands[1] = GEN_INT (off);
3796 operands[2] = GEN_INT (val - off);
3800 ;; 8-bit Integer moves
3802 ;; Unlike most other insns, the move insns can't be split with
3803 ;; different predicates, because register spilling and other parts of
3804 ;; the compiler, have memoized the insn number already.
3805 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3807 (define_expand "movqi"
3808 [(set (match_operand:QI 0 "")
3809 (match_operand:QI 1 ""))]
3812 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3816 (define_insn "*movqi_internal"
3817 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3818 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3820 && (register_operand (operands[0], QImode)
3821 || reg_or_0_operand (operands[1], QImode))"
3831 [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
3832 (set_attr "mode" "QI")
3833 (set_attr "length" "4,4,*,*,4,4,4,4")])
3835 (define_insn "*movqi_mips16"
3836 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3837 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3839 && (register_operand (operands[0], QImode)
3840 || register_operand (operands[1], QImode))"
3849 [(set_attr "type" "move,move,move,arith,arith,load,store")
3850 (set_attr "mode" "QI")
3851 (set_attr "length" "4,4,4,4,8,*,*")])
3853 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3854 ;; when the original load is a 4 byte instruction but the add and the
3855 ;; load are 2 2 byte instructions.
3858 [(set (match_operand:QI 0 "register_operand")
3859 (mem:QI (plus:SI (match_dup 0)
3860 (match_operand:SI 1 "const_int_operand"))))]
3861 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3862 && REG_P (operands[0])
3863 && M16_REG_P (REGNO (operands[0]))
3864 && GET_CODE (operands[1]) == CONST_INT
3865 && ((INTVAL (operands[1]) < 0
3866 && INTVAL (operands[1]) >= -0x80)
3867 || (INTVAL (operands[1]) >= 32
3868 && INTVAL (operands[1]) <= 31 + 0x7f))"
3869 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3870 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3872 HOST_WIDE_INT val = INTVAL (operands[1]);
3875 operands[2] = const0_rtx;
3878 operands[1] = GEN_INT (0x7f);
3879 operands[2] = GEN_INT (val - 0x7f);
3883 ;; 32-bit floating point moves
3885 (define_expand "movsf"
3886 [(set (match_operand:SF 0 "")
3887 (match_operand:SF 1 ""))]
3890 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3894 (define_insn "*movsf_hardfloat"
3895 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3896 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3898 && (register_operand (operands[0], SFmode)
3899 || reg_or_0_operand (operands[1], SFmode))"
3900 { return mips_output_move (operands[0], operands[1]); }
3901 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3902 (set_attr "mode" "SF")
3903 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3905 (define_insn "*movsf_softfloat"
3906 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3907 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3908 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3909 && (register_operand (operands[0], SFmode)
3910 || reg_or_0_operand (operands[1], SFmode))"
3911 { return mips_output_move (operands[0], operands[1]); }
3912 [(set_attr "type" "move,load,store")
3913 (set_attr "mode" "SF")
3914 (set_attr "length" "4,*,*")])
3916 (define_insn "*movsf_mips16"
3917 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3918 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3920 && (register_operand (operands[0], SFmode)
3921 || register_operand (operands[1], SFmode))"
3922 { return mips_output_move (operands[0], operands[1]); }
3923 [(set_attr "type" "move,move,move,load,store")
3924 (set_attr "mode" "SF")
3925 (set_attr "length" "4,4,4,*,*")])
3928 ;; 64-bit floating point moves
3930 (define_expand "movdf"
3931 [(set (match_operand:DF 0 "")
3932 (match_operand:DF 1 ""))]
3935 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3939 (define_insn "*movdf_hardfloat_64bit"
3940 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3941 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3942 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3943 && (register_operand (operands[0], DFmode)
3944 || reg_or_0_operand (operands[1], DFmode))"
3945 { return mips_output_move (operands[0], operands[1]); }
3946 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3947 (set_attr "mode" "DF")
3948 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3950 ;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
3951 (define_insn "*movdf_hardfloat_32bit"
3952 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3953 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3954 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
3955 && (register_operand (operands[0], DFmode)
3956 || reg_or_0_operand (operands[1], DFmode))"
3957 { return mips_output_move (operands[0], operands[1]); }
3958 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3959 (set_attr "mode" "DF")
3960 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
3962 (define_insn "*movdf_softfloat"
3963 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
3964 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
3965 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
3966 && (register_operand (operands[0], DFmode)
3967 || reg_or_0_operand (operands[1], DFmode))"
3968 { return mips_output_move (operands[0], operands[1]); }
3969 [(set_attr "type" "multi,load,store,mfc,mtc,fmove")
3970 (set_attr "mode" "DF")
3971 (set_attr "length" "8,*,*,4,4,4")])
3973 (define_insn "*movdf_mips16"
3974 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
3975 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
3977 && (register_operand (operands[0], DFmode)
3978 || register_operand (operands[1], DFmode))"
3979 { return mips_output_move (operands[0], operands[1]); }
3980 [(set_attr "type" "multi,multi,multi,load,store")
3981 (set_attr "mode" "DF")
3982 (set_attr "length" "8,8,8,*,*")])
3985 [(set (match_operand:DI 0 "nonimmediate_operand")
3986 (match_operand:DI 1 "move_operand"))]
3987 "reload_completed && !TARGET_64BIT
3988 && mips_split_64bit_move_p (operands[0], operands[1])"
3991 mips_split_64bit_move (operands[0], operands[1]);
3996 [(set (match_operand:DF 0 "nonimmediate_operand")
3997 (match_operand:DF 1 "move_operand"))]
3998 "reload_completed && !TARGET_64BIT
3999 && mips_split_64bit_move_p (operands[0], operands[1])"
4002 mips_split_64bit_move (operands[0], operands[1]);
4006 ;; When generating mips16 code, split moves of negative constants into
4007 ;; a positive "li" followed by a negation.
4009 [(set (match_operand 0 "register_operand")
4010 (match_operand 1 "const_int_operand"))]
4011 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4015 (neg:SI (match_dup 2)))]
4017 operands[2] = gen_lowpart (SImode, operands[0]);
4018 operands[3] = GEN_INT (-INTVAL (operands[1]));
4021 ;; 64-bit paired-single floating point moves
4023 (define_expand "movv2sf"
4024 [(set (match_operand:V2SF 0)
4025 (match_operand:V2SF 1))]
4026 "TARGET_PAIRED_SINGLE_FLOAT"
4028 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4032 (define_insn "movv2sf_hardfloat_64bit"
4033 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4034 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4035 "TARGET_PAIRED_SINGLE_FLOAT
4037 && (register_operand (operands[0], V2SFmode)
4038 || reg_or_0_operand (operands[1], V2SFmode))"
4039 { return mips_output_move (operands[0], operands[1]); }
4040 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4041 (set_attr "mode" "SF")
4042 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
4044 ;; The HI and LO registers are not truly independent. If we move an mthi
4045 ;; instruction before an mflo instruction, it will make the result of the
4046 ;; mflo unpredictable. The same goes for mtlo and mfhi.
4048 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
4049 ;; Operand 1 is the register we want, operand 2 is the other one.
4051 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
4052 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
4053 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
4055 (define_expand "mfhilo_<mode>"
4056 [(set (match_operand:GPR 0 "register_operand")
4057 (unspec:GPR [(match_operand:GPR 1 "register_operand")
4058 (match_operand:GPR 2 "register_operand")]
4061 (define_insn "*mfhilo_<mode>"
4062 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4063 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4064 (match_operand:GPR 2 "register_operand" "l,h")]
4068 [(set_attr "type" "mfhilo")
4069 (set_attr "mode" "<MODE>")])
4071 (define_insn "*mfhilo_<mode>_macc"
4072 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4073 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4074 (match_operand:GPR 2 "register_operand" "l,h")]
4080 [(set_attr "type" "mfhilo")
4081 (set_attr "mode" "<MODE>")])
4083 ;; Patterns for loading or storing part of a paired floating point
4084 ;; register. We need them because odd-numbered floating-point registers
4085 ;; are not fully independent: see mips_split_64bit_move.
4087 ;; Load the low word of operand 0 with operand 1.
4088 (define_insn "load_df_low"
4089 [(set (match_operand:DF 0 "register_operand" "=f,f")
4090 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
4091 UNSPEC_LOAD_DF_LOW))]
4092 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4094 operands[0] = mips_subword (operands[0], 0);
4095 return mips_output_move (operands[0], operands[1]);
4097 [(set_attr "type" "mtc,fpload")
4098 (set_attr "mode" "SF")])
4100 ;; Load the high word of operand 0 from operand 1, preserving the value
4102 (define_insn "load_df_high"
4103 [(set (match_operand:DF 0 "register_operand" "=f,f")
4104 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
4105 (match_operand:DF 2 "register_operand" "0,0")]
4106 UNSPEC_LOAD_DF_HIGH))]
4107 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4109 operands[0] = mips_subword (operands[0], 1);
4110 return mips_output_move (operands[0], operands[1]);
4112 [(set_attr "type" "mtc,fpload")
4113 (set_attr "mode" "SF")])
4115 ;; Store the high word of operand 1 in operand 0. The corresponding
4116 ;; low-word move is done in the normal way.
4117 (define_insn "store_df_high"
4118 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
4119 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
4120 UNSPEC_STORE_DF_HIGH))]
4121 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4123 operands[1] = mips_subword (operands[1], 1);
4124 return mips_output_move (operands[0], operands[1]);
4126 [(set_attr "type" "mfc,fpstore")
4127 (set_attr "mode" "SF")])
4129 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4130 ;; value in the low word.
4131 (define_insn "mthc1"
4132 [(set (match_operand:DF 0 "register_operand" "=f")
4133 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ")
4134 (match_operand:DF 2 "register_operand" "0")]
4136 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4138 [(set_attr "type" "mtc")
4139 (set_attr "mode" "SF")])
4141 ;; Move high word of operand 1 to operand 0 using mfhc1. The corresponding
4142 ;; low-word move is done in the normal way.
4143 (define_insn "mfhc1"
4144 [(set (match_operand:SI 0 "register_operand" "=d")
4145 (unspec:SI [(match_operand:DF 1 "register_operand" "f")]
4147 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4149 [(set_attr "type" "mfc")
4150 (set_attr "mode" "SF")])
4152 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4153 (define_expand "load_const_gp"
4154 [(set (match_operand 0 "register_operand" "=d")
4155 (const (unspec [(const_int 0)] UNSPEC_GP)))])
4157 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4158 ;; of _gp from the start of this function. Operand 1 is the incoming
4159 ;; function address.
4160 (define_insn_and_split "loadgp_newabi"
4161 [(unspec_volatile [(match_operand 0 "" "")
4162 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
4163 "mips_current_loadgp_style () == LOADGP_NEWABI"
4166 [(set (match_dup 2) (match_dup 3))
4167 (set (match_dup 2) (match_dup 4))
4168 (set (match_dup 2) (match_dup 5))]
4170 operands[2] = pic_offset_table_rtx;
4171 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
4172 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
4173 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
4175 [(set_attr "length" "12")])
4177 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4178 (define_insn_and_split "loadgp_absolute"
4179 [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
4180 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4185 mips_emit_move (pic_offset_table_rtx, operands[0]);
4188 [(set_attr "length" "8")])
4190 ;; The use of gp is hidden when not using explicit relocations.
4191 ;; This blockage instruction prevents the gp load from being
4192 ;; scheduled after an implicit use of gp. It also prevents
4193 ;; the load from being deleted as dead.
4194 (define_insn "loadgp_blockage"
4195 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
4198 [(set_attr "type" "unknown")
4199 (set_attr "mode" "none")
4200 (set_attr "length" "0")])
4202 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4203 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4204 (define_insn "loadgp_rtp"
4205 [(unspec_volatile [(match_operand 0 "symbol_ref_operand")
4206 (match_operand 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4207 "mips_current_loadgp_style () == LOADGP_RTP"
4209 [(set_attr "length" "12")])
4212 [(unspec_volatile [(match_operand:P 0 "symbol_ref_operand")
4213 (match_operand:P 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4214 "mips_current_loadgp_style () == LOADGP_RTP"
4215 [(set (match_dup 2) (high:P (match_dup 3)))
4216 (set (match_dup 2) (unspec:P [(match_dup 2)
4217 (match_dup 3)] UNSPEC_LOAD_GOT))
4218 (set (match_dup 2) (unspec:P [(match_dup 2)
4219 (match_dup 4)] UNSPEC_LOAD_GOT))]
4221 operands[2] = pic_offset_table_rtx;
4222 operands[3] = mips_unspec_address (operands[0], SYMBOL_ABSOLUTE);
4223 operands[4] = mips_unspec_address (operands[1], SYMBOL_HALF);
4226 ;; Emit a .cprestore directive, which normally expands to a single store
4227 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4228 ;; code so that jals inside inline asms will work correctly.
4229 (define_insn "cprestore"
4230 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4235 if (set_nomacro && which_alternative == 1)
4236 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4238 return ".cprestore\t%0";
4240 [(set_attr "type" "store")
4241 (set_attr "length" "4,12")])
4243 ;; Expand in-line code to clear the instruction cache between operand[0] and
4245 (define_expand "clear_cache"
4246 [(match_operand 0 "pmode_register_operand")
4247 (match_operand 1 "pmode_register_operand")]
4253 mips_expand_synci_loop (operands[0], operands[1]);
4254 emit_insn (gen_sync ());
4255 emit_insn (gen_clear_hazard ());
4257 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4259 rtx len = gen_reg_rtx (Pmode);
4260 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4261 /* Flush both caches. We need to flush the data cache in case
4262 the system has a write-back cache. */
4263 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func),
4264 0, VOIDmode, 3, operands[0], Pmode, len, Pmode,
4265 GEN_INT (3), TYPE_MODE (integer_type_node));
4271 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4275 (define_insn "synci"
4276 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4281 (define_insn "rdhwr"
4282 [(set (match_operand:SI 0 "register_operand" "=d")
4283 (unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
4288 (define_insn "clear_hazard"
4289 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4290 (clobber (reg:SI 31))]
4293 return ".set\tpush\n"
4294 "\t.set\tnoreorder\n"
4298 "1:\taddiu\t$31,$31,12\n"
4303 [(set_attr "length" "20")])
4305 ;; Atomic memory operations.
4307 (define_expand "memory_barrier"
4308 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4312 (define_insn "sync_compare_and_swap<mode>"
4313 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4314 (match_operand:GPR 1 "memory_operand" "+R,R"))
4316 (unspec_volatile:GPR [(match_operand:GPR 2 "register_operand" "d,d")
4317 (match_operand:GPR 3 "arith_operand" "I,d")]
4318 UNSPEC_COMPARE_AND_SWAP))]
4321 if (which_alternative == 0)
4322 return MIPS_COMPARE_AND_SWAP ("<d>", "li");
4324 return MIPS_COMPARE_AND_SWAP ("<d>", "move");
4326 [(set_attr "length" "28")])
4328 (define_insn "sync_add<mode>"
4329 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4330 (unspec_volatile:GPR
4331 [(plus:GPR (match_dup 0)
4332 (match_operand:GPR 1 "arith_operand" "I,d"))]
4333 UNSPEC_SYNC_OLD_OP))]
4336 if (which_alternative == 0)
4337 return MIPS_SYNC_OP ("<d>", "<d>addiu");
4339 return MIPS_SYNC_OP ("<d>", "<d>addu");
4341 [(set_attr "length" "24")])
4343 (define_insn "sync_sub<mode>"
4344 [(set (match_operand:GPR 0 "memory_operand" "+R")
4345 (unspec_volatile:GPR
4346 [(minus:GPR (match_dup 0)
4347 (match_operand:GPR 1 "register_operand" "d"))]
4348 UNSPEC_SYNC_OLD_OP))]
4351 return MIPS_SYNC_OP ("<d>", "<d>subu");
4353 [(set_attr "length" "24")])
4355 (define_insn "sync_old_add<mode>"
4356 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4357 (match_operand:GPR 1 "memory_operand" "+R,R"))
4359 (unspec_volatile:GPR
4360 [(plus:GPR (match_dup 1)
4361 (match_operand:GPR 2 "arith_operand" "I,d"))]
4362 UNSPEC_SYNC_OLD_OP))]
4365 if (which_alternative == 0)
4366 return MIPS_SYNC_OLD_OP ("<d>", "<d>addiu");
4368 return MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
4370 [(set_attr "length" "24")])
4372 (define_insn "sync_old_sub<mode>"
4373 [(set (match_operand:GPR 0 "register_operand" "=&d")
4374 (match_operand:GPR 1 "memory_operand" "+R"))
4376 (unspec_volatile:GPR
4377 [(minus:GPR (match_dup 1)
4378 (match_operand:GPR 2 "register_operand" "d"))]
4379 UNSPEC_SYNC_OLD_OP))]
4382 return MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
4384 [(set_attr "length" "24")])
4386 (define_insn "sync_new_add<mode>"
4387 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4388 (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
4389 (match_operand:GPR 2 "arith_operand" "I,d")))
4391 (unspec_volatile:GPR
4392 [(plus:GPR (match_dup 1) (match_dup 2))]
4393 UNSPEC_SYNC_NEW_OP))]
4396 if (which_alternative == 0)
4397 return MIPS_SYNC_NEW_OP ("<d>", "<d>addiu");
4399 return MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
4401 [(set_attr "length" "24")])
4403 (define_insn "sync_new_sub<mode>"
4404 [(set (match_operand:GPR 0 "register_operand" "=&d")
4405 (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
4406 (match_operand:GPR 2 "register_operand" "d")))
4408 (unspec_volatile:GPR
4409 [(minus:GPR (match_dup 1) (match_dup 2))]
4410 UNSPEC_SYNC_NEW_OP))]
4413 return MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
4415 [(set_attr "length" "24")])
4417 (define_insn "sync_<optab><mode>"
4418 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4419 (unspec_volatile:GPR
4420 [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
4422 UNSPEC_SYNC_OLD_OP))]
4425 if (which_alternative == 0)
4426 return MIPS_SYNC_OP ("<d>", "<immediate_insn>");
4428 return MIPS_SYNC_OP ("<d>", "<insn>");
4430 [(set_attr "length" "24")])
4432 (define_insn "sync_old_<optab><mode>"
4433 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4434 (match_operand:GPR 1 "memory_operand" "+R,R"))
4436 (unspec_volatile:GPR
4437 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4439 UNSPEC_SYNC_OLD_OP))]
4442 if (which_alternative == 0)
4443 return MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>");
4445 return MIPS_SYNC_OLD_OP ("<d>", "<insn>");
4447 [(set_attr "length" "24")])
4449 (define_insn "sync_new_<optab><mode>"
4450 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4451 (match_operand:GPR 1 "memory_operand" "+R,R"))
4453 (unspec_volatile:GPR
4454 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4456 UNSPEC_SYNC_NEW_OP))]
4459 if (which_alternative == 0)
4460 return MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>");
4462 return MIPS_SYNC_NEW_OP ("<d>", "<insn>");
4464 [(set_attr "length" "24")])
4466 (define_insn "sync_nand<mode>"
4467 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4468 (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
4469 UNSPEC_SYNC_OLD_OP))]
4472 if (which_alternative == 0)
4473 return MIPS_SYNC_NAND ("<d>", "andi");
4475 return MIPS_SYNC_NAND ("<d>", "and");
4477 [(set_attr "length" "28")])
4479 (define_insn "sync_old_nand<mode>"
4480 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4481 (match_operand:GPR 1 "memory_operand" "+R,R"))
4483 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4484 UNSPEC_SYNC_OLD_OP))]
4487 if (which_alternative == 0)
4488 return MIPS_SYNC_OLD_NAND ("<d>", "andi");
4490 return MIPS_SYNC_OLD_NAND ("<d>", "and");
4492 [(set_attr "length" "28")])
4494 (define_insn "sync_new_nand<mode>"
4495 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4496 (match_operand:GPR 1 "memory_operand" "+R,R"))
4498 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4499 UNSPEC_SYNC_NEW_OP))]
4502 if (which_alternative == 0)
4503 return MIPS_SYNC_NEW_NAND ("<d>", "andi");
4505 return MIPS_SYNC_NEW_NAND ("<d>", "and");
4507 [(set_attr "length" "28")])
4509 (define_insn "sync_lock_test_and_set<mode>"
4510 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4511 (match_operand:GPR 1 "memory_operand" "+R,R"))
4513 (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
4514 UNSPEC_SYNC_EXCHANGE))]
4517 if (which_alternative == 0)
4518 return MIPS_SYNC_EXCHANGE ("<d>", "li");
4520 return MIPS_SYNC_EXCHANGE ("<d>", "move");
4522 [(set_attr "length" "24")])
4524 ;; Block moves, see mips.c for more details.
4525 ;; Argument 0 is the destination
4526 ;; Argument 1 is the source
4527 ;; Argument 2 is the length
4528 ;; Argument 3 is the alignment
4530 (define_expand "movmemsi"
4531 [(parallel [(set (match_operand:BLK 0 "general_operand")
4532 (match_operand:BLK 1 "general_operand"))
4533 (use (match_operand:SI 2 ""))
4534 (use (match_operand:SI 3 "const_int_operand"))])]
4535 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4537 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4544 ;; ....................
4548 ;; ....................
4550 (define_expand "<optab><mode>3"
4551 [(set (match_operand:GPR 0 "register_operand")
4552 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4553 (match_operand:SI 2 "arith_operand")))]
4556 /* On the mips16, a shift of more than 8 is a four byte instruction,
4557 so, for a shift between 8 and 16, it is just as fast to do two
4558 shifts of 8 or less. If there is a lot of shifting going on, we
4559 may win in CSE. Otherwise combine will put the shifts back
4560 together again. This can be called by function_arg, so we must
4561 be careful not to allocate a new register if we've reached the
4565 && GET_CODE (operands[2]) == CONST_INT
4566 && INTVAL (operands[2]) > 8
4567 && INTVAL (operands[2]) <= 16
4568 && !reload_in_progress
4569 && !reload_completed)
4571 rtx temp = gen_reg_rtx (<MODE>mode);
4573 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4574 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4575 GEN_INT (INTVAL (operands[2]) - 8)));
4580 (define_insn "*<optab><mode>3"
4581 [(set (match_operand:GPR 0 "register_operand" "=d")
4582 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4583 (match_operand:SI 2 "arith_operand" "dI")))]
4586 if (GET_CODE (operands[2]) == CONST_INT)
4587 operands[2] = GEN_INT (INTVAL (operands[2])
4588 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4590 return "<d><insn>\t%0,%1,%2";
4592 [(set_attr "type" "shift")
4593 (set_attr "mode" "<MODE>")])
4595 (define_insn "*<optab>si3_extend"
4596 [(set (match_operand:DI 0 "register_operand" "=d")
4598 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4599 (match_operand:SI 2 "arith_operand" "dI"))))]
4600 "TARGET_64BIT && !TARGET_MIPS16"
4602 if (GET_CODE (operands[2]) == CONST_INT)
4603 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4605 return "<insn>\t%0,%1,%2";
4607 [(set_attr "type" "shift")
4608 (set_attr "mode" "SI")])
4610 (define_insn "*<optab>si3_mips16"
4611 [(set (match_operand:SI 0 "register_operand" "=d,d")
4612 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4613 (match_operand:SI 2 "arith_operand" "d,I")))]
4616 if (which_alternative == 0)
4617 return "<insn>\t%0,%2";
4619 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4620 return "<insn>\t%0,%1,%2";
4622 [(set_attr "type" "shift")
4623 (set_attr "mode" "SI")
4624 (set_attr_alternative "length"
4626 (if_then_else (match_operand 2 "m16_uimm3_b")
4630 ;; We need separate DImode MIPS16 patterns because of the irregularity
4632 (define_insn "*ashldi3_mips16"
4633 [(set (match_operand:DI 0 "register_operand" "=d,d")
4634 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4635 (match_operand:SI 2 "arith_operand" "d,I")))]
4636 "TARGET_64BIT && TARGET_MIPS16"
4638 if (which_alternative == 0)
4639 return "dsll\t%0,%2";
4641 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4642 return "dsll\t%0,%1,%2";
4644 [(set_attr "type" "shift")
4645 (set_attr "mode" "DI")
4646 (set_attr_alternative "length"
4648 (if_then_else (match_operand 2 "m16_uimm3_b")
4652 (define_insn "*ashrdi3_mips16"
4653 [(set (match_operand:DI 0 "register_operand" "=d,d")
4654 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4655 (match_operand:SI 2 "arith_operand" "d,I")))]
4656 "TARGET_64BIT && TARGET_MIPS16"
4658 if (GET_CODE (operands[2]) == CONST_INT)
4659 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4661 return "dsra\t%0,%2";
4663 [(set_attr "type" "shift")
4664 (set_attr "mode" "DI")
4665 (set_attr_alternative "length"
4667 (if_then_else (match_operand 2 "m16_uimm3_b")
4671 (define_insn "*lshrdi3_mips16"
4672 [(set (match_operand:DI 0 "register_operand" "=d,d")
4673 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4674 (match_operand:SI 2 "arith_operand" "d,I")))]
4675 "TARGET_64BIT && TARGET_MIPS16"
4677 if (GET_CODE (operands[2]) == CONST_INT)
4678 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4680 return "dsrl\t%0,%2";
4682 [(set_attr "type" "shift")
4683 (set_attr "mode" "DI")
4684 (set_attr_alternative "length"
4686 (if_then_else (match_operand 2 "m16_uimm3_b")
4690 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4693 [(set (match_operand:GPR 0 "register_operand")
4694 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4695 (match_operand:GPR 2 "const_int_operand")))]
4696 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4697 && GET_CODE (operands[2]) == CONST_INT
4698 && INTVAL (operands[2]) > 8
4699 && INTVAL (operands[2]) <= 16"
4700 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4701 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4702 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4704 ;; If we load a byte on the mips16 as a bitfield, the resulting
4705 ;; sequence of instructions is too complicated for combine, because it
4706 ;; involves four instructions: a load, a shift, a constant load into a
4707 ;; register, and an and (the key problem here is that the mips16 does
4708 ;; not have and immediate). We recognize a shift of a load in order
4709 ;; to make it simple enough for combine to understand.
4711 ;; The length here is the worst case: the length of the split version
4712 ;; will be more accurate.
4713 (define_insn_and_split ""
4714 [(set (match_operand:SI 0 "register_operand" "=d")
4715 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4716 (match_operand:SI 2 "immediate_operand" "I")))]
4720 [(set (match_dup 0) (match_dup 1))
4721 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4723 [(set_attr "type" "load")
4724 (set_attr "mode" "SI")
4725 (set_attr "length" "16")])
4727 (define_insn "rotr<mode>3"
4728 [(set (match_operand:GPR 0 "register_operand" "=d")
4729 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4730 (match_operand:SI 2 "arith_operand" "dI")))]
4733 if (GET_CODE (operands[2]) == CONST_INT)
4734 gcc_assert (INTVAL (operands[2]) >= 0
4735 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4737 return "<d>ror\t%0,%1,%2";
4739 [(set_attr "type" "shift")
4740 (set_attr "mode" "<MODE>")])
4743 ;; ....................
4747 ;; ....................
4749 ;; Flow here is rather complex:
4751 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4752 ;; into cmp_operands[] but generates no RTL.
4754 ;; 2) The appropriate branch define_expand is called, which then
4755 ;; creates the appropriate RTL for the comparison and branch.
4756 ;; Different CC modes are used, based on what type of branch is
4757 ;; done, so that we can constrain things appropriately. There
4758 ;; are assumptions in the rest of GCC that break if we fold the
4759 ;; operands into the branches for integer operations, and use cc0
4760 ;; for floating point, so we use the fp status register instead.
4761 ;; If needed, an appropriate temporary is created to hold the
4762 ;; of the integer compare.
4764 (define_expand "cmp<mode>"
4766 (compare:CC (match_operand:GPR 0 "register_operand")
4767 (match_operand:GPR 1 "nonmemory_operand")))]
4770 cmp_operands[0] = operands[0];
4771 cmp_operands[1] = operands[1];
4775 (define_expand "cmp<mode>"
4777 (compare:CC (match_operand:SCALARF 0 "register_operand")
4778 (match_operand:SCALARF 1 "register_operand")))]
4781 cmp_operands[0] = operands[0];
4782 cmp_operands[1] = operands[1];
4787 ;; ....................
4789 ;; CONDITIONAL BRANCHES
4791 ;; ....................
4793 ;; Conditional branches on floating-point equality tests.
4795 (define_insn "*branch_fp"
4798 (match_operator 0 "equality_operator"
4799 [(match_operand:CC 2 "register_operand" "z")
4801 (label_ref (match_operand 1 "" ""))
4805 return mips_output_conditional_branch (insn, operands,
4806 MIPS_BRANCH ("b%F0", "%Z2%1"),
4807 MIPS_BRANCH ("b%W0", "%Z2%1"));
4809 [(set_attr "type" "branch")
4810 (set_attr "mode" "none")])
4812 (define_insn "*branch_fp_inverted"
4815 (match_operator 0 "equality_operator"
4816 [(match_operand:CC 2 "register_operand" "z")
4819 (label_ref (match_operand 1 "" ""))))]
4822 return mips_output_conditional_branch (insn, operands,
4823 MIPS_BRANCH ("b%W0", "%Z2%1"),
4824 MIPS_BRANCH ("b%F0", "%Z2%1"));
4826 [(set_attr "type" "branch")
4827 (set_attr "mode" "none")])
4829 ;; Conditional branches on ordered comparisons with zero.
4831 (define_insn "*branch_order<mode>"
4834 (match_operator 0 "order_operator"
4835 [(match_operand:GPR 2 "register_operand" "d")
4837 (label_ref (match_operand 1 "" ""))
4840 { return mips_output_order_conditional_branch (insn, operands, false); }
4841 [(set_attr "type" "branch")
4842 (set_attr "mode" "none")])
4844 (define_insn "*branch_order<mode>_inverted"
4847 (match_operator 0 "order_operator"
4848 [(match_operand:GPR 2 "register_operand" "d")
4851 (label_ref (match_operand 1 "" ""))))]
4853 { return mips_output_order_conditional_branch (insn, operands, true); }
4854 [(set_attr "type" "branch")
4855 (set_attr "mode" "none")])
4857 ;; Conditional branch on equality comparison.
4859 (define_insn "*branch_equality<mode>"
4862 (match_operator 0 "equality_operator"
4863 [(match_operand:GPR 2 "register_operand" "d")
4864 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4865 (label_ref (match_operand 1 "" ""))
4869 return mips_output_conditional_branch (insn, operands,
4870 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
4871 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
4873 [(set_attr "type" "branch")
4874 (set_attr "mode" "none")])
4876 (define_insn "*branch_equality<mode>_inverted"
4879 (match_operator 0 "equality_operator"
4880 [(match_operand:GPR 2 "register_operand" "d")
4881 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4883 (label_ref (match_operand 1 "" ""))))]
4886 return mips_output_conditional_branch (insn, operands,
4887 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
4888 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
4890 [(set_attr "type" "branch")
4891 (set_attr "mode" "none")])
4895 (define_insn "*branch_equality<mode>_mips16"
4898 (match_operator 0 "equality_operator"
4899 [(match_operand:GPR 1 "register_operand" "d,t")
4901 (match_operand 2 "pc_or_label_operand" "")
4902 (match_operand 3 "pc_or_label_operand" "")))]
4905 if (operands[2] != pc_rtx)
4907 if (which_alternative == 0)
4908 return "b%C0z\t%1,%2";
4910 return "bt%C0z\t%2";
4914 if (which_alternative == 0)
4915 return "b%N0z\t%1,%3";
4917 return "bt%N0z\t%3";
4920 [(set_attr "type" "branch")
4921 (set_attr "mode" "none")
4922 (set_attr "length" "8")])
4924 (define_expand "b<code>"
4926 (if_then_else (any_cond:CC (cc0)
4928 (label_ref (match_operand 0 ""))
4932 gen_conditional_branch (operands, <CODE>);
4936 ;; Used to implement built-in functions.
4937 (define_expand "condjump"
4939 (if_then_else (match_operand 0)
4940 (label_ref (match_operand 1))
4944 ;; ....................
4946 ;; SETTING A REGISTER FROM A COMPARISON
4948 ;; ....................
4950 (define_expand "seq"
4951 [(set (match_operand:SI 0 "register_operand")
4952 (eq:SI (match_dup 1)
4955 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
4957 (define_insn "*seq_<mode>"
4958 [(set (match_operand:GPR 0 "register_operand" "=d")
4959 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4963 [(set_attr "type" "slt")
4964 (set_attr "mode" "<MODE>")])
4966 (define_insn "*seq_<mode>_mips16"
4967 [(set (match_operand:GPR 0 "register_operand" "=t")
4968 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4972 [(set_attr "type" "slt")
4973 (set_attr "mode" "<MODE>")])
4975 ;; "sne" uses sltu instructions in which the first operand is $0.
4976 ;; This isn't possible in mips16 code.
4978 (define_expand "sne"
4979 [(set (match_operand:SI 0 "register_operand")
4980 (ne:SI (match_dup 1)
4983 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
4985 (define_insn "*sne_<mode>"
4986 [(set (match_operand:GPR 0 "register_operand" "=d")
4987 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
4991 [(set_attr "type" "slt")
4992 (set_attr "mode" "<MODE>")])
4994 (define_expand "sgt"
4995 [(set (match_operand:SI 0 "register_operand")
4996 (gt:SI (match_dup 1)
4999 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
5001 (define_insn "*sgt_<mode>"
5002 [(set (match_operand:GPR 0 "register_operand" "=d")
5003 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
5004 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5007 [(set_attr "type" "slt")
5008 (set_attr "mode" "<MODE>")])
5010 (define_insn "*sgt_<mode>_mips16"
5011 [(set (match_operand:GPR 0 "register_operand" "=t")
5012 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
5013 (match_operand:GPR 2 "register_operand" "d")))]
5016 [(set_attr "type" "slt")
5017 (set_attr "mode" "<MODE>")])
5019 (define_expand "sge"
5020 [(set (match_operand:SI 0 "register_operand")
5021 (ge:SI (match_dup 1)
5024 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
5026 (define_insn "*sge_<mode>"
5027 [(set (match_operand:GPR 0 "register_operand" "=d")
5028 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
5032 [(set_attr "type" "slt")
5033 (set_attr "mode" "<MODE>")])
5035 (define_expand "slt"
5036 [(set (match_operand:SI 0 "register_operand")
5037 (lt:SI (match_dup 1)
5040 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
5042 (define_insn "*slt_<mode>"
5043 [(set (match_operand:GPR 0 "register_operand" "=d")
5044 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
5045 (match_operand:GPR 2 "arith_operand" "dI")))]
5048 [(set_attr "type" "slt")
5049 (set_attr "mode" "<MODE>")])
5051 (define_insn "*slt_<mode>_mips16"
5052 [(set (match_operand:GPR 0 "register_operand" "=t,t")
5053 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
5054 (match_operand:GPR 2 "arith_operand" "d,I")))]
5057 [(set_attr "type" "slt")
5058 (set_attr "mode" "<MODE>")
5059 (set_attr_alternative "length"
5061 (if_then_else (match_operand 2 "m16_uimm8_1")
5065 (define_expand "sle"
5066 [(set (match_operand:SI 0 "register_operand")
5067 (le:SI (match_dup 1)
5070 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
5072 (define_insn "*sle_<mode>"
5073 [(set (match_operand:GPR 0 "register_operand" "=d")
5074 (le:GPR (match_operand:GPR 1 "register_operand" "d")
5075 (match_operand:GPR 2 "sle_operand" "")))]
5078 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5079 return "slt\t%0,%1,%2";
5081 [(set_attr "type" "slt")
5082 (set_attr "mode" "<MODE>")])
5084 (define_insn "*sle_<mode>_mips16"
5085 [(set (match_operand:GPR 0 "register_operand" "=t")
5086 (le:GPR (match_operand:GPR 1 "register_operand" "d")
5087 (match_operand:GPR 2 "sle_operand" "")))]
5090 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5091 return "slt\t%1,%2";
5093 [(set_attr "type" "slt")
5094 (set_attr "mode" "<MODE>")
5095 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5099 (define_expand "sgtu"
5100 [(set (match_operand:SI 0 "register_operand")
5101 (gtu:SI (match_dup 1)
5104 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
5106 (define_insn "*sgtu_<mode>"
5107 [(set (match_operand:GPR 0 "register_operand" "=d")
5108 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
5109 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5112 [(set_attr "type" "slt")
5113 (set_attr "mode" "<MODE>")])
5115 (define_insn "*sgtu_<mode>_mips16"
5116 [(set (match_operand:GPR 0 "register_operand" "=t")
5117 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
5118 (match_operand:GPR 2 "register_operand" "d")))]
5121 [(set_attr "type" "slt")
5122 (set_attr "mode" "<MODE>")])
5124 (define_expand "sgeu"
5125 [(set (match_operand:SI 0 "register_operand")
5126 (geu:SI (match_dup 1)
5129 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
5131 (define_insn "*sge_<mode>"
5132 [(set (match_operand:GPR 0 "register_operand" "=d")
5133 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
5137 [(set_attr "type" "slt")
5138 (set_attr "mode" "<MODE>")])
5140 (define_expand "sltu"
5141 [(set (match_operand:SI 0 "register_operand")
5142 (ltu:SI (match_dup 1)
5145 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
5147 (define_insn "*sltu_<mode>"
5148 [(set (match_operand:GPR 0 "register_operand" "=d")
5149 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
5150 (match_operand:GPR 2 "arith_operand" "dI")))]
5153 [(set_attr "type" "slt")
5154 (set_attr "mode" "<MODE>")])
5156 (define_insn "*sltu_<mode>_mips16"
5157 [(set (match_operand:GPR 0 "register_operand" "=t,t")
5158 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
5159 (match_operand:GPR 2 "arith_operand" "d,I")))]
5162 [(set_attr "type" "slt")
5163 (set_attr "mode" "<MODE>")
5164 (set_attr_alternative "length"
5166 (if_then_else (match_operand 2 "m16_uimm8_1")
5170 (define_expand "sleu"
5171 [(set (match_operand:SI 0 "register_operand")
5172 (leu:SI (match_dup 1)
5175 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
5177 (define_insn "*sleu_<mode>"
5178 [(set (match_operand:GPR 0 "register_operand" "=d")
5179 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
5180 (match_operand:GPR 2 "sleu_operand" "")))]
5183 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5184 return "sltu\t%0,%1,%2";
5186 [(set_attr "type" "slt")
5187 (set_attr "mode" "<MODE>")])
5189 (define_insn "*sleu_<mode>_mips16"
5190 [(set (match_operand:GPR 0 "register_operand" "=t")
5191 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
5192 (match_operand:GPR 2 "sleu_operand" "")))]
5195 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5196 return "sltu\t%1,%2";
5198 [(set_attr "type" "slt")
5199 (set_attr "mode" "<MODE>")
5200 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5205 ;; ....................
5207 ;; FLOATING POINT COMPARISONS
5209 ;; ....................
5211 (define_insn "s<code>_<mode>"
5212 [(set (match_operand:CC 0 "register_operand" "=z")
5213 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5214 (match_operand:SCALARF 2 "register_operand" "f")))]
5216 "c.<fcond>.<fmt>\t%Z0%1,%2"
5217 [(set_attr "type" "fcmp")
5218 (set_attr "mode" "FPSW")])
5220 (define_insn "s<code>_<mode>"
5221 [(set (match_operand:CC 0 "register_operand" "=z")
5222 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5223 (match_operand:SCALARF 2 "register_operand" "f")))]
5225 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5226 [(set_attr "type" "fcmp")
5227 (set_attr "mode" "FPSW")])
5230 ;; ....................
5232 ;; UNCONDITIONAL BRANCHES
5234 ;; ....................
5236 ;; Unconditional branches.
5240 (label_ref (match_operand 0 "" "")))]
5245 if (get_attr_length (insn) <= 8)
5246 return "%*b\t%l0%/";
5249 output_asm_insn (mips_output_load_label (), operands);
5250 return "%*jr\t%@%/%]";
5254 return "%*j\t%l0%/";
5256 [(set_attr "type" "jump")
5257 (set_attr "mode" "none")
5258 (set (attr "length")
5259 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5260 ;; in range, otherwise load the address of the branch target into
5261 ;; $at and then jump to it.
5263 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5264 (lt (abs (minus (match_dup 0)
5265 (plus (pc) (const_int 4))))
5266 (const_int 131072)))
5267 (const_int 4) (const_int 16)))])
5269 ;; We need a different insn for the mips16, because a mips16 branch
5270 ;; does not have a delay slot.
5274 (label_ref (match_operand 0 "" "")))]
5277 [(set_attr "type" "branch")
5278 (set_attr "mode" "none")
5279 (set_attr "length" "8")])
5281 (define_expand "indirect_jump"
5282 [(set (pc) (match_operand 0 "register_operand"))]
5285 operands[0] = force_reg (Pmode, operands[0]);
5286 if (Pmode == SImode)
5287 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5289 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5293 (define_insn "indirect_jump<mode>"
5294 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5297 [(set_attr "type" "jump")
5298 (set_attr "mode" "none")])
5300 (define_expand "tablejump"
5302 (match_operand 0 "register_operand"))
5303 (use (label_ref (match_operand 1 "")))]
5306 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5307 operands[0] = expand_binop (Pmode, add_optab,
5308 convert_to_mode (Pmode, operands[0], false),
5309 gen_rtx_LABEL_REF (Pmode, operands[1]),
5311 else if (TARGET_GPWORD)
5312 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5313 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5314 else if (TARGET_RTP_PIC)
5316 /* When generating RTP PIC, we use case table entries that are relative
5317 to the start of the function. Add the function's address to the
5319 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5320 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5321 start, 0, 0, OPTAB_WIDEN);
5324 if (Pmode == SImode)
5325 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5327 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5331 (define_insn "tablejump<mode>"
5333 (match_operand:P 0 "register_operand" "d"))
5334 (use (label_ref (match_operand 1 "" "")))]
5337 [(set_attr "type" "jump")
5338 (set_attr "mode" "none")])
5340 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5341 ;; While it is possible to either pull it off the stack (in the
5342 ;; o32 case) or recalculate it given t9 and our target label,
5343 ;; it takes 3 or 4 insns to do so.
5345 (define_expand "builtin_setjmp_setup"
5346 [(use (match_operand 0 "register_operand"))]
5351 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5352 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5356 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5357 ;; that older code did recalculate the gp from $25. Continue to jump through
5358 ;; $25 for compatibility (we lose nothing by doing so).
5360 (define_expand "builtin_longjmp"
5361 [(use (match_operand 0 "register_operand"))]
5364 /* The elements of the buffer are, in order: */
5365 int W = GET_MODE_SIZE (Pmode);
5366 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5367 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5368 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5369 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5370 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5371 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5372 The target is bound to be using $28 as the global pointer
5373 but the current function might not be. */
5374 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5376 /* This bit is similar to expand_builtin_longjmp except that it
5377 restores $gp as well. */
5378 mips_emit_move (hard_frame_pointer_rtx, fp);
5379 mips_emit_move (pv, lab);
5380 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5381 mips_emit_move (gp, gpv);
5382 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5383 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5384 emit_insn (gen_rtx_USE (VOIDmode, gp));
5385 emit_indirect_jump (pv);
5390 ;; ....................
5392 ;; Function prologue/epilogue
5394 ;; ....................
5397 (define_expand "prologue"
5401 mips_expand_prologue ();
5405 ;; Block any insns from being moved before this point, since the
5406 ;; profiling call to mcount can use various registers that aren't
5407 ;; saved or used to pass arguments.
5409 (define_insn "blockage"
5410 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5413 [(set_attr "type" "unknown")
5414 (set_attr "mode" "none")
5415 (set_attr "length" "0")])
5417 (define_expand "epilogue"
5421 mips_expand_epilogue (false);
5425 (define_expand "sibcall_epilogue"
5429 mips_expand_epilogue (true);
5433 ;; Trivial return. Make it look like a normal return insn as that
5434 ;; allows jump optimizations to work better.
5436 (define_insn "return"
5438 "mips_can_use_return_insn ()"
5440 [(set_attr "type" "jump")
5441 (set_attr "mode" "none")])
5445 (define_insn "return_internal"
5447 (use (match_operand 0 "pmode_register_operand" ""))]
5450 [(set_attr "type" "jump")
5451 (set_attr "mode" "none")])
5453 ;; This is used in compiling the unwind routines.
5454 (define_expand "eh_return"
5455 [(use (match_operand 0 "general_operand"))]
5458 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
5460 if (GET_MODE (operands[0]) != gpr_mode)
5461 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
5463 emit_insn (gen_eh_set_lr_di (operands[0]));
5465 emit_insn (gen_eh_set_lr_si (operands[0]));
5470 ;; Clobber the return address on the stack. We can't expand this
5471 ;; until we know where it will be put in the stack frame.
5473 (define_insn "eh_set_lr_si"
5474 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5475 (clobber (match_scratch:SI 1 "=&d"))]
5479 (define_insn "eh_set_lr_di"
5480 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5481 (clobber (match_scratch:DI 1 "=&d"))]
5486 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5487 (clobber (match_scratch 1))]
5488 "reload_completed && !TARGET_DEBUG_D_MODE"
5491 mips_set_return_address (operands[0], operands[1]);
5495 (define_insn_and_split "nonlocal_goto_receiver"
5497 (unspec_volatile:SI [(const_int 0)] UNSPEC_NONLOCAL_GOTO_RECEIVER))]
5498 "TARGET_CALL_CLOBBERED_GP"
5500 "&& reload_completed"
5506 [(set_attr "type" "load")
5507 (set_attr "length" "12")])
5510 ;; ....................
5514 ;; ....................
5516 ;; Instructions to load a call address from the GOT. The address might
5517 ;; point to a function or to a lazy binding stub. In the latter case,
5518 ;; the stub will use the dynamic linker to resolve the function, which
5519 ;; in turn will change the GOT entry to point to the function's real
5522 ;; This means that every call, even pure and constant ones, can
5523 ;; potentially modify the GOT entry. And once a stub has been called,
5524 ;; we must not call it again.
5526 ;; We represent this restriction using an imaginary fixed register that
5527 ;; acts like a GOT version number. By making the register call-clobbered,
5528 ;; we tell the target-independent code that the address could be changed
5529 ;; by any call insn.
5530 (define_insn "load_call<mode>"
5531 [(set (match_operand:P 0 "register_operand" "=d")
5532 (unspec:P [(match_operand:P 1 "register_operand" "r")
5533 (match_operand:P 2 "immediate_operand" "")
5534 (reg:P FAKE_CALL_REGNO)]
5537 "<load>\t%0,%R2(%1)"
5538 [(set_attr "type" "load")
5539 (set_attr "mode" "<MODE>")
5540 (set_attr "length" "4")])
5542 ;; Sibling calls. All these patterns use jump instructions.
5544 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5545 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5546 ;; is defined in terms of call_insn_operand, the same is true of the
5549 ;; When we use an indirect jump, we need a register that will be
5550 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5551 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5552 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5555 (define_expand "sibcall"
5556 [(parallel [(call (match_operand 0 "")
5557 (match_operand 1 ""))
5558 (use (match_operand 2 "")) ;; next_arg_reg
5559 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5562 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5566 (define_insn "sibcall_internal"
5567 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5568 (match_operand 1 "" ""))]
5569 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5570 { return MIPS_CALL ("j", operands, 0); }
5571 [(set_attr "type" "call")])
5573 (define_expand "sibcall_value"
5574 [(parallel [(set (match_operand 0 "")
5575 (call (match_operand 1 "")
5576 (match_operand 2 "")))
5577 (use (match_operand 3 ""))])] ;; next_arg_reg
5580 mips_expand_call (operands[0], XEXP (operands[1], 0),
5581 operands[2], operands[3], true);
5585 (define_insn "sibcall_value_internal"
5586 [(set (match_operand 0 "register_operand" "")
5587 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5588 (match_operand 2 "" "")))]
5589 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5590 { return MIPS_CALL ("j", operands, 1); }
5591 [(set_attr "type" "call")])
5593 (define_insn "sibcall_value_multiple_internal"
5594 [(set (match_operand 0 "register_operand" "")
5595 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5596 (match_operand 2 "" "")))
5597 (set (match_operand 3 "register_operand" "")
5598 (call (mem:SI (match_dup 1))
5600 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5601 { return MIPS_CALL ("j", operands, 1); }
5602 [(set_attr "type" "call")])
5604 (define_expand "call"
5605 [(parallel [(call (match_operand 0 "")
5606 (match_operand 1 ""))
5607 (use (match_operand 2 "")) ;; next_arg_reg
5608 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5611 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5615 ;; This instruction directly corresponds to an assembly-language "jal".
5616 ;; There are four cases:
5619 ;; Both symbolic and register destinations are OK. The pattern
5620 ;; always expands to a single mips instruction.
5622 ;; - -mabicalls/-mno-explicit-relocs:
5623 ;; Again, both symbolic and register destinations are OK.
5624 ;; The call is treated as a multi-instruction black box.
5626 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5627 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5630 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5631 ;; Only "jal $25" is allowed. The call is actually two instructions:
5632 ;; "jalr $25" followed by an insn to reload $gp.
5634 ;; In the last case, we can generate the individual instructions with
5635 ;; a define_split. There are several things to be wary of:
5637 ;; - We can't expose the load of $gp before reload. If we did,
5638 ;; it might get removed as dead, but reload can introduce new
5639 ;; uses of $gp by rematerializing constants.
5641 ;; - We shouldn't restore $gp after calls that never return.
5642 ;; It isn't valid to insert instructions between a noreturn
5643 ;; call and the following barrier.
5645 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5646 ;; instruction preserves $gp and so have no effect on its liveness.
5647 ;; But once we generate the separate insns, it becomes obvious that
5648 ;; $gp is not live on entry to the call.
5650 ;; ??? The operands[2] = insn check is a hack to make the original insn
5651 ;; available to the splitter.
5652 (define_insn_and_split "call_internal"
5653 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5654 (match_operand 1 "" ""))
5655 (clobber (reg:SI 31))]
5657 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5658 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5661 emit_call_insn (gen_call_split (operands[0], operands[1]));
5662 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5666 [(set_attr "jal" "indirect,direct")
5667 (set_attr "extended_mips16" "no,yes")])
5669 (define_insn "call_split"
5670 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5671 (match_operand 1 "" ""))
5672 (clobber (reg:SI 31))
5673 (clobber (reg:SI 28))]
5674 "TARGET_SPLIT_CALLS"
5675 { return MIPS_CALL ("jal", operands, 0); }
5676 [(set_attr "type" "call")])
5678 (define_expand "call_value"
5679 [(parallel [(set (match_operand 0 "")
5680 (call (match_operand 1 "")
5681 (match_operand 2 "")))
5682 (use (match_operand 3 ""))])] ;; next_arg_reg
5685 mips_expand_call (operands[0], XEXP (operands[1], 0),
5686 operands[2], operands[3], false);
5690 ;; See comment for call_internal.
5691 (define_insn_and_split "call_value_internal"
5692 [(set (match_operand 0 "register_operand" "")
5693 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5694 (match_operand 2 "" "")))
5695 (clobber (reg:SI 31))]
5697 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5698 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5701 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5703 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5707 [(set_attr "jal" "indirect,direct")
5708 (set_attr "extended_mips16" "no,yes")])
5710 (define_insn "call_value_split"
5711 [(set (match_operand 0 "register_operand" "")
5712 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5713 (match_operand 2 "" "")))
5714 (clobber (reg:SI 31))
5715 (clobber (reg:SI 28))]
5716 "TARGET_SPLIT_CALLS"
5717 { return MIPS_CALL ("jal", operands, 1); }
5718 [(set_attr "type" "call")])
5720 ;; See comment for call_internal.
5721 (define_insn_and_split "call_value_multiple_internal"
5722 [(set (match_operand 0 "register_operand" "")
5723 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5724 (match_operand 2 "" "")))
5725 (set (match_operand 3 "register_operand" "")
5726 (call (mem:SI (match_dup 1))
5728 (clobber (reg:SI 31))]
5730 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5731 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5734 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5735 operands[2], operands[3]));
5736 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5740 [(set_attr "jal" "indirect,direct")
5741 (set_attr "extended_mips16" "no,yes")])
5743 (define_insn "call_value_multiple_split"
5744 [(set (match_operand 0 "register_operand" "")
5745 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5746 (match_operand 2 "" "")))
5747 (set (match_operand 3 "register_operand" "")
5748 (call (mem:SI (match_dup 1))
5750 (clobber (reg:SI 31))
5751 (clobber (reg:SI 28))]
5752 "TARGET_SPLIT_CALLS"
5753 { return MIPS_CALL ("jal", operands, 1); }
5754 [(set_attr "type" "call")])
5756 ;; Call subroutine returning any type.
5758 (define_expand "untyped_call"
5759 [(parallel [(call (match_operand 0 "")
5761 (match_operand 1 "")
5762 (match_operand 2 "")])]
5767 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5769 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5771 rtx set = XVECEXP (operands[2], 0, i);
5772 mips_emit_move (SET_DEST (set), SET_SRC (set));
5775 emit_insn (gen_blockage ());
5780 ;; ....................
5784 ;; ....................
5788 (define_insn "prefetch"
5789 [(prefetch (match_operand:QI 0 "address_operand" "p")
5790 (match_operand 1 "const_int_operand" "n")
5791 (match_operand 2 "const_int_operand" "n"))]
5792 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5794 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5795 return "pref\t%1,%a0";
5797 [(set_attr "type" "prefetch")])
5799 (define_insn "*prefetch_indexed_<mode>"
5800 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5801 (match_operand:P 1 "register_operand" "d"))
5802 (match_operand 2 "const_int_operand" "n")
5803 (match_operand 3 "const_int_operand" "n"))]
5804 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5806 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5807 return "prefx\t%2,%1(%0)";
5809 [(set_attr "type" "prefetchx")])
5815 [(set_attr "type" "nop")
5816 (set_attr "mode" "none")])
5818 ;; Like nop, but commented out when outside a .set noreorder block.
5819 (define_insn "hazard_nop"
5828 [(set_attr "type" "nop")])
5830 ;; MIPS4 Conditional move instructions.
5832 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5833 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5835 (match_operator:MOVECC 4 "equality_operator"
5836 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5838 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5839 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5844 [(set_attr "type" "condmove")
5845 (set_attr "mode" "<GPR:MODE>")])
5847 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5848 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5849 (if_then_else:SCALARF
5850 (match_operator:MOVECC 4 "equality_operator"
5851 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5853 (match_operand:SCALARF 2 "register_operand" "f,0")
5854 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5857 mov%T4.<fmt>\t%0,%2,%1
5858 mov%t4.<fmt>\t%0,%3,%1"
5859 [(set_attr "type" "condmove")
5860 (set_attr "mode" "<SCALARF:MODE>")])
5862 ;; These are the main define_expand's used to make conditional moves.
5864 (define_expand "mov<mode>cc"
5865 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5866 (set (match_operand:GPR 0 "register_operand")
5867 (if_then_else:GPR (match_dup 5)
5868 (match_operand:GPR 2 "reg_or_0_operand")
5869 (match_operand:GPR 3 "reg_or_0_operand")))]
5872 gen_conditional_move (operands);
5876 (define_expand "mov<mode>cc"
5877 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5878 (set (match_operand:SCALARF 0 "register_operand")
5879 (if_then_else:SCALARF (match_dup 5)
5880 (match_operand:SCALARF 2 "register_operand")
5881 (match_operand:SCALARF 3 "register_operand")))]
5884 gen_conditional_move (operands);
5889 ;; ....................
5891 ;; mips16 inline constant tables
5893 ;; ....................
5896 (define_insn "consttable_int"
5897 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
5898 (match_operand 1 "const_int_operand" "")]
5899 UNSPEC_CONSTTABLE_INT)]
5902 assemble_integer (operands[0], INTVAL (operands[1]),
5903 BITS_PER_UNIT * INTVAL (operands[1]), 1);
5906 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
5908 (define_insn "consttable_float"
5909 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
5910 UNSPEC_CONSTTABLE_FLOAT)]
5915 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
5916 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
5917 assemble_real (d, GET_MODE (operands[0]),
5918 GET_MODE_BITSIZE (GET_MODE (operands[0])));
5921 [(set (attr "length")
5922 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
5924 (define_insn "align"
5925 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
5928 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
5931 [(match_operand 0 "small_data_pattern")]
5934 { operands[0] = mips_rewrite_small_data (operands[0]); })
5937 ;; ....................
5939 ;; MIPS16e Save/Restore
5941 ;; ....................
5944 (define_insn "*mips16e_save_restore"
5945 [(match_parallel 0 ""
5946 [(set (match_operand:SI 1 "register_operand")
5947 (plus:SI (match_dup 1)
5948 (match_operand:SI 2 "const_int_operand")))])]
5949 "operands[1] == stack_pointer_rtx
5950 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
5951 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
5952 [(set_attr "type" "arith")
5953 (set_attr "extended_mips16" "yes")])
5955 ; Thread-Local Storage
5957 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
5958 ; MIPS architecture defines this register, and no current
5959 ; implementation provides it; instead, any OS which supports TLS is
5960 ; expected to trap and emulate this instruction. rdhwr is part of the
5961 ; MIPS 32r2 specification, but we use it on any architecture because
5962 ; we expect it to be emulated. Use .set to force the assembler to
5965 (define_insn "tls_get_tp_<mode>"
5966 [(set (match_operand:P 0 "register_operand" "=v")
5967 (unspec:P [(const_int 0)]
5968 UNSPEC_TLS_GET_TP))]
5969 "HAVE_AS_TLS && !TARGET_MIPS16"
5970 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
5971 [(set_attr "type" "unknown")
5972 ; Since rdhwr always generates a trap for now, putting it in a delay
5973 ; slot would make the kernel's emulation of it much slower.
5974 (set_attr "can_delay" "no")
5975 (set_attr "mode" "<MODE>")])
5977 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
5979 (include "mips-ps-3d.md")
5981 ; The MIPS DSP Instructions.
5983 (include "mips-dsp.md")
5985 ; The MIPS DSP REV 2 Instructions.
5987 (include "mips-dspr2.md")