| blob | 0106092e456895925740396c05d1813061aaed82 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2023 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 We check (with modified_between_p) to avoid combining in such a way
37 as to move a computation to a place where its value would be different.
39 Combination is done by mathematically substituting the previous
40 insn(s) values for the regs they set into the expressions in
41 the later insns that refer to these regs. If the result is a valid insn
42 for our target machine, according to the machine description,
43 we install it, delete the earlier insns, and update the data flow
44 information (LOG_LINKS and REG_NOTES) for what we did.
46 There are a few exceptions where the dataflow information isn't
47 completely updated (however this is only a local issue since it is
48 regenerated before the next pass that uses it):
50 - reg_live_length is not updated
51 - reg_n_refs is not adjusted in the rare case when a register is
52 no longer required in a computation
53 - there are extremely rare cases (see distribute_notes) when a
54 REG_DEAD note is lost
55 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
56 removed because there is no way to know which register it was
57 linking
59 To simplify substitution, we combine only when the earlier insn(s)
60 consist of only a single assignment. To simplify updating afterward,
61 we never combine when a subroutine call appears in the middle. */
83 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
95 /* Number of attempts to combine instructions in this function. */
99 /* Number of attempts that got as far as substitution in this function. */
103 /* Number of instructions combined with added SETs in this function. */
107 /* Number of instructions combined in this function. */
111 /* Totals over entire compilation. */
115 /* combine_instructions may try to replace the right hand side of the
116 second instruction with the value of an associated REG_EQUAL note
117 before throwing it at try_combine. That is problematic when there
118 is a REG_DEAD note for a register used in the old right hand side
119 and can cause distribute_notes to do wrong things. This is the
120 second instruction if it has been so modified, null otherwise. */
124 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
128 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
131 \f
133 /* Record last point of death of (hard or pseudo) register n. */
136 /* Record last point of modification of (hard or pseudo) register n. */
139 /* The next group of fields allows the recording of the last value assigned
140 to (hard or pseudo) register n. We use this information to see if an
141 operation being processed is redundant given a prior operation performed
142 on the register. For example, an `and' with a constant is redundant if
143 all the zero bits are already known to be turned off.
145 We use an approach similar to that used by cse, but change it in the
146 following ways:
148 (1) We do not want to reinitialize at each label.
149 (2) It is useful, but not critical, to know the actual value assigned
150 to a register. Often just its form is helpful.
152 Therefore, we maintain the following fields:
154 last_set_value the last value assigned
155 last_set_label records the value of label_tick when the
156 register was assigned
157 last_set_table_tick records the value of label_tick when a
158 value using the register is assigned
159 last_set_invalid set to nonzero when it is not valid
160 to use the value of this register in some
161 register's value
163 To understand the usage of these tables, it is important to understand
164 the distinction between the value in last_set_value being valid and
165 the register being validly contained in some other expression in the
166 table.
168 (The next two parameters are out of date).
170 reg_stat[i].last_set_value is valid if it is nonzero, and either
171 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
173 Register I may validly appear in any expression returned for the value
174 of another register if reg_n_sets[i] is 1. It may also appear in the
175 value for register J if reg_stat[j].last_set_invalid is zero, or
176 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
178 If an expression is found in the table containing a register which may
179 not validly appear in an expression, the register is replaced by
180 something that won't match, (clobber (const_int 0)). */
182 /* Record last value assigned to (hard or pseudo) register n. */
184 rtx last_set_value;
186 /* Record the value of label_tick when an expression involving register n
187 is placed in last_set_value. */
191 /* Record the value of label_tick when the value for register n is placed in
192 last_set_value. */
196 /* These fields are maintained in parallel with last_set_value and are
197 used to store the mode in which the register was last set, the bits
198 that were known to be zero when it was last set, and the number of
199 sign bits copies it was known to have when it was last set. */
205 /* Set nonzero if references to register n in expressions should not be
206 used. last_set_invalid is set nonzero when this register is being
207 assigned to and last_set_table_tick == label_tick. */
211 /* Some registers that are set more than once and used in more than one
212 basic block are nevertheless always set in similar ways. For example,
213 a QImode register may be loaded from memory in two places on a machine
214 where byte loads zero extend.
216 We record in the following fields if a register has some leading bits
217 that are always equal to the sign bit, and what we know about the
218 nonzero bits of a register, specifically which bits are known to be
219 zero.
221 If an entry is zero, it means that we don't know anything special. */
227 /* Record the value of the label_tick when the last truncation
228 happened. The field truncated_to_mode is only valid if
229 truncation_label == label_tick. */
233 /* Record the last truncation seen for this register. If truncation
234 is not a nop to this mode we might be able to save an explicit
235 truncation if we know that value already contains a truncated
236 value. */
239 };
244 /* One plus the highest pseudo for which we track REG_N_SETS.
245 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
246 but during combine_split_insns new pseudos can be created. As we don't have
247 updated DF information in that case, it is hard to initialize the array
248 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
249 so instead of growing the arrays, just assume all newly created pseudos
250 during combine might be set multiple times. */
254 /* Record the luid of the last insn that invalidated memory
255 (anything that writes memory, and subroutine calls, but not pushes). */
259 /* Record the luid of the last CALL_INSN
260 so we can tell whether a potential combination crosses any calls. */
264 /* When `subst' is called, this is the insn that is being modified
265 (by combining in a previous insn). The PATTERN of this insn
266 is still the old pattern partially modified and it should not be
267 looked at, but this may be used to examine the successors of the insn
268 to judge whether a simplification is valid. */
272 /* This is the lowest LUID that `subst' is currently dealing with.
273 get_last_value will not return a value if the register was set at or
274 after this LUID. If not for this mechanism, we could get confused if
275 I2 or I1 in try_combine were an insn that used the old value of a register
276 to obtain a new value. In that case, we might erroneously get the
277 new value of the register when we wanted the old one. */
281 /* This contains any hard registers that are used in newpat; reg_dead_at_p
282 must consider all these registers to be always live. */
286 /* This is an insn to which a LOG_LINKS entry has been added. If this
287 insn is the earlier than I2 or I3, combine should rescan starting at
288 that location. */
292 /* And similarly, for notes. */
296 /* Basic block in which we are performing combines. */
300 \f
301 /* Length of the currently allocated uid_insn_cost array. */
305 /* The following array records the insn_cost for every insn
306 in the instruction stream. */
310 /* The following array records the LOG_LINKS for every insn in the
311 instruction stream as struct insn_link pointers. */
317 };
323 {
327 }
329 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
330 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
332 #define FOR_EACH_LOG_LINK(L, INSN) \
333 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
335 /* Links for LOG_LINKS are allocated from this obstack. */
339 /* Allocate a link. */
343 {
351 }
353 /* Incremented for each basic block. */
357 /* Reset to label_tick for each extended basic block in scanning order. */
361 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
362 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
366 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
367 be safely used. It is zero while computing them and after combine has
368 completed. This former test prevents propagating values based on
369 previously set values, which can be incorrect if a variable is modified
370 in a loop. */
374 \f
375 /* Record one modification to rtl structure
376 to be undone by storing old_contents into *where. */
380 struct undo
381 {
386 };
388 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
389 num_undo says how many are currently recorded.
391 other_insn is nonzero if we have modified some other insn in the process
392 of working on subst_insn. It must be verified too. */
394 struct undobuf
395 {
399 };
403 /* Number of times the pseudo being substituted for
404 was found and replaced. */
409 scalar_int_mode,
412 scalar_int_mode,
484 \f
486 /* It is not safe to use ordinary gen_lowpart in combine.
487 See comments in gen_lowpart_for_combine. */
488 #undef RTL_HOOKS_GEN_LOWPART
489 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
491 /* Our implementation of gen_lowpart never emits a new pseudo. */
492 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
493 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
495 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
496 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
498 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
499 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
501 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
502 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
506 \f
507 /* Convenience wrapper for the canonicalize_comparison target hook.
508 Target hooks cannot use enum rtx_code. */
512 {
516 }
518 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
519 PATTERN cannot be split. Otherwise, it returns an insn sequence.
520 This is a wrapper around split_insns which ensures that the
521 reg_stat vector is made larger if the splitter creates a new
522 register. */
526 {
535 }
537 /* This is used by find_single_use to locate an rtx in LOC that
538 contains exactly one use of DEST, which is typically a REG.
539 It returns a pointer to the innermost rtx expression
540 containing DEST. Appearances of DEST that are being used to
541 totally replace it are not counted. */
545 {
554 {
558 CASE_CONST_ANY:
563 /* If the destination is anything other than PC, a REG or a SUBREG
564 of a REG that occupies all of the REG, the insn uses DEST if
565 it is mentioned in the destination or the source. Otherwise, we
566 need just check the source. */
582 }
584 /* If it wasn't one of the common cases above, check each expression and
585 vector of this code. Look for a unique usage of DEST. */
589 {
591 {
596 else
602 /* Duplicate usage. */
604 }
606 {
610 {
616 else
623 }
624 }
625 }
628 }
631 /* See if DEST, produced in INSN, is used only a single time in the
632 sequel. If so, return a pointer to the innermost rtx expression in which
633 it is used.
635 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
637 Otherwise, we find the single use by finding an insn that has a
638 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
639 only referenced once in that insn, we know that it must be the first
640 and last insn referencing DEST. */
644 {
645 basic_block bb;
658 {
664 {
669 }
670 }
673 }
674 \f
675 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
676 insn. The substitution can be undone by undo_all. If INTO is already
677 set to NEWVAL, do not record this change. Because computing NEWVAL might
678 also call SUBST, we have to compute it before we put anything into
679 the undo table. */
681 static void
683 {
690 /* We'd like to catch as many invalid transformations here as
691 possible. Unfortunately, there are way too many mode changes
692 that are perfectly valid, so we'd waste too much effort for
693 little gain doing the checks here. Focus on catching invalid
694 transformations involving integer constants. */
697 {
698 /* Sanity check that we're replacing oldval with a CONST_INT
699 that is a valid sign-extension for the original mode. */
703 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
704 CONST_INT is not valid, because after the replacement, the
705 original mode would be gone. Unfortunately, we can't tell
706 when do_SUBST is called to replace the operand thereof, so we
707 perform this test on oldval instead, checking whether an
708 invalid replacement took place before we got here. */
713 }
717 else
726 }
728 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
730 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
731 for the value of a HOST_WIDE_INT value (including CONST_INT) is
732 not safe. */
734 static void
736 {
745 else
754 }
756 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
758 /* Similar to SUBST, but just substitute the mode. This is used when
759 changing the mode of a pseudo-register, so that any other
760 references to the entry in the regno_reg_rtx array will change as
761 well. */
763 static void
765 {
775 else
784 }
786 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
788 static void
790 {
799 else
808 }
810 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
811 \f
812 /* Subroutine of try_combine. Determine whether the replacement patterns
813 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
814 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
815 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
816 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
817 of all the instructions can be estimated and the replacements are more
818 expensive than the original sequence. */
820 static bool
823 {
828 /* Lookup the original insn_costs. */
833 {
836 {
840 }
841 else
842 {
846 }
847 }
848 else
849 {
852 }
854 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
855 correct that. */
860 /* Calculate the replacement insn_costs. */
869 {
879 }
880 else
881 {
884 }
887 {
896 optimize_this_for_speed_p);
900 {
903 }
904 else
906 }
908 /* Disallow this combination if both new_cost and old_cost are greater than
909 zero, and new_cost is greater than old cost. */
913 {
932 else
934 }
939 /* Update the uid_insn_cost array with the replacement costs. */
943 {
947 }
950 }
953 /* Delete any insns that copy a register to itself.
954 Return true if the CFG was changed. */
956 static bool
958 {
960 basic_block bb;
965 {
967 {
970 {
975 }
976 }
977 }
980 }
982 \f
983 /* Return false if we do not want to (or cannot) combine DEF. */
984 static bool
986 {
987 /* Do not consider if it is pre/post modification in MEM. */
993 /* Do not combine frame pointer adjustments. */
996 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1004 }
1006 /* Return false if we do not want to (or cannot) combine USE. */
1007 static bool
1009 {
1010 /* Do not consider the usage of the stack pointer by function call. */
1015 }
1017 /* Fill in log links field for all insns. */
1019 static void
1021 {
1022 basic_block bb;
1029 /* Pass through each block from the end, recording the uses of each
1030 register and establishing log links when def is encountered.
1031 Note that we do not clear next_use array in order to save time,
1032 so we have to test whether the use is in the same basic block as def.
1034 There are a few cases below when we do not consider the definition or
1035 usage -- these are taken from original flow.c did. Don't ask me why it is
1036 done this way; I don't know and if it works, I don't want to know. */
1039 {
1041 {
1045 /* Log links are created only once. */
1049 {
1065 /* flow.c claimed:
1067 We don't build a LOG_LINK for hard registers contained
1068 in ASM_OPERANDs. If these registers get replaced,
1069 we might wind up changing the semantics of the insn,
1070 even if reload can make what appear to be valid
1071 assignments later. */
1076 /* Don't add duplicate links between instructions. */
1085 }
1090 }
1091 }
1094 }
1096 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1097 true if we found a LOG_LINK that proves that A feeds B. This only works
1098 if there are no instructions between A and B which could have a link
1099 depending on A, since in that case we would not record a link for B. */
1101 static bool
1103 {
1109 }
1110 \f
1111 /* Main entry point for combiner. F is the first insn of the function.
1112 NREGS is the first unused pseudo-reg number.
1114 Return nonzero if the CFG was changed (e.g. if the combiner has
1115 turned an indirect jump instruction into a direct jump). */
1116 static int
1118 {
1122 basic_block last_bb;
1142 /* Allocate array for insn info. */
1150 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1151 problems when, for example, we have j <<= 1 in a loop. */
1156 /* Scan all SETs and see if we can deduce anything about what
1157 bits are known to be zero for some registers and how many copies
1158 of the sign bit are known to exist for those registers.
1160 Also set any known values so that we can use it while searching
1161 for what bits are known to be set. */
1164 /* Allow the entry block and the first block to fall into the same EBB.
1165 Conceptually the incoming promotions are assigned to the entry block. */
1170 {
1175 label_tick++;
1183 {
1184 rtx links;
1196 insn);
1198 /* Record the current insn_cost of this instruction. */
1201 {
1204 }
1205 }
1206 }
1210 /* Now scan all the insns in forward order. */
1218 {
1221 /* Ignore instruction combination in basic blocks that are going to
1222 be removed as unreachable anyway. See PR82386. */
1230 label_tick++;
1240 {
1254 /* See if we know about function return values before this
1255 insn based upon SUBREG flags. */
1258 /* See if we can find hardregs and subreg of pseudos in
1259 narrower modes. This could help turning TRUNCATEs
1260 into SUBREGs. */
1263 /* Try this insn with each insn it links back to. */
1269 {
1272 }
1274 /* Try each sequence of three linked insns ending with this one. */
1278 {
1281 /* If the linked insn has been replaced by a note, then there
1282 is no point in pursuing this chain any further. */
1290 {
1293 }
1294 }
1296 /* Try combining an insn with two different insns whose results it
1297 uses. */
1307 {
1310 }
1312 /* Try four-instruction combinations. */
1315 {
1319 /* If the linked insn has been replaced by a note, then there
1320 is no point in pursuing this chain any further. */
1325 {
1329 /* I0 -> I1 -> I2 -> I3. */
1335 {
1338 }
1339 /* I0, I1 -> I2, I2 -> I3. */
1346 {
1349 }
1350 }
1353 {
1357 /* I0 -> I2; I1, I2 -> I3. */
1363 {
1366 }
1367 /* I0 -> I1; I1, I2 -> I3. */
1373 {
1376 }
1377 }
1378 }
1380 /* Try this insn with each REG_EQUAL note it links back to. */
1382 {
1389 /* Avoid using a register that may already been marked
1390 dead by an earlier instruction. */
1398 {
1399 /* Temporarily replace the set's source with the
1400 contents of the REG_EQUAL note. The insn will
1401 be deleted or recognized by try_combine. */
1412 last_combined_insn);
1415 {
1418 }
1422 }
1423 }
1428 retry:
1429 ;
1430 }
1431 }
1438 /* Clean up. */
1444 {
1447 {
1450 }
1452 }
1462 /* Make recognizer allow volatile MEMs again. */
1466 }
1468 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1470 static void
1472 {
1478 }
1479 \f
1480 /* Set up any promoted values for incoming argument registers. */
1482 static void
1484 {
1485 tree arg;
1490 {
1495 /* Only continue if the incoming argument is in a register. */
1499 /* Determine, if possible, whether all call sites of the current
1500 function lie within the current compilation unit. (This does
1501 take into account the exporting of a function via taking its
1502 address, and so forth.) */
1503 strictly_local
1506 /* The mode and signedness of the argument before any promotions happen
1507 (equal to the mode of the pseudo holding it at that stage). */
1511 /* The mode and signedness of the argument after any source language and
1512 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1516 /* The mode and signedness of the argument as it is actually passed,
1517 see assign_parm_setup_reg in function.cc. */
1521 /* The mode of the register in which the argument is being passed. */
1524 /* Eliminate sign extensions in the callee when:
1525 (a) A mode promotion has occurred; */
1528 /* (b) The mode of the register is the same as the mode of
1529 the argument as it is passed; */
1532 /* (c) There's no language level extension; */
1534 ;
1535 /* (c.1) All callers are from the current compilation unit. If that's
1536 the case we don't have to rely on an ABI, we only have to know
1537 what we're generating right now, and we know that we will do the
1538 mode1 to mode2 promotion with the given sign. */
1541 /* (c.2) The combination of the two promotions is useful. This is
1542 true when the signs match, or if the first promotion is unsigned.
1543 In the later case, (sign_extend (zero_extend x)) is the same as
1544 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1550 /* Record that the value was promoted from mode1 to mode3,
1551 so that any sign extension at the head of the current
1552 function may be eliminated. */
1556 }
1557 }
1559 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1560 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1561 because some machines (maybe most) will actually do the sign-extension and
1562 this is the conservative approach.
1564 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1565 kludge. */
1567 static rtx
1569 {
1570 scalar_int_mode int_mode;
1579 }
1581 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1582 and SET. */
1584 static void
1586 rtx x)
1587 {
1597 {
1601 }
1603 /* Don't call nonzero_bits if it cannot change anything. */
1605 {
1614 }
1616 /* Don't call num_sign_bit_copies if it cannot change anything. */
1618 {
1621 {
1625 }
1628 }
1629 }
1631 /* Called via note_stores. If X is a pseudo that is narrower than
1632 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1634 If we are setting only a portion of X and we can't figure out what
1635 portion, assume all bits will be used since we don't know what will
1636 be happening.
1638 Similarly, set how many bits of X are known to be copies of the sign bit
1639 at all locations in the function. This is the smallest number implied
1640 by any set of X. */
1642 static void
1644 {
1646 scalar_int_mode mode;
1650 /* If this register is undefined at the start of the file, we can't
1651 say what its contents were. */
1652 && ! REGNO_REG_SET_P
1656 {
1660 {
1664 }
1666 /* If this register is being initialized using itself, and the
1667 register is uninitialized in this basic block, and there are
1668 no LOG_LINKS which set the register, then part of the
1669 register is uninitialized. In that case we can't assume
1670 anything about the number of nonzero bits.
1672 ??? We could do better if we checked this in
1673 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1674 could avoid making assumptions about the insn which initially
1675 sets the register, while still using the information in other
1676 insns. We would have to be careful to check every insn
1677 involved in the combination. */
1683 {
1690 {
1694 }
1695 }
1697 /* If this is a complex assignment, see if we can convert it into a
1698 simple assignment. */
1701 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1702 set what we know about X. */
1708 else
1709 {
1712 }
1713 }
1714 }
1715 \f
1716 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1717 optionally insns that were previously combined into I3 or that will be
1718 combined into the merger of INSN and I3. The order is PRED, PRED2,
1719 INSN, SUCC, SUCC2, I3.
1721 Return 0 if the combination is not allowed for any reason.
1723 If the combination is allowed, *PDEST will be set to the single
1724 destination of INSN and *PSRC to the single source, and this function
1725 will return 1. */
1727 static int
1731 {
1736 rtx link;
1741 {
1743 {
1748 }
1753 }
1757 /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1758 or a PARALLEL consisting of such a SET and CLOBBERs.
1760 If INSN has CLOBBER parallel parts, ignore them for our processing.
1761 By definition, these happen during the execution of the insn. When it
1762 is merged with another insn, all bets are off. If they are, in fact,
1763 needed and aren't also supplied in I3, they may be added by
1764 recog_for_combine. Otherwise, it won't match.
1766 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1767 note.
1769 Get the source and destination of INSN. If more than one, can't
1770 combine. */
1776 {
1778 {
1782 {
1783 /* This is important to combine floating point insns
1784 for the SH4 port. */
1786 /* Combining an isolated USE doesn't make sense.
1787 We depend here on combinable_i3pat to reject them. */
1788 /* The code below this loop only verifies that the inputs of
1789 the SET in INSN do not change. We call reg_set_between_p
1790 to verify that the REG in the USE does not change between
1791 I3 and INSN.
1792 If the USE in INSN was for a pseudo register, the matching
1793 insn pattern will likely match any register; combining this
1794 with any other USE would only be safe if we knew that the
1795 used registers have identical values, or if there was
1796 something to tell them apart, e.g. different modes. For
1797 now, we forgo such complicated tests and simply disallow
1798 combining of USES of pseudo registers with any other USE. */
1801 {
1806 do
1807 {
1817 }
1819 }
1822 /* We can ignore CLOBBERs. */
1827 /* Ignore SETs whose result isn't used but not those that
1828 have side-effects. */
1834 /* If we have already found a SET, this is a second one and
1835 so we cannot combine with this insn. */
1843 /* Anything else means we can't combine. */
1845 }
1846 }
1849 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1850 so don't do anything with it. */
1853 }
1854 else
1860 /* The simplification in expand_field_assignment may call back to
1861 get_last_value, so set safe guard here. */
1867 /* Do not eliminate user-specified register if it is in an
1868 asm input because we may break the register asm usage defined
1869 in GCC manual if allow to do so.
1870 Be aware that this may cover more cases than we expect but this
1871 should be harmless. */
1876 /* Don't eliminate a store in the stack pointer. */
1878 /* Don't combine with an insn that sets a register to itself if it has
1879 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1881 /* Can't merge an ASM_OPERANDS. */
1883 /* Can't merge a function call. */
1885 /* Don't eliminate a function call argument. */
1891 /* Don't substitute into an incremented register. */
1895 /* Don't substitute into a non-local goto, this confuses CFG. */
1897 /* Make sure that DEST is not used after INSN but before SUCC, or
1898 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1899 || (!all_adjacent
1900 && ((succ2
1905 || (succ
1906 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1907 that case SUCC is not in the insn stream, so use SUCC2
1908 instead for this test. */
1910 succ2
1913 /* Make sure that the value that is to be substituted for the register
1914 does not use any registers whose values alter in between. However,
1915 If the insns are adjacent, a use can't cross a set even though we
1916 think it might (this can happen for a sequence of insns each setting
1917 the same destination; last_set of that register might point to
1918 a NOTE). If INSN has a REG_EQUIV note, the register is always
1919 equivalent to the memory so the substitution is valid even if there
1920 are intervening stores. Also, don't move a volatile asm or
1921 UNSPEC_VOLATILE across any other insns. */
1922 || (! all_adjacent
1928 /* Don't combine across a CALL_INSN, because that would possibly
1929 change whether the life span of some REGs crosses calls or not,
1930 and it is a pain to update that information.
1931 Exception: if source is a constant, moving it later can't hurt.
1932 Accept that as a special case. */
1936 /* DEST must be a REG. */
1938 {
1939 /* If register alignment is being enforced for multi-word items in all
1940 cases except for parameters, it is possible to have a register copy
1941 insn referencing a hard register that is not allowed to contain the
1942 mode being copied and which would not be valid as an operand of most
1943 insns. Eliminate this problem by not combining with such an insn.
1945 Also, on some machines we don't want to extend the life of a hard
1946 register. */
1951 /* Don't extend the life of a hard register unless it is
1952 user variable (if we have few registers) or it can't
1953 fit into the desired register (meaning something special
1954 is going on).
1955 Also avoid substituting a return register into I3, because
1956 reload can't handle a conflict with constraints of other
1957 inputs. */
1962 }
1963 else
1970 {
1973 /* If the clobber represents an earlyclobber operand, we must not
1974 substitute an expression containing the clobbered register.
1975 As we do not analyze the constraint strings here, we have to
1976 make the conservative assumption. However, if the register is
1977 a fixed hard reg, the clobber cannot represent any operand;
1978 we leave it up to the machine description to either accept or
1979 reject use-and-clobber patterns. */
1985 }
1987 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1988 or not), reject, unless nothing volatile comes between it and I3 */
1991 {
1992 /* Make sure neither succ nor succ2 contains a volatile reference. */
1997 /* We'll check insns between INSN and I3 below. */
1998 }
2000 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2001 to be an explicit register variable, and was chosen for a reason. */
2007 /* If INSN contains volatile references (specifically volatile MEMs),
2008 we cannot combine across any other volatile references.
2009 Even if INSN doesn't contain volatile references, any intervening
2010 volatile insn might affect machine state. */
2013 ? volatile_refs_p
2020 /* If INSN contains an autoincrement or autodecrement, make sure that
2021 register is not used between there and I3, and not already used in
2022 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2023 Also insist that I3 not be a jump if using LRA; if it were one
2024 and the incremented register were spilled, we would lose.
2025 Reload handles this correctly. */
2043 /* If we get here, we have passed all the tests and the combination is
2044 to be allowed. */
2050 }
2051 \f
2052 /* LOC is the location within I3 that contains its pattern or the component
2053 of a PARALLEL of the pattern. We validate that it is valid for combining.
2055 One problem is if I3 modifies its output, as opposed to replacing it
2056 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2057 doing so would produce an insn that is not equivalent to the original insns.
2059 Consider:
2061 (set (reg:DI 101) (reg:DI 100))
2062 (set (subreg:SI (reg:DI 101) 0) <foo>)
2064 This is NOT equivalent to:
2066 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2067 (set (reg:DI 101) (reg:DI 100))])
2069 Not only does this modify 100 (in which case it might still be valid
2070 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2072 We can also run into a problem if I2 sets a register that I1
2073 uses and I1 gets directly substituted into I3 (not via I2). In that
2074 case, we would be getting the wrong value of I2DEST into I3, so we
2075 must reject the combination. This case occurs when I2 and I1 both
2076 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2077 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2078 of a SET must prevent combination from occurring. The same situation
2079 can occur for I0, in which case I0_NOT_IN_SRC is set.
2081 Before doing the above check, we first try to expand a field assignment
2082 into a set of logical operations.
2084 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2085 we place a register that is both set and used within I3. If more than one
2086 such register is detected, we fail.
2088 Return 1 if the combination is valid, zero otherwise. */
2090 static int
2093 {
2097 {
2102 rtx subdest;
2109 /* Check for the case where I3 modifies its output, as discussed
2110 above. We don't want to prevent pseudos from being combined
2111 into the address of a MEM, so only prevent the combination if
2112 i1 or i2 set the same MEM. */
2122 /* This is the same test done in can_combine_p except we can't test
2123 all_adjacent; we don't have to, since this instruction will stay
2124 in place, thus we are not considering increasing the lifetime of
2125 INNER_DEST.
2127 Also, if this insn sets a function argument, combining it with
2128 something that might need a spill could clobber a previous
2129 function argument; the all_adjacent test in can_combine_p also
2130 checks this; here, we do a more specific test for this case. */
2140 /* If DEST is used in I3, it is being killed in this insn, so
2141 record that for later. We have to consider paradoxical
2142 subregs here, since they kill the whole register, but we
2143 ignore partial subregs, STRICT_LOW_PART, etc.
2144 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2145 STACK_POINTER_REGNUM, since these are always considered to be
2146 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2154 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2160 {
2165 }
2166 }
2169 {
2176 }
2179 }
2180 \f
2181 /* Return 1 if X is an arithmetic expression that contains a multiplication
2182 and division. We don't count multiplications by powers of two here. */
2184 static int
2186 {
2188 {
2204 }
2205 }
2206 \f
2207 /* Determine whether INSN can be used in a combination. Return nonzero if
2208 not. This is used in try_combine to detect early some cases where we
2209 can't perform combinations. */
2211 static int
2213 {
2214 rtx set;
2217 /* If this isn't really an insn, we can't do anything.
2218 This can occur when flow deletes an insn that it has merged into an
2219 auto-increment address. */
2223 /* Never combine loads and stores involving hard regs that are likely
2224 to be spilled. The register allocator can usually handle such
2225 reg-reg moves by tying. If we allow the combiner to make
2226 substitutions of likely-spilled regs, reload might die.
2227 As an exception, we allow combinations involving fixed regs; these are
2228 not available to the register allocator so there's no risk involved. */
2242 #ifdef LEAF_REGISTERS
2244 #else
2245 )
2246 #endif
2253 }
2255 struct likely_spilled_retval_info
2256 {
2259 };
2261 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2262 hard registers that are known to be written to / clobbered in full. */
2263 static void
2265 {
2282 else
2285 }
2287 /* Return nonzero iff part of the return value is live during INSN, and
2288 it is likely spilled. This can happen when more than one insn is needed
2289 to copy the return value, e.g. when we consider to combine into the
2290 second copy insn for a complex value. */
2292 static int
2294 {
2296 rtx reg;
2299 /* We assume here that no machine mode needs more than
2300 32 hard registers when the value overlaps with a register
2301 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2316 /* Disregard parts of the return value that are set later. */
2325 /* Check if any of the (probably) live return value registers is
2326 likely spilled. */
2327 nregs --;
2328 do
2329 {
2335 }
2337 /* Adjust INSN after we made a change to its destination.
2339 Changing the destination can invalidate notes that say something about
2340 the results of the insn and a LOG_LINK pointing to the insn. */
2342 static void
2344 {
2345 /* For notes, be conservative and simply remove them. */
2348 /* The new insn will have a destination that was previously the destination
2349 of an insn just above it. Call distribute_links to make a LOG_LINK from
2350 the next use of that destination. */
2366 }
2368 /* Return TRUE if combine can reuse reg X in mode MODE.
2369 ADDED_SETS is nonzero if the original set is still required. */
2370 static bool
2372 {
2378 /* Don't change between modes with different underlying register sizes,
2379 since this could lead to invalid subregs. */
2385 /* Allow hard registers if the new mode is legal, and occupies no more
2386 registers than the old mode. */
2391 /* Or a pseudo that is only used once. */
2394 && !added_sets
2396 }
2399 /* Check whether X, the destination of a set, refers to part of
2400 the register specified by REG. */
2402 static bool
2404 {
2405 /* Check that reg is an integer mode register. */
2417 }
2419 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2420 by an arbitrary number of CLOBBERs. */
2421 static bool
2423 {
2438 {
2445 }
2447 }
2449 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2450 CLOBBERs), can be split into individual SETs in that order, without
2451 changing semantics. */
2452 static bool
2454 {
2462 {
2471 }
2474 }
2476 /* Return whether X is just a single_set, with the source
2477 a general_operand. */
2478 static bool
2480 {
2486 }
2488 /* Callback function to count autoincs. */
2490 static int
2492 {
2496 }
2498 /* Try to combine the insns I0, I1 and I2 into I3.
2499 Here I0, I1 and I2 appear earlier than I3.
2500 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2501 I3.
2503 If we are combining more than two insns and the resulting insn is not
2504 recognized, try splitting it into two insns. If that happens, I2 and I3
2505 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2506 Otherwise, I0, I1 and I2 are pseudo-deleted.
2508 Return 0 if the combination does not work. Then nothing is changed.
2509 If we did the combination, return the insn at which combine should
2510 resume scanning.
2512 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2513 new direct jump instruction.
2515 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2516 been I3 passed to an earlier try_combine within the same basic
2517 block. */
2522 {
2523 /* New patterns for I3 and I2, respectively. */
2527 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2528 dead. */
2530 /* Total number of SETs to put into I3. */
2532 /* Nonzero if I2's or I1's body now appears in I3. */
2534 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2536 /* Contains I3 if the destination of I3 is used in its source, which means
2537 that the old life of I3 is being killed. If that usage is placed into
2538 I2 and not in I3, a REG_DEAD note must be made. */
2540 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2542 /* Copy of SET_SRC of I1 and I0, if needed. */
2544 /* Set if I2DEST was reused as a scratch register. */
2546 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2548 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2553 /* Notes that must be added to REG_NOTES in I3 and I2. */
2555 /* Notes that we substituted I3 into I2 instead of the normal case. */
2557 /* Notes that I1, I2 or I3 is a MULT operation. */
2567 rtx temp_expr;
2570 rtx new_other_notes;
2575 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2576 never be). */
2580 /* Only try four-insn combinations when there's high likelihood of
2581 success. Look for simple insns, such as loads of constants or
2582 binary operations involving a constant. */
2584 {
2594 {
2597 rtx src;
2602 {
2605 }
2607 ngood++;
2610 nshift++;
2611 }
2613 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2614 are likely manipulating its value. Ideally we'll be able to combine
2615 all four insns into a bitfield insertion of some kind.
2617 Note the source in I0 might be inside a sign/zero extension and the
2618 memory modes in I0 and I3 might be different. So extract the address
2619 from the destination of I3 and search for it in the source of I0.
2621 In the event that there's a match but the source/dest do not actually
2622 refer to the same memory, the worst that happens is we try some
2623 combinations that we wouldn't have otherwise. */
2625 /* Ensure the source of SET0 is a MEM, possibly buried inside
2626 an extension. */
2632 /* Ensure the destination of SET3 is a MEM. */
2634 /* Would it be better to extract the base address for the MEM
2635 in SET3 and look for that? I don't have cases where it matters
2636 but I could envision such cases. */
2642 }
2644 /* Exit early if one of the insns involved can't be used for
2645 combinations. */
2656 combine_attempts++;
2659 /* Reset the hard register usage information. */
2663 {
2670 else
2680 }
2682 /* If multiple insns feed into one of I2 or I3, they can be in any
2683 order. To simplify the code below, reorder them in sequence. */
2694 /* First check for one important special case that the code below will
2695 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2696 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2697 we may be able to replace that destination with the destination of I3.
2698 This occurs in the common code where we compute both a quotient and
2699 remainder into a structure, in which case we want to do the computation
2700 directly into the structure to avoid register-register copies.
2702 Note that this case handles both multiple sets in I2 and also cases
2703 where I2 has a number of CLOBBERs inside the PARALLEL.
2705 We make very conservative checks below and only try to handle the
2706 most common cases of this. For example, we only handle the case
2707 where I2 and I3 are adjacent to avoid making difficult register
2708 usage tests. */
2716 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2717 below would need to check what is inside (and reg_overlap_mentioned_p
2718 doesn't support those codes anyway). Don't allow those destinations;
2719 the resulting insn isn't likely to be recognized anyway. */
2725 {
2728 /* Make sure that the destination of I3,
2729 which we are going to substitute into one output of I2,
2730 is not used within another output of I2. We must avoid making this:
2731 (parallel [(set (mem (reg 69)) ...)
2732 (set (reg 69) ...)])
2733 which is not well-defined as to order of actions.
2734 (Besides, reload can't handle output reloads for this.)
2736 The problem can also happen if the dest of I3 is a memory ref,
2737 if another dest in I2 is an indirect memory ref.
2739 Neither can this PARALLEL be an asm. We do not allow combining
2740 that usually (see can_combine_p), so do not here either. */
2743 {
2752 }
2758 {
2759 combine_merges++;
2769 /* Replace the dest in I2 with our dest and make the resulting
2770 insn the new pattern for I3. Then skip to where we validate
2771 the pattern. Everything was set up above. */
2776 }
2777 }
2779 /* If I2 is setting a pseudo to a constant and I3 is setting some
2780 sub-part of it to another constant, merge them by making a new
2781 constant. */
2789 {
2796 {
2801 {
2807 }
2808 }
2809 else
2810 {
2814 {
2817 }
2818 }
2821 {
2822 /* If this is the low part, we're done. */
2824 ;
2825 /* Handle the case where inner is twice the size of outer. */
2829 /* Otherwise give up for now. */
2830 else
2832 }
2835 {
2843 combine_merges++;
2850 /* Replace the source in I2 with the new constant and make the
2851 resulting insn the new pattern for I3. Then skip to where we
2852 validate the pattern. Everything was set up above. */
2858 /* The dest of I3 has been replaced with the dest of I2. */
2861 }
2862 }
2864 /* If we have no I1 and I2 looks like:
2865 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2866 (set Y OP)])
2867 make up a dummy I1 that is
2868 (set Y OP)
2869 and change I2 to be
2870 (set (reg:CC X) (compare:CC Y (const_int 0)))
2872 (We can ignore any trailing CLOBBERs.)
2874 This undoes a previous combination and allows us to match a branch-and-
2875 decrement insn. */
2887 {
2888 /* We make I1 with the same INSN_UID as I2. This gives it
2889 the same DF_INSN_LUID for value tracking. Our fake I1 will
2890 never appear in the insn stream so giving it the same INSN_UID
2891 as I2 will not cause a problem. */
2904 }
2906 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2907 make those two SETs separate I1 and I2 insns, and make an I0 that is
2908 the original I1. */
2916 {
2917 /* If there is no I1, there is no I0 either. */
2920 /* We make I1 with the same INSN_UID as I2. This gives it
2921 the same DF_INSN_LUID for value tracking. Our fake I1 will
2922 never appear in the insn stream so giving it the same INSN_UID
2923 as I2 will not cause a problem. */
2931 }
2933 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2935 {
2940 }
2942 {
2947 }
2949 {
2954 }
2956 /* With non-call exceptions we can end up trying to combine multiple
2957 insns with possible EH side effects. Make sure we can combine
2958 that to a single insn which means there must be at most one insn
2959 in the combination with an EH side effect. */
2961 {
2966 {
2972 {
2978 }
2979 }
2980 }
2982 /* Record whether i2 and i3 are trivial moves. */
2986 /* Record whether I2DEST is used in I2SRC and similarly for the other
2987 cases. Knowing this will help in register status updating below. */
2998 /* For the earlier insns, determine which of the subsequent ones they
2999 feed. */
3006 /* Ensure that I3's pattern can be the destination of combines. */
3012 {
3015 }
3017 /* See if any of the insns is a MULT operation. Unless one is, we will
3018 reject a combination that is, since it must be slower. Be conservative
3019 here. */
3027 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3028 We used to do this EXCEPT in one case: I3 has a post-inc in an
3029 output operand. However, that exception can give rise to insns like
3030 mov r3,(r3)+
3031 which is a famous insn on the PDP-11 where the value of r3 used as the
3032 source was model-dependent. Avoid this sort of thing. */
3034 #if 0
3040 /* It's not the exception. */
3041 #endif
3043 {
3044 rtx link;
3050 {
3053 }
3054 }
3056 /* See if the SETs in I1 or I2 need to be kept around in the merged
3057 instruction: whenever the value set there is still needed past I3.
3058 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3060 For the SET in I1, we have two cases: if I1 and I2 independently feed
3061 into I3, the set in I1 needs to be kept around unless I1DEST dies
3062 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3063 in I1 needs to be kept around unless I1DEST dies or is set in either
3064 I2 or I3. The same considerations apply to I0. */
3071 else
3079 else
3082 /* We are about to copy insns for the case where they need to be kept
3083 around. Check that they can be copied in the merged instruction. */
3089 {
3092 }
3094 /* We cannot safely duplicate volatile references in any case. */
3099 {
3102 }
3104 /* Count how many auto_inc expressions there were in the original insns;
3105 we need to have the same number in the resulting patterns. */
3114 /* If the set in I2 needs to be kept around, we must make a copy of
3115 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3116 PATTERN (I2), we are only substituting for the original I1DEST, not into
3117 an already-substituted copy. This also prevents making self-referential
3118 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3119 I2DEST. */
3122 {
3125 else
3127 }
3130 {
3133 else
3135 }
3138 {
3141 else
3143 }
3145 combine_merges++;
3147 /* Substitute in the latest insn for the regs set by the earlier ones. */
3153 /* Many machines have insns that can both perform an
3154 arithmetic operation and set the condition code. These operations will
3155 be represented as a PARALLEL with the first element of the vector
3156 being a COMPARE of an arithmetic operation with the constant zero.
3157 The second element of the vector will set some pseudo to the result
3158 of the same arithmetic operation. If we simplify the COMPARE, we won't
3159 match such a pattern and so will generate an extra insn. Here we test
3160 for this case, where both the comparison and the operation result are
3161 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3162 I2SRC. Later we will make the PARALLEL that contains I2. */
3168 {
3169 rtx newpat_dest;
3175 scalar_int_mode mode;
3184 {
3190 }
3192 /* Do the rest only if op1 is const0_rtx, which may be the
3193 result of simplification. */
3195 {
3196 /* If a single use of the CC is found, prepare to modify it
3197 when SELECT_CC_MODE returns a new CC-class mode, or when
3198 the above simplify_compare_const() returned a new comparison
3199 operator. undobuf.other_insn is assigned the CC use insn
3200 when modifying it. */
3202 {
3203 #ifdef SELECT_CC_MODE
3204 machine_mode new_mode
3209 {
3214 else
3215 {
3218 }
3219 }
3220 #endif
3221 /* Cases for modifying the CC-using comparison. */
3223 /* ??? Do we need to verify the zero rtx? */
3225 {
3226 /* Replace cc_use_loc with entire new RTX. */
3231 }
3233 {
3234 /* Just replace the CC reg with a new mode. */
3237 }
3238 }
3240 /* Now we modify the current newpat:
3241 First, SET_DEST(newpat) is updated if the CC mode has been
3242 altered. For targets without SELECT_CC_MODE, this should be
3243 optimized away. */
3246 /* This is always done to propagate i2src into newpat. */
3249 /* Create new version of i2pat if needed; the below PARALLEL
3250 creation needs this to work correctly. */
3254 }
3255 }
3258 {
3259 /* It is possible that the source of I2 or I1 may be performing
3260 an unneeded operation, such as a ZERO_EXTEND of something
3261 that is known to have the high part zero. Handle that case
3262 by letting subst look at the inner insns.
3264 Another way to do this would be to have a function that tries
3265 to simplify a single insn instead of merging two or more
3266 insns. We don't do this because of the potential of infinite
3267 loops and because of the potential extra memory required.
3268 However, doing it the way we are is a bit of a kludge and
3269 doesn't catch all cases.
3271 But only do this if -fexpensive-optimizations since it slows
3272 things down and doesn't usually win.
3274 This is not done in the COMPARE case above because the
3275 unmodified I2PAT is used in the PARALLEL and so a pattern
3276 with a modified I2SRC would not match. */
3279 {
3280 /* Pass pc_rtx so no substitutions are done, just
3281 simplifications. */
3283 {
3286 }
3290 }
3295 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3296 copy of I2SRC each time we substitute it, in order to avoid creating
3297 self-referential RTL when we will be substituting I1SRC for I1DEST
3298 later. Likewise if I0 feeds into I2, either directly or indirectly
3299 through I1, and I0DEST is in I0SRC. */
3306 /* Record whether I2's body now appears within I3's body. */
3308 }
3310 /* If we already got a failure, don't try to do more. Otherwise, try to
3311 substitute I1 if we have it. */
3314 {
3315 /* Before we can do this substitution, we must redo the test done
3316 above (see detailed comments there) that ensures I1DEST isn't
3317 mentioned in any SETs in NEWPAT that are field assignments. */
3320 {
3323 }
3328 /* If the following substitution will modify I1SRC, make a copy of it
3329 for the case where it is substituted for I1DEST in I2PAT later. */
3333 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3334 copy of I1SRC each time we substitute it, in order to avoid creating
3335 self-referential RTL when we will be substituting I0SRC for I0DEST
3336 later. */
3341 /* Record whether I1's body now appears within I3's body. */
3343 }
3345 /* Likewise for I0 if we have it. */
3348 {
3351 {
3354 }
3356 /* If the following substitution will modify I0SRC, make a copy of it
3357 for the case where it is substituted for I0DEST in I1PAT later. */
3360 /* And a copy for I0DEST in I2PAT substitution. */
3369 }
3372 {
3377 {
3382 }
3383 }
3385 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3386 to count all the ways that I2SRC and I1SRC can be used. */
3397 /* Fail if we tried to make a new register. */
3399 /* Fail if we couldn't do something and have a CLOBBER. */
3401 /* Fail if this new pattern is a MULT and we didn't have one before
3402 at the outer level. */
3405 {
3408 }
3410 /* If the actions of the earlier insns must be kept
3411 in addition to substituting them into the latest one,
3412 we must make a new PARALLEL for the latest insn
3413 to hold additional the SETs. */
3416 {
3418 combine_extras++;
3421 {
3427 }
3428 else
3429 {
3434 }
3440 {
3446 }
3448 {
3457 }
3458 }
3460 validate_replacement:
3462 /* Note which hard regs this insn has as inputs. */
3465 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3466 consider splitting this pattern, we might need these clobbers. */
3469 {
3475 }
3477 /* We have recognized nothing yet. */
3480 /* See if this is a PARALLEL of two SETs where one SET's destination is
3481 a register that is unused and this isn't marked as an instruction that
3482 might trap in an EH region. In that case, we just need the other SET.
3483 We prefer this over the PARALLEL.
3485 This can occur when simplifying a divmod insn. We *must* test for this
3486 case here because the code below that splits two independent SETs doesn't
3487 handle this case correctly when it updates the register status.
3489 It's pointless doing this if we originally had two sets, one from
3490 i3, and one from i2. Combining then splitting the parallel results
3491 in the original i2 again plus an invalid insn (which we delete).
3492 The net effect is only to move instructions around, which makes
3493 debug info less accurate.
3495 If the remaining SET came from I2 its destination should not be used
3496 between I2 and I3. See PR82024. */
3501 {
3512 {
3515 }
3524 {
3529 {
3535 }
3536 }
3540 }
3542 /* Is the result of combination a valid instruction? */
3546 /* If we were combining three insns and the result is a simple SET
3547 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3548 insns. There are two ways to do this. It can be split using a
3549 machine-specific method (like when you have an addition of a large
3550 constant) or by combine in the function find_split_point. */
3554 {
3558 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3559 use I2DEST as a scratch register will help. In the latter case,
3560 convert I2DEST to the mode of the source of NEWPAT if we can. */
3564 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3565 inputs of NEWPAT. */
3567 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3568 possible to try that as a scratch reg. This would require adding
3569 more code to make it work though. */
3572 {
3575 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3576 (temporarily, until we are committed to this instruction
3577 combination) does not work: for example, any call to nonzero_bits
3578 on the register (from a splitter in the MD file, for example)
3579 will get the old information, which is invalid.
3581 Since nowadays we can create registers during combine just fine,
3582 we should just create a new one here, not reuse i2dest. */
3584 /* First try to split using the original register as a
3585 scratch register. */
3589 i2dest)));
3592 /* If that didn't work, try changing the mode of I2DEST if
3593 we can. */
3598 {
3600 rtx ni2dest;
3604 else
3605 {
3608 }
3610 parallel = (gen_rtx_PARALLEL
3614 ni2dest))));
3619 {
3627 }
3628 }
3631 }
3633 /* If recog_for_combine has discarded clobbers, try to use them
3634 again for the split. */
3636 {
3639 }
3642 {
3647 }
3651 {
3661 /* If I2 or I3 has multiple SETs, we won't know how to track
3662 register status, so don't use these insns. If I2's destination
3663 is used between I2 and I3, we also can't use these insns. */
3673 /* It is possible that both insns now set the destination of I3.
3674 If so, we must show an extra use of it. */
3677 {
3696 }
3697 }
3699 /* If we can split it and use I2DEST, go ahead and see if that
3700 helps things be recognized. Verify that none of the registers
3701 are set between I2 and I3. */
3704 /* We need I2DEST in the proper mode. If it is a hard register
3705 or the only use of a pseudo, we can change its mode.
3706 Make sure we don't change a hard register to have a mode that
3707 isn't valid for it, or change the number of registers. */
3714 /* We can't overwrite I2DEST if its value is still used by
3715 NEWPAT. */
3717 /* We should not split a possibly trapping part when we
3718 care about non-call EH and have REG_EH_REGION notes
3719 to distribute. */
3721 && has_non_call_exception
3723 {
3732 /* *SPLIT may be part of I2SRC, so make sure we have the
3733 original expression around for later debug processing.
3734 We should not need I2SRC any more in other cases. */
3737 else
3740 /* Get NEWDEST as a register in the proper mode. We have already
3741 validated that we can do this. */
3743 {
3746 else
3747 {
3750 }
3751 }
3753 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3754 an ASHIFT. This can occur if it was inside a PLUS and hence
3755 appeared to be a memory address. This is a kludge. */
3760 {
3764 /* Update split_code because we may not have a multiply
3765 anymore. */
3767 }
3769 /* Similarly for (plus (mult FOO (const_int pow2))). */
3775 {
3780 i_rtx));
3781 /* Update split_code because we may not have a multiply
3782 anymore. */
3784 }
3786 #ifdef INSN_SCHEDULING
3787 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3788 be written as a ZERO_EXTEND. */
3790 {
3791 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3792 what it really is. */
3797 else
3800 }
3801 #endif
3803 /* Attempt to split binary operators using arithmetic identities. */
3807 {
3814 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3816 {
3821 }
3822 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3829 {
3835 /* Split both "((X op Y) op X) op Y" and
3836 "((X op Y) op Y) op X" as "T op T" where T is
3837 "X op Y". */
3840 {
3845 }
3846 /* Split "((X op X) op Y) op Y)" as "T op T" where
3847 T is "X op Y". */
3849 {
3855 }
3856 }
3857 }
3860 {
3863 }
3867 /* recog_for_combine might have added CLOBBERs to newi2pat.
3868 Make sure NEWPAT does not depend on the clobbered regs. */
3872 {
3875 {
3878 }
3879 }
3881 /* If the split point was a MULT and we didn't have one before,
3882 don't use one now. */
3885 }
3886 }
3888 /* Check for a case where we loaded from memory in a narrow mode and
3889 then sign extended it, but we need both registers. In that case,
3890 we have a PARALLEL with both loads from the same memory location.
3891 We can split this into a load from memory followed by a register-register
3892 copy. This saves at least one insn, more if register allocation can
3893 eliminate the copy.
3895 We cannot do this if the destination of the first assignment is a
3896 condition code register. We eliminate this case by making sure
3897 the SET_DEST and SET_SRC have the same mode.
3899 We cannot do this if the destination of the second assignment is
3900 a register that we have already assumed is zero-extended. Similarly
3901 for a SUBREG of such a register. */
3920 BITS_PER_WORD)
3922 HOST_BITS_PER_INT)
3930 BITS_PER_WORD)
3932 HOST_BITS_PER_INT)
3939 {
3940 rtx ni2dest;
3954 }
3956 /* Similarly, check for a case where we have a PARALLEL of two independent
3957 SETs but we started with three insns. In this case, we can do the sets
3958 as two separate insns. This case occurs when some SET allows two
3959 other insns to combine, but the destination of that SET is still live.
3961 Also do this if we started with two insns and (at least) one of the
3962 resulting sets is a noop; this noop will be deleted later.
3964 Also do this if we started with two insns neither of which was a simple
3965 move. */
3972 && (i1
3986 {
3990 /* Normally, it doesn't matter which of the two is done first, but
3991 one which uses any regs/memory set in between i2 and i3 can't
3992 be first. The PARALLEL might also have been pre-existing in i3,
3993 so we need to make sure that we won't wrongly hoist a SET to i2
3994 that would conflict with a death note present in there, or would
3995 have its dest modified between i2 and i3. */
4003 /* If I3 is a jump, ensure that set0 is a jump so that
4004 we do not create invalid RTL. */
4006 )
4007 {
4010 }
4018 /* If I3 is a jump, ensure that set1 is a jump so that
4019 we do not create invalid RTL. */
4021 )
4022 {
4025 }
4026 else
4027 {
4030 }
4035 {
4036 /* recog_for_combine might have added CLOBBERs to newi2pat.
4037 Make sure NEWPAT does not depend on the clobbered regs. */
4039 {
4042 {
4045 {
4048 }
4049 }
4050 }
4054 /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4055 Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4056 mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4058 {
4061 {
4065 {
4068 }
4069 }
4070 }
4074 }
4075 }
4077 /* If it still isn't recognized, fail and change things back the way they
4078 were. */
4080 /* Is the result a reasonable ASM_OPERANDS? */
4082 {
4085 }
4087 /* If we had to change another insn, make sure it is valid also. */
4089 {
4097 {
4100 }
4101 }
4103 /* Only allow this combination if insn_cost reports that the
4104 replacement instructions are cheaper than the originals. */
4106 {
4109 }
4112 {
4117 {
4122 /* Temporarily revert mode back. */
4126 {
4127 /* If we used i2dest as a scratch register with a
4128 different mode, substitute it for the original
4129 i2src while its original mode is temporarily
4130 restored, and then clear i2scratch so that we don't
4131 do it again later. */
4133 this_basic_block);
4135 /* Put back the new mode. */
4137 }
4138 else
4139 {
4144 {
4147 }
4148 else
4149 {
4156 }
4158 /* We're dealing with a reg that changed mode but not
4159 meaning, so we want to turn it into a subreg for
4160 the new mode. However, because of REG sharing and
4161 because its mode had already changed, we have to do
4162 it in two steps. First, replace any debug uses of
4163 reg, with its original mode temporarily restored,
4164 with this copy we have created; then, replace the
4165 copy with the SUBREG of the original shared reg,
4166 once again changed to the new mode. */
4168 this_basic_block);
4172 this_basic_block);
4173 }
4174 }
4175 }
4177 /* If we will be able to accept this, we have made a
4178 change to the destination of I3. This requires us to
4179 do a few adjustments. */
4182 {
4185 }
4187 /* We now know that we can do this combination. Merge the insns and
4188 update the status of registers and LOG_LINKS. */
4191 {
4196 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4197 ensure that they are still valid. Then add any non-duplicate
4198 notes added by recog_for_combine. */
4200 {
4209 /* Simply drop equal note since it may be no longer valid
4210 for other_insn. It may be possible to record that CC
4211 register is changed and only discard those notes, but
4212 in practice it's unnecessary complication and doesn't
4213 give any meaningful improvement.
4215 See PR78559. */
4219 }
4223 NULL_RTX);
4224 }
4227 {
4228 /* I3 now uses what used to be its destination and which is now
4229 I2's destination. This requires us to do a few adjustments. */
4232 }
4235 {
4236 /* We might need a LOG_LINK from I3 to I2. But then we used to
4237 have one, so we still will.
4239 However, some later insn might be using I2's dest and have
4240 a LOG_LINK pointing at I3. We should change it to point at
4241 I2 instead. */
4243 /* newi2pat is usually a SET here; however, recog_for_combine might
4244 have added some clobbers. */
4252 {
4257 !done
4258 && insn
4262 {
4268 {
4272 }
4273 }
4274 }
4275 }
4277 {
4282 /* Compute which registers we expect to eliminate. newi2pat may be setting
4283 either i3dest or i2dest, so we must check it. */
4286 || !i2dest_killed
4288 /* For i1, we need to compute both local elimination and global
4289 elimination information with respect to newi2pat because i1dest
4290 may be the same as i3dest, in which case newi2pat may be setting
4291 i1dest. Global information is used when distributing REG_DEAD
4292 note for i2 and i3, in which case it does matter if newi2pat sets
4293 i1dest or not.
4295 Local information is used when distributing REG_DEAD note for i1,
4296 in which case it doesn't matter if newi2pat sets i1dest or not.
4297 See PR62151, if we have four insns combination:
4298 i0: r0 <- i0src
4299 i1: r1 <- i1src (using r0)
4300 REG_DEAD (r0)
4301 i2: r0 <- i2src (using r1)
4302 i3: r3 <- i3src (using r0)
4303 ix: using r0
4304 From i1's point of view, r0 is eliminated, no matter if it is set
4305 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4306 should be discarded.
4308 Note local information only affects cases in forms like "I1->I2->I3",
4309 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4310 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4311 i0dest anyway. */
4313 || !i1dest_killed
4318 /* Same case as i1. */
4325 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4326 clear them. */
4334 /* Ensure that we do not have something that should not be shared but
4335 occurs multiple times in the new insns. Check this by first
4336 resetting all the `used' flags and then copying anything is shared. */
4360 {
4363 {
4365 {
4366 /* I2SRC must still be meaningful at this point. Some
4367 splitting operations can invalidate I2SRC, but those
4368 operations do not apply to calls. */
4372 }
4379 }
4380 }
4385 /* We had one special case above where I2 had more than one set and
4386 we replaced a destination of one of those sets with the destination
4387 of I3. In that case, we have to update LOG_LINKS of insns later
4388 in this basic block. Note that this (expensive) case is rare.
4390 Also, in this case, we must pretend that all REG_NOTEs for I2
4391 actually came from I3, so that REG_UNUSED notes from I2 will be
4392 properly handled. */
4395 {
4404 temp_insn
4414 {
4419 }
4420 else
4423 }
4431 {
4434 this_basic_block);
4437 }
4438 else
4439 {
4442 this_basic_block);
4444 }
4447 {
4452 this_basic_block);
4454 }
4457 {
4462 this_basic_block);
4464 }
4466 /* Get death notes for everything that is now used in either I3 or
4467 I2 and used to die in a previous insn. If we built two new
4468 patterns, move from I1 to I2 then I2 to I3 so that we get the
4469 proper movement on registers that I2 modifies. */
4475 else
4481 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4498 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4499 know these are REG_UNUSED and want them to go to the desired insn,
4500 so we always pass it as i3. */
4504 NULL_RTX);
4508 NULL_RTX);
4510 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4511 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4512 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4513 in that case, it might delete I2. Similarly for I2 and I1.
4514 Show an additional death due to the REG_DEAD note we make here. If
4515 we discard it in distribute_notes, we will decrement it again. */
4518 {
4523 else
4526 }
4529 {
4534 else
4537 }
4540 {
4545 else
4548 }
4551 {
4556 else
4559 }
4567 {
4572 /* The insn that used to set this register doesn't exist, and
4573 this life of the register may not exist either. See if one of
4574 I3's links points to an insn that sets I2DEST. If it does,
4575 that is now the last known value for I2DEST. If we don't update
4576 this and I2 set the register to a value that depended on its old
4577 contents, we will get confused. If this insn is used, thing
4578 will be set correctly in combine_instructions. */
4586 /* If the reg formerly set in I2 died only once and that was in I3,
4587 zero its use count so it won't make `reload' do any work. */
4590 && ! i2dest_in_i2src
4593 }
4596 {
4609 && ! i1dest_in_i1src
4612 }
4615 {
4628 && ! i0dest_in_i0src
4631 }
4633 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4634 been made to this insn. The order is important, because newi2pat
4635 can affect nonzero_bits of newpat. */
4639 }
4642 {
4644 {
4647 }
4649 }
4652 {
4654 {
4657 }
4659 }
4662 {
4664 {
4667 }
4669 }
4672 {
4674 {
4677 }
4679 }
4682 {
4684 {
4687 }
4689 }
4691 /* Set new_direct_jump_p if a new return or simple jump instruction
4692 has been created. Adjust the CFG accordingly. */
4694 {
4698 }
4703 {
4706 }
4710 {
4716 }
4721 {
4727 }
4729 /* A noop might also need cleaning up of CFG, if it comes from the
4730 simplification of a jump. */
4735 {
4738 }
4745 {
4748 }
4750 combine_successes++;
4760 }
4761 \f
4762 /* Get a marker for undoing to the current state. */
4766 {
4768 }
4770 /* Undo the modifications up to the marker. */
4772 static void
4774 {
4778 {
4783 {
4799 }
4803 }
4806 }
4808 /* Undo all the modifications recorded in undobuf. */
4810 static void
4812 {
4814 }
4816 /* We've committed to accepting the changes we made. Move all
4817 of the undos to the free list. */
4819 static void
4821 {
4825 {
4829 }
4831 }
4832 \f
4833 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4834 where we have an arithmetic expression and return that point. LOC will
4835 be inside INSN.
4837 try_combine will call this function to see if an insn can be split into
4838 two insns. */
4842 {
4852 /* First special-case some codes. */
4854 {
4856 #ifdef INSN_SCHEDULING
4857 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4858 point. */
4861 #endif
4865 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4866 using LO_SUM and HIGH. */
4869 {
4877 }
4879 /* If we have a PLUS whose second operand is a constant and the
4880 address is not valid, perhaps we can split it up using
4881 the machine-specific way to split large constants. We use
4882 the first pseudo-reg (one of the virtual regs) as a placeholder;
4883 it will not remain in the result. */
4888 {
4891 subst_insn);
4893 /* This should have produced two insns, each of which sets our
4894 placeholder. If the source of the second is a valid address,
4895 we can put both sources together and make a split point
4896 in the middle. */
4909 && memory_address_addr_space_p
4912 {
4916 /* Replace the placeholder in SRC2 with SRC1. If we can
4917 find where in SRC2 it was placed, that can become our
4918 split point and we can replace this address with SRC2.
4919 Just try two obvious places. */
4930 {
4933 }
4934 }
4936 /* If that didn't work and we have a nested plus, like:
4937 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4938 is valid address, try to split (REG1 * CONST1). */
4945 {
4950 {
4953 }
4955 }
4962 {
4967 {
4970 }
4972 }
4974 /* If that didn't work, perhaps the first operand is complex and
4975 needs to be computed separately, so make a split point there.
4976 This will occur on machines that just support REG + CONST
4977 and have a constant moved through some previous computation. */
4982 }
4984 /* If we have a PLUS whose first operand is complex, try computing it
4985 separately by making a split there. */
4996 /* See if we can split SET_SRC as it stands. */
5001 /* See if we can split SET_DEST as it stands. */
5006 /* See if this is a bitfield assignment with everything constant. If
5007 so, this is an IOR of an AND, so split it into that. */
5019 {
5025 rtx or_mask;
5034 else
5035 {
5041 or_mask));
5042 }
5049 }
5051 /* Otherwise, see if this is an operation that we can split into two.
5052 If so, try to split that. */
5056 {
5058 /* If we are AND'ing with a large constant that is only a single
5059 bit and the result is only being used in a context where we
5060 need to know if it is zero or nonzero, replace it with a bit
5061 extraction. This will avoid the large constant, which might
5062 have taken more than one insn to make. If the constant were
5063 not a valid argument to the AND but took only one insn to make,
5064 this is no worse, but if it took more than one insn, it will
5065 be better. */
5075 {
5080 {
5083 }
5084 }
5088 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5089 is known to be on, this can be converted into a NEG of a shift. */
5095 {
5102 pos_rtx)));
5107 }
5113 /* We can't optimize if either mode is a partial integer
5114 mode as we don't know how many bits are significant
5115 in those modes. */
5131 {
5139 }
5144 }
5150 {
5151 /* For unsigned, we have a choice of a shift followed by an
5152 AND or two shifts. Use two shifts for field sizes where the
5153 constant might be too large. We assume here that we can
5154 always at least get 8-bit constants in an AND insn, which is
5155 true for every current RISC. */
5158 {
5159 unsigned HOST_WIDE_INT mask
5164 gen_rtx_LSHIFTRT
5171 }
5172 else
5173 {
5177 gen_rtx_fmt_ee
5187 }
5188 }
5190 /* See if this is a simple operation with a constant as the second
5191 operand. It might be that this constant is out of range and hence
5192 could be used as a split point. */
5200 /* Finally, see if this is a simple operation with its first operand
5201 not in a register. The operation might require this operand in a
5202 register, so return it as a split point. We can always do this
5203 because if the first operand were another operation, we would have
5204 already found it as a split point. */
5213 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5214 it is better to write this as (not (ior A B)) so we can split it.
5215 Similarly for IOR. */
5217 {
5225 }
5227 /* Many RISC machines have a large set of logical insns. If the
5228 second operand is a NOT, put it first so we will try to split the
5229 other operand first. */
5231 {
5235 }
5240 /* Canonicalization can produce (minus A (mult B C)), where C is a
5241 constant. It may be better to try splitting (plus (mult B -C) A)
5242 instead if this isn't a multiply by a power of two. */
5246 {
5254 mode)),
5257 }
5259 /* Split at a multiply-accumulate instruction. However if this is
5260 the SET_SRC, we likely do not have such an instruction and it's
5261 worthless to try this split. */
5270 }
5272 /* Otherwise, select our actions depending on our rtx class. */
5274 {
5280 /* fall through */
5288 /* fall through */
5290 /* Some machines have (and (shift ...) ...) insns. If X is not
5291 an AND, but XEXP (X, 0) is, use it as our split point. */
5301 /* Otherwise, we don't have a split point. */
5303 }
5304 }
5305 \f
5306 /* Throughout X, replace FROM with TO, and return the result.
5307 The result is TO if X is FROM;
5308 otherwise the result is X, but its contents may have been modified.
5309 If they were modified, a record was made in undobuf so that
5310 undo_all will (among other things) return X to its original state.
5312 If the number of changes necessary is too much to record to undo,
5313 the excess changes are not made, so the result is invalid.
5314 The changes already made can still be undone.
5315 undobuf.num_undo is incremented for such changes, so by testing that
5316 the caller can tell whether the result is valid.
5318 `n_occurrences' is incremented each time FROM is replaced.
5320 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5322 IN_COND is nonzero if we are at the top level of a condition.
5324 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5325 by copying if `n_occurrences' is nonzero. */
5327 static rtx
5329 {
5334 rtx new_rtx;
5336 /* Two expressions are equal if they are identical copies of a shared
5337 RTX or if they are both registers with the same register number
5338 and mode. */
5340 #define COMBINE_RTX_EQUAL_P(X,Y) \
5341 ((X) == (Y) \
5342 || (REG_P (X) && REG_P (Y) \
5343 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5345 /* Do not substitute into clobbers of regs -- this will never result in
5346 valid RTL. */
5351 {
5352 n_occurrences++;
5354 }
5356 /* If X and FROM are the same register but different modes, they
5357 will not have been seen as equal above. However, the log links code
5358 will make a LOG_LINKS entry for that case. If we do nothing, we
5359 will try to rerecognize our original insn and, when it succeeds,
5360 we will delete the feeding insn, which is incorrect.
5362 So force this insn not to match in this (rare) case. */
5367 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5368 of which may contain things that can be combined. */
5372 /* It is possible to have a subexpression appear twice in the insn.
5373 Suppose that FROM is a register that appears within TO.
5374 Then, after that subexpression has been scanned once by `subst',
5375 the second time it is scanned, TO may be found. If we were
5376 to scan TO here, we would find FROM within it and create a
5377 self-referent rtl structure which is completely wrong. */
5381 /* Parallel asm_operands need special attention because all of the
5382 inputs are shared across the arms. Furthermore, unsharing the
5383 rtl results in recognition failures. Failure to handle this case
5384 specially can result in circular rtl.
5386 Solve this by doing a normal pass across the first entry of the
5387 parallel, and only processing the SET_DESTs of the subsequent
5388 entries. Ug. */
5393 {
5396 /* If this substitution failed, this whole thing fails. */
5404 {
5408 {
5411 /* If this substitution failed, this whole thing fails. */
5417 }
5418 }
5419 }
5420 else
5421 {
5425 /* We don't need to process a SET_DEST that is a register or PC, so
5426 set up to skip this common case. All other cases where we want
5427 to suppress replacing something inside a SET_SRC are handled via
5428 the IN_DEST operand. */
5434 /* Trying to simplify the operands of a widening MULT is not likely
5435 to create RTL matching a machine insn. */
5447 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5448 constant. */
5453 {
5455 {
5458 {
5460 {
5463 n_occurrences++;
5464 }
5465 else
5466 {
5468 unique_copy);
5470 /* If this substitution failed, this whole thing
5471 fails. */
5475 }
5478 }
5479 }
5481 {
5482 /* If this is a register being set, ignore it. */
5489 ;
5492 {
5493 /* In general, don't install a subreg involving two
5494 modes not tieable. It can worsen register
5495 allocation, and can even make invalid reload
5496 insns, since the reg inside may need to be copied
5497 from in the outside mode, and that may be invalid
5498 if it is an fp reg copied in integer mode.
5500 We allow an exception to this: It is valid if
5501 it is inside another SUBREG and the mode of that
5502 SUBREG and the mode of the inside of TO is
5503 tieable. */
5522 n_occurrences++;
5523 }
5524 else
5525 /* If we are in a SET_DEST, suppress most cases unless we
5526 have gone inside a MEM, in which case we want to
5527 simplify the address. We assume here that things that
5528 are actually part of the destination have their inner
5529 parts in the first expression. This is true for SUBREG,
5530 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5531 things aside from REG and MEM that should appear in a
5532 SET_DEST. */
5534 (((in_dest
5540 unique_copy);
5542 /* If we found that we will have to reject this combination,
5543 indicate that by returning the CLOBBER ourselves, rather than
5544 an expression containing it. This will speed things up as
5545 well as prevent accidents where two CLOBBERs are considered
5546 to be equal, thus producing an incorrect simplification. */
5552 {
5560 }
5566 {
5568 new_rtx,
5572 }
5573 /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5574 etc. arguments, otherwise we can ICE before trying to recog
5575 it. See PR104446. */
5579 else
5581 }
5582 }
5583 }
5585 /* Check if we are loading something from the constant pool via float
5586 extension; in this case we would undo compress_float_constant
5587 optimization and degenerate constant load to an immediate value. */
5591 {
5595 }
5597 /* Try to simplify X. If the simplification changed the code, it is likely
5598 that further simplification will help, so loop, but limit the number
5599 of repetitions that will be performed. */
5602 {
5603 /* If X is sufficiently simple, don't bother trying to do anything
5604 with it. */
5613 /* We no longer know the original mode of operand 0 since we
5614 have changed the form of X) */
5616 }
5619 }
5620 \f
5621 /* If X is a commutative operation whose operands are not in the canonical
5622 order, use substitutions to swap them. */
5624 static void
5626 {
5629 {
5633 }
5634 }
5636 /* Simplify X, a piece of RTL. We just operate on the expression at the
5637 outer level; call `subst' to simplify recursively. Return the new
5638 expression.
5640 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5641 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5642 of a condition. */
5644 static rtx
5647 {
5650 scalar_int_mode int_mode;
5651 rtx temp;
5654 /* If this is a commutative operation, put a constant last and a complex
5655 expression first. We don't need to do this for comparisons here. */
5658 /* Try to fold this expression in case we have constants that weren't
5659 present before. */
5662 {
5670 {
5673 {
5677 }
5680 }
5693 }
5696 {
5701 }
5703 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5704 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5705 things. Check for cases where both arms are testing the same
5706 condition.
5708 Don't do anything if all operands are very simple. */
5721 {
5726 /* If everything is a comparison, what we have is highly unlikely
5727 to be simpler, so don't use it. */
5730 /* Similarly, if we end up with one of the expressions the same
5731 as the original, it is certainly not simpler. */
5734 {
5741 /* Simplify the alternative arms; this may collapse the true and
5742 false arms to store-flag values. Be careful to use copy_rtx
5743 here since true_rtx or false_rtx might share RTL with x as a
5744 result of the if_then_else_cond call above. */
5748 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5749 is unlikely to be simpler. */
5752 {
5755 /* Restarting if we generate a store-flag expression will cause
5756 us to loop. Just drop through in this case. */
5758 /* If the result values are STORE_FLAG_VALUE and zero, we can
5759 just make the comparison operation. */
5770 /* Likewise, we can make the negate of a comparison operation
5771 if the result values are - STORE_FLAG_VALUE and zero. */
5779 mode);
5790 mode);
5794 }
5795 }
5796 }
5798 /* First see if we can apply the inverse distributive law. */
5801 {
5805 }
5807 /* If CODE is an associative operation not otherwise handled, see if we
5808 can associate some operands. This can win if they are constants or
5809 if they are logically related (i.e. (a & b) & a). */
5815 {
5817 {
5821 rtx inner;
5823 /* Make sure we pass the constant operand if any as the second
5824 one if this is a commutative operation. */
5832 /* For commutative operations, try the other pair if that one
5833 didn't simplify. */
5835 {
5840 }
5844 }
5845 }
5847 /* A little bit of algebraic simplification here. */
5849 {
5851 /* Ensure that our address has any ASHIFTs converted to MULT in case
5852 address-recognizing predicates are called later. */
5861 /* See if this can be moved to simplify_subreg. */
5864 /* Don't call gen_lowpart if the inner mode
5865 is VOIDmode and we cannot simplify it, as SUBREG without
5866 inner mode is invalid. */
5873 {
5874 rtx temp;
5880 /* If op is known to have all lower bits zero, the result is zero. */
5894 }
5896 /* Don't change the mode of the MEM if that would change the meaning
5897 of the address. */
5904 /* Note that we cannot do any narrowing for non-constants since
5905 we might have been counting on using the fact that some bits were
5906 zero. We now do this in the SET. */
5913 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5914 replaced by (lshiftrt X C). This will convert
5915 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5923 /* If X has only a single bit that might be nonzero, say, bit I, convert
5924 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5925 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5926 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5927 or a SUBREG of one since we'd be making the expression more
5928 complex if it was just a register. */
5935 {
5936 rtx temp1 = simplify_shift_const
5942 /* If all we did was surround TEMP with the two shifts, we
5943 haven't improved anything, so don't use it. Otherwise,
5944 we are better off with TEMP1. */
5949 }
5953 /* We can't handle truncation to a partial integer mode here
5954 because we don't know the real bitsize of the partial
5955 integer mode. */
5964 /* We can truncate a constant value and return it. */
5965 {
5966 poly_int64 c;
5969 }
5971 /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
5972 whose value is a comparison can be replaced with a subreg if
5973 STORE_FLAG_VALUE permits. */
5983 /* (const (const X)) can become (const X). Do it this way rather than
5984 returning the inner CONST since CONST can be shared with a
5985 REG_EQUAL note. */
5991 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5992 can add in an offset. find_split_point will split this address up
5993 again if it doesn't match. */
6000 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6001 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6002 bit-field and can be replaced by either a sign_extend or a
6003 sign_extract. The `and' may be a zero_extend and the two
6004 <c>, -<c> constants may be reversed. */
6021 return simplify_shift_const
6028 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6029 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6030 the bitsize of the mode - 1. This allows simplification of
6031 "a = (b & 8) == 0;" */
6038 return simplify_shift_const
6042 const1_rtx),
6046 /* If we are adding two things that have no bits in common, convert
6047 the addition into an IOR. This will often be further simplified,
6048 for example in cases like ((a & 1) + (a & 2)), which can
6049 become a & 3. */
6054 {
6055 /* Try to simplify the expression further. */
6059 /* If we could, great. If not, do not go ahead with the IOR
6060 replacement, since PLUS appears in many special purpose
6061 address arithmetic instructions. */
6069 }
6071 /* Canonicalize x + x into x << 1. */
6080 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6081 (and <foo> (const_int pow2-1)) */
6092 /* If we have (mult (plus A B) C), apply the distributive law and then
6093 the inverse distributive law to see if things simplify. This
6094 occurs mostly in addresses, often when unrolling loops. */
6097 {
6101 }
6103 /* Try simplify a*(b/c) as (a*b)/c. */
6106 {
6112 }
6116 /* If this is a divide by a power of two, treat it as a shift if
6117 its first operand is a shift. */
6137 /* If the first operand is a condition code, we can't do anything
6138 with it. */
6141 {
6149 /* Simplify our comparison, if possible. */
6152 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6153 if only the low-order bit is possibly nonzero in X (such as when
6154 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6155 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6156 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6157 (plus X 1).
6159 Remove any ZERO_EXTRACT we made when thinking this was a
6160 comparison. It may now be simpler to use, e.g., an AND. If a
6161 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6162 the call to make_compound_operation in the SET case.
6164 Don't apply these optimizations if the caller would
6165 prefer a comparison rather than a value.
6166 E.g., for the condition in an IF_THEN_ELSE most targets need
6167 an explicit comparison. */
6170 ;
6188 {
6192 int_mode);
6193 }
6201 {
6205 const1_rtx);
6206 }
6215 {
6218 }
6220 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6221 those above. */
6223 ;
6240 {
6244 int_mode);
6245 }
6254 {
6258 int_mode);
6259 }
6261 /* If X is 0/1, (eq X 0) is X-1. */
6268 {
6271 }
6273 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6274 one bit that might be nonzero, we can convert (ne x 0) to
6275 (ashift x c) where C puts the bit in the sign bit. Remove any
6276 AND with STORE_FLAG_VALUE when we are done, since we are only
6277 going to test the sign bit. */
6285 {
6291 else
6293 }
6295 /* If the code changed, return a whole new comparison.
6296 We also need to avoid using SUBST in cases where
6297 simplify_comparison has widened a comparison with a CONST_INT,
6298 since in that case the wider CONST_INT may fail the sanity
6299 checks in do_SUBST. */
6306 /* Otherwise, keep this operation, but maybe change its operands.
6307 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6310 }
6320 /* If we are processing SET_DEST, we are done. */
6338 /* If this is a shift by a constant amount, simplify it. */
6346 (HOST_WIDE_INT_1U
6353 {
6357 /* If we select a low-part subreg, return that. */
6359 {
6363 }
6364 }
6368 }
6371 }
6372 \f
6373 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6375 static rtx
6377 {
6384 rtx temp;
6387 rtx reversed;
6390 /* Simplify storing of the truth value. */
6395 /* Also when the truth value has to be reversed. */
6401 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6402 in it is being compared against certain values. Get the true and false
6403 comparisons and see if that says anything about the value of each arm. */
6409 {
6410 HOST_WIDE_INT nzb;
6416 /* If FALSE_CODE is EQ, swap the codes and arms. */
6419 {
6422 }
6424 scalar_int_mode from_mode;
6426 {
6427 /* If we are comparing against zero and the expression being
6428 tested has only a single bit that might be nonzero, that is
6429 its value when it is not equal to zero. Similarly if it is
6430 known to be -1 or 0. */
6434 {
6437 }
6442 {
6445 }
6446 }
6448 /* Now simplify an arm if we know the value of the register in the
6449 branch and it is used in the arm. Be careful due to the potential
6450 of locally-shared RTL. */
6467 }
6469 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6470 reversed, do so to avoid needing two sets of patterns for
6471 subtract-and-branch insns. Similarly if we have a constant in the true
6472 arm, the false arm is the same as the first operand of the comparison, or
6473 the false arm is more complicated than the true arm. */
6486 {
6494 /* It is possible that the conditional has been simplified out. */
6497 }
6499 /* If the two arms are identical, we don't need the comparison. */
6504 /* Convert a == b ? b : a to "a". */
6516 /* Look for cases where we have (abs x) or (neg (abs X)). */
6519 && comparison_p
6526 {
6532 return
6535 mode);
6538 }
6540 /* Look for MIN or MAX. */
6543 || (flag_unsafe_math_optimizations
6546 && comparison_p
6551 {
6566 }
6568 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6569 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6570 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6571 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6572 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6573 neither 1 or -1, but it isn't worth checking for. */
6576 && comparison_p
6579 {
6595 /* If an identity-zero op is commutative, check whether there
6596 would be a match if we swapped the operands. */
6617 {
6621 }
6634 {
6638 }
6655 {
6659 }
6672 {
6676 }
6679 {
6689 const_true_rtx));
6697 }
6698 }
6700 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6701 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6702 negation of a single bit, we can convert this operation to a shift. We
6703 can actually do this more generally, but it doesn't seem worth it. */
6715 return
6719 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6720 non-zero bit in A is C1. */
6728 {
6734 }
6737 }
6738 \f
6739 /* Simplify X, a SET expression. Return the new expression. */
6741 static rtx
6743 {
6746 machine_mode mode
6750 scalar_int_mode int_mode;
6752 /* (set (pc) (return)) gets written as (return). */
6756 /* Now that we know for sure which bits of SRC we are using, see if we can
6757 simplify the expression for the object knowing that we only need the
6758 low-order bits. */
6761 {
6764 }
6766 /* If the source is a COMPARE, look for the use of the comparison result
6767 and try to simplify it unless we already have used undobuf.other_insn. */
6773 {
6782 {
6785 {
6788 }
6789 }
6790 else
6798 {
6802 }
6803 else
6804 {
6809 /* Attempt to simplify CC user. */
6811 {
6815 }
6817 /* Convert X into a no-op move. */
6821 }
6823 /* Simplify our comparison, if possible. */
6826 #ifdef SELECT_CC_MODE
6827 /* If this machine has CC modes other than CCmode, check to see if we
6828 need to use a different CC mode here. */
6837 else
6840 /* If the mode changed, we have to change SET_DEST, the mode in the
6841 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6842 a hard register, just build new versions with the proper mode. If it
6843 is a pseudo, we lose unless it is only time we set the pseudo, in
6844 which case we can safely change its mode. */
6846 {
6848 {
6850 rtx new_dest;
6854 else
6855 {
6858 }
6865 }
6866 }
6869 /* If the code changed, we have to build a new comparison in
6870 undobuf.other_insn. */
6872 {
6881 /* If the only change we made was to change an EQ into an NE or
6882 vice versa, OP0 has only one bit that might be nonzero, and OP1
6883 is zero, check if changing the user of the condition code will
6884 produce a valid insn. If it won't, we can keep the original code
6885 in that insn by surrounding our operation with an XOR. */
6892 {
6897 {
6904 }
6905 }
6906 }
6911 /* Don't generate a compare of a CC with 0, just use that CC. */
6913 {
6916 }
6917 /* Otherwise, if we didn't previously have the same COMPARE we
6918 want, create it from scratch. */
6921 {
6924 }
6925 }
6926 else
6927 {
6928 /* Get SET_SRC in a form where we have placed back any
6929 compound expressions. Then do the checks below. */
6932 }
6934 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6935 and X being a REG or (subreg (reg)), we may be able to convert this to
6936 (set (subreg:m2 x) (op)).
6938 We can always do this if M1 is narrower than M2 because that means that
6939 we only care about the low bits of the result.
6941 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6942 perform a narrower operation than requested since the high-order bits will
6943 be undefined. On machine where it is defined, this transformation is safe
6944 as long as M1 and M2 have the same number of words. */
6948 && (known_equal_after_align_up
6951 UNITS_PER_WORD))
6960 {
6963 dest));
6967 }
6969 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6970 would require a paradoxical subreg. Replace the subreg with a
6971 zero_extend to avoid the reload that would otherwise be required.
6972 Don't do this unless we have a scalar integer mode, otherwise the
6973 transformation is incorrect. */
6980 {
6985 }
6987 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6988 are comparing an item known to be 0 or -1 against 0, use a logical
6989 operation instead. Check for one of the arms being an IOR of the other
6990 arm with some value. We compute three terms to be IOR'ed together. In
6991 practice, at most two will be nonzero. Then we do the IOR's. */
6999 && (!HAVE_conditional_move
7004 {
7029 int_mode),
7030 false_rtx);
7036 term3));
7039 }
7041 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7042 whole thing fail. */
7047 else
7048 /* Convert this into a field assignment operation, if possible. */
7050 }
7051 \f
7052 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7053 result. */
7055 static rtx
7057 {
7060 scalar_int_mode mode;
7063 {
7065 /* We can call simplify_and_const_int only if we don't lose
7066 any (sign) bits when converting INTVAL (op1) to
7067 "unsigned HOST_WIDE_INT". */
7072 {
7079 }
7081 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7082 apply the distributive law and then the inverse distributive
7083 law to see if things simplify. */
7085 {
7089 }
7091 {
7095 }
7099 /* If we have (ior (and A B) C), apply the distributive law and then
7100 the inverse distributive law to see if things simplify. */
7103 {
7107 }
7110 {
7114 }
7119 }
7122 }
7123 \f
7124 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7125 operations" because they can be replaced with two more basic operations.
7126 ZERO_EXTEND is also considered "compound" because it can be replaced with
7127 an AND operation, which is simpler, though only one operation.
7129 The function expand_compound_operation is called with an rtx expression
7130 and will convert it to the appropriate shifts and AND operations,
7131 simplifying at each stage.
7133 The function make_compound_operation is called to convert an expression
7134 consisting of shifts and ANDs into the equivalent compound expression.
7135 It is the inverse of this function, loosely speaking. */
7137 static rtx
7139 {
7143 rtx tem;
7144 scalar_int_mode inner_mode;
7147 {
7150 /* FALLTHRU */
7152 /* We can't necessarily use a const_int for a multiword mode;
7153 it depends on implicitly extending the value.
7154 Since we don't know the right way to extend it,
7155 we can't tell whether the implicit way is right.
7157 Even for a mode that is no wider than a const_int,
7158 we can't win, because we need to sign extend one of its bits through
7159 the rest of it, and we don't know which bit. */
7163 /* Reject modes that aren't scalar integers because turning vector
7164 or complex modes into shifts causes problems. */
7168 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7169 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7170 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7171 reloaded. If not for that, MEM's would very rarely be safe.
7173 Reject modes bigger than a word, because we might not be able
7174 to reference a two-register group starting with an arbitrary register
7175 (and currently gen_lowpart might crash for a SUBREG). */
7181 /* If the inner object has VOIDmode (the only way this can happen
7182 is if it is an ASM_OPERANDS), we can't do anything since we don't
7183 know how much masking to do. */
7192 /* fall through */
7195 /* If the operand is a CLOBBER, just return it. */
7203 /* Reject modes that aren't scalar integers because turning vector
7204 or complex modes into shifts causes problems. */
7211 /* This should stay within the object being extracted, fail otherwise. */
7222 }
7224 /* We've rejected non-scalar operations by now. */
7227 /* Convert sign extension to zero extension, if we know that the high
7228 bit is not set, as this is easier to optimize. It will be converted
7229 back to cheaper alternative in make_extraction. */
7235 {
7239 /* Make sure this is a profitable operation. */
7246 else
7248 }
7250 /* We can optimize some special cases of ZERO_EXTEND. */
7252 {
7253 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7254 know that the last value didn't have any inappropriate bits
7255 set. */
7263 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7272 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7273 is a comparison and STORE_FLAG_VALUE permits. This is like
7274 the first case, but it works even when MODE is larger
7275 than HOST_WIDE_INT. */
7283 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7292 }
7294 /* If we reach here, we want to return a pair of shifts. The inner
7295 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7296 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7297 logical depending on the value of UNSIGNEDP.
7299 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7300 converted into an AND of a shift.
7302 We must check for the case where the left shift would have a negative
7303 count. This can happen in a case like (x >> 31) & 255 on machines
7304 that can't shift by a constant. On those machines, we would first
7305 combine the shift with the AND to produce a variable-position
7306 extraction. Then the constant of 31 would be substituted in
7307 to produce such a position. */
7311 {
7319 }
7321 {
7329 }
7330 else
7331 /* Any other cases we can't handle. */
7334 /* If we couldn't do this for some reason, return the original
7335 expression. */
7340 }
7341 \f
7342 /* X is a SET which contains an assignment of one object into
7343 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7344 or certain SUBREGS). If possible, convert it into a series of
7345 logical operations.
7347 We half-heartedly support variable positions, but do not at all
7348 support variable lengths. */
7350 static const_rtx
7352 {
7353 rtx inner;
7357 scalar_int_mode compute_mode;
7359 /* Loop until we find something we can't simplify. */
7361 {
7364 {
7370 MAX_MODE_INT);
7371 }
7374 {
7382 /* A constant position should stay within the width of INNER. */
7387 {
7393 /* If position is ADJUST - X, new position is X. */
7395 else
7399 pos);
7400 }
7401 }
7403 /* If the destination is a subreg that overwrites the whole of the inner
7404 register, we can move the subreg to the source. */
7406 /* We need SUBREGs to compute nonzero_bits properly. */
7407 && nonzero_sign_valid
7409 {
7411 gen_lowpart
7415 }
7416 else
7422 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7424 {
7425 /* Don't do anything for vector or complex integral types. */
7429 /* Try to find an integral mode to pun with. */
7435 }
7437 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7441 /* Don't try to compute in too wide unsupported modes. */
7445 /* Now compute the equivalent expression. Make a copy of INNER
7446 for the SET_DEST in case it is a MEM into which we will substitute;
7447 we don't want shared RTL in that case. */
7449 compute_mode);
7453 compute_mode,
7455 compute_mode),
7456 inner);
7461 mask),
7462 pos);
7467 }
7470 }
7471 \f
7472 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7473 it is an RTX that represents the (variable) starting position; otherwise,
7474 POS is the (constant) starting bit position. Both are counted from the LSB.
7476 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7478 IN_DEST is nonzero if this is a reference in the destination of a SET.
7479 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7480 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7481 be used.
7483 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7484 ZERO_EXTRACT should be built even for bits starting at bit 0.
7486 MODE is the desired mode of the result (if IN_DEST == 0).
7488 The result is an RTX for the extraction or NULL_RTX if the target
7489 can't handle it. */
7491 static rtx
7495 {
7496 /* This mode describes the size of the storage area
7497 to fetch the overall value from. Within that, we
7498 ignore the POS lowest bits, etc. */
7500 machine_mode inner_mode;
7501 scalar_int_mode wanted_inner_mode;
7507 HOST_WIDE_INT orig_pos;
7515 /* If trying or potentionally trying to extract
7516 bits outside of is_mode, don't look through
7517 non-paradoxical SUBREGs. See PR82192. */
7520 {
7521 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7522 consider just the QI as the memory to extract from.
7523 The subreg adds or removes high bits; its mode is
7524 irrelevant to the meaning of this extraction,
7525 since POS and LEN count from the lsb. */
7529 }
7534 {
7535 /* We're extracting the least significant bits of an rtx
7536 (ashift X (const_int C)), where LEN > C. Extract the
7537 least significant (LEN - C) bits of X, giving an rtx
7538 whose mode is MODE, then shift it left C times. */
7544 }
7548 {
7549 /* We're extracting the least significant bits of an rtx
7550 (mult X (const_int 2^C)), where LEN > C. Extract the
7551 least significant (LEN - C) bits of X, giving an rtx
7552 whose mode is MODE, then multiply it by 2^C. */
7555 {
7561 }
7562 }
7564 /* If trying or potentionally trying to extract
7565 bits outside of is_mode, don't look through
7566 TRUNCATE. See PR82192. */
7573 /* See if this can be done without an extraction. We never can if the
7574 width of the field is not the same as that of some integer mode. For
7575 registers, we can only avoid the extraction if the position is at the
7576 low-order bit and this is either not in the destination or we have the
7577 appropriate STRICT_LOW_PART operation available.
7579 For MEM, we can avoid an extract if the field starts on an appropriate
7580 boundary and we can change the mode of the memory reference. */
7582 scalar_int_mode tmode;
7591 && (! in_dest
7595 && (pos
7598 /* We can't do this if we are widening INNER_MODE (it
7599 may not be aligned, for one thing). */
7606 {
7607 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7608 field. If the original and current mode are the same, we need not
7609 adjust the offset. Otherwise, we do if bytes big endian.
7611 If INNER is not a MEM, get a piece consisting of just the field
7612 of interest (in this case POS % BITS_PER_WORD must be 0). */
7615 {
7616 poly_int64 offset;
7618 /* POS counts from lsb, but make OFFSET count in memory order. */
7622 else
7626 }
7628 {
7630 {
7631 /* We can't call gen_lowpart in a DEST since we
7632 always want a SUBREG (see below) and it would sometimes
7633 return a new hard register. */
7635 {
7636 poly_uint64 offset
7639 /* Avoid creating invalid subregs, for example when
7640 simplifying (x>>32)&255. */
7645 }
7646 else
7648 }
7649 else
7651 }
7652 else
7654 len >= HOST_BITS_PER_WIDE_INT
7655 ? HOST_WIDE_INT_M1U
7658 /* If this extraction is going into the destination of a SET,
7659 make a STRICT_LOW_PART unless we made a MEM. */
7674 /* If we know that no extraneous bits are set, and that the high
7675 bit is not set, convert the extraction to the cheaper of
7676 sign and zero extension, that are equivalent in these cases. */
7682 {
7686 /* Prefer ZERO_EXTENSION, since it gives more information to
7687 backends. */
7692 }
7694 /* Otherwise, sign- or zero-extend unless we already are in the
7695 proper mode. */
7699 }
7701 /* Unless this is a COMPARE or we have a funny memory reference,
7702 don't do anything with zero-extending field extracts starting at
7703 the low-order bit since they are simple AND operations. */
7708 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7709 if the position is not a constant and the length is not 1. In all
7710 other cases, we would only be going outside our object in cases when
7711 an original shift would have been undefined. */
7720 /* If INNER is not from memory, we want it to have the mode of a register
7721 extraction pattern's structure operand, or word_mode if there is no
7722 such pattern. The same applies to extraction_mode and pos_mode
7723 and their respective operands.
7725 For memory, assume that the desired extraction_mode and pos_mode
7726 are the same as for a register operation, since at present we don't
7727 have named patterns for aligned memory structures. */
7732 {
7736 }
7738 /* Never narrow an object, since that might not be safe. */
7744 /* Punt if len is too large for extraction_mode. */
7750 else
7751 {
7752 /* Be careful not to go beyond the extracted object and maintain the
7753 natural alignment of the memory. */
7758 }
7763 {
7764 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7765 BITS_BIG_ENDIAN style. If position is constant, compute new
7766 position. Otherwise, build subtraction.
7767 Note that POS is relative to the mode of the original argument.
7768 If it's a MEM we need to recompute POS relative to that.
7769 However, if we're extracting from (or inserting into) a register,
7770 we want to recompute POS relative to wanted_inner_mode. */
7779 else
7780 pos_rtx
7783 pos_rtx);
7784 /* POS may be less than 0 now, but we check for that below.
7785 Note that it can only be less than 0 if !MEM_P (inner). */
7786 }
7788 /* If INNER has a wider mode, and this is a constant extraction, try to
7789 make it smaller and adjust the byte to point to the byte containing
7790 the value. */
7793 && ! pos_rtx
7798 {
7801 /* The computations below will be correct if the machine is big
7802 endian in both bits and bytes or little endian in bits and bytes.
7803 If it is mixed, we must adjust. */
7805 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7806 adjust OFFSET to compensate. */
7811 /* We can now move to the desired byte. */
7822 }
7824 /* If INNER is not memory, get it into the proper mode. If we are changing
7825 its mode, POS must be a constant and smaller than the size of the new
7826 mode. */
7828 {
7829 /* On the LHS, don't create paradoxical subregs implicitely truncating
7830 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7833 wanted_inner_mode))
7845 pos_rtx
7847 ? HOST_WIDE_INT_M1U
7851 }
7853 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7854 have to zero extend. Otherwise, we can just use a SUBREG.
7856 We dealt with constant rtxes earlier, so pos_rtx cannot
7857 have VOIDmode at this point. */
7861 {
7865 /* If we know that no extraneous bits are set, and that the high
7866 bit is not set, convert extraction to cheaper one - either
7867 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7868 cases. */
7876 {
7880 /* Prefer ZERO_EXTENSION, since it gives more information to
7881 backends. */
7885 }
7887 }
7889 /* Make POS_RTX unless we already have it and it is correct. If we don't
7890 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7891 be a CONST_INT. */
7898 /* Make the required operation. See if we can use existing rtx. */
7905 }
7906 \f
7907 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7908 can be commuted with any other operations in X. Return X without
7909 that shift if so. */
7911 static rtx
7913 {
7915 rtx tem;
7918 {
7920 /* This is the shift itself. If it is wide enough, we will return
7921 either the value being shifted if the shift count is equal to
7922 COUNT or a shift for the difference. */
7936 /* If we can safely shift this constant and we find the inner shift,
7937 make a new operation. */
7942 {
7946 }
7951 }
7954 }
7955 \f
7956 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7957 level of the expression and MODE is its mode. IN_CODE is as for
7958 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7959 that should be used when recursing on operands of *X_PTR.
7961 There are two possible actions:
7963 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7964 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7966 - Return a new rtx, which the caller returns directly. */
7968 static rtx
7972 {
7980 rtx tem;
7981 scalar_int_mode inner_mode;
7985 {
7988 }
7990 /* Process depending on the code of this operation. If NEW is set
7991 nonzero, it will be returned. */
7994 {
7996 /* Convert shifts by constants into multiplications if inside
7997 an address. */
8001 {
8007 {
8010 }
8013 }
8022 {
8026 }
8029 {
8033 mode));
8035 }
8036 else
8037 {
8040 }
8050 {
8054 }
8057 {
8061 mode));
8063 }
8064 else
8065 {
8069 }
8072 /* If the second operand is not a constant, we can't do anything
8073 with it. */
8077 /* If the constant is a power of two minus one and the first operand
8078 is a logical right shift, make an extraction. */
8081 {
8085 }
8087 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8094 {
8101 /* If we narrowed the mode when dropping the subreg, then we lose. */
8105 /* If that didn't give anything, see if the AND simplifies on
8106 its own. */
8108 {
8112 }
8113 }
8114 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8120 {
8121 /* Apply the distributive law, and then try to make extractions. */
8128 }
8130 /* If we are have (and (rotate X C) M) and C is larger than the number
8131 of bits in M, this is an extraction. */
8137 {
8143 }
8145 /* On machines without logical shifts, if the operand of the AND is
8146 a logical shift and our mask turns off all the propagated sign
8147 bits, we can replace the logical shift with an arithmetic shift. */
8155 {
8165 next_code),
8167 }
8169 /* If the constant is one less than a power of two, this might be
8170 representable by an extraction even if no shift is present.
8171 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8172 we are in a COMPARE. */
8176 next_code),
8179 /* If we are in a comparison and this is an AND with a power of two,
8180 convert this into the appropriate bit extract. */
8186 next_code),
8189 /* If the one operand is a paradoxical subreg of a register or memory and
8190 the constant (limited to the smaller mode) has only zero bits where
8191 the sub expression has known zero bits, this can be expressed as
8192 a zero_extend. */
8194 {
8195 rtx sub;
8203 {
8207 /* original AND constant with all the known zero bits set */
8210 {
8214 }
8215 }
8216 }
8221 /* If the sign bit is known to be zero, replace this with an
8222 arithmetic shift. */
8227 {
8230 next_code),
8233 }
8235 /* fall through */
8241 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8242 this is a SIGN_EXTRACT. */
8249 {
8256 }
8258 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8259 If so, try to merge the shifts into a SIGN_EXTEND. We could
8260 also do this for some cases of SIGN_EXTRACT, but it doesn't
8261 seem worth the effort; the case checked for occurs on Alpha. */
8272 next_code),
8279 /* Call ourselves recursively on the inner expression. If we are
8280 narrowing the object and it has a different RTL code from
8281 what it originally did, do this SUBREG as a force_to_mode. */
8282 {
8286 /* If the SUBREG is masking of a logical right shift,
8287 make an extraction. */
8294 {
8303 }
8305 /* If in_code is COMPARE, it isn't always safe to pass it through
8306 to the recursive make_compound_operation call. */
8310 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8311 is (const_int 0), rather than
8312 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8313 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8314 for non-equality comparisons against 0 is not equivalent
8315 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8325 simplified
8333 {
8334 rtx newer
8337 /* If we have something other than a SUBREG, we might have
8338 done an expansion, so rerun ourselves. */
8342 /* force_to_mode can expand compounds. If it just re-expanded
8343 the compound, use gen_lowpart to convert to the desired
8344 mode. */
8346 /* Likewise if it re-expanded the compound only partially.
8347 This happens for SUBREG of ZERO_EXTRACT if they extract
8348 the same number of bits. */
8357 }
8361 }
8366 }
8372 }
8374 /* Look at the expression rooted at X. Look for expressions
8375 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8376 Form these expressions.
8378 Return the new rtx, usually just X.
8380 Also, for machines like the VAX that don't have logical shift insns,
8381 try to convert logical to arithmetic shift operations in cases where
8382 they are equivalent. This undoes the canonicalizations to logical
8383 shifts done elsewhere.
8385 We try, as much as possible, to re-use rtl expressions to save memory.
8387 IN_CODE says what kind of expression we are processing. Normally, it is
8388 SET. In a memory address it is MEM. When processing the arguments of
8389 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8390 precisely it is an equality comparison against zero. */
8392 rtx
8394 {
8401 /* Select the code to be used in recursive calls. Once we are inside an
8402 address, we stay there. If we have a comparison, set to COMPARE,
8403 but once inside, go back to our default of SET. */
8410 scalar_int_mode mode;
8412 {
8418 }
8420 /* Now recursively process each operand of this operation. We need to
8421 handle ZERO_EXTEND specially so that we don't lose track of the
8422 inner mode. */
8424 {
8432 }
8437 {
8440 }
8443 {
8446 }
8450 }
8451 \f
8452 /* Given M see if it is a value that would select a field of bits
8453 within an item, but not the entire word. Return -1 if not.
8454 Otherwise, return the starting position of the field, where 0 is the
8455 low-order bit.
8457 *PLEN is set to the length of the field. */
8459 static int
8461 {
8462 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8467 /* Now shift off the low-order zero bits and see if we have a
8468 power of two minus 1. */
8476 }
8477 \f
8478 /* If X refers to a register that equals REG in value, replace these
8479 references with REG. */
8480 static rtx
8482 {
8490 {
8523 /* FALLTHRU */
8527 {
8531 else
8533 }
8535 /* fall through */
8542 {
8545 {
8547 {
8550 }
8552 }
8553 }
8555 {
8558 {
8561 {
8563 {
8566 }
8568 }
8569 }
8570 }
8573 }
8576 }
8578 /* Return X converted to MODE. If the value is already truncated to
8579 MODE we can just return a subreg even though in the general case we
8580 would need an explicit truncation. */
8582 static rtx
8584 {
8589 {
8590 /* Bit-cast X into an integer mode. */
8595 }
8598 }
8600 /* See if X can be simplified knowing that we will only refer to it in
8601 MODE and will only refer to those bits that are nonzero in MASK.
8602 If other bits are being computed or if masking operations are done
8603 that select a superset of the bits in MASK, they can sometimes be
8604 ignored.
8606 Return a possibly simplified expression, but always convert X to
8607 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8609 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8610 are all off in X. This is used when X will be complemented, by either
8611 NOT, NEG, or XOR. */
8613 static rtx
8616 {
8619 machine_mode op_mode;
8622 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8623 code below will do the wrong thing since the mode of such an
8624 expression is VOIDmode.
8626 Also do nothing if X is a CLOBBER; this can happen if X was
8627 the return value from a call to gen_lowpart. */
8631 /* We want to perform the operation in its present mode unless we know
8632 that the operation is valid in MODE, in which case we do the operation
8633 in MODE. */
8638 /* It is not valid to do a right-shift in a narrower mode
8639 than the one it came in with. */
8644 /* Truncate MASK to fit OP_MODE. */
8648 /* Determine what bits of X are guaranteed to be (non)zero. */
8651 /* If none of the bits in X are needed, return a zero. */
8655 /* If X is a CONST_INT, return a new one. Do this here since the
8656 test below will fail. */
8658 {
8661 else
8662 {
8665 }
8666 }
8668 /* If X is narrower than MODE and we want all the bits in X's mode, just
8669 get X in the proper mode. */
8674 /* We can ignore the effect of a SUBREG if it narrows the mode or
8675 if the constant masks to zero all the bits the mode doesn't have. */
8679 || (mask
8687 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8688 integer too. */
8694 }
8696 /* Subroutine of force_to_mode that handles cases in which both X and
8697 the result are scalar integers. MODE is the mode of the result,
8698 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8699 is preferred for simplified versions of X. The other arguments
8700 are as for force_to_mode. */
8702 static rtx
8706 {
8711 poly_int64 const_op0;
8713 /* When we have an arithmetic operation, or a shift whose count we
8714 do not know, we need to assume that all bits up to the highest-order
8715 bit in MASK will be needed. This is how we form such a mask. */
8718 else
8723 {
8725 /* If X is a (clobber (const_int)), return it since we know we are
8726 generating something that won't match. */
8739 /* Similarly for a truncate. */
8743 /* If this is an AND with a constant, convert it into an AND
8744 whose constant is the AND of that constant with MASK. If it
8745 remains an AND of MASK, delete it since it is redundant. */
8748 {
8753 /* If X is still an AND, see if it is an AND with a mask that
8754 is just some low-order bits. If so, and it is MASK, we don't
8755 need it. */
8761 /* If it remains an AND, try making another AND with the bits
8762 in the mode mask that aren't in MASK turned on. If the
8763 constant in the AND is wide enough, this might make a
8764 cheaper constant. */
8769 {
8770 unsigned HOST_WIDE_INT cval
8772 rtx y;
8779 }
8782 }
8787 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8788 low-order bits (as in an alignment operation) and FOO is already
8789 aligned to that boundary, mask C1 to that boundary as well.
8790 This may eliminate that PLUS and, later, the AND. */
8792 {
8796 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8797 number, sign extend it. */
8810 }
8812 /* fall through */
8815 /* Substituting into the operands of a widening MULT is not likely to
8816 create RTL matching a machine insn. */
8826 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8827 most significant bit in MASK since carries from those bits will
8828 affect the bits we are interested in. */
8833 /* If X is (minus C Y) where C's least set bit is larger than any bit
8834 in the mask, then we may replace with (neg Y). */
8837 {
8840 }
8842 /* Similarly, if C contains every bit in the fuller_mask, then we may
8843 replace with (not Y). */
8846 {
8849 }
8856 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8857 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8858 operation which may be a bitfield extraction. Ensure that the
8859 constant we form is not wider than the mode of X. */
8871 {
8874 xmode);
8880 }
8882 binop:
8883 /* For most binary operations, just propagate into the operation and
8884 change the mode if we have an operation of that mode. */
8889 /* If we ended up truncating both operands, truncate the result of the
8890 operation instead. */
8893 {
8896 }
8902 {
8905 }
8909 /* For left shifts, do the same, but just for the first operand.
8910 However, we cannot do anything with shifts where we cannot
8911 guarantee that the counts are smaller than the size of the mode
8912 because such a count will have a different meaning in a
8913 wider mode. */
8923 /* If the shift count is a constant and we can do arithmetic in
8924 the mode of the shift, refine which bits we need. Otherwise, use the
8925 conservative form of the mask. */
8931 else
8939 {
8942 }
8946 /* Here we can only do something if the shift count is a constant,
8947 this shift constant is valid for the host, and we can do arithmetic
8948 in OP_MODE. */
8954 {
8958 /* Select the mask of the bits we need for the shift operand. */
8961 /* We can only change the mode of the shift if we can do arithmetic
8962 in the mode of the shift and INNER_MASK is no wider than the
8963 width of X's mode. */
8970 {
8973 }
8974 }
8976 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8977 shift and AND produces only copies of the sign bit (C2 is one less
8978 than a power of two), we can do this with just a shift. */
8982 /* The shift puts one of the sign bit copies in the least significant
8983 bit. */
8988 /* Number of bits left after the shift must be more than the mask
8989 needs. */
8992 /* Must be more sign bit copies than the mask needs. */
8995 {
8999 }
9003 /* If we are just looking for the sign bit, we don't need this shift at
9004 all, even if it has a variable count. */
9008 /* If this is a shift by a constant, get a mask that contains those bits
9009 that are not copies of the sign bit. We then have two cases: If
9010 MASK only includes those bits, this can be a logical shift, which may
9011 allow simplifications. If MASK is a single-bit field not within
9012 those bits, we are requesting a copy of the sign bit and hence can
9013 shift the sign bit to the appropriate location. */
9017 {
9021 /* If the considered data is wider than HOST_WIDE_INT, we can't
9022 represent a mask for all its bits in a single scalar.
9023 But we only care about the lower bits, so calculate these. */
9026 {
9029 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9030 is the number of bits a full-width mask would have set.
9031 We need only shift if these are fewer than nonzero can
9032 hold. If not, we must keep all bits set in nonzero. */
9037 + HOST_BITS_PER_WIDE_INT
9039 }
9040 else
9041 {
9044 }
9047 {
9052 }
9055 {
9056 x = simplify_shift_const
9062 }
9063 }
9065 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9066 even if the shift count isn't a constant. */
9070 shiftrt:
9072 /* If this is a zero- or sign-extension operation that just affects bits
9073 we don't care about, remove it. Be sure the call above returned
9074 something that is still a shift. */
9084 next_select);
9090 /* If the shift count is constant and we can do computations
9091 in the mode of X, compute where the bits we care about are.
9092 Otherwise, we can't do anything. Don't change the mode of
9093 the shift or propagate MODE into the shift, though. */
9096 {
9105 }
9109 /* If we just want the low-order bit, the NEG isn't needed since it
9110 won't change the low-order bit. */
9114 /* We need any bits less significant than the most significant bit in
9115 MASK since carries from those bits will affect the bits we are
9116 interested in. */
9121 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9122 same as the XOR case above. Ensure that the constant we form is not
9123 wider than the mode of X. */
9131 {
9138 }
9140 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9141 use the full mask inside the NOT. */
9144 unop:
9147 next_select));
9149 {
9152 }
9156 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9157 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9158 which is equal to STORE_FLAG_VALUE. */
9170 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9171 written in a narrower mode. We play it safe and do not do so. */
9187 }
9189 /* Ensure we return a value of the proper mode. */
9191 }
9192 \f
9193 /* Return nonzero if X is an expression that has one of two values depending on
9194 whether some other value is zero or nonzero. In that case, we return the
9195 value that is being tested, *PTRUE is set to the value if the rtx being
9196 returned has a nonzero value, and *PFALSE is set to the other alternative.
9198 If we return zero, we set *PTRUE and *PFALSE to X. */
9200 static rtx
9202 {
9207 scalar_int_mode int_mode;
9209 /* If we are comparing a value against zero, we are done. */
9212 {
9216 }
9218 /* If this is a unary operation whose operand has one of two values, apply
9219 our opcode to compute those values. */
9222 {
9227 }
9229 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9230 make can't possibly match and would suppress other optimizations. */
9232 ;
9234 /* If this is a binary operation, see if either side has only one of two
9235 values. If either one does or if both do and they are conditional on
9236 the same value, compute the new true and false values. */
9238 {
9246 {
9247 /* Try to enable a simplification by undoing work done by
9248 if_then_else_cond if it converted a REG into something more
9249 complex. */
9251 {
9254 }
9255 else
9256 {
9259 }
9260 }
9264 {
9265 /* If if_then_else_cond returned zero, then true/false are the
9266 same rtl. We must copy one of them to prevent invalid rtl
9267 sharing. */
9274 {
9279 }
9280 else
9281 {
9284 }
9287 }
9289 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9290 operands is zero when the other is nonzero, and vice-versa,
9291 and STORE_FLAG_VALUE is 1 or -1. */
9297 {
9315 {
9322 const_true_rtx);
9324 }
9325 }
9327 /* Similarly for MULT, AND and UMIN, except that for these the result
9328 is always zero. */
9332 {
9346 {
9349 }
9350 }
9351 }
9354 {
9355 /* If we have IF_THEN_ELSE already, extract the condition and
9356 canonicalize it if it is NE or EQ. */
9362 {
9365 }
9366 else
9368 }
9370 /* If X is a SUBREG, we can narrow both the true and false values
9371 if the inner expression, if there is a condition. */
9375 {
9381 {
9385 }
9386 }
9388 /* If X is a constant, this isn't special and will cause confusions
9389 if we treat it as such. Likewise if it is equivalent to a constant. */
9392 ;
9394 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9395 will be least confusing to the rest of the compiler. */
9397 {
9400 }
9402 /* If X is known to be either 0 or -1, those are the true and
9403 false values when testing X. */
9408 {
9411 }
9413 /* Likewise for 0 or a single bit. */
9416 {
9419 }
9421 /* Otherwise fail; show no condition with true and false values the same. */
9424 }
9425 \f
9426 /* Return the value of expression X given the fact that condition COND
9427 is known to be true when applied to REG as its first operand and VAL
9428 as its second. X is known to not be shared and so can be modified in
9429 place.
9431 We only handle the simplest cases, and specifically those cases that
9432 arise with IF_THEN_ELSE expressions. */
9434 static rtx
9436 {
9444 /* If either operand of the condition is a floating point value,
9445 then we have to avoid collapsing an EQ comparison. */
9455 /* If X is (abs REG) and we know something about REG's relationship
9456 with zero, we may be able to simplify this. */
9460 {
9469 }
9471 /* The only other cases we handle are MIN, MAX, and comparisons if the
9472 operands are the same as REG and VAL. */
9475 {
9477 {
9480 }
9483 {
9485 {
9493 else
9495 }
9498 {
9501 /* Do not reverse the condition when it is NE or EQ.
9502 This is because we cannot conclude anything about
9503 the value of 'SMAX (x, y)' when x is not equal to y,
9504 but we can when x equals y. */
9510 {
9521 }
9522 }
9523 }
9524 }
9526 {
9531 {
9532 /* We must simplify subreg here, before we lose track of the
9533 original inner_mode. */
9538 else
9540 }
9543 }
9544 /* We don't have to handle SIGN_EXTEND here, because even in the
9545 case of replacing something with a modeless CONST_INT, a
9546 CONST_INT is already (supposed to be) a valid sign extension for
9547 its narrower mode, which implies it's already properly
9548 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9549 story is different. */
9551 {
9556 {
9557 /* We must simplify the zero_extend here, before we lose
9558 track of the original inner_mode. */
9563 else
9565 }
9568 }
9572 {
9579 }
9582 }
9583 \f
9584 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9585 assignment as a field assignment. */
9587 static int
9589 {
9591 {
9599 }
9607 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9608 Note that all SUBREGs of MEM are paradoxical; otherwise they
9609 would have been rewritten. */
9622 /* We used to see if get_last_value of X and Y were the same but that's
9623 not correct. In one direction, we'll cause the assignment to have
9624 the wrong destination and in the case, we'll import a register into this
9625 insn that might have already have been dead. So fail if none of the
9626 above cases are true. */
9628 }
9629 \f
9630 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9631 Return that assignment if so.
9633 We only handle the most common cases. */
9635 static rtx
9637 {
9640 rtx assign;
9642 HOST_WIDE_INT c1;
9643 HOST_WIDE_INT pos;
9645 rtx other;
9647 /* All the rules in this function are specific to scalar integers. */
9648 scalar_int_mode mode;
9652 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9653 a clear of a one-bit field. We will have changed it to
9654 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9655 for a SUBREG. */
9661 {
9667 }
9676 {
9683 }
9685 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9686 one-bit field. */
9690 {
9696 }
9698 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9699 SRC is an AND with all bits of that field set, then we can discard
9700 the AND. */
9705 {
9712 else
9715 /* Complete overlap. We can remove the source AND. */
9719 /* Partial overlap. We can reduce the source AND. */
9721 {
9725 }
9726 }
9728 /* The other case we handle is assignments into a constant-position
9729 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9730 a mask that has all one bits except for a group of zero bits and
9731 OTHER is known to have zeros where C1 has ones, this is such an
9732 assignment. Compute the position and length from C1. Shift OTHER
9733 to the appropriate position, force it to the required mode, and
9734 make the extraction. Check for the AND in both operands. */
9736 /* One or more SUBREGs might obscure the constant-position field
9737 assignment. The first one we are likely to encounter is an outer
9738 narrowing SUBREG, which we can just strip for the purposes of
9739 identifying the constant-field assignment. */
9756 /* The second SUBREG that might get in the way is a paradoxical
9757 SUBREG around the first operand of the AND. We want to
9758 pretend the operand is as wide as the destination here. We
9759 do this by adjusting the MEM to wider mode for the sole
9760 purpose of the call to rtx_equal_for_field_assignment_p. Also
9761 note this trick only works for MEMs. */
9773 /* The second SUBREG that might get in the way is a paradoxical
9774 SUBREG around the first operand of the AND. We want to
9775 pretend the operand is as wide as the destination here. We
9776 do this by adjusting the MEM to wider mode for the sole
9777 purpose of the call to rtx_equal_for_field_assignment_p. Also
9778 note this trick only works for MEMs. */
9786 else
9800 /* The mode to use for the source is the mode of the assignment, or of
9801 what is inside a possible STRICT_LOW_PART. */
9805 /* Shift OTHER right POS places and make it the source, restricting it
9806 to the proper length and mode. */
9810 dest);
9812 len >= HOST_BITS_PER_WIDE_INT
9813 ? HOST_WIDE_INT_M1U
9817 /* If SRC is masked by an AND that does not make a difference in
9818 the value being stored, strip it. */
9829 }
9830 \f
9831 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9832 if so. */
9834 static rtx
9836 {
9840 rtx tem;
9842 /* Distributivity is not true for floating point as it can change the
9843 value. So we don't do it unless -funsafe-math-optimizations. */
9848 /* The outer operation can only be one of the following: */
9856 /* If either operand is a primitive we can't do anything, so get out
9857 fast. */
9867 /* See if the inner and outer operations distribute. */
9869 {
9874 /* These all distribute except over PLUS. */
9885 /* This is also a multiply, so it distributes over everything. */
9888 /* This used to handle SUBREG, but this turned out to be counter-
9889 productive, since (subreg (op ...)) usually is not handled by
9890 insn patterns, and this "optimization" therefore transformed
9891 recognizable patterns into unrecognizable ones. Therefore the
9892 SUBREG case was removed from here.
9894 It is possible that distributing SUBREG over arithmetic operations
9895 leads to an intermediate result than can then be optimized further,
9896 e.g. by moving the outer SUBREG to the other side of a SET as done
9897 in simplify_set. This seems to have been the original intent of
9898 handling SUBREGs here.
9900 However, with current GCC this does not appear to actually happen,
9901 at least on major platforms. If some case is found where removing
9902 the SUBREG case here prevents follow-on optimizations, distributing
9903 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9907 }
9909 /* Set LHS and RHS to the inner operands (A and B in the example
9910 above) and set OTHER to the common operand (C in the example).
9911 There is only one way to do this unless the inner operation is
9912 commutative. */
9924 else
9927 /* Form the new inner operation, seeing if it simplifies first. */
9930 /* There is one exception to the general way of distributing:
9931 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9933 {
9936 }
9938 /* We may be able to continuing distributing the result, so call
9939 ourselves recursively on the inner operation before forming the
9940 outer operation, which we return. */
9943 }
9945 /* See if X is of the form (* (+ A B) C), and if so convert to
9946 (+ (* A C) (* B C)) and try to simplify.
9948 Most of the time, this results in no change. However, if some of
9949 the operands are the same or inverses of each other, simplifications
9950 will result.
9952 For example, (and (ior A B) (not B)) can occur as the result of
9953 expanding a bit field assignment. When we apply the distributive
9954 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9955 which then simplifies to (and (A (not B))).
9957 Note that no checks happen on the validity of applying the inverse
9958 distributive law. This is pointless since we can do it in the
9959 few places where this routine is called.
9961 N is the index of the term that is decomposed (the arithmetic operation,
9962 i.e. (+ A B) in the first example above). !N is the index of the term that
9963 is distributed, i.e. of C in the first example above. */
9964 static rtx
9966 {
9967 machine_mode mode;
9971 /* Distributivity is not true for floating point as it can change the
9972 value. So we don't do it unless -funsafe-math-optimizations. */
9989 /* Special case (and (xor B C) (not A)), which is equivalent to
9990 (xor (ior A B) (ior A C)) */
9992 {
9995 }
9998 {
9999 /* Distribute the second term. */
10002 }
10003 else
10004 {
10005 /* Distribute the first term. */
10008 }
10018 }
10019 \f
10020 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10021 in MODE. Return an equivalent form, if different from (and VAROP
10022 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10024 static rtx
10027 {
10030 rtx orig_varop;
10038 /* Simplify VAROP knowing that we will be only looking at some of the
10039 bits in it.
10041 Note by passing in CONSTOP, we guarantee that the bits not set in
10042 CONSTOP are not significant and will never be examined. We must
10043 ensure that is the case by explicitly masking out those bits
10044 before returning. */
10047 /* If VAROP is a CLOBBER, we will fail so return it. */
10051 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10052 to VAROP and return the new constant. */
10056 /* See what bits may be nonzero in VAROP. Unlike the general case of
10057 a call to nonzero_bits, here we don't care about bits outside
10058 MODE unless WORD_REGISTER_OPERATIONS is true. */
10065 /* Turn off all bits in the constant that are known to already be zero.
10066 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10067 which is tested below. */
10071 /* If we don't have any bits left, return zero. */
10075 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10076 a power of two, we can replace this with an ASHIFT. */
10081 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10082 or XOR, then try to apply the distributive law. This may eliminate
10083 operations if either branch can be simplified because of the AND.
10084 It may also make some cases more complex, but those cases probably
10085 won't match a pattern either with or without this. */
10088 {
10090 return
10091 gen_lowpart
10093 apply_distributive_law
10097 constop),
10100 constop))));
10101 }
10103 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10104 the AND and see if one of the operands simplifies to zero. If so, we
10105 may eliminate it. */
10109 {
10118 }
10120 /* Make a SUBREG if necessary. If we can't make it, fail. */
10125 /* If we are only masking insignificant bits, return VAROP. */
10132 /* Otherwise, return an AND. */
10134 }
10137 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10138 in MODE.
10140 Return an equivalent form, if different from X. Otherwise, return X. If
10141 X is zero, we are to always construct the equivalent form. */
10143 static rtx
10146 {
10157 }
10158 \f
10159 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10160 We don't care about bits outside of those defined in MODE.
10161 We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10163 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10164 a shift, AND, or zero_extract, we can do better. */
10166 static rtx
10168 scalar_int_mode mode,
10170 {
10171 rtx tem;
10174 /* If X is a register whose nonzero bits value is current, use it.
10175 Otherwise, if X is a register whose value we can find, use that
10176 value. Otherwise, use the previously-computed global nonzero bits
10177 for this register. */
10192 && !REGNO_REG_SET_P
10195 {
10196 /* Note that, even if the precision of last_set_mode is lower than that
10197 of mode, record_value_for_reg invoked nonzero_bits on the register
10198 with nonzero_bits_mode (because last_set_mode is necessarily integral
10199 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10200 are all valid, hence in mode too since nonzero_bits_mode is defined
10201 to the largest HWI_COMPUTABLE_MODE_P mode. */
10204 }
10208 {
10213 }
10216 {
10220 /* We don't know anything about the upper bits. */
10224 }
10227 }
10229 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10230 end of X that are known to be equal to the sign bit. X will be used
10231 in mode MODE; the returned value will always be between 1 and the
10232 number of bits in MODE. */
10234 static rtx
10236 scalar_int_mode mode,
10238 {
10239 rtx tem;
10252 && !REGNO_REG_SET_P
10255 {
10258 }
10269 }
10270 \f
10271 /* Return the number of "extended" bits there are in X, when interpreted
10272 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10273 unsigned quantities, this is the number of high-order zero bits.
10274 For signed quantities, this is the number of copies of the sign bit
10275 minus 1. In both case, this function returns the number of "spare"
10276 bits. For example, if two quantities for which this function returns
10277 at least 1 are added, the addition is known not to overflow.
10279 This function will always return 0 unless called during combine, which
10280 implies that it must be called from a define_split. */
10282 unsigned int
10284 {
10288 scalar_int_mode int_mode;
10296 }
10298 /* This function is called from `simplify_shift_const' to merge two
10299 outer operations. Specifically, we have already found that we need
10300 to perform operation *POP0 with constant *PCONST0 at the outermost
10301 position. We would now like to also perform OP1 with constant CONST1
10302 (with *POP0 being done last).
10304 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10305 the resulting operation. *PCOMP_P is set to 1 if we would need to
10306 complement the innermost operand, otherwise it is unchanged.
10308 MODE is the mode in which the operation will be done. No bits outside
10309 the width of this mode matter. It is assumed that the width of this mode
10310 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10312 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10313 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10314 result is simply *PCONST0.
10316 If the resulting operation cannot be expressed as one operation, we
10317 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10319 static int
10320 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10321 {
10328 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10332 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10333 if OP0 is SET. */
10342 {
10344 {
10362 }
10363 }
10365 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10369 /* If the two constants aren't the same, we can't do anything. The
10370 remaining six cases can all be done. */
10374 else
10376 {
10379 /* (a & b) | b == b */
10382 /* (a ^ b) | b == a | b */
10383 {;}
10388 /* (a & b) ^ b == (~a) & b */
10391 /* (a | b) ^ b == a & ~b */
10397 /* (a | b) & b == b */
10400 /* (a ^ b) & b) == (~a) & b */
10405 }
10407 /* Check for NO-OP cases. */
10420 /* ??? Slightly redundant with the above mask, but not entirely.
10421 Moving this above means we'd have to sign-extend the mode mask
10422 for the final test. */
10427 }
10428 \f
10429 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10430 the shift in. The original shift operation CODE is performed on OP in
10431 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10432 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10433 result of the shift is subject to operation OUTER_CODE with operand
10434 OUTER_CONST. */
10436 static scalar_int_mode
10440 {
10443 /* In general we can't perform in wider mode for right shift and rotate. */
10445 {
10447 /* We can still widen if the bits brought in from the left are identical
10448 to the sign bit of ORIG_MODE. */
10456 /* Similarly here but with zero bits. */
10461 /* We can also widen if the bits brought in will be masked off. This
10462 operation is performed in ORIG_MODE. */
10464 {
10470 }
10471 /* fall through */
10481 }
10482 }
10484 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10485 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10486 if we cannot simplify it. Otherwise, return a simplified value.
10488 The shift is normally computed in the widest mode we find in VAROP, as
10489 long as it isn't a different number of words than RESULT_MODE. Exceptions
10490 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10492 static rtx
10495 {
10500 machine_mode shift_mode;
10502 /* We form (outer_op (code varop count) (outer_const)). */
10508 /* Make sure and truncate the "natural" shift on the way in. We don't
10509 want to do this inside the loop as it makes it more difficult to
10510 combine shifts. */
10514 /* If we were given an invalid count, don't do anything except exactly
10515 what was requested. */
10522 /* Unless one of the branches of the `if' in this loop does a `continue',
10523 we will `break' the loop after the `if'. */
10526 {
10527 /* If we have an operand of (clobber (const_int 0)), fail. */
10531 /* Convert ROTATERT to ROTATE. */
10533 {
10537 }
10541 {
10542 /* We only change the modes of scalar shifts. */
10548 }
10550 scalar_int_mode shift_unit_mode
10553 /* Handle cases where the count is greater than the size of the mode
10554 minus 1. For ASHIFT, use the size minus one as the count (this can
10555 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10556 take the count modulo the size. For other shifts, the result is
10557 zero.
10559 Since these shifts are being produced by the compiler by combining
10560 multiple operations, each of which are defined, we know what the
10561 result is supposed to be. */
10564 {
10569 else
10570 {
10571 /* We can't simply return zero because there may be an
10572 outer op. */
10576 }
10577 }
10579 /* If we discovered we had to complement VAROP, leave. Making a NOT
10580 here would cause an infinite loop. */
10585 {
10586 /* An arithmetic right shift of a quantity known to be -1 or 0
10587 is a no-op. */
10591 {
10594 }
10596 /* If we are doing an arithmetic right shift and discarding all but
10597 the sign bit copies, this is equivalent to doing a shift by the
10598 bitsize minus one. Convert it into that shift because it will
10599 often allow other simplifications. */
10606 /* We simplify the tests below and elsewhere by converting
10607 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10608 `make_compound_operation' will convert it to an ASHIFTRT for
10609 those machines (such as VAX) that don't have an LSHIFTRT. */
10614 shift_unit_mode)))
10626 }
10629 {
10636 {
10639 }
10643 /* The following rules apply only to scalars. */
10648 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10649 minus the width of a smaller mode, we can do this with a
10650 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10657 {
10666 }
10670 /* The following rules apply only to scalars. */
10676 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10677 the same number of words as what we've seen so far. Then store
10678 the widest mode in MODE. */
10685 {
10690 }
10694 /* Some machines use MULT instead of ASHIFT because MULT
10695 is cheaper. But it is still better on those machines to
10696 merge two shifts into one. */
10699 {
10704 }
10708 /* Similar, for when divides are cheaper. */
10711 {
10716 }
10720 /* If we are extracting just the sign bit of an arithmetic
10721 right shift, that shift is not needed. However, the sign
10722 bit of a wider mode may be different from what would be
10723 interpreted as the sign bit in a narrower mode, so, if
10724 the result is narrower, don't discard the shift. */
10729 {
10732 }
10734 /* fall through */
10739 /* The following rules apply only to scalars. */
10746 /* Here we have two nested shifts. The result is usually the
10747 AND of a new shift with a mask. We compute the result below. */
10753 {
10757 rtx mask_rtx;
10759 /* We have one common special case. We can't do any merging if
10760 the inner code is an ASHIFTRT of a smaller mode. However, if
10761 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10762 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10763 we can convert it to
10764 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10765 This simplifies certain SIGN_EXTEND operations. */
10769 {
10770 /* C3 has the low-order C1 bits zero. */
10782 }
10784 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10785 than C1 high-order bits equal to the sign bit, we can convert
10786 this to either an ASHIFT or an ASHIFTRT depending on the
10787 two counts.
10789 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10795 {
10799 {
10802 }
10805 }
10807 /* There are some cases we can't do. If CODE is ASHIFTRT,
10808 we can only do this if FIRST_CODE is also ASHIFTRT.
10810 We can't do the case when CODE is ROTATE and FIRST_CODE is
10811 ASHIFTRT.
10813 If the mode of this shift is not the mode of the outer shift,
10814 we can't do this if either shift is a right shift or ROTATE.
10816 Finally, we can't do any of these if the mode is too wide
10817 unless the codes are the same.
10819 Handle the case where the shift codes are the same
10820 first. */
10823 {
10832 }
10843 /* To compute the mask to apply after the shift, shift the
10844 nonzero bits of the inner shift the same way the
10845 outer shift will. */
10848 int_result_mode);
10850 mask_rtx
10854 /* Give up if we can't compute an outer operation to use. */
10862 /* If the shifts are in the same direction, we add the
10863 counts. Otherwise, we subtract them. */
10867 else
10870 /* If COUNT is positive, the new shift is usually CODE,
10871 except for the two exceptions below, in which case it is
10872 FIRST_CODE. If the count is negative, FIRST_CODE should
10873 always be used */
10883 }
10885 /* If we have (A << B << C) for any shift, we can convert this to
10886 (A << C << B). This wins if A is a constant. Only try this if
10887 B is not a constant. */
10892 {
10893 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10894 sure the result will be masked. See PR70222. */
10902 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10903 up outer sign extension (often left and right shift) is
10904 hardly more efficient than the original. See PR70429.
10905 Similarly punt for rotates with different modes.
10906 See PR97386. */
10914 count_rtx);
10918 }
10922 /* The following rules apply only to scalars. */
10926 /* Make this fit the case below. */
10933 /* The following rules apply only to scalars. */
10939 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10940 with C the size of VAROP - 1 and the shift is logical if
10941 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10942 we have an (le X 0) operation. If we have an arithmetic shift
10943 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10944 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10952 {
10955 const0_rtx);
10961 }
10963 /* If we have (shift (logical)), move the logical to the outside
10964 to allow it to possibly combine with another logical and the
10965 shift to combine with another shift. This also canonicalizes to
10966 what a ZERO_EXTRACT looks like. Also, some machines have
10967 (and (shift)) insns. */
10970 /* We can't do this if we have (ashiftrt (xor)) and the
10971 constant has its sign bit set in shift_unit_mode with
10972 shift_unit_mode wider than result_mode. */
10985 {
10988 }
10990 /* If we can't do that, try to simplify the shift in each arm of the
10991 logical expression, make a new logical expression, and apply
10992 the inverse distributive law. This also can't be done for
10993 (ashiftrt (xor)) where we've widened the shift and the constant
10994 changes the sign bit. */
11000 {
11012 }
11016 /* The following rules apply only to scalars. */
11021 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11022 says that the sign bit can be tested, FOO has mode MODE, C is
11023 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11024 that may be nonzero. */
11034 {
11038 }
11042 /* The following rules apply only to scalars. */
11047 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11048 than the number of bits in the mode is equivalent to A. */
11052 {
11056 }
11058 /* NEG commutes with ASHIFT since it is multiplication. Move the
11059 NEG outside to allow shifts to combine. */
11063 {
11066 }
11070 /* The following rules apply only to scalars. */
11075 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11076 is one less than the number of bits in the mode is
11077 equivalent to (xor A 1). */
11084 {
11088 }
11090 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11091 that might be nonzero in BAR are those being shifted out and those
11092 bits are known zero in FOO, we can replace the PLUS with FOO.
11093 Similarly in the other operand order. This code occurs when
11094 we are computing the size of a variable-size array. */
11101 {
11104 }
11112 {
11115 }
11117 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11128 {
11131 }
11133 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11134 signbit', and attempt to change the PLUS to an XOR and move it to
11135 the outer operation as is done above in the AND/IOR/XOR case
11136 leg for shift(logical). See details in logical handling above
11137 for reasoning in doing so. */
11149 {
11152 }
11157 /* The following rules apply only to scalars. */
11162 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11163 with C the size of VAROP - 1 and the shift is logical if
11164 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11165 we have a (gt X 0) operation. If the shift is arithmetic with
11166 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11167 we have a (neg (gt X 0)) operation. */
11176 {
11179 const0_rtx);
11185 }
11189 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11190 if the truncate does not affect the value. */
11197 {
11201 new_count);
11204 new_count_rtx);
11208 }
11213 }
11216 }
11220 {
11221 /* We only change the modes of scalar shifts. */
11226 }
11228 /* We have now finished analyzing the shift. The result should be
11229 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11230 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11231 to the result of the shift. OUTER_CONST is the relevant constant,
11232 but we must turn off all bits turned off in the shift. */
11240 /* Make a SUBREG if necessary. If we can't make it, fail. */
11245 /* If we have an outer operation and we just made a shift, it is
11246 possible that we could have simplified the shift were it not
11247 for the outer operation. So try to do the simplification
11248 recursively. */
11252 else
11259 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11260 turn off all the bits that the shift would have turned off. */
11262 /* We only change the modes of scalar shifts. */
11266 /* Do the remainder of the processing in RESULT_MODE. */
11269 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11270 operation. */
11275 {
11285 {
11286 /* This means that we have determined that the result is
11287 equivalent to a constant. This should be rare. */
11290 }
11293 else
11296 }
11299 }
11301 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11302 The result of the shift is RESULT_MODE. If we cannot simplify it,
11303 return X or, if it is NULL, synthesize the expression with
11304 simplify_gen_binary. Otherwise, return a simplified value.
11306 The shift is normally computed in the widest mode we find in VAROP, as
11307 long as it isn't a different number of words than RESULT_MODE. Exceptions
11308 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11310 static rtx
11313 {
11324 }
11326 \f
11327 /* A subroutine of recog_for_combine. See there for arguments and
11328 return value. */
11330 static int
11332 {
11334 rtx pat_without_clobbers;
11342 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11343 we use to indicate that something didn't match. If we find such a
11344 thing, force rejection. */
11358 {
11361 else
11364 }
11366 /* If it isn't, there is the possibility that we previously had an insn
11367 that clobbered some register as a side effect, but the combined
11368 insn doesn't need to do that. So try once more without the clobbers
11369 unless this represents an ASM insn. */
11373 {
11378 {
11381 pos++;
11382 }
11392 {
11395 else
11398 }
11399 }
11406 /* Recognize all noop sets, these will be killed by followup pass. */
11410 /* If we had any clobbers to add, make a new pattern than contains
11411 them. Then check to make sure that all of them are dead. */
11413 {
11423 else
11430 {
11435 {
11439 }
11440 }
11442 }
11446 {
11454 /* Allow targets to reject combined insn. */
11456 {
11459 dump_file);
11461 /* Callers expect recog_for_combine to strip
11462 clobbers from the pattern on failure. */
11467 }
11472 }
11478 }
11480 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11481 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11482 Return whether anything was so changed. */
11484 static bool
11486 {
11492 {
11504 {
11514 else
11518 {
11524 }
11525 }
11531 {
11536 {
11542 }
11543 }
11548 {
11552 }
11553 else
11559 {
11562 }
11566 }
11573 scalar_int_mode mode;
11579 {
11593 else
11601 }
11604 }
11606 /* Like recog, but we receive the address of a pointer to a new pattern.
11607 We try to match the rtx that the pointer points to.
11608 If that fails, we may try to modify or replace the pattern,
11609 storing the replacement into the same pointer object.
11611 Modifications include deletion or addition of CLOBBERs. If the
11612 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11613 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11614 (and undo if that fails).
11616 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11617 the CLOBBERs are placed.
11619 The value is the final insn code from the pattern ultimately matched,
11620 or -1. */
11622 static int
11624 {
11634 {
11635 /* For an unrecognized single set of a constant, try placing it in
11636 the constant pool, if this function already uses one. */
11641 {
11647 {
11650 }
11651 }
11652 else
11654 }
11656 {
11659 {
11663 }
11664 }
11667 {
11672 }
11675 }
11676 \f
11677 /* Like gen_lowpart_general but for use by combine. In combine it
11678 is not possible to create any new pseudoregs. However, it is
11679 safe to create invalid memory addresses, because combine will
11680 try to recognize them and all they will do is make the combine
11681 attempt fail.
11683 If for some reason this cannot do its job, an rtx
11684 (clobber (const_int 0)) is returned.
11685 An insn containing that will not be recognized. */
11687 static rtx
11689 {
11691 rtx result;
11696 /* We can only support MODE being wider than a word if X is a
11697 constant integer or has a mode the same size. */
11703 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11704 won't know what to do. So we will strip off the SUBREG here and
11705 process normally. */
11707 {
11710 /* For use in case we fall down into the address adjustments
11711 further below, we need to adjust the known mode and size of
11712 x; imode and isize, since we just adjusted x. */
11717 }
11725 {
11726 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11727 address. */
11732 /* If we want to refer to something bigger than the original memref,
11733 generate a paradoxical subreg instead. That will force a reload
11734 of the original memref X. */
11740 }
11742 /* If X is a comparison operator, rewrite it in a new mode. This
11743 probably won't match, but may allow further simplifications. */
11749 /* If we couldn't simplify X any other way, just enclose it in a
11750 SUBREG. Normally, this SUBREG won't match, but some patterns may
11751 include an explicit SUBREG or we may simplify it further in combine. */
11752 else
11753 {
11754 rtx res;
11757 {
11762 }
11766 }
11768 fail:
11770 }
11771 \f
11772 /* Try to simplify a comparison between OP0 and a constant OP1,
11773 where CODE is the comparison code that will be tested, into a
11774 (CODE OP0 const0_rtx) form.
11776 The result is a possibly different comparison code to use.
11777 *POP1 may be updated. */
11779 static enum rtx_code
11782 {
11783 scalar_int_mode int_mode;
11786 /* Get the constant we are comparing against and turn off all bits
11787 not on in our mode. */
11791 /* If we are comparing against a constant power of two and the value
11792 being compared can only have that single bit nonzero (e.g., it was
11793 `and'ed with that bit), we can replace this with a comparison
11794 with zero. */
11803 {
11806 }
11808 /* Similarly, if we are comparing a value known to be either -1 or
11809 0 with -1, change it to the opposite comparison against zero. */
11815 {
11818 }
11820 /* Do some canonicalizations based on the comparison code. We prefer
11821 comparisons against zero and then prefer equality comparisons.
11822 If we can reduce the size of a constant, we will do that too. */
11824 {
11826 /* < C is equivalent to <= (C - 1) */
11828 {
11831 /* ... fall through to LE case below. */
11833 }
11834 else
11838 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11840 {
11843 }
11845 /* If we are doing a <= 0 comparison on a value known to have
11846 a zero sign bit, we can replace this with == 0. */
11857 /* >= C is equivalent to > (C - 1). */
11859 {
11862 /* ... fall through to GT below. */
11864 }
11865 else
11869 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11871 {
11874 }
11876 /* If we are doing a > 0 comparison on a value known to have
11877 a zero sign bit, we can replace this with != 0. */
11888 /* < C is equivalent to <= (C - 1). */
11890 {
11893 /* ... fall through ... */
11895 }
11896 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11901 {
11905 }
11906 else
11910 /* unsigned <= 0 is equivalent to == 0 */
11913 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11917 == ((HOST_WIDE_INT_1U
11919 {
11922 }
11926 /* >= C is equivalent to > (C - 1). */
11928 {
11931 /* ... fall through ... */
11933 }
11935 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11940 {
11944 }
11945 else
11949 /* unsigned > 0 is equivalent to != 0 */
11952 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11956 == (HOST_WIDE_INT_1U
11958 {
11961 }
11966 }
11970 }
11971 \f
11972 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11973 comparison code that will be tested.
11975 The result is a possibly different comparison code to use. *POP0 and
11976 *POP1 may be updated.
11978 It is possible that we might detect that a comparison is either always
11979 true or always false. However, we do not perform general constant
11980 folding in combine, so this knowledge isn't useful. Such tautologies
11981 should have been detected earlier. Hence we ignore all such cases. */
11983 static enum rtx_code
11985 {
11991 opt_scalar_int_mode tmode_iter;
11993 /* Try a few ways of applying the same transformation to both operands. */
11995 {
11996 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11997 so check specially. */
12016 {
12019 }
12021 /* If both operands are the same constant shift, see if we can ignore the
12022 shift. We can if the shift is a rotate or if the bits shifted out of
12023 this shift are known to be zero for both inputs and if the type of
12024 comparison is compatible with the shift. */
12037 {
12050 else
12052 }
12054 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12055 SUBREGs are of the same mode, and, in both cases, the AND would
12056 be redundant if the comparison was done in the narrower mode,
12057 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12058 and the operand's possibly nonzero bits are 0xffffff01; in that case
12059 if we only care about QImode, we don't need the AND). This case
12060 occurs if the output mode of an scc insn is not SImode and
12061 STORE_FLAG_VALUE == 1 (e.g., the 386).
12063 Similarly, check for a case where the AND's are ZERO_EXTEND
12064 operations from some narrower mode even though a SUBREG is not
12065 present. */
12070 {
12086 {
12090 /* The resulting comparison is always unsigned since we masked
12091 off the original sign bit. */
12095 }
12101 {
12107 }
12111 }
12113 /* If both operands are NOT, we can strip off the outer operation
12114 and adjust the comparison code for swapped operands; similarly for
12115 NEG, except that this must be an equality comparison. */
12121 else
12123 }
12125 /* If the first operand is a constant, swap the operands and adjust the
12126 comparison code appropriately, but don't do this if the second operand
12127 is already a constant integer. */
12129 {
12132 }
12134 /* We now enter a loop during which we will try to simplify the comparison.
12135 For the most part, we only are concerned with comparisons with zero,
12136 but some things may really be comparisons with zero but not start
12137 out looking that way. */
12140 {
12142 scalar_int_mode int_mode;
12146 HOST_WIDE_INT const_op;
12148 /* We only want to handle integral modes. This catches VOIDmode,
12149 CCmode, and the floating-point modes. An exception is that we
12150 can handle VOIDmode if OP0 is a COMPARE or a comparison
12151 operation. */
12158 /* Try to simplify the compare to constant, possibly changing the
12159 comparison op, and/or changing op1 to zero. */
12163 /* Compute some predicates to simplify code below. */
12170 /* If this is a sign bit comparison and we can do arithmetic in
12171 MODE, say that we will only be needing the sign bit of OP0. */
12176 HOST_WIDE_INT_1U
12181 {
12182 /* We can't do anything if OP0 is a condition code value, rather
12183 than an actual data value. */
12188 /* Get the two operands being compared. */
12191 else
12194 /* Check for the cases where we simply want the result of the
12195 earlier test or the opposite of that result. */
12199 {
12203 else
12207 {
12212 }
12213 }
12215 }
12221 /* Now try cases based on the opcode of OP0. If none of the cases
12222 does a "continue", we exit this loop immediately after the
12223 switch. */
12228 {
12230 /* If we are extracting a single bit from a variable position in
12231 a constant that has only a single bit set and are comparing it
12232 with zero, we can convert this into an equality comparison
12233 between the position and the location of the single bit. */
12234 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12235 have already reduced the shift count modulo the word size. */
12241 {
12249 /* Result is nonzero iff shift count is equal to I. */
12252 }
12254 /* fall through */
12259 {
12262 }
12266 /* If testing for equality, we can take the NOT of the constant. */
12269 {
12273 }
12275 /* If just looking at the sign bit, reverse the sense of the
12276 comparison. */
12278 {
12282 }
12286 /* If testing for equality, we can take the NEG of the constant. */
12289 {
12293 }
12295 /* The remaining cases only apply to comparisons with zero. */
12299 /* When X is ABS or is known positive,
12300 (neg X) is < 0 if and only if X != 0. */
12308 {
12312 }
12314 /* If we have NEG of something whose two high-order bits are the
12315 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12317 {
12321 }
12325 /* If we are testing equality and our count is a constant, we
12326 can perform the inverse operation on our RHS. */
12330 {
12334 }
12336 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12337 a particular bit. Convert it to an AND of a constant of that
12338 bit. This will be converted into a ZERO_EXTRACT. */
12343 {
12345 (HOST_WIDE_INT_1U
12350 }
12352 /* Fall through. */
12355 /* ABS is ignorable inside an equality comparison with zero. */
12357 {
12360 }
12364 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12365 (compare FOO CONST) if CONST fits in FOO's mode and we
12366 are either testing inequality or have an unsigned
12367 comparison with ZERO_EXTEND or a signed comparison with
12368 SIGN_EXTEND. But don't do it if we don't have a compare
12369 insn of the given mode, since we'd have to revert it
12370 later on, and then we wouldn't know whether to sign- or
12371 zero-extend. */
12373 && ! unsigned_comparison_p
12377 {
12380 }
12384 /* Check for the case where we are comparing A - C1 with C2, that is
12386 (subreg:MODE (plus (A) (-C1))) op (C2)
12388 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12389 comparison in the wider mode. One of the following two conditions
12390 must be true in order for this to be valid:
12392 1. The mode extension results in the same bit pattern being added
12393 on both sides and the comparison is equality or unsigned. As
12394 C2 has been truncated to fit in MODE, the pattern can only be
12395 all 0s or all 1s.
12397 2. The mode extension results in the sign bit being copied on
12398 each side.
12400 The difficulty here is that we have predicates for A but not for
12401 (A - C1) so we need to check that C1 is within proper bounds so
12402 as to perturbate A as little as possible. */
12411 {
12419 /* (A - C1) zero-extends if it is positive and sign-extends
12420 if it is negative, C2 both zero- and sign-extends. */
12424 /* (A - C1) sign-extends if it is positive and 1-extends
12425 if it is negative, C2 both sign- and 1-extends. */
12432 /* (A - C1) always sign-extends, like C2. */
12436 {
12439 }
12440 }
12442 /* If the inner mode is narrower and we are extracting the low part,
12443 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12445 ;
12454 {
12455 /* Remove outer subregs that don't do anything. */
12460 {
12464 }
12466 }
12467 else
12470 /* FALLTHROUGH */
12479 {
12482 }
12486 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12487 this for equality comparisons due to pathological cases involving
12488 overflows. */
12492 {
12496 }
12498 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12501 {
12505 }
12509 /* We used to optimize signed comparisons against zero, but that
12510 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12511 arrive here as equality comparisons, or (GEU, LTU) are
12512 optimized away. No need to special-case them. */
12514 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12515 (eq B (minus A C)), whichever simplifies. We can only do
12516 this for equality comparisons due to pathological cases involving
12517 overflows. */
12521 {
12525 }
12530 {
12534 }
12536 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12537 of bits in X minus 1, is one iff X > 0. */
12542 {
12546 }
12550 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12551 if C is zero or B is a constant. */
12555 {
12559 }
12564 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12565 iff X <= 0. */
12569 {
12573 }
12577 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12578 will be converted to a ZERO_EXTRACT later. */
12582 {
12587 }
12589 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12590 zero and X is a comparison and C1 and C2 describe only bits set
12591 in STORE_FLAG_VALUE, we can compare with X. */
12599 {
12606 {
12609 }
12610 }
12612 /* If we are doing an equality comparison of an AND of a bit equal
12613 to the sign bit, replace this with a LT or GE comparison of
12614 the underlying value. */
12621 {
12625 }
12627 /* If this AND operation is really a ZERO_EXTEND from a narrower
12628 mode, the constant fits within that mode, and this is either an
12629 equality or unsigned comparison, try to do this comparison in
12630 the narrower mode.
12632 Note that in:
12634 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12635 -> (ne:DI (reg:SI 4) (const_int 0))
12637 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12638 known to hold a value of the required mode the
12639 transformation is invalid. */
12647 {
12650 }
12652 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12653 fits in both M1 and M2 and the SUBREG is either paradoxical
12654 or represents the low part, permute the SUBREG and the AND
12655 and try again. */
12658 {
12660 /* Require an integral mode, to avoid creating something like
12661 (AND:SF ...). */
12664 /* It is unsafe to commute the AND into the SUBREG if the
12665 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12666 not defined. As originally written the upper bits
12667 have a defined value due to the AND operation.
12668 However, if we commute the AND inside the SUBREG then
12669 they no longer have defined values and the meaning of
12670 the code has been changed.
12671 Also C1 should not change value in the smaller mode,
12672 see PR67028 (a positive C1 can become negative in the
12673 smaller mode, so that the AND does no longer mask the
12674 upper bits). */
12675 && ((WORD_REGISTER_OPERATIONS
12687 {
12693 }
12694 }
12696 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12700 {
12705 }
12707 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12708 (eq (and (lshiftrt X) 1) 0).
12709 Also handle the case where (not X) is expressed using xor. */
12713 {
12723 == HOST_WIDE_INT_1U
12725 {
12726 op0
12731 }
12732 }
12736 /* If we have (compare (ashift FOO N) (const_int C)) and
12737 the high order N bits of FOO (N+1 if an inequality comparison)
12738 are known to be zero, we can do this by comparing FOO with C
12739 shifted right N bits so long as the low-order N bits of C are
12740 zero. */
12752 {
12753 /* We must perform a logical shift, not an arithmetic one,
12754 as we want the top N bits of C to be zero. */
12761 }
12763 /* If we are doing a sign bit comparison, it means we are testing
12764 a particular bit. Convert it to the appropriate AND. */
12767 {
12769 (HOST_WIDE_INT_1U
12774 }
12776 /* If this an equality comparison with zero and we are shifting
12777 the low bit to the sign bit, we can convert this to an AND of the
12778 low-order bit. */
12782 {
12785 }
12789 /* If this is an equality comparison with zero, we can do this
12790 as a logical shift, which might be much simpler. */
12793 {
12798 }
12800 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12801 do the comparison in a narrower mode. */
12811 {
12814 }
12816 /* Likewise if OP0 is a PLUS of a sign extension with a
12817 constant, which is usually represented with the PLUS
12818 between the shifts. */
12830 {
12838 new_const);
12840 }
12842 /* FALLTHROUGH */
12844 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12845 the low order N bits of FOO are known to be zero, we can do this
12846 by comparing FOO with C shifted left N bits so long as no
12847 overflow occurs. Even if the low order N bits of FOO aren't known
12848 to be zero, if the comparison is >= or < we can use the same
12849 optimization and for > or <= by setting all the low
12850 order N bits in the comparison constant. */
12861 {
12862 unsigned HOST_WIDE_INT low_bits
12864 & ((HOST_WIDE_INT_1U
12867 {
12868 /* If the shift was logical, then we must make the condition
12869 unsigned. */
12878 const_op
12883 }
12884 }
12886 /* If we are using this shift to extract just the sign bit, we
12887 can replace this with an LT or GE comparison. */
12892 {
12896 }
12901 }
12904 }
12906 /* Now make any compound operations involved in this comparison. Then,
12907 check for an outmost SUBREG on OP0 that is not doing anything or is
12908 paradoxical. The latter transformation must only be performed when
12909 it is known that the "extra" bits will be the same in op0 and op1 or
12910 that they don't matter. There are three cases to consider:
12912 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12913 care bits and we can assume they have any convenient value. So
12914 making the transformation is safe.
12916 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12917 In this case the upper bits of op0 are undefined. We should not make
12918 the simplification in that case as we do not know the contents of
12919 those bits.
12921 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12922 In that case we know those bits are zeros or ones. We must also be
12923 sure that they are the same as the upper bits of op1.
12925 We can never remove a SUBREG for a non-equality comparison because
12926 the sign bit is in a different place in the underlying object. */
12939 {
12941 {
12942 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12943 implemented. */
12945 {
12948 }
12949 }
12953 {
12958 }
12959 }
12961 /* We now do the opposite procedure: Some machines don't have compare
12962 insns in all modes. If OP0's mode is an integer mode smaller than a
12963 word and we can't do a compare in that mode, see if there is a larger
12964 mode for which we can do the compare. There are a number of cases in
12965 which we can use the wider mode. */
12971 {
12976 {
12979 /* If this is a test for negative, we can make an explicit
12980 test of the sign bit. Test this first so we can use
12981 a paradoxical subreg to extend OP0. */
12985 {
12986 unsigned HOST_WIDE_INT sign
12993 }
12995 /* If the only nonzero bits in OP0 and OP1 are those in the
12996 narrower mode and this is an equality or unsigned comparison,
12997 we can use the wider mode. Similarly for sign-extended
12998 values, in which case it is true for all comparisons. */
13015 {
13016 /* If OP0 is an AND and we don't have an AND in MODE either,
13017 make a new AND in the proper mode. */
13025 else
13026 {
13028 {
13033 }
13034 else
13035 {
13040 }
13042 }
13043 }
13044 }
13045 }
13047 /* We may have changed the comparison operands. Re-canonicalize. */
13049 {
13052 }
13054 /* If this machine only supports a subset of valid comparisons, see if we
13055 can convert an unsupported one into a supported one. */
13062 }
13063 \f
13064 /* Utility function for record_value_for_reg. Count number of
13065 rtxs in X. */
13066 static int
13068 {
13075 {
13095 }
13106 }
13107 \f
13108 /* Utility function for following routine. Called when X is part of a value
13109 being stored into last_set_value. Sets last_set_table_tick
13110 for each register mentioned. Similar to mention_regs in cse.cc */
13112 static void
13114 {
13120 {
13126 {
13129 }
13132 }
13136 {
13137 /* Check for identical subexpressions. If x contains
13138 identical subexpression we only have to traverse one of
13139 them. */
13141 {
13142 /* Note that at this point x1 has already been
13143 processed. */
13147 /* If x0 and x1 are identical then there is no need to
13148 process x0. */
13152 /* If x0 is identical to a subexpression of x1 then while
13153 processing x1, x0 has already been processed. Thus we
13154 are done with x. */
13159 /* If x1 is identical to a subexpression of x0 then we
13160 still have to process the rest of x0. */
13163 {
13166 }
13167 }
13170 }
13174 }
13176 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13177 are saying that the register is clobbered and we no longer know its
13178 value. If INSN is zero, don't update reg_stat[].last_set; this is
13179 only permitted with VALUE also zero and is used to invalidate the
13180 register. */
13182 static void
13184 {
13190 /* If VALUE contains REG and we have a previous value for REG, substitute
13191 the previous value. */
13193 {
13194 rtx tem;
13196 /* Set things up so get_last_value is allowed to see anything set up to
13197 our insn. */
13201 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13202 it isn't going to be useful and will take a lot of time to process,
13203 so just use the CLOBBER. */
13206 {
13212 {
13213 /* If there are two or more occurrences of REG in VALUE,
13214 prevent the value from growing too much. */
13217 }
13220 }
13221 }
13223 /* For each register modified, show we don't know its value, that
13224 we don't know about its bitwise content, that its value has been
13225 updated, and that we don't know the location of the death of the
13226 register. */
13228 {
13240 }
13242 /* Mark registers that are being referenced in this value. */
13246 /* Now update the status of each register being set.
13247 If someone is using this register in this block, set this register
13248 to invalid since we will get confused between the two lives in this
13249 basic block. This makes using this register always invalid. In cse, we
13250 scan the table to invalidate all entries using this register, but this
13251 is too much work for us. */
13254 {
13260 else
13262 }
13264 /* The value being assigned might refer to X (like in "x++;"). In that
13265 case, we must replace it with (clobber (const_int 0)) to prevent
13266 infinite loops. */
13269 {
13273 }
13275 /* For the main register being modified, update the value, the mode, the
13276 nonzero bits, and the number of sign bit copies. */
13281 {
13289 rsp->last_set_sign_bit_copies
13291 }
13292 }
13294 /* Called via note_stores from record_dead_and_set_regs to handle one
13295 SET or CLOBBER in an insn. DATA is the instruction in which the
13296 set is occurring. */
13298 static void
13300 {
13307 {
13311 }
13314 {
13315 /* If we are setting the whole register, we know its value. Otherwise
13316 show that we don't know the value. We can handle a SUBREG if it's
13317 the low part, but we must be careful with paradoxical SUBREGs on
13318 RISC architectures because we cannot strip e.g. an extension around
13319 a load and record the naked load since the RTL middle-end considers
13320 that the upper bits are defined according to LOAD_EXTEND_OP. */
13327 BITS_PER_WORD)
13330 WORD_REGISTER_OPERATIONS
13336 else
13338 }
13340 /* Ignore pushes, they clobber nothing. */
13343 }
13345 /* Update the records of when each REG was most recently set or killed
13346 for the things done by INSN. This is the last thing done in processing
13347 INSN in the combiner loop.
13349 We update reg_stat[], in particular fields last_set, last_set_value,
13350 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13351 last_death, and also the similar information mem_last_set (which insn
13352 most recently modified memory) and last_call_luid (which insn was the
13353 most recent subroutine call). */
13355 static void
13357 {
13358 rtx link;
13362 {
13365 {
13370 {
13375 }
13376 }
13379 }
13382 {
13383 HARD_REG_SET callee_clobbers
13385 hard_reg_set_iterator hrsi;
13387 {
13390 /* ??? We could try to preserve some information from the last
13391 set of register I if the call doesn't actually clobber
13392 (reg:last_set_mode I), which might be true for ABIs with
13393 partial clobbers. However, it would be difficult to
13394 update last_set_nonzero_bits and last_sign_bit_copies
13395 to account for the part of I that actually was clobbered.
13396 It wouldn't help much anyway, since we rarely see this
13397 situation before RA. */
13407 }
13411 /* We can't combine into a call pattern. Remember, though, that
13412 the return value register is set at this LUID. We could
13413 still replace a register with the return value from the
13414 wrong subroutine call! */
13416 }
13417 else
13419 }
13421 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13422 register present in the SUBREG, so for each such SUBREG go back and
13423 adjust nonzero and sign bit information of the registers that are
13424 known to have some zero/sign bits set.
13426 This is needed because when combine blows the SUBREGs away, the
13427 information on zero/sign bits is lost and further combines can be
13428 missed because of that. */
13430 static void
13432 {
13434 rtx set;
13442 {
13451 {
13454 }
13458 {
13461 }
13464 {
13467 }
13468 else
13470 }
13471 }
13473 /* Check if X, a register, is known to contain a value already
13474 truncated to MODE. In this case we can use a subreg to refer to
13475 the truncated value even though in the generic case we would need
13476 an explicit truncation. */
13478 static bool
13480 {
13492 }
13494 /* If X is a hard reg or a subreg record the mode that the register is
13495 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13496 able to turn a truncate into a subreg using this information. Return true
13497 if traversing X is complete. */
13499 static bool
13501 {
13502 machine_mode truncated_mode;
13506 {
13518 }
13519 /* ??? For hard-regs we now record everything. We might be able to
13520 optimize this using last_set_mode. */
13523 else
13530 {
13533 }
13536 }
13538 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13539 the modes they are used in. This can help truning TRUNCATEs into
13540 SUBREGs. */
13542 static void
13544 {
13549 }
13551 /* Scan X for promoted SUBREGs. For each one found,
13552 note what it implies to the registers used in it. */
13554 static void
13556 {
13561 else
13562 {
13568 {
13578 }
13579 }
13580 }
13581 \f
13582 /* Verify that all the registers and memory references mentioned in *LOC are
13583 still valid. *LOC was part of a value set in INSN when label_tick was
13584 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13585 the invalid references with (clobber (const_int 0)) and return 1. This
13586 replacement is useful because we often can get useful information about
13587 the form of a value (e.g., if it was produced by a shift that always
13588 produces -1 or 0) even though we don't know exactly what registers it
13589 was produced from. */
13591 static int
13593 {
13600 {
13606 {
13609 /* If this is a pseudo-register that was only set once and not
13610 live at the beginning of the function, it is always valid. */
13614 && (!REGNO_REG_SET_P
13616 regno)))
13618 {
13622 }
13623 }
13626 }
13627 /* If this is a memory reference, make sure that there were no stores after
13628 it that might have clobbered the value. We don't have alias info, so we
13629 assume any store invalidates it. Moreover, we only have local UIDs, so
13630 we also assume that there were stores in the intervening basic blocks. */
13633 {
13637 }
13640 {
13642 {
13643 /* Check for identical subexpressions. If x contains
13644 identical subexpression we only have to traverse one of
13645 them. */
13647 {
13648 /* Note that at this point x0 has already been checked
13649 and found valid. */
13653 /* If x0 and x1 are identical then x is also valid. */
13657 /* If x1 is identical to a subexpression of x0 then
13658 while checking x0, x1 has already been checked. Thus
13659 it is valid and so as x. */
13664 /* If x0 is identical to a subexpression of x1 then x is
13665 valid iff the rest of x1 is valid. */
13668 return
13672 }
13677 }
13683 }
13685 /* If we haven't found a reason for it to be invalid, it is valid. */
13687 }
13689 /* Get the last value assigned to X, if known. Some registers
13690 in the value may be replaced with (clobber (const_int 0)) if their value
13691 is known longer known reliably. */
13693 static rtx
13695 {
13697 rtx value;
13700 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13701 then convert it to the desired mode. If this is a paradoxical SUBREG,
13702 we cannot predict what values the "extra" bits might have. */
13716 /* If we don't have a value, or if it isn't for this basic block and
13717 it's either a hard register, set more than once, or it's a live
13718 at the beginning of the function, return 0.
13720 Because if it's not live at the beginning of the function then the reg
13721 is always set before being used (is never used without being set).
13722 And, if it's set only once, and it's always set before use, then all
13723 uses must have the same last value, even if it's not from this basic
13724 block. */
13731 || REGNO_REG_SET_P
13735 /* If the value was set in a later insn than the ones we are processing,
13736 we can't use it even if the register was only set once. */
13741 /* If fewer bits were set than what we are asked for now, we cannot use
13742 the value. */
13747 /* If the value has all its registers valid, return it. */
13751 /* Otherwise, make a copy and replace any invalid register with
13752 (clobber (const_int 0)). If that fails for some reason, return 0. */
13759 }
13760 \f
13761 /* Define three variables used for communication between the following
13762 routines. */
13766 rtx reg_dead_reg;
13768 /* Function called via note_stores from reg_dead_at_p.
13770 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13771 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13773 static void
13775 {
13785 }
13787 /* Return nonzero if REG is known to be dead at INSN.
13789 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13790 referencing REG, it is dead. If we hit a SET referencing REG, it is
13791 live. Otherwise, see if it is live or dead at the start of the basic
13792 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13793 must be assumed to be always live. */
13795 static int
13797 {
13798 basic_block block;
13801 /* Set variables for reg_dead_at_p_1. */
13808 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13809 we allow the machine description to decide whether use-and-clobber
13810 patterns are OK. */
13812 {
13816 }
13818 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13819 beginning of basic block. */
13822 {
13824 {
13834 }
13840 }
13842 /* Look at live-in sets for the basic block that we were in. */
13848 }
13849 \f
13850 /* Note hard registers in X that are used. */
13852 static void
13854 {
13860 {
13864 CASE_CONST_ANY:
13872 /* If we are clobbering a MEM, mark any hard registers inside the
13873 address as used. */
13880 /* A hard reg in a wide mode may really be multiple registers.
13881 If so, mark all of them just like the first. */
13883 {
13884 /* None of this applies to the stack, frame or arg pointers. */
13886 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13894 }
13898 {
13899 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13900 the address. */
13912 }
13917 }
13919 /* Recursively scan the operands of this expression. */
13921 {
13925 {
13929 {
13934 }
13935 }
13936 }
13937 }
13938 \f
13939 /* Remove register number REGNO from the dead registers list of INSN.
13941 Return the note used to record the death, if there was one. */
13943 rtx
13945 {
13952 }
13954 /* For each register (hardware or pseudo) used within expression X, if its
13955 death is in an instruction with luid between FROM_LUID (inclusive) and
13956 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13957 list headed by PNOTES.
13959 That said, don't move registers killed by maybe_kill_insn.
13961 This is done when X is being merged by combination into TO_INSN. These
13962 notes will then be distributed as needed. */
13964 static void
13967 {
13973 {
13977 /* If we do not know where the register died, it may still die between
13978 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
13980 {
13985 {
13987 {
13991 }
13994 }
13995 }
13997 /* Don't move the register if it gets killed in between from and to. */
14006 {
14009 /* It is possible for the call above to return 0. This can occur
14010 when last_death points to I2 or I1 that we combined with.
14011 In that case make a new note.
14013 We must also check for the case where X is a hard register
14014 and NOTE is a death note for a range of hard registers
14015 including X. In that case, we must put REG_DEAD notes for
14016 the remaining registers in place of NOTE. */
14020 {
14029 }
14031 /* If we didn't find any note, or if we found a REG_DEAD note that
14032 covers only part of the given reg, and we have a multi-reg hard
14033 register, then to be safe we must check for REG_DEAD notes
14034 for each register other than the first. They could have
14035 their own REG_DEAD notes lying around. */
14042 {
14049 else
14055 }
14058 {
14061 }
14062 else
14064 }
14067 }
14070 {
14075 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14076 that accesses one word of a multi-word item, some
14077 piece of everything register in the expression is used by
14078 this insn, so remove any old death. */
14079 /* ??? So why do we test for equality of the sizes? */
14085 {
14088 }
14090 /* If this is some other SUBREG, we know it replaces the entire
14091 value, so use that as the destination. */
14095 /* If this is a MEM, adjust deaths of anything used in the address.
14096 For a REG (the only other possibility), the entire value is
14097 being replaced so the old value is not used in this insn. */
14103 }
14112 {
14114 {
14119 }
14122 }
14123 }
14124 \f
14125 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14126 pattern of an insn. X must be a REG. */
14128 static int
14130 {
14134 {
14136 rtx target;
14143 else
14160 }
14168 }
14169 \f
14170 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14171 as appropriate. I3 and I2 are the insns resulting from the combination
14172 insns including FROM (I2 may be zero).
14174 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14175 not need REG_DEAD notes because they are being substituted for. This
14176 saves searching in the most common cases.
14178 Each note in the list is either ignored or placed on some insns, depending
14179 on the type of note. */
14181 static void
14184 {
14186 rtx tem_note;
14190 {
14195 {
14198 /* Doesn't matter much where we put this, as long as it's somewhere.
14199 It is preferable to keep these notes on branches, which is most
14200 likely to be i3. */
14207 else
14208 {
14211 }
14215 {
14216 /* The landing pad handling needs to be kept in sync with the
14217 prerequisite checking in try_combine. */
14219 /* A REG_EH_REGION note transfering control can only ever come
14220 from i3. */
14223 /* We are making sure there is a single effective REG_EH_REGION
14224 note and it's valid to put it on i3. */
14227 /* Throw away stray notes on insns that can never throw or
14228 make a nonlocal goto. */
14229 ;
14230 else
14231 {
14234 else
14235 {
14237 /* If i3 can still trap preserve the note, otherwise we've
14238 combined things such that we can now prove that the
14239 instructions can't trap. Drop the note in this case. */
14242 }
14243 }
14245 }
14248 /* ??? How to distribute between i3-i1. Assume i3 contains the
14249 entire adjustment. Assert i3 contains at least some adjust. */
14251 {
14253 /* fixup_args_size_notes looks at REG_NORETURN note,
14254 so ensure the note is placed there first. */
14256 {
14260 {
14266 }
14267 }
14269 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14270 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14273 && !ACCUMULATE_OUTGOING_ARGS
14275 }
14284 /* These notes must remain with the call. It should not be
14285 possible for both I2 and I3 to be a call. */
14288 else
14289 {
14292 }
14296 /* Any clobbers for i3 may still exist, and so we must process
14297 REG_UNUSED notes from that insn.
14299 Any clobbers from i2 or i1 can only exist if they were added by
14300 recog_for_combine. In that case, recog_for_combine created the
14301 necessary REG_UNUSED notes. Trying to keep any original
14302 REG_UNUSED notes from these insns can cause incorrect output
14303 if it is for the same register as the original i3 dest.
14304 In that case, we will notice that the register is set in i3,
14305 and then add a REG_UNUSED note for the destination of i3, which
14306 is wrong. However, it is possible to have REG_UNUSED notes from
14307 i2 or i1 for register which were both used and clobbered, so
14308 we keep notes from i2 or i1 if they will turn into REG_DEAD
14309 notes. */
14311 /* If this register is set or clobbered between FROM_INSN and I3,
14312 we should not create a note for it. */
14316 /* If this register is set or clobbered in I3, put the note there
14317 unless there is one already. */
14319 {
14327 }
14328 /* Otherwise, if this register is used by I3, then this register
14329 now dies here, so we must put a REG_DEAD note here unless there
14330 is one already. */
14336 {
14339 }
14341 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14342 but we can't tell which at this point. We must reset any
14343 expectations we had about the value that was previously
14344 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14345 and, if appropriate, restore its previous value, but we
14346 don't have enough information for that at this point. */
14347 else
14348 {
14351 /* Otherwise, if this register is now referenced in i2
14352 then the register used to be modified in one of the
14353 original insns. If it was i3 (say, in an unused
14354 parallel), it's now completely gone, so the note can
14355 be discarded. But if it was modified in i2, i1 or i0
14356 and we still reference it in i2, then we're
14357 referencing the previous value, and since the
14358 register was modified and REG_UNUSED, we know that
14359 the previous value is now dead. So, if we only
14360 reference the register in i2, we change the note to
14361 REG_DEAD, to reflect the previous value. However, if
14362 we're also setting or clobbering the register as
14363 scratch, we know (because the register was not
14364 referenced in i3) that it's unused, just as it was
14365 unused before, and we place the note in i2. */
14368 {
14377 }
14378 }
14385 /* These notes say something about results of an insn. We can
14386 only support them if they used to be on I3 in which case they
14387 remain on I3. Otherwise they are ignored.
14389 If the note refers to an expression that is not a constant, we
14390 must also ignore the note since we cannot tell whether the
14391 equivalence is still true. It might be possible to do
14392 slightly better than this (we only have a problem if I2DEST
14393 or I1DEST is present in the expression), but it doesn't
14394 seem worth the trouble. */
14402 /* These notes say something about how a register is used. They must
14403 be present on any use of the register in I2 or I3. */
14408 {
14411 else
14413 }
14418 /* This can show up in several ways -- either directly in the
14419 pattern, or hidden off in the constant pool with (or without?)
14420 a REG_EQUAL note. */
14421 /* ??? Ignore the without-reg_equal-note problem for now. */
14433 {
14436 else
14438 }
14440 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14441 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14442 there. */
14447 {
14454 }
14460 {
14468 }
14472 /* This note says something about the value of a register prior
14473 to the execution of an insn. It is too much trouble to see
14474 if the note is still correct in all situations. It is better
14475 to simply delete it. */
14479 /* If we replaced the right hand side of FROM_INSN with a
14480 REG_EQUAL note, the original use of the dying register
14481 will not have been combined into I3 and I2. In such cases,
14482 FROM_INSN is guaranteed to be the first of the combined
14483 instructions, so we simply need to search back before
14484 FROM_INSN for the previous use or set of this register,
14485 then alter the notes there appropriately.
14487 If the register is used as an input in I3, it dies there.
14488 Similarly for I2, if it is nonzero and adjacent to I3.
14490 If the register is not used as an input in either I3 or I2
14491 and it is not one of the registers we were supposed to eliminate,
14492 there are two possibilities. We might have a non-adjacent I2
14493 or we might have somehow eliminated an additional register
14494 from a computation. For example, we might have had A & B where
14495 we discover that B will always be zero. In this case we will
14496 eliminate the reference to A.
14498 In both cases, we must search to see if we can find a previous
14499 use of A and put the death note there. */
14505 else
14506 {
14512 {
14513 /* If the new I2 sets the same register that is marked
14514 dead in the note, we do not in general know where to
14515 put the note. One important case we _can_ handle is
14516 when the note comes from I3. */
14519 else
14521 }
14528 && !(i2mod
14530 i2mod_old_rhs)))
14535 }
14538 {
14542 {
14544 {
14548 }
14550 /* If the register is being set at TEM_INSN, see if that is all
14551 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14552 into a REG_UNUSED note instead. Don't delete sets to
14553 global register vars. */
14557 {
14567 ;
14569 /* Verify that it was the set, and not a clobber that
14570 modified the register.
14572 If we cannot delete the setter due to side
14573 effects, mark the user with an UNUSED note instead
14574 of deleting it. */
14578 {
14579 /* Move the notes and links of TEM_INSN elsewhere.
14580 This might delete other dead insns recursively.
14581 First set the pattern to something that won't use
14582 any register. */
14600 }
14601 else
14602 {
14605 /* If there isn't already a REG_UNUSED note, put one
14606 here. Do not place a REG_DEAD note, even if
14607 the register is also used here; that would not
14608 match the algorithm used in lifetime analysis
14609 and can cause the consistency check in the
14610 scheduler to fail. */
14615 }
14616 }
14620 {
14623 /* If we are doing a 3->2 combination, and we have a
14624 register which formerly died in i3 and was not used
14625 by i2, which now no longer dies in i3 and is used in
14626 i2 but does not die in i2, and place is between i2
14627 and i3, then we may need to move a link from place to
14628 i2. */
14630 && from_insn
14633 {
14637 }
14639 }
14643 }
14645 }
14647 /* If the register is set or already dead at PLACE, we needn't do
14648 anything with this note if it is still a REG_DEAD note.
14649 We check here if it is set at all, not if is it totally replaced,
14650 which is what `dead_or_set_p' checks, so also check for it being
14651 set partially. */
14654 {
14660 {
14661 /* Unless the register previously died in PLACE, clear
14662 last_death. [I no longer understand why this is
14663 being done.] */
14667 }
14668 else
14671 /* If this is a death note for a hard reg that is occupying
14672 multiple registers, ensure that we are still using all
14673 parts of the object. If we find a piece of the object
14674 that is unused, we must arrange for an appropriate REG_DEAD
14675 note to be added for it. However, we can't just emit a USE
14676 and tag the note to it, since the register might actually
14677 be dead; so we recourse, and the recursive call then finds
14678 the previous insn that used this register. */
14681 {
14690 {
14693 }
14696 {
14697 /* Put only REG_DEAD notes for pieces that are
14698 not already dead or set. */
14702 {
14709 {
14711 NULL_RTX);
14715 NULL_RTX);
14716 }
14721 {
14723 {
14727 }
14731 {
14734 }
14735 }
14736 }
14739 }
14740 }
14741 }
14745 /* Any other notes should not be present at this point in the
14746 compilation. */
14748 }
14751 {
14755 /* Set added_notes_insn to the earliest insn we added a note to. */
14759 }
14762 {
14765 /* Set added_notes_insn to the earliest insn we added a note to. */
14769 }
14770 }
14771 }
14772 \f
14773 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14774 I3, I2, and I1 to new locations. This is also called to add a link
14775 pointing at I3 when I3's destination is changed. */
14777 static void
14779 {
14783 {
14790 /* If the insn that this link points to is a NOTE, ignore it. */
14799 {
14802 {
14818 }
14821 }
14822 else
14835 /* A LOG_LINK is defined as being placed on the first insn that uses
14836 a register and points to the insn that sets the register. Start
14837 searching at the next insn after the target of the link and stop
14838 when we reach a set of the register or the end of the basic block.
14840 Note that this correctly handles the link that used to point from
14841 I3 to I2. Also note that not much searching is typically done here
14842 since most links don't point very far away. */
14851 {
14855 }
14858 {
14861 }
14865 /* If we found a place to put the link, place it there unless there
14866 is already a link to the same insn as LINK at that point. */
14869 {
14877 {
14881 /* Set added_links_insn to the earliest insn we added a
14882 link to. */
14886 }
14887 }
14888 }
14889 }
14890 \f
14891 /* Check for any register or memory mentioned in EQUIV that is not
14892 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14893 of EXPR where some registers may have been replaced by constants. */
14895 static bool
14897 {
14900 {
14905 }
14907 }
14908 \f
14909 DEBUG_FUNCTION void
14911 {
14912 fprintf
14914 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14916 }
14918 void
14920 {
14921 fprintf
14923 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14925 }
14926 \f
14927 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
14928 the reg-to-reg copy can usefully combine with later instructions, but we
14929 do not want to combine the hard reg into later instructions, for that
14930 restricts register allocation. */
14931 static void
14933 {
14934 basic_block bb;
14937 {
14941 {
14964 }
14965 }
14966 }
14968 /* Try combining insns through substitution. */
14969 static unsigned int
14971 {
14981 int rebuild_jump_labels_after_combine
14984 /* Combining insns may have turned an indirect jump into a
14985 direct jump. Rebuild the JUMP_LABEL fields of jumping
14986 instructions. */
14988 {
14995 }
14999 }
15004 {
15014 };
15017 {
15021 {}
15023 /* opt_pass methods: */
15026 {
15028 }
15034 rtl_opt_pass *
15036 {
15038 }