1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2023 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 We check (with modified_between_p) to avoid combining in such a way
37 as to move a computation to a place where its value would be different.
39 Combination is done by mathematically substituting the previous
40 insn(s) values for the regs they set into the expressions in
41 the later insns that refer to these regs. If the result is a valid insn
42 for our target machine, according to the machine description,
43 we install it, delete the earlier insns, and update the data flow
44 information (LOG_LINKS and REG_NOTES) for what we did.
46 There are a few exceptions where the dataflow information isn't
47 completely updated (however this is only a local issue since it is
48 regenerated before the next pass that uses it):
50 - reg_live_length is not updated
51 - reg_n_refs is not adjusted in the rare case when a register is
52 no longer required in a computation
53 - there are extremely rare cases (see distribute_notes) when a
55 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
56 removed because there is no way to know which register it was
59 To simplify substitution, we combine only when the earlier insn(s)
60 consist of only a single assignment. To simplify updating afterward,
61 we never combine when a subroutine call appears in the middle. */
65 #include "coretypes.h"
80 #include "stor-layout.h"
82 #include "cfgcleanup.h"
83 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
85 #include "insn-attr.h"
86 #include "rtlhooks-def.h"
88 #include "tree-pass.h"
91 #include "print-rtl.h"
92 #include "function-abi.h"
95 /* Number of attempts to combine instructions in this function. */
97 static int combine_attempts
;
99 /* Number of attempts that got as far as substitution in this function. */
101 static int combine_merges
;
103 /* Number of instructions combined with added SETs in this function. */
105 static int combine_extras
;
107 /* Number of instructions combined in this function. */
109 static int combine_successes
;
111 /* Totals over entire compilation. */
113 static int total_attempts
, total_merges
, total_extras
, total_successes
;
115 /* combine_instructions may try to replace the right hand side of the
116 second instruction with the value of an associated REG_EQUAL note
117 before throwing it at try_combine. That is problematic when there
118 is a REG_DEAD note for a register used in the old right hand side
119 and can cause distribute_notes to do wrong things. This is the
120 second instruction if it has been so modified, null otherwise. */
122 static rtx_insn
*i2mod
;
124 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
126 static rtx i2mod_old_rhs
;
128 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
130 static rtx i2mod_new_rhs
;
132 struct reg_stat_type
{
133 /* Record last point of death of (hard or pseudo) register n. */
134 rtx_insn
*last_death
;
136 /* Record last point of modification of (hard or pseudo) register n. */
139 /* The next group of fields allows the recording of the last value assigned
140 to (hard or pseudo) register n. We use this information to see if an
141 operation being processed is redundant given a prior operation performed
142 on the register. For example, an `and' with a constant is redundant if
143 all the zero bits are already known to be turned off.
145 We use an approach similar to that used by cse, but change it in the
148 (1) We do not want to reinitialize at each label.
149 (2) It is useful, but not critical, to know the actual value assigned
150 to a register. Often just its form is helpful.
152 Therefore, we maintain the following fields:
154 last_set_value the last value assigned
155 last_set_label records the value of label_tick when the
156 register was assigned
157 last_set_table_tick records the value of label_tick when a
158 value using the register is assigned
159 last_set_invalid set to nonzero when it is not valid
160 to use the value of this register in some
163 To understand the usage of these tables, it is important to understand
164 the distinction between the value in last_set_value being valid and
165 the register being validly contained in some other expression in the
168 (The next two parameters are out of date).
170 reg_stat[i].last_set_value is valid if it is nonzero, and either
171 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
173 Register I may validly appear in any expression returned for the value
174 of another register if reg_n_sets[i] is 1. It may also appear in the
175 value for register J if reg_stat[j].last_set_invalid is zero, or
176 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
178 If an expression is found in the table containing a register which may
179 not validly appear in an expression, the register is replaced by
180 something that won't match, (clobber (const_int 0)). */
182 /* Record last value assigned to (hard or pseudo) register n. */
186 /* Record the value of label_tick when an expression involving register n
187 is placed in last_set_value. */
189 int last_set_table_tick
;
191 /* Record the value of label_tick when the value for register n is placed in
196 /* These fields are maintained in parallel with last_set_value and are
197 used to store the mode in which the register was last set, the bits
198 that were known to be zero when it was last set, and the number of
199 sign bits copies it was known to have when it was last set. */
201 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
202 char last_set_sign_bit_copies
;
203 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
205 /* Set nonzero if references to register n in expressions should not be
206 used. last_set_invalid is set nonzero when this register is being
207 assigned to and last_set_table_tick == label_tick. */
209 char last_set_invalid
;
211 /* Some registers that are set more than once and used in more than one
212 basic block are nevertheless always set in similar ways. For example,
213 a QImode register may be loaded from memory in two places on a machine
214 where byte loads zero extend.
216 We record in the following fields if a register has some leading bits
217 that are always equal to the sign bit, and what we know about the
218 nonzero bits of a register, specifically which bits are known to be
221 If an entry is zero, it means that we don't know anything special. */
223 unsigned char sign_bit_copies
;
225 unsigned HOST_WIDE_INT nonzero_bits
;
227 /* Record the value of the label_tick when the last truncation
228 happened. The field truncated_to_mode is only valid if
229 truncation_label == label_tick. */
231 int truncation_label
;
233 /* Record the last truncation seen for this register. If truncation
234 is not a nop to this mode we might be able to save an explicit
235 truncation if we know that value already contains a truncated
238 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
242 static vec
<reg_stat_type
> reg_stat
;
244 /* One plus the highest pseudo for which we track REG_N_SETS.
245 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
246 but during combine_split_insns new pseudos can be created. As we don't have
247 updated DF information in that case, it is hard to initialize the array
248 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
249 so instead of growing the arrays, just assume all newly created pseudos
250 during combine might be set multiple times. */
252 static unsigned int reg_n_sets_max
;
254 /* Record the luid of the last insn that invalidated memory
255 (anything that writes memory, and subroutine calls, but not pushes). */
257 static int mem_last_set
;
259 /* Record the luid of the last CALL_INSN
260 so we can tell whether a potential combination crosses any calls. */
262 static int last_call_luid
;
264 /* When `subst' is called, this is the insn that is being modified
265 (by combining in a previous insn). The PATTERN of this insn
266 is still the old pattern partially modified and it should not be
267 looked at, but this may be used to examine the successors of the insn
268 to judge whether a simplification is valid. */
270 static rtx_insn
*subst_insn
;
272 /* This is the lowest LUID that `subst' is currently dealing with.
273 get_last_value will not return a value if the register was set at or
274 after this LUID. If not for this mechanism, we could get confused if
275 I2 or I1 in try_combine were an insn that used the old value of a register
276 to obtain a new value. In that case, we might erroneously get the
277 new value of the register when we wanted the old one. */
279 static int subst_low_luid
;
281 /* This contains any hard registers that are used in newpat; reg_dead_at_p
282 must consider all these registers to be always live. */
284 static HARD_REG_SET newpat_used_regs
;
286 /* This is an insn to which a LOG_LINKS entry has been added. If this
287 insn is the earlier than I2 or I3, combine should rescan starting at
290 static rtx_insn
*added_links_insn
;
292 /* And similarly, for notes. */
294 static rtx_insn
*added_notes_insn
;
296 /* Basic block in which we are performing combines. */
297 static basic_block this_basic_block
;
298 static bool optimize_this_for_speed_p
;
301 /* Length of the currently allocated uid_insn_cost array. */
303 static int max_uid_known
;
305 /* The following array records the insn_cost for every insn
306 in the instruction stream. */
308 static int *uid_insn_cost
;
310 /* The following array records the LOG_LINKS for every insn in the
311 instruction stream as struct insn_link pointers. */
316 struct insn_link
*next
;
319 static struct insn_link
**uid_log_links
;
322 insn_uid_check (const_rtx insn
)
324 int uid
= INSN_UID (insn
);
325 gcc_checking_assert (uid
<= max_uid_known
);
329 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
330 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
332 #define FOR_EACH_LOG_LINK(L, INSN) \
333 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
335 /* Links for LOG_LINKS are allocated from this obstack. */
337 static struct obstack insn_link_obstack
;
339 /* Allocate a link. */
341 static inline struct insn_link
*
342 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
345 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
346 sizeof (struct insn_link
));
353 /* Incremented for each basic block. */
355 static int label_tick
;
357 /* Reset to label_tick for each extended basic block in scanning order. */
359 static int label_tick_ebb_start
;
361 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
362 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
364 static scalar_int_mode nonzero_bits_mode
;
366 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
367 be safely used. It is zero while computing them and after combine has
368 completed. This former test prevents propagating values based on
369 previously set values, which can be incorrect if a variable is modified
372 static int nonzero_sign_valid
;
375 /* Record one modification to rtl structure
376 to be undone by storing old_contents into *where. */
378 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
384 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
385 union { rtx
*r
; int *i
; int regno
; struct insn_link
**l
; } where
;
388 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
389 num_undo says how many are currently recorded.
391 other_insn is nonzero if we have modified some other insn in the process
392 of working on subst_insn. It must be verified too. */
398 rtx_insn
*other_insn
;
401 static struct undobuf undobuf
;
403 /* Number of times the pseudo being substituted for
404 was found and replaced. */
406 static int n_occurrences
;
408 static rtx
reg_nonzero_bits_for_combine (const_rtx
, scalar_int_mode
,
410 unsigned HOST_WIDE_INT
*);
411 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, scalar_int_mode
,
414 static void do_SUBST (rtx
*, rtx
);
415 static void do_SUBST_INT (int *, int);
416 static void init_reg_last (void);
417 static void setup_incoming_promotions (rtx_insn
*);
418 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
419 static int cant_combine_insn_p (rtx_insn
*);
420 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
421 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
422 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
423 static int contains_muldiv (rtx
);
424 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
426 static void undo_all (void);
427 static void undo_commit (void);
428 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
429 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
430 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
431 static rtx
simplify_if_then_else (rtx
);
432 static rtx
simplify_set (rtx
);
433 static rtx
simplify_logical (rtx
);
434 static rtx
expand_compound_operation (rtx
);
435 static const_rtx
expand_field_assignment (const_rtx
);
436 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
437 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
438 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
439 unsigned HOST_WIDE_INT
*);
440 static rtx
canon_reg_for_combine (rtx
, rtx
);
441 static rtx
force_int_to_mode (rtx
, scalar_int_mode
, scalar_int_mode
,
442 scalar_int_mode
, unsigned HOST_WIDE_INT
, int);
443 static rtx
force_to_mode (rtx
, machine_mode
,
444 unsigned HOST_WIDE_INT
, int);
445 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
446 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
447 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
448 static rtx
make_field_assignment (rtx
);
449 static rtx
apply_distributive_law (rtx
);
450 static rtx
distribute_and_simplify_rtx (rtx
, int);
451 static rtx
simplify_and_const_int_1 (scalar_int_mode
, rtx
,
452 unsigned HOST_WIDE_INT
);
453 static rtx
simplify_and_const_int (rtx
, scalar_int_mode
, rtx
,
454 unsigned HOST_WIDE_INT
);
455 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
456 HOST_WIDE_INT
, machine_mode
, int *);
457 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
458 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
460 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
461 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
462 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
464 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
465 static void update_table_tick (rtx
);
466 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
467 static void check_promoted_subreg (rtx_insn
*, rtx
);
468 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
469 static void record_dead_and_set_regs (rtx_insn
*);
470 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
471 static rtx
get_last_value (const_rtx
);
472 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
473 static int reg_dead_at_p (rtx
, rtx_insn
*);
474 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
475 static int reg_bitfield_target_p (rtx
, rtx
);
476 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
477 static void distribute_links (struct insn_link
*);
478 static void mark_used_regs_combine (rtx
);
479 static void record_promoted_value (rtx_insn
*, rtx
);
480 static bool unmentioned_reg_p (rtx
, rtx
);
481 static void record_truncated_values (rtx
*, void *);
482 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
483 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
486 /* It is not safe to use ordinary gen_lowpart in combine.
487 See comments in gen_lowpart_for_combine. */
488 #undef RTL_HOOKS_GEN_LOWPART
489 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
491 /* Our implementation of gen_lowpart never emits a new pseudo. */
492 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
493 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
495 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
496 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
498 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
499 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
501 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
502 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
504 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
507 /* Convenience wrapper for the canonicalize_comparison target hook.
508 Target hooks cannot use enum rtx_code. */
510 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
511 bool op0_preserve_value
)
513 int code_int
= (int)*code
;
514 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
515 *code
= (enum rtx_code
)code_int
;
518 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
519 PATTERN cannot be split. Otherwise, it returns an insn sequence.
520 This is a wrapper around split_insns which ensures that the
521 reg_stat vector is made larger if the splitter creates a new
525 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
530 ret
= split_insns (pattern
, insn
);
531 nregs
= max_reg_num ();
532 if (nregs
> reg_stat
.length ())
533 reg_stat
.safe_grow_cleared (nregs
, true);
537 /* This is used by find_single_use to locate an rtx in LOC that
538 contains exactly one use of DEST, which is typically a REG.
539 It returns a pointer to the innermost rtx expression
540 containing DEST. Appearances of DEST that are being used to
541 totally replace it are not counted. */
544 find_single_use_1 (rtx dest
, rtx
*loc
)
547 enum rtx_code code
= GET_CODE (x
);
563 /* If the destination is anything other than PC, a REG or a SUBREG
564 of a REG that occupies all of the REG, the insn uses DEST if
565 it is mentioned in the destination or the source. Otherwise, we
566 need just check the source. */
567 if (GET_CODE (SET_DEST (x
)) != PC
568 && !REG_P (SET_DEST (x
))
569 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
570 && REG_P (SUBREG_REG (SET_DEST (x
)))
571 && !read_modify_subreg_p (SET_DEST (x
))))
574 return find_single_use_1 (dest
, &SET_SRC (x
));
578 return find_single_use_1 (dest
, &XEXP (x
, 0));
584 /* If it wasn't one of the common cases above, check each expression and
585 vector of this code. Look for a unique usage of DEST. */
587 fmt
= GET_RTX_FORMAT (code
);
588 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
592 if (dest
== XEXP (x
, i
)
593 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
594 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
597 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
600 result
= this_result
;
601 else if (this_result
)
602 /* Duplicate usage. */
605 else if (fmt
[i
] == 'E')
609 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
611 if (XVECEXP (x
, i
, j
) == dest
613 && REG_P (XVECEXP (x
, i
, j
))
614 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
617 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
620 result
= this_result
;
621 else if (this_result
)
631 /* See if DEST, produced in INSN, is used only a single time in the
632 sequel. If so, return a pointer to the innermost rtx expression in which
635 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
637 Otherwise, we find the single use by finding an insn that has a
638 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
639 only referenced once in that insn, we know that it must be the first
640 and last insn referencing DEST. */
643 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
648 struct insn_link
*link
;
653 bb
= BLOCK_FOR_INSN (insn
);
654 for (next
= NEXT_INSN (insn
);
655 next
&& BLOCK_FOR_INSN (next
) == bb
;
656 next
= NEXT_INSN (next
))
657 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
659 FOR_EACH_LOG_LINK (link
, next
)
660 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
665 result
= find_single_use_1 (dest
, &PATTERN (next
));
675 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
676 insn. The substitution can be undone by undo_all. If INTO is already
677 set to NEWVAL, do not record this change. Because computing NEWVAL might
678 also call SUBST, we have to compute it before we put anything into
682 do_SUBST (rtx
*into
, rtx newval
)
687 if (oldval
== newval
)
690 /* We'd like to catch as many invalid transformations here as
691 possible. Unfortunately, there are way too many mode changes
692 that are perfectly valid, so we'd waste too much effort for
693 little gain doing the checks here. Focus on catching invalid
694 transformations involving integer constants. */
695 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
696 && CONST_INT_P (newval
))
698 /* Sanity check that we're replacing oldval with a CONST_INT
699 that is a valid sign-extension for the original mode. */
700 gcc_assert (INTVAL (newval
)
701 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
703 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
704 CONST_INT is not valid, because after the replacement, the
705 original mode would be gone. Unfortunately, we can't tell
706 when do_SUBST is called to replace the operand thereof, so we
707 perform this test on oldval instead, checking whether an
708 invalid replacement took place before we got here. */
709 gcc_assert (!(GET_CODE (oldval
) == SUBREG
710 && CONST_INT_P (SUBREG_REG (oldval
))));
711 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
712 && CONST_INT_P (XEXP (oldval
, 0))));
716 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
718 buf
= XNEW (struct undo
);
720 buf
->kind
= UNDO_RTX
;
722 buf
->old_contents
.r
= oldval
;
725 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
728 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
730 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
731 for the value of a HOST_WIDE_INT value (including CONST_INT) is
735 do_SUBST_INT (int *into
, int newval
)
740 if (oldval
== newval
)
744 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
746 buf
= XNEW (struct undo
);
748 buf
->kind
= UNDO_INT
;
750 buf
->old_contents
.i
= oldval
;
753 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
756 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
758 /* Similar to SUBST, but just substitute the mode. This is used when
759 changing the mode of a pseudo-register, so that any other
760 references to the entry in the regno_reg_rtx array will change as
764 subst_mode (int regno
, machine_mode newval
)
767 rtx reg
= regno_reg_rtx
[regno
];
768 machine_mode oldval
= GET_MODE (reg
);
770 if (oldval
== newval
)
774 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
776 buf
= XNEW (struct undo
);
778 buf
->kind
= UNDO_MODE
;
779 buf
->where
.regno
= regno
;
780 buf
->old_contents
.m
= oldval
;
781 adjust_reg_mode (reg
, newval
);
783 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
786 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
789 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
792 struct insn_link
* oldval
= *into
;
794 if (oldval
== newval
)
798 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
800 buf
= XNEW (struct undo
);
802 buf
->kind
= UNDO_LINKS
;
804 buf
->old_contents
.l
= oldval
;
807 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
810 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
812 /* Subroutine of try_combine. Determine whether the replacement patterns
813 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
814 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
815 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
816 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
817 of all the instructions can be estimated and the replacements are more
818 expensive than the original sequence. */
821 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
822 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
824 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
825 int new_i2_cost
, new_i3_cost
;
826 int old_cost
, new_cost
;
828 /* Lookup the original insn_costs. */
829 i2_cost
= INSN_COST (i2
);
830 i3_cost
= INSN_COST (i3
);
834 i1_cost
= INSN_COST (i1
);
837 i0_cost
= INSN_COST (i0
);
838 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
839 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
843 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
844 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
850 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
851 i1_cost
= i0_cost
= 0;
854 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
856 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
860 /* Calculate the replacement insn_costs. */
861 rtx tmp
= PATTERN (i3
);
862 PATTERN (i3
) = newpat
;
863 int tmpi
= INSN_CODE (i3
);
865 new_i3_cost
= insn_cost (i3
, optimize_this_for_speed_p
);
867 INSN_CODE (i3
) = tmpi
;
871 PATTERN (i2
) = newi2pat
;
872 tmpi
= INSN_CODE (i2
);
874 new_i2_cost
= insn_cost (i2
, optimize_this_for_speed_p
);
876 INSN_CODE (i2
) = tmpi
;
877 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
878 ? new_i2_cost
+ new_i3_cost
: 0;
882 new_cost
= new_i3_cost
;
886 if (undobuf
.other_insn
)
888 int old_other_cost
, new_other_cost
;
890 old_other_cost
= INSN_COST (undobuf
.other_insn
);
891 tmp
= PATTERN (undobuf
.other_insn
);
892 PATTERN (undobuf
.other_insn
) = newotherpat
;
893 tmpi
= INSN_CODE (undobuf
.other_insn
);
894 INSN_CODE (undobuf
.other_insn
) = -1;
895 new_other_cost
= insn_cost (undobuf
.other_insn
,
896 optimize_this_for_speed_p
);
897 PATTERN (undobuf
.other_insn
) = tmp
;
898 INSN_CODE (undobuf
.other_insn
) = tmpi
;
899 if (old_other_cost
> 0 && new_other_cost
> 0)
901 old_cost
+= old_other_cost
;
902 new_cost
+= new_other_cost
;
908 /* Disallow this combination if both new_cost and old_cost are greater than
909 zero, and new_cost is greater than old cost. */
910 int reject
= old_cost
> 0 && new_cost
> old_cost
;
914 fprintf (dump_file
, "%s combination of insns ",
915 reject
? "rejecting" : "allowing");
917 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
918 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
919 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
920 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
922 fprintf (dump_file
, "original costs ");
924 fprintf (dump_file
, "%d + ", i0_cost
);
925 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
926 fprintf (dump_file
, "%d + ", i1_cost
);
927 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
930 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
931 new_i2_cost
, new_i3_cost
, new_cost
);
933 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
939 /* Update the uid_insn_cost array with the replacement costs. */
940 INSN_COST (i2
) = new_i2_cost
;
941 INSN_COST (i3
) = new_i3_cost
;
953 /* Delete any insns that copy a register to itself.
954 Return true if the CFG was changed. */
957 delete_noop_moves (void)
959 rtx_insn
*insn
, *next
;
962 bool edges_deleted
= false;
964 FOR_EACH_BB_FN (bb
, cfun
)
966 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
968 next
= NEXT_INSN (insn
);
969 if (INSN_P (insn
) && noop_move_p (insn
))
972 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
974 edges_deleted
|= delete_insn_and_edges (insn
);
979 return edges_deleted
;
983 /* Return false if we do not want to (or cannot) combine DEF. */
985 can_combine_def_p (df_ref def
)
987 /* Do not consider if it is pre/post modification in MEM. */
988 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
991 unsigned int regno
= DF_REF_REGNO (def
);
993 /* Do not combine frame pointer adjustments. */
994 if ((regno
== FRAME_POINTER_REGNUM
995 && (!reload_completed
|| frame_pointer_needed
))
996 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
997 && regno
== HARD_FRAME_POINTER_REGNUM
998 && (!reload_completed
|| frame_pointer_needed
))
999 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1000 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1006 /* Return false if we do not want to (or cannot) combine USE. */
1008 can_combine_use_p (df_ref use
)
1010 /* Do not consider the usage of the stack pointer by function call. */
1011 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1017 /* Fill in log links field for all insns. */
1020 create_log_links (void)
1023 rtx_insn
**next_use
;
1027 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1029 /* Pass through each block from the end, recording the uses of each
1030 register and establishing log links when def is encountered.
1031 Note that we do not clear next_use array in order to save time,
1032 so we have to test whether the use is in the same basic block as def.
1034 There are a few cases below when we do not consider the definition or
1035 usage -- these are taken from original flow.c did. Don't ask me why it is
1036 done this way; I don't know and if it works, I don't want to know. */
1038 FOR_EACH_BB_FN (bb
, cfun
)
1040 FOR_BB_INSNS_REVERSE (bb
, insn
)
1042 if (!NONDEBUG_INSN_P (insn
))
1045 /* Log links are created only once. */
1046 gcc_assert (!LOG_LINKS (insn
));
1048 FOR_EACH_INSN_DEF (def
, insn
)
1050 unsigned int regno
= DF_REF_REGNO (def
);
1053 if (!next_use
[regno
])
1056 if (!can_combine_def_p (def
))
1059 use_insn
= next_use
[regno
];
1060 next_use
[regno
] = NULL
;
1062 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1067 We don't build a LOG_LINK for hard registers contained
1068 in ASM_OPERANDs. If these registers get replaced,
1069 we might wind up changing the semantics of the insn,
1070 even if reload can make what appear to be valid
1071 assignments later. */
1072 if (regno
< FIRST_PSEUDO_REGISTER
1073 && asm_noperands (PATTERN (use_insn
)) >= 0)
1076 /* Don't add duplicate links between instructions. */
1077 struct insn_link
*links
;
1078 FOR_EACH_LOG_LINK (links
, use_insn
)
1079 if (insn
== links
->insn
&& regno
== links
->regno
)
1083 LOG_LINKS (use_insn
)
1084 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1087 FOR_EACH_INSN_USE (use
, insn
)
1088 if (can_combine_use_p (use
))
1089 next_use
[DF_REF_REGNO (use
)] = insn
;
1096 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1097 true if we found a LOG_LINK that proves that A feeds B. This only works
1098 if there are no instructions between A and B which could have a link
1099 depending on A, since in that case we would not record a link for B. */
1102 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1104 struct insn_link
*links
;
1105 FOR_EACH_LOG_LINK (links
, b
)
1106 if (links
->insn
== a
)
1111 /* Main entry point for combiner. F is the first insn of the function.
1112 NREGS is the first unused pseudo-reg number.
1114 Return nonzero if the CFG was changed (e.g. if the combiner has
1115 turned an indirect jump instruction into a direct jump). */
1117 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1119 rtx_insn
*insn
, *next
;
1120 struct insn_link
*links
, *nextlinks
;
1122 basic_block last_bb
;
1124 int new_direct_jump_p
= 0;
1126 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1127 first
= NEXT_INSN (first
);
1131 combine_attempts
= 0;
1134 combine_successes
= 0;
1136 rtl_hooks
= combine_rtl_hooks
;
1138 reg_stat
.safe_grow_cleared (nregs
, true);
1140 init_recog_no_volatile ();
1142 /* Allocate array for insn info. */
1143 max_uid_known
= get_max_uid ();
1144 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1145 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1146 gcc_obstack_init (&insn_link_obstack
);
1148 nonzero_bits_mode
= int_mode_for_size (HOST_BITS_PER_WIDE_INT
, 0).require ();
1150 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1151 problems when, for example, we have j <<= 1 in a loop. */
1153 nonzero_sign_valid
= 0;
1154 label_tick
= label_tick_ebb_start
= 1;
1156 /* Scan all SETs and see if we can deduce anything about what
1157 bits are known to be zero for some registers and how many copies
1158 of the sign bit are known to exist for those registers.
1160 Also set any known values so that we can use it while searching
1161 for what bits are known to be set. */
1163 setup_incoming_promotions (first
);
1164 /* Allow the entry block and the first block to fall into the same EBB.
1165 Conceptually the incoming promotions are assigned to the entry block. */
1166 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1168 create_log_links ();
1169 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1171 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1176 if (!single_pred_p (this_basic_block
)
1177 || single_pred (this_basic_block
) != last_bb
)
1178 label_tick_ebb_start
= label_tick
;
1179 last_bb
= this_basic_block
;
1181 FOR_BB_INSNS (this_basic_block
, insn
)
1182 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1186 subst_low_luid
= DF_INSN_LUID (insn
);
1189 note_stores (insn
, set_nonzero_bits_and_sign_copies
, insn
);
1190 record_dead_and_set_regs (insn
);
1193 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1194 if (REG_NOTE_KIND (links
) == REG_INC
)
1195 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1198 /* Record the current insn_cost of this instruction. */
1199 INSN_COST (insn
) = insn_cost (insn
, optimize_this_for_speed_p
);
1202 fprintf (dump_file
, "insn_cost %d for ", INSN_COST (insn
));
1203 dump_insn_slim (dump_file
, insn
);
1208 nonzero_sign_valid
= 1;
1210 /* Now scan all the insns in forward order. */
1211 label_tick
= label_tick_ebb_start
= 1;
1213 setup_incoming_promotions (first
);
1214 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1215 int max_combine
= param_max_combine_insns
;
1217 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1219 rtx_insn
*last_combined_insn
= NULL
;
1221 /* Ignore instruction combination in basic blocks that are going to
1222 be removed as unreachable anyway. See PR82386. */
1223 if (EDGE_COUNT (this_basic_block
->preds
) == 0)
1226 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1231 if (!single_pred_p (this_basic_block
)
1232 || single_pred (this_basic_block
) != last_bb
)
1233 label_tick_ebb_start
= label_tick
;
1234 last_bb
= this_basic_block
;
1236 rtl_profile_for_bb (this_basic_block
);
1237 for (insn
= BB_HEAD (this_basic_block
);
1238 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1239 insn
= next
? next
: NEXT_INSN (insn
))
1242 if (!NONDEBUG_INSN_P (insn
))
1245 while (last_combined_insn
1246 && (!NONDEBUG_INSN_P (last_combined_insn
)
1247 || last_combined_insn
->deleted ()))
1248 last_combined_insn
= PREV_INSN (last_combined_insn
);
1249 if (last_combined_insn
== NULL_RTX
1250 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1251 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1252 last_combined_insn
= insn
;
1254 /* See if we know about function return values before this
1255 insn based upon SUBREG flags. */
1256 check_promoted_subreg (insn
, PATTERN (insn
));
1258 /* See if we can find hardregs and subreg of pseudos in
1259 narrower modes. This could help turning TRUNCATEs
1261 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1263 /* Try this insn with each insn it links back to. */
1265 FOR_EACH_LOG_LINK (links
, insn
)
1266 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1267 NULL
, &new_direct_jump_p
,
1268 last_combined_insn
)) != 0)
1270 statistics_counter_event (cfun
, "two-insn combine", 1);
1274 /* Try each sequence of three linked insns ending with this one. */
1276 if (max_combine
>= 3)
1277 FOR_EACH_LOG_LINK (links
, insn
)
1279 rtx_insn
*link
= links
->insn
;
1281 /* If the linked insn has been replaced by a note, then there
1282 is no point in pursuing this chain any further. */
1286 FOR_EACH_LOG_LINK (nextlinks
, link
)
1287 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1288 NULL
, &new_direct_jump_p
,
1289 last_combined_insn
)) != 0)
1291 statistics_counter_event (cfun
, "three-insn combine", 1);
1296 /* Try combining an insn with two different insns whose results it
1298 if (max_combine
>= 3)
1299 FOR_EACH_LOG_LINK (links
, insn
)
1300 for (nextlinks
= links
->next
; nextlinks
;
1301 nextlinks
= nextlinks
->next
)
1302 if ((next
= try_combine (insn
, links
->insn
,
1303 nextlinks
->insn
, NULL
,
1305 last_combined_insn
)) != 0)
1308 statistics_counter_event (cfun
, "three-insn combine", 1);
1312 /* Try four-instruction combinations. */
1313 if (max_combine
>= 4)
1314 FOR_EACH_LOG_LINK (links
, insn
)
1316 struct insn_link
*next1
;
1317 rtx_insn
*link
= links
->insn
;
1319 /* If the linked insn has been replaced by a note, then there
1320 is no point in pursuing this chain any further. */
1324 FOR_EACH_LOG_LINK (next1
, link
)
1326 rtx_insn
*link1
= next1
->insn
;
1329 /* I0 -> I1 -> I2 -> I3. */
1330 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1331 if ((next
= try_combine (insn
, link
, link1
,
1334 last_combined_insn
)) != 0)
1336 statistics_counter_event (cfun
, "four-insn combine", 1);
1339 /* I0, I1 -> I2, I2 -> I3. */
1340 for (nextlinks
= next1
->next
; nextlinks
;
1341 nextlinks
= nextlinks
->next
)
1342 if ((next
= try_combine (insn
, link
, link1
,
1345 last_combined_insn
)) != 0)
1347 statistics_counter_event (cfun
, "four-insn combine", 1);
1352 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1354 rtx_insn
*link1
= next1
->insn
;
1357 /* I0 -> I2; I1, I2 -> I3. */
1358 FOR_EACH_LOG_LINK (nextlinks
, link
)
1359 if ((next
= try_combine (insn
, link
, link1
,
1362 last_combined_insn
)) != 0)
1364 statistics_counter_event (cfun
, "four-insn combine", 1);
1367 /* I0 -> I1; I1, I2 -> I3. */
1368 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1369 if ((next
= try_combine (insn
, link
, link1
,
1372 last_combined_insn
)) != 0)
1374 statistics_counter_event (cfun
, "four-insn combine", 1);
1380 /* Try this insn with each REG_EQUAL note it links back to. */
1381 FOR_EACH_LOG_LINK (links
, insn
)
1384 rtx_insn
*temp
= links
->insn
;
1385 if ((set
= single_set (temp
)) != 0
1386 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1387 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1388 && ! side_effects_p (SET_SRC (set
))
1389 /* Avoid using a register that may already been marked
1390 dead by an earlier instruction. */
1391 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1392 && (GET_MODE (note
) == VOIDmode
1393 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1394 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1395 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1396 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1397 == GET_MODE (note
))))))
1399 /* Temporarily replace the set's source with the
1400 contents of the REG_EQUAL note. The insn will
1401 be deleted or recognized by try_combine. */
1402 rtx orig_src
= SET_SRC (set
);
1403 rtx orig_dest
= SET_DEST (set
);
1404 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1405 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1406 SET_SRC (set
) = note
;
1408 i2mod_old_rhs
= copy_rtx (orig_src
);
1409 i2mod_new_rhs
= copy_rtx (note
);
1410 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1412 last_combined_insn
);
1416 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1419 INSN_CODE (temp
) = -1;
1420 SET_SRC (set
) = orig_src
;
1421 SET_DEST (set
) = orig_dest
;
1426 record_dead_and_set_regs (insn
);
1433 default_rtl_profile ();
1435 new_direct_jump_p
|= purge_all_dead_edges ();
1436 new_direct_jump_p
|= delete_noop_moves ();
1439 obstack_free (&insn_link_obstack
, NULL
);
1440 free (uid_log_links
);
1441 free (uid_insn_cost
);
1442 reg_stat
.release ();
1445 struct undo
*undo
, *next
;
1446 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1454 total_attempts
+= combine_attempts
;
1455 total_merges
+= combine_merges
;
1456 total_extras
+= combine_extras
;
1457 total_successes
+= combine_successes
;
1459 nonzero_sign_valid
= 0;
1460 rtl_hooks
= general_rtl_hooks
;
1462 /* Make recognizer allow volatile MEMs again. */
1465 return new_direct_jump_p
;
1468 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1471 init_reg_last (void)
1476 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1477 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1480 /* Set up any promoted values for incoming argument registers. */
1483 setup_incoming_promotions (rtx_insn
*first
)
1486 bool strictly_local
= false;
1488 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1489 arg
= DECL_CHAIN (arg
))
1491 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1493 machine_mode mode1
, mode2
, mode3
, mode4
;
1495 /* Only continue if the incoming argument is in a register. */
1499 /* Determine, if possible, whether all call sites of the current
1500 function lie within the current compilation unit. (This does
1501 take into account the exporting of a function via taking its
1502 address, and so forth.) */
1504 = cgraph_node::local_info_node (current_function_decl
)->local
;
1506 /* The mode and signedness of the argument before any promotions happen
1507 (equal to the mode of the pseudo holding it at that stage). */
1508 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1509 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1511 /* The mode and signedness of the argument after any source language and
1512 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1513 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1514 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1516 /* The mode and signedness of the argument as it is actually passed,
1517 see assign_parm_setup_reg in function.cc. */
1518 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1519 TREE_TYPE (cfun
->decl
), 0);
1521 /* The mode of the register in which the argument is being passed. */
1522 mode4
= GET_MODE (reg
);
1524 /* Eliminate sign extensions in the callee when:
1525 (a) A mode promotion has occurred; */
1528 /* (b) The mode of the register is the same as the mode of
1529 the argument as it is passed; */
1532 /* (c) There's no language level extension; */
1535 /* (c.1) All callers are from the current compilation unit. If that's
1536 the case we don't have to rely on an ABI, we only have to know
1537 what we're generating right now, and we know that we will do the
1538 mode1 to mode2 promotion with the given sign. */
1539 else if (!strictly_local
)
1541 /* (c.2) The combination of the two promotions is useful. This is
1542 true when the signs match, or if the first promotion is unsigned.
1543 In the later case, (sign_extend (zero_extend x)) is the same as
1544 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1550 /* Record that the value was promoted from mode1 to mode3,
1551 so that any sign extension at the head of the current
1552 function may be eliminated. */
1553 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1554 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1555 record_value_for_reg (reg
, first
, x
);
1559 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1560 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1561 because some machines (maybe most) will actually do the sign-extension and
1562 this is the conservative approach.
1564 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1568 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1570 scalar_int_mode int_mode
;
1571 if (CONST_INT_P (src
)
1572 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1573 && GET_MODE_PRECISION (int_mode
) < prec
1575 && val_signbit_known_set_p (int_mode
, INTVAL (src
)))
1576 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (int_mode
));
1581 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1585 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1588 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1589 unsigned HOST_WIDE_INT bits
= 0;
1590 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1591 unsigned int num
= 0;
1594 reg_equal
= XEXP (reg_equal_note
, 0);
1596 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1598 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1600 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1603 /* Don't call nonzero_bits if it cannot change anything. */
1604 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1606 machine_mode mode
= GET_MODE (x
);
1607 if (GET_MODE_CLASS (mode
) == MODE_INT
1608 && HWI_COMPUTABLE_MODE_P (mode
))
1609 mode
= nonzero_bits_mode
;
1610 bits
= nonzero_bits (src
, mode
);
1611 if (reg_equal
&& bits
)
1612 bits
&= nonzero_bits (reg_equal
, mode
);
1613 rsp
->nonzero_bits
|= bits
;
1616 /* Don't call num_sign_bit_copies if it cannot change anything. */
1617 if (rsp
->sign_bit_copies
!= 1)
1619 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1620 if (reg_equal
&& maybe_ne (num
, GET_MODE_PRECISION (GET_MODE (x
))))
1622 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1623 if (num
== 0 || numeq
> num
)
1626 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1627 rsp
->sign_bit_copies
= num
;
1631 /* Called via note_stores. If X is a pseudo that is narrower than
1632 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1634 If we are setting only a portion of X and we can't figure out what
1635 portion, assume all bits will be used since we don't know what will
1638 Similarly, set how many bits of X are known to be copies of the sign bit
1639 at all locations in the function. This is the smallest number implied
1643 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1645 rtx_insn
*insn
= (rtx_insn
*) data
;
1646 scalar_int_mode mode
;
1649 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1650 /* If this register is undefined at the start of the file, we can't
1651 say what its contents were. */
1652 && ! REGNO_REG_SET_P
1653 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1654 && is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
1655 && HWI_COMPUTABLE_MODE_P (mode
))
1657 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1659 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1661 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1662 rsp
->sign_bit_copies
= 1;
1666 /* If this register is being initialized using itself, and the
1667 register is uninitialized in this basic block, and there are
1668 no LOG_LINKS which set the register, then part of the
1669 register is uninitialized. In that case we can't assume
1670 anything about the number of nonzero bits.
1672 ??? We could do better if we checked this in
1673 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1674 could avoid making assumptions about the insn which initially
1675 sets the register, while still using the information in other
1676 insns. We would have to be careful to check every insn
1677 involved in the combination. */
1680 && reg_referenced_p (x
, PATTERN (insn
))
1681 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1684 struct insn_link
*link
;
1686 FOR_EACH_LOG_LINK (link
, insn
)
1687 if (dead_or_set_p (link
->insn
, x
))
1691 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1692 rsp
->sign_bit_copies
= 1;
1697 /* If this is a complex assignment, see if we can convert it into a
1698 simple assignment. */
1699 set
= expand_field_assignment (set
);
1701 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1702 set what we know about X. */
1704 if (SET_DEST (set
) == x
1705 || (paradoxical_subreg_p (SET_DEST (set
))
1706 && SUBREG_REG (SET_DEST (set
)) == x
))
1707 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1710 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1711 rsp
->sign_bit_copies
= 1;
1716 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1717 optionally insns that were previously combined into I3 or that will be
1718 combined into the merger of INSN and I3. The order is PRED, PRED2,
1719 INSN, SUCC, SUCC2, I3.
1721 Return 0 if the combination is not allowed for any reason.
1723 If the combination is allowed, *PDEST will be set to the single
1724 destination of INSN and *PSRC to the single source, and this function
1728 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1729 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1730 rtx
*pdest
, rtx
*psrc
)
1737 bool all_adjacent
= true;
1738 int (*is_volatile_p
) (const_rtx
);
1744 if (next_active_insn (succ2
) != i3
)
1745 all_adjacent
= false;
1746 if (next_active_insn (succ
) != succ2
)
1747 all_adjacent
= false;
1749 else if (next_active_insn (succ
) != i3
)
1750 all_adjacent
= false;
1751 if (next_active_insn (insn
) != succ
)
1752 all_adjacent
= false;
1754 else if (next_active_insn (insn
) != i3
)
1755 all_adjacent
= false;
1757 /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1758 or a PARALLEL consisting of such a SET and CLOBBERs.
1760 If INSN has CLOBBER parallel parts, ignore them for our processing.
1761 By definition, these happen during the execution of the insn. When it
1762 is merged with another insn, all bets are off. If they are, in fact,
1763 needed and aren't also supplied in I3, they may be added by
1764 recog_for_combine. Otherwise, it won't match.
1766 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1769 Get the source and destination of INSN. If more than one, can't
1772 if (GET_CODE (PATTERN (insn
)) == SET
)
1773 set
= PATTERN (insn
);
1774 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1775 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1777 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1779 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1781 switch (GET_CODE (elt
))
1783 /* This is important to combine floating point insns
1784 for the SH4 port. */
1786 /* Combining an isolated USE doesn't make sense.
1787 We depend here on combinable_i3pat to reject them. */
1788 /* The code below this loop only verifies that the inputs of
1789 the SET in INSN do not change. We call reg_set_between_p
1790 to verify that the REG in the USE does not change between
1792 If the USE in INSN was for a pseudo register, the matching
1793 insn pattern will likely match any register; combining this
1794 with any other USE would only be safe if we knew that the
1795 used registers have identical values, or if there was
1796 something to tell them apart, e.g. different modes. For
1797 now, we forgo such complicated tests and simply disallow
1798 combining of USES of pseudo registers with any other USE. */
1799 if (REG_P (XEXP (elt
, 0))
1800 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1802 rtx i3pat
= PATTERN (i3
);
1803 int i
= XVECLEN (i3pat
, 0) - 1;
1804 unsigned int regno
= REGNO (XEXP (elt
, 0));
1808 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1810 if (GET_CODE (i3elt
) == USE
1811 && REG_P (XEXP (i3elt
, 0))
1812 && (REGNO (XEXP (i3elt
, 0)) == regno
1813 ? reg_set_between_p (XEXP (elt
, 0),
1814 PREV_INSN (insn
), i3
)
1815 : regno
>= FIRST_PSEUDO_REGISTER
))
1822 /* We can ignore CLOBBERs. */
1827 /* Ignore SETs whose result isn't used but not those that
1828 have side-effects. */
1829 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1830 && insn_nothrow_p (insn
)
1831 && !side_effects_p (elt
))
1834 /* If we have already found a SET, this is a second one and
1835 so we cannot combine with this insn. */
1843 /* Anything else means we can't combine. */
1849 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1850 so don't do anything with it. */
1851 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1860 /* The simplification in expand_field_assignment may call back to
1861 get_last_value, so set safe guard here. */
1862 subst_low_luid
= DF_INSN_LUID (insn
);
1864 set
= expand_field_assignment (set
);
1865 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1867 /* Do not eliminate user-specified register if it is in an
1868 asm input because we may break the register asm usage defined
1869 in GCC manual if allow to do so.
1870 Be aware that this may cover more cases than we expect but this
1871 should be harmless. */
1872 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1873 && extract_asm_operands (PATTERN (i3
)))
1876 /* Don't eliminate a store in the stack pointer. */
1877 if (dest
== stack_pointer_rtx
1878 /* Don't combine with an insn that sets a register to itself if it has
1879 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1880 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1881 /* Can't merge an ASM_OPERANDS. */
1882 || GET_CODE (src
) == ASM_OPERANDS
1883 /* Can't merge a function call. */
1884 || GET_CODE (src
) == CALL
1885 /* Don't eliminate a function call argument. */
1887 && (find_reg_fusage (i3
, USE
, dest
)
1889 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1890 && global_regs
[REGNO (dest
)])))
1891 /* Don't substitute into an incremented register. */
1892 || FIND_REG_INC_NOTE (i3
, dest
)
1893 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1894 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1895 /* Don't substitute into a non-local goto, this confuses CFG. */
1896 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1897 /* Make sure that DEST is not used after INSN but before SUCC, or
1898 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1901 && (reg_used_between_p (dest
, succ2
, i3
)
1902 || reg_used_between_p (dest
, succ
, succ2
)))
1903 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))
1904 || (!succ2
&& !succ
&& reg_used_between_p (dest
, insn
, i3
))
1906 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1907 that case SUCC is not in the insn stream, so use SUCC2
1908 instead for this test. */
1909 && reg_used_between_p (dest
, insn
,
1911 && INSN_UID (succ
) == INSN_UID (succ2
)
1913 /* Make sure that the value that is to be substituted for the register
1914 does not use any registers whose values alter in between. However,
1915 If the insns are adjacent, a use can't cross a set even though we
1916 think it might (this can happen for a sequence of insns each setting
1917 the same destination; last_set of that register might point to
1918 a NOTE). If INSN has a REG_EQUIV note, the register is always
1919 equivalent to the memory so the substitution is valid even if there
1920 are intervening stores. Also, don't move a volatile asm or
1921 UNSPEC_VOLATILE across any other insns. */
1924 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1925 && modified_between_p (src
, insn
, i3
))
1926 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1927 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1928 /* Don't combine across a CALL_INSN, because that would possibly
1929 change whether the life span of some REGs crosses calls or not,
1930 and it is a pain to update that information.
1931 Exception: if source is a constant, moving it later can't hurt.
1932 Accept that as a special case. */
1933 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1936 /* DEST must be a REG. */
1939 /* If register alignment is being enforced for multi-word items in all
1940 cases except for parameters, it is possible to have a register copy
1941 insn referencing a hard register that is not allowed to contain the
1942 mode being copied and which would not be valid as an operand of most
1943 insns. Eliminate this problem by not combining with such an insn.
1945 Also, on some machines we don't want to extend the life of a hard
1949 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1950 && !targetm
.hard_regno_mode_ok (REGNO (dest
), GET_MODE (dest
)))
1951 /* Don't extend the life of a hard register unless it is
1952 user variable (if we have few registers) or it can't
1953 fit into the desired register (meaning something special
1955 Also avoid substituting a return register into I3, because
1956 reload can't handle a conflict with constraints of other
1958 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1959 && !targetm
.hard_regno_mode_ok (REGNO (src
),
1967 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1968 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1969 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1971 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1973 /* If the clobber represents an earlyclobber operand, we must not
1974 substitute an expression containing the clobbered register.
1975 As we do not analyze the constraint strings here, we have to
1976 make the conservative assumption. However, if the register is
1977 a fixed hard reg, the clobber cannot represent any operand;
1978 we leave it up to the machine description to either accept or
1979 reject use-and-clobber patterns. */
1981 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1982 || !fixed_regs
[REGNO (reg
)])
1983 if (reg_overlap_mentioned_p (reg
, src
))
1987 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1988 or not), reject, unless nothing volatile comes between it and I3 */
1990 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1992 /* Make sure neither succ nor succ2 contains a volatile reference. */
1993 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1995 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1997 /* We'll check insns between INSN and I3 below. */
2000 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2001 to be an explicit register variable, and was chosen for a reason. */
2003 if (GET_CODE (src
) == ASM_OPERANDS
2004 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2007 /* If INSN contains volatile references (specifically volatile MEMs),
2008 we cannot combine across any other volatile references.
2009 Even if INSN doesn't contain volatile references, any intervening
2010 volatile insn might affect machine state. */
2012 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2016 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2017 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2020 /* If INSN contains an autoincrement or autodecrement, make sure that
2021 register is not used between there and I3, and not already used in
2022 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2023 Also insist that I3 not be a jump if using LRA; if it were one
2024 and the incremented register were spilled, we would lose.
2025 Reload handles this correctly. */
2028 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2029 if (REG_NOTE_KIND (link
) == REG_INC
2030 && ((JUMP_P (i3
) && targetm
.lra_p ())
2031 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2032 || (pred
!= NULL_RTX
2033 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2034 || (pred2
!= NULL_RTX
2035 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2036 || (succ
!= NULL_RTX
2037 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2038 || (succ2
!= NULL_RTX
2039 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2040 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2043 /* If we get here, we have passed all the tests and the combination is
2052 /* LOC is the location within I3 that contains its pattern or the component
2053 of a PARALLEL of the pattern. We validate that it is valid for combining.
2055 One problem is if I3 modifies its output, as opposed to replacing it
2056 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2057 doing so would produce an insn that is not equivalent to the original insns.
2061 (set (reg:DI 101) (reg:DI 100))
2062 (set (subreg:SI (reg:DI 101) 0) <foo>)
2064 This is NOT equivalent to:
2066 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2067 (set (reg:DI 101) (reg:DI 100))])
2069 Not only does this modify 100 (in which case it might still be valid
2070 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2072 We can also run into a problem if I2 sets a register that I1
2073 uses and I1 gets directly substituted into I3 (not via I2). In that
2074 case, we would be getting the wrong value of I2DEST into I3, so we
2075 must reject the combination. This case occurs when I2 and I1 both
2076 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2077 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2078 of a SET must prevent combination from occurring. The same situation
2079 can occur for I0, in which case I0_NOT_IN_SRC is set.
2081 Before doing the above check, we first try to expand a field assignment
2082 into a set of logical operations.
2084 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2085 we place a register that is both set and used within I3. If more than one
2086 such register is detected, we fail.
2088 Return 1 if the combination is valid, zero otherwise. */
2091 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2092 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2096 if (GET_CODE (x
) == SET
)
2099 rtx dest
= SET_DEST (set
);
2100 rtx src
= SET_SRC (set
);
2101 rtx inner_dest
= dest
;
2104 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2105 || GET_CODE (inner_dest
) == SUBREG
2106 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2107 inner_dest
= XEXP (inner_dest
, 0);
2109 /* Check for the case where I3 modifies its output, as discussed
2110 above. We don't want to prevent pseudos from being combined
2111 into the address of a MEM, so only prevent the combination if
2112 i1 or i2 set the same MEM. */
2113 if ((inner_dest
!= dest
&&
2114 (!MEM_P (inner_dest
)
2115 || rtx_equal_p (i2dest
, inner_dest
)
2116 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2117 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2118 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2119 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2120 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2122 /* This is the same test done in can_combine_p except we can't test
2123 all_adjacent; we don't have to, since this instruction will stay
2124 in place, thus we are not considering increasing the lifetime of
2127 Also, if this insn sets a function argument, combining it with
2128 something that might need a spill could clobber a previous
2129 function argument; the all_adjacent test in can_combine_p also
2130 checks this; here, we do a more specific test for this case. */
2132 || (REG_P (inner_dest
)
2133 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2134 && !targetm
.hard_regno_mode_ok (REGNO (inner_dest
),
2135 GET_MODE (inner_dest
)))
2136 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2137 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2140 /* If DEST is used in I3, it is being killed in this insn, so
2141 record that for later. We have to consider paradoxical
2142 subregs here, since they kill the whole register, but we
2143 ignore partial subregs, STRICT_LOW_PART, etc.
2144 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2145 STACK_POINTER_REGNUM, since these are always considered to be
2146 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2148 if (GET_CODE (subdest
) == SUBREG
&& !partial_subreg_p (subdest
))
2149 subdest
= SUBREG_REG (subdest
);
2152 && reg_referenced_p (subdest
, PATTERN (i3
))
2153 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2154 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2155 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2156 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2157 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2158 || ! fixed_regs
[REGNO (subdest
)]))
2159 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2161 if (*pi3dest_killed
)
2164 *pi3dest_killed
= subdest
;
2168 else if (GET_CODE (x
) == PARALLEL
)
2172 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2173 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2174 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2181 /* Return 1 if X is an arithmetic expression that contains a multiplication
2182 and division. We don't count multiplications by powers of two here. */
2185 contains_muldiv (rtx x
)
2187 switch (GET_CODE (x
))
2189 case MOD
: case DIV
: case UMOD
: case UDIV
:
2193 return ! (CONST_INT_P (XEXP (x
, 1))
2194 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2197 return contains_muldiv (XEXP (x
, 0))
2198 || contains_muldiv (XEXP (x
, 1));
2201 return contains_muldiv (XEXP (x
, 0));
2207 /* Determine whether INSN can be used in a combination. Return nonzero if
2208 not. This is used in try_combine to detect early some cases where we
2209 can't perform combinations. */
2212 cant_combine_insn_p (rtx_insn
*insn
)
2217 /* If this isn't really an insn, we can't do anything.
2218 This can occur when flow deletes an insn that it has merged into an
2219 auto-increment address. */
2220 if (!NONDEBUG_INSN_P (insn
))
2223 /* Never combine loads and stores involving hard regs that are likely
2224 to be spilled. The register allocator can usually handle such
2225 reg-reg moves by tying. If we allow the combiner to make
2226 substitutions of likely-spilled regs, reload might die.
2227 As an exception, we allow combinations involving fixed regs; these are
2228 not available to the register allocator so there's no risk involved. */
2230 set
= single_set (insn
);
2233 src
= SET_SRC (set
);
2234 dest
= SET_DEST (set
);
2235 if (GET_CODE (src
) == SUBREG
)
2236 src
= SUBREG_REG (src
);
2237 if (GET_CODE (dest
) == SUBREG
)
2238 dest
= SUBREG_REG (dest
);
2239 if (REG_P (src
) && REG_P (dest
)
2240 && ((HARD_REGISTER_P (src
)
2241 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2242 #ifdef LEAF_REGISTERS
2243 && ! LEAF_REGISTERS
[REGNO (src
)])
2247 || (HARD_REGISTER_P (dest
)
2248 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2249 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2255 struct likely_spilled_retval_info
2257 unsigned regno
, nregs
;
2261 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2262 hard registers that are known to be written to / clobbered in full. */
2264 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2266 struct likely_spilled_retval_info
*const info
=
2267 (struct likely_spilled_retval_info
*) data
;
2268 unsigned regno
, nregs
;
2271 if (!REG_P (XEXP (set
, 0)))
2274 if (regno
>= info
->regno
+ info
->nregs
)
2276 nregs
= REG_NREGS (x
);
2277 if (regno
+ nregs
<= info
->regno
)
2279 new_mask
= (2U << (nregs
- 1)) - 1;
2280 if (regno
< info
->regno
)
2281 new_mask
>>= info
->regno
- regno
;
2283 new_mask
<<= regno
- info
->regno
;
2284 info
->mask
&= ~new_mask
;
2287 /* Return nonzero iff part of the return value is live during INSN, and
2288 it is likely spilled. This can happen when more than one insn is needed
2289 to copy the return value, e.g. when we consider to combine into the
2290 second copy insn for a complex value. */
2293 likely_spilled_retval_p (rtx_insn
*insn
)
2295 rtx_insn
*use
= BB_END (this_basic_block
);
2298 unsigned regno
, nregs
;
2299 /* We assume here that no machine mode needs more than
2300 32 hard registers when the value overlaps with a register
2301 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2303 struct likely_spilled_retval_info info
;
2305 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2307 reg
= XEXP (PATTERN (use
), 0);
2308 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2310 regno
= REGNO (reg
);
2311 nregs
= REG_NREGS (reg
);
2314 mask
= (2U << (nregs
- 1)) - 1;
2316 /* Disregard parts of the return value that are set later. */
2320 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2322 note_stores (p
, likely_spilled_retval_1
, &info
);
2325 /* Check if any of the (probably) live return value registers is
2330 if ((mask
& 1 << nregs
)
2331 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2337 /* Adjust INSN after we made a change to its destination.
2339 Changing the destination can invalidate notes that say something about
2340 the results of the insn and a LOG_LINK pointing to the insn. */
2343 adjust_for_new_dest (rtx_insn
*insn
)
2345 /* For notes, be conservative and simply remove them. */
2346 remove_reg_equal_equiv_notes (insn
, true);
2348 /* The new insn will have a destination that was previously the destination
2349 of an insn just above it. Call distribute_links to make a LOG_LINK from
2350 the next use of that destination. */
2352 rtx set
= single_set (insn
);
2355 rtx reg
= SET_DEST (set
);
2357 while (GET_CODE (reg
) == ZERO_EXTRACT
2358 || GET_CODE (reg
) == STRICT_LOW_PART
2359 || GET_CODE (reg
) == SUBREG
)
2360 reg
= XEXP (reg
, 0);
2361 gcc_assert (REG_P (reg
));
2363 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2365 df_insn_rescan (insn
);
2368 /* Return TRUE if combine can reuse reg X in mode MODE.
2369 ADDED_SETS is nonzero if the original set is still required. */
2371 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2378 /* Don't change between modes with different underlying register sizes,
2379 since this could lead to invalid subregs. */
2380 if (maybe_ne (REGMODE_NATURAL_SIZE (mode
),
2381 REGMODE_NATURAL_SIZE (GET_MODE (x
))))
2385 /* Allow hard registers if the new mode is legal, and occupies no more
2386 registers than the old mode. */
2387 if (regno
< FIRST_PSEUDO_REGISTER
)
2388 return (targetm
.hard_regno_mode_ok (regno
, mode
)
2389 && REG_NREGS (x
) >= hard_regno_nregs (regno
, mode
));
2391 /* Or a pseudo that is only used once. */
2392 return (regno
< reg_n_sets_max
2393 && REG_N_SETS (regno
) == 1
2395 && !REG_USERVAR_P (x
));
2399 /* Check whether X, the destination of a set, refers to part of
2400 the register specified by REG. */
2403 reg_subword_p (rtx x
, rtx reg
)
2405 /* Check that reg is an integer mode register. */
2406 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2409 if (GET_CODE (x
) == STRICT_LOW_PART
2410 || GET_CODE (x
) == ZERO_EXTRACT
)
2413 return GET_CODE (x
) == SUBREG
2414 && !paradoxical_subreg_p (x
)
2415 && SUBREG_REG (x
) == reg
2416 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2419 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2420 by an arbitrary number of CLOBBERs. */
2422 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2424 if (GET_CODE (pat
) != PARALLEL
)
2427 int len
= XVECLEN (pat
, 0);
2432 for (i
= 0; i
< n
; i
++)
2433 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2434 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2436 for ( ; i
< len
; i
++)
2437 switch (GET_CODE (XVECEXP (pat
, 0, i
)))
2440 if (XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2449 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2450 CLOBBERs), can be split into individual SETs in that order, without
2451 changing semantics. */
2453 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2455 if (!insn_nothrow_p (insn
))
2458 rtx pat
= PATTERN (insn
);
2461 for (i
= 0; i
< n
; i
++)
2463 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2466 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2468 for (j
= i
+ 1; j
< n
; j
++)
2469 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2476 /* Return whether X is just a single_set, with the source
2477 a general_operand. */
2479 is_just_move (rtx_insn
*x
)
2481 rtx set
= single_set (x
);
2485 return general_operand (SET_SRC (set
), VOIDmode
);
2488 /* Callback function to count autoincs. */
2491 count_auto_inc (rtx
, rtx
, rtx
, rtx
, rtx
, void *arg
)
2498 /* Try to combine the insns I0, I1 and I2 into I3.
2499 Here I0, I1 and I2 appear earlier than I3.
2500 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2503 If we are combining more than two insns and the resulting insn is not
2504 recognized, try splitting it into two insns. If that happens, I2 and I3
2505 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2506 Otherwise, I0, I1 and I2 are pseudo-deleted.
2508 Return 0 if the combination does not work. Then nothing is changed.
2509 If we did the combination, return the insn at which combine should
2512 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2513 new direct jump instruction.
2515 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2516 been I3 passed to an earlier try_combine within the same basic
2520 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2521 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2523 /* New patterns for I3 and I2, respectively. */
2524 rtx newpat
, newi2pat
= 0;
2525 rtvec newpat_vec_with_clobbers
= 0;
2526 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2527 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2529 int added_sets_0
, added_sets_1
, added_sets_2
;
2530 /* Total number of SETs to put into I3. */
2532 /* Nonzero if I2's or I1's body now appears in I3. */
2533 int i2_is_used
= 0, i1_is_used
= 0;
2534 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2535 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2536 /* Contains I3 if the destination of I3 is used in its source, which means
2537 that the old life of I3 is being killed. If that usage is placed into
2538 I2 and not in I3, a REG_DEAD note must be made. */
2539 rtx i3dest_killed
= 0;
2540 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2541 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2542 /* Copy of SET_SRC of I1 and I0, if needed. */
2543 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2544 /* Set if I2DEST was reused as a scratch register. */
2545 bool i2scratch
= false;
2546 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2547 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2548 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2549 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2550 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2551 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2552 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2553 /* Notes that must be added to REG_NOTES in I3 and I2. */
2554 rtx new_i3_notes
, new_i2_notes
;
2555 /* Notes that we substituted I3 into I2 instead of the normal case. */
2556 int i3_subst_into_i2
= 0;
2557 /* Notes that I1, I2 or I3 is a MULT operation. */
2561 int changed_i3_dest
= 0;
2562 bool i2_was_move
= false, i3_was_move
= false;
2566 rtx_insn
*temp_insn
;
2568 struct insn_link
*link
;
2570 rtx new_other_notes
;
2572 scalar_int_mode dest_mode
, temp_mode
;
2573 bool has_non_call_exception
= false;
2575 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2577 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2580 /* Only try four-insn combinations when there's high likelihood of
2581 success. Look for simple insns, such as loads of constants or
2582 binary operations involving a constant. */
2590 if (!flag_expensive_optimizations
)
2593 for (i
= 0; i
< 4; i
++)
2595 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2596 rtx set
= single_set (insn
);
2600 src
= SET_SRC (set
);
2601 if (CONSTANT_P (src
))
2606 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2608 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2609 || GET_CODE (src
) == LSHIFTRT
)
2613 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2614 are likely manipulating its value. Ideally we'll be able to combine
2615 all four insns into a bitfield insertion of some kind.
2617 Note the source in I0 might be inside a sign/zero extension and the
2618 memory modes in I0 and I3 might be different. So extract the address
2619 from the destination of I3 and search for it in the source of I0.
2621 In the event that there's a match but the source/dest do not actually
2622 refer to the same memory, the worst that happens is we try some
2623 combinations that we wouldn't have otherwise. */
2624 if ((set0
= single_set (i0
))
2625 /* Ensure the source of SET0 is a MEM, possibly buried inside
2627 && (GET_CODE (SET_SRC (set0
)) == MEM
2628 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2629 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2630 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2631 && (set3
= single_set (i3
))
2632 /* Ensure the destination of SET3 is a MEM. */
2633 && GET_CODE (SET_DEST (set3
)) == MEM
2634 /* Would it be better to extract the base address for the MEM
2635 in SET3 and look for that? I don't have cases where it matters
2636 but I could envision such cases. */
2637 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2640 if (ngood
< 2 && nshift
< 2)
2644 /* Exit early if one of the insns involved can't be used for
2647 || (i1
&& CALL_P (i1
))
2648 || (i0
&& CALL_P (i0
))
2649 || cant_combine_insn_p (i3
)
2650 || cant_combine_insn_p (i2
)
2651 || (i1
&& cant_combine_insn_p (i1
))
2652 || (i0
&& cant_combine_insn_p (i0
))
2653 || likely_spilled_retval_p (i3
))
2657 undobuf
.other_insn
= 0;
2659 /* Reset the hard register usage information. */
2660 CLEAR_HARD_REG_SET (newpat_used_regs
);
2662 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2665 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2666 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2668 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2669 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2671 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2672 INSN_UID (i2
), INSN_UID (i3
));
2675 dump_insn_slim (dump_file
, i0
);
2677 dump_insn_slim (dump_file
, i1
);
2678 dump_insn_slim (dump_file
, i2
);
2679 dump_insn_slim (dump_file
, i3
);
2682 /* If multiple insns feed into one of I2 or I3, they can be in any
2683 order. To simplify the code below, reorder them in sequence. */
2684 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2686 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2688 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2691 added_links_insn
= 0;
2692 added_notes_insn
= 0;
2694 /* First check for one important special case that the code below will
2695 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2696 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2697 we may be able to replace that destination with the destination of I3.
2698 This occurs in the common code where we compute both a quotient and
2699 remainder into a structure, in which case we want to do the computation
2700 directly into the structure to avoid register-register copies.
2702 Note that this case handles both multiple sets in I2 and also cases
2703 where I2 has a number of CLOBBERs inside the PARALLEL.
2705 We make very conservative checks below and only try to handle the
2706 most common cases of this. For example, we only handle the case
2707 where I2 and I3 are adjacent to avoid making difficult register
2710 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2711 && REG_P (SET_SRC (PATTERN (i3
)))
2712 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2713 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2714 && GET_CODE (PATTERN (i2
)) == PARALLEL
2715 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2716 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2717 below would need to check what is inside (and reg_overlap_mentioned_p
2718 doesn't support those codes anyway). Don't allow those destinations;
2719 the resulting insn isn't likely to be recognized anyway. */
2720 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2721 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2722 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2723 SET_DEST (PATTERN (i3
)))
2724 && next_active_insn (i2
) == i3
)
2726 rtx p2
= PATTERN (i2
);
2728 /* Make sure that the destination of I3,
2729 which we are going to substitute into one output of I2,
2730 is not used within another output of I2. We must avoid making this:
2731 (parallel [(set (mem (reg 69)) ...)
2732 (set (reg 69) ...)])
2733 which is not well-defined as to order of actions.
2734 (Besides, reload can't handle output reloads for this.)
2736 The problem can also happen if the dest of I3 is a memory ref,
2737 if another dest in I2 is an indirect memory ref.
2739 Neither can this PARALLEL be an asm. We do not allow combining
2740 that usually (see can_combine_p), so do not here either. */
2742 for (i
= 0; ok
&& i
< XVECLEN (p2
, 0); i
++)
2744 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2745 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2746 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2747 SET_DEST (XVECEXP (p2
, 0, i
))))
2749 else if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2750 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2755 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2756 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2757 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2762 subst_low_luid
= DF_INSN_LUID (i2
);
2764 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2765 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2766 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2767 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2769 /* Replace the dest in I2 with our dest and make the resulting
2770 insn the new pattern for I3. Then skip to where we validate
2771 the pattern. Everything was set up above. */
2772 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2774 i3_subst_into_i2
= 1;
2775 goto validate_replacement
;
2779 /* If I2 is setting a pseudo to a constant and I3 is setting some
2780 sub-part of it to another constant, merge them by making a new
2783 && (temp_expr
= single_set (i2
)) != 0
2784 && is_a
<scalar_int_mode
> (GET_MODE (SET_DEST (temp_expr
)), &temp_mode
)
2785 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2786 && GET_CODE (PATTERN (i3
)) == SET
2787 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2788 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2790 rtx dest
= SET_DEST (PATTERN (i3
));
2791 rtx temp_dest
= SET_DEST (temp_expr
);
2795 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2797 if (CONST_INT_P (XEXP (dest
, 1))
2798 && CONST_INT_P (XEXP (dest
, 2))
2799 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (dest
, 0)),
2802 width
= INTVAL (XEXP (dest
, 1));
2803 offset
= INTVAL (XEXP (dest
, 2));
2804 dest
= XEXP (dest
, 0);
2805 if (BITS_BIG_ENDIAN
)
2806 offset
= GET_MODE_PRECISION (dest_mode
) - width
- offset
;
2811 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2812 dest
= XEXP (dest
, 0);
2813 if (is_a
<scalar_int_mode
> (GET_MODE (dest
), &dest_mode
))
2815 width
= GET_MODE_PRECISION (dest_mode
);
2822 /* If this is the low part, we're done. */
2823 if (subreg_lowpart_p (dest
))
2825 /* Handle the case where inner is twice the size of outer. */
2826 else if (GET_MODE_PRECISION (temp_mode
)
2827 == 2 * GET_MODE_PRECISION (dest_mode
))
2828 offset
+= GET_MODE_PRECISION (dest_mode
);
2829 /* Otherwise give up for now. */
2836 rtx inner
= SET_SRC (PATTERN (i3
));
2837 rtx outer
= SET_SRC (temp_expr
);
2839 wide_int o
= wi::insert (rtx_mode_t (outer
, temp_mode
),
2840 rtx_mode_t (inner
, dest_mode
),
2845 subst_low_luid
= DF_INSN_LUID (i2
);
2846 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2848 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2850 /* Replace the source in I2 with the new constant and make the
2851 resulting insn the new pattern for I3. Then skip to where we
2852 validate the pattern. Everything was set up above. */
2853 SUBST (SET_SRC (temp_expr
),
2854 immed_wide_int_const (o
, temp_mode
));
2856 newpat
= PATTERN (i2
);
2858 /* The dest of I3 has been replaced with the dest of I2. */
2859 changed_i3_dest
= 1;
2860 goto validate_replacement
;
2864 /* If we have no I1 and I2 looks like:
2865 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2867 make up a dummy I1 that is
2870 (set (reg:CC X) (compare:CC Y (const_int 0)))
2872 (We can ignore any trailing CLOBBERs.)
2874 This undoes a previous combination and allows us to match a branch-and-
2878 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2879 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2881 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2882 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2883 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2884 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2885 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2886 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2888 /* We make I1 with the same INSN_UID as I2. This gives it
2889 the same DF_INSN_LUID for value tracking. Our fake I1 will
2890 never appear in the insn stream so giving it the same INSN_UID
2891 as I2 will not cause a problem. */
2893 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2894 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2896 INSN_UID (i1
) = INSN_UID (i2
);
2898 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2899 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2900 SET_DEST (PATTERN (i1
)));
2901 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2902 SUBST_LINK (LOG_LINKS (i2
),
2903 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2906 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2907 make those two SETs separate I1 and I2 insns, and make an I0 that is
2910 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2911 && can_split_parallel_of_n_reg_sets (i2
, 2)
2912 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2913 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
)
2914 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2915 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2917 /* If there is no I1, there is no I0 either. */
2920 /* We make I1 with the same INSN_UID as I2. This gives it
2921 the same DF_INSN_LUID for value tracking. Our fake I1 will
2922 never appear in the insn stream so giving it the same INSN_UID
2923 as I2 will not cause a problem. */
2925 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2926 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2928 INSN_UID (i1
) = INSN_UID (i2
);
2930 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2933 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2934 if (!can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
))
2936 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2937 fprintf (dump_file
, "Can't combine i2 into i3\n");
2941 if (i1
&& !can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
, &i1dest
, &i1src
))
2943 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2944 fprintf (dump_file
, "Can't combine i1 into i3\n");
2948 if (i0
&& !can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
, &i0dest
, &i0src
))
2950 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2951 fprintf (dump_file
, "Can't combine i0 into i3\n");
2956 /* With non-call exceptions we can end up trying to combine multiple
2957 insns with possible EH side effects. Make sure we can combine
2958 that to a single insn which means there must be at most one insn
2959 in the combination with an EH side effect. */
2960 if (cfun
->can_throw_non_call_exceptions
)
2962 if (find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
)
2963 || find_reg_note (i2
, REG_EH_REGION
, NULL_RTX
)
2964 || (i1
&& find_reg_note (i1
, REG_EH_REGION
, NULL_RTX
))
2965 || (i0
&& find_reg_note (i0
, REG_EH_REGION
, NULL_RTX
)))
2967 has_non_call_exception
= true;
2968 if (insn_could_throw_p (i3
)
2969 + insn_could_throw_p (i2
)
2970 + (i1
? insn_could_throw_p (i1
) : 0)
2971 + (i0
? insn_could_throw_p (i0
) : 0) > 1)
2973 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2974 fprintf (dump_file
, "Can't combine multiple insns with EH "
2982 /* Record whether i2 and i3 are trivial moves. */
2983 i2_was_move
= is_just_move (i2
);
2984 i3_was_move
= is_just_move (i3
);
2986 /* Record whether I2DEST is used in I2SRC and similarly for the other
2987 cases. Knowing this will help in register status updating below. */
2988 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2989 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2990 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2991 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2992 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2993 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2994 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2995 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2996 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2998 /* For the earlier insns, determine which of the subsequent ones they
3000 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3001 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3002 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3003 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3004 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3006 /* Ensure that I3's pattern can be the destination of combines. */
3007 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3008 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3009 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3010 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3017 /* See if any of the insns is a MULT operation. Unless one is, we will
3018 reject a combination that is, since it must be slower. Be conservative
3020 if (GET_CODE (i2src
) == MULT
3021 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3022 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3023 || (GET_CODE (PATTERN (i3
)) == SET
3024 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3027 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3028 We used to do this EXCEPT in one case: I3 has a post-inc in an
3029 output operand. However, that exception can give rise to insns like
3031 which is a famous insn on the PDP-11 where the value of r3 used as the
3032 source was model-dependent. Avoid this sort of thing. */
3035 if (!(GET_CODE (PATTERN (i3
)) == SET
3036 && REG_P (SET_SRC (PATTERN (i3
)))
3037 && MEM_P (SET_DEST (PATTERN (i3
)))
3038 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3039 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3040 /* It's not the exception. */
3045 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3046 if (REG_NOTE_KIND (link
) == REG_INC
3047 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3049 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3056 /* See if the SETs in I1 or I2 need to be kept around in the merged
3057 instruction: whenever the value set there is still needed past I3.
3058 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3060 For the SET in I1, we have two cases: if I1 and I2 independently feed
3061 into I3, the set in I1 needs to be kept around unless I1DEST dies
3062 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3063 in I1 needs to be kept around unless I1DEST dies or is set in either
3064 I2 or I3. The same considerations apply to I0. */
3066 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3069 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3070 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3075 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3076 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3077 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3078 && dead_or_set_p (i2
, i0dest
)));
3082 /* We are about to copy insns for the case where they need to be kept
3083 around. Check that they can be copied in the merged instruction. */
3085 if (targetm
.cannot_copy_insn_p
3086 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3087 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3088 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3094 /* We cannot safely duplicate volatile references in any case. */
3096 if ((added_sets_2
&& volatile_refs_p (PATTERN (i2
)))
3097 || (added_sets_1
&& volatile_refs_p (PATTERN (i1
)))
3098 || (added_sets_0
&& volatile_refs_p (PATTERN (i0
))))
3104 /* Count how many auto_inc expressions there were in the original insns;
3105 we need to have the same number in the resulting patterns. */
3108 for_each_inc_dec (PATTERN (i0
), count_auto_inc
, &n_auto_inc
);
3110 for_each_inc_dec (PATTERN (i1
), count_auto_inc
, &n_auto_inc
);
3111 for_each_inc_dec (PATTERN (i2
), count_auto_inc
, &n_auto_inc
);
3112 for_each_inc_dec (PATTERN (i3
), count_auto_inc
, &n_auto_inc
);
3114 /* If the set in I2 needs to be kept around, we must make a copy of
3115 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3116 PATTERN (I2), we are only substituting for the original I1DEST, not into
3117 an already-substituted copy. This also prevents making self-referential
3118 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3123 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3124 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3126 i2pat
= copy_rtx (PATTERN (i2
));
3131 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3132 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3134 i1pat
= copy_rtx (PATTERN (i1
));
3139 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3140 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3142 i0pat
= copy_rtx (PATTERN (i0
));
3147 /* Substitute in the latest insn for the regs set by the earlier ones. */
3149 maxreg
= max_reg_num ();
3153 /* Many machines have insns that can both perform an
3154 arithmetic operation and set the condition code. These operations will
3155 be represented as a PARALLEL with the first element of the vector
3156 being a COMPARE of an arithmetic operation with the constant zero.
3157 The second element of the vector will set some pseudo to the result
3158 of the same arithmetic operation. If we simplify the COMPARE, we won't
3159 match such a pattern and so will generate an extra insn. Here we test
3160 for this case, where both the comparison and the operation result are
3161 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3162 I2SRC. Later we will make the PARALLEL that contains I2. */
3164 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3165 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3166 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3167 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3170 rtx
*cc_use_loc
= NULL
;
3171 rtx_insn
*cc_use_insn
= NULL
;
3172 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3173 machine_mode compare_mode
, orig_compare_mode
;
3174 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3175 scalar_int_mode mode
;
3177 newpat
= PATTERN (i3
);
3178 newpat_dest
= SET_DEST (newpat
);
3179 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3181 if (undobuf
.other_insn
== 0
3182 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3185 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3186 if (is_a
<scalar_int_mode
> (GET_MODE (i2dest
), &mode
))
3187 compare_code
= simplify_compare_const (compare_code
, mode
,
3189 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3192 /* Do the rest only if op1 is const0_rtx, which may be the
3193 result of simplification. */
3194 if (op1
== const0_rtx
)
3196 /* If a single use of the CC is found, prepare to modify it
3197 when SELECT_CC_MODE returns a new CC-class mode, or when
3198 the above simplify_compare_const() returned a new comparison
3199 operator. undobuf.other_insn is assigned the CC use insn
3200 when modifying it. */
3203 #ifdef SELECT_CC_MODE
3204 machine_mode new_mode
3205 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3206 if (new_mode
!= orig_compare_mode
3207 && can_change_dest_mode (SET_DEST (newpat
),
3208 added_sets_2
, new_mode
))
3210 unsigned int regno
= REGNO (newpat_dest
);
3211 compare_mode
= new_mode
;
3212 if (regno
< FIRST_PSEUDO_REGISTER
)
3213 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3216 subst_mode (regno
, compare_mode
);
3217 newpat_dest
= regno_reg_rtx
[regno
];
3221 /* Cases for modifying the CC-using comparison. */
3222 if (compare_code
!= orig_compare_code
3223 /* ??? Do we need to verify the zero rtx? */
3224 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3226 /* Replace cc_use_loc with entire new RTX. */
3228 gen_rtx_fmt_ee (compare_code
, GET_MODE (*cc_use_loc
),
3229 newpat_dest
, const0_rtx
));
3230 undobuf
.other_insn
= cc_use_insn
;
3232 else if (compare_mode
!= orig_compare_mode
)
3234 /* Just replace the CC reg with a new mode. */
3235 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3236 undobuf
.other_insn
= cc_use_insn
;
3240 /* Now we modify the current newpat:
3241 First, SET_DEST(newpat) is updated if the CC mode has been
3242 altered. For targets without SELECT_CC_MODE, this should be
3244 if (compare_mode
!= orig_compare_mode
)
3245 SUBST (SET_DEST (newpat
), newpat_dest
);
3246 /* This is always done to propagate i2src into newpat. */
3247 SUBST (SET_SRC (newpat
),
3248 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3249 /* Create new version of i2pat if needed; the below PARALLEL
3250 creation needs this to work correctly. */
3251 if (! rtx_equal_p (i2src
, op0
))
3252 i2pat
= gen_rtx_SET (i2dest
, op0
);
3257 if (i2_is_used
== 0)
3259 /* It is possible that the source of I2 or I1 may be performing
3260 an unneeded operation, such as a ZERO_EXTEND of something
3261 that is known to have the high part zero. Handle that case
3262 by letting subst look at the inner insns.
3264 Another way to do this would be to have a function that tries
3265 to simplify a single insn instead of merging two or more
3266 insns. We don't do this because of the potential of infinite
3267 loops and because of the potential extra memory required.
3268 However, doing it the way we are is a bit of a kludge and
3269 doesn't catch all cases.
3271 But only do this if -fexpensive-optimizations since it slows
3272 things down and doesn't usually win.
3274 This is not done in the COMPARE case above because the
3275 unmodified I2PAT is used in the PARALLEL and so a pattern
3276 with a modified I2SRC would not match. */
3278 if (flag_expensive_optimizations
)
3280 /* Pass pc_rtx so no substitutions are done, just
3284 subst_low_luid
= DF_INSN_LUID (i1
);
3285 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3288 subst_low_luid
= DF_INSN_LUID (i2
);
3289 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3292 n_occurrences
= 0; /* `subst' counts here */
3293 subst_low_luid
= DF_INSN_LUID (i2
);
3295 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3296 copy of I2SRC each time we substitute it, in order to avoid creating
3297 self-referential RTL when we will be substituting I1SRC for I1DEST
3298 later. Likewise if I0 feeds into I2, either directly or indirectly
3299 through I1, and I0DEST is in I0SRC. */
3300 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3301 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3302 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3303 && i0dest_in_i0src
));
3306 /* Record whether I2's body now appears within I3's body. */
3307 i2_is_used
= n_occurrences
;
3310 /* If we already got a failure, don't try to do more. Otherwise, try to
3311 substitute I1 if we have it. */
3313 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3315 /* Before we can do this substitution, we must redo the test done
3316 above (see detailed comments there) that ensures I1DEST isn't
3317 mentioned in any SETs in NEWPAT that are field assignments. */
3318 if (!combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3326 subst_low_luid
= DF_INSN_LUID (i1
);
3328 /* If the following substitution will modify I1SRC, make a copy of it
3329 for the case where it is substituted for I1DEST in I2PAT later. */
3330 if (added_sets_2
&& i1_feeds_i2_n
)
3331 i1src_copy
= copy_rtx (i1src
);
3333 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3334 copy of I1SRC each time we substitute it, in order to avoid creating
3335 self-referential RTL when we will be substituting I0SRC for I0DEST
3337 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3338 i0_feeds_i1_n
&& i0dest_in_i0src
);
3341 /* Record whether I1's body now appears within I3's body. */
3342 i1_is_used
= n_occurrences
;
3345 /* Likewise for I0 if we have it. */
3347 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3349 if (!combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3356 /* If the following substitution will modify I0SRC, make a copy of it
3357 for the case where it is substituted for I0DEST in I1PAT later. */
3358 if (added_sets_1
&& i0_feeds_i1_n
)
3359 i0src_copy
= copy_rtx (i0src
);
3360 /* And a copy for I0DEST in I2PAT substitution. */
3361 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3362 || (i0_feeds_i2_n
)))
3363 i0src_copy2
= copy_rtx (i0src
);
3366 subst_low_luid
= DF_INSN_LUID (i0
);
3367 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3373 int new_n_auto_inc
= 0;
3374 for_each_inc_dec (newpat
, count_auto_inc
, &new_n_auto_inc
);
3376 if (n_auto_inc
!= new_n_auto_inc
)
3378 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
3379 fprintf (dump_file
, "Number of auto_inc expressions changed\n");
3385 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3386 to count all the ways that I2SRC and I1SRC can be used. */
3387 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3388 && i2_is_used
+ added_sets_2
> 1)
3389 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3390 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3392 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3393 && (n_occurrences
+ added_sets_0
3394 + (added_sets_1
&& i0_feeds_i1_n
)
3395 + (added_sets_2
&& i0_feeds_i2_n
)
3397 /* Fail if we tried to make a new register. */
3398 || max_reg_num () != maxreg
3399 /* Fail if we couldn't do something and have a CLOBBER. */
3400 || GET_CODE (newpat
) == CLOBBER
3401 /* Fail if this new pattern is a MULT and we didn't have one before
3402 at the outer level. */
3403 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3410 /* If the actions of the earlier insns must be kept
3411 in addition to substituting them into the latest one,
3412 we must make a new PARALLEL for the latest insn
3413 to hold additional the SETs. */
3415 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3417 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3420 if (GET_CODE (newpat
) == PARALLEL
)
3422 rtvec old
= XVEC (newpat
, 0);
3423 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3424 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3425 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3426 sizeof (old
->elem
[0]) * old
->num_elem
);
3431 total_sets
= 1 + extra_sets
;
3432 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3433 XVECEXP (newpat
, 0, 0) = old
;
3437 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3443 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3445 XVECEXP (newpat
, 0, --total_sets
) = t
;
3451 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3452 i0_feeds_i1_n
&& i0dest_in_i0src
);
3453 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3454 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3456 XVECEXP (newpat
, 0, --total_sets
) = t
;
3460 validate_replacement
:
3462 /* Note which hard regs this insn has as inputs. */
3463 mark_used_regs_combine (newpat
);
3465 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3466 consider splitting this pattern, we might need these clobbers. */
3467 if (i1
&& GET_CODE (newpat
) == PARALLEL
3468 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3470 int len
= XVECLEN (newpat
, 0);
3472 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3473 for (i
= 0; i
< len
; i
++)
3474 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3477 /* We have recognized nothing yet. */
3478 insn_code_number
= -1;
3480 /* See if this is a PARALLEL of two SETs where one SET's destination is
3481 a register that is unused and this isn't marked as an instruction that
3482 might trap in an EH region. In that case, we just need the other SET.
3483 We prefer this over the PARALLEL.
3485 This can occur when simplifying a divmod insn. We *must* test for this
3486 case here because the code below that splits two independent SETs doesn't
3487 handle this case correctly when it updates the register status.
3489 It's pointless doing this if we originally had two sets, one from
3490 i3, and one from i2. Combining then splitting the parallel results
3491 in the original i2 again plus an invalid insn (which we delete).
3492 The net effect is only to move instructions around, which makes
3493 debug info less accurate.
3495 If the remaining SET came from I2 its destination should not be used
3496 between I2 and I3. See PR82024. */
3498 if (!(added_sets_2
&& i1
== 0)
3499 && is_parallel_of_n_reg_sets (newpat
, 2)
3500 && asm_noperands (newpat
) < 0)
3502 rtx set0
= XVECEXP (newpat
, 0, 0);
3503 rtx set1
= XVECEXP (newpat
, 0, 1);
3504 rtx oldpat
= newpat
;
3506 if (((REG_P (SET_DEST (set1
))
3507 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3508 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3509 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3510 && insn_nothrow_p (i3
)
3511 && !side_effects_p (SET_SRC (set1
)))
3514 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3517 else if (((REG_P (SET_DEST (set0
))
3518 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3519 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3520 && find_reg_note (i3
, REG_UNUSED
,
3521 SUBREG_REG (SET_DEST (set0
)))))
3522 && insn_nothrow_p (i3
)
3523 && !side_effects_p (SET_SRC (set0
)))
3525 rtx dest
= SET_DEST (set1
);
3526 if (GET_CODE (dest
) == SUBREG
)
3527 dest
= SUBREG_REG (dest
);
3528 if (!reg_used_between_p (dest
, i2
, i3
))
3531 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3533 if (insn_code_number
>= 0)
3534 changed_i3_dest
= 1;
3538 if (insn_code_number
< 0)
3542 /* Is the result of combination a valid instruction? */
3543 if (insn_code_number
< 0)
3544 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3546 /* If we were combining three insns and the result is a simple SET
3547 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3548 insns. There are two ways to do this. It can be split using a
3549 machine-specific method (like when you have an addition of a large
3550 constant) or by combine in the function find_split_point. */
3552 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3553 && asm_noperands (newpat
) < 0)
3555 rtx parallel
, *split
;
3556 rtx_insn
*m_split_insn
;
3558 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3559 use I2DEST as a scratch register will help. In the latter case,
3560 convert I2DEST to the mode of the source of NEWPAT if we can. */
3562 m_split_insn
= combine_split_insns (newpat
, i3
);
3564 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3565 inputs of NEWPAT. */
3567 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3568 possible to try that as a scratch reg. This would require adding
3569 more code to make it work though. */
3571 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3573 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3575 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3576 (temporarily, until we are committed to this instruction
3577 combination) does not work: for example, any call to nonzero_bits
3578 on the register (from a splitter in the MD file, for example)
3579 will get the old information, which is invalid.
3581 Since nowadays we can create registers during combine just fine,
3582 we should just create a new one here, not reuse i2dest. */
3584 /* First try to split using the original register as a
3585 scratch register. */
3586 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3587 gen_rtvec (2, newpat
,
3588 gen_rtx_CLOBBER (VOIDmode
,
3590 m_split_insn
= combine_split_insns (parallel
, i3
);
3592 /* If that didn't work, try changing the mode of I2DEST if
3594 if (m_split_insn
== 0
3595 && new_mode
!= GET_MODE (i2dest
)
3596 && new_mode
!= VOIDmode
3597 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3599 machine_mode old_mode
= GET_MODE (i2dest
);
3602 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3603 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3606 subst_mode (REGNO (i2dest
), new_mode
);
3607 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3610 parallel
= (gen_rtx_PARALLEL
3612 gen_rtvec (2, newpat
,
3613 gen_rtx_CLOBBER (VOIDmode
,
3615 m_split_insn
= combine_split_insns (parallel
, i3
);
3617 if (m_split_insn
== 0
3618 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3622 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3623 buf
= undobuf
.undos
;
3624 undobuf
.undos
= buf
->next
;
3625 buf
->next
= undobuf
.frees
;
3626 undobuf
.frees
= buf
;
3630 i2scratch
= m_split_insn
!= 0;
3633 /* If recog_for_combine has discarded clobbers, try to use them
3634 again for the split. */
3635 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3637 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3638 m_split_insn
= combine_split_insns (parallel
, i3
);
3641 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3643 rtx m_split_pat
= PATTERN (m_split_insn
);
3644 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3645 if (insn_code_number
>= 0)
3646 newpat
= m_split_pat
;
3648 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3649 && (next_nonnote_nondebug_insn (i2
) == i3
3650 || !modified_between_p (PATTERN (m_split_insn
), i2
, i3
)))
3653 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3654 newi2pat
= PATTERN (m_split_insn
);
3656 i3set
= single_set (NEXT_INSN (m_split_insn
));
3657 i2set
= single_set (m_split_insn
);
3659 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3661 /* If I2 or I3 has multiple SETs, we won't know how to track
3662 register status, so don't use these insns. If I2's destination
3663 is used between I2 and I3, we also can't use these insns. */
3665 if (i2_code_number
>= 0 && i2set
&& i3set
3666 && (next_nonnote_nondebug_insn (i2
) == i3
3667 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3668 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3670 if (insn_code_number
>= 0)
3673 /* It is possible that both insns now set the destination of I3.
3674 If so, we must show an extra use of it. */
3676 if (insn_code_number
>= 0)
3678 rtx new_i3_dest
= SET_DEST (i3set
);
3679 rtx new_i2_dest
= SET_DEST (i2set
);
3681 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3682 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3683 || GET_CODE (new_i3_dest
) == SUBREG
)
3684 new_i3_dest
= XEXP (new_i3_dest
, 0);
3686 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3687 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3688 || GET_CODE (new_i2_dest
) == SUBREG
)
3689 new_i2_dest
= XEXP (new_i2_dest
, 0);
3691 if (REG_P (new_i3_dest
)
3692 && REG_P (new_i2_dest
)
3693 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3694 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3695 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3699 /* If we can split it and use I2DEST, go ahead and see if that
3700 helps things be recognized. Verify that none of the registers
3701 are set between I2 and I3. */
3702 if (insn_code_number
< 0
3703 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3704 /* We need I2DEST in the proper mode. If it is a hard register
3705 or the only use of a pseudo, we can change its mode.
3706 Make sure we don't change a hard register to have a mode that
3707 isn't valid for it, or change the number of registers. */
3708 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3709 || GET_MODE (*split
) == VOIDmode
3710 || can_change_dest_mode (i2dest
, added_sets_2
,
3712 && (next_nonnote_nondebug_insn (i2
) == i3
3713 || !modified_between_p (*split
, i2
, i3
))
3714 /* We can't overwrite I2DEST if its value is still used by
3716 && ! reg_referenced_p (i2dest
, newpat
)
3717 /* We should not split a possibly trapping part when we
3718 care about non-call EH and have REG_EH_REGION notes
3720 && ! (cfun
->can_throw_non_call_exceptions
3721 && has_non_call_exception
3722 && may_trap_p (*split
)))
3724 rtx newdest
= i2dest
;
3725 enum rtx_code split_code
= GET_CODE (*split
);
3726 machine_mode split_mode
= GET_MODE (*split
);
3727 bool subst_done
= false;
3728 newi2pat
= NULL_RTX
;
3732 /* *SPLIT may be part of I2SRC, so make sure we have the
3733 original expression around for later debug processing.
3734 We should not need I2SRC any more in other cases. */
3735 if (MAY_HAVE_DEBUG_BIND_INSNS
)
3736 i2src
= copy_rtx (i2src
);
3740 /* Get NEWDEST as a register in the proper mode. We have already
3741 validated that we can do this. */
3742 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3744 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3745 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3748 subst_mode (REGNO (i2dest
), split_mode
);
3749 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3753 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3754 an ASHIFT. This can occur if it was inside a PLUS and hence
3755 appeared to be a memory address. This is a kludge. */
3756 if (split_code
== MULT
3757 && CONST_INT_P (XEXP (*split
, 1))
3758 && INTVAL (XEXP (*split
, 1)) > 0
3759 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3761 rtx i_rtx
= gen_int_shift_amount (split_mode
, i
);
3762 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3763 XEXP (*split
, 0), i_rtx
));
3764 /* Update split_code because we may not have a multiply
3766 split_code
= GET_CODE (*split
);
3769 /* Similarly for (plus (mult FOO (const_int pow2))). */
3770 if (split_code
== PLUS
3771 && GET_CODE (XEXP (*split
, 0)) == MULT
3772 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3773 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3774 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3776 rtx nsplit
= XEXP (*split
, 0);
3777 rtx i_rtx
= gen_int_shift_amount (GET_MODE (nsplit
), i
);
3778 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3781 /* Update split_code because we may not have a multiply
3783 split_code
= GET_CODE (*split
);
3786 #ifdef INSN_SCHEDULING
3787 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3788 be written as a ZERO_EXTEND. */
3789 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3791 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3792 what it really is. */
3793 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3795 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3796 SUBREG_REG (*split
)));
3798 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3799 SUBREG_REG (*split
)));
3803 /* Attempt to split binary operators using arithmetic identities. */
3804 if (BINARY_P (SET_SRC (newpat
))
3805 && split_mode
== GET_MODE (SET_SRC (newpat
))
3806 && ! side_effects_p (SET_SRC (newpat
)))
3808 rtx setsrc
= SET_SRC (newpat
);
3809 machine_mode mode
= GET_MODE (setsrc
);
3810 enum rtx_code code
= GET_CODE (setsrc
);
3811 rtx src_op0
= XEXP (setsrc
, 0);
3812 rtx src_op1
= XEXP (setsrc
, 1);
3814 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3815 if (rtx_equal_p (src_op0
, src_op1
))
3817 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3818 SUBST (XEXP (setsrc
, 0), newdest
);
3819 SUBST (XEXP (setsrc
, 1), newdest
);
3822 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3823 else if ((code
== PLUS
|| code
== MULT
)
3824 && GET_CODE (src_op0
) == code
3825 && GET_CODE (XEXP (src_op0
, 0)) == code
3826 && (INTEGRAL_MODE_P (mode
)
3827 || (FLOAT_MODE_P (mode
)
3828 && flag_unsafe_math_optimizations
)))
3830 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3831 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3832 rtx r
= XEXP (src_op0
, 1);
3835 /* Split both "((X op Y) op X) op Y" and
3836 "((X op Y) op Y) op X" as "T op T" where T is
3838 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3839 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3841 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3842 SUBST (XEXP (setsrc
, 0), newdest
);
3843 SUBST (XEXP (setsrc
, 1), newdest
);
3846 /* Split "((X op X) op Y) op Y)" as "T op T" where
3848 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3850 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3851 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3852 SUBST (XEXP (setsrc
, 0), newdest
);
3853 SUBST (XEXP (setsrc
, 1), newdest
);
3861 newi2pat
= gen_rtx_SET (newdest
, *split
);
3862 SUBST (*split
, newdest
);
3865 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3867 /* recog_for_combine might have added CLOBBERs to newi2pat.
3868 Make sure NEWPAT does not depend on the clobbered regs. */
3869 if (GET_CODE (newi2pat
) == PARALLEL
)
3870 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3871 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3873 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3874 if (reg_overlap_mentioned_p (reg
, newpat
))
3881 /* If the split point was a MULT and we didn't have one before,
3882 don't use one now. */
3883 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3884 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3888 /* Check for a case where we loaded from memory in a narrow mode and
3889 then sign extended it, but we need both registers. In that case,
3890 we have a PARALLEL with both loads from the same memory location.
3891 We can split this into a load from memory followed by a register-register
3892 copy. This saves at least one insn, more if register allocation can
3895 We cannot do this if the destination of the first assignment is a
3896 condition code register. We eliminate this case by making sure
3897 the SET_DEST and SET_SRC have the same mode.
3899 We cannot do this if the destination of the second assignment is
3900 a register that we have already assumed is zero-extended. Similarly
3901 for a SUBREG of such a register. */
3903 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3904 && GET_CODE (newpat
) == PARALLEL
3905 && XVECLEN (newpat
, 0) == 2
3906 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3907 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3908 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3909 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3910 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3911 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3912 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3913 && !modified_between_p (SET_SRC (XVECEXP (newpat
, 0, 1)), i2
, i3
)
3914 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3915 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3916 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3918 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3919 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3921 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3923 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3924 != GET_MODE_MASK (word_mode
))))
3925 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3926 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3928 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3929 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3931 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3933 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3934 != GET_MODE_MASK (word_mode
)))))
3935 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3936 SET_SRC (XVECEXP (newpat
, 0, 1)))
3937 && ! find_reg_note (i3
, REG_UNUSED
,
3938 SET_DEST (XVECEXP (newpat
, 0, 0))))
3942 newi2pat
= XVECEXP (newpat
, 0, 0);
3943 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3944 newpat
= XVECEXP (newpat
, 0, 1);
3945 SUBST (SET_SRC (newpat
),
3946 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3947 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3949 if (i2_code_number
>= 0)
3950 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3952 if (insn_code_number
>= 0)
3956 /* Similarly, check for a case where we have a PARALLEL of two independent
3957 SETs but we started with three insns. In this case, we can do the sets
3958 as two separate insns. This case occurs when some SET allows two
3959 other insns to combine, but the destination of that SET is still live.
3961 Also do this if we started with two insns and (at least) one of the
3962 resulting sets is a noop; this noop will be deleted later.
3964 Also do this if we started with two insns neither of which was a simple
3967 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3968 && GET_CODE (newpat
) == PARALLEL
3969 && XVECLEN (newpat
, 0) == 2
3970 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3971 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3973 || set_noop_p (XVECEXP (newpat
, 0, 0))
3974 || set_noop_p (XVECEXP (newpat
, 0, 1))
3975 || (!i2_was_move
&& !i3_was_move
))
3976 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3977 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3978 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3979 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3980 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3981 XVECEXP (newpat
, 0, 0))
3982 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3983 XVECEXP (newpat
, 0, 1))
3984 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3985 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3987 rtx set0
= XVECEXP (newpat
, 0, 0);
3988 rtx set1
= XVECEXP (newpat
, 0, 1);
3990 /* Normally, it doesn't matter which of the two is done first, but
3991 one which uses any regs/memory set in between i2 and i3 can't
3992 be first. The PARALLEL might also have been pre-existing in i3,
3993 so we need to make sure that we won't wrongly hoist a SET to i2
3994 that would conflict with a death note present in there, or would
3995 have its dest modified between i2 and i3. */
3996 if (!modified_between_p (SET_SRC (set1
), i2
, i3
)
3997 && !(REG_P (SET_DEST (set1
))
3998 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3999 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
4000 && find_reg_note (i2
, REG_DEAD
,
4001 SUBREG_REG (SET_DEST (set1
))))
4002 && !modified_between_p (SET_DEST (set1
), i2
, i3
)
4003 /* If I3 is a jump, ensure that set0 is a jump so that
4004 we do not create invalid RTL. */
4005 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
4011 else if (!modified_between_p (SET_SRC (set0
), i2
, i3
)
4012 && !(REG_P (SET_DEST (set0
))
4013 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
4014 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
4015 && find_reg_note (i2
, REG_DEAD
,
4016 SUBREG_REG (SET_DEST (set0
))))
4017 && !modified_between_p (SET_DEST (set0
), i2
, i3
)
4018 /* If I3 is a jump, ensure that set1 is a jump so that
4019 we do not create invalid RTL. */
4020 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
4032 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4034 if (i2_code_number
>= 0)
4036 /* recog_for_combine might have added CLOBBERs to newi2pat.
4037 Make sure NEWPAT does not depend on the clobbered regs. */
4038 if (GET_CODE (newi2pat
) == PARALLEL
)
4040 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4041 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4043 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4044 if (reg_overlap_mentioned_p (reg
, newpat
))
4052 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4054 /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4055 Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4056 mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4057 if (insn_code_number
>= 0 && GET_CODE (newpat
) == PARALLEL
)
4059 for (i
= XVECLEN (newpat
, 0) - 1; i
>= 0; i
--)
4060 if (GET_CODE (XVECEXP (newpat
, 0, i
)) == CLOBBER
)
4062 rtx reg
= XEXP (XVECEXP (newpat
, 0, i
), 0);
4063 if (reg_overlap_mentioned_p (reg
, SET_DEST (set0
))
4064 || reg_overlap_mentioned_p (reg
, SET_DEST (set1
)))
4072 if (insn_code_number
>= 0)
4077 /* If it still isn't recognized, fail and change things back the way they
4079 if ((insn_code_number
< 0
4080 /* Is the result a reasonable ASM_OPERANDS? */
4081 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4087 /* If we had to change another insn, make sure it is valid also. */
4088 if (undobuf
.other_insn
)
4090 CLEAR_HARD_REG_SET (newpat_used_regs
);
4092 other_pat
= PATTERN (undobuf
.other_insn
);
4093 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4096 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4103 /* Only allow this combination if insn_cost reports that the
4104 replacement instructions are cheaper than the originals. */
4105 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4111 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4115 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4116 if (undo
->kind
== UNDO_MODE
)
4118 rtx reg
= regno_reg_rtx
[undo
->where
.regno
];
4119 machine_mode new_mode
= GET_MODE (reg
);
4120 machine_mode old_mode
= undo
->old_contents
.m
;
4122 /* Temporarily revert mode back. */
4123 adjust_reg_mode (reg
, old_mode
);
4125 if (reg
== i2dest
&& i2scratch
)
4127 /* If we used i2dest as a scratch register with a
4128 different mode, substitute it for the original
4129 i2src while its original mode is temporarily
4130 restored, and then clear i2scratch so that we don't
4131 do it again later. */
4132 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4135 /* Put back the new mode. */
4136 adjust_reg_mode (reg
, new_mode
);
4140 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4141 rtx_insn
*first
, *last
;
4146 last
= last_combined_insn
;
4151 last
= undobuf
.other_insn
;
4153 if (DF_INSN_LUID (last
)
4154 < DF_INSN_LUID (last_combined_insn
))
4155 last
= last_combined_insn
;
4158 /* We're dealing with a reg that changed mode but not
4159 meaning, so we want to turn it into a subreg for
4160 the new mode. However, because of REG sharing and
4161 because its mode had already changed, we have to do
4162 it in two steps. First, replace any debug uses of
4163 reg, with its original mode temporarily restored,
4164 with this copy we have created; then, replace the
4165 copy with the SUBREG of the original shared reg,
4166 once again changed to the new mode. */
4167 propagate_for_debug (first
, last
, reg
, tempreg
,
4169 adjust_reg_mode (reg
, new_mode
);
4170 propagate_for_debug (first
, last
, tempreg
,
4171 lowpart_subreg (old_mode
, reg
, new_mode
),
4177 /* If we will be able to accept this, we have made a
4178 change to the destination of I3. This requires us to
4179 do a few adjustments. */
4181 if (changed_i3_dest
)
4183 PATTERN (i3
) = newpat
;
4184 adjust_for_new_dest (i3
);
4187 /* We now know that we can do this combination. Merge the insns and
4188 update the status of registers and LOG_LINKS. */
4190 if (undobuf
.other_insn
)
4194 PATTERN (undobuf
.other_insn
) = other_pat
;
4196 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4197 ensure that they are still valid. Then add any non-duplicate
4198 notes added by recog_for_combine. */
4199 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4201 next
= XEXP (note
, 1);
4203 if ((REG_NOTE_KIND (note
) == REG_DEAD
4204 && !reg_referenced_p (XEXP (note
, 0),
4205 PATTERN (undobuf
.other_insn
)))
4206 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4207 && !reg_set_p (XEXP (note
, 0),
4208 PATTERN (undobuf
.other_insn
)))
4209 /* Simply drop equal note since it may be no longer valid
4210 for other_insn. It may be possible to record that CC
4211 register is changed and only discard those notes, but
4212 in practice it's unnecessary complication and doesn't
4213 give any meaningful improvement.
4216 || REG_NOTE_KIND (note
) == REG_EQUAL
4217 || REG_NOTE_KIND (note
) == REG_EQUIV
)
4218 remove_note (undobuf
.other_insn
, note
);
4221 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4222 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4228 /* I3 now uses what used to be its destination and which is now
4229 I2's destination. This requires us to do a few adjustments. */
4230 PATTERN (i3
) = newpat
;
4231 adjust_for_new_dest (i3
);
4234 if (swap_i2i3
|| split_i2i3
)
4236 /* We might need a LOG_LINK from I3 to I2. But then we used to
4237 have one, so we still will.
4239 However, some later insn might be using I2's dest and have
4240 a LOG_LINK pointing at I3. We should change it to point at
4243 /* newi2pat is usually a SET here; however, recog_for_combine might
4244 have added some clobbers. */
4246 if (GET_CODE (x
) == PARALLEL
)
4247 x
= XVECEXP (newi2pat
, 0, 0);
4249 if (REG_P (SET_DEST (x
))
4250 || (GET_CODE (SET_DEST (x
)) == SUBREG
4251 && REG_P (SUBREG_REG (SET_DEST (x
)))))
4253 unsigned int regno
= reg_or_subregno (SET_DEST (x
));
4256 for (rtx_insn
*insn
= NEXT_INSN (i3
);
4260 && BLOCK_FOR_INSN (insn
) == this_basic_block
;
4261 insn
= NEXT_INSN (insn
))
4263 if (DEBUG_INSN_P (insn
))
4265 struct insn_link
*link
;
4266 FOR_EACH_LOG_LINK (link
, insn
)
4267 if (link
->insn
== i3
&& link
->regno
== regno
)
4278 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4279 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4282 /* Compute which registers we expect to eliminate. newi2pat may be setting
4283 either i3dest or i2dest, so we must check it. */
4284 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4285 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4288 /* For i1, we need to compute both local elimination and global
4289 elimination information with respect to newi2pat because i1dest
4290 may be the same as i3dest, in which case newi2pat may be setting
4291 i1dest. Global information is used when distributing REG_DEAD
4292 note for i2 and i3, in which case it does matter if newi2pat sets
4295 Local information is used when distributing REG_DEAD note for i1,
4296 in which case it doesn't matter if newi2pat sets i1dest or not.
4297 See PR62151, if we have four insns combination:
4299 i1: r1 <- i1src (using r0)
4301 i2: r0 <- i2src (using r1)
4302 i3: r3 <- i3src (using r0)
4304 From i1's point of view, r0 is eliminated, no matter if it is set
4305 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4306 should be discarded.
4308 Note local information only affects cases in forms like "I1->I2->I3",
4309 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4310 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4312 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4315 rtx elim_i1
= (local_elim_i1
== 0
4316 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4318 /* Same case as i1. */
4319 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4321 rtx elim_i0
= (local_elim_i0
== 0
4322 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4325 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4327 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4328 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4330 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4332 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4334 /* Ensure that we do not have something that should not be shared but
4335 occurs multiple times in the new insns. Check this by first
4336 resetting all the `used' flags and then copying anything is shared. */
4338 reset_used_flags (i3notes
);
4339 reset_used_flags (i2notes
);
4340 reset_used_flags (i1notes
);
4341 reset_used_flags (i0notes
);
4342 reset_used_flags (newpat
);
4343 reset_used_flags (newi2pat
);
4344 if (undobuf
.other_insn
)
4345 reset_used_flags (PATTERN (undobuf
.other_insn
));
4347 i3notes
= copy_rtx_if_shared (i3notes
);
4348 i2notes
= copy_rtx_if_shared (i2notes
);
4349 i1notes
= copy_rtx_if_shared (i1notes
);
4350 i0notes
= copy_rtx_if_shared (i0notes
);
4351 newpat
= copy_rtx_if_shared (newpat
);
4352 newi2pat
= copy_rtx_if_shared (newi2pat
);
4353 if (undobuf
.other_insn
)
4354 reset_used_flags (PATTERN (undobuf
.other_insn
));
4356 INSN_CODE (i3
) = insn_code_number
;
4357 PATTERN (i3
) = newpat
;
4359 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4361 for (rtx link
= CALL_INSN_FUNCTION_USAGE (i3
); link
;
4362 link
= XEXP (link
, 1))
4366 /* I2SRC must still be meaningful at this point. Some
4367 splitting operations can invalidate I2SRC, but those
4368 operations do not apply to calls. */
4370 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4374 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4377 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4382 if (undobuf
.other_insn
)
4383 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4385 /* We had one special case above where I2 had more than one set and
4386 we replaced a destination of one of those sets with the destination
4387 of I3. In that case, we have to update LOG_LINKS of insns later
4388 in this basic block. Note that this (expensive) case is rare.
4390 Also, in this case, we must pretend that all REG_NOTEs for I2
4391 actually came from I3, so that REG_UNUSED notes from I2 will be
4392 properly handled. */
4394 if (i3_subst_into_i2
)
4396 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4397 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4398 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4399 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4400 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4401 && ! find_reg_note (i2
, REG_UNUSED
,
4402 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4403 for (temp_insn
= NEXT_INSN (i2
);
4405 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4406 || BB_HEAD (this_basic_block
) != temp_insn
);
4407 temp_insn
= NEXT_INSN (temp_insn
))
4408 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4409 FOR_EACH_LOG_LINK (link
, temp_insn
)
4410 if (link
->insn
== i2
)
4416 while (XEXP (link
, 1))
4417 link
= XEXP (link
, 1);
4418 XEXP (link
, 1) = i2notes
;
4425 LOG_LINKS (i3
) = NULL
;
4427 LOG_LINKS (i2
) = NULL
;
4432 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2scratch
)
4433 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4435 INSN_CODE (i2
) = i2_code_number
;
4436 PATTERN (i2
) = newi2pat
;
4440 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2src
)
4441 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4443 SET_INSN_DELETED (i2
);
4448 LOG_LINKS (i1
) = NULL
;
4450 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4451 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4453 SET_INSN_DELETED (i1
);
4458 LOG_LINKS (i0
) = NULL
;
4460 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4461 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4463 SET_INSN_DELETED (i0
);
4466 /* Get death notes for everything that is now used in either I3 or
4467 I2 and used to die in a previous insn. If we built two new
4468 patterns, move from I1 to I2 then I2 to I3 so that we get the
4469 proper movement on registers that I2 modifies. */
4472 from_luid
= DF_INSN_LUID (i0
);
4474 from_luid
= DF_INSN_LUID (i1
);
4476 from_luid
= DF_INSN_LUID (i2
);
4478 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4479 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4481 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4483 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4484 elim_i2
, elim_i1
, elim_i0
);
4486 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4487 elim_i2
, elim_i1
, elim_i0
);
4489 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4490 elim_i2
, local_elim_i1
, local_elim_i0
);
4492 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4493 elim_i2
, elim_i1
, local_elim_i0
);
4495 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4496 elim_i2
, elim_i1
, elim_i0
);
4498 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4499 know these are REG_UNUSED and want them to go to the desired insn,
4500 so we always pass it as i3. */
4502 if (newi2pat
&& new_i2_notes
)
4503 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4507 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4510 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4511 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4512 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4513 in that case, it might delete I2. Similarly for I2 and I1.
4514 Show an additional death due to the REG_DEAD note we make here. If
4515 we discard it in distribute_notes, we will decrement it again. */
4519 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4520 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4521 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4524 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4525 elim_i2
, elim_i1
, elim_i0
);
4528 if (i2dest_in_i2src
)
4530 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4531 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4532 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4533 NULL_RTX
, NULL_RTX
);
4535 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4536 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4539 if (i1dest_in_i1src
)
4541 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4542 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4543 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4544 NULL_RTX
, NULL_RTX
);
4546 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4547 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4550 if (i0dest_in_i0src
)
4552 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4553 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4554 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4555 NULL_RTX
, NULL_RTX
);
4557 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4558 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4561 distribute_links (i3links
);
4562 distribute_links (i2links
);
4563 distribute_links (i1links
);
4564 distribute_links (i0links
);
4568 struct insn_link
*link
;
4569 rtx_insn
*i2_insn
= 0;
4570 rtx i2_val
= 0, set
;
4572 /* The insn that used to set this register doesn't exist, and
4573 this life of the register may not exist either. See if one of
4574 I3's links points to an insn that sets I2DEST. If it does,
4575 that is now the last known value for I2DEST. If we don't update
4576 this and I2 set the register to a value that depended on its old
4577 contents, we will get confused. If this insn is used, thing
4578 will be set correctly in combine_instructions. */
4579 FOR_EACH_LOG_LINK (link
, i3
)
4580 if ((set
= single_set (link
->insn
)) != 0
4581 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4582 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4584 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4586 /* If the reg formerly set in I2 died only once and that was in I3,
4587 zero its use count so it won't make `reload' do any work. */
4589 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4590 && ! i2dest_in_i2src
4591 && REGNO (i2dest
) < reg_n_sets_max
)
4592 INC_REG_N_SETS (REGNO (i2dest
), -1);
4595 if (i1
&& REG_P (i1dest
))
4597 struct insn_link
*link
;
4598 rtx_insn
*i1_insn
= 0;
4599 rtx i1_val
= 0, set
;
4601 FOR_EACH_LOG_LINK (link
, i3
)
4602 if ((set
= single_set (link
->insn
)) != 0
4603 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4604 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4606 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4609 && ! i1dest_in_i1src
4610 && REGNO (i1dest
) < reg_n_sets_max
)
4611 INC_REG_N_SETS (REGNO (i1dest
), -1);
4614 if (i0
&& REG_P (i0dest
))
4616 struct insn_link
*link
;
4617 rtx_insn
*i0_insn
= 0;
4618 rtx i0_val
= 0, set
;
4620 FOR_EACH_LOG_LINK (link
, i3
)
4621 if ((set
= single_set (link
->insn
)) != 0
4622 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4623 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4625 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4628 && ! i0dest_in_i0src
4629 && REGNO (i0dest
) < reg_n_sets_max
)
4630 INC_REG_N_SETS (REGNO (i0dest
), -1);
4633 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4634 been made to this insn. The order is important, because newi2pat
4635 can affect nonzero_bits of newpat. */
4637 note_pattern_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4638 note_pattern_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4641 if (undobuf
.other_insn
!= NULL_RTX
)
4645 fprintf (dump_file
, "modifying other_insn ");
4646 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4648 df_insn_rescan (undobuf
.other_insn
);
4651 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4655 fprintf (dump_file
, "modifying insn i0 ");
4656 dump_insn_slim (dump_file
, i0
);
4658 df_insn_rescan (i0
);
4661 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4665 fprintf (dump_file
, "modifying insn i1 ");
4666 dump_insn_slim (dump_file
, i1
);
4668 df_insn_rescan (i1
);
4671 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4675 fprintf (dump_file
, "modifying insn i2 ");
4676 dump_insn_slim (dump_file
, i2
);
4678 df_insn_rescan (i2
);
4681 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4685 fprintf (dump_file
, "modifying insn i3 ");
4686 dump_insn_slim (dump_file
, i3
);
4688 df_insn_rescan (i3
);
4691 /* Set new_direct_jump_p if a new return or simple jump instruction
4692 has been created. Adjust the CFG accordingly. */
4693 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4695 *new_direct_jump_p
= 1;
4696 mark_jump_label (PATTERN (i3
), i3
, 0);
4697 update_cfg_for_uncondjump (i3
);
4700 if (undobuf
.other_insn
!= NULL_RTX
4701 && (returnjump_p (undobuf
.other_insn
)
4702 || any_uncondjump_p (undobuf
.other_insn
)))
4704 *new_direct_jump_p
= 1;
4705 update_cfg_for_uncondjump (undobuf
.other_insn
);
4708 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4709 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4711 basic_block bb
= BLOCK_FOR_INSN (i3
);
4713 remove_edge (split_block (bb
, i3
));
4714 emit_barrier_after_bb (bb
);
4715 *new_direct_jump_p
= 1;
4718 if (undobuf
.other_insn
4719 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4720 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4722 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4724 remove_edge (split_block (bb
, undobuf
.other_insn
));
4725 emit_barrier_after_bb (bb
);
4726 *new_direct_jump_p
= 1;
4729 /* A noop might also need cleaning up of CFG, if it comes from the
4730 simplification of a jump. */
4732 && GET_CODE (newpat
) == SET
4733 && SET_SRC (newpat
) == pc_rtx
4734 && SET_DEST (newpat
) == pc_rtx
)
4736 *new_direct_jump_p
= 1;
4737 update_cfg_for_uncondjump (i3
);
4740 if (undobuf
.other_insn
!= NULL_RTX
4741 && JUMP_P (undobuf
.other_insn
)
4742 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4743 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4744 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4746 *new_direct_jump_p
= 1;
4747 update_cfg_for_uncondjump (undobuf
.other_insn
);
4750 combine_successes
++;
4753 rtx_insn
*ret
= newi2pat
? i2
: i3
;
4754 if (added_links_insn
&& DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (ret
))
4755 ret
= added_links_insn
;
4756 if (added_notes_insn
&& DF_INSN_LUID (added_notes_insn
) < DF_INSN_LUID (ret
))
4757 ret
= added_notes_insn
;
4762 /* Get a marker for undoing to the current state. */
4765 get_undo_marker (void)
4767 return undobuf
.undos
;
4770 /* Undo the modifications up to the marker. */
4773 undo_to_marker (void *marker
)
4775 struct undo
*undo
, *next
;
4777 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4785 *undo
->where
.r
= undo
->old_contents
.r
;
4788 *undo
->where
.i
= undo
->old_contents
.i
;
4791 adjust_reg_mode (regno_reg_rtx
[undo
->where
.regno
],
4792 undo
->old_contents
.m
);
4795 *undo
->where
.l
= undo
->old_contents
.l
;
4801 undo
->next
= undobuf
.frees
;
4802 undobuf
.frees
= undo
;
4805 undobuf
.undos
= (struct undo
*) marker
;
4808 /* Undo all the modifications recorded in undobuf. */
4816 /* We've committed to accepting the changes we made. Move all
4817 of the undos to the free list. */
4822 struct undo
*undo
, *next
;
4824 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4827 undo
->next
= undobuf
.frees
;
4828 undobuf
.frees
= undo
;
4833 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4834 where we have an arithmetic expression and return that point. LOC will
4837 try_combine will call this function to see if an insn can be split into
4841 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4844 enum rtx_code code
= GET_CODE (x
);
4846 unsigned HOST_WIDE_INT len
= 0;
4847 HOST_WIDE_INT pos
= 0;
4849 rtx inner
= NULL_RTX
;
4850 scalar_int_mode mode
, inner_mode
;
4852 /* First special-case some codes. */
4856 #ifdef INSN_SCHEDULING
4857 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4859 if (MEM_P (SUBREG_REG (x
)))
4862 return find_split_point (&SUBREG_REG (x
), insn
, false);
4865 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4866 using LO_SUM and HIGH. */
4867 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4868 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4870 machine_mode address_mode
= get_address_mode (x
);
4873 gen_rtx_LO_SUM (address_mode
,
4874 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4876 return &XEXP (XEXP (x
, 0), 0);
4879 /* If we have a PLUS whose second operand is a constant and the
4880 address is not valid, perhaps we can split it up using
4881 the machine-specific way to split large constants. We use
4882 the first pseudo-reg (one of the virtual regs) as a placeholder;
4883 it will not remain in the result. */
4884 if (GET_CODE (XEXP (x
, 0)) == PLUS
4885 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4886 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4887 MEM_ADDR_SPACE (x
)))
4889 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4890 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4893 /* This should have produced two insns, each of which sets our
4894 placeholder. If the source of the second is a valid address,
4895 we can put both sources together and make a split point
4899 && NEXT_INSN (seq
) != NULL_RTX
4900 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4901 && NONJUMP_INSN_P (seq
)
4902 && GET_CODE (PATTERN (seq
)) == SET
4903 && SET_DEST (PATTERN (seq
)) == reg
4904 && ! reg_mentioned_p (reg
,
4905 SET_SRC (PATTERN (seq
)))
4906 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4907 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4908 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4909 && memory_address_addr_space_p
4910 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4911 MEM_ADDR_SPACE (x
)))
4913 rtx src1
= SET_SRC (PATTERN (seq
));
4914 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4916 /* Replace the placeholder in SRC2 with SRC1. If we can
4917 find where in SRC2 it was placed, that can become our
4918 split point and we can replace this address with SRC2.
4919 Just try two obvious places. */
4921 src2
= replace_rtx (src2
, reg
, src1
);
4923 if (XEXP (src2
, 0) == src1
)
4924 split
= &XEXP (src2
, 0);
4925 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4926 && XEXP (XEXP (src2
, 0), 0) == src1
)
4927 split
= &XEXP (XEXP (src2
, 0), 0);
4931 SUBST (XEXP (x
, 0), src2
);
4936 /* If that didn't work and we have a nested plus, like:
4937 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4938 is valid address, try to split (REG1 * CONST1). */
4939 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
4940 && !OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4941 && OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4942 && ! (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SUBREG
4943 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x
, 0),
4946 rtx tem
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4947 XEXP (XEXP (XEXP (x
, 0), 0), 0) = reg
;
4948 if (memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4949 MEM_ADDR_SPACE (x
)))
4951 XEXP (XEXP (XEXP (x
, 0), 0), 0) = tem
;
4952 return &XEXP (XEXP (XEXP (x
, 0), 0), 0);
4954 XEXP (XEXP (XEXP (x
, 0), 0), 0) = tem
;
4956 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
4957 && OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4958 && !OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4959 && ! (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == SUBREG
4960 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x
, 0),
4963 rtx tem
= XEXP (XEXP (XEXP (x
, 0), 0), 1);
4964 XEXP (XEXP (XEXP (x
, 0), 0), 1) = reg
;
4965 if (memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4966 MEM_ADDR_SPACE (x
)))
4968 XEXP (XEXP (XEXP (x
, 0), 0), 1) = tem
;
4969 return &XEXP (XEXP (XEXP (x
, 0), 0), 1);
4971 XEXP (XEXP (XEXP (x
, 0), 0), 1) = tem
;
4974 /* If that didn't work, perhaps the first operand is complex and
4975 needs to be computed separately, so make a split point there.
4976 This will occur on machines that just support REG + CONST
4977 and have a constant moved through some previous computation. */
4978 if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4979 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4980 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4981 return &XEXP (XEXP (x
, 0), 0);
4984 /* If we have a PLUS whose first operand is complex, try computing it
4985 separately by making a split there. */
4986 if (GET_CODE (XEXP (x
, 0)) == PLUS
4987 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4989 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4990 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4991 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4992 return &XEXP (XEXP (x
, 0), 0);
4996 /* See if we can split SET_SRC as it stands. */
4997 split
= find_split_point (&SET_SRC (x
), insn
, true);
4998 if (split
&& split
!= &SET_SRC (x
))
5001 /* See if we can split SET_DEST as it stands. */
5002 split
= find_split_point (&SET_DEST (x
), insn
, false);
5003 if (split
&& split
!= &SET_DEST (x
))
5006 /* See if this is a bitfield assignment with everything constant. If
5007 so, this is an IOR of an AND, so split it into that. */
5008 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5009 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_DEST (x
), 0)),
5011 && HWI_COMPUTABLE_MODE_P (inner_mode
)
5012 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
5013 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
5014 && CONST_INT_P (SET_SRC (x
))
5015 && ((INTVAL (XEXP (SET_DEST (x
), 1))
5016 + INTVAL (XEXP (SET_DEST (x
), 2)))
5017 <= GET_MODE_PRECISION (inner_mode
))
5018 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
5020 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
5021 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
5022 rtx dest
= XEXP (SET_DEST (x
), 0);
5023 unsigned HOST_WIDE_INT mask
= (HOST_WIDE_INT_1U
<< len
) - 1;
5024 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
)) & mask
;
5027 if (BITS_BIG_ENDIAN
)
5028 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5030 or_mask
= gen_int_mode (src
<< pos
, inner_mode
);
5033 simplify_gen_binary (IOR
, inner_mode
, dest
, or_mask
));
5036 rtx negmask
= gen_int_mode (~(mask
<< pos
), inner_mode
);
5038 simplify_gen_binary (IOR
, inner_mode
,
5039 simplify_gen_binary (AND
, inner_mode
,
5044 SUBST (SET_DEST (x
), dest
);
5046 split
= find_split_point (&SET_SRC (x
), insn
, true);
5047 if (split
&& split
!= &SET_SRC (x
))
5051 /* Otherwise, see if this is an operation that we can split into two.
5052 If so, try to split that. */
5053 code
= GET_CODE (SET_SRC (x
));
5058 /* If we are AND'ing with a large constant that is only a single
5059 bit and the result is only being used in a context where we
5060 need to know if it is zero or nonzero, replace it with a bit
5061 extraction. This will avoid the large constant, which might
5062 have taken more than one insn to make. If the constant were
5063 not a valid argument to the AND but took only one insn to make,
5064 this is no worse, but if it took more than one insn, it will
5067 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5068 && REG_P (XEXP (SET_SRC (x
), 0))
5069 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
5070 && REG_P (SET_DEST (x
))
5071 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
5072 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
5073 && XEXP (*split
, 0) == SET_DEST (x
)
5074 && XEXP (*split
, 1) == const0_rtx
)
5076 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
5077 XEXP (SET_SRC (x
), 0),
5078 pos
, NULL_RTX
, 1, 1, 0, 0);
5079 if (extraction
!= 0)
5081 SUBST (SET_SRC (x
), extraction
);
5082 return find_split_point (loc
, insn
, false);
5088 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5089 is known to be on, this can be converted into a NEG of a shift. */
5090 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
5091 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
5092 && ((pos
= exact_log2 (nonzero_bits (XEXP (SET_SRC (x
), 0),
5093 GET_MODE (XEXP (SET_SRC (x
),
5096 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
5097 rtx pos_rtx
= gen_int_shift_amount (mode
, pos
);
5100 gen_rtx_LSHIFTRT (mode
,
5101 XEXP (SET_SRC (x
), 0),
5104 split
= find_split_point (&SET_SRC (x
), insn
, true);
5105 if (split
&& split
!= &SET_SRC (x
))
5111 inner
= XEXP (SET_SRC (x
), 0);
5113 /* We can't optimize if either mode is a partial integer
5114 mode as we don't know how many bits are significant
5116 if (!is_int_mode (GET_MODE (inner
), &inner_mode
)
5117 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5121 len
= GET_MODE_PRECISION (inner_mode
);
5127 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_SRC (x
), 0)),
5129 && CONST_INT_P (XEXP (SET_SRC (x
), 1))
5130 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5132 inner
= XEXP (SET_SRC (x
), 0);
5133 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5134 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5136 if (BITS_BIG_ENDIAN
)
5137 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5138 unsignedp
= (code
== ZERO_EXTRACT
);
5147 && known_subrange_p (pos
, len
,
5148 0, GET_MODE_PRECISION (GET_MODE (inner
)))
5149 && is_a
<scalar_int_mode
> (GET_MODE (SET_SRC (x
)), &mode
))
5151 /* For unsigned, we have a choice of a shift followed by an
5152 AND or two shifts. Use two shifts for field sizes where the
5153 constant might be too large. We assume here that we can
5154 always at least get 8-bit constants in an AND insn, which is
5155 true for every current RISC. */
5157 if (unsignedp
&& len
<= 8)
5159 unsigned HOST_WIDE_INT mask
5160 = (HOST_WIDE_INT_1U
<< len
) - 1;
5161 rtx pos_rtx
= gen_int_shift_amount (mode
, pos
);
5165 (mode
, gen_lowpart (mode
, inner
), pos_rtx
),
5166 gen_int_mode (mask
, mode
)));
5168 split
= find_split_point (&SET_SRC (x
), insn
, true);
5169 if (split
&& split
!= &SET_SRC (x
))
5174 int left_bits
= GET_MODE_PRECISION (mode
) - len
- pos
;
5175 int right_bits
= GET_MODE_PRECISION (mode
) - len
;
5178 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5179 gen_rtx_ASHIFT (mode
,
5180 gen_lowpart (mode
, inner
),
5181 gen_int_shift_amount (mode
, left_bits
)),
5182 gen_int_shift_amount (mode
, right_bits
)));
5184 split
= find_split_point (&SET_SRC (x
), insn
, true);
5185 if (split
&& split
!= &SET_SRC (x
))
5190 /* See if this is a simple operation with a constant as the second
5191 operand. It might be that this constant is out of range and hence
5192 could be used as a split point. */
5193 if (BINARY_P (SET_SRC (x
))
5194 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5195 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5196 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5197 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5198 return &XEXP (SET_SRC (x
), 1);
5200 /* Finally, see if this is a simple operation with its first operand
5201 not in a register. The operation might require this operand in a
5202 register, so return it as a split point. We can always do this
5203 because if the first operand were another operation, we would have
5204 already found it as a split point. */
5205 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5206 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5207 return &XEXP (SET_SRC (x
), 0);
5213 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5214 it is better to write this as (not (ior A B)) so we can split it.
5215 Similarly for IOR. */
5216 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5219 gen_rtx_NOT (GET_MODE (x
),
5220 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5222 XEXP (XEXP (x
, 0), 0),
5223 XEXP (XEXP (x
, 1), 0))));
5224 return find_split_point (loc
, insn
, set_src
);
5227 /* Many RISC machines have a large set of logical insns. If the
5228 second operand is a NOT, put it first so we will try to split the
5229 other operand first. */
5230 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5232 rtx tem
= XEXP (x
, 0);
5233 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5234 SUBST (XEXP (x
, 1), tem
);
5240 /* Canonicalization can produce (minus A (mult B C)), where C is a
5241 constant. It may be better to try splitting (plus (mult B -C) A)
5242 instead if this isn't a multiply by a power of two. */
5243 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5244 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5245 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5247 machine_mode mode
= GET_MODE (x
);
5248 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5249 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5250 SUBST (*loc
, gen_rtx_PLUS (mode
,
5252 XEXP (XEXP (x
, 1), 0),
5253 gen_int_mode (other_int
,
5256 return find_split_point (loc
, insn
, set_src
);
5259 /* Split at a multiply-accumulate instruction. However if this is
5260 the SET_SRC, we likely do not have such an instruction and it's
5261 worthless to try this split. */
5263 && (GET_CODE (XEXP (x
, 0)) == MULT
5264 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5265 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5272 /* Otherwise, select our actions depending on our rtx class. */
5273 switch (GET_RTX_CLASS (code
))
5275 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5277 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5282 case RTX_COMM_ARITH
:
5284 case RTX_COMM_COMPARE
:
5285 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5290 /* Some machines have (and (shift ...) ...) insns. If X is not
5291 an AND, but XEXP (X, 0) is, use it as our split point. */
5292 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5293 return &XEXP (x
, 0);
5295 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5301 /* Otherwise, we don't have a split point. */
5306 /* Throughout X, replace FROM with TO, and return the result.
5307 The result is TO if X is FROM;
5308 otherwise the result is X, but its contents may have been modified.
5309 If they were modified, a record was made in undobuf so that
5310 undo_all will (among other things) return X to its original state.
5312 If the number of changes necessary is too much to record to undo,
5313 the excess changes are not made, so the result is invalid.
5314 The changes already made can still be undone.
5315 undobuf.num_undo is incremented for such changes, so by testing that
5316 the caller can tell whether the result is valid.
5318 `n_occurrences' is incremented each time FROM is replaced.
5320 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5322 IN_COND is nonzero if we are at the top level of a condition.
5324 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5325 by copying if `n_occurrences' is nonzero. */
5328 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5330 enum rtx_code code
= GET_CODE (x
);
5331 machine_mode op0_mode
= VOIDmode
;
5336 /* Two expressions are equal if they are identical copies of a shared
5337 RTX or if they are both registers with the same register number
5340 #define COMBINE_RTX_EQUAL_P(X,Y) \
5342 || (REG_P (X) && REG_P (Y) \
5343 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5345 /* Do not substitute into clobbers of regs -- this will never result in
5347 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5350 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5353 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5356 /* If X and FROM are the same register but different modes, they
5357 will not have been seen as equal above. However, the log links code
5358 will make a LOG_LINKS entry for that case. If we do nothing, we
5359 will try to rerecognize our original insn and, when it succeeds,
5360 we will delete the feeding insn, which is incorrect.
5362 So force this insn not to match in this (rare) case. */
5363 if (! in_dest
&& code
== REG
&& REG_P (from
)
5364 && reg_overlap_mentioned_p (x
, from
))
5365 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5367 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5368 of which may contain things that can be combined. */
5369 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5372 /* It is possible to have a subexpression appear twice in the insn.
5373 Suppose that FROM is a register that appears within TO.
5374 Then, after that subexpression has been scanned once by `subst',
5375 the second time it is scanned, TO may be found. If we were
5376 to scan TO here, we would find FROM within it and create a
5377 self-referent rtl structure which is completely wrong. */
5378 if (COMBINE_RTX_EQUAL_P (x
, to
))
5381 /* Parallel asm_operands need special attention because all of the
5382 inputs are shared across the arms. Furthermore, unsharing the
5383 rtl results in recognition failures. Failure to handle this case
5384 specially can result in circular rtl.
5386 Solve this by doing a normal pass across the first entry of the
5387 parallel, and only processing the SET_DESTs of the subsequent
5390 if (code
== PARALLEL
5391 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5392 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5394 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5396 /* If this substitution failed, this whole thing fails. */
5397 if (GET_CODE (new_rtx
) == CLOBBER
5398 && XEXP (new_rtx
, 0) == const0_rtx
)
5401 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5403 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5405 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5407 if (!REG_P (dest
) && GET_CODE (dest
) != PC
)
5409 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5411 /* If this substitution failed, this whole thing fails. */
5412 if (GET_CODE (new_rtx
) == CLOBBER
5413 && XEXP (new_rtx
, 0) == const0_rtx
)
5416 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5422 len
= GET_RTX_LENGTH (code
);
5423 fmt
= GET_RTX_FORMAT (code
);
5425 /* We don't need to process a SET_DEST that is a register or PC, so
5426 set up to skip this common case. All other cases where we want
5427 to suppress replacing something inside a SET_SRC are handled via
5428 the IN_DEST operand. */
5430 && (REG_P (SET_DEST (x
))
5431 || GET_CODE (SET_DEST (x
)) == PC
))
5434 /* Trying to simplify the operands of a widening MULT is not likely
5435 to create RTL matching a machine insn. */
5437 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5438 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5439 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5440 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5441 && REG_P (XEXP (XEXP (x
, 0), 0))
5442 && REG_P (XEXP (XEXP (x
, 1), 0))
5447 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5450 op0_mode
= GET_MODE (XEXP (x
, 0));
5452 for (i
= 0; i
< len
; i
++)
5457 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5459 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5461 new_rtx
= (unique_copy
&& n_occurrences
5462 ? copy_rtx (to
) : to
);
5467 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5470 /* If this substitution failed, this whole thing
5472 if (GET_CODE (new_rtx
) == CLOBBER
5473 && XEXP (new_rtx
, 0) == const0_rtx
)
5477 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5480 else if (fmt
[i
] == 'e')
5482 /* If this is a register being set, ignore it. */
5483 new_rtx
= XEXP (x
, i
);
5486 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5488 || code
== STRICT_LOW_PART
))
5491 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5493 /* In general, don't install a subreg involving two
5494 modes not tieable. It can worsen register
5495 allocation, and can even make invalid reload
5496 insns, since the reg inside may need to be copied
5497 from in the outside mode, and that may be invalid
5498 if it is an fp reg copied in integer mode.
5500 We allow an exception to this: It is valid if
5501 it is inside another SUBREG and the mode of that
5502 SUBREG and the mode of the inside of TO is
5505 if (GET_CODE (to
) == SUBREG
5506 && !targetm
.modes_tieable_p (GET_MODE (to
),
5507 GET_MODE (SUBREG_REG (to
)))
5508 && ! (code
== SUBREG
5509 && (targetm
.modes_tieable_p
5510 (GET_MODE (x
), GET_MODE (SUBREG_REG (to
))))))
5511 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5515 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5516 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5519 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5521 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5525 /* If we are in a SET_DEST, suppress most cases unless we
5526 have gone inside a MEM, in which case we want to
5527 simplify the address. We assume here that things that
5528 are actually part of the destination have their inner
5529 parts in the first expression. This is true for SUBREG,
5530 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5531 things aside from REG and MEM that should appear in a
5533 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5535 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5536 || code
== ZERO_EXTRACT
))
5539 code
== IF_THEN_ELSE
&& i
== 0,
5542 /* If we found that we will have to reject this combination,
5543 indicate that by returning the CLOBBER ourselves, rather than
5544 an expression containing it. This will speed things up as
5545 well as prevent accidents where two CLOBBERs are considered
5546 to be equal, thus producing an incorrect simplification. */
5548 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5551 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5553 machine_mode mode
= GET_MODE (x
);
5555 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5556 GET_MODE (SUBREG_REG (x
)),
5559 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5561 else if (CONST_SCALAR_INT_P (new_rtx
)
5562 && (GET_CODE (x
) == ZERO_EXTEND
5563 || GET_CODE (x
) == SIGN_EXTEND
5564 || GET_CODE (x
) == FLOAT
5565 || GET_CODE (x
) == UNSIGNED_FLOAT
))
5567 x
= simplify_unary_operation (GET_CODE (x
), GET_MODE (x
),
5569 GET_MODE (XEXP (x
, 0)));
5571 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5573 /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5574 etc. arguments, otherwise we can ICE before trying to recog
5575 it. See PR104446. */
5576 else if (CONST_SCALAR_INT_P (new_rtx
)
5577 && GET_RTX_CLASS (GET_CODE (x
)) == RTX_AUTOINC
)
5578 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5580 SUBST (XEXP (x
, i
), new_rtx
);
5585 /* Check if we are loading something from the constant pool via float
5586 extension; in this case we would undo compress_float_constant
5587 optimization and degenerate constant load to an immediate value. */
5588 if (GET_CODE (x
) == FLOAT_EXTEND
5589 && MEM_P (XEXP (x
, 0))
5590 && MEM_READONLY_P (XEXP (x
, 0)))
5592 rtx tmp
= avoid_constant_pool_reference (x
);
5597 /* Try to simplify X. If the simplification changed the code, it is likely
5598 that further simplification will help, so loop, but limit the number
5599 of repetitions that will be performed. */
5601 for (i
= 0; i
< 4; i
++)
5603 /* If X is sufficiently simple, don't bother trying to do anything
5605 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5606 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5608 if (GET_CODE (x
) == code
)
5611 code
= GET_CODE (x
);
5613 /* We no longer know the original mode of operand 0 since we
5614 have changed the form of X) */
5615 op0_mode
= VOIDmode
;
5621 /* If X is a commutative operation whose operands are not in the canonical
5622 order, use substitutions to swap them. */
5625 maybe_swap_commutative_operands (rtx x
)
5627 if (COMMUTATIVE_ARITH_P (x
)
5628 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5630 rtx temp
= XEXP (x
, 0);
5631 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5632 SUBST (XEXP (x
, 1), temp
);
5636 /* Simplify X, a piece of RTL. We just operate on the expression at the
5637 outer level; call `subst' to simplify recursively. Return the new
5640 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5641 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5645 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5648 enum rtx_code code
= GET_CODE (x
);
5649 machine_mode mode
= GET_MODE (x
);
5650 scalar_int_mode int_mode
;
5654 /* If this is a commutative operation, put a constant last and a complex
5655 expression first. We don't need to do this for comparisons here. */
5656 maybe_swap_commutative_operands (x
);
5658 /* Try to fold this expression in case we have constants that weren't
5661 switch (GET_RTX_CLASS (code
))
5664 if (op0_mode
== VOIDmode
)
5665 op0_mode
= GET_MODE (XEXP (x
, 0));
5666 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5669 case RTX_COMM_COMPARE
:
5671 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5672 if (cmp_mode
== VOIDmode
)
5674 cmp_mode
= GET_MODE (XEXP (x
, 1));
5675 if (cmp_mode
== VOIDmode
)
5676 cmp_mode
= op0_mode
;
5678 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5679 XEXP (x
, 0), XEXP (x
, 1));
5682 case RTX_COMM_ARITH
:
5684 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5686 case RTX_BITFIELD_OPS
:
5688 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5689 XEXP (x
, 1), XEXP (x
, 2));
5698 code
= GET_CODE (temp
);
5699 op0_mode
= VOIDmode
;
5700 mode
= GET_MODE (temp
);
5703 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5704 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5705 things. Check for cases where both arms are testing the same
5708 Don't do anything if all operands are very simple. */
5711 && ((!OBJECT_P (XEXP (x
, 0))
5712 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5713 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5714 || (!OBJECT_P (XEXP (x
, 1))
5715 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5716 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5718 && (!OBJECT_P (XEXP (x
, 0))
5719 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5720 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5722 rtx cond
, true_rtx
, false_rtx
;
5724 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5726 /* If everything is a comparison, what we have is highly unlikely
5727 to be simpler, so don't use it. */
5728 && ! (COMPARISON_P (x
)
5729 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
)))
5730 /* Similarly, if we end up with one of the expressions the same
5731 as the original, it is certainly not simpler. */
5732 && ! rtx_equal_p (x
, true_rtx
)
5733 && ! rtx_equal_p (x
, false_rtx
))
5735 rtx cop1
= const0_rtx
;
5736 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5738 if (cond_code
== NE
&& COMPARISON_P (cond
))
5741 /* Simplify the alternative arms; this may collapse the true and
5742 false arms to store-flag values. Be careful to use copy_rtx
5743 here since true_rtx or false_rtx might share RTL with x as a
5744 result of the if_then_else_cond call above. */
5745 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5746 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5748 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5749 is unlikely to be simpler. */
5750 if (general_operand (true_rtx
, VOIDmode
)
5751 && general_operand (false_rtx
, VOIDmode
))
5753 enum rtx_code reversed
;
5755 /* Restarting if we generate a store-flag expression will cause
5756 us to loop. Just drop through in this case. */
5758 /* If the result values are STORE_FLAG_VALUE and zero, we can
5759 just make the comparison operation. */
5760 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5761 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5763 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5764 && ((reversed
= reversed_comparison_code_parts
5765 (cond_code
, cond
, cop1
, NULL
))
5767 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5770 /* Likewise, we can make the negate of a comparison operation
5771 if the result values are - STORE_FLAG_VALUE and zero. */
5772 else if (CONST_INT_P (true_rtx
)
5773 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5774 && false_rtx
== const0_rtx
)
5775 x
= simplify_gen_unary (NEG
, mode
,
5776 simplify_gen_relational (cond_code
,
5780 else if (CONST_INT_P (false_rtx
)
5781 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5782 && true_rtx
== const0_rtx
5783 && ((reversed
= reversed_comparison_code_parts
5784 (cond_code
, cond
, cop1
, NULL
))
5786 x
= simplify_gen_unary (NEG
, mode
,
5787 simplify_gen_relational (reversed
,
5792 code
= GET_CODE (x
);
5793 op0_mode
= VOIDmode
;
5798 /* First see if we can apply the inverse distributive law. */
5799 if (code
== PLUS
|| code
== MINUS
5800 || code
== AND
|| code
== IOR
|| code
== XOR
)
5802 x
= apply_distributive_law (x
);
5803 code
= GET_CODE (x
);
5804 op0_mode
= VOIDmode
;
5807 /* If CODE is an associative operation not otherwise handled, see if we
5808 can associate some operands. This can win if they are constants or
5809 if they are logically related (i.e. (a & b) & a). */
5810 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5811 || code
== AND
|| code
== IOR
|| code
== XOR
5812 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5813 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5814 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5816 if (GET_CODE (XEXP (x
, 0)) == code
)
5818 rtx other
= XEXP (XEXP (x
, 0), 0);
5819 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5820 rtx inner_op1
= XEXP (x
, 1);
5823 /* Make sure we pass the constant operand if any as the second
5824 one if this is a commutative operation. */
5825 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5826 std::swap (inner_op0
, inner_op1
);
5827 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5828 : code
== DIV
? MULT
5830 mode
, inner_op0
, inner_op1
);
5832 /* For commutative operations, try the other pair if that one
5834 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5836 other
= XEXP (XEXP (x
, 0), 1);
5837 inner
= simplify_binary_operation (code
, mode
,
5838 XEXP (XEXP (x
, 0), 0),
5843 return simplify_gen_binary (code
, mode
, other
, inner
);
5847 /* A little bit of algebraic simplification here. */
5851 /* Ensure that our address has any ASHIFTs converted to MULT in case
5852 address-recognizing predicates are called later. */
5853 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5854 SUBST (XEXP (x
, 0), temp
);
5858 if (op0_mode
== VOIDmode
)
5859 op0_mode
= GET_MODE (SUBREG_REG (x
));
5861 /* See if this can be moved to simplify_subreg. */
5862 if (CONSTANT_P (SUBREG_REG (x
))
5863 && known_eq (subreg_lowpart_offset (mode
, op0_mode
), SUBREG_BYTE (x
))
5864 /* Don't call gen_lowpart if the inner mode
5865 is VOIDmode and we cannot simplify it, as SUBREG without
5866 inner mode is invalid. */
5867 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5868 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5869 return gen_lowpart (mode
, SUBREG_REG (x
));
5871 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5875 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5880 /* If op is known to have all lower bits zero, the result is zero. */
5881 scalar_int_mode int_mode
, int_op0_mode
;
5883 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5884 && is_a
<scalar_int_mode
> (op0_mode
, &int_op0_mode
)
5885 && (GET_MODE_PRECISION (int_mode
)
5886 < GET_MODE_PRECISION (int_op0_mode
))
5887 && known_eq (subreg_lowpart_offset (int_mode
, int_op0_mode
),
5889 && HWI_COMPUTABLE_MODE_P (int_op0_mode
)
5890 && ((nonzero_bits (SUBREG_REG (x
), int_op0_mode
)
5891 & GET_MODE_MASK (int_mode
)) == 0)
5892 && !side_effects_p (SUBREG_REG (x
)))
5893 return CONST0_RTX (int_mode
);
5896 /* Don't change the mode of the MEM if that would change the meaning
5898 if (MEM_P (SUBREG_REG (x
))
5899 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5900 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5901 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5902 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5904 /* Note that we cannot do any narrowing for non-constants since
5905 we might have been counting on using the fact that some bits were
5906 zero. We now do this in the SET. */
5911 temp
= expand_compound_operation (XEXP (x
, 0));
5913 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5914 replaced by (lshiftrt X C). This will convert
5915 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5917 if (GET_CODE (temp
) == ASHIFTRT
5918 && CONST_INT_P (XEXP (temp
, 1))
5919 && INTVAL (XEXP (temp
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
5920 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5921 INTVAL (XEXP (temp
, 1)));
5923 /* If X has only a single bit that might be nonzero, say, bit I, convert
5924 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5925 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5926 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5927 or a SUBREG of one since we'd be making the expression more
5928 complex if it was just a register. */
5931 && ! (GET_CODE (temp
) == SUBREG
5932 && REG_P (SUBREG_REG (temp
)))
5933 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5934 && (i
= exact_log2 (nonzero_bits (temp
, int_mode
))) >= 0)
5936 rtx temp1
= simplify_shift_const
5937 (NULL_RTX
, ASHIFTRT
, int_mode
,
5938 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
, temp
,
5939 GET_MODE_PRECISION (int_mode
) - 1 - i
),
5940 GET_MODE_PRECISION (int_mode
) - 1 - i
);
5942 /* If all we did was surround TEMP with the two shifts, we
5943 haven't improved anything, so don't use it. Otherwise,
5944 we are better off with TEMP1. */
5945 if (GET_CODE (temp1
) != ASHIFTRT
5946 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5947 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5953 /* We can't handle truncation to a partial integer mode here
5954 because we don't know the real bitsize of the partial
5956 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5959 if (HWI_COMPUTABLE_MODE_P (mode
))
5961 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5962 GET_MODE_MASK (mode
), 0));
5964 /* We can truncate a constant value and return it. */
5967 if (poly_int_rtx_p (XEXP (x
, 0), &c
))
5968 return gen_int_mode (c
, mode
);
5971 /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
5972 whose value is a comparison can be replaced with a subreg if
5973 STORE_FLAG_VALUE permits. */
5974 if (HWI_COMPUTABLE_MODE_P (mode
)
5975 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5976 && (temp
= get_last_value (XEXP (x
, 0)))
5977 && COMPARISON_P (temp
)
5978 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (XEXP (x
, 0))))
5979 return gen_lowpart (mode
, XEXP (x
, 0));
5983 /* (const (const X)) can become (const X). Do it this way rather than
5984 returning the inner CONST since CONST can be shared with a
5986 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5987 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5991 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5992 can add in an offset. find_split_point will split this address up
5993 again if it doesn't match. */
5994 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5995 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
6000 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6001 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6002 bit-field and can be replaced by either a sign_extend or a
6003 sign_extract. The `and' may be a zero_extend and the two
6004 <c>, -<c> constants may be reversed. */
6005 if (GET_CODE (XEXP (x
, 0)) == XOR
6006 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6007 && CONST_INT_P (XEXP (x
, 1))
6008 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
6009 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
6010 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
6011 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
6012 && HWI_COMPUTABLE_MODE_P (int_mode
)
6013 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
6014 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6015 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6016 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
6017 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
6018 && known_eq ((GET_MODE_PRECISION
6019 (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))),
6020 (unsigned int) i
+ 1))))
6021 return simplify_shift_const
6022 (NULL_RTX
, ASHIFTRT
, int_mode
,
6023 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6024 XEXP (XEXP (XEXP (x
, 0), 0), 0),
6025 GET_MODE_PRECISION (int_mode
) - (i
+ 1)),
6026 GET_MODE_PRECISION (int_mode
) - (i
+ 1));
6028 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6029 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6030 the bitsize of the mode - 1. This allows simplification of
6031 "a = (b & 8) == 0;" */
6032 if (XEXP (x
, 1) == constm1_rtx
6033 && !REG_P (XEXP (x
, 0))
6034 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
6035 && REG_P (SUBREG_REG (XEXP (x
, 0))))
6036 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6037 && nonzero_bits (XEXP (x
, 0), int_mode
) == 1)
6038 return simplify_shift_const
6039 (NULL_RTX
, ASHIFTRT
, int_mode
,
6040 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6041 gen_rtx_XOR (int_mode
, XEXP (x
, 0),
6043 GET_MODE_PRECISION (int_mode
) - 1),
6044 GET_MODE_PRECISION (int_mode
) - 1);
6046 /* If we are adding two things that have no bits in common, convert
6047 the addition into an IOR. This will often be further simplified,
6048 for example in cases like ((a & 1) + (a & 2)), which can
6051 if (HWI_COMPUTABLE_MODE_P (mode
)
6052 && (nonzero_bits (XEXP (x
, 0), mode
)
6053 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
6055 /* Try to simplify the expression further. */
6056 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
6057 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
6059 /* If we could, great. If not, do not go ahead with the IOR
6060 replacement, since PLUS appears in many special purpose
6061 address arithmetic instructions. */
6062 if (GET_CODE (temp
) != CLOBBER
6063 && (GET_CODE (temp
) != IOR
6064 || ((XEXP (temp
, 0) != XEXP (x
, 0)
6065 || XEXP (temp
, 1) != XEXP (x
, 1))
6066 && (XEXP (temp
, 0) != XEXP (x
, 1)
6067 || XEXP (temp
, 1) != XEXP (x
, 0)))))
6071 /* Canonicalize x + x into x << 1. */
6072 if (GET_MODE_CLASS (mode
) == MODE_INT
6073 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
6074 && !side_effects_p (XEXP (x
, 0)))
6075 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
6080 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6081 (and <foo> (const_int pow2-1)) */
6082 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6083 && GET_CODE (XEXP (x
, 1)) == AND
6084 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
6085 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
6086 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6087 return simplify_and_const_int (NULL_RTX
, int_mode
, XEXP (x
, 0),
6088 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
6092 /* If we have (mult (plus A B) C), apply the distributive law and then
6093 the inverse distributive law to see if things simplify. This
6094 occurs mostly in addresses, often when unrolling loops. */
6096 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
6098 rtx result
= distribute_and_simplify_rtx (x
, 0);
6103 /* Try simplify a*(b/c) as (a*b)/c. */
6104 if (FLOAT_MODE_P (mode
) && flag_associative_math
6105 && GET_CODE (XEXP (x
, 0)) == DIV
)
6107 rtx tem
= simplify_binary_operation (MULT
, mode
,
6108 XEXP (XEXP (x
, 0), 0),
6111 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
6116 /* If this is a divide by a power of two, treat it as a shift if
6117 its first operand is a shift. */
6118 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6119 && CONST_INT_P (XEXP (x
, 1))
6120 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6121 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6122 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6123 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6124 || GET_CODE (XEXP (x
, 0)) == ROTATE
6125 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6126 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, int_mode
,
6131 case GT
: case GTU
: case GE
: case GEU
:
6132 case LT
: case LTU
: case LE
: case LEU
:
6133 case UNEQ
: case LTGT
:
6134 case UNGT
: case UNGE
:
6135 case UNLT
: case UNLE
:
6136 case UNORDERED
: case ORDERED
:
6137 /* If the first operand is a condition code, we can't do anything
6139 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6140 || GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
)
6142 rtx op0
= XEXP (x
, 0);
6143 rtx op1
= XEXP (x
, 1);
6144 enum rtx_code new_code
;
6146 if (GET_CODE (op0
) == COMPARE
)
6147 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6149 /* Simplify our comparison, if possible. */
6150 new_code
= simplify_comparison (code
, &op0
, &op1
);
6152 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6153 if only the low-order bit is possibly nonzero in X (such as when
6154 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6155 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6156 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6159 Remove any ZERO_EXTRACT we made when thinking this was a
6160 comparison. It may now be simpler to use, e.g., an AND. If a
6161 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6162 the call to make_compound_operation in the SET case.
6164 Don't apply these optimizations if the caller would
6165 prefer a comparison rather than a value.
6166 E.g., for the condition in an IF_THEN_ELSE most targets need
6167 an explicit comparison. */
6172 else if (STORE_FLAG_VALUE
== 1
6174 && is_int_mode (mode
, &int_mode
)
6175 && op1
== const0_rtx
6176 && int_mode
== GET_MODE (op0
)
6177 && nonzero_bits (op0
, int_mode
) == 1)
6178 return gen_lowpart (int_mode
,
6179 expand_compound_operation (op0
));
6181 else if (STORE_FLAG_VALUE
== 1
6183 && is_int_mode (mode
, &int_mode
)
6184 && op1
== const0_rtx
6185 && int_mode
== GET_MODE (op0
)
6186 && (num_sign_bit_copies (op0
, int_mode
)
6187 == GET_MODE_PRECISION (int_mode
)))
6189 op0
= expand_compound_operation (op0
);
6190 return simplify_gen_unary (NEG
, int_mode
,
6191 gen_lowpart (int_mode
, op0
),
6195 else if (STORE_FLAG_VALUE
== 1
6197 && is_int_mode (mode
, &int_mode
)
6198 && op1
== const0_rtx
6199 && int_mode
== GET_MODE (op0
)
6200 && nonzero_bits (op0
, int_mode
) == 1)
6202 op0
= expand_compound_operation (op0
);
6203 return simplify_gen_binary (XOR
, int_mode
,
6204 gen_lowpart (int_mode
, op0
),
6208 else if (STORE_FLAG_VALUE
== 1
6210 && is_int_mode (mode
, &int_mode
)
6211 && op1
== const0_rtx
6212 && int_mode
== GET_MODE (op0
)
6213 && (num_sign_bit_copies (op0
, int_mode
)
6214 == GET_MODE_PRECISION (int_mode
)))
6216 op0
= expand_compound_operation (op0
);
6217 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), 1);
6220 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6225 else if (STORE_FLAG_VALUE
== -1
6227 && is_int_mode (mode
, &int_mode
)
6228 && op1
== const0_rtx
6229 && int_mode
== GET_MODE (op0
)
6230 && (num_sign_bit_copies (op0
, int_mode
)
6231 == GET_MODE_PRECISION (int_mode
)))
6232 return gen_lowpart (int_mode
, expand_compound_operation (op0
));
6234 else if (STORE_FLAG_VALUE
== -1
6236 && is_int_mode (mode
, &int_mode
)
6237 && op1
== const0_rtx
6238 && int_mode
== GET_MODE (op0
)
6239 && nonzero_bits (op0
, int_mode
) == 1)
6241 op0
= expand_compound_operation (op0
);
6242 return simplify_gen_unary (NEG
, int_mode
,
6243 gen_lowpart (int_mode
, op0
),
6247 else if (STORE_FLAG_VALUE
== -1
6249 && is_int_mode (mode
, &int_mode
)
6250 && op1
== const0_rtx
6251 && int_mode
== GET_MODE (op0
)
6252 && (num_sign_bit_copies (op0
, int_mode
)
6253 == GET_MODE_PRECISION (int_mode
)))
6255 op0
= expand_compound_operation (op0
);
6256 return simplify_gen_unary (NOT
, int_mode
,
6257 gen_lowpart (int_mode
, op0
),
6261 /* If X is 0/1, (eq X 0) is X-1. */
6262 else if (STORE_FLAG_VALUE
== -1
6264 && is_int_mode (mode
, &int_mode
)
6265 && op1
== const0_rtx
6266 && int_mode
== GET_MODE (op0
)
6267 && nonzero_bits (op0
, int_mode
) == 1)
6269 op0
= expand_compound_operation (op0
);
6270 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), -1);
6273 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6274 one bit that might be nonzero, we can convert (ne x 0) to
6275 (ashift x c) where C puts the bit in the sign bit. Remove any
6276 AND with STORE_FLAG_VALUE when we are done, since we are only
6277 going to test the sign bit. */
6279 && is_int_mode (mode
, &int_mode
)
6280 && HWI_COMPUTABLE_MODE_P (int_mode
)
6281 && val_signbit_p (int_mode
, STORE_FLAG_VALUE
)
6282 && op1
== const0_rtx
6283 && int_mode
== GET_MODE (op0
)
6284 && (i
= exact_log2 (nonzero_bits (op0
, int_mode
))) >= 0)
6286 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6287 expand_compound_operation (op0
),
6288 GET_MODE_PRECISION (int_mode
) - 1 - i
);
6289 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6295 /* If the code changed, return a whole new comparison.
6296 We also need to avoid using SUBST in cases where
6297 simplify_comparison has widened a comparison with a CONST_INT,
6298 since in that case the wider CONST_INT may fail the sanity
6299 checks in do_SUBST. */
6300 if (new_code
!= code
6301 || (CONST_INT_P (op1
)
6302 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6303 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6304 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6306 /* Otherwise, keep this operation, but maybe change its operands.
6307 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6308 SUBST (XEXP (x
, 0), op0
);
6309 SUBST (XEXP (x
, 1), op1
);
6314 return simplify_if_then_else (x
);
6320 /* If we are processing SET_DEST, we are done. */
6324 return expand_compound_operation (x
);
6327 return simplify_set (x
);
6331 return simplify_logical (x
);
6338 /* If this is a shift by a constant amount, simplify it. */
6339 if (CONST_INT_P (XEXP (x
, 1)))
6340 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6341 INTVAL (XEXP (x
, 1)));
6343 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6345 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6347 << exact_log2 (GET_MODE_UNIT_BITSIZE
6354 rtx trueop0
= XEXP (x
, 0);
6355 mode
= GET_MODE (trueop0
);
6356 rtx trueop1
= XEXP (x
, 1);
6357 /* If we select a low-part subreg, return that. */
6358 if (vec_series_lowpart_p (GET_MODE (x
), mode
, trueop1
))
6360 rtx new_rtx
= lowpart_subreg (GET_MODE (x
), trueop0
, mode
);
6361 if (new_rtx
!= NULL_RTX
)
6373 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6376 simplify_if_then_else (rtx x
)
6378 machine_mode mode
= GET_MODE (x
);
6379 rtx cond
= XEXP (x
, 0);
6380 rtx true_rtx
= XEXP (x
, 1);
6381 rtx false_rtx
= XEXP (x
, 2);
6382 enum rtx_code true_code
= GET_CODE (cond
);
6383 int comparison_p
= COMPARISON_P (cond
);
6386 enum rtx_code false_code
;
6388 scalar_int_mode int_mode
, inner_mode
;
6390 /* Simplify storing of the truth value. */
6391 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6392 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6393 XEXP (cond
, 0), XEXP (cond
, 1));
6395 /* Also when the truth value has to be reversed. */
6397 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6398 && (reversed
= reversed_comparison (cond
, mode
)))
6401 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6402 in it is being compared against certain values. Get the true and false
6403 comparisons and see if that says anything about the value of each arm. */
6406 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6408 && REG_P (XEXP (cond
, 0)))
6411 rtx from
= XEXP (cond
, 0);
6412 rtx true_val
= XEXP (cond
, 1);
6413 rtx false_val
= true_val
;
6416 /* If FALSE_CODE is EQ, swap the codes and arms. */
6418 if (false_code
== EQ
)
6420 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6421 std::swap (true_rtx
, false_rtx
);
6424 scalar_int_mode from_mode
;
6425 if (is_a
<scalar_int_mode
> (GET_MODE (from
), &from_mode
))
6427 /* If we are comparing against zero and the expression being
6428 tested has only a single bit that might be nonzero, that is
6429 its value when it is not equal to zero. Similarly if it is
6430 known to be -1 or 0. */
6432 && true_val
== const0_rtx
6433 && pow2p_hwi (nzb
= nonzero_bits (from
, from_mode
)))
6436 false_val
= gen_int_mode (nzb
, from_mode
);
6438 else if (true_code
== EQ
6439 && true_val
== const0_rtx
6440 && (num_sign_bit_copies (from
, from_mode
)
6441 == GET_MODE_PRECISION (from_mode
)))
6444 false_val
= constm1_rtx
;
6448 /* Now simplify an arm if we know the value of the register in the
6449 branch and it is used in the arm. Be careful due to the potential
6450 of locally-shared RTL. */
6452 if (reg_mentioned_p (from
, true_rtx
))
6453 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6455 pc_rtx
, pc_rtx
, 0, 0, 0);
6456 if (reg_mentioned_p (from
, false_rtx
))
6457 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6459 pc_rtx
, pc_rtx
, 0, 0, 0);
6461 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6462 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6464 true_rtx
= XEXP (x
, 1);
6465 false_rtx
= XEXP (x
, 2);
6466 true_code
= GET_CODE (cond
);
6469 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6470 reversed, do so to avoid needing two sets of patterns for
6471 subtract-and-branch insns. Similarly if we have a constant in the true
6472 arm, the false arm is the same as the first operand of the comparison, or
6473 the false arm is more complicated than the true arm. */
6476 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6477 && (true_rtx
== pc_rtx
6478 || (CONSTANT_P (true_rtx
)
6479 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6480 || true_rtx
== const0_rtx
6481 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6482 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6483 && !OBJECT_P (false_rtx
))
6484 || reg_mentioned_p (true_rtx
, false_rtx
)
6485 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6487 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6488 SUBST (XEXP (x
, 1), false_rtx
);
6489 SUBST (XEXP (x
, 2), true_rtx
);
6491 std::swap (true_rtx
, false_rtx
);
6494 /* It is possible that the conditional has been simplified out. */
6495 true_code
= GET_CODE (cond
);
6496 comparison_p
= COMPARISON_P (cond
);
6499 /* If the two arms are identical, we don't need the comparison. */
6501 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6504 /* Convert a == b ? b : a to "a". */
6505 if (true_code
== EQ
&& ! side_effects_p (cond
)
6506 && !HONOR_NANS (mode
)
6507 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6508 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6510 else if (true_code
== NE
&& ! side_effects_p (cond
)
6511 && !HONOR_NANS (mode
)
6512 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6513 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6516 /* Look for cases where we have (abs x) or (neg (abs X)). */
6518 if (GET_MODE_CLASS (mode
) == MODE_INT
6520 && XEXP (cond
, 1) == const0_rtx
6521 && GET_CODE (false_rtx
) == NEG
6522 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6523 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6524 && ! side_effects_p (true_rtx
))
6529 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6533 simplify_gen_unary (NEG
, mode
,
6534 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6540 /* Look for MIN or MAX. */
6542 if ((! FLOAT_MODE_P (mode
)
6543 || (flag_unsafe_math_optimizations
6544 && !HONOR_NANS (mode
)
6545 && !HONOR_SIGNED_ZEROS (mode
)))
6547 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6548 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6549 && ! side_effects_p (cond
))
6554 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6557 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6560 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6563 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6568 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6569 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6570 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6571 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6572 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6573 neither 1 or -1, but it isn't worth checking for. */
6575 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6577 && is_int_mode (mode
, &int_mode
)
6578 && ! side_effects_p (x
))
6580 rtx t
= make_compound_operation (true_rtx
, SET
);
6581 rtx f
= make_compound_operation (false_rtx
, SET
);
6582 rtx cond_op0
= XEXP (cond
, 0);
6583 rtx cond_op1
= XEXP (cond
, 1);
6584 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6585 scalar_int_mode m
= int_mode
;
6586 rtx z
= 0, c1
= NULL_RTX
;
6588 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6589 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6590 || GET_CODE (t
) == ASHIFT
6591 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6592 && rtx_equal_p (XEXP (t
, 0), f
))
6593 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6595 /* If an identity-zero op is commutative, check whether there
6596 would be a match if we swapped the operands. */
6597 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6598 || GET_CODE (t
) == XOR
)
6599 && rtx_equal_p (XEXP (t
, 1), f
))
6600 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6601 else if (GET_CODE (t
) == SIGN_EXTEND
6602 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6603 && (GET_CODE (XEXP (t
, 0)) == PLUS
6604 || GET_CODE (XEXP (t
, 0)) == MINUS
6605 || GET_CODE (XEXP (t
, 0)) == IOR
6606 || GET_CODE (XEXP (t
, 0)) == XOR
6607 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6608 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6609 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6610 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6611 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6612 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6613 && (num_sign_bit_copies (f
, GET_MODE (f
))
6615 (GET_MODE_PRECISION (int_mode
)
6616 - GET_MODE_PRECISION (inner_mode
))))
6618 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6619 extend_op
= SIGN_EXTEND
;
6622 else if (GET_CODE (t
) == SIGN_EXTEND
6623 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6624 && (GET_CODE (XEXP (t
, 0)) == PLUS
6625 || GET_CODE (XEXP (t
, 0)) == IOR
6626 || GET_CODE (XEXP (t
, 0)) == XOR
)
6627 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6628 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6629 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6630 && (num_sign_bit_copies (f
, GET_MODE (f
))
6632 (GET_MODE_PRECISION (int_mode
)
6633 - GET_MODE_PRECISION (inner_mode
))))
6635 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6636 extend_op
= SIGN_EXTEND
;
6639 else if (GET_CODE (t
) == ZERO_EXTEND
6640 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6641 && (GET_CODE (XEXP (t
, 0)) == PLUS
6642 || GET_CODE (XEXP (t
, 0)) == MINUS
6643 || GET_CODE (XEXP (t
, 0)) == IOR
6644 || GET_CODE (XEXP (t
, 0)) == XOR
6645 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6646 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6647 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6648 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6649 && HWI_COMPUTABLE_MODE_P (int_mode
)
6650 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6651 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6652 && ((nonzero_bits (f
, GET_MODE (f
))
6653 & ~GET_MODE_MASK (inner_mode
))
6656 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6657 extend_op
= ZERO_EXTEND
;
6660 else if (GET_CODE (t
) == ZERO_EXTEND
6661 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6662 && (GET_CODE (XEXP (t
, 0)) == PLUS
6663 || GET_CODE (XEXP (t
, 0)) == IOR
6664 || GET_CODE (XEXP (t
, 0)) == XOR
)
6665 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6666 && HWI_COMPUTABLE_MODE_P (int_mode
)
6667 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6668 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6669 && ((nonzero_bits (f
, GET_MODE (f
))
6670 & ~GET_MODE_MASK (inner_mode
))
6673 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6674 extend_op
= ZERO_EXTEND
;
6680 machine_mode cm
= m
;
6681 if ((op
== ASHIFT
|| op
== LSHIFTRT
|| op
== ASHIFTRT
)
6682 && GET_MODE (c1
) != VOIDmode
)
6684 temp
= subst (simplify_gen_relational (true_code
, cm
, VOIDmode
,
6685 cond_op0
, cond_op1
),
6686 pc_rtx
, pc_rtx
, 0, 0, 0);
6687 temp
= simplify_gen_binary (MULT
, cm
, temp
,
6688 simplify_gen_binary (MULT
, cm
, c1
,
6690 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6691 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6693 if (extend_op
!= UNKNOWN
)
6694 temp
= simplify_gen_unary (extend_op
, int_mode
, temp
, m
);
6700 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6701 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6702 negation of a single bit, we can convert this operation to a shift. We
6703 can actually do this more generally, but it doesn't seem worth it. */
6706 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6707 && XEXP (cond
, 1) == const0_rtx
6708 && false_rtx
== const0_rtx
6709 && CONST_INT_P (true_rtx
)
6710 && ((nonzero_bits (XEXP (cond
, 0), int_mode
) == 1
6711 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6712 || ((num_sign_bit_copies (XEXP (cond
, 0), int_mode
)
6713 == GET_MODE_PRECISION (int_mode
))
6714 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6716 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6717 gen_lowpart (int_mode
, XEXP (cond
, 0)), i
);
6719 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6720 non-zero bit in A is C1. */
6721 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6722 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6723 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6724 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (cond
, 0)), &inner_mode
)
6725 && (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))
6726 == nonzero_bits (XEXP (cond
, 0), inner_mode
)
6727 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))) >= 0)
6729 rtx val
= XEXP (cond
, 0);
6730 if (inner_mode
== int_mode
)
6732 else if (GET_MODE_PRECISION (inner_mode
) < GET_MODE_PRECISION (int_mode
))
6733 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, val
, inner_mode
);
6739 /* Simplify X, a SET expression. Return the new expression. */
6742 simplify_set (rtx x
)
6744 rtx src
= SET_SRC (x
);
6745 rtx dest
= SET_DEST (x
);
6747 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6748 rtx_insn
*other_insn
;
6750 scalar_int_mode int_mode
;
6752 /* (set (pc) (return)) gets written as (return). */
6753 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6756 /* Now that we know for sure which bits of SRC we are using, see if we can
6757 simplify the expression for the object knowing that we only need the
6760 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6762 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6763 SUBST (SET_SRC (x
), src
);
6766 /* If the source is a COMPARE, look for the use of the comparison result
6767 and try to simplify it unless we already have used undobuf.other_insn. */
6768 if ((GET_MODE_CLASS (mode
) == MODE_CC
|| GET_CODE (src
) == COMPARE
)
6769 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6770 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6771 && COMPARISON_P (*cc_use
)
6772 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6774 enum rtx_code old_code
= GET_CODE (*cc_use
);
6775 enum rtx_code new_code
;
6777 int other_changed
= 0;
6778 rtx inner_compare
= NULL_RTX
;
6779 machine_mode compare_mode
= GET_MODE (dest
);
6781 if (GET_CODE (src
) == COMPARE
)
6783 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6784 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6786 inner_compare
= op0
;
6787 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6791 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6793 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6796 new_code
= old_code
;
6797 else if (!CONSTANT_P (tmp
))
6799 new_code
= GET_CODE (tmp
);
6800 op0
= XEXP (tmp
, 0);
6801 op1
= XEXP (tmp
, 1);
6805 rtx pat
= PATTERN (other_insn
);
6806 undobuf
.other_insn
= other_insn
;
6807 SUBST (*cc_use
, tmp
);
6809 /* Attempt to simplify CC user. */
6810 if (GET_CODE (pat
) == SET
)
6812 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6813 if (new_rtx
!= NULL_RTX
)
6814 SUBST (SET_SRC (pat
), new_rtx
);
6817 /* Convert X into a no-op move. */
6818 SUBST (SET_DEST (x
), pc_rtx
);
6819 SUBST (SET_SRC (x
), pc_rtx
);
6823 /* Simplify our comparison, if possible. */
6824 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6826 #ifdef SELECT_CC_MODE
6827 /* If this machine has CC modes other than CCmode, check to see if we
6828 need to use a different CC mode here. */
6829 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6830 compare_mode
= GET_MODE (op0
);
6831 else if (inner_compare
6832 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6833 && new_code
== old_code
6834 && op0
== XEXP (inner_compare
, 0)
6835 && op1
== XEXP (inner_compare
, 1))
6836 compare_mode
= GET_MODE (inner_compare
);
6838 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6840 /* If the mode changed, we have to change SET_DEST, the mode in the
6841 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6842 a hard register, just build new versions with the proper mode. If it
6843 is a pseudo, we lose unless it is only time we set the pseudo, in
6844 which case we can safely change its mode. */
6845 if (compare_mode
!= GET_MODE (dest
))
6847 if (can_change_dest_mode (dest
, 0, compare_mode
))
6849 unsigned int regno
= REGNO (dest
);
6852 if (regno
< FIRST_PSEUDO_REGISTER
)
6853 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6856 subst_mode (regno
, compare_mode
);
6857 new_dest
= regno_reg_rtx
[regno
];
6860 SUBST (SET_DEST (x
), new_dest
);
6861 SUBST (XEXP (*cc_use
, 0), new_dest
);
6867 #endif /* SELECT_CC_MODE */
6869 /* If the code changed, we have to build a new comparison in
6870 undobuf.other_insn. */
6871 if (new_code
!= old_code
)
6873 int other_changed_previously
= other_changed
;
6874 unsigned HOST_WIDE_INT mask
;
6875 rtx old_cc_use
= *cc_use
;
6877 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6881 /* If the only change we made was to change an EQ into an NE or
6882 vice versa, OP0 has only one bit that might be nonzero, and OP1
6883 is zero, check if changing the user of the condition code will
6884 produce a valid insn. If it won't, we can keep the original code
6885 in that insn by surrounding our operation with an XOR. */
6887 if (((old_code
== NE
&& new_code
== EQ
)
6888 || (old_code
== EQ
&& new_code
== NE
))
6889 && ! other_changed_previously
&& op1
== const0_rtx
6890 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6891 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6893 rtx pat
= PATTERN (other_insn
), note
= 0;
6895 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6896 && ! check_asm_operands (pat
)))
6898 *cc_use
= old_cc_use
;
6901 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6909 undobuf
.other_insn
= other_insn
;
6911 /* Don't generate a compare of a CC with 0, just use that CC. */
6912 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6914 SUBST (SET_SRC (x
), op0
);
6917 /* Otherwise, if we didn't previously have the same COMPARE we
6918 want, create it from scratch. */
6919 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6920 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6922 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6928 /* Get SET_SRC in a form where we have placed back any
6929 compound expressions. Then do the checks below. */
6930 src
= make_compound_operation (src
, SET
);
6931 SUBST (SET_SRC (x
), src
);
6934 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6935 and X being a REG or (subreg (reg)), we may be able to convert this to
6936 (set (subreg:m2 x) (op)).
6938 We can always do this if M1 is narrower than M2 because that means that
6939 we only care about the low bits of the result.
6941 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6942 perform a narrower operation than requested since the high-order bits will
6943 be undefined. On machine where it is defined, this transformation is safe
6944 as long as M1 and M2 have the same number of words. */
6946 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6947 && !OBJECT_P (SUBREG_REG (src
))
6948 && (known_equal_after_align_up
6949 (GET_MODE_SIZE (GET_MODE (src
)),
6950 GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))),
6952 && (WORD_REGISTER_OPERATIONS
|| !paradoxical_subreg_p (src
))
6953 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6954 && !REG_CAN_CHANGE_MODE_P (REGNO (dest
),
6955 GET_MODE (SUBREG_REG (src
)),
6958 || (GET_CODE (dest
) == SUBREG
6959 && REG_P (SUBREG_REG (dest
)))))
6961 SUBST (SET_DEST (x
),
6962 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6964 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6966 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6969 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6970 would require a paradoxical subreg. Replace the subreg with a
6971 zero_extend to avoid the reload that would otherwise be required.
6972 Don't do this unless we have a scalar integer mode, otherwise the
6973 transformation is incorrect. */
6975 enum rtx_code extend_op
;
6976 if (paradoxical_subreg_p (src
)
6977 && MEM_P (SUBREG_REG (src
))
6978 && SCALAR_INT_MODE_P (GET_MODE (src
))
6979 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
6982 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
6987 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6988 are comparing an item known to be 0 or -1 against 0, use a logical
6989 operation instead. Check for one of the arms being an IOR of the other
6990 arm with some value. We compute three terms to be IOR'ed together. In
6991 practice, at most two will be nonzero. Then we do the IOR's. */
6993 if (GET_CODE (dest
) != PC
6994 && GET_CODE (src
) == IF_THEN_ELSE
6995 && is_int_mode (GET_MODE (src
), &int_mode
)
6996 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6997 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6998 && int_mode
== GET_MODE (XEXP (XEXP (src
, 0), 0))
6999 && (!HAVE_conditional_move
7000 || ! can_conditionally_move_p (int_mode
))
7001 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0), int_mode
)
7002 == GET_MODE_PRECISION (int_mode
))
7003 && ! side_effects_p (src
))
7005 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7006 ? XEXP (src
, 1) : XEXP (src
, 2));
7007 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7008 ? XEXP (src
, 2) : XEXP (src
, 1));
7009 rtx term1
= const0_rtx
, term2
, term3
;
7011 if (GET_CODE (true_rtx
) == IOR
7012 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
7013 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
7014 else if (GET_CODE (true_rtx
) == IOR
7015 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
7016 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
7017 else if (GET_CODE (false_rtx
) == IOR
7018 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
7019 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
7020 else if (GET_CODE (false_rtx
) == IOR
7021 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
7022 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
7024 term2
= simplify_gen_binary (AND
, int_mode
,
7025 XEXP (XEXP (src
, 0), 0), true_rtx
);
7026 term3
= simplify_gen_binary (AND
, int_mode
,
7027 simplify_gen_unary (NOT
, int_mode
,
7028 XEXP (XEXP (src
, 0), 0),
7033 simplify_gen_binary (IOR
, int_mode
,
7034 simplify_gen_binary (IOR
, int_mode
,
7041 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7042 whole thing fail. */
7043 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
7045 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
7048 /* Convert this into a field assignment operation, if possible. */
7049 return make_field_assignment (x
);
7052 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7056 simplify_logical (rtx x
)
7058 rtx op0
= XEXP (x
, 0);
7059 rtx op1
= XEXP (x
, 1);
7060 scalar_int_mode mode
;
7062 switch (GET_CODE (x
))
7065 /* We can call simplify_and_const_int only if we don't lose
7066 any (sign) bits when converting INTVAL (op1) to
7067 "unsigned HOST_WIDE_INT". */
7068 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
7069 && CONST_INT_P (op1
)
7070 && (HWI_COMPUTABLE_MODE_P (mode
)
7071 || INTVAL (op1
) > 0))
7073 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
7074 if (GET_CODE (x
) != AND
)
7081 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7082 apply the distributive law and then the inverse distributive
7083 law to see if things simplify. */
7084 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
7086 rtx result
= distribute_and_simplify_rtx (x
, 0);
7090 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
7092 rtx result
= distribute_and_simplify_rtx (x
, 1);
7099 /* If we have (ior (and A B) C), apply the distributive law and then
7100 the inverse distributive law to see if things simplify. */
7102 if (GET_CODE (op0
) == AND
)
7104 rtx result
= distribute_and_simplify_rtx (x
, 0);
7109 if (GET_CODE (op1
) == AND
)
7111 rtx result
= distribute_and_simplify_rtx (x
, 1);
7124 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7125 operations" because they can be replaced with two more basic operations.
7126 ZERO_EXTEND is also considered "compound" because it can be replaced with
7127 an AND operation, which is simpler, though only one operation.
7129 The function expand_compound_operation is called with an rtx expression
7130 and will convert it to the appropriate shifts and AND operations,
7131 simplifying at each stage.
7133 The function make_compound_operation is called to convert an expression
7134 consisting of shifts and ANDs into the equivalent compound expression.
7135 It is the inverse of this function, loosely speaking. */
7138 expand_compound_operation (rtx x
)
7140 unsigned HOST_WIDE_INT pos
= 0, len
;
7142 unsigned int modewidth
;
7144 scalar_int_mode inner_mode
;
7146 switch (GET_CODE (x
))
7152 /* We can't necessarily use a const_int for a multiword mode;
7153 it depends on implicitly extending the value.
7154 Since we don't know the right way to extend it,
7155 we can't tell whether the implicit way is right.
7157 Even for a mode that is no wider than a const_int,
7158 we can't win, because we need to sign extend one of its bits through
7159 the rest of it, and we don't know which bit. */
7160 if (CONST_INT_P (XEXP (x
, 0)))
7163 /* Reject modes that aren't scalar integers because turning vector
7164 or complex modes into shifts causes problems. */
7165 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7168 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7169 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7170 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7171 reloaded. If not for that, MEM's would very rarely be safe.
7173 Reject modes bigger than a word, because we might not be able
7174 to reference a two-register group starting with an arbitrary register
7175 (and currently gen_lowpart might crash for a SUBREG). */
7177 if (GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7180 len
= GET_MODE_PRECISION (inner_mode
);
7181 /* If the inner object has VOIDmode (the only way this can happen
7182 is if it is an ASM_OPERANDS), we can't do anything since we don't
7183 know how much masking to do. */
7195 /* If the operand is a CLOBBER, just return it. */
7196 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7199 if (!CONST_INT_P (XEXP (x
, 1))
7200 || !CONST_INT_P (XEXP (x
, 2)))
7203 /* Reject modes that aren't scalar integers because turning vector
7204 or complex modes into shifts causes problems. */
7205 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7208 len
= INTVAL (XEXP (x
, 1));
7209 pos
= INTVAL (XEXP (x
, 2));
7211 /* This should stay within the object being extracted, fail otherwise. */
7212 if (len
+ pos
> GET_MODE_PRECISION (inner_mode
))
7215 if (BITS_BIG_ENDIAN
)
7216 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
7224 /* We've rejected non-scalar operations by now. */
7225 scalar_int_mode mode
= as_a
<scalar_int_mode
> (GET_MODE (x
));
7227 /* Convert sign extension to zero extension, if we know that the high
7228 bit is not set, as this is easier to optimize. It will be converted
7229 back to cheaper alternative in make_extraction. */
7230 if (GET_CODE (x
) == SIGN_EXTEND
7231 && HWI_COMPUTABLE_MODE_P (mode
)
7232 && ((nonzero_bits (XEXP (x
, 0), inner_mode
)
7233 & ~(((unsigned HOST_WIDE_INT
) GET_MODE_MASK (inner_mode
)) >> 1))
7236 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7237 rtx temp2
= expand_compound_operation (temp
);
7239 /* Make sure this is a profitable operation. */
7240 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7241 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7243 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7244 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7250 /* We can optimize some special cases of ZERO_EXTEND. */
7251 if (GET_CODE (x
) == ZERO_EXTEND
)
7253 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7254 know that the last value didn't have any inappropriate bits
7256 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7257 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7258 && HWI_COMPUTABLE_MODE_P (mode
)
7259 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
)
7260 & ~GET_MODE_MASK (inner_mode
)) == 0)
7261 return XEXP (XEXP (x
, 0), 0);
7263 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7264 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7265 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7266 && subreg_lowpart_p (XEXP (x
, 0))
7267 && HWI_COMPUTABLE_MODE_P (mode
)
7268 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), mode
)
7269 & ~GET_MODE_MASK (inner_mode
)) == 0)
7270 return SUBREG_REG (XEXP (x
, 0));
7272 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7273 is a comparison and STORE_FLAG_VALUE permits. This is like
7274 the first case, but it works even when MODE is larger
7275 than HOST_WIDE_INT. */
7276 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7277 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7278 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7279 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7280 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7281 return XEXP (XEXP (x
, 0), 0);
7283 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7284 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7285 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7286 && subreg_lowpart_p (XEXP (x
, 0))
7287 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7288 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7289 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7290 return SUBREG_REG (XEXP (x
, 0));
7294 /* If we reach here, we want to return a pair of shifts. The inner
7295 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7296 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7297 logical depending on the value of UNSIGNEDP.
7299 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7300 converted into an AND of a shift.
7302 We must check for the case where the left shift would have a negative
7303 count. This can happen in a case like (x >> 31) & 255 on machines
7304 that can't shift by a constant. On those machines, we would first
7305 combine the shift with the AND to produce a variable-position
7306 extraction. Then the constant of 31 would be substituted in
7307 to produce such a position. */
7309 modewidth
= GET_MODE_PRECISION (mode
);
7310 if (modewidth
>= pos
+ len
)
7312 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7313 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7315 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7316 tem
, modewidth
- pos
- len
);
7317 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7318 mode
, tem
, modewidth
- len
);
7320 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7322 tem
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, inner_mode
,
7324 tem
= gen_lowpart (mode
, tem
);
7325 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7327 tem
= simplify_and_const_int (NULL_RTX
, mode
, tem
,
7328 (HOST_WIDE_INT_1U
<< len
) - 1);
7331 /* Any other cases we can't handle. */
7334 /* If we couldn't do this for some reason, return the original
7336 if (GET_CODE (tem
) == CLOBBER
)
7342 /* X is a SET which contains an assignment of one object into
7343 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7344 or certain SUBREGS). If possible, convert it into a series of
7347 We half-heartedly support variable positions, but do not at all
7348 support variable lengths. */
7351 expand_field_assignment (const_rtx x
)
7354 rtx pos
; /* Always counts from low bit. */
7356 rtx mask
, cleared
, masked
;
7357 scalar_int_mode compute_mode
;
7359 /* Loop until we find something we can't simplify. */
7362 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7363 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7365 rtx x0
= XEXP (SET_DEST (x
), 0);
7366 if (!GET_MODE_PRECISION (GET_MODE (x0
)).is_constant (&len
))
7368 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7369 pos
= gen_int_mode (subreg_lsb (XEXP (SET_DEST (x
), 0)),
7372 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7373 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7375 inner
= XEXP (SET_DEST (x
), 0);
7376 if (!GET_MODE_PRECISION (GET_MODE (inner
)).is_constant (&inner_len
))
7379 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7380 pos
= XEXP (SET_DEST (x
), 2);
7382 /* A constant position should stay within the width of INNER. */
7383 if (CONST_INT_P (pos
) && INTVAL (pos
) + len
> inner_len
)
7386 if (BITS_BIG_ENDIAN
)
7388 if (CONST_INT_P (pos
))
7389 pos
= GEN_INT (inner_len
- len
- INTVAL (pos
));
7390 else if (GET_CODE (pos
) == MINUS
7391 && CONST_INT_P (XEXP (pos
, 1))
7392 && INTVAL (XEXP (pos
, 1)) == inner_len
- len
)
7393 /* If position is ADJUST - X, new position is X. */
7394 pos
= XEXP (pos
, 0);
7396 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7397 gen_int_mode (inner_len
- len
,
7403 /* If the destination is a subreg that overwrites the whole of the inner
7404 register, we can move the subreg to the source. */
7405 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7406 /* We need SUBREGs to compute nonzero_bits properly. */
7407 && nonzero_sign_valid
7408 && !read_modify_subreg_p (SET_DEST (x
)))
7410 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7412 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7419 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7420 inner
= SUBREG_REG (inner
);
7422 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7423 if (!is_a
<scalar_int_mode
> (GET_MODE (inner
), &compute_mode
))
7425 /* Don't do anything for vector or complex integral types. */
7426 if (! FLOAT_MODE_P (GET_MODE (inner
)))
7429 /* Try to find an integral mode to pun with. */
7430 if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner
)), 0)
7431 .exists (&compute_mode
))
7434 inner
= gen_lowpart (compute_mode
, inner
);
7437 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7438 if (len
>= HOST_BITS_PER_WIDE_INT
)
7441 /* Don't try to compute in too wide unsupported modes. */
7442 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7445 /* Now compute the equivalent expression. Make a copy of INNER
7446 for the SET_DEST in case it is a MEM into which we will substitute;
7447 we don't want shared RTL in that case. */
7448 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7450 cleared
= simplify_gen_binary (AND
, compute_mode
,
7451 simplify_gen_unary (NOT
, compute_mode
,
7452 simplify_gen_binary (ASHIFT
,
7457 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7458 simplify_gen_binary (
7460 gen_lowpart (compute_mode
, SET_SRC (x
)),
7464 x
= gen_rtx_SET (copy_rtx (inner
),
7465 simplify_gen_binary (IOR
, compute_mode
,
7472 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7473 it is an RTX that represents the (variable) starting position; otherwise,
7474 POS is the (constant) starting bit position. Both are counted from the LSB.
7476 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7478 IN_DEST is nonzero if this is a reference in the destination of a SET.
7479 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7480 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7483 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7484 ZERO_EXTRACT should be built even for bits starting at bit 0.
7486 MODE is the desired mode of the result (if IN_DEST == 0).
7488 The result is an RTX for the extraction or NULL_RTX if the target
7492 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7493 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7494 int in_dest
, int in_compare
)
7496 /* This mode describes the size of the storage area
7497 to fetch the overall value from. Within that, we
7498 ignore the POS lowest bits, etc. */
7499 machine_mode is_mode
= GET_MODE (inner
);
7500 machine_mode inner_mode
;
7501 scalar_int_mode wanted_inner_mode
;
7502 scalar_int_mode wanted_inner_reg_mode
= word_mode
;
7503 scalar_int_mode pos_mode
= word_mode
;
7504 machine_mode extraction_mode
= word_mode
;
7506 rtx orig_pos_rtx
= pos_rtx
;
7507 HOST_WIDE_INT orig_pos
;
7509 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7510 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7512 if (GET_CODE (inner
) == SUBREG
7513 && subreg_lowpart_p (inner
)
7514 && (paradoxical_subreg_p (inner
)
7515 /* If trying or potentionally trying to extract
7516 bits outside of is_mode, don't look through
7517 non-paradoxical SUBREGs. See PR82192. */
7518 || (pos_rtx
== NULL_RTX
7519 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
)))))
7521 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7522 consider just the QI as the memory to extract from.
7523 The subreg adds or removes high bits; its mode is
7524 irrelevant to the meaning of this extraction,
7525 since POS and LEN count from the lsb. */
7526 if (MEM_P (SUBREG_REG (inner
)))
7527 is_mode
= GET_MODE (SUBREG_REG (inner
));
7528 inner
= SUBREG_REG (inner
);
7530 else if (GET_CODE (inner
) == ASHIFT
7531 && CONST_INT_P (XEXP (inner
, 1))
7532 && pos_rtx
== 0 && pos
== 0
7533 && len
> UINTVAL (XEXP (inner
, 1)))
7535 /* We're extracting the least significant bits of an rtx
7536 (ashift X (const_int C)), where LEN > C. Extract the
7537 least significant (LEN - C) bits of X, giving an rtx
7538 whose mode is MODE, then shift it left C times. */
7539 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7540 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7541 unsignedp
, in_dest
, in_compare
);
7543 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7545 else if (GET_CODE (inner
) == MULT
7546 && CONST_INT_P (XEXP (inner
, 1))
7547 && pos_rtx
== 0 && pos
== 0)
7549 /* We're extracting the least significant bits of an rtx
7550 (mult X (const_int 2^C)), where LEN > C. Extract the
7551 least significant (LEN - C) bits of X, giving an rtx
7552 whose mode is MODE, then multiply it by 2^C. */
7553 const HOST_WIDE_INT shift_amt
= exact_log2 (INTVAL (XEXP (inner
, 1)));
7554 if (IN_RANGE (shift_amt
, 1, len
- 1))
7556 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7557 0, 0, len
- shift_amt
,
7558 unsignedp
, in_dest
, in_compare
);
7560 return gen_rtx_MULT (mode
, new_rtx
, XEXP (inner
, 1));
7563 else if (GET_CODE (inner
) == TRUNCATE
7564 /* If trying or potentionally trying to extract
7565 bits outside of is_mode, don't look through
7566 TRUNCATE. See PR82192. */
7567 && pos_rtx
== NULL_RTX
7568 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
)))
7569 inner
= XEXP (inner
, 0);
7571 inner_mode
= GET_MODE (inner
);
7573 /* See if this can be done without an extraction. We never can if the
7574 width of the field is not the same as that of some integer mode. For
7575 registers, we can only avoid the extraction if the position is at the
7576 low-order bit and this is either not in the destination or we have the
7577 appropriate STRICT_LOW_PART operation available.
7579 For MEM, we can avoid an extract if the field starts on an appropriate
7580 boundary and we can change the mode of the memory reference. */
7582 scalar_int_mode tmode
;
7583 if (int_mode_for_size (len
, 1).exists (&tmode
)
7584 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7586 && (pos
== 0 || REG_P (inner
))
7587 && (inner_mode
== tmode
7589 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7590 || reg_truncated_to_mode (tmode
, inner
))
7593 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7594 || (MEM_P (inner
) && pos_rtx
== 0
7596 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7597 : BITS_PER_UNIT
)) == 0
7598 /* We can't do this if we are widening INNER_MODE (it
7599 may not be aligned, for one thing). */
7600 && !paradoxical_subreg_p (tmode
, inner_mode
)
7601 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
))
7602 && (inner_mode
== tmode
7603 || (! mode_dependent_address_p (XEXP (inner
, 0),
7604 MEM_ADDR_SPACE (inner
))
7605 && ! MEM_VOLATILE_P (inner
))))))
7607 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7608 field. If the original and current mode are the same, we need not
7609 adjust the offset. Otherwise, we do if bytes big endian.
7611 If INNER is not a MEM, get a piece consisting of just the field
7612 of interest (in this case POS % BITS_PER_WORD must be 0). */
7618 /* POS counts from lsb, but make OFFSET count in memory order. */
7619 if (BYTES_BIG_ENDIAN
)
7620 offset
= bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode
)
7623 offset
= pos
/ BITS_PER_UNIT
;
7625 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7627 else if (REG_P (inner
))
7629 if (tmode
!= inner_mode
)
7631 /* We can't call gen_lowpart in a DEST since we
7632 always want a SUBREG (see below) and it would sometimes
7633 return a new hard register. */
7637 = subreg_offset_from_lsb (tmode
, inner_mode
, pos
);
7639 /* Avoid creating invalid subregs, for example when
7640 simplifying (x>>32)&255. */
7641 if (!validate_subreg (tmode
, inner_mode
, inner
, offset
))
7644 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, offset
);
7647 new_rtx
= gen_lowpart (tmode
, inner
);
7653 new_rtx
= force_to_mode (inner
, tmode
,
7654 len
>= HOST_BITS_PER_WIDE_INT
7656 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7658 /* If this extraction is going into the destination of a SET,
7659 make a STRICT_LOW_PART unless we made a MEM. */
7662 return (MEM_P (new_rtx
) ? new_rtx
7663 : (GET_CODE (new_rtx
) != SUBREG
7664 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7665 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7670 if (CONST_SCALAR_INT_P (new_rtx
))
7671 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7672 mode
, new_rtx
, tmode
);
7674 /* If we know that no extraneous bits are set, and that the high
7675 bit is not set, convert the extraction to the cheaper of
7676 sign and zero extension, that are equivalent in these cases. */
7677 if (flag_expensive_optimizations
7678 && (HWI_COMPUTABLE_MODE_P (tmode
)
7679 && ((nonzero_bits (new_rtx
, tmode
)
7680 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7683 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7684 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7686 /* Prefer ZERO_EXTENSION, since it gives more information to
7688 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7689 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7694 /* Otherwise, sign- or zero-extend unless we already are in the
7697 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7701 /* Unless this is a COMPARE or we have a funny memory reference,
7702 don't do anything with zero-extending field extracts starting at
7703 the low-order bit since they are simple AND operations. */
7704 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7705 && ! in_compare
&& unsignedp
)
7708 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7709 if the position is not a constant and the length is not 1. In all
7710 other cases, we would only be going outside our object in cases when
7711 an original shift would have been undefined. */
7713 && ((pos_rtx
== 0 && maybe_gt (pos
+ len
, GET_MODE_PRECISION (is_mode
)))
7714 || (pos_rtx
!= 0 && len
!= 1)))
7717 enum extraction_pattern pattern
= (in_dest
? EP_insv
7718 : unsignedp
? EP_extzv
: EP_extv
);
7720 /* If INNER is not from memory, we want it to have the mode of a register
7721 extraction pattern's structure operand, or word_mode if there is no
7722 such pattern. The same applies to extraction_mode and pos_mode
7723 and their respective operands.
7725 For memory, assume that the desired extraction_mode and pos_mode
7726 are the same as for a register operation, since at present we don't
7727 have named patterns for aligned memory structures. */
7728 class extraction_insn insn
;
7729 unsigned int inner_size
;
7730 if (GET_MODE_BITSIZE (inner_mode
).is_constant (&inner_size
)
7731 && get_best_reg_extraction_insn (&insn
, pattern
, inner_size
, mode
))
7733 wanted_inner_reg_mode
= insn
.struct_mode
.require ();
7734 pos_mode
= insn
.pos_mode
;
7735 extraction_mode
= insn
.field_mode
;
7738 /* Never narrow an object, since that might not be safe. */
7740 if (mode
!= VOIDmode
7741 && partial_subreg_p (extraction_mode
, mode
))
7742 extraction_mode
= mode
;
7744 /* Punt if len is too large for extraction_mode. */
7745 if (maybe_gt (len
, GET_MODE_PRECISION (extraction_mode
)))
7749 wanted_inner_mode
= wanted_inner_reg_mode
;
7752 /* Be careful not to go beyond the extracted object and maintain the
7753 natural alignment of the memory. */
7754 wanted_inner_mode
= smallest_int_mode_for_size (len
);
7755 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7756 > GET_MODE_BITSIZE (wanted_inner_mode
))
7757 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
).require ();
7762 if (BITS_BIG_ENDIAN
)
7764 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7765 BITS_BIG_ENDIAN style. If position is constant, compute new
7766 position. Otherwise, build subtraction.
7767 Note that POS is relative to the mode of the original argument.
7768 If it's a MEM we need to recompute POS relative to that.
7769 However, if we're extracting from (or inserting into) a register,
7770 we want to recompute POS relative to wanted_inner_mode. */
7773 width
= GET_MODE_BITSIZE (wanted_inner_mode
);
7774 else if (!GET_MODE_BITSIZE (is_mode
).is_constant (&width
))
7778 pos
= width
- len
- pos
;
7781 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7782 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7784 /* POS may be less than 0 now, but we check for that below.
7785 Note that it can only be less than 0 if !MEM_P (inner). */
7788 /* If INNER has a wider mode, and this is a constant extraction, try to
7789 make it smaller and adjust the byte to point to the byte containing
7791 if (wanted_inner_mode
!= VOIDmode
7792 && inner_mode
!= wanted_inner_mode
7794 && partial_subreg_p (wanted_inner_mode
, is_mode
)
7796 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7797 && ! MEM_VOLATILE_P (inner
))
7799 poly_int64 offset
= 0;
7801 /* The computations below will be correct if the machine is big
7802 endian in both bits and bytes or little endian in bits and bytes.
7803 If it is mixed, we must adjust. */
7805 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7806 adjust OFFSET to compensate. */
7807 if (BYTES_BIG_ENDIAN
7808 && paradoxical_subreg_p (is_mode
, inner_mode
))
7809 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7811 /* We can now move to the desired byte. */
7812 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7813 * GET_MODE_SIZE (wanted_inner_mode
);
7814 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7816 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7817 && is_mode
!= wanted_inner_mode
)
7818 offset
= (GET_MODE_SIZE (is_mode
)
7819 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7821 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7824 /* If INNER is not memory, get it into the proper mode. If we are changing
7825 its mode, POS must be a constant and smaller than the size of the new
7827 else if (!MEM_P (inner
))
7829 /* On the LHS, don't create paradoxical subregs implicitely truncating
7830 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7832 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7836 if (GET_MODE (inner
) != wanted_inner_mode
7838 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7844 inner
= force_to_mode (inner
, wanted_inner_mode
,
7846 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7848 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7853 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7854 have to zero extend. Otherwise, we can just use a SUBREG.
7856 We dealt with constant rtxes earlier, so pos_rtx cannot
7857 have VOIDmode at this point. */
7859 && (GET_MODE_SIZE (pos_mode
)
7860 > GET_MODE_SIZE (as_a
<scalar_int_mode
> (GET_MODE (pos_rtx
)))))
7862 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7863 GET_MODE (pos_rtx
));
7865 /* If we know that no extraneous bits are set, and that the high
7866 bit is not set, convert extraction to cheaper one - either
7867 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7869 if (flag_expensive_optimizations
7870 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7871 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7872 & ~(((unsigned HOST_WIDE_INT
)
7873 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7877 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7878 GET_MODE (pos_rtx
));
7880 /* Prefer ZERO_EXTENSION, since it gives more information to
7882 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7883 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7889 /* Make POS_RTX unless we already have it and it is correct. If we don't
7890 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7892 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7893 pos_rtx
= orig_pos_rtx
;
7895 else if (pos_rtx
== 0)
7896 pos_rtx
= GEN_INT (pos
);
7898 /* Make the required operation. See if we can use existing rtx. */
7899 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7900 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7902 new_rtx
= gen_lowpart (mode
, new_rtx
);
7907 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7908 can be commuted with any other operations in X. Return X without
7909 that shift if so. */
7912 extract_left_shift (scalar_int_mode mode
, rtx x
, int count
)
7914 enum rtx_code code
= GET_CODE (x
);
7920 /* This is the shift itself. If it is wide enough, we will return
7921 either the value being shifted if the shift count is equal to
7922 COUNT or a shift for the difference. */
7923 if (CONST_INT_P (XEXP (x
, 1))
7924 && INTVAL (XEXP (x
, 1)) >= count
)
7925 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7926 INTVAL (XEXP (x
, 1)) - count
);
7930 if ((tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
7931 return simplify_gen_unary (code
, mode
, tem
, mode
);
7935 case PLUS
: case IOR
: case XOR
: case AND
:
7936 /* If we can safely shift this constant and we find the inner shift,
7937 make a new operation. */
7938 if (CONST_INT_P (XEXP (x
, 1))
7939 && (UINTVAL (XEXP (x
, 1))
7940 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7941 && (tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
7943 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7944 return simplify_gen_binary (code
, mode
, tem
,
7945 gen_int_mode (val
, mode
));
7956 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7957 level of the expression and MODE is its mode. IN_CODE is as for
7958 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7959 that should be used when recursing on operands of *X_PTR.
7961 There are two possible actions:
7963 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7964 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7966 - Return a new rtx, which the caller returns directly. */
7969 make_compound_operation_int (scalar_int_mode mode
, rtx
*x_ptr
,
7970 enum rtx_code in_code
,
7971 enum rtx_code
*next_code_ptr
)
7974 enum rtx_code next_code
= *next_code_ptr
;
7975 enum rtx_code code
= GET_CODE (x
);
7976 int mode_width
= GET_MODE_PRECISION (mode
);
7981 scalar_int_mode inner_mode
;
7982 bool equality_comparison
= false;
7986 equality_comparison
= true;
7990 /* Process depending on the code of this operation. If NEW is set
7991 nonzero, it will be returned. */
7996 /* Convert shifts by constants into multiplications if inside
7998 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7999 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8000 && INTVAL (XEXP (x
, 1)) >= 0)
8002 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
8003 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
8005 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8006 if (GET_CODE (new_rtx
) == NEG
)
8008 new_rtx
= XEXP (new_rtx
, 0);
8011 multval
= trunc_int_for_mode (multval
, mode
);
8012 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
8019 lhs
= make_compound_operation (lhs
, next_code
);
8020 rhs
= make_compound_operation (rhs
, next_code
);
8021 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
8023 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
8025 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8027 else if (GET_CODE (lhs
) == MULT
8028 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
8030 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
8031 simplify_gen_unary (NEG
, mode
,
8034 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8038 SUBST (XEXP (x
, 0), lhs
);
8039 SUBST (XEXP (x
, 1), rhs
);
8041 maybe_swap_commutative_operands (x
);
8047 lhs
= make_compound_operation (lhs
, next_code
);
8048 rhs
= make_compound_operation (rhs
, next_code
);
8049 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
8051 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
8053 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8055 else if (GET_CODE (rhs
) == MULT
8056 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
8058 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
8059 simplify_gen_unary (NEG
, mode
,
8062 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8066 SUBST (XEXP (x
, 0), lhs
);
8067 SUBST (XEXP (x
, 1), rhs
);
8072 /* If the second operand is not a constant, we can't do anything
8074 if (!CONST_INT_P (XEXP (x
, 1)))
8077 /* If the constant is a power of two minus one and the first operand
8078 is a logical right shift, make an extraction. */
8079 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8080 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8082 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8083 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1),
8084 i
, 1, 0, in_code
== COMPARE
);
8087 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8088 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
8089 && subreg_lowpart_p (XEXP (x
, 0))
8090 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (XEXP (x
, 0))),
8092 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
8093 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8095 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
8096 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
8097 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
8099 i
, 1, 0, in_code
== COMPARE
);
8101 /* If we narrowed the mode when dropping the subreg, then we lose. */
8102 if (GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (mode
))
8105 /* If that didn't give anything, see if the AND simplifies on
8107 if (!new_rtx
&& i
>= 0)
8109 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8110 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
8111 0, in_code
== COMPARE
);
8114 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8115 else if ((GET_CODE (XEXP (x
, 0)) == XOR
8116 || GET_CODE (XEXP (x
, 0)) == IOR
)
8117 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
8118 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
8119 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8121 /* Apply the distributive law, and then try to make extractions. */
8122 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
8123 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
8125 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
8127 new_rtx
= make_compound_operation (new_rtx
, in_code
);
8130 /* If we are have (and (rotate X C) M) and C is larger than the number
8131 of bits in M, this is an extraction. */
8133 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
8134 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8135 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
8136 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
8138 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8139 new_rtx
= make_extraction (mode
, new_rtx
,
8140 (GET_MODE_PRECISION (mode
)
8141 - INTVAL (XEXP (XEXP (x
, 0), 1))),
8142 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8145 /* On machines without logical shifts, if the operand of the AND is
8146 a logical shift and our mask turns off all the propagated sign
8147 bits, we can replace the logical shift with an arithmetic shift. */
8148 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8149 && !have_insn_for (LSHIFTRT
, mode
)
8150 && have_insn_for (ASHIFTRT
, mode
)
8151 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8152 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8153 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8154 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8156 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8158 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8159 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8161 gen_rtx_ASHIFTRT (mode
,
8162 make_compound_operation (XEXP (XEXP (x
,
8166 XEXP (XEXP (x
, 0), 1)));
8169 /* If the constant is one less than a power of two, this might be
8170 representable by an extraction even if no shift is present.
8171 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8172 we are in a COMPARE. */
8173 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8174 new_rtx
= make_extraction (mode
,
8175 make_compound_operation (XEXP (x
, 0),
8177 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8179 /* If we are in a comparison and this is an AND with a power of two,
8180 convert this into the appropriate bit extract. */
8181 else if (in_code
== COMPARE
8182 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8183 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8184 new_rtx
= make_extraction (mode
,
8185 make_compound_operation (XEXP (x
, 0),
8187 i
, NULL_RTX
, 1, 1, 0, 1);
8189 /* If the one operand is a paradoxical subreg of a register or memory and
8190 the constant (limited to the smaller mode) has only zero bits where
8191 the sub expression has known zero bits, this can be expressed as
8193 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8197 sub
= XEXP (XEXP (x
, 0), 0);
8198 machine_mode sub_mode
= GET_MODE (sub
);
8200 if ((REG_P (sub
) || MEM_P (sub
))
8201 && GET_MODE_PRECISION (sub_mode
).is_constant (&sub_width
)
8202 && sub_width
< mode_width
)
8204 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8205 unsigned HOST_WIDE_INT mask
;
8207 /* original AND constant with all the known zero bits set */
8208 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8209 if ((mask
& mode_mask
) == mode_mask
)
8211 new_rtx
= make_compound_operation (sub
, next_code
);
8212 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0, sub_width
,
8213 1, 0, in_code
== COMPARE
);
8221 /* If the sign bit is known to be zero, replace this with an
8222 arithmetic shift. */
8223 if (have_insn_for (ASHIFTRT
, mode
)
8224 && ! have_insn_for (LSHIFTRT
, mode
)
8225 && mode_width
<= HOST_BITS_PER_WIDE_INT
8226 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8228 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8229 make_compound_operation (XEXP (x
, 0),
8241 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8242 this is a SIGN_EXTRACT. */
8243 if (CONST_INT_P (rhs
)
8244 && GET_CODE (lhs
) == ASHIFT
8245 && CONST_INT_P (XEXP (lhs
, 1))
8246 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8247 && INTVAL (XEXP (lhs
, 1)) >= 0
8248 && INTVAL (rhs
) < mode_width
)
8250 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8251 new_rtx
= make_extraction (mode
, new_rtx
,
8252 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8253 NULL_RTX
, mode_width
- INTVAL (rhs
),
8254 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8258 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8259 If so, try to merge the shifts into a SIGN_EXTEND. We could
8260 also do this for some cases of SIGN_EXTRACT, but it doesn't
8261 seem worth the effort; the case checked for occurs on Alpha. */
8264 && ! (GET_CODE (lhs
) == SUBREG
8265 && (OBJECT_P (SUBREG_REG (lhs
))))
8266 && CONST_INT_P (rhs
)
8267 && INTVAL (rhs
) >= 0
8268 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8269 && INTVAL (rhs
) < mode_width
8270 && (new_rtx
= extract_left_shift (mode
, lhs
, INTVAL (rhs
))) != 0)
8271 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
,
8273 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8274 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8279 /* Call ourselves recursively on the inner expression. If we are
8280 narrowing the object and it has a different RTL code from
8281 what it originally did, do this SUBREG as a force_to_mode. */
8283 rtx inner
= SUBREG_REG (x
), simplified
;
8284 enum rtx_code subreg_code
= in_code
;
8286 /* If the SUBREG is masking of a logical right shift,
8287 make an extraction. */
8288 if (GET_CODE (inner
) == LSHIFTRT
8289 && is_a
<scalar_int_mode
> (GET_MODE (inner
), &inner_mode
)
8290 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (inner_mode
)
8291 && CONST_INT_P (XEXP (inner
, 1))
8292 && UINTVAL (XEXP (inner
, 1)) < GET_MODE_PRECISION (inner_mode
)
8293 && subreg_lowpart_p (x
))
8295 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8296 int width
= GET_MODE_PRECISION (inner_mode
)
8297 - INTVAL (XEXP (inner
, 1));
8298 if (width
> mode_width
)
8300 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8301 width
, 1, 0, in_code
== COMPARE
);
8305 /* If in_code is COMPARE, it isn't always safe to pass it through
8306 to the recursive make_compound_operation call. */
8307 if (subreg_code
== COMPARE
8308 && (!subreg_lowpart_p (x
)
8309 || GET_CODE (inner
) == SUBREG
8310 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8311 is (const_int 0), rather than
8312 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8313 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8314 for non-equality comparisons against 0 is not equivalent
8315 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8316 || (GET_CODE (inner
) == AND
8317 && CONST_INT_P (XEXP (inner
, 1))
8318 && partial_subreg_p (x
)
8319 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8320 >= GET_MODE_BITSIZE (mode
) - 1)))
8323 tem
= make_compound_operation (inner
, subreg_code
);
8326 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8330 if (GET_CODE (tem
) != GET_CODE (inner
)
8331 && partial_subreg_p (x
)
8332 && subreg_lowpart_p (x
))
8335 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8337 /* If we have something other than a SUBREG, we might have
8338 done an expansion, so rerun ourselves. */
8339 if (GET_CODE (newer
) != SUBREG
)
8340 newer
= make_compound_operation (newer
, in_code
);
8342 /* force_to_mode can expand compounds. If it just re-expanded
8343 the compound, use gen_lowpart to convert to the desired
8345 if (rtx_equal_p (newer
, x
)
8346 /* Likewise if it re-expanded the compound only partially.
8347 This happens for SUBREG of ZERO_EXTRACT if they extract
8348 the same number of bits. */
8349 || (GET_CODE (newer
) == SUBREG
8350 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8351 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8352 && GET_CODE (inner
) == AND
8353 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8354 return gen_lowpart (GET_MODE (x
), tem
);
8369 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8370 *next_code_ptr
= next_code
;
8374 /* Look at the expression rooted at X. Look for expressions
8375 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8376 Form these expressions.
8378 Return the new rtx, usually just X.
8380 Also, for machines like the VAX that don't have logical shift insns,
8381 try to convert logical to arithmetic shift operations in cases where
8382 they are equivalent. This undoes the canonicalizations to logical
8383 shifts done elsewhere.
8385 We try, as much as possible, to re-use rtl expressions to save memory.
8387 IN_CODE says what kind of expression we are processing. Normally, it is
8388 SET. In a memory address it is MEM. When processing the arguments of
8389 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8390 precisely it is an equality comparison against zero. */
8393 make_compound_operation (rtx x
, enum rtx_code in_code
)
8395 enum rtx_code code
= GET_CODE (x
);
8398 enum rtx_code next_code
;
8401 /* Select the code to be used in recursive calls. Once we are inside an
8402 address, we stay there. If we have a comparison, set to COMPARE,
8403 but once inside, go back to our default of SET. */
8405 next_code
= (code
== MEM
? MEM
8406 : ((code
== COMPARE
|| COMPARISON_P (x
))
8407 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8408 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8410 scalar_int_mode mode
;
8411 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
8413 rtx new_rtx
= make_compound_operation_int (mode
, &x
, in_code
,
8417 code
= GET_CODE (x
);
8420 /* Now recursively process each operand of this operation. We need to
8421 handle ZERO_EXTEND specially so that we don't lose track of the
8423 if (code
== ZERO_EXTEND
)
8425 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8426 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8427 new_rtx
, GET_MODE (XEXP (x
, 0)));
8430 SUBST (XEXP (x
, 0), new_rtx
);
8434 fmt
= GET_RTX_FORMAT (code
);
8435 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8438 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8439 SUBST (XEXP (x
, i
), new_rtx
);
8441 else if (fmt
[i
] == 'E')
8442 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8444 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8445 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8448 maybe_swap_commutative_operands (x
);
8452 /* Given M see if it is a value that would select a field of bits
8453 within an item, but not the entire word. Return -1 if not.
8454 Otherwise, return the starting position of the field, where 0 is the
8457 *PLEN is set to the length of the field. */
8460 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8462 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8463 int pos
= m
? ctz_hwi (m
) : -1;
8467 /* Now shift off the low-order zero bits and see if we have a
8468 power of two minus 1. */
8469 len
= exact_log2 ((m
>> pos
) + 1);
8478 /* If X refers to a register that equals REG in value, replace these
8479 references with REG. */
8481 canon_reg_for_combine (rtx x
, rtx reg
)
8488 enum rtx_code code
= GET_CODE (x
);
8489 switch (GET_RTX_CLASS (code
))
8492 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8493 if (op0
!= XEXP (x
, 0))
8494 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8499 case RTX_COMM_ARITH
:
8500 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8501 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8502 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8503 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8507 case RTX_COMM_COMPARE
:
8508 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8509 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8510 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8511 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8512 GET_MODE (op0
), op0
, op1
);
8516 case RTX_BITFIELD_OPS
:
8517 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8518 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8519 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8520 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8521 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8522 GET_MODE (op0
), op0
, op1
, op2
);
8528 if (rtx_equal_p (get_last_value (reg
), x
)
8529 || rtx_equal_p (reg
, get_last_value (x
)))
8538 fmt
= GET_RTX_FORMAT (code
);
8540 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8543 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8544 if (op
!= XEXP (x
, i
))
8554 else if (fmt
[i
] == 'E')
8557 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8559 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8560 if (op
!= XVECEXP (x
, i
, j
))
8567 XVECEXP (x
, i
, j
) = op
;
8578 /* Return X converted to MODE. If the value is already truncated to
8579 MODE we can just return a subreg even though in the general case we
8580 would need an explicit truncation. */
8583 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8585 if (!CONST_INT_P (x
)
8586 && partial_subreg_p (mode
, GET_MODE (x
))
8587 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8588 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8590 /* Bit-cast X into an integer mode. */
8591 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8592 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)).require (), x
);
8593 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
).require (),
8597 return gen_lowpart (mode
, x
);
8600 /* See if X can be simplified knowing that we will only refer to it in
8601 MODE and will only refer to those bits that are nonzero in MASK.
8602 If other bits are being computed or if masking operations are done
8603 that select a superset of the bits in MASK, they can sometimes be
8606 Return a possibly simplified expression, but always convert X to
8607 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8609 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8610 are all off in X. This is used when X will be complemented, by either
8611 NOT, NEG, or XOR. */
8614 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8617 enum rtx_code code
= GET_CODE (x
);
8618 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8619 machine_mode op_mode
;
8620 unsigned HOST_WIDE_INT nonzero
;
8622 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8623 code below will do the wrong thing since the mode of such an
8624 expression is VOIDmode.
8626 Also do nothing if X is a CLOBBER; this can happen if X was
8627 the return value from a call to gen_lowpart. */
8628 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8631 /* We want to perform the operation in its present mode unless we know
8632 that the operation is valid in MODE, in which case we do the operation
8634 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8635 && have_insn_for (code
, mode
))
8636 ? mode
: GET_MODE (x
));
8638 /* It is not valid to do a right-shift in a narrower mode
8639 than the one it came in with. */
8640 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8641 && partial_subreg_p (mode
, GET_MODE (x
)))
8642 op_mode
= GET_MODE (x
);
8644 /* Truncate MASK to fit OP_MODE. */
8646 mask
&= GET_MODE_MASK (op_mode
);
8648 /* Determine what bits of X are guaranteed to be (non)zero. */
8649 nonzero
= nonzero_bits (x
, mode
);
8651 /* If none of the bits in X are needed, return a zero. */
8652 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8655 /* If X is a CONST_INT, return a new one. Do this here since the
8656 test below will fail. */
8657 if (CONST_INT_P (x
))
8659 if (SCALAR_INT_MODE_P (mode
))
8660 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8663 x
= GEN_INT (INTVAL (x
) & mask
);
8664 return gen_lowpart_common (mode
, x
);
8668 /* If X is narrower than MODE and we want all the bits in X's mode, just
8669 get X in the proper mode. */
8670 if (paradoxical_subreg_p (mode
, GET_MODE (x
))
8671 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8672 return gen_lowpart (mode
, x
);
8674 /* We can ignore the effect of a SUBREG if it narrows the mode or
8675 if the constant masks to zero all the bits the mode doesn't have. */
8676 if (GET_CODE (x
) == SUBREG
8677 && subreg_lowpart_p (x
)
8678 && (partial_subreg_p (x
)
8680 & GET_MODE_MASK (GET_MODE (x
))
8681 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))) == 0))
8682 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8684 scalar_int_mode int_mode
, xmode
;
8685 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
8686 && is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
8687 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8689 return force_int_to_mode (x
, int_mode
, xmode
,
8690 as_a
<scalar_int_mode
> (op_mode
),
8693 return gen_lowpart_or_truncate (mode
, x
);
8696 /* Subroutine of force_to_mode that handles cases in which both X and
8697 the result are scalar integers. MODE is the mode of the result,
8698 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8699 is preferred for simplified versions of X. The other arguments
8700 are as for force_to_mode. */
8703 force_int_to_mode (rtx x
, scalar_int_mode mode
, scalar_int_mode xmode
,
8704 scalar_int_mode op_mode
, unsigned HOST_WIDE_INT mask
,
8707 enum rtx_code code
= GET_CODE (x
);
8708 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8709 unsigned HOST_WIDE_INT fuller_mask
;
8711 poly_int64 const_op0
;
8713 /* When we have an arithmetic operation, or a shift whose count we
8714 do not know, we need to assume that all bits up to the highest-order
8715 bit in MASK will be needed. This is how we form such a mask. */
8716 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8717 fuller_mask
= HOST_WIDE_INT_M1U
;
8719 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8725 /* If X is a (clobber (const_int)), return it since we know we are
8726 generating something that won't match. */
8733 x
= expand_compound_operation (x
);
8734 if (GET_CODE (x
) != code
)
8735 return force_to_mode (x
, mode
, mask
, next_select
);
8739 /* Similarly for a truncate. */
8740 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8743 /* If this is an AND with a constant, convert it into an AND
8744 whose constant is the AND of that constant with MASK. If it
8745 remains an AND of MASK, delete it since it is redundant. */
8747 if (CONST_INT_P (XEXP (x
, 1)))
8749 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8750 mask
& INTVAL (XEXP (x
, 1)));
8753 /* If X is still an AND, see if it is an AND with a mask that
8754 is just some low-order bits. If so, and it is MASK, we don't
8757 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8758 && (INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (xmode
)) == mask
)
8761 /* If it remains an AND, try making another AND with the bits
8762 in the mode mask that aren't in MASK turned on. If the
8763 constant in the AND is wide enough, this might make a
8764 cheaper constant. */
8766 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8767 && GET_MODE_MASK (xmode
) != mask
8768 && HWI_COMPUTABLE_MODE_P (xmode
))
8770 unsigned HOST_WIDE_INT cval
8771 = UINTVAL (XEXP (x
, 1)) | (GET_MODE_MASK (xmode
) & ~mask
);
8774 y
= simplify_gen_binary (AND
, xmode
, XEXP (x
, 0),
8775 gen_int_mode (cval
, xmode
));
8776 if (set_src_cost (y
, xmode
, optimize_this_for_speed_p
)
8777 < set_src_cost (x
, xmode
, optimize_this_for_speed_p
))
8787 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8788 low-order bits (as in an alignment operation) and FOO is already
8789 aligned to that boundary, mask C1 to that boundary as well.
8790 This may eliminate that PLUS and, later, the AND. */
8793 unsigned int width
= GET_MODE_PRECISION (mode
);
8794 unsigned HOST_WIDE_INT smask
= mask
;
8796 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8797 number, sign extend it. */
8799 if (width
< HOST_BITS_PER_WIDE_INT
8800 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8801 smask
|= HOST_WIDE_INT_M1U
<< width
;
8803 if (CONST_INT_P (XEXP (x
, 1))
8804 && pow2p_hwi (- smask
)
8805 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8806 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8807 return force_to_mode (plus_constant (xmode
, XEXP (x
, 0),
8808 (INTVAL (XEXP (x
, 1)) & smask
)),
8809 mode
, smask
, next_select
);
8815 /* Substituting into the operands of a widening MULT is not likely to
8816 create RTL matching a machine insn. */
8818 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8819 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8820 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8821 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8822 && REG_P (XEXP (XEXP (x
, 0), 0))
8823 && REG_P (XEXP (XEXP (x
, 1), 0)))
8824 return gen_lowpart_or_truncate (mode
, x
);
8826 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8827 most significant bit in MASK since carries from those bits will
8828 affect the bits we are interested in. */
8833 /* If X is (minus C Y) where C's least set bit is larger than any bit
8834 in the mask, then we may replace with (neg Y). */
8835 if (poly_int_rtx_p (XEXP (x
, 0), &const_op0
)
8836 && known_alignment (poly_uint64 (const_op0
)) > mask
)
8838 x
= simplify_gen_unary (NEG
, xmode
, XEXP (x
, 1), xmode
);
8839 return force_to_mode (x
, mode
, mask
, next_select
);
8842 /* Similarly, if C contains every bit in the fuller_mask, then we may
8843 replace with (not Y). */
8844 if (CONST_INT_P (XEXP (x
, 0))
8845 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8847 x
= simplify_gen_unary (NOT
, xmode
, XEXP (x
, 1), xmode
);
8848 return force_to_mode (x
, mode
, mask
, next_select
);
8856 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8857 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8858 operation which may be a bitfield extraction. Ensure that the
8859 constant we form is not wider than the mode of X. */
8861 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8862 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8863 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8864 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8865 && CONST_INT_P (XEXP (x
, 1))
8866 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8867 + floor_log2 (INTVAL (XEXP (x
, 1))))
8868 < GET_MODE_PRECISION (xmode
))
8869 && (UINTVAL (XEXP (x
, 1))
8870 & ~nonzero_bits (XEXP (x
, 0), xmode
)) == 0)
8872 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8873 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8875 temp
= simplify_gen_binary (GET_CODE (x
), xmode
,
8876 XEXP (XEXP (x
, 0), 0), temp
);
8877 x
= simplify_gen_binary (LSHIFTRT
, xmode
, temp
,
8878 XEXP (XEXP (x
, 0), 1));
8879 return force_to_mode (x
, mode
, mask
, next_select
);
8883 /* For most binary operations, just propagate into the operation and
8884 change the mode if we have an operation of that mode. */
8886 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8887 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8889 /* If we ended up truncating both operands, truncate the result of the
8890 operation instead. */
8891 if (GET_CODE (op0
) == TRUNCATE
8892 && GET_CODE (op1
) == TRUNCATE
)
8894 op0
= XEXP (op0
, 0);
8895 op1
= XEXP (op1
, 0);
8898 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8899 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8901 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8903 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8909 /* For left shifts, do the same, but just for the first operand.
8910 However, we cannot do anything with shifts where we cannot
8911 guarantee that the counts are smaller than the size of the mode
8912 because such a count will have a different meaning in a
8915 if (! (CONST_INT_P (XEXP (x
, 1))
8916 && INTVAL (XEXP (x
, 1)) >= 0
8917 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8918 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8919 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8920 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8923 /* If the shift count is a constant and we can do arithmetic in
8924 the mode of the shift, refine which bits we need. Otherwise, use the
8925 conservative form of the mask. */
8926 if (CONST_INT_P (XEXP (x
, 1))
8927 && INTVAL (XEXP (x
, 1)) >= 0
8928 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8929 && HWI_COMPUTABLE_MODE_P (op_mode
))
8930 mask
>>= INTVAL (XEXP (x
, 1));
8934 op0
= gen_lowpart_or_truncate (op_mode
,
8935 force_to_mode (XEXP (x
, 0), mode
,
8936 mask
, next_select
));
8938 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
8940 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8946 /* Here we can only do something if the shift count is a constant,
8947 this shift constant is valid for the host, and we can do arithmetic
8950 if (CONST_INT_P (XEXP (x
, 1))
8951 && INTVAL (XEXP (x
, 1)) >= 0
8952 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8953 && HWI_COMPUTABLE_MODE_P (op_mode
))
8955 rtx inner
= XEXP (x
, 0);
8956 unsigned HOST_WIDE_INT inner_mask
;
8958 /* Select the mask of the bits we need for the shift operand. */
8959 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8961 /* We can only change the mode of the shift if we can do arithmetic
8962 in the mode of the shift and INNER_MASK is no wider than the
8963 width of X's mode. */
8964 if ((inner_mask
& ~GET_MODE_MASK (xmode
)) != 0)
8967 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8969 if (xmode
!= op_mode
|| inner
!= XEXP (x
, 0))
8971 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8976 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8977 shift and AND produces only copies of the sign bit (C2 is one less
8978 than a power of two), we can do this with just a shift. */
8980 if (GET_CODE (x
) == LSHIFTRT
8981 && CONST_INT_P (XEXP (x
, 1))
8982 /* The shift puts one of the sign bit copies in the least significant
8984 && ((INTVAL (XEXP (x
, 1))
8985 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8986 >= GET_MODE_PRECISION (xmode
))
8987 && pow2p_hwi (mask
+ 1)
8988 /* Number of bits left after the shift must be more than the mask
8990 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8991 <= GET_MODE_PRECISION (xmode
))
8992 /* Must be more sign bit copies than the mask needs. */
8993 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8994 >= exact_log2 (mask
+ 1)))
8996 int nbits
= GET_MODE_PRECISION (xmode
) - exact_log2 (mask
+ 1);
8997 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0),
8998 gen_int_shift_amount (xmode
, nbits
));
9003 /* If we are just looking for the sign bit, we don't need this shift at
9004 all, even if it has a variable count. */
9005 if (val_signbit_p (xmode
, mask
))
9006 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9008 /* If this is a shift by a constant, get a mask that contains those bits
9009 that are not copies of the sign bit. We then have two cases: If
9010 MASK only includes those bits, this can be a logical shift, which may
9011 allow simplifications. If MASK is a single-bit field not within
9012 those bits, we are requesting a copy of the sign bit and hence can
9013 shift the sign bit to the appropriate location. */
9015 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
9016 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
9018 unsigned HOST_WIDE_INT nonzero
;
9021 /* If the considered data is wider than HOST_WIDE_INT, we can't
9022 represent a mask for all its bits in a single scalar.
9023 But we only care about the lower bits, so calculate these. */
9025 if (GET_MODE_PRECISION (xmode
) > HOST_BITS_PER_WIDE_INT
)
9027 nonzero
= HOST_WIDE_INT_M1U
;
9029 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9030 is the number of bits a full-width mask would have set.
9031 We need only shift if these are fewer than nonzero can
9032 hold. If not, we must keep all bits set in nonzero. */
9034 if (GET_MODE_PRECISION (xmode
) - INTVAL (XEXP (x
, 1))
9035 < HOST_BITS_PER_WIDE_INT
)
9036 nonzero
>>= INTVAL (XEXP (x
, 1))
9037 + HOST_BITS_PER_WIDE_INT
9038 - GET_MODE_PRECISION (xmode
);
9042 nonzero
= GET_MODE_MASK (xmode
);
9043 nonzero
>>= INTVAL (XEXP (x
, 1));
9046 if ((mask
& ~nonzero
) == 0)
9048 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, xmode
,
9049 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
9050 if (GET_CODE (x
) != ASHIFTRT
)
9051 return force_to_mode (x
, mode
, mask
, next_select
);
9054 else if ((i
= exact_log2 (mask
)) >= 0)
9056 x
= simplify_shift_const
9057 (NULL_RTX
, LSHIFTRT
, xmode
, XEXP (x
, 0),
9058 GET_MODE_PRECISION (xmode
) - 1 - i
);
9060 if (GET_CODE (x
) != ASHIFTRT
)
9061 return force_to_mode (x
, mode
, mask
, next_select
);
9065 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9066 even if the shift count isn't a constant. */
9068 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0), XEXP (x
, 1));
9072 /* If this is a zero- or sign-extension operation that just affects bits
9073 we don't care about, remove it. Be sure the call above returned
9074 something that is still a shift. */
9076 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
9077 && CONST_INT_P (XEXP (x
, 1))
9078 && INTVAL (XEXP (x
, 1)) >= 0
9079 && (INTVAL (XEXP (x
, 1))
9080 <= GET_MODE_PRECISION (xmode
) - (floor_log2 (mask
) + 1))
9081 && GET_CODE (XEXP (x
, 0)) == ASHIFT
9082 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
9083 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
9090 /* If the shift count is constant and we can do computations
9091 in the mode of X, compute where the bits we care about are.
9092 Otherwise, we can't do anything. Don't change the mode of
9093 the shift or propagate MODE into the shift, though. */
9094 if (CONST_INT_P (XEXP (x
, 1))
9095 && INTVAL (XEXP (x
, 1)) >= 0)
9097 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
9098 xmode
, gen_int_mode (mask
, xmode
),
9100 if (temp
&& CONST_INT_P (temp
))
9101 x
= simplify_gen_binary (code
, xmode
,
9102 force_to_mode (XEXP (x
, 0), xmode
,
9103 INTVAL (temp
), next_select
),
9109 /* If we just want the low-order bit, the NEG isn't needed since it
9110 won't change the low-order bit. */
9112 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
9114 /* We need any bits less significant than the most significant bit in
9115 MASK since carries from those bits will affect the bits we are
9121 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9122 same as the XOR case above. Ensure that the constant we form is not
9123 wider than the mode of X. */
9125 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
9126 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
9127 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
9128 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
9129 < GET_MODE_PRECISION (xmode
))
9130 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
9132 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)), xmode
);
9133 temp
= simplify_gen_binary (XOR
, xmode
, XEXP (XEXP (x
, 0), 0), temp
);
9134 x
= simplify_gen_binary (LSHIFTRT
, xmode
,
9135 temp
, XEXP (XEXP (x
, 0), 1));
9137 return force_to_mode (x
, mode
, mask
, next_select
);
9140 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9141 use the full mask inside the NOT. */
9145 op0
= gen_lowpart_or_truncate (op_mode
,
9146 force_to_mode (XEXP (x
, 0), mode
, mask
,
9148 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
9150 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
9156 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9157 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9158 which is equal to STORE_FLAG_VALUE. */
9159 if ((mask
& ~STORE_FLAG_VALUE
) == 0
9160 && XEXP (x
, 1) == const0_rtx
9161 && GET_MODE (XEXP (x
, 0)) == mode
9162 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
9163 && (nonzero_bits (XEXP (x
, 0), mode
)
9164 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
9165 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9170 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9171 written in a narrower mode. We play it safe and do not do so. */
9173 op0
= gen_lowpart_or_truncate (xmode
,
9174 force_to_mode (XEXP (x
, 1), mode
,
9175 mask
, next_select
));
9176 op1
= gen_lowpart_or_truncate (xmode
,
9177 force_to_mode (XEXP (x
, 2), mode
,
9178 mask
, next_select
));
9179 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
9180 x
= simplify_gen_ternary (IF_THEN_ELSE
, xmode
,
9181 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
9189 /* Ensure we return a value of the proper mode. */
9190 return gen_lowpart_or_truncate (mode
, x
);
9193 /* Return nonzero if X is an expression that has one of two values depending on
9194 whether some other value is zero or nonzero. In that case, we return the
9195 value that is being tested, *PTRUE is set to the value if the rtx being
9196 returned has a nonzero value, and *PFALSE is set to the other alternative.
9198 If we return zero, we set *PTRUE and *PFALSE to X. */
9201 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9203 machine_mode mode
= GET_MODE (x
);
9204 enum rtx_code code
= GET_CODE (x
);
9205 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9206 unsigned HOST_WIDE_INT nz
;
9207 scalar_int_mode int_mode
;
9209 /* If we are comparing a value against zero, we are done. */
9210 if ((code
== NE
|| code
== EQ
)
9211 && XEXP (x
, 1) == const0_rtx
)
9213 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9214 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9218 /* If this is a unary operation whose operand has one of two values, apply
9219 our opcode to compute those values. */
9220 else if (UNARY_P (x
)
9221 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9223 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9224 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9225 GET_MODE (XEXP (x
, 0)));
9229 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9230 make can't possibly match and would suppress other optimizations. */
9231 else if (code
== COMPARE
)
9234 /* If this is a binary operation, see if either side has only one of two
9235 values. If either one does or if both do and they are conditional on
9236 the same value, compute the new true and false values. */
9237 else if (BINARY_P (x
))
9239 rtx op0
= XEXP (x
, 0);
9240 rtx op1
= XEXP (x
, 1);
9241 cond0
= if_then_else_cond (op0
, &true0
, &false0
);
9242 cond1
= if_then_else_cond (op1
, &true1
, &false1
);
9244 if ((cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
))
9245 && (REG_P (op0
) || REG_P (op1
)))
9247 /* Try to enable a simplification by undoing work done by
9248 if_then_else_cond if it converted a REG into something more
9253 true0
= false0
= op0
;
9258 true1
= false1
= op1
;
9262 if ((cond0
!= 0 || cond1
!= 0)
9263 && ! (cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
)))
9265 /* If if_then_else_cond returned zero, then true/false are the
9266 same rtl. We must copy one of them to prevent invalid rtl
9269 true0
= copy_rtx (true0
);
9270 else if (cond1
== 0)
9271 true1
= copy_rtx (true1
);
9273 if (COMPARISON_P (x
))
9275 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9277 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9282 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9283 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9286 return cond0
? cond0
: cond1
;
9289 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9290 operands is zero when the other is nonzero, and vice-versa,
9291 and STORE_FLAG_VALUE is 1 or -1. */
9293 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9294 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9296 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9298 rtx op0
= XEXP (XEXP (x
, 0), 1);
9299 rtx op1
= XEXP (XEXP (x
, 1), 1);
9301 cond0
= XEXP (XEXP (x
, 0), 0);
9302 cond1
= XEXP (XEXP (x
, 1), 0);
9304 if (COMPARISON_P (cond0
)
9305 && COMPARISON_P (cond1
)
9306 && SCALAR_INT_MODE_P (mode
)
9307 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9308 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9309 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9310 || ((swap_condition (GET_CODE (cond0
))
9311 == reversed_comparison_code (cond1
, NULL
))
9312 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9313 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9314 && ! side_effects_p (x
))
9316 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9317 *pfalse
= simplify_gen_binary (MULT
, mode
,
9319 ? simplify_gen_unary (NEG
, mode
,
9327 /* Similarly for MULT, AND and UMIN, except that for these the result
9329 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9330 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9331 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9333 cond0
= XEXP (XEXP (x
, 0), 0);
9334 cond1
= XEXP (XEXP (x
, 1), 0);
9336 if (COMPARISON_P (cond0
)
9337 && COMPARISON_P (cond1
)
9338 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9339 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9340 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9341 || ((swap_condition (GET_CODE (cond0
))
9342 == reversed_comparison_code (cond1
, NULL
))
9343 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9344 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9345 && ! side_effects_p (x
))
9347 *ptrue
= *pfalse
= const0_rtx
;
9353 else if (code
== IF_THEN_ELSE
)
9355 /* If we have IF_THEN_ELSE already, extract the condition and
9356 canonicalize it if it is NE or EQ. */
9357 cond0
= XEXP (x
, 0);
9358 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9359 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9360 return XEXP (cond0
, 0);
9361 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9363 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9364 return XEXP (cond0
, 0);
9370 /* If X is a SUBREG, we can narrow both the true and false values
9371 if the inner expression, if there is a condition. */
9372 else if (code
== SUBREG
9373 && (cond0
= if_then_else_cond (SUBREG_REG (x
), &true0
,
9376 true0
= simplify_gen_subreg (mode
, true0
,
9377 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9378 false0
= simplify_gen_subreg (mode
, false0
,
9379 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9380 if (true0
&& false0
)
9388 /* If X is a constant, this isn't special and will cause confusions
9389 if we treat it as such. Likewise if it is equivalent to a constant. */
9390 else if (CONSTANT_P (x
)
9391 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9394 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9395 will be least confusing to the rest of the compiler. */
9396 else if (mode
== BImode
)
9398 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9402 /* If X is known to be either 0 or -1, those are the true and
9403 false values when testing X. */
9404 else if (x
== constm1_rtx
|| x
== const0_rtx
9405 || (is_a
<scalar_int_mode
> (mode
, &int_mode
)
9406 && (num_sign_bit_copies (x
, int_mode
)
9407 == GET_MODE_PRECISION (int_mode
))))
9409 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9413 /* Likewise for 0 or a single bit. */
9414 else if (HWI_COMPUTABLE_MODE_P (mode
)
9415 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9417 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9421 /* Otherwise fail; show no condition with true and false values the same. */
9422 *ptrue
= *pfalse
= x
;
9426 /* Return the value of expression X given the fact that condition COND
9427 is known to be true when applied to REG as its first operand and VAL
9428 as its second. X is known to not be shared and so can be modified in
9431 We only handle the simplest cases, and specifically those cases that
9432 arise with IF_THEN_ELSE expressions. */
9435 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9437 enum rtx_code code
= GET_CODE (x
);
9441 if (side_effects_p (x
))
9444 /* If either operand of the condition is a floating point value,
9445 then we have to avoid collapsing an EQ comparison. */
9447 && rtx_equal_p (x
, reg
)
9448 && ! FLOAT_MODE_P (GET_MODE (x
))
9449 && ! FLOAT_MODE_P (GET_MODE (val
)))
9452 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9455 /* If X is (abs REG) and we know something about REG's relationship
9456 with zero, we may be able to simplify this. */
9458 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9461 case GE
: case GT
: case EQ
:
9464 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9466 GET_MODE (XEXP (x
, 0)));
9471 /* The only other cases we handle are MIN, MAX, and comparisons if the
9472 operands are the same as REG and VAL. */
9474 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9476 if (rtx_equal_p (XEXP (x
, 0), val
))
9478 std::swap (val
, reg
);
9479 cond
= swap_condition (cond
);
9482 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9484 if (COMPARISON_P (x
))
9486 if (comparison_dominates_p (cond
, code
))
9487 return VECTOR_MODE_P (GET_MODE (x
)) ? x
: const_true_rtx
;
9489 code
= reversed_comparison_code (x
, NULL
);
9491 && comparison_dominates_p (cond
, code
))
9492 return CONST0_RTX (GET_MODE (x
));
9496 else if (code
== SMAX
|| code
== SMIN
9497 || code
== UMIN
|| code
== UMAX
)
9499 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9501 /* Do not reverse the condition when it is NE or EQ.
9502 This is because we cannot conclude anything about
9503 the value of 'SMAX (x, y)' when x is not equal to y,
9504 but we can when x equals y. */
9505 if ((code
== SMAX
|| code
== UMAX
)
9506 && ! (cond
== EQ
|| cond
== NE
))
9507 cond
= reverse_condition (cond
);
9512 return unsignedp
? x
: XEXP (x
, 1);
9514 return unsignedp
? x
: XEXP (x
, 0);
9516 return unsignedp
? XEXP (x
, 1) : x
;
9518 return unsignedp
? XEXP (x
, 0) : x
;
9525 else if (code
== SUBREG
)
9527 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9528 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9530 if (SUBREG_REG (x
) != r
)
9532 /* We must simplify subreg here, before we lose track of the
9533 original inner_mode. */
9534 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9535 inner_mode
, SUBREG_BYTE (x
));
9539 SUBST (SUBREG_REG (x
), r
);
9544 /* We don't have to handle SIGN_EXTEND here, because even in the
9545 case of replacing something with a modeless CONST_INT, a
9546 CONST_INT is already (supposed to be) a valid sign extension for
9547 its narrower mode, which implies it's already properly
9548 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9549 story is different. */
9550 else if (code
== ZERO_EXTEND
)
9552 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9553 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9555 if (XEXP (x
, 0) != r
)
9557 /* We must simplify the zero_extend here, before we lose
9558 track of the original inner_mode. */
9559 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9564 SUBST (XEXP (x
, 0), r
);
9570 fmt
= GET_RTX_FORMAT (code
);
9571 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9574 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9575 else if (fmt
[i
] == 'E')
9576 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9577 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9584 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9585 assignment as a field assignment. */
9588 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9590 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9592 if (paradoxical_subreg_p (GET_MODE (x
), GET_MODE (y
)))
9594 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9596 x
= adjust_address_nv (x
, GET_MODE (y
),
9597 byte_lowpart_offset (GET_MODE (y
),
9601 if (x
== y
|| rtx_equal_p (x
, y
))
9604 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9607 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9608 Note that all SUBREGs of MEM are paradoxical; otherwise they
9609 would have been rewritten. */
9610 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9611 && MEM_P (SUBREG_REG (y
))
9612 && rtx_equal_p (SUBREG_REG (y
),
9613 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9616 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9617 && MEM_P (SUBREG_REG (x
))
9618 && rtx_equal_p (SUBREG_REG (x
),
9619 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9622 /* We used to see if get_last_value of X and Y were the same but that's
9623 not correct. In one direction, we'll cause the assignment to have
9624 the wrong destination and in the case, we'll import a register into this
9625 insn that might have already have been dead. So fail if none of the
9626 above cases are true. */
9630 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9631 Return that assignment if so.
9633 We only handle the most common cases. */
9636 make_field_assignment (rtx x
)
9638 rtx dest
= SET_DEST (x
);
9639 rtx src
= SET_SRC (x
);
9644 unsigned HOST_WIDE_INT len
;
9647 /* All the rules in this function are specific to scalar integers. */
9648 scalar_int_mode mode
;
9649 if (!is_a
<scalar_int_mode
> (GET_MODE (dest
), &mode
))
9652 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9653 a clear of a one-bit field. We will have changed it to
9654 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9657 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9658 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9659 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9660 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9662 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9665 return gen_rtx_SET (assign
, const0_rtx
);
9669 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9670 && subreg_lowpart_p (XEXP (src
, 0))
9671 && partial_subreg_p (XEXP (src
, 0))
9672 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9673 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9674 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9675 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9677 assign
= make_extraction (VOIDmode
, dest
, 0,
9678 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9681 return gen_rtx_SET (assign
, const0_rtx
);
9685 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9687 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9688 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9689 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9691 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9694 return gen_rtx_SET (assign
, const1_rtx
);
9698 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9699 SRC is an AND with all bits of that field set, then we can discard
9701 if (GET_CODE (dest
) == ZERO_EXTRACT
9702 && CONST_INT_P (XEXP (dest
, 1))
9703 && GET_CODE (src
) == AND
9704 && CONST_INT_P (XEXP (src
, 1)))
9706 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9707 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9708 unsigned HOST_WIDE_INT ze_mask
;
9710 if (width
>= HOST_BITS_PER_WIDE_INT
)
9713 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9715 /* Complete overlap. We can remove the source AND. */
9716 if ((and_mask
& ze_mask
) == ze_mask
)
9717 return gen_rtx_SET (dest
, XEXP (src
, 0));
9719 /* Partial overlap. We can reduce the source AND. */
9720 if ((and_mask
& ze_mask
) != and_mask
)
9722 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9723 gen_int_mode (and_mask
& ze_mask
, mode
));
9724 return gen_rtx_SET (dest
, src
);
9728 /* The other case we handle is assignments into a constant-position
9729 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9730 a mask that has all one bits except for a group of zero bits and
9731 OTHER is known to have zeros where C1 has ones, this is such an
9732 assignment. Compute the position and length from C1. Shift OTHER
9733 to the appropriate position, force it to the required mode, and
9734 make the extraction. Check for the AND in both operands. */
9736 /* One or more SUBREGs might obscure the constant-position field
9737 assignment. The first one we are likely to encounter is an outer
9738 narrowing SUBREG, which we can just strip for the purposes of
9739 identifying the constant-field assignment. */
9740 scalar_int_mode src_mode
= mode
;
9741 if (GET_CODE (src
) == SUBREG
9742 && subreg_lowpart_p (src
)
9743 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (src
)), &src_mode
))
9744 src
= SUBREG_REG (src
);
9746 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9749 rhs
= expand_compound_operation (XEXP (src
, 0));
9750 lhs
= expand_compound_operation (XEXP (src
, 1));
9752 if (GET_CODE (rhs
) == AND
9753 && CONST_INT_P (XEXP (rhs
, 1))
9754 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9755 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9756 /* The second SUBREG that might get in the way is a paradoxical
9757 SUBREG around the first operand of the AND. We want to
9758 pretend the operand is as wide as the destination here. We
9759 do this by adjusting the MEM to wider mode for the sole
9760 purpose of the call to rtx_equal_for_field_assignment_p. Also
9761 note this trick only works for MEMs. */
9762 else if (GET_CODE (rhs
) == AND
9763 && paradoxical_subreg_p (XEXP (rhs
, 0))
9764 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9765 && CONST_INT_P (XEXP (rhs
, 1))
9766 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9768 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9769 else if (GET_CODE (lhs
) == AND
9770 && CONST_INT_P (XEXP (lhs
, 1))
9771 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9772 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9773 /* The second SUBREG that might get in the way is a paradoxical
9774 SUBREG around the first operand of the AND. We want to
9775 pretend the operand is as wide as the destination here. We
9776 do this by adjusting the MEM to wider mode for the sole
9777 purpose of the call to rtx_equal_for_field_assignment_p. Also
9778 note this trick only works for MEMs. */
9779 else if (GET_CODE (lhs
) == AND
9780 && paradoxical_subreg_p (XEXP (lhs
, 0))
9781 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9782 && CONST_INT_P (XEXP (lhs
, 1))
9783 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9785 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9789 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (mode
), &len
);
9791 || pos
+ len
> GET_MODE_PRECISION (mode
)
9792 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
9793 || (c1
& nonzero_bits (other
, mode
)) != 0)
9796 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9800 /* The mode to use for the source is the mode of the assignment, or of
9801 what is inside a possible STRICT_LOW_PART. */
9802 machine_mode new_mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9803 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9805 /* Shift OTHER right POS places and make it the source, restricting it
9806 to the proper length and mode. */
9808 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9809 src_mode
, other
, pos
),
9811 src
= force_to_mode (src
, new_mode
,
9812 len
>= HOST_BITS_PER_WIDE_INT
9814 : (HOST_WIDE_INT_1U
<< len
) - 1,
9817 /* If SRC is masked by an AND that does not make a difference in
9818 the value being stored, strip it. */
9819 if (GET_CODE (assign
) == ZERO_EXTRACT
9820 && CONST_INT_P (XEXP (assign
, 1))
9821 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9822 && GET_CODE (src
) == AND
9823 && CONST_INT_P (XEXP (src
, 1))
9824 && UINTVAL (XEXP (src
, 1))
9825 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9826 src
= XEXP (src
, 0);
9828 return gen_rtx_SET (assign
, src
);
9831 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9835 apply_distributive_law (rtx x
)
9837 enum rtx_code code
= GET_CODE (x
);
9838 enum rtx_code inner_code
;
9839 rtx lhs
, rhs
, other
;
9842 /* Distributivity is not true for floating point as it can change the
9843 value. So we don't do it unless -funsafe-math-optimizations. */
9844 if (FLOAT_MODE_P (GET_MODE (x
))
9845 && ! flag_unsafe_math_optimizations
)
9848 /* The outer operation can only be one of the following: */
9849 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9850 && code
!= PLUS
&& code
!= MINUS
)
9856 /* If either operand is a primitive we can't do anything, so get out
9858 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9861 lhs
= expand_compound_operation (lhs
);
9862 rhs
= expand_compound_operation (rhs
);
9863 inner_code
= GET_CODE (lhs
);
9864 if (inner_code
!= GET_CODE (rhs
))
9867 /* See if the inner and outer operations distribute. */
9874 /* These all distribute except over PLUS. */
9875 if (code
== PLUS
|| code
== MINUS
)
9880 if (code
!= PLUS
&& code
!= MINUS
)
9885 /* This is also a multiply, so it distributes over everything. */
9888 /* This used to handle SUBREG, but this turned out to be counter-
9889 productive, since (subreg (op ...)) usually is not handled by
9890 insn patterns, and this "optimization" therefore transformed
9891 recognizable patterns into unrecognizable ones. Therefore the
9892 SUBREG case was removed from here.
9894 It is possible that distributing SUBREG over arithmetic operations
9895 leads to an intermediate result than can then be optimized further,
9896 e.g. by moving the outer SUBREG to the other side of a SET as done
9897 in simplify_set. This seems to have been the original intent of
9898 handling SUBREGs here.
9900 However, with current GCC this does not appear to actually happen,
9901 at least on major platforms. If some case is found where removing
9902 the SUBREG case here prevents follow-on optimizations, distributing
9903 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9909 /* Set LHS and RHS to the inner operands (A and B in the example
9910 above) and set OTHER to the common operand (C in the example).
9911 There is only one way to do this unless the inner operation is
9913 if (COMMUTATIVE_ARITH_P (lhs
)
9914 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9915 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9916 else if (COMMUTATIVE_ARITH_P (lhs
)
9917 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9918 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9919 else if (COMMUTATIVE_ARITH_P (lhs
)
9920 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9921 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9922 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9923 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9927 /* Form the new inner operation, seeing if it simplifies first. */
9928 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9930 /* There is one exception to the general way of distributing:
9931 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9932 if (code
== XOR
&& inner_code
== IOR
)
9935 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9938 /* We may be able to continuing distributing the result, so call
9939 ourselves recursively on the inner operation before forming the
9940 outer operation, which we return. */
9941 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9942 apply_distributive_law (tem
), other
);
9945 /* See if X is of the form (* (+ A B) C), and if so convert to
9946 (+ (* A C) (* B C)) and try to simplify.
9948 Most of the time, this results in no change. However, if some of
9949 the operands are the same or inverses of each other, simplifications
9952 For example, (and (ior A B) (not B)) can occur as the result of
9953 expanding a bit field assignment. When we apply the distributive
9954 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9955 which then simplifies to (and (A (not B))).
9957 Note that no checks happen on the validity of applying the inverse
9958 distributive law. This is pointless since we can do it in the
9959 few places where this routine is called.
9961 N is the index of the term that is decomposed (the arithmetic operation,
9962 i.e. (+ A B) in the first example above). !N is the index of the term that
9963 is distributed, i.e. of C in the first example above. */
9965 distribute_and_simplify_rtx (rtx x
, int n
)
9968 enum rtx_code outer_code
, inner_code
;
9969 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9971 /* Distributivity is not true for floating point as it can change the
9972 value. So we don't do it unless -funsafe-math-optimizations. */
9973 if (FLOAT_MODE_P (GET_MODE (x
))
9974 && ! flag_unsafe_math_optimizations
)
9977 decomposed
= XEXP (x
, n
);
9978 if (!ARITHMETIC_P (decomposed
))
9981 mode
= GET_MODE (x
);
9982 outer_code
= GET_CODE (x
);
9983 distributed
= XEXP (x
, !n
);
9985 inner_code
= GET_CODE (decomposed
);
9986 inner_op0
= XEXP (decomposed
, 0);
9987 inner_op1
= XEXP (decomposed
, 1);
9989 /* Special case (and (xor B C) (not A)), which is equivalent to
9990 (xor (ior A B) (ior A C)) */
9991 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9993 distributed
= XEXP (distributed
, 0);
9999 /* Distribute the second term. */
10000 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
10001 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
10005 /* Distribute the first term. */
10006 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
10007 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
10010 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
10011 new_op0
, new_op1
));
10012 if (GET_CODE (tmp
) != outer_code
10013 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
10014 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
10020 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10021 in MODE. Return an equivalent form, if different from (and VAROP
10022 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10025 simplify_and_const_int_1 (scalar_int_mode mode
, rtx varop
,
10026 unsigned HOST_WIDE_INT constop
)
10028 unsigned HOST_WIDE_INT nonzero
;
10029 unsigned HOST_WIDE_INT orig_constop
;
10033 orig_varop
= varop
;
10034 orig_constop
= constop
;
10035 if (GET_CODE (varop
) == CLOBBER
)
10038 /* Simplify VAROP knowing that we will be only looking at some of the
10041 Note by passing in CONSTOP, we guarantee that the bits not set in
10042 CONSTOP are not significant and will never be examined. We must
10043 ensure that is the case by explicitly masking out those bits
10044 before returning. */
10045 varop
= force_to_mode (varop
, mode
, constop
, 0);
10047 /* If VAROP is a CLOBBER, we will fail so return it. */
10048 if (GET_CODE (varop
) == CLOBBER
)
10051 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10052 to VAROP and return the new constant. */
10053 if (CONST_INT_P (varop
))
10054 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
10056 /* See what bits may be nonzero in VAROP. Unlike the general case of
10057 a call to nonzero_bits, here we don't care about bits outside
10058 MODE unless WORD_REGISTER_OPERATIONS is true. */
10060 scalar_int_mode tmode
= mode
;
10061 if (WORD_REGISTER_OPERATIONS
&& GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
10063 nonzero
= nonzero_bits (varop
, tmode
) & GET_MODE_MASK (tmode
);
10065 /* Turn off all bits in the constant that are known to already be zero.
10066 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10067 which is tested below. */
10069 constop
&= nonzero
;
10071 /* If we don't have any bits left, return zero. */
10072 if (constop
== 0 && !side_effects_p (varop
))
10075 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10076 a power of two, we can replace this with an ASHIFT. */
10077 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), tmode
) == 1
10078 && (i
= exact_log2 (constop
)) >= 0)
10079 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
10081 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10082 or XOR, then try to apply the distributive law. This may eliminate
10083 operations if either branch can be simplified because of the AND.
10084 It may also make some cases more complex, but those cases probably
10085 won't match a pattern either with or without this. */
10087 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
10089 scalar_int_mode varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10093 apply_distributive_law
10094 (simplify_gen_binary (GET_CODE (varop
), varop_mode
,
10095 simplify_and_const_int (NULL_RTX
, varop_mode
,
10098 simplify_and_const_int (NULL_RTX
, varop_mode
,
10103 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10104 the AND and see if one of the operands simplifies to zero. If so, we
10105 may eliminate it. */
10107 if (GET_CODE (varop
) == PLUS
10108 && pow2p_hwi (constop
+ 1))
10112 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
10113 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
10114 if (o0
== const0_rtx
)
10116 if (o1
== const0_rtx
)
10120 /* Make a SUBREG if necessary. If we can't make it, fail. */
10121 varop
= gen_lowpart (mode
, varop
);
10122 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10125 /* If we are only masking insignificant bits, return VAROP. */
10126 if (constop
== nonzero
)
10129 if (varop
== orig_varop
&& constop
== orig_constop
)
10132 /* Otherwise, return an AND. */
10133 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
10137 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10140 Return an equivalent form, if different from X. Otherwise, return X. If
10141 X is zero, we are to always construct the equivalent form. */
10144 simplify_and_const_int (rtx x
, scalar_int_mode mode
, rtx varop
,
10145 unsigned HOST_WIDE_INT constop
)
10147 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
10152 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
10153 gen_int_mode (constop
, mode
));
10154 if (GET_MODE (x
) != mode
)
10155 x
= gen_lowpart (mode
, x
);
10159 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10160 We don't care about bits outside of those defined in MODE.
10161 We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10163 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10164 a shift, AND, or zero_extract, we can do better. */
10167 reg_nonzero_bits_for_combine (const_rtx x
, scalar_int_mode xmode
,
10168 scalar_int_mode mode
,
10169 unsigned HOST_WIDE_INT
*nonzero
)
10172 reg_stat_type
*rsp
;
10174 /* If X is a register whose nonzero bits value is current, use it.
10175 Otherwise, if X is a register whose value we can find, use that
10176 value. Otherwise, use the previously-computed global nonzero bits
10177 for this register. */
10179 rsp
= ®_stat
[REGNO (x
)];
10180 if (rsp
->last_set_value
!= 0
10181 && (rsp
->last_set_mode
== mode
10182 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10183 && GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
10184 && GET_MODE_CLASS (mode
) == MODE_INT
))
10185 && ((rsp
->last_set_label
>= label_tick_ebb_start
10186 && rsp
->last_set_label
< label_tick
)
10187 || (rsp
->last_set_label
== label_tick
10188 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10189 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10190 && REGNO (x
) < reg_n_sets_max
10191 && REG_N_SETS (REGNO (x
)) == 1
10192 && !REGNO_REG_SET_P
10193 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10196 /* Note that, even if the precision of last_set_mode is lower than that
10197 of mode, record_value_for_reg invoked nonzero_bits on the register
10198 with nonzero_bits_mode (because last_set_mode is necessarily integral
10199 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10200 are all valid, hence in mode too since nonzero_bits_mode is defined
10201 to the largest HWI_COMPUTABLE_MODE_P mode. */
10202 *nonzero
&= rsp
->last_set_nonzero_bits
;
10206 tem
= get_last_value (x
);
10209 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
10210 tem
= sign_extend_short_imm (tem
, xmode
, GET_MODE_PRECISION (mode
));
10215 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
10217 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
10219 if (GET_MODE_PRECISION (xmode
) < GET_MODE_PRECISION (mode
))
10220 /* We don't know anything about the upper bits. */
10221 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (xmode
);
10229 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10230 end of X that are known to be equal to the sign bit. X will be used
10231 in mode MODE; the returned value will always be between 1 and the
10232 number of bits in MODE. */
10235 reg_num_sign_bit_copies_for_combine (const_rtx x
, scalar_int_mode xmode
,
10236 scalar_int_mode mode
,
10237 unsigned int *result
)
10240 reg_stat_type
*rsp
;
10242 rsp
= ®_stat
[REGNO (x
)];
10243 if (rsp
->last_set_value
!= 0
10244 && rsp
->last_set_mode
== mode
10245 && ((rsp
->last_set_label
>= label_tick_ebb_start
10246 && rsp
->last_set_label
< label_tick
)
10247 || (rsp
->last_set_label
== label_tick
10248 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10249 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10250 && REGNO (x
) < reg_n_sets_max
10251 && REG_N_SETS (REGNO (x
)) == 1
10252 && !REGNO_REG_SET_P
10253 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10256 *result
= rsp
->last_set_sign_bit_copies
;
10260 tem
= get_last_value (x
);
10264 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10265 && GET_MODE_PRECISION (xmode
) == GET_MODE_PRECISION (mode
))
10266 *result
= rsp
->sign_bit_copies
;
10271 /* Return the number of "extended" bits there are in X, when interpreted
10272 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10273 unsigned quantities, this is the number of high-order zero bits.
10274 For signed quantities, this is the number of copies of the sign bit
10275 minus 1. In both case, this function returns the number of "spare"
10276 bits. For example, if two quantities for which this function returns
10277 at least 1 are added, the addition is known not to overflow.
10279 This function will always return 0 unless called during combine, which
10280 implies that it must be called from a define_split. */
10283 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10285 if (nonzero_sign_valid
== 0)
10288 scalar_int_mode int_mode
;
10290 ? (is_a
<scalar_int_mode
> (mode
, &int_mode
)
10291 && HWI_COMPUTABLE_MODE_P (int_mode
)
10292 ? (unsigned int) (GET_MODE_PRECISION (int_mode
) - 1
10293 - floor_log2 (nonzero_bits (x
, int_mode
)))
10295 : num_sign_bit_copies (x
, mode
) - 1);
10298 /* This function is called from `simplify_shift_const' to merge two
10299 outer operations. Specifically, we have already found that we need
10300 to perform operation *POP0 with constant *PCONST0 at the outermost
10301 position. We would now like to also perform OP1 with constant CONST1
10302 (with *POP0 being done last).
10304 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10305 the resulting operation. *PCOMP_P is set to 1 if we would need to
10306 complement the innermost operand, otherwise it is unchanged.
10308 MODE is the mode in which the operation will be done. No bits outside
10309 the width of this mode matter. It is assumed that the width of this mode
10310 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10312 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10313 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10314 result is simply *PCONST0.
10316 If the resulting operation cannot be expressed as one operation, we
10317 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10320 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10322 enum rtx_code op0
= *pop0
;
10323 HOST_WIDE_INT const0
= *pconst0
;
10325 const0
&= GET_MODE_MASK (mode
);
10326 const1
&= GET_MODE_MASK (mode
);
10328 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10332 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10335 if (op1
== UNKNOWN
|| op0
== SET
)
10338 else if (op0
== UNKNOWN
)
10339 op0
= op1
, const0
= const1
;
10341 else if (op0
== op1
)
10365 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10366 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10369 /* If the two constants aren't the same, we can't do anything. The
10370 remaining six cases can all be done. */
10371 else if (const0
!= const1
)
10379 /* (a & b) | b == b */
10381 else /* op1 == XOR */
10382 /* (a ^ b) | b == a | b */
10388 /* (a & b) ^ b == (~a) & b */
10389 op0
= AND
, *pcomp_p
= 1;
10390 else /* op1 == IOR */
10391 /* (a | b) ^ b == a & ~b */
10392 op0
= AND
, const0
= ~const0
;
10397 /* (a | b) & b == b */
10399 else /* op1 == XOR */
10400 /* (a ^ b) & b) == (~a) & b */
10407 /* Check for NO-OP cases. */
10408 const0
&= GET_MODE_MASK (mode
);
10410 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10412 else if (const0
== 0 && op0
== AND
)
10414 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10420 /* ??? Slightly redundant with the above mask, but not entirely.
10421 Moving this above means we'd have to sign-extend the mode mask
10422 for the final test. */
10423 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10424 *pconst0
= trunc_int_for_mode (const0
, mode
);
10429 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10430 the shift in. The original shift operation CODE is performed on OP in
10431 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10432 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10433 result of the shift is subject to operation OUTER_CODE with operand
10436 static scalar_int_mode
10437 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10438 scalar_int_mode orig_mode
, scalar_int_mode mode
,
10439 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10441 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10443 /* In general we can't perform in wider mode for right shift and rotate. */
10447 /* We can still widen if the bits brought in from the left are identical
10448 to the sign bit of ORIG_MODE. */
10449 if (num_sign_bit_copies (op
, mode
)
10450 > (unsigned) (GET_MODE_PRECISION (mode
)
10451 - GET_MODE_PRECISION (orig_mode
)))
10456 /* Similarly here but with zero bits. */
10457 if (HWI_COMPUTABLE_MODE_P (mode
)
10458 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10461 /* We can also widen if the bits brought in will be masked off. This
10462 operation is performed in ORIG_MODE. */
10463 if (outer_code
== AND
)
10465 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10468 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10477 gcc_unreachable ();
10484 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10485 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10486 if we cannot simplify it. Otherwise, return a simplified value.
10488 The shift is normally computed in the widest mode we find in VAROP, as
10489 long as it isn't a different number of words than RESULT_MODE. Exceptions
10490 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10493 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10494 rtx varop
, int orig_count
)
10496 enum rtx_code orig_code
= code
;
10497 rtx orig_varop
= varop
;
10499 machine_mode mode
= result_mode
;
10500 machine_mode shift_mode
;
10501 scalar_int_mode tmode
, inner_mode
, int_mode
, int_varop_mode
, int_result_mode
;
10502 /* We form (outer_op (code varop count) (outer_const)). */
10503 enum rtx_code outer_op
= UNKNOWN
;
10504 HOST_WIDE_INT outer_const
= 0;
10505 int complement_p
= 0;
10508 /* Make sure and truncate the "natural" shift on the way in. We don't
10509 want to do this inside the loop as it makes it more difficult to
10511 if (SHIFT_COUNT_TRUNCATED
)
10512 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10514 /* If we were given an invalid count, don't do anything except exactly
10515 what was requested. */
10517 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10520 count
= orig_count
;
10522 /* Unless one of the branches of the `if' in this loop does a `continue',
10523 we will `break' the loop after the `if'. */
10527 /* If we have an operand of (clobber (const_int 0)), fail. */
10528 if (GET_CODE (varop
) == CLOBBER
)
10531 /* Convert ROTATERT to ROTATE. */
10532 if (code
== ROTATERT
)
10534 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10536 count
= bitsize
- count
;
10539 shift_mode
= result_mode
;
10540 if (shift_mode
!= mode
)
10542 /* We only change the modes of scalar shifts. */
10543 int_mode
= as_a
<scalar_int_mode
> (mode
);
10544 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10545 shift_mode
= try_widen_shift_mode (code
, varop
, count
,
10546 int_result_mode
, int_mode
,
10547 outer_op
, outer_const
);
10550 scalar_int_mode shift_unit_mode
10551 = as_a
<scalar_int_mode
> (GET_MODE_INNER (shift_mode
));
10553 /* Handle cases where the count is greater than the size of the mode
10554 minus 1. For ASHIFT, use the size minus one as the count (this can
10555 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10556 take the count modulo the size. For other shifts, the result is
10559 Since these shifts are being produced by the compiler by combining
10560 multiple operations, each of which are defined, we know what the
10561 result is supposed to be. */
10563 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10565 if (code
== ASHIFTRT
)
10566 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10567 else if (code
== ROTATE
|| code
== ROTATERT
)
10568 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10571 /* We can't simply return zero because there may be an
10573 varop
= const0_rtx
;
10579 /* If we discovered we had to complement VAROP, leave. Making a NOT
10580 here would cause an infinite loop. */
10584 if (shift_mode
== shift_unit_mode
)
10586 /* An arithmetic right shift of a quantity known to be -1 or 0
10588 if (code
== ASHIFTRT
10589 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10590 == GET_MODE_PRECISION (shift_unit_mode
)))
10596 /* If we are doing an arithmetic right shift and discarding all but
10597 the sign bit copies, this is equivalent to doing a shift by the
10598 bitsize minus one. Convert it into that shift because it will
10599 often allow other simplifications. */
10601 if (code
== ASHIFTRT
10602 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10603 >= GET_MODE_PRECISION (shift_unit_mode
)))
10604 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10606 /* We simplify the tests below and elsewhere by converting
10607 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10608 `make_compound_operation' will convert it to an ASHIFTRT for
10609 those machines (such as VAX) that don't have an LSHIFTRT. */
10610 if (code
== ASHIFTRT
10611 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10612 && val_signbit_known_clear_p (shift_unit_mode
,
10613 nonzero_bits (varop
,
10617 if (((code
== LSHIFTRT
10618 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10619 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10621 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10622 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10623 & GET_MODE_MASK (shift_unit_mode
))))
10624 && !side_effects_p (varop
))
10625 varop
= const0_rtx
;
10628 switch (GET_CODE (varop
))
10634 new_rtx
= expand_compound_operation (varop
);
10635 if (new_rtx
!= varop
)
10643 /* The following rules apply only to scalars. */
10644 if (shift_mode
!= shift_unit_mode
)
10646 int_mode
= as_a
<scalar_int_mode
> (mode
);
10648 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10649 minus the width of a smaller mode, we can do this with a
10650 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10651 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10652 && ! mode_dependent_address_p (XEXP (varop
, 0),
10653 MEM_ADDR_SPACE (varop
))
10654 && ! MEM_VOLATILE_P (varop
)
10655 && (int_mode_for_size (GET_MODE_BITSIZE (int_mode
) - count
, 1)
10658 new_rtx
= adjust_address_nv (varop
, tmode
,
10659 BYTES_BIG_ENDIAN
? 0
10660 : count
/ BITS_PER_UNIT
);
10662 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10663 : ZERO_EXTEND
, int_mode
, new_rtx
);
10670 /* The following rules apply only to scalars. */
10671 if (shift_mode
!= shift_unit_mode
)
10673 int_mode
= as_a
<scalar_int_mode
> (mode
);
10674 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10676 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10677 the same number of words as what we've seen so far. Then store
10678 the widest mode in MODE. */
10679 if (subreg_lowpart_p (varop
)
10680 && is_int_mode (GET_MODE (SUBREG_REG (varop
)), &inner_mode
)
10681 && GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_varop_mode
)
10682 && (CEIL (GET_MODE_SIZE (inner_mode
), UNITS_PER_WORD
)
10683 == CEIL (GET_MODE_SIZE (int_mode
), UNITS_PER_WORD
))
10684 && GET_MODE_CLASS (int_varop_mode
) == MODE_INT
)
10686 varop
= SUBREG_REG (varop
);
10687 if (GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_mode
))
10694 /* Some machines use MULT instead of ASHIFT because MULT
10695 is cheaper. But it is still better on those machines to
10696 merge two shifts into one. */
10697 if (CONST_INT_P (XEXP (varop
, 1))
10698 && (log2
= exact_log2 (UINTVAL (XEXP (varop
, 1)))) >= 0)
10700 rtx log2_rtx
= gen_int_shift_amount (GET_MODE (varop
), log2
);
10701 varop
= simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10702 XEXP (varop
, 0), log2_rtx
);
10708 /* Similar, for when divides are cheaper. */
10709 if (CONST_INT_P (XEXP (varop
, 1))
10710 && (log2
= exact_log2 (UINTVAL (XEXP (varop
, 1)))) >= 0)
10712 rtx log2_rtx
= gen_int_shift_amount (GET_MODE (varop
), log2
);
10713 varop
= simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10714 XEXP (varop
, 0), log2_rtx
);
10720 /* If we are extracting just the sign bit of an arithmetic
10721 right shift, that shift is not needed. However, the sign
10722 bit of a wider mode may be different from what would be
10723 interpreted as the sign bit in a narrower mode, so, if
10724 the result is narrower, don't discard the shift. */
10725 if (code
== LSHIFTRT
10726 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10727 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10728 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10730 varop
= XEXP (varop
, 0);
10739 /* The following rules apply only to scalars. */
10740 if (shift_mode
!= shift_unit_mode
)
10742 int_mode
= as_a
<scalar_int_mode
> (mode
);
10743 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10744 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10746 /* Here we have two nested shifts. The result is usually the
10747 AND of a new shift with a mask. We compute the result below. */
10748 if (CONST_INT_P (XEXP (varop
, 1))
10749 && INTVAL (XEXP (varop
, 1)) >= 0
10750 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (int_varop_mode
)
10751 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
10752 && HWI_COMPUTABLE_MODE_P (int_mode
))
10754 enum rtx_code first_code
= GET_CODE (varop
);
10755 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10756 unsigned HOST_WIDE_INT mask
;
10759 /* We have one common special case. We can't do any merging if
10760 the inner code is an ASHIFTRT of a smaller mode. However, if
10761 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10762 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10763 we can convert it to
10764 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10765 This simplifies certain SIGN_EXTEND operations. */
10766 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10767 && count
== (GET_MODE_PRECISION (int_result_mode
)
10768 - GET_MODE_PRECISION (int_varop_mode
)))
10770 /* C3 has the low-order C1 bits zero. */
10772 mask
= GET_MODE_MASK (int_mode
)
10773 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10775 varop
= simplify_and_const_int (NULL_RTX
, int_result_mode
,
10776 XEXP (varop
, 0), mask
);
10777 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
,
10778 int_result_mode
, varop
, count
);
10779 count
= first_count
;
10784 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10785 than C1 high-order bits equal to the sign bit, we can convert
10786 this to either an ASHIFT or an ASHIFTRT depending on the
10789 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10791 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10792 && int_varop_mode
== shift_unit_mode
10793 && (num_sign_bit_copies (XEXP (varop
, 0), shift_unit_mode
)
10796 varop
= XEXP (varop
, 0);
10797 count
-= first_count
;
10807 /* There are some cases we can't do. If CODE is ASHIFTRT,
10808 we can only do this if FIRST_CODE is also ASHIFTRT.
10810 We can't do the case when CODE is ROTATE and FIRST_CODE is
10813 If the mode of this shift is not the mode of the outer shift,
10814 we can't do this if either shift is a right shift or ROTATE.
10816 Finally, we can't do any of these if the mode is too wide
10817 unless the codes are the same.
10819 Handle the case where the shift codes are the same
10822 if (code
== first_code
)
10824 if (int_varop_mode
!= int_result_mode
10825 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10826 || code
== ROTATE
))
10829 count
+= first_count
;
10830 varop
= XEXP (varop
, 0);
10834 if (code
== ASHIFTRT
10835 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10836 || GET_MODE_PRECISION (int_mode
) > HOST_BITS_PER_WIDE_INT
10837 || (int_varop_mode
!= int_result_mode
10838 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10839 || first_code
== ROTATE
10840 || code
== ROTATE
)))
10843 /* To compute the mask to apply after the shift, shift the
10844 nonzero bits of the inner shift the same way the
10845 outer shift will. */
10847 mask_rtx
= gen_int_mode (nonzero_bits (varop
, int_varop_mode
),
10849 rtx count_rtx
= gen_int_shift_amount (int_result_mode
, count
);
10851 = simplify_const_binary_operation (code
, int_result_mode
,
10852 mask_rtx
, count_rtx
);
10854 /* Give up if we can't compute an outer operation to use. */
10856 || !CONST_INT_P (mask_rtx
)
10857 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10859 int_result_mode
, &complement_p
))
10862 /* If the shifts are in the same direction, we add the
10863 counts. Otherwise, we subtract them. */
10864 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10865 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10866 count
+= first_count
;
10868 count
-= first_count
;
10870 /* If COUNT is positive, the new shift is usually CODE,
10871 except for the two exceptions below, in which case it is
10872 FIRST_CODE. If the count is negative, FIRST_CODE should
10875 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10876 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10878 else if (count
< 0)
10879 code
= first_code
, count
= -count
;
10881 varop
= XEXP (varop
, 0);
10885 /* If we have (A << B << C) for any shift, we can convert this to
10886 (A << C << B). This wins if A is a constant. Only try this if
10887 B is not a constant. */
10889 else if (GET_CODE (varop
) == code
10890 && CONST_INT_P (XEXP (varop
, 0))
10891 && !CONST_INT_P (XEXP (varop
, 1)))
10893 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10894 sure the result will be masked. See PR70222. */
10895 if (code
== LSHIFTRT
10896 && int_mode
!= int_result_mode
10897 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10898 GET_MODE_MASK (int_result_mode
)
10899 >> orig_count
, int_result_mode
,
10902 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10903 up outer sign extension (often left and right shift) is
10904 hardly more efficient than the original. See PR70429.
10905 Similarly punt for rotates with different modes.
10907 if ((code
== ASHIFTRT
|| code
== ROTATE
)
10908 && int_mode
!= int_result_mode
)
10911 rtx count_rtx
= gen_int_shift_amount (int_result_mode
, count
);
10912 rtx new_rtx
= simplify_const_binary_operation (code
, int_mode
,
10915 varop
= gen_rtx_fmt_ee (code
, int_mode
, new_rtx
, XEXP (varop
, 1));
10922 /* The following rules apply only to scalars. */
10923 if (shift_mode
!= shift_unit_mode
)
10926 /* Make this fit the case below. */
10927 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10933 /* The following rules apply only to scalars. */
10934 if (shift_mode
!= shift_unit_mode
)
10936 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10937 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10939 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10940 with C the size of VAROP - 1 and the shift is logical if
10941 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10942 we have an (le X 0) operation. If we have an arithmetic shift
10943 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10944 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10946 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10947 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10948 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10949 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10950 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
10951 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10954 varop
= gen_rtx_LE (int_varop_mode
, XEXP (varop
, 1),
10957 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10958 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
10963 /* If we have (shift (logical)), move the logical to the outside
10964 to allow it to possibly combine with another logical and the
10965 shift to combine with another shift. This also canonicalizes to
10966 what a ZERO_EXTRACT looks like. Also, some machines have
10967 (and (shift)) insns. */
10969 if (CONST_INT_P (XEXP (varop
, 1))
10970 /* We can't do this if we have (ashiftrt (xor)) and the
10971 constant has its sign bit set in shift_unit_mode with
10972 shift_unit_mode wider than result_mode. */
10973 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10974 && int_result_mode
!= shift_unit_mode
10975 && trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10976 shift_unit_mode
) < 0)
10977 && (new_rtx
= simplify_const_binary_operation
10978 (code
, int_result_mode
,
10979 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
10980 gen_int_shift_amount (int_result_mode
, count
))) != 0
10981 && CONST_INT_P (new_rtx
)
10982 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10983 INTVAL (new_rtx
), int_result_mode
,
10986 varop
= XEXP (varop
, 0);
10990 /* If we can't do that, try to simplify the shift in each arm of the
10991 logical expression, make a new logical expression, and apply
10992 the inverse distributive law. This also can't be done for
10993 (ashiftrt (xor)) where we've widened the shift and the constant
10994 changes the sign bit. */
10995 if (CONST_INT_P (XEXP (varop
, 1))
10996 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10997 && int_result_mode
!= shift_unit_mode
10998 && trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10999 shift_unit_mode
) < 0))
11001 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
11002 XEXP (varop
, 0), count
);
11003 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
11004 XEXP (varop
, 1), count
);
11006 varop
= simplify_gen_binary (GET_CODE (varop
), shift_unit_mode
,
11008 varop
= apply_distributive_law (varop
);
11016 /* The following rules apply only to scalars. */
11017 if (shift_mode
!= shift_unit_mode
)
11019 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11021 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11022 says that the sign bit can be tested, FOO has mode MODE, C is
11023 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11024 that may be nonzero. */
11025 if (code
== LSHIFTRT
11026 && XEXP (varop
, 1) == const0_rtx
11027 && GET_MODE (XEXP (varop
, 0)) == int_result_mode
11028 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11029 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
11030 && STORE_FLAG_VALUE
== -1
11031 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
11032 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
11033 int_result_mode
, &complement_p
))
11035 varop
= XEXP (varop
, 0);
11042 /* The following rules apply only to scalars. */
11043 if (shift_mode
!= shift_unit_mode
)
11045 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11047 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11048 than the number of bits in the mode is equivalent to A. */
11049 if (code
== LSHIFTRT
11050 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11051 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1)
11053 varop
= XEXP (varop
, 0);
11058 /* NEG commutes with ASHIFT since it is multiplication. Move the
11059 NEG outside to allow shifts to combine. */
11061 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0,
11062 int_result_mode
, &complement_p
))
11064 varop
= XEXP (varop
, 0);
11070 /* The following rules apply only to scalars. */
11071 if (shift_mode
!= shift_unit_mode
)
11073 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11075 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11076 is one less than the number of bits in the mode is
11077 equivalent to (xor A 1). */
11078 if (code
== LSHIFTRT
11079 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11080 && XEXP (varop
, 1) == constm1_rtx
11081 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
11082 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
11083 int_result_mode
, &complement_p
))
11086 varop
= XEXP (varop
, 0);
11090 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11091 that might be nonzero in BAR are those being shifted out and those
11092 bits are known zero in FOO, we can replace the PLUS with FOO.
11093 Similarly in the other operand order. This code occurs when
11094 we are computing the size of a variable-size array. */
11096 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11097 && count
< HOST_BITS_PER_WIDE_INT
11098 && nonzero_bits (XEXP (varop
, 1), int_result_mode
) >> count
== 0
11099 && (nonzero_bits (XEXP (varop
, 1), int_result_mode
)
11100 & nonzero_bits (XEXP (varop
, 0), int_result_mode
)) == 0)
11102 varop
= XEXP (varop
, 0);
11105 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11106 && count
< HOST_BITS_PER_WIDE_INT
11107 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
11108 && (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11110 && (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11111 & nonzero_bits (XEXP (varop
, 1), int_result_mode
)) == 0)
11113 varop
= XEXP (varop
, 1);
11117 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11119 && CONST_INT_P (XEXP (varop
, 1))
11120 && (new_rtx
= simplify_const_binary_operation
11121 (ASHIFT
, int_result_mode
,
11122 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11123 gen_int_shift_amount (int_result_mode
, count
))) != 0
11124 && CONST_INT_P (new_rtx
)
11125 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
11126 INTVAL (new_rtx
), int_result_mode
,
11129 varop
= XEXP (varop
, 0);
11133 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11134 signbit', and attempt to change the PLUS to an XOR and move it to
11135 the outer operation as is done above in the AND/IOR/XOR case
11136 leg for shift(logical). See details in logical handling above
11137 for reasoning in doing so. */
11138 if (code
== LSHIFTRT
11139 && CONST_INT_P (XEXP (varop
, 1))
11140 && mode_signbit_p (int_result_mode
, XEXP (varop
, 1))
11141 && (new_rtx
= simplify_const_binary_operation
11142 (code
, int_result_mode
,
11143 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11144 gen_int_shift_amount (int_result_mode
, count
))) != 0
11145 && CONST_INT_P (new_rtx
)
11146 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
11147 INTVAL (new_rtx
), int_result_mode
,
11150 varop
= XEXP (varop
, 0);
11157 /* The following rules apply only to scalars. */
11158 if (shift_mode
!= shift_unit_mode
)
11160 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
11162 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11163 with C the size of VAROP - 1 and the shift is logical if
11164 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11165 we have a (gt X 0) operation. If the shift is arithmetic with
11166 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11167 we have a (neg (gt X 0)) operation. */
11169 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
11170 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
11171 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
11172 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11173 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11174 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
11175 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11178 varop
= gen_rtx_GT (int_varop_mode
, XEXP (varop
, 1),
11181 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11182 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
11189 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11190 if the truncate does not affect the value. */
11191 if (code
== LSHIFTRT
11192 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
11193 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11194 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
11195 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
11196 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
11198 rtx varop_inner
= XEXP (varop
, 0);
11199 int new_count
= count
+ INTVAL (XEXP (varop_inner
, 1));
11200 rtx new_count_rtx
= gen_int_shift_amount (GET_MODE (varop_inner
),
11202 varop_inner
= gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
11203 XEXP (varop_inner
, 0),
11205 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
11218 shift_mode
= result_mode
;
11219 if (shift_mode
!= mode
)
11221 /* We only change the modes of scalar shifts. */
11222 int_mode
= as_a
<scalar_int_mode
> (mode
);
11223 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11224 shift_mode
= try_widen_shift_mode (code
, varop
, count
, int_result_mode
,
11225 int_mode
, outer_op
, outer_const
);
11228 /* We have now finished analyzing the shift. The result should be
11229 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11230 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11231 to the result of the shift. OUTER_CONST is the relevant constant,
11232 but we must turn off all bits turned off in the shift. */
11234 if (outer_op
== UNKNOWN
11235 && orig_code
== code
&& orig_count
== count
11236 && varop
== orig_varop
11237 && shift_mode
== GET_MODE (varop
))
11240 /* Make a SUBREG if necessary. If we can't make it, fail. */
11241 varop
= gen_lowpart (shift_mode
, varop
);
11242 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11245 /* If we have an outer operation and we just made a shift, it is
11246 possible that we could have simplified the shift were it not
11247 for the outer operation. So try to do the simplification
11250 if (outer_op
!= UNKNOWN
)
11251 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11256 x
= simplify_gen_binary (code
, shift_mode
, varop
,
11257 gen_int_shift_amount (shift_mode
, count
));
11259 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11260 turn off all the bits that the shift would have turned off. */
11261 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11262 /* We only change the modes of scalar shifts. */
11263 x
= simplify_and_const_int (NULL_RTX
, as_a
<scalar_int_mode
> (shift_mode
),
11264 x
, GET_MODE_MASK (result_mode
) >> orig_count
);
11266 /* Do the remainder of the processing in RESULT_MODE. */
11267 x
= gen_lowpart_or_truncate (result_mode
, x
);
11269 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11272 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11274 if (outer_op
!= UNKNOWN
)
11276 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11278 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11279 && GET_MODE_PRECISION (int_result_mode
) < HOST_BITS_PER_WIDE_INT
)
11280 outer_const
= trunc_int_for_mode (outer_const
, int_result_mode
);
11282 if (outer_op
== AND
)
11283 x
= simplify_and_const_int (NULL_RTX
, int_result_mode
, x
, outer_const
);
11284 else if (outer_op
== SET
)
11286 /* This means that we have determined that the result is
11287 equivalent to a constant. This should be rare. */
11288 if (!side_effects_p (x
))
11289 x
= GEN_INT (outer_const
);
11291 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11292 x
= simplify_gen_unary (outer_op
, int_result_mode
, x
, int_result_mode
);
11294 x
= simplify_gen_binary (outer_op
, int_result_mode
, x
,
11295 GEN_INT (outer_const
));
11301 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11302 The result of the shift is RESULT_MODE. If we cannot simplify it,
11303 return X or, if it is NULL, synthesize the expression with
11304 simplify_gen_binary. Otherwise, return a simplified value.
11306 The shift is normally computed in the widest mode we find in VAROP, as
11307 long as it isn't a different number of words than RESULT_MODE. Exceptions
11308 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11311 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11312 rtx varop
, int count
)
11314 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11319 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
,
11320 gen_int_shift_amount (GET_MODE (varop
), count
));
11321 if (GET_MODE (x
) != result_mode
)
11322 x
= gen_lowpart (result_mode
, x
);
11327 /* A subroutine of recog_for_combine. See there for arguments and
11331 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11333 rtx pat
= *pnewpat
;
11334 rtx pat_without_clobbers
;
11335 int insn_code_number
;
11336 int num_clobbers_to_add
= 0;
11338 rtx notes
= NULL_RTX
;
11339 rtx old_notes
, old_pat
;
11342 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11343 we use to indicate that something didn't match. If we find such a
11344 thing, force rejection. */
11345 if (GET_CODE (pat
) == PARALLEL
)
11346 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11347 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11348 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11351 old_pat
= PATTERN (insn
);
11352 old_notes
= REG_NOTES (insn
);
11353 PATTERN (insn
) = pat
;
11354 REG_NOTES (insn
) = NULL_RTX
;
11356 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11357 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11359 if (insn_code_number
< 0)
11360 fputs ("Failed to match this instruction:\n", dump_file
);
11362 fputs ("Successfully matched this instruction:\n", dump_file
);
11363 print_rtl_single (dump_file
, pat
);
11366 /* If it isn't, there is the possibility that we previously had an insn
11367 that clobbered some register as a side effect, but the combined
11368 insn doesn't need to do that. So try once more without the clobbers
11369 unless this represents an ASM insn. */
11371 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11372 && GET_CODE (pat
) == PARALLEL
)
11376 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11377 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11380 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11384 SUBST_INT (XVECLEN (pat
, 0), pos
);
11387 pat
= XVECEXP (pat
, 0, 0);
11389 PATTERN (insn
) = pat
;
11390 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11391 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11393 if (insn_code_number
< 0)
11394 fputs ("Failed to match this instruction:\n", dump_file
);
11396 fputs ("Successfully matched this instruction:\n", dump_file
);
11397 print_rtl_single (dump_file
, pat
);
11401 pat_without_clobbers
= pat
;
11403 PATTERN (insn
) = old_pat
;
11404 REG_NOTES (insn
) = old_notes
;
11406 /* Recognize all noop sets, these will be killed by followup pass. */
11407 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11408 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11410 /* If we had any clobbers to add, make a new pattern than contains
11411 them. Then check to make sure that all of them are dead. */
11412 if (num_clobbers_to_add
)
11414 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11415 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11416 ? (XVECLEN (pat
, 0)
11417 + num_clobbers_to_add
)
11418 : num_clobbers_to_add
+ 1));
11420 if (GET_CODE (pat
) == PARALLEL
)
11421 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11422 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11424 XVECEXP (newpat
, 0, 0) = pat
;
11426 add_clobbers (newpat
, insn_code_number
);
11428 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11429 i
< XVECLEN (newpat
, 0); i
++)
11431 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11432 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11434 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11436 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11437 notes
= alloc_reg_note (REG_UNUSED
,
11438 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11444 if (insn_code_number
>= 0
11445 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11447 old_pat
= PATTERN (insn
);
11448 old_notes
= REG_NOTES (insn
);
11449 old_icode
= INSN_CODE (insn
);
11450 PATTERN (insn
) = pat
;
11451 REG_NOTES (insn
) = notes
;
11452 INSN_CODE (insn
) = insn_code_number
;
11454 /* Allow targets to reject combined insn. */
11455 if (!targetm
.legitimate_combined_insn (insn
))
11457 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11458 fputs ("Instruction not appropriate for target.",
11461 /* Callers expect recog_for_combine to strip
11462 clobbers from the pattern on failure. */
11463 pat
= pat_without_clobbers
;
11466 insn_code_number
= -1;
11469 PATTERN (insn
) = old_pat
;
11470 REG_NOTES (insn
) = old_notes
;
11471 INSN_CODE (insn
) = old_icode
;
11477 return insn_code_number
;
11480 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11481 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11482 Return whether anything was so changed. */
11485 change_zero_ext (rtx pat
)
11487 bool changed
= false;
11488 rtx
*src
= &SET_SRC (pat
);
11490 subrtx_ptr_iterator::array_type array
;
11491 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11494 scalar_int_mode mode
, inner_mode
;
11495 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
11499 if (GET_CODE (x
) == ZERO_EXTRACT
11500 && CONST_INT_P (XEXP (x
, 1))
11501 && CONST_INT_P (XEXP (x
, 2))
11502 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
)
11503 && GET_MODE_PRECISION (inner_mode
) <= GET_MODE_PRECISION (mode
))
11505 size
= INTVAL (XEXP (x
, 1));
11507 int start
= INTVAL (XEXP (x
, 2));
11508 if (BITS_BIG_ENDIAN
)
11509 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11512 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0),
11513 gen_int_shift_amount (inner_mode
, start
));
11517 if (mode
!= inner_mode
)
11519 if (REG_P (x
) && HARD_REGISTER_P (x
)
11520 && !can_change_dest_mode (x
, 0, mode
))
11523 x
= gen_lowpart_SUBREG (mode
, x
);
11526 else if (GET_CODE (x
) == ZERO_EXTEND
11527 && GET_CODE (XEXP (x
, 0)) == SUBREG
11528 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11529 && !paradoxical_subreg_p (XEXP (x
, 0))
11530 && subreg_lowpart_p (XEXP (x
, 0)))
11532 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11533 size
= GET_MODE_PRECISION (inner_mode
);
11534 x
= SUBREG_REG (XEXP (x
, 0));
11535 if (GET_MODE (x
) != mode
)
11537 if (REG_P (x
) && HARD_REGISTER_P (x
)
11538 && !can_change_dest_mode (x
, 0, mode
))
11541 x
= gen_lowpart_SUBREG (mode
, x
);
11544 else if (GET_CODE (x
) == ZERO_EXTEND
11545 && REG_P (XEXP (x
, 0))
11546 && HARD_REGISTER_P (XEXP (x
, 0))
11547 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11549 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11550 size
= GET_MODE_PRECISION (inner_mode
);
11551 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11556 if (!(GET_CODE (x
) == LSHIFTRT
11557 && CONST_INT_P (XEXP (x
, 1))
11558 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11560 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11561 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11569 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11570 maybe_swap_commutative_operands (**iter
);
11572 rtx
*dst
= &SET_DEST (pat
);
11573 scalar_int_mode mode
;
11574 if (GET_CODE (*dst
) == ZERO_EXTRACT
11575 && REG_P (XEXP (*dst
, 0))
11576 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (*dst
, 0)), &mode
)
11577 && CONST_INT_P (XEXP (*dst
, 1))
11578 && CONST_INT_P (XEXP (*dst
, 2)))
11580 rtx reg
= XEXP (*dst
, 0);
11581 int width
= INTVAL (XEXP (*dst
, 1));
11582 int offset
= INTVAL (XEXP (*dst
, 2));
11583 int reg_width
= GET_MODE_PRECISION (mode
);
11584 if (BITS_BIG_ENDIAN
)
11585 offset
= reg_width
- width
- offset
;
11588 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11589 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11590 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11592 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11595 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11596 w
= gen_rtx_IOR (mode
, x
, z
);
11597 SUBST (SET_DEST (pat
), reg
);
11598 SUBST (SET_SRC (pat
), w
);
11606 /* Like recog, but we receive the address of a pointer to a new pattern.
11607 We try to match the rtx that the pointer points to.
11608 If that fails, we may try to modify or replace the pattern,
11609 storing the replacement into the same pointer object.
11611 Modifications include deletion or addition of CLOBBERs. If the
11612 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11613 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11614 (and undo if that fails).
11616 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11617 the CLOBBERs are placed.
11619 The value is the final insn code from the pattern ultimately matched,
11623 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11625 rtx pat
= *pnewpat
;
11626 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11627 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11628 return insn_code_number
;
11630 void *marker
= get_undo_marker ();
11631 bool changed
= false;
11633 if (GET_CODE (pat
) == SET
)
11635 /* For an unrecognized single set of a constant, try placing it in
11636 the constant pool, if this function already uses one. */
11637 rtx src
= SET_SRC (pat
);
11638 if (CONSTANT_P (src
)
11639 && !CONST_INT_P (src
)
11640 && crtl
->uses_const_pool
)
11642 machine_mode mode
= GET_MODE (src
);
11643 if (mode
== VOIDmode
)
11644 mode
= GET_MODE (SET_DEST (pat
));
11645 src
= force_const_mem (mode
, src
);
11648 SUBST (SET_SRC (pat
), src
);
11653 changed
= change_zero_ext (pat
);
11655 else if (GET_CODE (pat
) == PARALLEL
)
11658 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11660 rtx set
= XVECEXP (pat
, 0, i
);
11661 if (GET_CODE (set
) == SET
)
11662 changed
|= change_zero_ext (set
);
11668 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11670 if (insn_code_number
< 0)
11671 undo_to_marker (marker
);
11674 return insn_code_number
;
11677 /* Like gen_lowpart_general but for use by combine. In combine it
11678 is not possible to create any new pseudoregs. However, it is
11679 safe to create invalid memory addresses, because combine will
11680 try to recognize them and all they will do is make the combine
11683 If for some reason this cannot do its job, an rtx
11684 (clobber (const_int 0)) is returned.
11685 An insn containing that will not be recognized. */
11688 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11690 machine_mode imode
= GET_MODE (x
);
11693 if (omode
== imode
)
11696 /* We can only support MODE being wider than a word if X is a
11697 constant integer or has a mode the same size. */
11698 if (maybe_gt (GET_MODE_SIZE (omode
), UNITS_PER_WORD
)
11699 && ! (CONST_SCALAR_INT_P (x
)
11700 || known_eq (GET_MODE_SIZE (imode
), GET_MODE_SIZE (omode
))))
11703 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11704 won't know what to do. So we will strip off the SUBREG here and
11705 process normally. */
11706 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11708 x
= SUBREG_REG (x
);
11710 /* For use in case we fall down into the address adjustments
11711 further below, we need to adjust the known mode and size of
11712 x; imode and isize, since we just adjusted x. */
11713 imode
= GET_MODE (x
);
11715 if (imode
== omode
)
11719 result
= gen_lowpart_common (omode
, x
);
11726 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11728 if (MEM_VOLATILE_P (x
)
11729 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11732 /* If we want to refer to something bigger than the original memref,
11733 generate a paradoxical subreg instead. That will force a reload
11734 of the original memref X. */
11735 if (paradoxical_subreg_p (omode
, imode
))
11736 return gen_rtx_SUBREG (omode
, x
, 0);
11738 poly_int64 offset
= byte_lowpart_offset (omode
, imode
);
11739 return adjust_address_nv (x
, omode
, offset
);
11742 /* If X is a comparison operator, rewrite it in a new mode. This
11743 probably won't match, but may allow further simplifications. */
11744 else if (COMPARISON_P (x
)
11745 && SCALAR_INT_MODE_P (imode
)
11746 && SCALAR_INT_MODE_P (omode
))
11747 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11749 /* If we couldn't simplify X any other way, just enclose it in a
11750 SUBREG. Normally, this SUBREG won't match, but some patterns may
11751 include an explicit SUBREG or we may simplify it further in combine. */
11756 if (imode
== VOIDmode
)
11758 imode
= int_mode_for_mode (omode
).require ();
11759 x
= gen_lowpart_common (imode
, x
);
11763 res
= lowpart_subreg (omode
, x
, imode
);
11769 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11772 /* Try to simplify a comparison between OP0 and a constant OP1,
11773 where CODE is the comparison code that will be tested, into a
11774 (CODE OP0 const0_rtx) form.
11776 The result is a possibly different comparison code to use.
11777 *POP1 may be updated. */
11779 static enum rtx_code
11780 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11781 rtx op0
, rtx
*pop1
)
11783 scalar_int_mode int_mode
;
11784 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11786 /* Get the constant we are comparing against and turn off all bits
11787 not on in our mode. */
11788 if (mode
!= VOIDmode
)
11789 const_op
= trunc_int_for_mode (const_op
, mode
);
11791 /* If we are comparing against a constant power of two and the value
11792 being compared can only have that single bit nonzero (e.g., it was
11793 `and'ed with that bit), we can replace this with a comparison
11796 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11797 || code
== LT
|| code
== LTU
)
11798 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11799 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11800 && pow2p_hwi (const_op
& GET_MODE_MASK (int_mode
))
11801 && (nonzero_bits (op0
, int_mode
)
11802 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (int_mode
))))
11804 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11808 /* Similarly, if we are comparing a value known to be either -1 or
11809 0 with -1, change it to the opposite comparison against zero. */
11811 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11812 || code
== GEU
|| code
== LTU
)
11813 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11814 && num_sign_bit_copies (op0
, int_mode
) == GET_MODE_PRECISION (int_mode
))
11816 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11820 /* Do some canonicalizations based on the comparison code. We prefer
11821 comparisons against zero and then prefer equality comparisons.
11822 If we can reduce the size of a constant, we will do that too. */
11826 /* < C is equivalent to <= (C - 1) */
11831 /* ... fall through to LE case below. */
11832 gcc_fallthrough ();
11838 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11845 /* If we are doing a <= 0 comparison on a value known to have
11846 a zero sign bit, we can replace this with == 0. */
11847 else if (const_op
== 0
11848 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11849 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11850 && (nonzero_bits (op0
, int_mode
)
11851 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11857 /* >= C is equivalent to > (C - 1). */
11862 /* ... fall through to GT below. */
11863 gcc_fallthrough ();
11869 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11876 /* If we are doing a > 0 comparison on a value known to have
11877 a zero sign bit, we can replace this with != 0. */
11878 else if (const_op
== 0
11879 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11880 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11881 && (nonzero_bits (op0
, int_mode
)
11882 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11888 /* < C is equivalent to <= (C - 1). */
11893 /* ... fall through ... */
11894 gcc_fallthrough ();
11896 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11897 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11898 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11899 && ((unsigned HOST_WIDE_INT
) const_op
11900 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11910 /* unsigned <= 0 is equivalent to == 0 */
11913 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11914 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11915 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11916 && ((unsigned HOST_WIDE_INT
) const_op
11917 == ((HOST_WIDE_INT_1U
11918 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1)))
11926 /* >= C is equivalent to > (C - 1). */
11931 /* ... fall through ... */
11932 gcc_fallthrough ();
11935 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11936 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11937 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11938 && ((unsigned HOST_WIDE_INT
) const_op
11939 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11949 /* unsigned > 0 is equivalent to != 0 */
11952 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11953 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11954 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11955 && ((unsigned HOST_WIDE_INT
) const_op
11956 == (HOST_WIDE_INT_1U
11957 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1))
11968 *pop1
= GEN_INT (const_op
);
11972 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11973 comparison code that will be tested.
11975 The result is a possibly different comparison code to use. *POP0 and
11976 *POP1 may be updated.
11978 It is possible that we might detect that a comparison is either always
11979 true or always false. However, we do not perform general constant
11980 folding in combine, so this knowledge isn't useful. Such tautologies
11981 should have been detected earlier. Hence we ignore all such cases. */
11983 static enum rtx_code
11984 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11990 scalar_int_mode mode
, inner_mode
, tmode
;
11991 opt_scalar_int_mode tmode_iter
;
11993 /* Try a few ways of applying the same transformation to both operands. */
11996 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11997 so check specially. */
11998 if (!WORD_REGISTER_OPERATIONS
11999 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
12000 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
12001 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12002 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
12003 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
12004 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
12005 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &mode
)
12006 && (is_a
<scalar_int_mode
>
12007 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))), &inner_mode
))
12008 && inner_mode
== GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0)))
12009 && CONST_INT_P (XEXP (op0
, 1))
12010 && XEXP (op0
, 1) == XEXP (op1
, 1)
12011 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12012 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
12013 && (INTVAL (XEXP (op0
, 1))
12014 == (GET_MODE_PRECISION (mode
)
12015 - GET_MODE_PRECISION (inner_mode
))))
12017 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
12018 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
12021 /* If both operands are the same constant shift, see if we can ignore the
12022 shift. We can if the shift is a rotate or if the bits shifted out of
12023 this shift are known to be zero for both inputs and if the type of
12024 comparison is compatible with the shift. */
12025 if (GET_CODE (op0
) == GET_CODE (op1
)
12026 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
12027 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
12028 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
12029 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
12030 || (GET_CODE (op0
) == ASHIFTRT
12031 && (code
!= GTU
&& code
!= LTU
12032 && code
!= GEU
&& code
!= LEU
)))
12033 && CONST_INT_P (XEXP (op0
, 1))
12034 && INTVAL (XEXP (op0
, 1)) >= 0
12035 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12036 && XEXP (op0
, 1) == XEXP (op1
, 1))
12038 machine_mode mode
= GET_MODE (op0
);
12039 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12040 int shift_count
= INTVAL (XEXP (op0
, 1));
12042 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
12043 mask
&= (mask
>> shift_count
) << shift_count
;
12044 else if (GET_CODE (op0
) == ASHIFT
)
12045 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
12047 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
12048 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
12049 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
12054 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12055 SUBREGs are of the same mode, and, in both cases, the AND would
12056 be redundant if the comparison was done in the narrower mode,
12057 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12058 and the operand's possibly nonzero bits are 0xffffff01; in that case
12059 if we only care about QImode, we don't need the AND). This case
12060 occurs if the output mode of an scc insn is not SImode and
12061 STORE_FLAG_VALUE == 1 (e.g., the 386).
12063 Similarly, check for a case where the AND's are ZERO_EXTEND
12064 operations from some narrower mode even though a SUBREG is not
12067 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
12068 && CONST_INT_P (XEXP (op0
, 1))
12069 && CONST_INT_P (XEXP (op1
, 1)))
12071 rtx inner_op0
= XEXP (op0
, 0);
12072 rtx inner_op1
= XEXP (op1
, 0);
12073 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
12074 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
12077 if (paradoxical_subreg_p (inner_op0
)
12078 && GET_CODE (inner_op1
) == SUBREG
12079 && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0
)))
12080 && (GET_MODE (SUBREG_REG (inner_op0
))
12081 == GET_MODE (SUBREG_REG (inner_op1
)))
12082 && ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
12083 GET_MODE (SUBREG_REG (inner_op0
)))) == 0
12084 && ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
12085 GET_MODE (SUBREG_REG (inner_op1
)))) == 0)
12087 op0
= SUBREG_REG (inner_op0
);
12088 op1
= SUBREG_REG (inner_op1
);
12090 /* The resulting comparison is always unsigned since we masked
12091 off the original sign bit. */
12092 code
= unsigned_condition (code
);
12098 FOR_EACH_MODE_UNTIL (tmode
,
12099 as_a
<scalar_int_mode
> (GET_MODE (op0
)))
12100 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
12102 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
12103 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
12104 code
= unsigned_condition (code
);
12113 /* If both operands are NOT, we can strip off the outer operation
12114 and adjust the comparison code for swapped operands; similarly for
12115 NEG, except that this must be an equality comparison. */
12116 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
12117 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
12118 && (code
== EQ
|| code
== NE
)))
12119 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
12125 /* If the first operand is a constant, swap the operands and adjust the
12126 comparison code appropriately, but don't do this if the second operand
12127 is already a constant integer. */
12128 if (swap_commutative_operands_p (op0
, op1
))
12130 std::swap (op0
, op1
);
12131 code
= swap_condition (code
);
12134 /* We now enter a loop during which we will try to simplify the comparison.
12135 For the most part, we only are concerned with comparisons with zero,
12136 but some things may really be comparisons with zero but not start
12137 out looking that way. */
12139 while (CONST_INT_P (op1
))
12141 machine_mode raw_mode
= GET_MODE (op0
);
12142 scalar_int_mode int_mode
;
12143 int equality_comparison_p
;
12144 int sign_bit_comparison_p
;
12145 int unsigned_comparison_p
;
12146 HOST_WIDE_INT const_op
;
12148 /* We only want to handle integral modes. This catches VOIDmode,
12149 CCmode, and the floating-point modes. An exception is that we
12150 can handle VOIDmode if OP0 is a COMPARE or a comparison
12153 if (GET_MODE_CLASS (raw_mode
) != MODE_INT
12154 && ! (raw_mode
== VOIDmode
12155 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
12158 /* Try to simplify the compare to constant, possibly changing the
12159 comparison op, and/or changing op1 to zero. */
12160 code
= simplify_compare_const (code
, raw_mode
, op0
, &op1
);
12161 const_op
= INTVAL (op1
);
12163 /* Compute some predicates to simplify code below. */
12165 equality_comparison_p
= (code
== EQ
|| code
== NE
);
12166 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
12167 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
12170 /* If this is a sign bit comparison and we can do arithmetic in
12171 MODE, say that we will only be needing the sign bit of OP0. */
12172 if (sign_bit_comparison_p
12173 && is_a
<scalar_int_mode
> (raw_mode
, &int_mode
)
12174 && HWI_COMPUTABLE_MODE_P (int_mode
))
12175 op0
= force_to_mode (op0
, int_mode
,
12177 << (GET_MODE_PRECISION (int_mode
) - 1),
12180 if (COMPARISON_P (op0
))
12182 /* We can't do anything if OP0 is a condition code value, rather
12183 than an actual data value. */
12185 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12188 /* Get the two operands being compared. */
12189 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12190 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12192 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12194 /* Check for the cases where we simply want the result of the
12195 earlier test or the opposite of that result. */
12196 if (code
== NE
|| code
== EQ
12197 || (val_signbit_known_set_p (raw_mode
, STORE_FLAG_VALUE
)
12198 && (code
== LT
|| code
== GE
)))
12200 enum rtx_code new_code
;
12201 if (code
== LT
|| code
== NE
)
12202 new_code
= GET_CODE (op0
);
12204 new_code
= reversed_comparison_code (op0
, NULL
);
12206 if (new_code
!= UNKNOWN
)
12217 if (raw_mode
== VOIDmode
)
12219 scalar_int_mode mode
= as_a
<scalar_int_mode
> (raw_mode
);
12221 /* Now try cases based on the opcode of OP0. If none of the cases
12222 does a "continue", we exit this loop immediately after the
12225 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
12226 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12227 switch (GET_CODE (op0
))
12230 /* If we are extracting a single bit from a variable position in
12231 a constant that has only a single bit set and are comparing it
12232 with zero, we can convert this into an equality comparison
12233 between the position and the location of the single bit. */
12234 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12235 have already reduced the shift count modulo the word size. */
12236 if (!SHIFT_COUNT_TRUNCATED
12237 && CONST_INT_P (XEXP (op0
, 0))
12238 && XEXP (op0
, 1) == const1_rtx
12239 && equality_comparison_p
&& const_op
== 0
12240 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
12242 if (BITS_BIG_ENDIAN
)
12243 i
= BITS_PER_WORD
- 1 - i
;
12245 op0
= XEXP (op0
, 2);
12249 /* Result is nonzero iff shift count is equal to I. */
12250 code
= reverse_condition (code
);
12257 tem
= expand_compound_operation (op0
);
12266 /* If testing for equality, we can take the NOT of the constant. */
12267 if (equality_comparison_p
12268 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
12270 op0
= XEXP (op0
, 0);
12275 /* If just looking at the sign bit, reverse the sense of the
12277 if (sign_bit_comparison_p
)
12279 op0
= XEXP (op0
, 0);
12280 code
= (code
== GE
? LT
: GE
);
12286 /* If testing for equality, we can take the NEG of the constant. */
12287 if (equality_comparison_p
12288 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
12290 op0
= XEXP (op0
, 0);
12295 /* The remaining cases only apply to comparisons with zero. */
12299 /* When X is ABS or is known positive,
12300 (neg X) is < 0 if and only if X != 0. */
12302 if (sign_bit_comparison_p
12303 && (GET_CODE (XEXP (op0
, 0)) == ABS
12304 || (mode_width
<= HOST_BITS_PER_WIDE_INT
12305 && (nonzero_bits (XEXP (op0
, 0), mode
)
12306 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12309 op0
= XEXP (op0
, 0);
12310 code
= (code
== LT
? NE
: EQ
);
12314 /* If we have NEG of something whose two high-order bits are the
12315 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12316 if (num_sign_bit_copies (op0
, mode
) >= 2)
12318 op0
= XEXP (op0
, 0);
12319 code
= swap_condition (code
);
12325 /* If we are testing equality and our count is a constant, we
12326 can perform the inverse operation on our RHS. */
12327 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12328 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
12329 op1
, XEXP (op0
, 1))) != 0)
12331 op0
= XEXP (op0
, 0);
12336 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12337 a particular bit. Convert it to an AND of a constant of that
12338 bit. This will be converted into a ZERO_EXTRACT. */
12339 if (const_op
== 0 && sign_bit_comparison_p
12340 && CONST_INT_P (XEXP (op0
, 1))
12341 && mode_width
<= HOST_BITS_PER_WIDE_INT
12342 && UINTVAL (XEXP (op0
, 1)) < mode_width
)
12344 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12347 - INTVAL (XEXP (op0
, 1)))));
12348 code
= (code
== LT
? NE
: EQ
);
12352 /* Fall through. */
12355 /* ABS is ignorable inside an equality comparison with zero. */
12356 if (const_op
== 0 && equality_comparison_p
)
12358 op0
= XEXP (op0
, 0);
12364 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12365 (compare FOO CONST) if CONST fits in FOO's mode and we
12366 are either testing inequality or have an unsigned
12367 comparison with ZERO_EXTEND or a signed comparison with
12368 SIGN_EXTEND. But don't do it if we don't have a compare
12369 insn of the given mode, since we'd have to revert it
12370 later on, and then we wouldn't know whether to sign- or
12372 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12373 && ! unsigned_comparison_p
12374 && HWI_COMPUTABLE_MODE_P (mode
)
12375 && trunc_int_for_mode (const_op
, mode
) == const_op
12376 && have_insn_for (COMPARE
, mode
))
12378 op0
= XEXP (op0
, 0);
12384 /* Check for the case where we are comparing A - C1 with C2, that is
12386 (subreg:MODE (plus (A) (-C1))) op (C2)
12388 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12389 comparison in the wider mode. One of the following two conditions
12390 must be true in order for this to be valid:
12392 1. The mode extension results in the same bit pattern being added
12393 on both sides and the comparison is equality or unsigned. As
12394 C2 has been truncated to fit in MODE, the pattern can only be
12397 2. The mode extension results in the sign bit being copied on
12400 The difficulty here is that we have predicates for A but not for
12401 (A - C1) so we need to check that C1 is within proper bounds so
12402 as to perturbate A as little as possible. */
12404 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12405 && subreg_lowpart_p (op0
)
12406 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op0
)),
12408 && GET_MODE_PRECISION (inner_mode
) > mode_width
12409 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12410 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12412 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12413 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12416 && (unsigned HOST_WIDE_INT
) c1
12417 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12418 && (equality_comparison_p
|| unsigned_comparison_p
)
12419 /* (A - C1) zero-extends if it is positive and sign-extends
12420 if it is negative, C2 both zero- and sign-extends. */
12421 && (((nonzero_bits (a
, inner_mode
)
12422 & ~GET_MODE_MASK (mode
)) == 0
12424 /* (A - C1) sign-extends if it is positive and 1-extends
12425 if it is negative, C2 both sign- and 1-extends. */
12426 || (num_sign_bit_copies (a
, inner_mode
)
12427 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12430 || ((unsigned HOST_WIDE_INT
) c1
12431 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12432 /* (A - C1) always sign-extends, like C2. */
12433 && num_sign_bit_copies (a
, inner_mode
)
12434 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12435 - (mode_width
- 1))))
12437 op0
= SUBREG_REG (op0
);
12442 /* If the inner mode is narrower and we are extracting the low part,
12443 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12444 if (paradoxical_subreg_p (op0
))
12446 else if (subreg_lowpart_p (op0
)
12447 && GET_MODE_CLASS (mode
) == MODE_INT
12448 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12449 && (code
== NE
|| code
== EQ
)
12450 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
12451 && !paradoxical_subreg_p (op0
)
12452 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
12453 & ~GET_MODE_MASK (mode
)) == 0)
12455 /* Remove outer subregs that don't do anything. */
12456 tem
= gen_lowpart (inner_mode
, op1
);
12458 if ((nonzero_bits (tem
, inner_mode
)
12459 & ~GET_MODE_MASK (mode
)) == 0)
12461 op0
= SUBREG_REG (op0
);
12473 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12474 && (unsigned_comparison_p
|| equality_comparison_p
)
12475 && HWI_COMPUTABLE_MODE_P (mode
)
12476 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12478 && have_insn_for (COMPARE
, mode
))
12480 op0
= XEXP (op0
, 0);
12486 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12487 this for equality comparisons due to pathological cases involving
12489 if (equality_comparison_p
12490 && (tem
= simplify_binary_operation (MINUS
, mode
,
12491 op1
, XEXP (op0
, 1))) != 0)
12493 op0
= XEXP (op0
, 0);
12498 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12499 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12500 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12502 op0
= XEXP (XEXP (op0
, 0), 0);
12503 code
= (code
== LT
? EQ
: NE
);
12509 /* We used to optimize signed comparisons against zero, but that
12510 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12511 arrive here as equality comparisons, or (GEU, LTU) are
12512 optimized away. No need to special-case them. */
12514 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12515 (eq B (minus A C)), whichever simplifies. We can only do
12516 this for equality comparisons due to pathological cases involving
12518 if (equality_comparison_p
12519 && (tem
= simplify_binary_operation (PLUS
, mode
,
12520 XEXP (op0
, 1), op1
)) != 0)
12522 op0
= XEXP (op0
, 0);
12527 if (equality_comparison_p
12528 && (tem
= simplify_binary_operation (MINUS
, mode
,
12529 XEXP (op0
, 0), op1
)) != 0)
12531 op0
= XEXP (op0
, 1);
12536 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12537 of bits in X minus 1, is one iff X > 0. */
12538 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12539 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12540 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12541 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12543 op0
= XEXP (op0
, 1);
12544 code
= (code
== GE
? LE
: GT
);
12550 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12551 if C is zero or B is a constant. */
12552 if (equality_comparison_p
12553 && (tem
= simplify_binary_operation (XOR
, mode
,
12554 XEXP (op0
, 1), op1
)) != 0)
12556 op0
= XEXP (op0
, 0);
12564 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12566 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12567 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12568 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12570 op0
= XEXP (op0
, 1);
12571 code
= (code
== GE
? GT
: LE
);
12577 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12578 will be converted to a ZERO_EXTRACT later. */
12579 if (const_op
== 0 && equality_comparison_p
12580 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12581 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12583 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12584 XEXP (XEXP (op0
, 0), 1));
12585 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12589 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12590 zero and X is a comparison and C1 and C2 describe only bits set
12591 in STORE_FLAG_VALUE, we can compare with X. */
12592 if (const_op
== 0 && equality_comparison_p
12593 && mode_width
<= HOST_BITS_PER_WIDE_INT
12594 && CONST_INT_P (XEXP (op0
, 1))
12595 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12596 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12597 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12598 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12600 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12601 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12602 if ((~STORE_FLAG_VALUE
& mask
) == 0
12603 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12604 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12605 && COMPARISON_P (tem
))))
12607 op0
= XEXP (XEXP (op0
, 0), 0);
12612 /* If we are doing an equality comparison of an AND of a bit equal
12613 to the sign bit, replace this with a LT or GE comparison of
12614 the underlying value. */
12615 if (equality_comparison_p
12617 && CONST_INT_P (XEXP (op0
, 1))
12618 && mode_width
<= HOST_BITS_PER_WIDE_INT
12619 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12620 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12622 op0
= XEXP (op0
, 0);
12623 code
= (code
== EQ
? GE
: LT
);
12627 /* If this AND operation is really a ZERO_EXTEND from a narrower
12628 mode, the constant fits within that mode, and this is either an
12629 equality or unsigned comparison, try to do this comparison in
12634 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12635 -> (ne:DI (reg:SI 4) (const_int 0))
12637 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12638 known to hold a value of the required mode the
12639 transformation is invalid. */
12640 if ((equality_comparison_p
|| unsigned_comparison_p
)
12641 && CONST_INT_P (XEXP (op0
, 1))
12642 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12643 & GET_MODE_MASK (mode
))
12645 && const_op
>> i
== 0
12646 && int_mode_for_size (i
, 1).exists (&tmode
))
12648 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12652 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12653 fits in both M1 and M2 and the SUBREG is either paradoxical
12654 or represents the low part, permute the SUBREG and the AND
12656 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12657 && CONST_INT_P (XEXP (op0
, 1)))
12659 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12660 /* Require an integral mode, to avoid creating something like
12662 if ((is_a
<scalar_int_mode
>
12663 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))), &tmode
))
12664 /* It is unsafe to commute the AND into the SUBREG if the
12665 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12666 not defined. As originally written the upper bits
12667 have a defined value due to the AND operation.
12668 However, if we commute the AND inside the SUBREG then
12669 they no longer have defined values and the meaning of
12670 the code has been changed.
12671 Also C1 should not change value in the smaller mode,
12672 see PR67028 (a positive C1 can become negative in the
12673 smaller mode, so that the AND does no longer mask the
12675 && ((WORD_REGISTER_OPERATIONS
12676 && mode_width
> GET_MODE_PRECISION (tmode
)
12677 && mode_width
<= BITS_PER_WORD
12678 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12679 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12680 && subreg_lowpart_p (XEXP (op0
, 0))))
12681 && mode_width
<= HOST_BITS_PER_WIDE_INT
12682 && HWI_COMPUTABLE_MODE_P (tmode
)
12683 && (c1
& ~mask
) == 0
12684 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12686 && c1
!= GET_MODE_MASK (tmode
))
12688 op0
= simplify_gen_binary (AND
, tmode
,
12689 SUBREG_REG (XEXP (op0
, 0)),
12690 gen_int_mode (c1
, tmode
));
12691 op0
= gen_lowpart (mode
, op0
);
12696 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12697 if (const_op
== 0 && equality_comparison_p
12698 && XEXP (op0
, 1) == const1_rtx
12699 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12701 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12702 XEXP (XEXP (op0
, 0), 0), 1);
12703 code
= (code
== NE
? EQ
: NE
);
12707 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12708 (eq (and (lshiftrt X) 1) 0).
12709 Also handle the case where (not X) is expressed using xor. */
12710 if (const_op
== 0 && equality_comparison_p
12711 && XEXP (op0
, 1) == const1_rtx
12712 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12714 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12715 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12717 if (GET_CODE (shift_op
) == NOT
12718 || (GET_CODE (shift_op
) == XOR
12719 && CONST_INT_P (XEXP (shift_op
, 1))
12720 && CONST_INT_P (shift_count
)
12721 && HWI_COMPUTABLE_MODE_P (mode
)
12722 && (UINTVAL (XEXP (shift_op
, 1))
12723 == HOST_WIDE_INT_1U
12724 << INTVAL (shift_count
))))
12727 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12728 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12729 code
= (code
== NE
? EQ
: NE
);
12736 /* If we have (compare (ashift FOO N) (const_int C)) and
12737 the high order N bits of FOO (N+1 if an inequality comparison)
12738 are known to be zero, we can do this by comparing FOO with C
12739 shifted right N bits so long as the low-order N bits of C are
12741 if (CONST_INT_P (XEXP (op0
, 1))
12742 && INTVAL (XEXP (op0
, 1)) >= 0
12743 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12744 < HOST_BITS_PER_WIDE_INT
)
12745 && (((unsigned HOST_WIDE_INT
) const_op
12746 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12748 && mode_width
<= HOST_BITS_PER_WIDE_INT
12749 && (nonzero_bits (XEXP (op0
, 0), mode
)
12750 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12751 + ! equality_comparison_p
))) == 0)
12753 /* We must perform a logical shift, not an arithmetic one,
12754 as we want the top N bits of C to be zero. */
12755 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12757 temp
>>= INTVAL (XEXP (op0
, 1));
12758 op1
= gen_int_mode (temp
, mode
);
12759 op0
= XEXP (op0
, 0);
12763 /* If we are doing a sign bit comparison, it means we are testing
12764 a particular bit. Convert it to the appropriate AND. */
12765 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12766 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12768 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12771 - INTVAL (XEXP (op0
, 1)))));
12772 code
= (code
== LT
? NE
: EQ
);
12776 /* If this an equality comparison with zero and we are shifting
12777 the low bit to the sign bit, we can convert this to an AND of the
12779 if (const_op
== 0 && equality_comparison_p
12780 && CONST_INT_P (XEXP (op0
, 1))
12781 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12783 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12789 /* If this is an equality comparison with zero, we can do this
12790 as a logical shift, which might be much simpler. */
12791 if (equality_comparison_p
&& const_op
== 0
12792 && CONST_INT_P (XEXP (op0
, 1)))
12794 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12796 INTVAL (XEXP (op0
, 1)));
12800 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12801 do the comparison in a narrower mode. */
12802 if (! unsigned_comparison_p
12803 && CONST_INT_P (XEXP (op0
, 1))
12804 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12805 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12806 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12808 && (((unsigned HOST_WIDE_INT
) const_op
12809 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12810 <= GET_MODE_MASK (tmode
)))
12812 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12816 /* Likewise if OP0 is a PLUS of a sign extension with a
12817 constant, which is usually represented with the PLUS
12818 between the shifts. */
12819 if (! unsigned_comparison_p
12820 && CONST_INT_P (XEXP (op0
, 1))
12821 && GET_CODE (XEXP (op0
, 0)) == PLUS
12822 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12823 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12824 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12825 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12827 && (((unsigned HOST_WIDE_INT
) const_op
12828 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12829 <= GET_MODE_MASK (tmode
)))
12831 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12832 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12833 rtx new_const
= simplify_gen_binary (ASHIFTRT
, mode
,
12834 add_const
, XEXP (op0
, 1));
12836 op0
= simplify_gen_binary (PLUS
, tmode
,
12837 gen_lowpart (tmode
, inner
),
12844 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12845 the low order N bits of FOO are known to be zero, we can do this
12846 by comparing FOO with C shifted left N bits so long as no
12847 overflow occurs. Even if the low order N bits of FOO aren't known
12848 to be zero, if the comparison is >= or < we can use the same
12849 optimization and for > or <= by setting all the low
12850 order N bits in the comparison constant. */
12851 if (CONST_INT_P (XEXP (op0
, 1))
12852 && INTVAL (XEXP (op0
, 1)) > 0
12853 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12854 && mode_width
<= HOST_BITS_PER_WIDE_INT
12855 && (((unsigned HOST_WIDE_INT
) const_op
12856 + (GET_CODE (op0
) != LSHIFTRT
12857 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12860 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12862 unsigned HOST_WIDE_INT low_bits
12863 = (nonzero_bits (XEXP (op0
, 0), mode
)
12864 & ((HOST_WIDE_INT_1U
12865 << INTVAL (XEXP (op0
, 1))) - 1));
12866 if (low_bits
== 0 || !equality_comparison_p
)
12868 /* If the shift was logical, then we must make the condition
12870 if (GET_CODE (op0
) == LSHIFTRT
)
12871 code
= unsigned_condition (code
);
12873 const_op
= (unsigned HOST_WIDE_INT
) const_op
12874 << INTVAL (XEXP (op0
, 1));
12876 && (code
== GT
|| code
== GTU
12877 || code
== LE
|| code
== LEU
))
12879 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12880 op1
= GEN_INT (const_op
);
12881 op0
= XEXP (op0
, 0);
12886 /* If we are using this shift to extract just the sign bit, we
12887 can replace this with an LT or GE comparison. */
12889 && (equality_comparison_p
|| sign_bit_comparison_p
)
12890 && CONST_INT_P (XEXP (op0
, 1))
12891 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12893 op0
= XEXP (op0
, 0);
12894 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12906 /* Now make any compound operations involved in this comparison. Then,
12907 check for an outmost SUBREG on OP0 that is not doing anything or is
12908 paradoxical. The latter transformation must only be performed when
12909 it is known that the "extra" bits will be the same in op0 and op1 or
12910 that they don't matter. There are three cases to consider:
12912 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12913 care bits and we can assume they have any convenient value. So
12914 making the transformation is safe.
12916 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12917 In this case the upper bits of op0 are undefined. We should not make
12918 the simplification in that case as we do not know the contents of
12921 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12922 In that case we know those bits are zeros or ones. We must also be
12923 sure that they are the same as the upper bits of op1.
12925 We can never remove a SUBREG for a non-equality comparison because
12926 the sign bit is in a different place in the underlying object. */
12928 rtx_code op0_mco_code
= SET
;
12929 if (op1
== const0_rtx
)
12930 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
12932 op0
= make_compound_operation (op0
, op0_mco_code
);
12933 op1
= make_compound_operation (op1
, SET
);
12935 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12936 && is_int_mode (GET_MODE (op0
), &mode
)
12937 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12938 && (code
== NE
|| code
== EQ
))
12940 if (paradoxical_subreg_p (op0
))
12942 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12944 if (REG_P (SUBREG_REG (op0
)))
12946 op0
= SUBREG_REG (op0
);
12947 op1
= gen_lowpart (inner_mode
, op1
);
12950 else if (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
12951 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
12952 & ~GET_MODE_MASK (mode
)) == 0)
12954 tem
= gen_lowpart (inner_mode
, op1
);
12956 if ((nonzero_bits (tem
, inner_mode
) & ~GET_MODE_MASK (mode
)) == 0)
12957 op0
= SUBREG_REG (op0
), op1
= tem
;
12961 /* We now do the opposite procedure: Some machines don't have compare
12962 insns in all modes. If OP0's mode is an integer mode smaller than a
12963 word and we can't do a compare in that mode, see if there is a larger
12964 mode for which we can do the compare. There are a number of cases in
12965 which we can use the wider mode. */
12967 if (is_int_mode (GET_MODE (op0
), &mode
)
12968 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12969 && ! have_insn_for (COMPARE
, mode
))
12970 FOR_EACH_WIDER_MODE (tmode_iter
, mode
)
12972 tmode
= tmode_iter
.require ();
12973 if (!HWI_COMPUTABLE_MODE_P (tmode
))
12975 if (have_insn_for (COMPARE
, tmode
))
12979 /* If this is a test for negative, we can make an explicit
12980 test of the sign bit. Test this first so we can use
12981 a paradoxical subreg to extend OP0. */
12983 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12984 && HWI_COMPUTABLE_MODE_P (mode
))
12986 unsigned HOST_WIDE_INT sign
12987 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
12988 op0
= simplify_gen_binary (AND
, tmode
,
12989 gen_lowpart (tmode
, op0
),
12990 gen_int_mode (sign
, tmode
));
12991 code
= (code
== LT
) ? NE
: EQ
;
12995 /* If the only nonzero bits in OP0 and OP1 are those in the
12996 narrower mode and this is an equality or unsigned comparison,
12997 we can use the wider mode. Similarly for sign-extended
12998 values, in which case it is true for all comparisons. */
12999 zero_extended
= ((code
== EQ
|| code
== NE
13000 || code
== GEU
|| code
== GTU
13001 || code
== LEU
|| code
== LTU
)
13002 && (nonzero_bits (op0
, tmode
)
13003 & ~GET_MODE_MASK (mode
)) == 0
13004 && ((CONST_INT_P (op1
)
13005 || (nonzero_bits (op1
, tmode
)
13006 & ~GET_MODE_MASK (mode
)) == 0)));
13009 || ((num_sign_bit_copies (op0
, tmode
)
13010 > (unsigned int) (GET_MODE_PRECISION (tmode
)
13011 - GET_MODE_PRECISION (mode
)))
13012 && (num_sign_bit_copies (op1
, tmode
)
13013 > (unsigned int) (GET_MODE_PRECISION (tmode
)
13014 - GET_MODE_PRECISION (mode
)))))
13016 /* If OP0 is an AND and we don't have an AND in MODE either,
13017 make a new AND in the proper mode. */
13018 if (GET_CODE (op0
) == AND
13019 && !have_insn_for (AND
, mode
))
13020 op0
= simplify_gen_binary (AND
, tmode
,
13021 gen_lowpart (tmode
,
13023 gen_lowpart (tmode
,
13029 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
13031 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
13036 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
13038 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
13047 /* We may have changed the comparison operands. Re-canonicalize. */
13048 if (swap_commutative_operands_p (op0
, op1
))
13050 std::swap (op0
, op1
);
13051 code
= swap_condition (code
);
13054 /* If this machine only supports a subset of valid comparisons, see if we
13055 can convert an unsupported one into a supported one. */
13056 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
13064 /* Utility function for record_value_for_reg. Count number of
13069 enum rtx_code code
= GET_CODE (x
);
13073 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
13074 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
13076 rtx x0
= XEXP (x
, 0);
13077 rtx x1
= XEXP (x
, 1);
13080 return 1 + 2 * count_rtxs (x0
);
13082 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
13083 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
13084 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13085 return 2 + 2 * count_rtxs (x0
)
13086 + count_rtxs (x
== XEXP (x1
, 0)
13087 ? XEXP (x1
, 1) : XEXP (x1
, 0));
13089 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
13090 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
13091 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13092 return 2 + 2 * count_rtxs (x1
)
13093 + count_rtxs (x
== XEXP (x0
, 0)
13094 ? XEXP (x0
, 1) : XEXP (x0
, 0));
13097 fmt
= GET_RTX_FORMAT (code
);
13098 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13100 ret
+= count_rtxs (XEXP (x
, i
));
13101 else if (fmt
[i
] == 'E')
13102 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13103 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
13108 /* Utility function for following routine. Called when X is part of a value
13109 being stored into last_set_value. Sets last_set_table_tick
13110 for each register mentioned. Similar to mention_regs in cse.cc */
13113 update_table_tick (rtx x
)
13115 enum rtx_code code
= GET_CODE (x
);
13116 const char *fmt
= GET_RTX_FORMAT (code
);
13121 unsigned int regno
= REGNO (x
);
13122 unsigned int endregno
= END_REGNO (x
);
13125 for (r
= regno
; r
< endregno
; r
++)
13127 reg_stat_type
*rsp
= ®_stat
[r
];
13128 rsp
->last_set_table_tick
= label_tick
;
13134 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13137 /* Check for identical subexpressions. If x contains
13138 identical subexpression we only have to traverse one of
13140 if (i
== 0 && ARITHMETIC_P (x
))
13142 /* Note that at this point x1 has already been
13144 rtx x0
= XEXP (x
, 0);
13145 rtx x1
= XEXP (x
, 1);
13147 /* If x0 and x1 are identical then there is no need to
13152 /* If x0 is identical to a subexpression of x1 then while
13153 processing x1, x0 has already been processed. Thus we
13154 are done with x. */
13155 if (ARITHMETIC_P (x1
)
13156 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13159 /* If x1 is identical to a subexpression of x0 then we
13160 still have to process the rest of x0. */
13161 if (ARITHMETIC_P (x0
)
13162 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13164 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
13169 update_table_tick (XEXP (x
, i
));
13171 else if (fmt
[i
] == 'E')
13172 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13173 update_table_tick (XVECEXP (x
, i
, j
));
13176 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13177 are saying that the register is clobbered and we no longer know its
13178 value. If INSN is zero, don't update reg_stat[].last_set; this is
13179 only permitted with VALUE also zero and is used to invalidate the
13183 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
13185 unsigned int regno
= REGNO (reg
);
13186 unsigned int endregno
= END_REGNO (reg
);
13188 reg_stat_type
*rsp
;
13190 /* If VALUE contains REG and we have a previous value for REG, substitute
13191 the previous value. */
13192 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
13196 /* Set things up so get_last_value is allowed to see anything set up to
13198 subst_low_luid
= DF_INSN_LUID (insn
);
13199 tem
= get_last_value (reg
);
13201 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13202 it isn't going to be useful and will take a lot of time to process,
13203 so just use the CLOBBER. */
13207 if (ARITHMETIC_P (tem
)
13208 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
13209 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
13210 tem
= XEXP (tem
, 0);
13211 else if (count_occurrences (value
, reg
, 1) >= 2)
13213 /* If there are two or more occurrences of REG in VALUE,
13214 prevent the value from growing too much. */
13215 if (count_rtxs (tem
) > param_max_last_value_rtl
)
13216 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
13219 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
13223 /* For each register modified, show we don't know its value, that
13224 we don't know about its bitwise content, that its value has been
13225 updated, and that we don't know the location of the death of the
13227 for (i
= regno
; i
< endregno
; i
++)
13229 rsp
= ®_stat
[i
];
13232 rsp
->last_set
= insn
;
13234 rsp
->last_set_value
= 0;
13235 rsp
->last_set_mode
= VOIDmode
;
13236 rsp
->last_set_nonzero_bits
= 0;
13237 rsp
->last_set_sign_bit_copies
= 0;
13238 rsp
->last_death
= 0;
13239 rsp
->truncated_to_mode
= VOIDmode
;
13242 /* Mark registers that are being referenced in this value. */
13244 update_table_tick (value
);
13246 /* Now update the status of each register being set.
13247 If someone is using this register in this block, set this register
13248 to invalid since we will get confused between the two lives in this
13249 basic block. This makes using this register always invalid. In cse, we
13250 scan the table to invalidate all entries using this register, but this
13251 is too much work for us. */
13253 for (i
= regno
; i
< endregno
; i
++)
13255 rsp
= ®_stat
[i
];
13256 rsp
->last_set_label
= label_tick
;
13258 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
13259 rsp
->last_set_invalid
= 1;
13261 rsp
->last_set_invalid
= 0;
13264 /* The value being assigned might refer to X (like in "x++;"). In that
13265 case, we must replace it with (clobber (const_int 0)) to prevent
13267 rsp
= ®_stat
[regno
];
13268 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
13270 value
= copy_rtx (value
);
13271 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
13275 /* For the main register being modified, update the value, the mode, the
13276 nonzero bits, and the number of sign bit copies. */
13278 rsp
->last_set_value
= value
;
13282 machine_mode mode
= GET_MODE (reg
);
13283 subst_low_luid
= DF_INSN_LUID (insn
);
13284 rsp
->last_set_mode
= mode
;
13285 if (GET_MODE_CLASS (mode
) == MODE_INT
13286 && HWI_COMPUTABLE_MODE_P (mode
))
13287 mode
= nonzero_bits_mode
;
13288 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
13289 rsp
->last_set_sign_bit_copies
13290 = num_sign_bit_copies (value
, GET_MODE (reg
));
13294 /* Called via note_stores from record_dead_and_set_regs to handle one
13295 SET or CLOBBER in an insn. DATA is the instruction in which the
13296 set is occurring. */
13299 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13301 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13303 if (GET_CODE (dest
) == SUBREG
)
13304 dest
= SUBREG_REG (dest
);
13306 if (!record_dead_insn
)
13309 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13315 /* If we are setting the whole register, we know its value. Otherwise
13316 show that we don't know the value. We can handle a SUBREG if it's
13317 the low part, but we must be careful with paradoxical SUBREGs on
13318 RISC architectures because we cannot strip e.g. an extension around
13319 a load and record the naked load since the RTL middle-end considers
13320 that the upper bits are defined according to LOAD_EXTEND_OP. */
13321 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13322 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13323 else if (GET_CODE (setter
) == SET
13324 && GET_CODE (SET_DEST (setter
)) == SUBREG
13325 && SUBREG_REG (SET_DEST (setter
)) == dest
13326 && known_le (GET_MODE_PRECISION (GET_MODE (dest
)),
13328 && subreg_lowpart_p (SET_DEST (setter
)))
13329 record_value_for_reg (dest
, record_dead_insn
,
13330 WORD_REGISTER_OPERATIONS
13331 && word_register_operation_p (SET_SRC (setter
))
13332 && paradoxical_subreg_p (SET_DEST (setter
))
13334 : gen_lowpart (GET_MODE (dest
),
13335 SET_SRC (setter
)));
13337 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13339 else if (MEM_P (dest
)
13340 /* Ignore pushes, they clobber nothing. */
13341 && ! push_operand (dest
, GET_MODE (dest
)))
13342 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13345 /* Update the records of when each REG was most recently set or killed
13346 for the things done by INSN. This is the last thing done in processing
13347 INSN in the combiner loop.
13349 We update reg_stat[], in particular fields last_set, last_set_value,
13350 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13351 last_death, and also the similar information mem_last_set (which insn
13352 most recently modified memory) and last_call_luid (which insn was the
13353 most recent subroutine call). */
13356 record_dead_and_set_regs (rtx_insn
*insn
)
13361 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13363 if (REG_NOTE_KIND (link
) == REG_DEAD
13364 && REG_P (XEXP (link
, 0)))
13366 unsigned int regno
= REGNO (XEXP (link
, 0));
13367 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13369 for (i
= regno
; i
< endregno
; i
++)
13371 reg_stat_type
*rsp
;
13373 rsp
= ®_stat
[i
];
13374 rsp
->last_death
= insn
;
13377 else if (REG_NOTE_KIND (link
) == REG_INC
)
13378 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13383 HARD_REG_SET callee_clobbers
13384 = insn_callee_abi (insn
).full_and_partial_reg_clobbers ();
13385 hard_reg_set_iterator hrsi
;
13386 EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers
, 0, i
, hrsi
)
13388 reg_stat_type
*rsp
;
13390 /* ??? We could try to preserve some information from the last
13391 set of register I if the call doesn't actually clobber
13392 (reg:last_set_mode I), which might be true for ABIs with
13393 partial clobbers. However, it would be difficult to
13394 update last_set_nonzero_bits and last_sign_bit_copies
13395 to account for the part of I that actually was clobbered.
13396 It wouldn't help much anyway, since we rarely see this
13397 situation before RA. */
13398 rsp
= ®_stat
[i
];
13399 rsp
->last_set_invalid
= 1;
13400 rsp
->last_set
= insn
;
13401 rsp
->last_set_value
= 0;
13402 rsp
->last_set_mode
= VOIDmode
;
13403 rsp
->last_set_nonzero_bits
= 0;
13404 rsp
->last_set_sign_bit_copies
= 0;
13405 rsp
->last_death
= 0;
13406 rsp
->truncated_to_mode
= VOIDmode
;
13409 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13411 /* We can't combine into a call pattern. Remember, though, that
13412 the return value register is set at this LUID. We could
13413 still replace a register with the return value from the
13414 wrong subroutine call! */
13415 note_stores (insn
, record_dead_and_set_regs_1
, NULL_RTX
);
13418 note_stores (insn
, record_dead_and_set_regs_1
, insn
);
13421 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13422 register present in the SUBREG, so for each such SUBREG go back and
13423 adjust nonzero and sign bit information of the registers that are
13424 known to have some zero/sign bits set.
13426 This is needed because when combine blows the SUBREGs away, the
13427 information on zero/sign bits is lost and further combines can be
13428 missed because of that. */
13431 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13433 struct insn_link
*links
;
13435 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13436 machine_mode mode
= GET_MODE (subreg
);
13438 if (!HWI_COMPUTABLE_MODE_P (mode
))
13441 for (links
= LOG_LINKS (insn
); links
;)
13443 reg_stat_type
*rsp
;
13445 insn
= links
->insn
;
13446 set
= single_set (insn
);
13448 if (! set
|| !REG_P (SET_DEST (set
))
13449 || REGNO (SET_DEST (set
)) != regno
13450 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13452 links
= links
->next
;
13456 rsp
= ®_stat
[regno
];
13457 if (rsp
->last_set
== insn
)
13459 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13460 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13463 if (REG_P (SET_SRC (set
)))
13465 regno
= REGNO (SET_SRC (set
));
13466 links
= LOG_LINKS (insn
);
13473 /* Check if X, a register, is known to contain a value already
13474 truncated to MODE. In this case we can use a subreg to refer to
13475 the truncated value even though in the generic case we would need
13476 an explicit truncation. */
13479 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13481 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13482 machine_mode truncated
= rsp
->truncated_to_mode
;
13485 || rsp
->truncation_label
< label_tick_ebb_start
)
13487 if (!partial_subreg_p (mode
, truncated
))
13489 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13494 /* If X is a hard reg or a subreg record the mode that the register is
13495 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13496 able to turn a truncate into a subreg using this information. Return true
13497 if traversing X is complete. */
13500 record_truncated_value (rtx x
)
13502 machine_mode truncated_mode
;
13503 reg_stat_type
*rsp
;
13505 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13507 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13508 truncated_mode
= GET_MODE (x
);
13510 if (!partial_subreg_p (truncated_mode
, original_mode
))
13513 truncated_mode
= GET_MODE (x
);
13514 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13517 x
= SUBREG_REG (x
);
13519 /* ??? For hard-regs we now record everything. We might be able to
13520 optimize this using last_set_mode. */
13521 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13522 truncated_mode
= GET_MODE (x
);
13526 rsp
= ®_stat
[REGNO (x
)];
13527 if (rsp
->truncated_to_mode
== 0
13528 || rsp
->truncation_label
< label_tick_ebb_start
13529 || partial_subreg_p (truncated_mode
, rsp
->truncated_to_mode
))
13531 rsp
->truncated_to_mode
= truncated_mode
;
13532 rsp
->truncation_label
= label_tick
;
13538 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13539 the modes they are used in. This can help truning TRUNCATEs into
13543 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13545 subrtx_var_iterator::array_type array
;
13546 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13547 if (record_truncated_value (*iter
))
13548 iter
.skip_subrtxes ();
13551 /* Scan X for promoted SUBREGs. For each one found,
13552 note what it implies to the registers used in it. */
13555 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13557 if (GET_CODE (x
) == SUBREG
13558 && SUBREG_PROMOTED_VAR_P (x
)
13559 && REG_P (SUBREG_REG (x
)))
13560 record_promoted_value (insn
, x
);
13563 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13566 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13570 check_promoted_subreg (insn
, XEXP (x
, i
));
13574 if (XVEC (x
, i
) != 0)
13575 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13576 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13582 /* Verify that all the registers and memory references mentioned in *LOC are
13583 still valid. *LOC was part of a value set in INSN when label_tick was
13584 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13585 the invalid references with (clobber (const_int 0)) and return 1. This
13586 replacement is useful because we often can get useful information about
13587 the form of a value (e.g., if it was produced by a shift that always
13588 produces -1 or 0) even though we don't know exactly what registers it
13589 was produced from. */
13592 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13595 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13596 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13601 unsigned int regno
= REGNO (x
);
13602 unsigned int endregno
= END_REGNO (x
);
13605 for (j
= regno
; j
< endregno
; j
++)
13607 reg_stat_type
*rsp
= ®_stat
[j
];
13608 if (rsp
->last_set_invalid
13609 /* If this is a pseudo-register that was only set once and not
13610 live at the beginning of the function, it is always valid. */
13611 || (! (regno
>= FIRST_PSEUDO_REGISTER
13612 && regno
< reg_n_sets_max
13613 && REG_N_SETS (regno
) == 1
13614 && (!REGNO_REG_SET_P
13615 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13617 && rsp
->last_set_label
> tick
))
13620 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13627 /* If this is a memory reference, make sure that there were no stores after
13628 it that might have clobbered the value. We don't have alias info, so we
13629 assume any store invalidates it. Moreover, we only have local UIDs, so
13630 we also assume that there were stores in the intervening basic blocks. */
13631 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13632 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13635 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13639 for (i
= 0; i
< len
; i
++)
13643 /* Check for identical subexpressions. If x contains
13644 identical subexpression we only have to traverse one of
13646 if (i
== 1 && ARITHMETIC_P (x
))
13648 /* Note that at this point x0 has already been checked
13649 and found valid. */
13650 rtx x0
= XEXP (x
, 0);
13651 rtx x1
= XEXP (x
, 1);
13653 /* If x0 and x1 are identical then x is also valid. */
13657 /* If x1 is identical to a subexpression of x0 then
13658 while checking x0, x1 has already been checked. Thus
13659 it is valid and so as x. */
13660 if (ARITHMETIC_P (x0
)
13661 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13664 /* If x0 is identical to a subexpression of x1 then x is
13665 valid iff the rest of x1 is valid. */
13666 if (ARITHMETIC_P (x1
)
13667 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13669 get_last_value_validate (&XEXP (x1
,
13670 x0
== XEXP (x1
, 0) ? 1 : 0),
13671 insn
, tick
, replace
);
13674 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13678 else if (fmt
[i
] == 'E')
13679 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13680 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13681 insn
, tick
, replace
) == 0)
13685 /* If we haven't found a reason for it to be invalid, it is valid. */
13689 /* Get the last value assigned to X, if known. Some registers
13690 in the value may be replaced with (clobber (const_int 0)) if their value
13691 is known longer known reliably. */
13694 get_last_value (const_rtx x
)
13696 unsigned int regno
;
13698 reg_stat_type
*rsp
;
13700 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13701 then convert it to the desired mode. If this is a paradoxical SUBREG,
13702 we cannot predict what values the "extra" bits might have. */
13703 if (GET_CODE (x
) == SUBREG
13704 && subreg_lowpart_p (x
)
13705 && !paradoxical_subreg_p (x
)
13706 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13707 return gen_lowpart (GET_MODE (x
), value
);
13713 rsp
= ®_stat
[regno
];
13714 value
= rsp
->last_set_value
;
13716 /* If we don't have a value, or if it isn't for this basic block and
13717 it's either a hard register, set more than once, or it's a live
13718 at the beginning of the function, return 0.
13720 Because if it's not live at the beginning of the function then the reg
13721 is always set before being used (is never used without being set).
13722 And, if it's set only once, and it's always set before use, then all
13723 uses must have the same last value, even if it's not from this basic
13727 || (rsp
->last_set_label
< label_tick_ebb_start
13728 && (regno
< FIRST_PSEUDO_REGISTER
13729 || regno
>= reg_n_sets_max
13730 || REG_N_SETS (regno
) != 1
13732 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13735 /* If the value was set in a later insn than the ones we are processing,
13736 we can't use it even if the register was only set once. */
13737 if (rsp
->last_set_label
== label_tick
13738 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13741 /* If fewer bits were set than what we are asked for now, we cannot use
13743 if (maybe_lt (GET_MODE_PRECISION (rsp
->last_set_mode
),
13744 GET_MODE_PRECISION (GET_MODE (x
))))
13747 /* If the value has all its registers valid, return it. */
13748 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13751 /* Otherwise, make a copy and replace any invalid register with
13752 (clobber (const_int 0)). If that fails for some reason, return 0. */
13754 value
= copy_rtx (value
);
13755 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13761 /* Define three variables used for communication between the following
13764 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13765 static int reg_dead_flag
;
13768 /* Function called via note_stores from reg_dead_at_p.
13770 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13771 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13774 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13776 unsigned int regno
, endregno
;
13781 regno
= REGNO (dest
);
13782 endregno
= END_REGNO (dest
);
13783 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13784 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13787 /* Return nonzero if REG is known to be dead at INSN.
13789 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13790 referencing REG, it is dead. If we hit a SET referencing REG, it is
13791 live. Otherwise, see if it is live or dead at the start of the basic
13792 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13793 must be assumed to be always live. */
13796 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13801 /* Set variables for reg_dead_at_p_1. */
13802 reg_dead_regno
= REGNO (reg
);
13803 reg_dead_endregno
= END_REGNO (reg
);
13804 reg_dead_reg
= reg
;
13808 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13809 we allow the machine description to decide whether use-and-clobber
13810 patterns are OK. */
13811 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13813 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13814 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13818 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13819 beginning of basic block. */
13820 block
= BLOCK_FOR_INSN (insn
);
13825 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13828 note_stores (insn
, reg_dead_at_p_1
, NULL
);
13830 return reg_dead_flag
== 1 ? 1 : 0;
13832 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13836 if (insn
== BB_HEAD (block
))
13839 insn
= PREV_INSN (insn
);
13842 /* Look at live-in sets for the basic block that we were in. */
13843 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13844 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13850 /* Note hard registers in X that are used. */
13853 mark_used_regs_combine (rtx x
)
13855 RTX_CODE code
= GET_CODE (x
);
13856 unsigned int regno
;
13867 case ADDR_DIFF_VEC
:
13872 /* If we are clobbering a MEM, mark any hard registers inside the
13873 address as used. */
13874 if (MEM_P (XEXP (x
, 0)))
13875 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13880 /* A hard reg in a wide mode may really be multiple registers.
13881 If so, mark all of them just like the first. */
13882 if (regno
< FIRST_PSEUDO_REGISTER
)
13884 /* None of this applies to the stack, frame or arg pointers. */
13885 if (regno
== STACK_POINTER_REGNUM
13886 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13887 && regno
== HARD_FRAME_POINTER_REGNUM
)
13888 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13889 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13890 || regno
== FRAME_POINTER_REGNUM
)
13893 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13899 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13901 rtx testreg
= SET_DEST (x
);
13903 while (GET_CODE (testreg
) == SUBREG
13904 || GET_CODE (testreg
) == ZERO_EXTRACT
13905 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13906 testreg
= XEXP (testreg
, 0);
13908 if (MEM_P (testreg
))
13909 mark_used_regs_combine (XEXP (testreg
, 0));
13911 mark_used_regs_combine (SET_SRC (x
));
13919 /* Recursively scan the operands of this expression. */
13922 const char *fmt
= GET_RTX_FORMAT (code
);
13924 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13927 mark_used_regs_combine (XEXP (x
, i
));
13928 else if (fmt
[i
] == 'E')
13932 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13933 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13939 /* Remove register number REGNO from the dead registers list of INSN.
13941 Return the note used to record the death, if there was one. */
13944 remove_death (unsigned int regno
, rtx_insn
*insn
)
13946 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13949 remove_note (insn
, note
);
13954 /* For each register (hardware or pseudo) used within expression X, if its
13955 death is in an instruction with luid between FROM_LUID (inclusive) and
13956 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13957 list headed by PNOTES.
13959 That said, don't move registers killed by maybe_kill_insn.
13961 This is done when X is being merged by combination into TO_INSN. These
13962 notes will then be distributed as needed. */
13965 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13970 enum rtx_code code
= GET_CODE (x
);
13974 unsigned int regno
= REGNO (x
);
13975 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13977 /* If we do not know where the register died, it may still die between
13978 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
13979 if (!where_dead
|| DF_INSN_LUID (where_dead
) >= DF_INSN_LUID (to_insn
))
13981 rtx_insn
*insn
= prev_real_nondebug_insn (to_insn
);
13983 && BLOCK_FOR_INSN (insn
) == BLOCK_FOR_INSN (to_insn
)
13984 && DF_INSN_LUID (insn
) >= from_luid
)
13986 if (dead_or_set_regno_p (insn
, regno
))
13988 if (find_regno_note (insn
, REG_DEAD
, regno
))
13993 insn
= prev_real_nondebug_insn (insn
);
13997 /* Don't move the register if it gets killed in between from and to. */
13998 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13999 && ! reg_referenced_p (x
, maybe_kill_insn
))
14003 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
14004 && DF_INSN_LUID (where_dead
) >= from_luid
14005 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
14007 rtx note
= remove_death (regno
, where_dead
);
14009 /* It is possible for the call above to return 0. This can occur
14010 when last_death points to I2 or I1 that we combined with.
14011 In that case make a new note.
14013 We must also check for the case where X is a hard register
14014 and NOTE is a death note for a range of hard registers
14015 including X. In that case, we must put REG_DEAD notes for
14016 the remaining registers in place of NOTE. */
14018 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
14019 && partial_subreg_p (GET_MODE (x
), GET_MODE (XEXP (note
, 0))))
14021 unsigned int deadregno
= REGNO (XEXP (note
, 0));
14022 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
14023 unsigned int ourend
= END_REGNO (x
);
14026 for (i
= deadregno
; i
< deadend
; i
++)
14027 if (i
< regno
|| i
>= ourend
)
14028 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
14031 /* If we didn't find any note, or if we found a REG_DEAD note that
14032 covers only part of the given reg, and we have a multi-reg hard
14033 register, then to be safe we must check for REG_DEAD notes
14034 for each register other than the first. They could have
14035 their own REG_DEAD notes lying around. */
14036 else if ((note
== 0
14038 && partial_subreg_p (GET_MODE (XEXP (note
, 0)),
14040 && regno
< FIRST_PSEUDO_REGISTER
14041 && REG_NREGS (x
) > 1)
14043 unsigned int ourend
= END_REGNO (x
);
14044 unsigned int i
, offset
;
14048 offset
= hard_regno_nregs (regno
, GET_MODE (XEXP (note
, 0)));
14052 for (i
= regno
+ offset
; i
< ourend
; i
++)
14053 move_deaths (regno_reg_rtx
[i
],
14054 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
14057 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
14059 XEXP (note
, 1) = *pnotes
;
14063 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
14069 else if (GET_CODE (x
) == SET
)
14071 rtx dest
= SET_DEST (x
);
14073 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14075 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14076 that accesses one word of a multi-word item, some
14077 piece of everything register in the expression is used by
14078 this insn, so remove any old death. */
14079 /* ??? So why do we test for equality of the sizes? */
14081 if (GET_CODE (dest
) == ZERO_EXTRACT
14082 || GET_CODE (dest
) == STRICT_LOW_PART
14083 || (GET_CODE (dest
) == SUBREG
14084 && !read_modify_subreg_p (dest
)))
14086 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14090 /* If this is some other SUBREG, we know it replaces the entire
14091 value, so use that as the destination. */
14092 if (GET_CODE (dest
) == SUBREG
)
14093 dest
= SUBREG_REG (dest
);
14095 /* If this is a MEM, adjust deaths of anything used in the address.
14096 For a REG (the only other possibility), the entire value is
14097 being replaced so the old value is not used in this insn. */
14100 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
14105 else if (GET_CODE (x
) == CLOBBER
)
14108 len
= GET_RTX_LENGTH (code
);
14109 fmt
= GET_RTX_FORMAT (code
);
14111 for (i
= 0; i
< len
; i
++)
14116 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
14117 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
14120 else if (fmt
[i
] == 'e')
14121 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14125 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14126 pattern of an insn. X must be a REG. */
14129 reg_bitfield_target_p (rtx x
, rtx body
)
14133 if (GET_CODE (body
) == SET
)
14135 rtx dest
= SET_DEST (body
);
14137 unsigned int regno
, tregno
, endregno
, endtregno
;
14139 if (GET_CODE (dest
) == ZERO_EXTRACT
)
14140 target
= XEXP (dest
, 0);
14141 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
14142 target
= SUBREG_REG (XEXP (dest
, 0));
14146 if (GET_CODE (target
) == SUBREG
)
14147 target
= SUBREG_REG (target
);
14149 if (!REG_P (target
))
14152 tregno
= REGNO (target
), regno
= REGNO (x
);
14153 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
14154 return target
== x
;
14156 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
14157 endregno
= end_hard_regno (GET_MODE (x
), regno
);
14159 return endregno
> tregno
&& regno
< endtregno
;
14162 else if (GET_CODE (body
) == PARALLEL
)
14163 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
14164 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
14170 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14171 as appropriate. I3 and I2 are the insns resulting from the combination
14172 insns including FROM (I2 may be zero).
14174 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14175 not need REG_DEAD notes because they are being substituted for. This
14176 saves searching in the most common cases.
14178 Each note in the list is either ignored or placed on some insns, depending
14179 on the type of note. */
14182 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
14183 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
14185 rtx note
, next_note
;
14187 rtx_insn
*tem_insn
;
14189 for (note
= notes
; note
; note
= next_note
)
14191 rtx_insn
*place
= 0, *place2
= 0;
14193 next_note
= XEXP (note
, 1);
14194 switch (REG_NOTE_KIND (note
))
14198 /* Doesn't matter much where we put this, as long as it's somewhere.
14199 It is preferable to keep these notes on branches, which is most
14200 likely to be i3. */
14204 case REG_NON_LOCAL_GOTO
:
14209 gcc_assert (i2
&& JUMP_P (i2
));
14214 case REG_EH_REGION
:
14216 /* The landing pad handling needs to be kept in sync with the
14217 prerequisite checking in try_combine. */
14218 int lp_nr
= INTVAL (XEXP (note
, 0));
14219 /* A REG_EH_REGION note transfering control can only ever come
14222 gcc_assert (from_insn
== i3
);
14223 /* We are making sure there is a single effective REG_EH_REGION
14224 note and it's valid to put it on i3. */
14225 if (!insn_could_throw_p (from_insn
)
14226 && !(lp_nr
== INT_MIN
&& can_nonlocal_goto (from_insn
)))
14227 /* Throw away stray notes on insns that can never throw or
14228 make a nonlocal goto. */
14236 gcc_assert (cfun
->can_throw_non_call_exceptions
);
14237 /* If i3 can still trap preserve the note, otherwise we've
14238 combined things such that we can now prove that the
14239 instructions can't trap. Drop the note in this case. */
14240 if (may_trap_p (i3
))
14247 case REG_ARGS_SIZE
:
14248 /* ??? How to distribute between i3-i1. Assume i3 contains the
14249 entire adjustment. Assert i3 contains at least some adjust. */
14250 if (!noop_move_p (i3
))
14252 poly_int64 old_size
, args_size
= get_args_size (note
);
14253 /* fixup_args_size_notes looks at REG_NORETURN note,
14254 so ensure the note is placed there first. */
14258 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
14259 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
14263 XEXP (n
, 1) = REG_NOTES (i3
);
14264 REG_NOTES (i3
) = n
;
14268 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
14269 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14270 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14271 gcc_assert (maybe_ne (old_size
, args_size
)
14273 && !ACCUMULATE_OUTGOING_ARGS
14274 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
14281 case REG_CALL_DECL
:
14282 case REG_UNTYPED_CALL
:
14283 case REG_CALL_NOCF_CHECK
:
14284 /* These notes must remain with the call. It should not be
14285 possible for both I2 and I3 to be a call. */
14290 gcc_assert (i2
&& CALL_P (i2
));
14296 /* Any clobbers for i3 may still exist, and so we must process
14297 REG_UNUSED notes from that insn.
14299 Any clobbers from i2 or i1 can only exist if they were added by
14300 recog_for_combine. In that case, recog_for_combine created the
14301 necessary REG_UNUSED notes. Trying to keep any original
14302 REG_UNUSED notes from these insns can cause incorrect output
14303 if it is for the same register as the original i3 dest.
14304 In that case, we will notice that the register is set in i3,
14305 and then add a REG_UNUSED note for the destination of i3, which
14306 is wrong. However, it is possible to have REG_UNUSED notes from
14307 i2 or i1 for register which were both used and clobbered, so
14308 we keep notes from i2 or i1 if they will turn into REG_DEAD
14311 /* If this register is set or clobbered between FROM_INSN and I3,
14312 we should not create a note for it. */
14313 if (reg_set_between_p (XEXP (note
, 0), from_insn
, i3
))
14316 /* If this register is set or clobbered in I3, put the note there
14317 unless there is one already. */
14318 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14320 if (from_insn
!= i3
)
14323 if (! (REG_P (XEXP (note
, 0))
14324 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14325 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14328 /* Otherwise, if this register is used by I3, then this register
14329 now dies here, so we must put a REG_DEAD note here unless there
14331 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14332 && ! (REG_P (XEXP (note
, 0))
14333 ? find_regno_note (i3
, REG_DEAD
,
14334 REGNO (XEXP (note
, 0)))
14335 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14337 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14341 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14342 but we can't tell which at this point. We must reset any
14343 expectations we had about the value that was previously
14344 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14345 and, if appropriate, restore its previous value, but we
14346 don't have enough information for that at this point. */
14349 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14351 /* Otherwise, if this register is now referenced in i2
14352 then the register used to be modified in one of the
14353 original insns. If it was i3 (say, in an unused
14354 parallel), it's now completely gone, so the note can
14355 be discarded. But if it was modified in i2, i1 or i0
14356 and we still reference it in i2, then we're
14357 referencing the previous value, and since the
14358 register was modified and REG_UNUSED, we know that
14359 the previous value is now dead. So, if we only
14360 reference the register in i2, we change the note to
14361 REG_DEAD, to reflect the previous value. However, if
14362 we're also setting or clobbering the register as
14363 scratch, we know (because the register was not
14364 referenced in i3) that it's unused, just as it was
14365 unused before, and we place the note in i2. */
14366 if (from_insn
!= i3
&& i2
&& INSN_P (i2
)
14367 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14369 if (!reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14370 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14371 if (! (REG_P (XEXP (note
, 0))
14372 ? find_regno_note (i2
, REG_NOTE_KIND (note
),
14373 REGNO (XEXP (note
, 0)))
14374 : find_reg_note (i2
, REG_NOTE_KIND (note
),
14385 /* These notes say something about results of an insn. We can
14386 only support them if they used to be on I3 in which case they
14387 remain on I3. Otherwise they are ignored.
14389 If the note refers to an expression that is not a constant, we
14390 must also ignore the note since we cannot tell whether the
14391 equivalence is still true. It might be possible to do
14392 slightly better than this (we only have a problem if I2DEST
14393 or I1DEST is present in the expression), but it doesn't
14394 seem worth the trouble. */
14396 if (from_insn
== i3
14397 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14402 /* These notes say something about how a register is used. They must
14403 be present on any use of the register in I2 or I3. */
14404 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14407 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14416 case REG_LABEL_TARGET
:
14417 case REG_LABEL_OPERAND
:
14418 /* This can show up in several ways -- either directly in the
14419 pattern, or hidden off in the constant pool with (or without?)
14420 a REG_EQUAL note. */
14421 /* ??? Ignore the without-reg_equal-note problem for now. */
14422 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14423 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14424 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14425 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14429 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14430 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14431 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14432 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14440 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14441 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14443 if (place
&& JUMP_P (place
)
14444 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14445 && (JUMP_LABEL (place
) == NULL
14446 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14448 rtx label
= JUMP_LABEL (place
);
14451 JUMP_LABEL (place
) = XEXP (note
, 0);
14452 else if (LABEL_P (label
))
14453 LABEL_NUSES (label
)--;
14456 if (place2
&& JUMP_P (place2
)
14457 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14458 && (JUMP_LABEL (place2
) == NULL
14459 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14461 rtx label
= JUMP_LABEL (place2
);
14464 JUMP_LABEL (place2
) = XEXP (note
, 0);
14465 else if (LABEL_P (label
))
14466 LABEL_NUSES (label
)--;
14472 /* This note says something about the value of a register prior
14473 to the execution of an insn. It is too much trouble to see
14474 if the note is still correct in all situations. It is better
14475 to simply delete it. */
14479 /* If we replaced the right hand side of FROM_INSN with a
14480 REG_EQUAL note, the original use of the dying register
14481 will not have been combined into I3 and I2. In such cases,
14482 FROM_INSN is guaranteed to be the first of the combined
14483 instructions, so we simply need to search back before
14484 FROM_INSN for the previous use or set of this register,
14485 then alter the notes there appropriately.
14487 If the register is used as an input in I3, it dies there.
14488 Similarly for I2, if it is nonzero and adjacent to I3.
14490 If the register is not used as an input in either I3 or I2
14491 and it is not one of the registers we were supposed to eliminate,
14492 there are two possibilities. We might have a non-adjacent I2
14493 or we might have somehow eliminated an additional register
14494 from a computation. For example, we might have had A & B where
14495 we discover that B will always be zero. In this case we will
14496 eliminate the reference to A.
14498 In both cases, we must search to see if we can find a previous
14499 use of A and put the death note there. */
14502 && from_insn
== i2mod
14503 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14504 tem_insn
= from_insn
;
14508 && CALL_P (from_insn
)
14509 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14511 else if (i2
&& reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14513 /* If the new I2 sets the same register that is marked
14514 dead in the note, we do not in general know where to
14515 put the note. One important case we _can_ handle is
14516 when the note comes from I3. */
14517 if (from_insn
== i3
)
14522 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14524 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14525 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14527 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14529 && reg_overlap_mentioned_p (XEXP (note
, 0),
14531 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14532 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14539 basic_block bb
= this_basic_block
;
14541 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14543 if (!NONDEBUG_INSN_P (tem_insn
))
14545 if (tem_insn
== BB_HEAD (bb
))
14550 /* If the register is being set at TEM_INSN, see if that is all
14551 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14552 into a REG_UNUSED note instead. Don't delete sets to
14553 global register vars. */
14554 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14555 || !global_regs
[REGNO (XEXP (note
, 0))])
14556 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14558 rtx set
= single_set (tem_insn
);
14559 rtx inner_dest
= 0;
14562 for (inner_dest
= SET_DEST (set
);
14563 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14564 || GET_CODE (inner_dest
) == SUBREG
14565 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14566 inner_dest
= XEXP (inner_dest
, 0))
14569 /* Verify that it was the set, and not a clobber that
14570 modified the register.
14572 If we cannot delete the setter due to side
14573 effects, mark the user with an UNUSED note instead
14576 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14577 && rtx_equal_p (XEXP (note
, 0), inner_dest
))
14579 /* Move the notes and links of TEM_INSN elsewhere.
14580 This might delete other dead insns recursively.
14581 First set the pattern to something that won't use
14583 rtx old_notes
= REG_NOTES (tem_insn
);
14585 PATTERN (tem_insn
) = pc_rtx
;
14586 REG_NOTES (tem_insn
) = NULL
;
14588 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14589 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14590 distribute_links (LOG_LINKS (tem_insn
));
14592 unsigned int regno
= REGNO (XEXP (note
, 0));
14593 reg_stat_type
*rsp
= ®_stat
[regno
];
14594 if (rsp
->last_set
== tem_insn
)
14595 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14597 SET_INSN_DELETED (tem_insn
);
14598 if (tem_insn
== i2
)
14603 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14605 /* If there isn't already a REG_UNUSED note, put one
14606 here. Do not place a REG_DEAD note, even if
14607 the register is also used here; that would not
14608 match the algorithm used in lifetime analysis
14609 and can cause the consistency check in the
14610 scheduler to fail. */
14611 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14612 REGNO (XEXP (note
, 0))))
14617 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14618 || (CALL_P (tem_insn
)
14619 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14623 /* If we are doing a 3->2 combination, and we have a
14624 register which formerly died in i3 and was not used
14625 by i2, which now no longer dies in i3 and is used in
14626 i2 but does not die in i2, and place is between i2
14627 and i3, then we may need to move a link from place to
14629 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14631 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14632 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14634 struct insn_link
*links
= LOG_LINKS (place
);
14635 LOG_LINKS (place
) = NULL
;
14636 distribute_links (links
);
14641 if (tem_insn
== BB_HEAD (bb
))
14647 /* If the register is set or already dead at PLACE, we needn't do
14648 anything with this note if it is still a REG_DEAD note.
14649 We check here if it is set at all, not if is it totally replaced,
14650 which is what `dead_or_set_p' checks, so also check for it being
14653 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14655 unsigned int regno
= REGNO (XEXP (note
, 0));
14656 reg_stat_type
*rsp
= ®_stat
[regno
];
14658 if (dead_or_set_p (place
, XEXP (note
, 0))
14659 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14661 /* Unless the register previously died in PLACE, clear
14662 last_death. [I no longer understand why this is
14664 if (rsp
->last_death
!= place
)
14665 rsp
->last_death
= 0;
14669 rsp
->last_death
= place
;
14671 /* If this is a death note for a hard reg that is occupying
14672 multiple registers, ensure that we are still using all
14673 parts of the object. If we find a piece of the object
14674 that is unused, we must arrange for an appropriate REG_DEAD
14675 note to be added for it. However, we can't just emit a USE
14676 and tag the note to it, since the register might actually
14677 be dead; so we recourse, and the recursive call then finds
14678 the previous insn that used this register. */
14680 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14682 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14683 bool all_used
= true;
14686 for (i
= regno
; i
< endregno
; i
++)
14687 if ((! refers_to_regno_p (i
, PATTERN (place
))
14688 && ! find_regno_fusage (place
, USE
, i
))
14689 || dead_or_set_regno_p (place
, i
))
14697 /* Put only REG_DEAD notes for pieces that are
14698 not already dead or set. */
14700 for (i
= regno
; i
< endregno
;
14701 i
+= hard_regno_nregs (i
, reg_raw_mode
[i
]))
14703 rtx piece
= regno_reg_rtx
[i
];
14704 basic_block bb
= this_basic_block
;
14706 if (! dead_or_set_p (place
, piece
)
14707 && ! reg_bitfield_target_p (piece
,
14710 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14713 distribute_notes (new_note
, place
, place
,
14714 NULL
, NULL_RTX
, NULL_RTX
,
14717 else if (! refers_to_regno_p (i
, PATTERN (place
))
14718 && ! find_regno_fusage (place
, USE
, i
))
14719 for (tem_insn
= PREV_INSN (place
); ;
14720 tem_insn
= PREV_INSN (tem_insn
))
14722 if (!NONDEBUG_INSN_P (tem_insn
))
14724 if (tem_insn
== BB_HEAD (bb
))
14728 if (dead_or_set_p (tem_insn
, piece
)
14729 || reg_bitfield_target_p (piece
,
14730 PATTERN (tem_insn
)))
14732 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14745 /* Any other notes should not be present at this point in the
14747 gcc_unreachable ();
14752 XEXP (note
, 1) = REG_NOTES (place
);
14753 REG_NOTES (place
) = note
;
14755 /* Set added_notes_insn to the earliest insn we added a note to. */
14756 if (added_notes_insn
== 0
14757 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place
))
14758 added_notes_insn
= place
;
14763 add_shallow_copy_of_reg_note (place2
, note
);
14765 /* Set added_notes_insn to the earliest insn we added a note to. */
14766 if (added_notes_insn
== 0
14767 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place2
))
14768 added_notes_insn
= place2
;
14773 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14774 I3, I2, and I1 to new locations. This is also called to add a link
14775 pointing at I3 when I3's destination is changed. */
14778 distribute_links (struct insn_link
*links
)
14780 struct insn_link
*link
, *next_link
;
14782 for (link
= links
; link
; link
= next_link
)
14784 rtx_insn
*place
= 0;
14788 next_link
= link
->next
;
14790 /* If the insn that this link points to is a NOTE, ignore it. */
14791 if (NOTE_P (link
->insn
))
14795 rtx pat
= PATTERN (link
->insn
);
14796 if (GET_CODE (pat
) == SET
)
14798 else if (GET_CODE (pat
) == PARALLEL
)
14801 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14803 set
= XVECEXP (pat
, 0, i
);
14804 if (GET_CODE (set
) != SET
)
14807 reg
= SET_DEST (set
);
14808 while (GET_CODE (reg
) == ZERO_EXTRACT
14809 || GET_CODE (reg
) == STRICT_LOW_PART
14810 || GET_CODE (reg
) == SUBREG
)
14811 reg
= XEXP (reg
, 0);
14816 if (REGNO (reg
) == link
->regno
)
14819 if (i
== XVECLEN (pat
, 0))
14825 reg
= SET_DEST (set
);
14827 while (GET_CODE (reg
) == ZERO_EXTRACT
14828 || GET_CODE (reg
) == STRICT_LOW_PART
14829 || GET_CODE (reg
) == SUBREG
)
14830 reg
= XEXP (reg
, 0);
14835 /* A LOG_LINK is defined as being placed on the first insn that uses
14836 a register and points to the insn that sets the register. Start
14837 searching at the next insn after the target of the link and stop
14838 when we reach a set of the register or the end of the basic block.
14840 Note that this correctly handles the link that used to point from
14841 I3 to I2. Also note that not much searching is typically done here
14842 since most links don't point very far away. */
14844 for (insn
= NEXT_INSN (link
->insn
);
14845 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14846 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14847 insn
= NEXT_INSN (insn
))
14848 if (DEBUG_INSN_P (insn
))
14850 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14852 if (reg_referenced_p (reg
, PATTERN (insn
)))
14856 else if (CALL_P (insn
)
14857 && find_reg_fusage (insn
, USE
, reg
))
14862 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14865 /* If we found a place to put the link, place it there unless there
14866 is already a link to the same insn as LINK at that point. */
14870 struct insn_link
*link2
;
14872 FOR_EACH_LOG_LINK (link2
, place
)
14873 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14878 link
->next
= LOG_LINKS (place
);
14879 LOG_LINKS (place
) = link
;
14881 /* Set added_links_insn to the earliest insn we added a
14883 if (added_links_insn
== 0
14884 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14885 added_links_insn
= place
;
14891 /* Check for any register or memory mentioned in EQUIV that is not
14892 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14893 of EXPR where some registers may have been replaced by constants. */
14896 unmentioned_reg_p (rtx equiv
, rtx expr
)
14898 subrtx_iterator::array_type array
;
14899 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14901 const_rtx x
= *iter
;
14902 if ((REG_P (x
) || MEM_P (x
))
14903 && !reg_mentioned_p (x
, expr
))
14909 DEBUG_FUNCTION
void
14910 dump_combine_stats (FILE *file
)
14914 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14915 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14919 dump_combine_total_stats (FILE *file
)
14923 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14924 total_attempts
, total_merges
, total_extras
, total_successes
);
14927 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
14928 the reg-to-reg copy can usefully combine with later instructions, but we
14929 do not want to combine the hard reg into later instructions, for that
14930 restricts register allocation. */
14932 make_more_copies (void)
14936 FOR_EACH_BB_FN (bb
, cfun
)
14940 FOR_BB_INSNS (bb
, insn
)
14942 if (!NONDEBUG_INSN_P (insn
))
14945 rtx set
= single_set (insn
);
14949 rtx dest
= SET_DEST (set
);
14950 if (!(REG_P (dest
) && !HARD_REGISTER_P (dest
)))
14953 rtx src
= SET_SRC (set
);
14954 if (!(REG_P (src
) && HARD_REGISTER_P (src
)))
14956 if (TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
)))
14959 rtx new_reg
= gen_reg_rtx (GET_MODE (dest
));
14960 rtx_insn
*new_insn
= gen_move_insn (new_reg
, src
);
14961 SET_SRC (set
) = new_reg
;
14962 emit_insn_before (new_insn
, insn
);
14963 df_insn_rescan (insn
);
14968 /* Try combining insns through substitution. */
14969 static unsigned int
14970 rest_of_handle_combine (void)
14972 make_more_copies ();
14974 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14975 df_note_add_problem ();
14978 regstat_init_n_sets_and_refs ();
14979 reg_n_sets_max
= max_reg_num ();
14981 int rebuild_jump_labels_after_combine
14982 = combine_instructions (get_insns (), max_reg_num ());
14984 /* Combining insns may have turned an indirect jump into a
14985 direct jump. Rebuild the JUMP_LABEL fields of jumping
14987 if (rebuild_jump_labels_after_combine
)
14989 if (dom_info_available_p (CDI_DOMINATORS
))
14990 free_dominance_info (CDI_DOMINATORS
);
14991 timevar_push (TV_JUMP
);
14992 rebuild_jump_labels (get_insns ());
14994 timevar_pop (TV_JUMP
);
14997 regstat_free_n_sets_and_refs ();
15003 const pass_data pass_data_combine
=
15005 RTL_PASS
, /* type */
15006 "combine", /* name */
15007 OPTGROUP_NONE
, /* optinfo_flags */
15008 TV_COMBINE
, /* tv_id */
15009 PROP_cfglayout
, /* properties_required */
15010 0, /* properties_provided */
15011 0, /* properties_destroyed */
15012 0, /* todo_flags_start */
15013 TODO_df_finish
, /* todo_flags_finish */
15016 class pass_combine
: public rtl_opt_pass
15019 pass_combine (gcc::context
*ctxt
)
15020 : rtl_opt_pass (pass_data_combine
, ctxt
)
15023 /* opt_pass methods: */
15024 bool gate (function
*) final override
{ return (optimize
> 0); }
15025 unsigned int execute (function
*) final override
15027 return rest_of_handle_combine ();
15030 }; // class pass_combine
15032 } // anon namespace
15035 make_pass_combine (gcc::context
*ctxt
)
15037 return new pass_combine (ctxt
);