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Delete some dead code.
[official-gcc.git] / gcc / config / arm / arm.h
blobf8a5d4ff84141c6db2aacdb72a7439443579adef
1 /* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
2 Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
7 This file is part of GNU CC.
8
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22
23 /* Sometimes the directive `riscos' is checked. This does not imply that this
24 tm file can be used unchanged to build a GCC for RISC OS.
25 (Since in fact, it can't.) */
26
27 extern void output_prologue ();
28 extern void output_epilogue ();
29 extern char *arm_output_llc ();
30 extern char *arithmetic_instr ();
31 extern char *output_add_immediate ();
32 extern char *output_call ();
33 extern char *output_call_mem ();
34 extern char *output_move_double ();
35 extern char *output_mov_double_fpu_from_arm ();
36 extern char *output_mov_double_arm_from_fpu ();
37 extern char *output_mov_long_double_fpu_from_arm ();
38 extern char *output_mov_long_double_arm_from_fpu ();
39 extern char *output_mov_long_double_arm_from_arm ();
40 extern char *output_mov_immediate ();
41 extern char *output_multi_immediate ();
42 extern char *output_shifted_move ();
43 extern char *output_shift_compare ();
44 extern char *output_arithmetic_with_immediate_multiply ();
45 extern char *output_arithmetic_with_shift ();
46 extern char *output_return_instruction ();
47 extern char *output_load_symbol ();
48 extern char *fp_immediate_constant ();
49 extern char *shift_instr ();
50 extern struct rtx_def *gen_compare_reg ();
51 extern struct rtx_def *arm_gen_store_multiple ();
52 extern struct rtx_def *arm_gen_load_multiple ();
53
54 extern char *arm_condition_codes[];
55
56 /* This is needed by the tail-calling peepholes */
57 extern int frame_pointer_needed;
58
59 \f
60 #ifndef CPP_PREDEFINES
61 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
62 #endif
63
64 #ifndef CPP_SPEC
65 #define CPP_SPEC "%{m6:-D__arm6__}"
66 #endif
67 \f
68 /* Run-time Target Specification. */
69 #ifndef TARGET_VERSION
70 #define TARGET_VERSION \
71 fputs (" (ARM/generic)", stderr);
72 #endif
73
74 /* Run-time compilation parameters selecting different hardware subsets.
75 On the ARM, misuse it in a different way. */
76 extern int target_flags;
77
78 /* Nonzero if the function prologue (and epilogue) should obey
79 the ARM Procedure Call Standard. */
80 #define TARGET_APCS (target_flags & 1)
81
82 /* Nonzero if the function prologue should output the function name to enable
83 the post mortem debugger to print a backtrace (very useful on RISCOS,
84 unused on RISCiX). Specifying this flag also enables -mapcs.
85 XXX Must still be implemented in the prologue. */
86 #define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
87
88 /* Nonzero if floating point instructions are emulated by the FPE, in which
89 case instruction scheduling becomes very uninteresting. */
90 #define TARGET_FPE (target_flags & 4)
91
92 /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
93 of condition flags when returning from a branch & link (ie. a function) */
94 #define TARGET_6 (target_flags & 8)
95
96 /* ARM_EXTRA_TARGET_SWITCHES is used in riscix.h to define some options which
97 are passed to the preprocessor and the assembler post-processor. They
98 aren't needed in the main pass of the compiler, but if we don't define
99 them in target switches cc1 complains about them. For the sake of
100 argument lets allocate bit 31 of target flags for such options. */
101
102 #ifndef ARM_EXTRA_TARGET_SWITCHES
103 #define ARM_EXTRA_TARGET_SWITCHES
104 #endif
105
106 #define TARGET_SWITCHES \
107 { \
108 {"apcs", 1}, \
109 {"poke-function-name", 2}, \
110 {"fpe", 4}, \
111 {"6", 8}, \
112 {"2", -8}, \
113 {"3", -8}, \
114 ARM_EXTRA_TARGET_SWITCHES \
115 {"", TARGET_DEFAULT } \
116 }
117
118 /* Which processor we are running on. Currently this is only used to
119 get the condition code clobbering attribute right when we are running on
120 an arm 6 */
121
122 enum processor_type
123 {
124 PROCESSOR_ARM2,
125 PROCESSOR_ARM3,
126 PROCESSOR_ARM6
127 };
128
129 /* Recast the cpu class to be the cpu attribute. */
130
131 /* Recast the cpu class to be the cpu attribute. */
132 #define arm_cpu_attr ((enum attr_cpu)arm_cpu)
133
134 extern enum processor_type arm_cpu;
135
136 #define TARGET_DEFAULT 0
137
138 #define TARGET_MEM_FUNCTIONS 1
139
140 /* OVERRIDE_OPTIONS takes care of the following:
141 - if -mpoke-function-name, then -mapcs.
142 - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
143 - if floating point is done by emulation, forget about instruction
144 scheduling. Note that this only saves compilation time; it doesn't
145 matter for the final code. */
146 #ifndef TARGET_WHEN_DEBUGGING
147 #define TARGET_WHEN_DEBUGGING 1
148 #endif
149
150 #define OVERRIDE_OPTIONS \
151 { \
152 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \
153 warning ("-g without a frame pointer may not give sensible debugging");\
154 if (TARGET_POKE_FUNCTION_NAME) \
155 target_flags |= 1; \
156 if (TARGET_FPE) \
157 flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
158 arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \
159 }
160 \f
161 /* Target machine storage Layout. */
162
163
164 /* Define this macro if it is advisable to hold scalars in registers
165 in a wider mode than that declared by the program. In such cases,
166 the value is constrained to be within the bounds of the declared
167 type, but kept valid in the wider mode. The signedness of the
168 extension may differ from that of the type. */
169
170 /* It is far faster to zero extend chars than to sign extend them */
171
172 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
173 if (GET_MODE_CLASS (MODE) == MODE_INT \
174 && GET_MODE_SIZE (MODE) < 4) \
175 { \
176 if (MODE == QImode) \
177 UNSIGNEDP = 1; \
178 (MODE) = SImode; \
179 }
180
181 /* Define for XFmode extended real floating point support.
182 This will automatically cause REAL_ARITHMETIC to be defined. */
183 /* For the ARM:
184 I think I have added all the code to make this work. Unfortunately,
185 early releases of the floating point emulation code on RISCiX used a
186 different format for extended precision numbers. On my RISCiX box there
187 is a bug somewhere which causes the machine to lock up when running enquire
188 with long doubles. There is the additional aspect that Norcroft C
189 treats long doubles as doubles and we ought to remain compatible.
190 Perhaps someone with an FPA coprocessor and not running RISCiX would like
191 to try this someday. */
192 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
193
194 /* Disable XFmode patterns in md file */
195 #define ENABLE_XF_PATTERNS 0
196
197 /* Define if you don't want extended real, but do want to use the
198 software floating point emulator for REAL_ARITHMETIC and
199 decimal <-> binary conversion. */
200 /* See comment above */
201 #define REAL_ARITHMETIC
202
203 /* Define this if most significant bit is lowest numbered
204 in instructions that operate on numbered bit-fields. */
205 #define BITS_BIG_ENDIAN 0
206
207 /* Define this if most significant byte of a word is the lowest numbered. */
208 #define BYTES_BIG_ENDIAN 0
209
210 /* Define this if most significant word of a multiword number is the lowest
211 numbered. */
212 #define WORDS_BIG_ENDIAN 0
213
214 /* Define this if most significant word of doubles is the lowest numbered */
215 #define FLOAT_WORDS_BIG_ENDIAN 1
216
217 /* Number of bits in an addressable storage unit */
218 #define BITS_PER_UNIT 8
219
220 #define BITS_PER_WORD 32
221
222 #define UNITS_PER_WORD 4
223
224 #define POINTER_SIZE 32
225
226 #define PARM_BOUNDARY 32
227
228 #define STACK_BOUNDARY 32
229
230 #define FUNCTION_BOUNDARY 32
231
232 #define EMPTY_FIELD_BOUNDARY 32
233
234 #define BIGGEST_ALIGNMENT 32
235
236 /* Make strings word-aligned so strcpy from constants will be faster. */
237 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
238 (TREE_CODE (EXP) == STRING_CST \
239 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
240
241 /* Every structures size must be a multiple of 32 bits. */
242 #define STRUCTURE_SIZE_BOUNDARY 32
243
244 /* Non-zero if move instructions will actually fail to work
245 when given unaligned data. */
246 #define STRICT_ALIGNMENT 1
247
248 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
249
250 /* Define number of bits in most basic integer type.
251 (If undefined, default is BITS_PER_WORD). */
252 /* #define INT_TYPE_SIZE */
253 \f
254 /* Standard register usage. */
255
256 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
257 (S - saved over call).
258
259 r0 * argument word/integer result
260 r1-r3 argument word
261
262 r4-r8 S register variable
263 r9 S (rfp) register variable (real frame pointer)
264
265 r10 F S (sl) stack limit (not currently used)
266 r11 F S (fp) argument pointer
267 r12 (ip) temp workspace
268 r13 F S (sp) lower end of current stack frame
269 r14 (lr) link address/workspace
270 r15 F (pc) program counter
271
272 f0 floating point result
273 f1-f3 floating point scratch
274
275 f4-f7 S floating point variable
276
277 cc This is NOT a real register, but is used internally
278 to represent things that use or set the condition
279 codes.
280 sfp This isn't either. It is used during rtl generation
281 since the offset between the frame pointer and the
282 auto's isn't known until after register allocation.
283 afp Nor this, we only need this because of non-local
284 goto. Without it fp appears to be used and the
285 elimination code won't get rid of sfp. It tracks
286 fp exactly at all times.
287
288 *: See CONDITIONAL_REGISTER_USAGE */
289
290 /* The stack backtrace structure is as follows:
291 fp points to here: | save code pointer | [fp]
292 | return link value | [fp, #-4]
293 | return sp value | [fp, #-8]
294 | return fp value | [fp, #-12]
295 [| saved r10 value |]
296 [| saved r9 value |]
297 [| saved r8 value |]
298 [| saved r7 value |]
299 [| saved r6 value |]
300 [| saved r5 value |]
301 [| saved r4 value |]
302 [| saved r3 value |]
303 [| saved r2 value |]
304 [| saved r1 value |]
305 [| saved r0 value |]
306 [| saved f7 value |] three words
307 [| saved f6 value |] three words
308 [| saved f5 value |] three words
309 [| saved f4 value |] three words
310 r0-r3 are not normally saved in a C function. */
311
312 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
313 #define FIRST_PSEUDO_REGISTER 27
314
315 /* 1 for registers that have pervasive standard uses
316 and are not available for the register allocator. */
317 #define FIXED_REGISTERS \
318 { \
319 0,0,0,0,0,0,0,0, \
320 0,0,1,1,0,1,0,1, \
321 0,0,0,0,0,0,0,0, \
322 1,1,1 \
323 }
324
325 /* 1 for registers not available across function calls.
326 These must include the FIXED_REGISTERS and also any
327 registers that can be used without being saved.
328 The latter must include the registers where values are returned
329 and the register where structure-value addresses are passed.
330 Aside from that, you can include as many other registers as you like.
331 The CC is not preserved over function calls on the ARM 6, so it is
332 easier to assume this for all. SFP is preserved, since FP is. */
333 #define CALL_USED_REGISTERS \
334 { \
335 1,1,1,1,0,0,0,0, \
336 0,0,1,1,1,1,1,1, \
337 1,1,1,1,0,0,0,0, \
338 1,1,1 \
339 }
340
341 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
342 trampled. This effectively reduces the number of available registers by 1.
343 XXX It is a hack, I know.
344 XXX Is this still needed? */
345 #define CONDITIONAL_REGISTER_USAGE \
346 { \
347 if (obey_regdecls) \
348 fixed_regs[0] = 1; \
349 }
350
351 /* Return number of consecutive hard regs needed starting at reg REGNO
352 to hold something of mode MODE.
353 This is ordinarily the length in words of a value of mode MODE
354 but can be less for certain modes in special long registers.
355
356 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
357 mode. */
358 #define HARD_REGNO_NREGS(REGNO, MODE) \
359 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
360 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
361 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
362
363 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
364 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
365 regs holding FP. */
366 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
367 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
368 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
369 || REGNO == ARG_POINTER_REGNUM \
370 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
371
372 /* Value is 1 if it is a good idea to tie two pseudo registers
373 when one has mode MODE1 and one has mode MODE2.
374 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
375 for any hard reg, then this must be 0 for correct output. */
376 #define MODES_TIEABLE_P(MODE1, MODE2) \
377 (((MODE1) == SFmode || (MODE1) == DFmode) \
378 == ((MODE2) == SFmode || (MODE2) == DFmode))
379
380 /* Specify the registers used for certain standard purposes.
381 The values of these macros are register numbers. */
382
383 /* Define this if the program counter is overloaded on a register. */
384 #define PC_REGNUM 15
385
386 /* Register to use for pushing function arguments. */
387 #define STACK_POINTER_REGNUM 13
388
389 /* Base register for access to local variables of the function. */
390 #define FRAME_POINTER_REGNUM 25
391
392 /* Define this to be where the real frame pointer is if it is not possible to
393 work out the offset between the frame pointer and the automatic variables
394 until after register allocation has taken place. FRAME_POINTER_REGNUM
395 should point to a special register that we will make sure is eliminated. */
396 #define HARD_FRAME_POINTER_REGNUM 11
397
398 /* Value should be nonzero if functions must have frame pointers.
399 Zero means the frame pointer need not be set up (and parms may be accessed
400 via the stack pointer) in functions that seem suitable.
401 If we have to have a frame pointer we might as well make use of it.
402 APCS says that the frame pointer does not need to be pushed in leaf
403 functions. */
404 #define FRAME_POINTER_REQUIRED (TARGET_APCS && !leaf_function_p ())
405
406 /* Base register for access to arguments of the function. */
407 #define ARG_POINTER_REGNUM 26
408
409 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
410 as an invisible last argument (possible since varargs don't exist in
411 Pascal), so the following is not true. */
412 #define STATIC_CHAIN_REGNUM 8
413
414 /* Register in which address to store a structure value
415 is passed to a function. */
416 #define STRUCT_VALUE_REGNUM 0
417
418 /* Internal, so that we don't need to refer to a raw number */
419 #define CC_REGNUM 24
420
421 /* The order in which register should be allocated. It is good to use ip
422 since no saving is required (though calls clobber it) and it never contains
423 function parameters. It is quite good to use lr since other calls may
424 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
425 least likely to contain a function parameter; in addition results are
426 returned in r0.
427 */
428 #define REG_ALLOC_ORDER \
429 { \
430 3, 2, 1, 0, 12, 14, 4, 5, \
431 6, 7, 8, 10, 9, 11, 13, 15, \
432 16, 17, 18, 19, 20, 21, 22, 23, \
433 24, 25 \
434 }
435 \f
436 /* Register and constant classes. */
437
438 /* Register classes: all ARM regs or all FPU regs---simple! */
439 enum reg_class
440 {
441 NO_REGS,
442 FPU_REGS,
443 GENERAL_REGS,
444 ALL_REGS,
445 LIM_REG_CLASSES
446 };
447
448 #define N_REG_CLASSES (int) LIM_REG_CLASSES
449
450 /* Give names of register classes as strings for dump file. */
451 #define REG_CLASS_NAMES \
452 { \
453 "NO_REGS", \
454 "FPU_REGS", \
455 "GENERAL_REGS", \
456 "ALL_REGS", \
457 }
458
459 /* Define which registers fit in which classes.
460 This is an initializer for a vector of HARD_REG_SET
461 of length N_REG_CLASSES. */
462 #define REG_CLASS_CONTENTS \
463 { \
464 0x0000000, /* NO_REGS */ \
465 0x0FF0000, /* FPU_REGS */ \
466 0x200FFFF, /* GENERAL_REGS */ \
467 0x2FFFFFF /* ALL_REGS */ \
468 }
469
470 /* The same information, inverted:
471 Return the class number of the smallest class containing
472 reg number REGNO. This could be a conditional expression
473 or could index an array. */
474 #define REGNO_REG_CLASS(REGNO) \
475 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
476 || REGNO == ARG_POINTER_REGNUM) \
477 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
478 ? NO_REGS : FPU_REGS)
479
480 /* The class value for index registers, and the one for base regs. */
481 #define INDEX_REG_CLASS GENERAL_REGS
482 #define BASE_REG_CLASS GENERAL_REGS
483
484 /* Get reg_class from a letter such as appears in the machine description.
485 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
486 #define REG_CLASS_FROM_LETTER(C) \
487 ((C)=='f' ? FPU_REGS : NO_REGS)
488
489 /* The letters I, J, K, L and M in a register constraint string
490 can be used to stand for particular ranges of immediate operands.
491 This macro defines what the ranges are.
492 C is the letter, and VALUE is a constant value.
493 Return 1 if VALUE is in the range specified by C.
494 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
495 J: valid indexing constants.
496 K: as I but also (not (value)) ok.
497 L: as I but also (neg (value)) ok.*/
498 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
499 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
500 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
501 (C) == 'K' ? (const_ok_for_arm (VALUE) || const_ok_for_arm (~(VALUE))) : \
502 (C) == 'L' ? (const_ok_for_arm (VALUE) || const_ok_for_arm (-(VALUE))) : 0)
503
504 /* For the ARM, `Q' means that this is a memory operand that is just
505 an offset from a register.
506 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
507 address. This means that the symbol is in the text segment and can be
508 accessed without using a load. */
509
510 #define EXTRA_CONSTRAINT(OP, C) \
511 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
512 : (C) == 'R' ? (GET_CODE (OP) == MEM \
513 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
514 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
515 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0)
516
517 /* Constant letter 'G' for the FPU immediate constants.
518 'H' means the same constant negated. */
519 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
520 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
521 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
522
523 /* Given an rtx X being reloaded into a reg required to be
524 in class CLASS, return the class of reg to actually use.
525 In general this is just CLASS; but on some machines
526 in some cases it is preferable to use a more restrictive class. */
527 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
528
529 /* Return the register class of a scratch register needed to copy IN into
530 or out of a register in CLASS in MODE. If it can be done directly,
531 NO_REGS is returned. */
532 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
533 (((MODE) == DFmode && (CLASS) == GENERAL_REGS \
534 && true_regnum (X) == -1) ? GENERAL_REGS \
535 : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS)
536
537 /* Return the maximum number of consecutive registers
538 needed to represent mode MODE in a register of class CLASS.
539 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
540 #define CLASS_MAX_NREGS(CLASS, MODE) \
541 ((CLASS) == FPU_REGS ? 1 \
542 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
543
544 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
545 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
546 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
547 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
548 ? 20 : 2)
549 \f
550 /* Stack layout; function entry, exit and calling. */
551
552 /* Define this if pushing a word on the stack
553 makes the stack pointer a smaller address. */
554 #define STACK_GROWS_DOWNWARD 1
555
556 /* Define this if the nominal address of the stack frame
557 is at the high-address end of the local variables;
558 that is, each additional local variable allocated
559 goes at a more negative offset in the frame. */
560 #define FRAME_GROWS_DOWNWARD 1
561
562 /* Offset within stack frame to start allocating local variables at.
563 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
564 first local allocated. Otherwise, it is the offset to the BEGINNING
565 of the first local allocated. */
566 #define STARTING_FRAME_OFFSET 0
567
568 /* If we generate an insn to push BYTES bytes,
569 this says how many the stack pointer really advances by. */
570 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
571
572 /* Offset of first parameter from the argument pointer register value. */
573 #define FIRST_PARM_OFFSET(FNDECL) 4
574
575 /* Value is the number of byte of arguments automatically
576 popped when returning from a subroutine call.
577 FUNTYPE is the data type of the function (as a tree),
578 or for a library call it is an identifier node for the subroutine name.
579 SIZE is the number of bytes of arguments passed on the stack.
580
581 On the ARM, the caller does not pop any of its arguments that were passed
582 on the stack. */
583 #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
584
585 /* Define how to find the value returned by a function.
586 VALTYPE is the data type of the value (as a tree).
587 If the precise function being called is known, FUNC is its FUNCTION_DECL;
588 otherwise, FUNC is 0. */
589 #define FUNCTION_VALUE(VALTYPE, FUNC) \
590 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
591 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
592 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
593
594 /* Define how to find the value returned by a library function
595 assuming the value has mode MODE. */
596 #define LIBCALL_VALUE(MODE) \
597 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
598 ? gen_rtx (REG, MODE, 16) \
599 : gen_rtx (REG, MODE, 0))
600
601 /* 1 if N is a possible register number for a function value.
602 On the ARM, only r0 and f0 can return results. */
603 #define FUNCTION_VALUE_REGNO_P(REGNO) \
604 ((REGNO) == 0 || (REGNO) == 16)
605
606 /* Define where to put the arguments to a function.
607 Value is zero to push the argument on the stack,
608 or a hard register in which to store the argument.
609
610 MODE is the argument's machine mode.
611 TYPE is the data type of the argument (as a tree).
612 This is null for libcalls where that information may
613 not be available.
614 CUM is a variable of type CUMULATIVE_ARGS which gives info about
615 the preceding args and about the function being called.
616 NAMED is nonzero if this argument is a named parameter
617 (otherwise it is an extra parameter matching an ellipsis).
618
619 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
620 other arguments are passed on the stack. If (NAMED == 0) (which happens
621 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
622 passed in the stack (function_prologue will indeed make it pass in the
623 stack if necessary). */
624 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
625 ((NAMED) \
626 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
627 : 0)
628
629 /* For an arg passed partly in registers and partly in memory,
630 this is the number of registers used.
631 For args passed entirely in registers or entirely in memory, zero. */
632 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
633 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
634 ? GET_MODE_SIZE (MODE) \
635 : int_size_in_bytes (TYPE)) \
636 ? 4 - (CUM) / 4 : 0)
637
638 /* A C type for declaring a variable that is used as the first argument of
639 `FUNCTION_ARG' and other related values. For some target machines, the
640 type `int' suffices and can hold the number of bytes of argument so far.
641
642 On the ARM, this is the number of bytes of arguments scanned so far. */
643 #define CUMULATIVE_ARGS int
644
645 /* Initialize a variable CUM of type CUMULATIVE_ARGS
646 for a call to a function whose data type is FNTYPE.
647 For a library call, FNTYPE is 0.
648 On the ARM, the offset starts at 0. */
649 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
650 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
651
652 /* Update the data in CUM to advance over an argument
653 of mode MODE and data type TYPE.
654 (TYPE is null for libcalls where that information may not be available.) */
655 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
656 (CUM) += ((MODE) != BLKmode \
657 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
658 : (int_size_in_bytes (TYPE) + 3) & ~3) \
659
660 /* 1 if N is a possible register number for function argument passing.
661 On the ARM, r0-r3 are used to pass args. */
662 #define FUNCTION_ARG_REGNO_P(REGNO) \
663 ((REGNO) >= 0 && (REGNO) <= 3)
664
665 /* Perform any actions needed for a function that is receiving a variable
666 number of arguments. CUM is as above. MODE and TYPE are the mode and type
667 of the current parameter. PRETEND_SIZE is a variable that should be set to
668 the amount of stack that must be pushed by the prolog to pretend that our
669 caller pushed it.
670
671 Normally, this macro will push all remaining incoming registers on the
672 stack and set PRETEND_SIZE to the length of the registers pushed.
673
674 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
675 named arg and all anonymous args onto the stack.
676 XXX I know the prologue shouldn't be pushing registers, but it is faster
677 that way. */
678 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
679 { \
680 extern int current_function_anonymous_args; \
681 current_function_anonymous_args = 1; \
682 if ((CUM) < 16) \
683 (PRETEND_SIZE) = 16 - (CUM); \
684 }
685
686 /* Generate assembly output for the start of a function. */
687 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
688 output_func_prologue ((STREAM), (SIZE))
689
690 /* Call the function profiler with a given profile label. The Acorn compiler
691 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
692 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
693 to mind about this! */
694 #define FUNCTION_PROFILER(STREAM,LABELNO) \
695 { \
696 fprintf(STREAM, "\tmov\tip, lr\n"); \
697 fprintf(STREAM, "\tbl\tmcount\n"); \
698 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
699 arm_increase_location (12); \
700 }
701
702 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
703 the stack pointer does not matter. The value is tested only in
704 functions that have frame pointers.
705 No definition is equivalent to always zero.
706
707 On the ARM, the function epilogue recovers the stack pointer from the
708 frame. */
709 #define EXIT_IGNORE_STACK 1
710
711 /* Generate the assembly code for function exit. */
712 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
713 output_func_epilogue ((STREAM), (SIZE))
714
715 /* Determine if the epilogue should be output as RTL.
716 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
717 #define USE_RETURN_INSN use_return_insn ()
718
719 /* Definitions for register eliminations.
720
721 This is an array of structures. Each structure initializes one pair
722 of eliminable registers. The "from" register number is given first,
723 followed by "to". Eliminations of the same "from" register are listed
724 in order of preference.
725
726 We have two registers that can be eliminated on the ARM. First, the
727 arg pointer register can often be eliminated in favor of the stack
728 pointer register. Secondly, the pseudo frame pointer register can always
729 be eliminated; it is replaced with either the stack or the real frame
730 pointer. */
731
732 #define ELIMINABLE_REGS \
733 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
734 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
735 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
736 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
737
738 /* Given FROM and TO register numbers, say whether this elimination is allowed.
739 Frame pointer elimination is automatically handled.
740
741 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
742 HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame
743 pointer, we must eliminate FRAME_POINTER_REGNUM into
744 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
745 #define CAN_ELIMINATE(FROM, TO) \
746 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
747
748 /* Define the offset between two registers, one to be eliminated, and the other
749 its replacement, at the start of a routine. */
750 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
751 { \
752 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
753 (OFFSET) = 0; \
754 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
755 (OFFSET) = (get_frame_size () + 3 & ~3); \
756 else \
757 { \
758 int regno; \
759 int offset = 12; \
760 int saved_hard_reg = 0; \
761 \
762 for (regno = 0; regno <= 10; regno++) \
763 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
764 saved_hard_reg = 1, offset += 4; \
765 for (regno = 16; regno <=23; regno++) \
766 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
767 offset += 12; \
768 if ((FROM) == FRAME_POINTER_REGNUM) \
769 (OFFSET) = -offset; \
770 else \
771 { \
772 if (! regs_ever_live[HARD_FRAME_POINTER_REGNUM]) \
773 offset -= 16; \
774 if (regs_ever_live[14] || saved_hard_reg) \
775 offset += 4; \
776 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
777 } \
778 } \
779 }
780
781 /* Output assembler code for a block containing the constant parts
782 of a trampoline, leaving space for the variable parts.
783
784 On the ARM, (if r8 is the static chain regnum, and remembering that
785 referencing pc adds an offset of 8) the trampoline looks like:
786 ldr r8, [pc, #0]
787 ldr pc, [pc]
788 .word static chain value
789 .word function's address */
790 #define TRAMPOLINE_TEMPLATE(FILE) \
791 { \
792 fprintf ((FILE), "\tldr\tr8, [pc, #0]\n"); \
793 fprintf ((FILE), "\tldr\tpc, [pc, #0]\n"); \
794 fprintf ((FILE), "\t.word\t0\n"); \
795 fprintf ((FILE), "\t.word\t0\n"); \
796 }
797
798 /* Length in units of the trampoline for entering a nested function. */
799 #define TRAMPOLINE_SIZE 16
800
801 /* Alignment required for a trampoline in units. */
802 #define TRAMPOLINE_ALIGN 4
803
804 /* Emit RTL insns to initialize the variable parts of a trampoline.
805 FNADDR is an RTX for the address of the function's pure code.
806 CXT is an RTX for the static chain value for the function. */
807 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
808 { \
809 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
810 (CXT)); \
811 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
812 (FNADDR)); \
813 }
814
815 /* Call the function profiler with a given profile label. The Acorn compiler
816 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
817 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
818 to mind about this! */
819 #define FUNCTION_PROFILER(STREAM,LABELNO) \
820 { \
821 fprintf(STREAM, "\tmov\tip, lr\n"); \
822 fprintf(STREAM, "\tbl\tmcount\n"); \
823 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
824 arm_increase_location (12); \
825 }
826 \f
827 /* Addressing modes, and classification of registers for them. */
828
829 #define HAVE_POST_INCREMENT 1
830 #define HAVE_PRE_INCREMENT 1
831 #define HAVE_POST_DECREMENT 1
832 #define HAVE_PRE_DECREMENT 1
833
834 /* Macros to check register numbers against specific register classes. */
835
836 /* These assume that REGNO is a hard or pseudo reg number.
837 They give nonzero only if REGNO is a hard reg of the suitable class
838 or a pseudo reg currently allocated to a suitable hard reg.
839 Since they use reg_renumber, they are safe only once reg_renumber
840 has been allocated, which happens in local-alloc.c.
841
842 On the ARM, don't allow the pc to be used. */
843 #define REGNO_OK_FOR_BASE_P(REGNO) \
844 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
845 || (REGNO) == ARG_POINTER_REGNUM \
846 || (unsigned) reg_renumber[(REGNO)] < 15 \
847 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
848 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
849 #define REGNO_OK_FOR_INDEX_P(REGNO) \
850 REGNO_OK_FOR_BASE_P(REGNO)
851
852 /* Maximum number of registers that can appear in a valid memory address.
853 Shifts in addresses can't be by a register. */
854
855 #define MAX_REGS_PER_ADDRESS 2
856
857 /* Recognize any constant value that is a valid address. */
858 /* XXX We can address any constant, eventually... */
859 #if 0
860 #define CONSTANT_ADDRESS_P(X) \
861 ( GET_CODE(X) == LABEL_REF \
862 || GET_CODE(X) == SYMBOL_REF \
863 || GET_CODE(X) == CONST_INT \
864 || GET_CODE(X) == CONST )
865 #endif
866
867 #define CONSTANT_ADDRESS_P(X) \
868 (GET_CODE (X) == SYMBOL_REF \
869 && (CONSTANT_POOL_ADDRESS_P (X) \
870 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
871
872 /* Nonzero if the constant value X is a legitimate general operand.
873 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
874
875 On the ARM, allow any integer (invalid ones are removed later by insn
876 patterns), nice doubles and symbol_refs which refer to the function's
877 constant pool XXX. */
878 #define LEGITIMATE_CONSTANT_P(X) \
879 (GET_CODE (X) == CONST_INT \
880 || (GET_CODE (X) == CONST_DOUBLE \
881 && (const_double_rtx_ok_for_fpu (X) \
882 || neg_const_double_rtx_ok_for_fpu (X))) \
883 || CONSTANT_ADDRESS_P (X))
884
885 /* Symbols in the text segment can be accessed without indirecting via the
886 constant pool; it may take an extra binary operation, but this is still
887 faster than indirecting via memory. Don't do this when not optimizing,
888 since we won't be calculating al of the offsets necessary to do this
889 simplification. */
890
891 #define ENCODE_SECTION_INFO(decl) \
892 { \
893 if (optimize > 0 && TREE_CONSTANT (decl) \
894 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
895 { \
896 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
897 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
898 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
899 } \
900 }
901
902 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
903 and check its validity for a certain class.
904 We have two alternate definitions for each of them.
905 The usual definition accepts all pseudo regs; the other rejects
906 them unless they have been allocated suitable hard regs.
907 The symbol REG_OK_STRICT causes the latter definition to be used. */
908 #ifndef REG_OK_STRICT
909
910 /* Nonzero if X is a hard reg that can be used as a base reg
911 or if it is a pseudo reg. */
912 #define REG_OK_FOR_BASE_P(X) \
913 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
914 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
915
916 /* Nonzero if X is a hard reg that can be used as an index
917 or if it is a pseudo reg. */
918 #define REG_OK_FOR_INDEX_P(X) \
919 REG_OK_FOR_BASE_P(X)
920
921 #define REG_OK_FOR_PRE_POST_P(X) \
922 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
923 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
924
925 #else
926
927 /* Nonzero if X is a hard reg that can be used as a base reg. */
928 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
929
930 /* Nonzero if X is a hard reg that can be used as an index. */
931 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
932
933 #define REG_OK_FOR_PRE_POST_P(X) \
934 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
935 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
936 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
937 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
938
939 #endif
940 \f
941 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
942 that is a valid memory address for an instruction.
943 The MODE argument is the machine mode for the MEM expression
944 that wants to use this address.
945
946 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
947 #define BASE_REGISTER_RTX_P(X) \
948 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
949
950 #define INDEX_REGISTER_RTX_P(X) \
951 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
952
953 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
954 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
955 only be small constants. */
956 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
957 do \
958 { \
959 HOST_WIDE_INT range; \
960 enum rtx_code code = GET_CODE (INDEX); \
961 \
962 if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
963 { \
964 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
965 && INTVAL (INDEX) > -1024 \
966 && (INTVAL (INDEX) & 3) == 0) \
967 goto LABEL; \
968 } \
969 else \
970 { \
971 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
972 goto LABEL; \
973 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \
974 { \
975 rtx xiop0 = XEXP (INDEX, 0); \
976 rtx xiop1 = XEXP (INDEX, 1); \
977 if (INDEX_REGISTER_RTX_P (xiop0) \
978 && power_of_two_operand (xiop1, SImode)) \
979 goto LABEL; \
980 if (INDEX_REGISTER_RTX_P (xiop1) \
981 && power_of_two_operand (xiop0, SImode)) \
982 goto LABEL; \
983 } \
984 if (GET_MODE_SIZE (MODE) <= 4 \
985 && (code == LSHIFTRT || code == ASHIFTRT \
986 || code == ASHIFT || code == ROTATERT)) \
987 { \
988 rtx op = XEXP (INDEX, 1); \
989 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
990 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
991 && INTVAL (op) <= 31) \
992 goto LABEL; \
993 } \
994 range = (MODE) == HImode ? 4095 : 4096; \
995 if (code == CONST_INT && INTVAL (INDEX) < range \
996 && INTVAL (INDEX) > -range) \
997 goto LABEL; \
998 } \
999 } while (0)
1000
1001 /* Jump to LABEL if X is a valid address RTX. This must also take
1002 REG_OK_STRICT into account when deciding about valid registers, but it uses
1003 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1004 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1005 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1006 refs must be forced though a static cell to ensure addressability. */
1007 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1008 { \
1009 if (BASE_REGISTER_RTX_P (X)) \
1010 goto LABEL; \
1011 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1012 && GET_CODE (XEXP (X, 0)) == REG \
1013 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1014 goto LABEL; \
1015 else if ((MODE) == TImode) \
1016 ; \
1017 else if (GET_CODE (X) == PLUS) \
1018 { \
1019 rtx xop0 = XEXP(X,0); \
1020 rtx xop1 = XEXP(X,1); \
1021 \
1022 if (BASE_REGISTER_RTX_P (xop0)) \
1023 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1024 else if (BASE_REGISTER_RTX_P (xop1)) \
1025 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1026 } \
1027 else if (GET_CODE (X) == MINUS) \
1028 { \
1029 rtx xop0 = XEXP (X,0); \
1030 rtx xop1 = XEXP (X,1); \
1031 \
1032 if (BASE_REGISTER_RTX_P (xop0)) \
1033 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1034 } \
1035 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1036 && GET_CODE (X) == SYMBOL_REF \
1037 && CONSTANT_POOL_ADDRESS_P (X)) \
1038 goto LABEL; \
1039 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1040 && GET_CODE (XEXP (X, 0)) == REG \
1041 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1042 goto LABEL; \
1043 }
1044 \f
1045 /* Try machine-dependent ways of modifying an illegitimate address
1046 to be legitimate. If we find one, return the new, valid address.
1047 This macro is used in only one place: `memory_address' in explow.c.
1048
1049 OLDX is the address as it was before break_out_memory_refs was called.
1050 In some cases it is useful to look at this to decide what needs to be done.
1051
1052 MODE and WIN are passed so that this macro can use
1053 GO_IF_LEGITIMATE_ADDRESS.
1054
1055 It is always safe for this macro to do nothing. It exists to recognize
1056 opportunities to optimize the output.
1057
1058 On the ARM, try to convert [REG, #BIGCONST]
1059 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1060 where VALIDCONST == 0 in case of TImode. */
1061 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1062 { \
1063 if (GET_CODE (X) == PLUS) \
1064 { \
1065 rtx xop0 = XEXP (X, 0); \
1066 rtx xop1 = XEXP (X, 1); \
1067 \
1068 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1069 { \
1070 int n = INTVAL (xop1); \
1071 int low_n = ((MODE) == TImode ? 0 \
1072 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1073 rtx base_reg = gen_reg_rtx (SImode); \
1074 rtx val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1075 gen_rtx (CONST_INT, \
1076 VOIDmode, n - low_n)), \
1077 0); \
1078 emit_move_insn (base_reg, val); \
1079 (X) = (low_n == 0 ? base_reg \
1080 : gen_rtx (PLUS, SImode, base_reg, \
1081 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1082 } \
1083 else if (BASE_REGISTER_RTX_P (xop1) && GET_CODE (xop0) == CONST_INT) \
1084 { \
1085 int n = INTVAL (xop0); \
1086 int low_n = ((MODE) == TImode ? 0 \
1087 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1088 rtx base_reg = gen_reg_rtx (SImode); \
1089 rtx val = force_operand (gen_rtx (PLUS, SImode, xop1, \
1090 gen_rtx (CONST_INT, \
1091 VOIDmode, n - low_n)), \
1092 0); \
1093 emit_move_insn (base_reg, val); \
1094 (X) = (low_n == 0 ? base_reg \
1095 : gen_rtx (PLUS, SImode, base_reg, \
1096 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1097 } \
1098 } \
1099 if (memory_address_p (MODE, X)) \
1100 goto win; \
1101 }
1102
1103 /* Go to LABEL if ADDR (a legitimate address expression)
1104 has an effect that depends on the machine mode it is used for. */
1105 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1106 { \
1107 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1108 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1109 goto LABEL; \
1110 }
1111 \f
1112 /* Specify the machine mode that this machine uses
1113 for the index in the tablejump instruction. */
1114 #define CASE_VECTOR_MODE SImode
1115
1116 /* Define this if the tablejump instruction expects the table
1117 to contain offsets from the address of the table.
1118 Do not define this if the table should contain absolute addresses. */
1119 /* #define CASE_VECTOR_PC_RELATIVE */
1120
1121 /* Specify the tree operation to be used to convert reals to integers. */
1122 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1123
1124 /* This is the kind of divide that is easiest to do in the general case. */
1125 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1126
1127 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1128 unsigned is probably best, but may break some code. */
1129 #ifndef DEFAULT_SIGNED_CHAR
1130 #define DEFAULT_SIGNED_CHAR 1
1131 #endif
1132
1133 /* Don't cse the address of the function being compiled. */
1134 #define NO_RECURSIVE_FUNCTION_CSE 1
1135
1136 /* Max number of bytes we can move from memory to memory
1137 in one reasonably fast instruction. */
1138 #define MOVE_MAX 4
1139
1140 /* Define if operations between registers always perform the operation
1141 on the full register even if a narrower mode is specified. */
1142 #define WORD_REGISTER_OPERATIONS
1143
1144 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1145 will either zero-extend or sign-extend. The value of this macro should
1146 be the code that says which one of the two operations is implicitly
1147 done, NIL if none. */
1148 #define LOAD_EXTEND_OP(MODE) \
1149 ((MODE) == QImode ? ZERO_EXTEND : NIL)
1150
1151 /* Define this if zero-extension is slow (more than one real instruction).
1152 On the ARM, it is more than one instruction only if not fetching from
1153 memory. */
1154 /* #define SLOW_ZERO_EXTEND */
1155
1156 /* Nonzero if access to memory by bytes is slow and undesirable. */
1157 #define SLOW_BYTE_ACCESS 0
1158
1159 /* Immediate shift counts are truncated by the output routines (or was it
1160 the assembler?). Shift counts in a register are truncated by ARM. Note
1161 that the native compiler puts too large (> 32) immediate shift counts
1162 into a register and shifts by the register, letting the ARM decide what
1163 to do instead of doing that itself. */
1164 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1165 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1166 On the arm, Y in a register is used modulo 256 for the shift. Only for
1167 rotates is modulo 32 used. */
1168 /* #define SHIFT_COUNT_TRUNCATED 1 */
1169
1170 /* XX This is not true, is it? */
1171 /* All integers have the same format so truncation is easy. */
1172 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1173
1174 /* Calling from registers is a massive pain. */
1175 #define NO_FUNCTION_CSE 1
1176
1177 /* Chars and shorts should be passed as ints. */
1178 #define PROMOTE_PROTOTYPES 1
1179
1180 /* The machine modes of pointers and functions */
1181 #define Pmode SImode
1182 #define FUNCTION_MODE Pmode
1183
1184 /* The structure type of the machine dependent info field of insns
1185 No uses for this yet. */
1186 /* #define INSN_MACHINE_INFO struct machine_info */
1187
1188 /* The relative costs of various types of constants. Note that cse.c defines
1189 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1190 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1191 case CONST_INT: \
1192 if (const_ok_for_arm (INTVAL (RTX))) \
1193 return (OUTER_CODE) == SET ? 2 : -1; \
1194 else if (OUTER_CODE == AND \
1195 && const_ok_for_arm (~INTVAL (RTX))) \
1196 return -1; \
1197 else if ((OUTER_CODE == COMPARE \
1198 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1199 && const_ok_for_arm (-INTVAL (RTX))) \
1200 return -1; \
1201 else \
1202 return 5; \
1203 case CONST: \
1204 case LABEL_REF: \
1205 case SYMBOL_REF: \
1206 return 6; \
1207 case CONST_DOUBLE: \
1208 if (const_double_rtx_ok_for_fpu (RTX)) \
1209 return (OUTER_CODE) == SET ? 2 : -1; \
1210 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1211 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1212 return -1; \
1213 return(7);
1214
1215 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1216 case MEM: \
1217 { \
1218 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1;\
1219 return (COSTS_N_INSNS (10*num_words)); \
1220 } \
1221 case MULT: \
1222 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1223 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
1224 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1225 return COSTS_N_INSNS (9); \
1226 case ASHIFT: \
1227 case LSHIFTRT: \
1228 case ASHIFTRT: \
1229 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1230 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1231 break; \
1232 case MINUS: \
1233 { \
1234 enum rtx_code code = GET_CODE (XEXP (X, 1)); \
1235 if (code == MULT) \
1236 { \
1237 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT \
1238 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1239 return COSTS_N_INSNS (1); \
1240 break; \
1241 } \
1242 else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
1243 return COSTS_N_INSNS (1); \
1244 } /* fall through */ \
1245 case PLUS: \
1246 case IOR: \
1247 case XOR: \
1248 case AND: \
1249 { \
1250 enum rtx_code code = GET_CODE (XEXP (X, 0)); \
1251 if (code == MULT) \
1252 { \
1253 if (GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1254 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1255 return COSTS_N_INSNS (1); \
1256 if (GET_CODE (X) == PLUS) \
1257 return COSTS_N_INSNS (12); \
1258 break; \
1259 } \
1260 else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
1261 return COSTS_N_INSNS (1); \
1262 break; \
1263 } \
1264 case NOT: \
1265 return rtx_cost (XEXP (X, 0), GET_CODE (XEXP (X, 0))); \
1266 case IF_THEN_ELSE: \
1267 { \
1268 if (GET_CODE (XEXP(X,1)) == PC || GET_CODE (XEXP(X,2)) == PC) \
1269 return COSTS_N_INSNS (4); \
1270 return COSTS_N_INSNS (1); \
1271 } \
1272 case SIGN_EXTEND: \
1273 return COSTS_N_INSNS (2); \
1274 case ZERO_EXTEND: \
1275 if (GET_MODE (XEXP (X, 0)) == QImode) \
1276 { \
1277 if (GET_CODE (XEXP (X, 0)) == MEM) \
1278 return COSTS_N_INSNS (10); \
1279 return COSTS_N_INSNS (1); \
1280 } \
1281 break; \
1282 case COMPARE: \
1283 if (GET_CODE (XEXP (X, 1)) == REG) \
1284 return 4; \
1285 case SMIN: \
1286 case SMAX: \
1287 case UMIN: \
1288 case UMAX: \
1289 return COSTS_N_INSNS (3); \
1290 case ABS: \
1291 if (GET_MODE (X) == SImode) \
1292 return COSTS_N_INSNS (2); \
1293 return COSTS_N_INSNS (1);
1294
1295 /* Moves to and from memory are quite expensive */
1296 #define MEMORY_MOVE_COST(MODE) 10
1297
1298 /* All address computations that can be done are free */
1299 #define ADDRESS_COST(x) 2
1300
1301 /* Try to generate sequences that don't involve branches, we can then use
1302 conditional instructions */
1303 #define BRANCH_COST 4
1304 \f
1305 /* Condition code information. */
1306 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1307 return the mode to be used for the comparison.
1308 CCFPEmode should be used with floating inequalites,
1309 CCFPmode should be used with floating equalities.
1310 CC_NOOVmode should be used with SImode integer equalites
1311 CCmode should be used otherwise. */
1312
1313 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1314
1315 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1316
1317 #define SELECT_CC_MODE(OP,X,Y) \
1318 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1319 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1320 : ((GET_MODE (X) == SImode) \
1321 && ((OP) == EQ || (OP) == NE) \
1322 && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1323 || GET_CODE (X) == AND || GET_CODE (X) == IOR \
1324 || GET_CODE (X) == XOR || GET_CODE (X) == MULT \
1325 || GET_CODE (X) == NOT || GET_CODE (X) == NEG \
1326 || GET_CODE (X) == LSHIFTRT \
1327 || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
1328 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
1329 ? CC_NOOVmode \
1330 : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode))
1331
1332 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1333
1334 #define STORE_FLAG_VALUE 1
1335
1336 /* Define the information needed to generate branch insns. This is
1337 stored from the compare operation. Note that we can't use "rtx" here
1338 since it hasn't been defined! */
1339
1340 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1341 extern int arm_compare_fp;
1342
1343 /* Define the codes that are matched by predicates in arm.c */
1344 #define PREDICATE_CODES \
1345 {"s_register_operand", {SUBREG, REG}}, \
1346 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1347 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1348 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1349 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1350 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1351 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1352 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1353 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, MULT}}, \
1354 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1355 {"load_multiple_operation", {PARALLEL}}, \
1356 {"store_multiple_operation", {PARALLEL}}, \
1357 {"equality_operator", {EQ, NE}}, \
1358 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1359 {"const_shift_operand", {CONST_INT}}, \
1360 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1361 {"cc_register", {REG}},
1362
1363 \f
1364 /* Assembler output control */
1365
1366 #ifndef ARM_OS_NAME
1367 #define ARM_OS_NAME "(generic)"
1368 #endif
1369
1370 /* The text to go at the start of the assembler file */
1371 #define ASM_FILE_START(STREAM) \
1372 { \
1373 extern char *version_string; \
1374 \
1375 fprintf (STREAM,"@ Generated by gcc %s for ARM/%s\n", version_string, \
1376 ARM_OS_NAME); \
1377 fprintf (STREAM,"rfp\t.req\tr9\n"); \
1378 fprintf (STREAM,"fp\t.req\tr11\n"); \
1379 fprintf (STREAM,"ip\t.req\tr12\n"); \
1380 fprintf (STREAM,"sp\t.req\tr13\n"); \
1381 fprintf (STREAM,"lr\t.req\tr14\n"); \
1382 fprintf (STREAM,"pc\t.req\tr15\n"); \
1383 }
1384
1385 #define ASM_APP_ON ""
1386 #define ASM_APP_OFF ""
1387
1388 /* Switch to the text or data segment. */
1389 #define TEXT_SECTION_ASM_OP ".text"
1390 #define DATA_SECTION_ASM_OP ".data"
1391
1392 /* The assembler's names for the registers. RFP need not always be used as
1393 the Real framepointer; it can also be used as a normal general register.
1394 Note that the name `fp' is horribly misleading since `fp' is in fact only
1395 the argument-and-return-context pointer. */
1396 #define REGISTER_NAMES \
1397 { \
1398 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1399 "r8","rfp", "sl", "fp", "ip", "sp", "lr", "pc", \
1400 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1401 "cc", "sfp", "afp" \
1402 }
1403
1404 /* Arm Assembler barfs on dollars */
1405 #define DOLLARS_IN_IDENTIFIERS 0
1406
1407 #define NO_DOLLAR_IN_LABEL
1408
1409 /* DBX register number for a given compiler register number */
1410 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1411
1412 /* Generate DBX debugging information. riscix.h will undefine this because
1413 the native assembler does not support stabs. */
1414 #define DBX_DEBUGGING_INFO 1
1415
1416 /* Acorn dbx moans about continuation chars, so don't use any. */
1417 #define DBX_CONTIN_LENGTH 0
1418
1419 /* Output a source filename for the debugger. RISCiX dbx insists that the
1420 ``desc'' field is set to compiler version number >= 315 (sic). */
1421 #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \
1422 do { \
1423 fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \
1424 &ltext_label_name[1]); \
1425 text_section (); \
1426 ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \
1427 } while (0)
1428
1429 /* Output a label definition. */
1430 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
1431 arm_asm_output_label ((STREAM), (NAME))
1432
1433 /* Output a function label definition. */
1434 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1435 ASM_OUTPUT_LABEL(STREAM, NAME)
1436
1437 /* Output a globalising directive for a label. */
1438 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1439 (fprintf (STREAM, "\t.global\t"), \
1440 assemble_name (STREAM, NAME), \
1441 fputc ('\n',STREAM)) \
1442
1443 /* Output a reference to a label. */
1444 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1445 fprintf (STREAM, "_%s", NAME)
1446
1447 /* Make an internal label into a string. */
1448 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1449 sprintf (STRING, "*%s%d", PREFIX, NUM)
1450
1451 /* Output an internal label definition. */
1452 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1453 do \
1454 { \
1455 char *s = (char *) alloca (11 + strlen (PREFIX)); \
1456 extern int arm_target_label, arm_ccfsm_state; \
1457 extern rtx arm_target_insn; \
1458 \
1459 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1460 && !strcmp (PREFIX, "L")) \
1461 { \
1462 arm_ccfsm_state = 0; \
1463 arm_target_insn = NULL; \
1464 } \
1465 strcpy (s, "*"); \
1466 sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \
1467 arm_asm_output_label (STREAM, s); \
1468 } while (0)
1469
1470 /* Nothing special is done about jump tables */
1471 /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1472 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1473
1474 /* Construct a private name. */
1475 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1476 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1477 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1478
1479 /* Output a push or a pop instruction (only used when profiling). */
1480 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1481 fprintf(STREAM,"\tstmfd\tsp!,{%s}\n", reg_names[REGNO])
1482
1483 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1484 fprintf(STREAM,"\tldmfd\tsp!,{%s}\n", reg_names[REGNO])
1485
1486 /* Output a relative address. Not needed since jump tables are absolute
1487 but we must define it anyway. */
1488 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1489 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1490
1491 /* Output an element of a dispatch table. */
1492 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1493 fprintf (STREAM, "\t.word\tL%d\n", VALUE)
1494
1495 /* Output various types of constants. For real numbers we output hex, with
1496 a comment containing the "human" value, this allows us to pass NaN's which
1497 the riscix assembler doesn't understand (it also makes cross-assembling
1498 less likely to fail). */
1499
1500 #define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
1501 do { char dstr[30]; \
1502 long l[3]; \
1503 arm_increase_location (12); \
1504 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1505 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1506 if (sizeof (int) == sizeof (long)) \
1507 fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t@ long double %s\n", \
1508 l[2], l[1], l[0], dstr); \
1509 else \
1510 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t@ long double %s\n",\
1511 l[0], l[1], l[2], dstr); \
1512 } while (0)
1513
1514
1515 #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1516 do { char dstr[30]; \
1517 long l[2]; \
1518 arm_increase_location (8); \
1519 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1520 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \
1521 if (sizeof (int) == sizeof (long)) \
1522 fprintf (STREAM, "\t.long 0x%x, 0x%x\t@ double %s\n", l[0], l[1],\
1523 dstr); \
1524 else \
1525 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t@ double %s\n", l[0], \
1526 l[1], dstr); \
1527 } while (0)
1528
1529 #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1530 do { char dstr[30]; \
1531 long l; \
1532 arm_increase_location (4); \
1533 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1534 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \
1535 if (sizeof (int) == sizeof (long)) \
1536 fprintf (STREAM, "\t.word 0x%x\t@ float %s\n", l, dstr); \
1537 else \
1538 fprintf (STREAM, "\t.word 0x%lx\t@ float %s\n", l, dstr); \
1539 } while (0);
1540
1541 #define ASM_OUTPUT_INT(STREAM, EXP) \
1542 (fprintf (STREAM, "\t.word\t"), \
1543 output_addr_const (STREAM, (EXP)), \
1544 arm_increase_location (4), \
1545 fputc ('\n', STREAM))
1546
1547 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1548 (fprintf (STREAM, "\t.short\t"), \
1549 output_addr_const (STREAM, (EXP)), \
1550 arm_increase_location (2), \
1551 fputc ('\n', STREAM))
1552
1553 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1554 (fprintf (STREAM, "\t.byte\t"), \
1555 output_addr_const (STREAM, (EXP)), \
1556 arm_increase_location (1), \
1557 fputc ('\n', STREAM))
1558
1559 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1560 (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \
1561 arm_increase_location (1))
1562
1563 #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
1564 output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN))
1565
1566 /* Output a gap. In fact we fill it with nulls. */
1567 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1568 (arm_increase_location (NBYTES), \
1569 fprintf (STREAM, "\t.space\t%d\n", NBYTES))
1570
1571 /* Align output to a power of two. Horrible /bin/as. */
1572 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1573 do \
1574 { \
1575 register int amount = 1 << (POWER); \
1576 extern int arm_text_location; \
1577 \
1578 if (amount == 2) \
1579 fprintf (STREAM, "\t.even\n"); \
1580 else \
1581 fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
1582 \
1583 if (in_text_section ()) \
1584 arm_text_location = ((arm_text_location + amount - 1) \
1585 & ~(amount - 1)); \
1586 } while (0)
1587
1588 /* Output a common block */
1589 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1590 (fprintf (STREAM, "\t.comm\t"), \
1591 assemble_name ((STREAM), (NAME)), \
1592 fprintf(STREAM, ", %d\t@%d\n", ROUNDED, SIZE))
1593
1594 /* Output a local common block. /bin/as can't do this, so hack a `.space' into
1595 the bss segment. Note that this is *bad* practice. */
1596 #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1597 output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1598
1599 /* Output a source line for the debugger. */
1600 /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1601
1602 /* Output a #ident directive. */
1603 #define ASM_OUTPUT_IDENT(STREAM,STRING) \
1604 fprintf (STREAM,"- - - ident %s\n",STRING)
1605
1606 /* The assembler's parentheses characters. */
1607 #define ASM_OPEN_PAREN "("
1608 #define ASM_CLOSE_PAREN ")"
1609
1610 /* Target characters. */
1611 #define TARGET_BELL 007
1612 #define TARGET_BS 010
1613 #define TARGET_TAB 011
1614 #define TARGET_NEWLINE 012
1615 #define TARGET_VT 013
1616 #define TARGET_FF 014
1617 #define TARGET_CR 015
1618 \f
1619 /* FINAL_PRESCAN_INSN is used to take a look at the insns, in order to delete
1620 small-distance conditional branches and have ASM_OUTPUT_OPCODE make the
1621 instructions conditional. Suffixes like s (affect flags) and b (bytewise
1622 load/store) need to stay suffixes, so the possible condition code comes
1623 before these suffixes. %d<n> or %D<n> may appear in the opcode if
1624 it can take a condition; a null rtx will cause no condition to be added,
1625 this is what we expect to happen if arm_ccfsm_state is non-zero. */
1626 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1627 { \
1628 extern int arm_ccfsm_state, arm_current_cc; \
1629 extern char *arm_condition_codes[]; \
1630 int i; \
1631 \
1632 fflush (STREAM); /* XXX for debugging only. */ \
1633 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) \
1634 { \
1635 for (i = 0; *(PTR) != ' ' && *(PTR) != '\t' && *(PTR) != '%' && i < 3;\
1636 i++, (PTR)++) \
1637 putc (*(PTR), STREAM); \
1638 fprintf (STREAM, "%s", arm_condition_codes[arm_current_cc]); \
1639 for (; *(PTR) != ' ' && *(PTR) != '\t' && *(PTR) != '%'; (PTR)++) \
1640 putc (*(PTR), STREAM); \
1641 } \
1642 }
1643
1644 /* Only perform branch elimination (by making instructions conditional) if
1645 we're optimising. Otherwise it's of no use anyway. */
1646 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1647 if (optimize) \
1648 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1649
1650 /* Output an operand of an instruction. If X is a REG and CODE is `M', output
1651 a ldm/stm style multi-reg. */
1652 #define PRINT_OPERAND(STREAM, X, CODE) \
1653 { \
1654 if ((CODE) == 'd') \
1655 { \
1656 if (X) \
1657 fputs (arm_condition_codes[get_arm_condition_code (X)], \
1658 (STREAM)); \
1659 } \
1660 else if ((CODE) == 'D') \
1661 { \
1662 if (X) \
1663 fputs (arm_condition_codes[get_arm_condition_code (X) ^ 1], \
1664 (STREAM)); \
1665 } \
1666 else if ((CODE) == 'R') \
1667 fputs (reg_names[REGNO (X) + 1], (STREAM)); \
1668 else if (GET_CODE (X) == REG) \
1669 { \
1670 if ((CODE) != 'M') \
1671 fputs (reg_names[REGNO (X)], (STREAM)); \
1672 else \
1673 fprintf ((STREAM), "{%s-%s}", \
1674 reg_names[REGNO (X)], \
1675 reg_names[REGNO (X) - 1 \
1676 + ((GET_MODE_SIZE (GET_MODE (X)) \
1677 + GET_MODE_SIZE (SImode) - 1) \
1678 / GET_MODE_SIZE (SImode))]); \
1679 } \
1680 else if (GET_CODE (X) == MEM) \
1681 { \
1682 extern int output_memory_reference_mode; \
1683 output_memory_reference_mode = GET_MODE (X); \
1684 output_address (XEXP (X, 0)); \
1685 } \
1686 else if (GET_CODE(X) == CONST_DOUBLE) \
1687 fprintf(STREAM,"#%s", fp_immediate_constant(X)); \
1688 else if (GET_CODE (X) == NEG) \
1689 { \
1690 fputc ('-', (STREAM)); \
1691 output_operand ((X), 0); \
1692 } \
1693 else \
1694 { \
1695 fputc('#', STREAM); \
1696 output_addr_const(STREAM, X); \
1697 } \
1698 }
1699
1700 /* Output the address of an operand. */
1701 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1702 { \
1703 int is_minus = GET_CODE (X) == MINUS; \
1704 \
1705 if (GET_CODE (X) == REG) \
1706 fprintf (STREAM, "[%s, #0]", reg_names[REGNO (X)]); \
1707 else if (GET_CODE (X) == PLUS || is_minus) \
1708 { \
1709 rtx base = XEXP (X, 0); \
1710 rtx index = XEXP (X, 1); \
1711 char *base_reg_name; \
1712 int offset = 0; \
1713 int shift; \
1714 if (GET_CODE (base) != REG) \
1715 { \
1716 /* Ensure that BASE is a register (one of them must be). */ \
1717 rtx temp = base; \
1718 base = index; \
1719 index = temp; \
1720 } \
1721 base_reg_name = reg_names[REGNO (base)]; \
1722 switch (GET_CODE (index)) \
1723 { \
1724 case CONST_INT: \
1725 offset = INTVAL (index); \
1726 if (is_minus) \
1727 offset = -offset; \
1728 fprintf (STREAM, "[%s, #%d]", base_reg_name, offset); \
1729 break; \
1730 \
1731 case REG: \
1732 fprintf (STREAM, "[%s, %s%s]", base_reg_name, \
1733 is_minus ? "-" : "", reg_names[REGNO (index)] ); \
1734 break; \
1735 \
1736 case MULT: \
1737 if (GET_CODE (XEXP (index,0)) == CONST_INT) \
1738 { \
1739 shift = int_log2 (INTVAL (XEXP (index, 0))); \
1740 index = XEXP (index, 1); \
1741 } \
1742 else if (GET_CODE(XEXP(index,1)) == CONST_INT) \
1743 { \
1744 shift = int_log2 (INTVAL (XEXP (index, 1))); \
1745 index = XEXP (index, 0); \
1746 } \
1747 else \
1748 abort(); \
1749 fprintf (STREAM, "[%s, %s%s, asl #%d]", base_reg_name, \
1750 is_minus ? "-" : "", reg_names[REGNO (index)], \
1751 shift); \
1752 break; \
1753 case ASHIFTRT: \
1754 case LSHIFTRT: \
1755 case ASHIFT: \
1756 case ROTATERT: \
1757 { \
1758 char *shift_type = shift_instr (GET_CODE (index), \
1759 &XEXP (index, 1)); \
1760 shift = INTVAL (XEXP (index, 1)); \
1761 index = XEXP (index, 0); \
1762 fprintf (STREAM, "[%s, %s%s, %s #%d]", base_reg_name, \
1763 is_minus ? "-" : "", reg_names[REGNO (index)], \
1764 shift_type, shift); \
1765 break; \
1766 } \
1767 \
1768 default: \
1769 abort(); \
1770 } \
1771 } \
1772 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1773 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1774 { \
1775 extern int output_memory_reference_mode; \
1776 \
1777 if (GET_CODE (XEXP (X, 0)) != REG) \
1778 abort (); \
1779 \
1780 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1781 fprintf (STREAM, "[%s, #%s%d]!", reg_names[REGNO (XEXP (X, 0))],\
1782 GET_CODE (X) == PRE_DEC ? "-" : "", \
1783 GET_MODE_SIZE (output_memory_reference_mode)); \
1784 else \
1785 fprintf (STREAM, "[%s], #%s%d", reg_names[REGNO (XEXP (X, 0))], \
1786 GET_CODE (X) == POST_DEC ? "-" : "", \
1787 GET_MODE_SIZE (output_memory_reference_mode)); \
1788 } \
1789 else output_addr_const(STREAM, X); \
1790 }
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