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1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992-2019 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Instruction reorganization pass.
24 This pass runs after register allocation and final jump
25 optimization. It should be the last pass to run before peephole.
26 It serves primarily to fill delay slots of insns, typically branch
27 and call insns. Other insns typically involve more complicated
28 interactions of data dependencies and resource constraints, and
29 are better handled by scheduling before register allocation (by the
30 function `schedule_insns').
32 The Branch Penalty is the number of extra cycles that are needed to
33 execute a branch insn. On an ideal machine, branches take a single
34 cycle, and the Branch Penalty is 0. Several RISC machines approach
35 branch delays differently:
37 The MIPS has a single branch delay slot. Most insns
38 (except other branches) can be used to fill this slot. When the
39 slot is filled, two insns execute in two cycles, reducing the
40 branch penalty to zero.
42 The SPARC always has a branch delay slot, but its effects can be
43 annulled when the branch is not taken. This means that failing to
44 find other sources of insns, we can hoist an insn from the branch
45 target that would only be safe to execute knowing that the branch
46 is taken.
48 The HP-PA always has a branch delay slot. For unconditional branches
49 its effects can be annulled when the branch is taken. The effects
50 of the delay slot in a conditional branch can be nullified for forward
51 taken branches, or for untaken backward branches. This means
52 we can hoist insns from the fall-through path for forward branches or
53 steal insns from the target of backward branches.
55 The TMS320C3x and C4x have three branch delay slots. When the three
56 slots are filled, the branch penalty is zero. Most insns can fill the
57 delay slots except jump insns.
59 Three techniques for filling delay slots have been implemented so far:
61 (1) `fill_simple_delay_slots' is the simplest, most efficient way
62 to fill delay slots. This pass first looks for insns which come
63 from before the branch and which are safe to execute after the
64 branch. Then it searches after the insn requiring delay slots or,
65 in the case of a branch, for insns that are after the point at
66 which the branch merges into the fallthrough code, if such a point
67 exists. When such insns are found, the branch penalty decreases
68 and no code expansion takes place.
70 (2) `fill_eager_delay_slots' is more complicated: it is used for
71 scheduling conditional jumps, or for scheduling jumps which cannot
72 be filled using (1). A machine need not have annulled jumps to use
73 this strategy, but it helps (by keeping more options open).
74 `fill_eager_delay_slots' tries to guess the direction the branch
75 will go; if it guesses right 100% of the time, it can reduce the
76 branch penalty as much as `fill_simple_delay_slots' does. If it
77 guesses wrong 100% of the time, it might as well schedule nops. When
78 `fill_eager_delay_slots' takes insns from the fall-through path of
79 the jump, usually there is no code expansion; when it takes insns
80 from the branch target, there is code expansion if it is not the
81 only way to reach that target.
83 (3) `relax_delay_slots' uses a set of rules to simplify code that
84 has been reorganized by (1) and (2). It finds cases where
85 conditional test can be eliminated, jumps can be threaded, extra
86 insns can be eliminated, etc. It is the job of (1) and (2) to do a
87 good job of scheduling locally; `relax_delay_slots' takes care of
88 making the various individual schedules work well together. It is
89 especially tuned to handle the control flow interactions of branch
90 insns. It does nothing for insns with delay slots that do not
91 branch.
93 On machines that use CC0, we are very conservative. We will not make
94 a copy of an insn involving CC0 since we want to maintain a 1-1
95 correspondence between the insn that sets and uses CC0. The insns are
96 allowed to be separated by placing an insn that sets CC0 (but not an insn
97 that uses CC0; we could do this, but it doesn't seem worthwhile) in a
98 delay slot. In that case, we point each insn at the other with REG_CC_USER
99 and REG_CC_SETTER notes. Note that these restrictions affect very few
100 machines because most RISC machines with delay slots will not use CC0
101 (the RT is the only known exception at this point). */
122 \f
123 /* First, some functions that were used before GCC got a control flow graph.
124 These functions are now only used here in reorg.c, and have therefore
125 been moved here to avoid inadvertent misuse elsewhere in the compiler. */
127 /* Return the last label to mark the same position as LABEL. Return LABEL
128 itself if it is null or any return rtx. */
130 static rtx
132 {
145 }
147 /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER
148 and REG_CC_USER notes so we can find it. */
150 static void
152 {
160 }
161 \f
162 /* Insns which have delay slots that have not yet been filled. */
167 /* Define macros to refer to the first and last slot containing unfilled
168 insns. These are used because the list may move and its address
169 should be recomputed at each use. */
171 #define unfilled_slots_base \
172 ((rtx_insn **) obstack_base (&unfilled_slots_obstack))
174 #define unfilled_slots_next \
175 ((rtx_insn **) obstack_next_free (&unfilled_slots_obstack))
177 /* Points to the label before the end of the function, or before a
178 return insn. */
180 /* Likewise for a simple_return. */
183 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
184 not always monotonically increase. */
187 /* Highest valid index in `uid_to_ruid'. */
215 rtx *);
237 \f
238 /* A wrapper around next_active_insn which takes care to return ret_rtx
239 unchanged. */
241 static rtx
243 {
247 }
248 \f
249 /* Return true iff INSN is a simplejump, or any kind of return insn. */
251 static bool
253 {
257 }
258 \f
259 /* Return TRUE if this insn should stop the search for insn to fill delay
260 slots. LABELS_P indicates that labels should terminate the search.
261 In all cases, jumps terminate the search. */
263 static int
265 {
269 /* If the insn can throw an exception that is caught within the function,
270 it may effectively perform a jump from the viewpoint of the function.
271 Therefore act like for a jump. */
276 {
290 /* OK unless it contains a delay slot or is an `asm' insn of some type.
291 We don't know anything about these. */
298 }
299 }
300 \f
301 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
302 resource set contains a volatile memory reference. Otherwise, return FALSE. */
304 static int
306 {
312 }
314 /* Return TRUE if any resource marked in RES, a `struct resources', is
315 referenced by INSN. If INCLUDE_DELAYED_EFFECTS is set, return if the called
316 routine is using those resources.
318 We compute this by computing all the resources referenced by INSN and
319 seeing if this conflicts with RES. It might be faster to directly check
320 ourselves, and this is the way it used to work, but it means duplicating
321 a large block of complex code. */
323 static int
326 {
332 }
334 /* Return TRUE if INSN modifies resources that are marked in RES.
335 INCLUDE_DELAYED_EFFECTS is set if the actions of that routine should be
336 included. CC0 is only modified if it is explicitly set; see comments
337 in front of mark_set_resources for details. */
339 static int
342 {
347 (include_delayed_effects
348 ? MARK_SRC_DEST_CALL
351 }
352 \f
353 /* Find a label at the end of the function or before a RETURN. If there
354 is none, try to make one. If that fails, returns 0.
356 The property of such a label is that it is placed just before the
357 epilogue or a bare RETURN insn, so that another bare RETURN can be
358 turned into a jump to the label unconditionally. In particular, the
359 label cannot be placed before a RETURN insn with a filled delay slot.
361 ??? There may be a problem with the current implementation. Suppose
362 we start with a bare RETURN insn and call find_end_label. It may set
363 function_return_label just before the RETURN. Suppose the machinery
364 is able to fill the delay slot of the RETURN insn afterwards. Then
365 function_return_label is no longer valid according to the property
366 described above and find_end_label will still return it unmodified.
367 Note that this is probably mitigated by the following observation:
368 once function_return_label is made, it is very likely the target of
369 a jump, so filling the delay slot of the RETURN will be much more
370 difficult.
371 KIND is either simple_return_rtx or ret_rtx, indicating which type of
372 return we're looking for. */
376 {
382 else
383 {
386 }
388 /* If we found one previously, return it. */
392 /* Otherwise, see if there is a label at the end of the function. If there
393 is, it must be that RETURN insns aren't needed, so that is our return
394 label and we don't have to do anything else. */
404 /* When a target threads its epilogue we might already have a
405 suitable return insn. If so put a label before it for the
406 function_return_label. */
410 {
415 /* Put the label before any USE insns that may precede the RETURN
416 insn. */
422 }
426 else
427 {
430 /* If the basic block reorder pass moves the return insn to
431 some other place try to locate it again and put our
432 function_return_label there. */
436 {
439 /* Put the label before any USE insns that may precede the
440 RETURN insn. */
445 }
446 else
447 {
449 /* The RETURN insn has its delay slot filled so we cannot
450 emit the label just before it. Since we already have
451 an epilogue and cannot emit a new RETURN, we cannot
452 emit the label at all. */
455 /* Otherwise, make a new label and emit a RETURN and BARRIER,
456 if needed. */
459 {
460 /* The return we make may have delay slots too. */
467 }
468 }
470 }
472 /* Show one additional use for this label so it won't go away until
473 we are done. */
477 }
478 \f
479 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
480 the pattern of INSN with the SEQUENCE.
482 Returns the insn containing the SEQUENCE that replaces INSN. */
486 {
487 /* Allocate the rtvec to hold the insns and the SEQUENCE. */
492 /* If DELAY_INSN has a location, use it for SEQ_INSN. If DELAY_INSN does
493 not have a location, but one of the delayed insns does, we pick up a
494 location from there later. */
497 /* Unlink INSN from the insn chain, so that we can put it into
498 the SEQUENCE. Remember where we want to emit SEQUENCE in AFTER. */
503 /* Build our SEQUENCE and rebuild the insn chain. */
510 {
514 /* Show that this copy of the insn isn't deleted. */
517 /* Unlink insn from its original place, and re-emit it into
518 the sequence. */
522 /* SPARC assembler, for instance, emit warning when debug info is output
523 into the delay slot. */
529 {
532 {
534 /* Remove any REG_DEAD notes because we can't rely on them now
535 that the insn has been moved. */
541 /* Keep the label reference count up to date. */
548 }
549 }
550 }
553 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
557 }
559 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
560 be in the order in which the insns are to be executed. */
562 static void
564 {
565 /* If INSN has its block number recorded, clear it since we may
566 be moving the insn to a new block. */
569 }
570 \f
571 /* Delete INSN from the delay slot of the insn that it is in, which may
572 produce an insn with no delay slots. Return the new insn. */
576 {
582 /* We first must find the insn containing the SEQUENCE with INSN in its
583 delay slot. Do this by finding an insn, TRIAL, where
584 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
589 ;
597 /* Create a delay list consisting of all the insns other than the one
598 we are deleting (unless we were the only one). */
605 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
606 list, and rebuild the delay list if non-empty. */
612 /* If there was a barrier after the old SEQUENCE, remit it. */
616 /* If there are any delay insns, remit them. Otherwise clear the
617 annul flag. */
625 /* Show we need to fill this insn again. */
629 }
630 \f
631 /* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down
632 the insn that sets CC0 for it and delete it too. */
634 static void
636 {
637 /* Delete the insn that sets cc0 for us. On machines without cc0, we could
638 delete the insn that sets the condition code, but it is hard to find it.
639 Since this case is rare anyway, don't bother trying; there would likely
640 be other insns that became dead anyway, which we wouldn't know to
641 delete. */
644 {
647 /* If a reg-note was found, it points to an insn to set CC0. This
648 insn is in the delay list of some other insn. So delete it from
649 the delay list it was in. */
651 {
655 }
656 else
657 {
658 /* The insn setting CC0 is our previous insn, but it may be in
659 a delay slot. It will be the last insn in the delay slot, if
660 it is. */
669 else
671 }
672 }
675 }
676 \f
677 /* Counters for delay-slot filling. */
679 #define NUM_REORG_FUNCTIONS 2
680 #define MAX_DELAY_HISTOGRAM 3
681 #define MAX_REORG_PASSES 2
689 static void
691 {
696 }
697 \f
698 /* Optimize the following cases:
700 1. When a conditional branch skips over only one instruction,
701 use an annulling branch and put that insn in the delay slot.
702 Use either a branch that annuls when the condition if true or
703 invert the test with a branch that annuls when the condition is
704 false. This saves insns, since otherwise we must copy an insn
705 from the L1 target.
707 (orig) (skip) (otherwise)
708 Bcc.n L1 Bcc',a L1 Bcc,a L1'
709 insn insn insn2
710 L1: L1: L1:
711 insn2 insn2 insn2
712 insn3 insn3 L1':
713 insn3
715 2. When a conditional branch skips over only one instruction,
716 and after that, it unconditionally branches somewhere else,
717 perform the similar optimization. This saves executing the
718 second branch in the case where the inverted condition is true.
720 Bcc.n L1 Bcc',a L2
721 insn insn
722 L1: L1:
723 Bra L2 Bra L2
725 INSN is a JUMP_INSN.
727 This should be expanded to skip over N insns, where N is the number
728 of delay slots required. */
730 static void
732 {
749 /* There are two cases where we are just executing one insn (we assume
750 here that a branch requires only one insn; this should be generalized
751 at some point): Where the branch goes around a single insn or where
752 we have one insn followed by a branch to the same label we branch to.
753 In both of these cases, inverting the jump and annulling the delay
754 slot give the same effect in fewer insns. */
759 {
761 {
766 }
773 /* Also, if we are targeting an unconditional
774 branch, thread our jump to the target of that branch. Don't
775 change this into a RETURN here, because it may not accept what
776 we have in the delay slot. We'll fix this up later. */
778 {
784 {
785 /* Recompute the flags based on TARGET_LABEL since threading
786 the jump to TARGET_LABEL may change the direction of the
787 jump (which may change the circumstances in which the
788 delay slot is nullified). */
792 }
793 }
796 }
797 }
798 \f
799 /* Encode and return branch direction and prediction information for
800 INSN assuming it will jump to LABEL.
802 Non conditional branches return no direction information and
803 are predicted as very likely taken. */
805 static int
807 {
810 /* get_jump_flags can be passed any insn with delay slots, these may
811 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
812 direction information, and only if they are conditional jumps.
814 If LABEL is a return, then there is no way to determine the branch
815 direction. */
821 flags
824 /* No valid direction information. */
825 else
829 }
831 /* Return truth value of the statement that this branch
832 is mostly taken. If we think that the branch is extremely likely
833 to be taken, we return 2. If the branch is slightly more likely to be
834 taken, return 1. If the branch is slightly less likely to be taken,
835 return 0 and if the branch is highly unlikely to be taken, return -1. */
837 static int
839 {
840 /* If branch probabilities are available, then use that number since it
841 always gives a correct answer. */
844 {
854 else
856 }
858 /* If there is no note, assume branches are not taken.
859 This should be rare. */
861 }
863 /* Return the condition under which INSN will branch to TARGET. If TARGET
864 is zero, return the condition under which INSN will return. If INSN is
865 an unconditional branch, return const_true_rtx. If INSN isn't a simple
866 type of jump, or it doesn't go to TARGET, return 0. */
868 static rtx
870 {
872 rtx src;
899 {
906 }
909 }
911 /* Return nonzero if CONDITION is more strict than the condition of
912 INSN, i.e., if INSN will always branch if CONDITION is true. */
914 static int
916 {
935 }
937 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
938 any insns already in the delay slot of JUMP. */
940 static int
942 {
946 /* Make sure all the delay slots of this jump would still
947 be valid after threading the jump. If they are still
948 valid, then return nonzero. */
953 #if ANNUL_IFFALSE_SLOTS
957 #endif
958 #if ANNUL_IFTRUE_SLOTS
962 #endif
967 }
969 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
970 any insns we wish to place in the delay slot of JUMP. */
972 static int
975 {
976 /* Make sure all the insns in DELAY_LIST would still be
977 valid after threading the jump. If they are still
978 valid, then return nonzero. */
985 #if ANNUL_IFFALSE_SLOTS
989 #endif
990 #if ANNUL_IFTRUE_SLOTS
994 #endif
999 }
1001 /* DELAY_LIST is a list of insns that have already been placed into delay
1002 slots. See if all of them have the same annulling status as ANNUL_TRUE_P.
1003 If not, return 0; otherwise return 1. */
1005 static int
1008 {
1017 }
1018 \f
1019 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
1020 the condition tested by INSN is CONDITION and the resources shown in
1021 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
1022 from SEQ's delay list, in addition to whatever insns it may execute
1023 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
1024 needed while searching for delay slot insns. Return the concatenated
1025 delay list if possible, otherwise, return 0.
1027 SLOTS_TO_FILL is the total number of slots required by INSN, and
1028 PSLOTS_FILLED points to the number filled so far (also the number of
1029 insns in DELAY_LIST). It is updated with the number that have been
1030 filled from the SEQUENCE, if any.
1032 PANNUL_P points to a nonzero value if we already know that we need
1033 to annul INSN. If this routine determines that annulling is needed,
1034 it may set that value nonzero.
1036 PNEW_THREAD points to a location that is to receive the place at which
1037 execution should continue. */
1039 static void
1047 {
1057 /* We can't do anything if there are more delay slots in SEQ than we
1058 can handle, or if we don't know that it will be a taken branch.
1059 We know that it will be a taken branch if it is either an unconditional
1060 branch or a conditional branch with a stricter branch condition.
1062 Also, exit if the branch has more than one set, since then it is computing
1063 other results that can't be ignored, e.g. the HPPA mov&branch instruction.
1064 ??? It may be possible to move other sets into INSN in addition to
1065 moving the instructions in the delay slots.
1067 We cannot steal the delay list if one of the instructions in the
1068 current delay_list modifies the condition codes and the jump in the
1069 sequence is a conditional jump. We cannot do this because we cannot
1070 change the direction of the jump because the condition codes
1071 will effect the direction of the jump in the sequence. */
1077 {
1081 }
1088 /* On some targets, branches with delay slots can have a limited
1089 displacement. Give the back end a chance to tell us we can't do
1090 this. */
1096 {
1103 /* If TRIAL sets CC0, we can't copy it, so we can't steal this
1104 delay list. */
1106 /* If TRIAL is from the fallthrough code of an annulled branch insn
1107 in SEQ, we cannot use it. */
1112 /* If this insn was already done (usually in a previous delay slot),
1113 pretend we put it in our delay slot. */
1118 /* We will end up re-vectoring this branch, so compute flags
1119 based on jumping to the new label. */
1133 {
1135 {
1136 /* Frame related instructions cannot go into annulled delay
1137 slots, it messes up the dwarf info. */
1141 }
1145 total_slots_filled++;
1149 }
1150 else
1152 }
1154 /* Record the effect of the instructions that were redundant and which
1155 we therefore decided not to copy. */
1158 {
1161 }
1163 /* Show the place to which we will be branching. */
1166 /* Add any new insns to the delay list and update the count of the
1167 number of slots filled. */
1175 }
1176 \f
1177 /* Similar to steal_delay_list_from_target except that SEQ is on the
1178 fallthrough path of INSN. Here we only do something if the delay insn
1179 of SEQ is an unconditional branch. In that case we steal its delay slot
1180 for INSN since unconditional branches are much easier to fill. */
1182 static void
1191 {
1199 /* We can't do anything if SEQ's delay insn isn't an
1200 unconditional branch. */
1206 {
1210 /* If TRIAL sets CC0, stealing it will move it too far from the use
1211 of CC0. */
1219 /* If this insn was already done, we don't need it. */
1221 {
1226 }
1236 {
1244 }
1245 else
1247 }
1251 }
1252 \f
1253 /* Try merging insns starting at THREAD which match exactly the insns in
1254 INSN's delay list.
1256 If all insns were matched and the insn was previously annulling, the
1257 annul bit will be cleared.
1259 For each insn that is merged, if the branch is or will be non-annulling,
1260 we delete the merged insn. */
1262 static void
1264 {
1280 /* If this is not an annulling branch, take into account anything needed in
1281 INSN's delay slot. This prevents two increments from being incorrectly
1282 folded into one. If we are annulling, this would be the correct
1283 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1284 will essentially disable this optimization. This method is somewhat of
1285 a kludge, but I don't see a better way.) */
1293 {
1299 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1306 /* We can't share an insn that sets cc0. */
1312 /* Update next_trial, in case try_split succeeded. */
1314 /* Likewise THREAD. */
1317 /* Have to test this condition if annul condition is different
1318 from (and less restrictive than) non-annulling one. */
1320 {
1323 {
1330 }
1331 else
1338 }
1342 }
1344 /* See if we stopped on a filled insn. If we did, try to see if its
1345 delay slots match. */
1351 {
1355 /* Account for resources set/needed by the filled insn. */
1360 {
1364 /* Account for resources set by the insn following NEXT_TO_MATCH
1365 inside INSN's delay list. */
1369 /* Account for resources set by the insn before DTRIAL and inside
1370 TRIAL's delay list. */
1379 /* Check that DTRIAL and NEXT_TO_MATCH does not reference a
1380 resource modified between them (only dtrial is checked because
1381 next_to_match and dtrial shall to be equal in order to hit
1382 this line) */
1385 {
1387 {
1395 }
1396 else
1404 }
1405 else
1406 {
1407 /* Keep track of the set/referenced resources for the delay
1408 slots of any trial insns we encounter. */
1411 }
1412 }
1413 }
1415 /* If all insns in the delay slot have been matched and we were previously
1416 annulling the branch, we need not any more. In that case delete all the
1417 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn in
1418 the delay list so that we know that it isn't only being used at the
1419 target. */
1421 {
1425 {
1430 }
1431 else
1432 {
1435 }
1441 }
1442 }
1443 \f
1444 /* See if INSN is redundant with an insn in front of TARGET. Often this
1445 is called when INSN is a candidate for a delay slot of TARGET.
1446 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1447 of INSN. Often INSN will be redundant with an insn in a delay slot of
1448 some previous insn. This happens when we have a series of branches to the
1449 same label; in that case the first insn at the target might want to go
1450 into each of the delay slots.
1452 If we are not careful, this routine can take up a significant fraction
1453 of the total compilation time (4%), but only wins rarely. Hence we
1454 speed this routine up by making two passes. The first pass goes back
1455 until it hits a label and sees if it finds an insn with an identical
1456 pattern. Only in this (relatively rare) event does it check for
1457 data conflicts.
1459 We do not split insns we encounter. This could cause us not to find a
1460 redundant insn, but the cost of splitting seems greater than the possible
1461 gain in rare cases. */
1465 {
1469 rtx pat;
1474 /* If INSN has any REG_UNUSED notes, it can't match anything since we
1475 are allowed to not actually assign to such a register. */
1479 /* Scan backwards looking for a match. */
1484 {
1485 /* (use (insn))s can come immediately after a barrier if the
1486 label that used to precede them has been deleted as dead.
1487 See delete_related_insns. */
1504 {
1505 /* Stop for a CALL and its delay slots because it is difficult to
1506 track its resource needs correctly. */
1510 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
1511 slots because it is difficult to track its resource needs
1512 correctly. */
1520 /* See if any of the insns in the delay slot match, updating
1521 resource requirements as we go. */
1528 /* If found a match, exit this loop early. */
1531 }
1536 }
1538 /* If we didn't find an insn that matches, return 0. */
1542 /* See what resources this insn sets and needs. If they overlap, or
1543 if this insn references CC0, it can't be redundant. */
1550 /* If TARGET is a SEQUENCE, get the main insn. */
1556 /* The insn requiring the delay may not set anything needed or set by
1557 INSN. */
1562 /* Insns we pass may not set either NEEDED or SET, so merge them for
1563 simpler tests. */
1567 /* This insn isn't redundant if it conflicts with an insn that either is
1568 or will be in a delay slot of TARGET. */
1582 /* Scan backwards until we reach a label or an insn that uses something
1583 INSN sets or sets something insn uses or sets. */
1589 {
1603 {
1607 /* If this is a CALL_INSN and its delay slots, it is hard to track
1608 the resource needs properly, so give up. */
1612 /* If this is an INSN or JUMP_INSN with delayed effects, it
1613 is hard to track the resource needs properly, so give up. */
1624 /* See if any of the insns in the delay slot match, updating
1625 resource requirements as we go. */
1627 {
1630 /* If an insn will be annulled if the branch is false, it isn't
1631 considered as a possible duplicate insn. */
1634 {
1635 /* Show that this insn will be used in the sequel. */
1638 }
1640 /* Unless this is an annulled insn from the target of a branch,
1641 we must stop if it sets anything needed or set by INSN. */
1645 }
1647 /* If the insn requiring the delay slot conflicts with INSN, we
1648 must stop. */
1651 }
1652 else
1653 {
1654 /* See if TRIAL is the same as INSN. */
1659 /* Can't go any further if TRIAL conflicts with INSN. */
1662 }
1663 }
1666 }
1667 \f
1668 /* Return 1 if THREAD can only be executed in one way. If LABEL is nonzero,
1669 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
1670 is nonzero, we are allowed to fall into this thread; otherwise, we are
1671 not.
1673 If LABEL is used more than one or we pass a label other than LABEL before
1674 finding an active insn, we do not own this thread. */
1676 static int
1678 {
1682 /* We don't own the function end. */
1686 /* We have a non-NULL insn. */
1689 /* Get the first active insn, or THREAD_INSN, if it is an active insn. */
1700 /* Ensure that we reach a BARRIER before any insn or label. */
1713 }
1714 \f
1715 /* Called when INSN is being moved from a location near the target of a jump.
1716 We leave a marker of the form (use (INSN)) immediately in front of WHERE
1717 for mark_target_live_regs. These markers will be deleted at the end.
1719 We used to try to update the live status of registers if WHERE is at
1720 the start of a basic block, but that can't work since we may remove a
1721 BARRIER in relax_delay_slots. */
1723 static void
1725 {
1728 /* INSN might be making a value live in a block where it didn't use to
1729 be. So recompute liveness information for this block. */
1731 }
1733 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
1734 the basic block containing the jump. */
1736 static int
1738 {
1741 }
1743 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
1744 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
1745 that reference values used in INSN. If we find one, then we move the
1746 REG_DEAD note to INSN.
1748 This is needed to handle the case where a later insn (after INSN) has a
1749 REG_DEAD note for a register used by INSN, and this later insn subsequently
1750 gets moved before a CODE_LABEL because it is a redundant insn. In this
1751 case, mark_target_live_regs may be confused into thinking the register
1752 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
1754 static void
1756 {
1763 {
1771 {
1772 /* Move the REG_DEAD note from P to INSN. */
1776 }
1777 }
1778 }
1780 /* Called when an insn redundant with start_insn is deleted. If there
1781 is a REG_DEAD note for the target of start_insn between start_insn
1782 and stop_insn, then the REG_DEAD note needs to be deleted since the
1783 value no longer dies there.
1785 If the REG_DEAD note isn't deleted, then mark_target_live_regs may be
1786 confused into thinking the register is dead. */
1788 static void
1790 {
1797 {
1805 {
1808 }
1809 }
1810 }
1812 /* Delete any REG_UNUSED notes that exist on INSN but not on OTHER_INSN.
1814 This handles the case of udivmodXi4 instructions which optimize their
1815 output depending on whether any REG_UNUSED notes are present. We must
1816 make sure that INSN calculates as many results as OTHER_INSN does. */
1818 static void
1820 {
1824 {
1833 }
1834 }
1835 \f
1838 /* Return the label before INSN, or put a new label there. If SIBLING is
1839 non-zero, it is another label associated with the new label (if any),
1840 typically the former target of the jump that will be redirected to
1841 the new label. */
1845 {
1848 /* Find an existing label at this point
1849 or make a new one if there is none. */
1853 {
1860 {
1863 }
1864 }
1866 }
1868 /* Scan a function looking for insns that need a delay slot and find insns to
1869 put into the delay slot.
1871 NON_JUMPS_P is nonzero if we are to only try to fill non-jump insns (such
1872 as calls). We do these first since we don't want jump insns (that are
1873 easier to fill) to get the only insns that could be used for non-jump insns.
1874 When it is zero, only try to fill JUMP_INSNs.
1876 When slots are filled in this manner, the insns (including the
1877 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
1878 it is possible to tell whether a delay slot has really been filled
1879 or not. `final' knows how to deal with this, by communicating
1880 through FINAL_SEQUENCE. */
1882 static void
1884 {
1886 rtx pat;
1894 {
1896 /* Get the next insn to fill. If it has already had any slots assigned,
1897 we can't do anything with it. Maybe we'll improve this later. */
1908 /* It may have been that this insn used to need delay slots, but
1909 now doesn't; ignore in that case. This can happen, for example,
1910 on the HP PA RISC, where the number of delay slots depends on
1911 what insns are nearby. */
1914 /* Some machine description have defined instructions to have
1915 delay slots only in certain circumstances which may depend on
1916 nearby insns (which change due to reorg's actions).
1918 For example, the PA port normally has delay slots for unconditional
1919 jumps.
1921 However, the PA port claims such jumps do not have a delay slot
1922 if they are immediate successors of certain CALL_INSNs. This
1923 allows the port to favor filling the delay slot of the call with
1924 the unconditional jump. */
1928 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
1929 says how many. After initialization, first try optimizing
1931 call _foo call _foo
1932 nop add %o7,.-L1,%o7
1933 b,a L1
1934 nop
1936 If this case applies, the delay slot of the call is filled with
1937 the unconditional jump. This is done first to avoid having the
1938 delay slot of the call filled in the backward scan. Also, since
1939 the unconditional jump is likely to also have a delay slot, that
1940 insn must exist when it is subsequently scanned.
1942 This is tried on each insn with delay slots as some machines
1943 have insns which perform calls, but are not represented as
1944 CALL_INSNs. */
1951 else
1960 {
1962 slots_filled++;
1965 /* TRIAL may have had its delay slot filled, then unfilled. When
1966 the delay slot is unfilled, TRIAL is placed back on the unfilled
1967 slots obstack. Unfortunately, it is placed on the end of the
1968 obstack, not in its original location. Therefore, we must search
1969 from entry i + 1 to the end of the unfilled slots obstack to
1970 try and find TRIAL. */
1973 tmp++;
1975 /* Remove the unconditional jump from consideration for delay slot
1976 filling and unthread it. */
1979 {
1986 }
1987 }
1989 /* Now, scan backwards from the insn to search for a potential
1990 delay-slot candidate. Stop searching when a label or jump is hit.
1992 For each candidate, if it is to go into the delay slot (moved
1993 forward in execution sequence), it must not need or set any resources
1994 that were set by later insns and must not set any resources that
1995 are needed for those insns.
1997 The delay slot insn itself sets resources unless it is a call
1998 (in which case the called routine, not the insn itself, is doing
1999 the setting). */
2002 {
2003 /* If the flags register is dead after the insn, then we want to be
2004 able to accept a candidate that clobbers it. For this purpose,
2005 we need to filter the flags register during life analysis, so
2006 that it doesn't create RAW and WAW dependencies, while still
2007 creating the necessary WAR dependencies. */
2008 bool filter_flags
2017 {
2020 }
2025 {
2028 /* This must be an INSN or CALL_INSN. */
2031 /* Stand-alone USE and CLOBBER are just for flow. */
2036 /* And DEBUG_INSNs never go into delay slots. */
2040 /* Check for resource conflict first, to avoid unnecessary
2041 splitting. */
2047 /* Can't separate set of cc0 from its use. */
2050 {
2054 {
2055 /* In this case, we are searching backward, so if we
2056 find insns to put on the delay list, we want
2057 to put them at the head, rather than the
2058 tail, of the list. */
2067 }
2068 }
2072 {
2074 /* If the flags register is set, then it doesn't create RAW
2075 dependencies any longer and it also doesn't create WAW
2076 dependencies since it's dead after the original insn. */
2078 {
2081 }
2082 }
2084 }
2085 }
2087 /* If all needed slots haven't been filled, we come here. */
2089 /* Try to optimize case of jumping around a single insn. */
2096 {
2100 }
2102 /* Try to get insns from beyond the insn needing the delay slot.
2103 These insns can neither set or reference resources set in insns being
2104 skipped, cannot set resources in the insn being skipped, and, if this
2105 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
2106 call might not return).
2108 There used to be code which continued past the target label if
2109 we saw all uses of the target label. This code did not work,
2110 because it failed to account for some instructions which were
2111 both annulled and marked as from the target. This can happen as a
2112 result of optimize_skip. Since this code was redundant with
2113 fill_eager_delay_slots anyways, it was just deleted. */
2116 /* If this instruction could throw an exception which is
2117 caught in the same function, then it's not safe to fill
2118 the delay slot with an instruction from beyond this
2119 point. For example, consider:
2121 int i = 2;
2123 try {
2124 f();
2125 i = 3;
2126 } catch (...) {}
2128 return i;
2130 Even though `i' is a local variable, we must be sure not
2131 to put `i = 3' in the delay slot if `f' might throw an
2132 exception.
2134 Presumably, we should also check to see if we could get
2135 back to this function via `setjmp'. */
2138 {
2152 {
2155 /* This must be an INSN or CALL_INSN. */
2158 /* Stand-alone USE and CLOBBER are just for flow. */
2163 /* And DEBUG_INSNs do not go in delay slots. */
2167 /* If this already has filled delay slots, get the insn needing
2168 the delay slots. */
2171 else
2174 /* Stop our search when seeing a jump. */
2178 /* See if we have a resource problem before we try to split. */
2188 {
2198 }
2203 /* Ensure we don't put insns between the setting of cc and the
2204 comparison by moving a setting of cc into an earlier delay
2205 slot since these insns could clobber the condition code. */
2208 /* If this is a call, we might not get here. */
2211 }
2213 /* If there are slots left to fill and our search was stopped by an
2214 unconditional branch, try the insn at the branch target. We can
2215 redirect the branch if it works.
2217 Don't do this if the insn at the branch target is a branch. */
2219 && trial
2234 {
2235 /* See comment in relax_delay_slots about necessity of using
2236 next_real_nondebug_insn here. */
2241 else
2245 {
2248 slots_filled++;
2250 new_label);
2251 }
2252 }
2253 }
2255 /* If this is an unconditional jump, then try to get insns from the
2256 target of the jump. */
2275 }
2276 }
2277 \f
2278 /* Follow any unconditional jump at LABEL, for the purpose of redirecting JUMP;
2279 return the ultimate label reached by any such chain of jumps.
2280 Return a suitable return rtx if the chain ultimately leads to a
2281 return instruction.
2282 If LABEL is not followed by a jump, return LABEL.
2283 If the chain loops or we can't find end, return LABEL,
2284 since that tells caller to avoid changing the insn.
2285 If the returned label is obtained by following a crossing jump,
2286 set *CROSSING to true, otherwise set it to false. */
2288 static rtx
2290 {
2310 depth++)
2311 {
2314 /* If we have found a cycle, make the insn jump to itself. */
2318 /* Cannot follow returns and cannot look through tablejumps. */
2332 }
2336 }
2338 /* Try to find insns to place in delay slots.
2340 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
2341 or is an unconditional branch if CONDITION is const_true_rtx.
2342 *PSLOTS_FILLED is updated with the number of slots that we have filled.
2344 THREAD is a flow-of-control, either the insns to be executed if the
2345 branch is true or if the branch is false, THREAD_IF_TRUE says which.
2347 OPPOSITE_THREAD is the thread in the opposite direction. It is used
2348 to see if any potential delay slot insns set things needed there.
2350 LIKELY is nonzero if it is extremely likely that the branch will be
2351 taken and THREAD_IF_TRUE is set. This is used for the branch at the
2352 end of a loop back up to the top.
2354 OWN_THREAD is true if we are the only user of the thread, i.e. it is
2355 the target of the jump when we are the only jump going there.
2357 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
2358 case, we can only take insns from the head of the thread for our delay
2359 slot. We then adjust the jump to point after the insns we have taken. */
2361 static void
2366 {
2367 rtx new_thread;
2374 /* Validate our arguments. */
2380 /* If our thread is the end of subroutine, we can't get any delay
2381 insns from that. */
2387 /* If this is an unconditional branch, nothing is needed at the
2388 opposite thread. Otherwise, compute what is needed there. */
2391 else
2394 /* If the insn at THREAD can be split, do it here to avoid having to
2395 update THREAD and NEW_THREAD if it is done in the loop below. Also
2396 initialize NEW_THREAD. */
2400 /* Scan insns at THREAD. We are looking for an insn that can be removed
2401 from THREAD (it neither sets nor references resources that were set
2402 ahead of it and it doesn't set anything needs by the insns ahead of
2403 it) and that either can be placed in an annulling insn or aren't
2404 needed at OPPOSITE_THREAD. */
2409 /* If we do not own this thread, we must stop as soon as we find
2410 something that we can't put in a delay slot, since all we can do
2411 is branch into THREAD at a later point. Therefore, labels stop
2412 the search if this is not the `true' thread. */
2417 {
2420 /* If we have passed a label, we no longer own this thread. */
2422 {
2425 }
2435 /* If TRIAL conflicts with the insns ahead of it, we lose. Also,
2436 don't separate or copy insns that set and use CC0. */
2443 {
2446 /* If TRIAL is redundant with some insn before INSN, we don't
2447 actually need to add it to the delay list; we can merely pretend
2448 we did. */
2450 {
2453 {
2456 {
2460 }
2463 }
2464 else
2465 {
2468 }
2471 }
2473 /* There are two ways we can win: If TRIAL doesn't set anything
2474 needed at the opposite thread and can't trap, or if it can
2475 go into an annulled delay slot. But we want neither to copy
2476 nor to speculate frame-related insns. */
2483 {
2493 }
2497 {
2510 {
2514 winner:
2519 /* If we own this thread, delete the insn. If this is the
2520 destination of a branch, show that a basic block status
2521 may have been updated. In any case, mark the new
2522 starting point of this thread. */
2524 {
2525 rtx note;
2529 {
2533 }
2535 /* We are moving this insn, not deleting it. We must
2536 temporarily increment the use count on any referenced
2537 label lest it be deleted by delete_related_insns. */
2543 {
2544 /* REG_LABEL_OPERAND could be
2545 NOTE_INSN_DELETED_LABEL too. */
2548 else
2551 }
2562 {
2563 /* REG_LABEL_OPERAND could be
2564 NOTE_INSN_DELETED_LABEL too. */
2567 else
2570 }
2573 }
2574 else
2584 {
2585 /* Even though we have filled all the slots, we
2586 may be branching to a location that has a
2587 redundant insn. Skip any if so. */
2594 && (prior_insn
2597 {
2598 /* We know we do not own the thread, so no need
2599 to call update_block and delete_insn. */
2602 new_thread
2604 }
2606 }
2609 }
2610 }
2611 }
2613 /* This insn can't go into a delay slot. */
2618 /* Ensure we don't put insns between the setting of cc and the comparison
2619 by moving a setting of cc into an earlier delay slot since these insns
2620 could clobber the condition code. */
2623 /* If this insn is a register-register copy and the next insn has
2624 a use of our destination, change it to use our source. That way,
2625 it will become a candidate for our delay slot the next time
2626 through this loop. This case occurs commonly in loops that
2627 scan a list.
2629 We could check for more complex cases than those tested below,
2630 but it doesn't seem worth it. It might also be a good idea to try
2631 to swap the two insns. That might do better.
2633 We can't do this if the next insn modifies our destination, because
2634 that would make the replacement into the insn invalid. We also can't
2635 do this if it modifies our source, because it might be an earlyclobber
2636 operand. This latter test also prevents updating the contents of
2637 a PRE_INC. We also can't do this if there's overlap of source and
2638 destination. Overlap may happen for larger-than-register-size modes. */
2644 {
2654 }
2655 }
2657 /* If we stopped on a branch insn that has delay slots, see if we can
2658 steal some of the insns in those slots. */
2662 {
2664 /* If this is the `true' thread, we will want to follow the jump,
2665 so we can only do this if we have taken everything up to here. */
2667 {
2673 /* If we owned the thread and are told that it branched
2674 elsewhere, make sure we own the thread at the new location. */
2677 }
2683 }
2685 /* If we haven't found anything for this delay slot and it is very
2686 likely that the branch will be taken, see if the insn at our target
2687 increments or decrements a register with an increment that does not
2688 depend on the destination register. If so, try to place the opposite
2689 arithmetic insn after the jump insn and put the arithmetic insn in the
2690 delay slot. If we can't do this, return. */
2697 {
2699 rtx dest;
2700 rtx src;
2702 /* We know "new_thread" is an insn due to NONJUMP_INSN_P (new_thread)
2703 above. */
2720 {
2722 rtx new_arith;
2725 /* If this is a constant adjustment, use the same code with
2726 the negated constant. Otherwise, reverse the sense of the
2727 arithmetic. */
2731 else
2740 {
2743 }
2746 {
2749 {
2753 }
2755 }
2756 else
2765 }
2766 }
2771 /* If we are to branch into the middle of this thread, find an appropriate
2772 label or make a new one if none, and redirect INSN to it. If we hit the
2773 end of the function, use the end-of-function label. */
2775 {
2776 rtx label;
2792 else
2797 {
2801 }
2802 }
2803 }
2804 \f
2805 /* Make another attempt to find insns to place in delay slots.
2807 We previously looked for insns located in front of the delay insn
2808 and, for non-jump delay insns, located behind the delay insn.
2810 Here only try to schedule jump insns and try to move insns from either
2811 the target or the following insns into the delay slot. If annulling is
2812 supported, we will be likely to do this. Otherwise, we can do this only
2813 if safe. */
2815 static void
2817 {
2823 {
2824 rtx condition;
2841 /* Some machine description have defined instructions to have
2842 delay slots only in certain circumstances which may depend on
2843 nearby insns (which change due to reorg's actions).
2845 For example, the PA port normally has delay slots for unconditional
2846 jumps.
2848 However, the PA port claims such jumps do not have a delay slot
2849 if they are immediate successors of certain CALL_INSNs. This
2850 allows the port to favor filling the delay slot of the call with
2851 the unconditional jump. */
2862 /* Get the next active fallthrough and target insns and see if we own
2863 them. Then see whether the branch is likely true. We don't need
2864 to do a lot of this for unconditional branches. */
2870 {
2874 }
2875 else
2876 {
2880 }
2882 /* If this insn is expected to branch, first try to get insns from our
2883 target, then our fallthrough insns. If it is not expected to branch,
2884 try the other order. */
2887 {
2890 own_target,
2894 {
2895 /* Even though we didn't find anything for delay slots,
2896 we might have found a redundant insn which we deleted
2897 from the thread that was filled. So we have to recompute
2898 the next insn at the target. */
2906 }
2907 }
2908 else
2909 {
2919 }
2929 }
2930 }
2931 \f
2934 /* Recursively delete prior insns that compute the value (used only by INSN
2935 which the caller is deleting) stored in the register mentioned by NOTE
2936 which is a REG_DEAD note associated with INSN. */
2938 static void
2940 {
2948 {
2951 /* If we reach a CALL which is not calling a const function
2952 or the callee pops the arguments, then give up. */
2958 /* If we reach a SEQUENCE, it is too complex to try to
2959 do anything with it, so give up. We can be run during
2960 and after reorg, so SEQUENCE rtl can legitimately show
2961 up here. */
2967 /* reorg creates USEs that look like this. We leave them
2968 alone because reorg needs them for its own purposes. */
2972 {
2977 {
2978 /* If we find a SET of something else, we can't
2979 delete the insn. */
2984 {
2990 }
2994 }
2997 {
3007 /* We may have a multi-word hard register and some, but not
3008 all, of the words of the register are needed in subsequent
3009 insns. Write REG_UNUSED notes for those parts that were not
3010 needed. */
3013 {
3024 }
3025 }
3028 }
3030 /* If PAT references the register that dies here, it is an
3031 additional use. Hence any prior SET isn't dead. However, this
3032 insn becomes the new place for the REG_DEAD note. */
3034 {
3038 }
3039 }
3040 }
3042 /* Delete INSN and recursively delete insns that compute values used only
3043 by INSN. This uses the REG_DEAD notes computed during flow analysis.
3045 Look at all our REG_DEAD notes. If a previous insn does nothing other
3046 than set a register that dies in this insn, we can delete that insn
3047 as well.
3049 On machines with CC0, if CC0 is used in this insn, we may be able to
3050 delete the insn that set it. */
3052 static void
3054 {
3058 {
3060 /* We assume that at this stage
3061 CC's are always set explicitly
3062 and always immediately before the jump that
3063 will use them. So if the previous insn
3064 exists to set the CC's, delete it
3065 (unless it performs auto-increments, etc.). */
3068 {
3072 else
3073 /* Otherwise, show that cc0 won't be used. */
3075 }
3076 }
3079 {
3083 /* Verify that the REG_NOTE is legitimate. */
3088 }
3091 }
3093 /* If all INSN does is set the pc, delete it,
3094 and delete the insn that set the condition codes for it
3095 if that's what the previous thing was. */
3097 static void
3099 {
3104 }
3108 {
3111 {
3117 }
3119 }
3121 /* Return TRUE if there is a NOTE_INSN_SWITCH_TEXT_SECTIONS note in between
3122 BEG and END. */
3124 static bool
3126 {
3132 }
3134 \f
3135 /* Once we have tried two ways to fill a delay slot, make a pass over the
3136 code to try to improve the results and to do such things as more jump
3137 threading. */
3139 static void
3141 {
3145 rtx target_label;
3147 /* Look at every JUMP_INSN and see if we can improve it. */
3149 {
3155 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3156 the next insn, or jumps to a label that is not the last of a
3157 group of consecutive labels. */
3161 {
3163 target_label
3173 {
3176 }
3179 {
3183 }
3185 /* See if this jump conditionally branches around an unconditional
3186 jump. If so, invert this jump and point it to the target of the
3187 second jump. Check if it's possible on the target. */
3190 && target_label
3195 {
3198 /* Be careful how we do this to avoid deleting code or
3199 labels that are momentarily dead. See similar optimization
3200 in jump.c.
3202 We also need to ensure we properly handle the case when
3203 invert_jump fails. */
3210 {
3213 }
3222 }
3223 }
3225 /* If this is an unconditional jump and the previous insn is a
3226 conditional jump, try reversing the condition of the previous
3227 insn and swapping our targets. The next pass might be able to
3228 fill the slots.
3230 Don't do this if we expect the conditional branch to be true, because
3231 we would then be making the more common case longer. */
3238 {
3244 }
3246 /* Now look only at cases where we have a filled delay slot. */
3253 /* See if the first insn in the delay slot is redundant with some
3254 previous insn. Remove it from the delay slot if so; then set up
3255 to reprocess this insn. */
3257 {
3263 }
3265 /* See if we have a RETURN insn with a filled delay slot followed
3266 by a RETURN insn with an unfilled a delay slot. If so, we can delete
3267 the first RETURN (but not its delay insn). This gives the same
3268 effect in fewer instructions.
3270 Only do so if optimizing for size since this results in slower, but
3271 smaller code. */
3274 && next
3277 {
3281 /* Delete the RETURN and just execute the delay list insns.
3283 We do this by deleting the INSN containing the SEQUENCE, then
3284 re-emitting the insns separately, and then deleting the RETURN.
3285 This allows the count of the jump target to be properly
3286 decremented.
3288 Note that we need to change the INSN_UID of the re-emitted insns
3289 since it is used to hash the insns for mark_target_live_regs and
3290 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3292 Clear the from target bit, since these insns are no longer
3293 in delay slots. */
3306 }
3308 /* Now look only at the cases where we have a filled JUMP_INSN. */
3319 /* If this jump goes to another unconditional jump, thread it, but
3320 don't convert a jump into a RETURN here. */
3322 delay_jump_insn,
3329 {
3334 }
3336 /* If the first insn at TARGET_LABEL is redundant with a previous
3337 insn, redirect the jump to the following insn and process again.
3338 We use next_real_nondebug_insn instead of next_active_insn so we
3339 don't skip USE-markers, or we'll end up with incorrect
3340 liveness info. */
3345 {
3346 /* Figure out where to emit the special USE insn so we don't
3347 later incorrectly compute register live/death info. */
3353 {
3354 /* Insert the special USE insn and update dataflow info.
3355 We know "trial" is an insn here as it is the output of
3356 next_real_nondebug_insn () above. */
3359 /* Now emit a label before the special USE insn, and
3360 redirect our jump to the new label. */
3365 }
3366 }
3368 /* Similarly, if it is an unconditional jump with one insn in its
3369 delay list and that insn is redundant, thread the jump. */
3377 {
3385 {
3390 }
3391 }
3393 /* See if we have a simple (conditional) jump that is useless. */
3399 /* If the last insn in the delay slot sets CC0 for some insn,
3400 various code assumes that it is in a delay slot. We could
3401 put it back where it belonged and delete the register notes,
3402 but it doesn't seem worthwhile in this uncommon case. */
3403 && (!HAVE_cc0
3406 {
3410 /* All this insn does is execute its delay list and jump to the
3411 following insn. So delete the jump and just execute the delay
3412 list insns.
3414 We do this by deleting the INSN containing the SEQUENCE, then
3415 re-emitting the insns separately, and then deleting the jump.
3416 This allows the count of the jump target to be properly
3417 decremented.
3419 Note that we need to change the INSN_UID of the re-emitted insns
3420 since it is used to hash the insns for mark_target_live_regs and
3421 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3423 Clear the from target bit, since these insns are no longer
3424 in delay slots. */
3437 }
3439 /* See if this is an unconditional jump around a single insn which is
3440 identical to the one in its delay slot. In this case, we can just
3441 delete the branch and the insn in its delay slot. */
3447 {
3450 }
3452 /* See if this jump (with its delay slots) conditionally branches
3453 around an unconditional jump (without delay slots). If so, invert
3454 this jump and point it to the target of the second jump. We cannot
3455 do this for annulled jumps, though. Again, don't convert a jump to
3456 a RETURN here. */
3463 {
3470 /* find_end_label can generate a new label. Check this first. */
3475 {
3476 /* Be careful how we do this to avoid deleting code or labels
3477 that are momentarily dead. See similar optimization in
3478 jump.c */
3483 {
3486 /* Must update the INSN_FROM_TARGET_P bits now that
3487 the branch is reversed, so that mark_target_live_regs
3488 will handle the delay slot insn correctly. */
3490 {
3493 }
3497 }
3502 }
3503 }
3505 /* If we own the thread opposite the way this insn branches, see if we
3506 can merge its delay slots with following insns. */
3515 /* If we get here, we haven't deleted INSN. But we may have deleted
3516 NEXT, so recompute it. */
3518 }
3519 }
3520 \f
3522 /* Look for filled jumps to the end of function label. We can try to convert
3523 them into RETURN insns if the insns in the delay slot are valid for the
3524 RETURN as well. */
3526 static void
3528 {
3535 /* See if there is a RETURN insn in the function other than the one we
3536 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
3537 into a RETURN to jump to it. */
3540 {
3544 else
3547 }
3549 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
3550 was equal to END_OF_FUNCTION_LABEL. */
3556 /* Clear the list of insns to fill so we can use it. */
3560 {
3564 /* Only look at filled JUMP_INSNs that go to the end of function
3565 label. */
3578 {
3581 }
3583 {
3586 }
3587 else
3592 /* If we can't make the jump into a RETURN, try to redirect it to the best
3593 RETURN and go on to the next insn. */
3595 {
3596 /* Make sure redirecting the jump will not invalidate the delay
3597 slot insns. */
3601 }
3603 /* See if this RETURN can accept the insns current in its delay slot.
3604 It can if it has more or an equal number of slots and the contents
3605 of each is valid. */
3610 {
3613 #if ANNUL_IFFALSE_SLOTS
3618 #endif
3619 #if ANNUL_IFTRUE_SLOTS
3624 #endif
3628 }
3629 else
3635 /* We have to do something with this insn. If it is an unconditional
3636 RETURN, delete the SEQUENCE and output the individual insns,
3637 followed by the RETURN. Then set things up so we try to find
3638 insns for its delay slots, if it needs some. */
3640 {
3652 }
3653 else
3654 /* It is probably more efficient to keep this with its current
3655 delay slot as a branch to a RETURN. */
3657 }
3659 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
3660 new delay slots we have created. */
3669 }
3670 \f
3671 /* Try to find insns to place in delay slots. */
3673 static void
3675 {
3680 /* If the current function has no insns other than the prologue and
3681 epilogue, then do not try to fill any delay slots. */
3685 /* Find the highest INSN_UID and allocate and initialize our map from
3686 INSN_UID's to position in code. */
3688 {
3694 }
3700 /* Initialize the list of insns that need filling. */
3702 {
3705 }
3708 {
3709 rtx target;
3711 /* Skip vector tables. We can't get attributes for them. */
3722 /* Ensure all jumps go to the last of a set of consecutive labels. */
3729 }
3733 /* Show we haven't computed an end-of-function label yet. */
3736 /* Initialize the statistics for this function. */
3740 /* Now do the delay slot filling. Try everything twice in case earlier
3741 changes make more slots fillable. */
3745 reorg_pass_number++)
3746 {
3752 }
3754 /* If we made an end of function label, indicate that it is now
3755 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
3756 If it is now unused, delete it. */
3770 /* Delete any USE insns made by update_block; subsequent passes don't need
3771 them or know how to deal with them. */
3773 {
3779 }
3783 /* It is not clear why the line below is needed, but it does seem to be. */
3787 {
3794 reorg_pass_number++)
3795 {
3798 {
3807 {
3813 }
3815 }
3816 }
3820 {
3826 {
3828 {
3829 rtx control;
3836 else
3838 }
3841 }
3842 }
3846 {
3848 {
3853 }
3854 }
3858 {
3862 {
3864 {
3869 }
3870 }
3872 }
3875 }
3878 {
3881 }
3886 }
3887 \f
3888 /* Run delay slot optimization. */
3889 static unsigned int
3891 {
3896 }
3901 {
3911 };
3914 {
3918 {}
3920 /* opt_pass methods: */
3923 {
3925 }
3929 bool
3931 {
3932 /* At -O0 dataflow info isn't updated after RA. */
3937 }
3941 rtl_opt_pass *
3943 {
3945 }
3947 /* Machine dependent reorg pass. */
3952 {
3962 };
3965 {
3969 {}
3971 /* opt_pass methods: */
3973 {
3975 }
3978 {
3981 }
3987 rtl_opt_pass *
3989 {
3991 }