1 ;; Predicate definitions for Synopsys DesignWare ARC.
2 ;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_predicate "dest_reg_operand"
21 (match_code "reg,subreg")
25 if (GET_CODE (op0) == SUBREG)
26 op0 = SUBREG_REG (op0);
27 if (REG_P (op0) && REGNO (op0) < FIRST_PSEUDO_REGISTER
28 && TEST_HARD_REG_BIT (reg_class_contents[ALL_CORE_REGS],
30 && !TEST_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS],
33 return register_operand (op, mode);
36 (define_predicate "mpy_dest_reg_operand"
37 (match_code "reg,subreg")
41 if (GET_CODE (op0) == SUBREG)
42 op0 = SUBREG_REG (op0);
43 if (REG_P (op0) && REGNO (op0) < FIRST_PSEUDO_REGISTER
44 && TEST_HARD_REG_BIT (reg_class_contents[ALL_CORE_REGS],
46 /* Make sure the destination register is not LP_COUNT. */
47 && !TEST_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS],
50 return register_operand (op, mode);
54 ;; Returns 1 if OP is a symbol reference.
55 (define_predicate "symbolic_operand"
56 (match_code "symbol_ref, label_ref, const")
59 ;; Acceptable arguments to the call insn.
60 (define_predicate "call_address_operand"
61 (ior (match_code "const_int, reg")
62 (match_operand 0 "symbolic_operand")
63 (match_test "CONSTANT_P (op)
64 && arc_legitimate_constant_p (VOIDmode, op)"))
67 (define_predicate "call_operand"
68 (and (match_code "mem")
69 (match_test "call_address_operand (XEXP (op, 0), mode)"))
72 ;; Return true if OP is a unsigned 6-bit immediate (u6) value.
73 (define_predicate "u6_immediate_operand"
74 (and (match_code "const_int")
75 (match_test "UNSIGNED_INT6 (INTVAL (op))"))
78 ;; Return true if OP is a short immediate (shimm) value.
79 (define_predicate "short_immediate_operand"
80 (and (match_code "const_int")
81 (match_test "SMALL_INT (INTVAL (op))"))
84 (define_predicate "p2_immediate_operand"
85 (and (match_code "const_int")
86 (match_test "((INTVAL (op) - 1) & INTVAL (op)) == 0")
87 (match_test "INTVAL (op)"))
90 ;; Return true if OP will require a long immediate (limm) value.
91 ;; This is currently only used when calculating length attributes.
92 (define_predicate "long_immediate_operand"
93 (match_code "symbol_ref, label_ref, const, const_double, const_int")
95 switch (GET_CODE (op))
102 return !SIGNED_INT12 (INTVAL (op));
104 /* These can happen because large unsigned 32 bit constants are
105 represented this way (the multiplication patterns can cause these
106 to be generated). They also occur for SFmode values. */
115 ;; Return true if OP is a MEM that when used as a load or store address will
116 ;; require an 8 byte insn.
117 ;; Load and store instructions don't allow the same possibilities but they're
118 ;; similar enough that this one function will do.
119 ;; This is currently only used when calculating length attributes. */
120 (define_predicate "long_immediate_loadstore_operand"
123 int size = GET_MODE_SIZE (GET_MODE (op));
126 if (TARGET_NPS_CMEM && cmem_address (op, SImode))
128 switch (GET_CODE (op))
135 /* This must be handled as "st c,[limm]". Ditto for load.
136 Technically, the assembler could translate some possibilities to
137 "st c,[limm/2 + limm/2]" if limm/2 will fit in a shimm, but we don't
138 assume that it does. */
141 /* These can happen because large unsigned 32 bit constants are
142 represented this way (the multiplication patterns can cause these
143 to be generated). They also occur for SFmode values. */
149 rtx x = XEXP (op, 1);
151 if ((GET_CODE (XEXP (op, 0)) == MULT)
152 && REG_P (XEXP (XEXP (op, 0), 0))
156 if (GET_CODE (x) == CONST)
159 if (GET_CODE (x) == PLUS)
163 return (!SMALL_INT (INTVAL (x))
164 && (size <= 1 || size > 4
165 || (INTVAL (x) & (size - 1)) != 0
166 || !SMALL_INT (INTVAL (x) / size)));
167 else if (GET_CODE (x) == SYMBOL_REF)
168 return TARGET_NO_SDATA_SET || !SYMBOL_REF_SMALL_P (x);
178 ;; Return true if OP is any of R0-R3,R12-R15 for ARCompact 16-bit
180 (define_predicate "compact_register_operand"
181 (match_code "reg, subreg")
183 if ((GET_MODE (op) != mode) && (mode != VOIDmode))
186 return (GET_CODE (op) == REG)
187 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
188 || COMPACT_GP_REG_P (REGNO (op))) ;
192 (define_predicate "compact_hreg_operand"
193 (match_code "reg, subreg")
195 if ((GET_MODE (op) != mode) && (mode != VOIDmode))
198 return (GET_CODE (op) == REG)
199 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
200 || (TARGET_V2 && REGNO (op) <= 31 && REGNO (op) != 30)
205 ;; Return true if OP is an acceptable memory operand for ARCompact
206 ;; 16-bit store instructions
207 (define_predicate "compact_store_memory_operand"
210 rtx addr, plus0, plus1;
213 if (mode == VOIDmode)
214 mode = GET_MODE (op);
216 /* .di instructions have no 16-bit form. */
217 if (MEM_VOLATILE_P (op) && !TARGET_VOLATILE_CACHE_SET)
220 size = GET_MODE_SIZE (mode);
222 /* dword operations really put out 2 instructions, so eliminate them. */
223 if (size > UNITS_PER_WORD)
226 /* Decode the address now. */
228 switch (GET_CODE (addr))
231 return (REGNO (addr) >= FIRST_PSEUDO_REGISTER
232 || COMPACT_GP_REG_P (REGNO (addr))
233 || (SP_REG_P (REGNO (addr)) && (size != 2)));
234 /* stw_s does not support SP as a parameter. */
236 plus0 = XEXP (addr, 0);
237 plus1 = XEXP (addr, 1);
239 if ((GET_CODE (plus0) == REG)
240 && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
241 || COMPACT_GP_REG_P (REGNO (plus0)))
242 && (GET_CODE (plus1) == CONST_INT))
244 off = INTVAL (plus1);
246 /* Negative offset is not supported in 16-bit load/store insns. */
255 return ((off < 64) && (off % 2 == 0));
257 return ((off < 128) && (off % 4 == 0));
261 if ((GET_CODE (plus0) == REG)
262 && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
263 || SP_REG_P (REGNO (plus0)))
264 && (GET_CODE (plus1) == CONST_INT))
266 off = INTVAL (plus1);
268 return ((size != 2) && (off >= 0 && off < 128) && (off % 4 == 0));
277 ;; Return true if OP is an acceptable argument for a single word
279 (define_predicate "move_src_operand"
280 (match_code "symbol_ref, label_ref, const, const_int, const_double, reg, subreg, mem")
282 switch (GET_CODE (op))
285 if (SYMBOL_REF_TLS_MODEL (op))
291 return arc_legitimate_constant_p (mode, op);
293 return (LARGE_INT (INTVAL (op)));
295 /* We can handle DImode integer constants in SImode if the value
296 (signed or unsigned) will fit in 32 bits. This is needed because
297 large unsigned 32 bit constants are represented as CONST_DOUBLEs. */
299 return arc_double_limm_p (op);
300 /* We can handle 32 bit floating point constants. */
302 return GET_MODE (op) == SFmode;
305 return register_operand (op, mode);
307 /* (subreg (mem ...) ...) can occur here if the inner part was once a
308 pseudo-reg and is now a stack slot. */
309 if (GET_CODE (SUBREG_REG (op)) == MEM)
310 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
312 return register_operand (op, mode);
314 return address_operand (XEXP (op, 0), mode);
321 ;; Return true if OP is an acceptable argument for a double word
323 (define_predicate "move_double_src_operand"
324 (match_code "reg, subreg, mem, const_int, const_double")
326 switch (GET_CODE (op))
329 return register_operand (op, mode);
331 /* (subreg (mem ...) ...) can occur here if the inner part was once a
332 pseudo-reg and is now a stack slot. */
333 if (GET_CODE (SUBREG_REG (op)) == MEM)
334 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
336 return register_operand (op, mode);
338 return address_operand (XEXP (op, 0), mode);
348 ;; Return true if OP is an acceptable argument for a move destination.
349 (define_predicate "move_dest_operand"
350 (match_code "reg, subreg, mem")
352 switch (GET_CODE (op))
355 /* Program Counter register cannot be the target of a move. It is
356 a readonly register. */
357 if (REGNO (op) == PROGRAM_COUNTER_REGNO)
359 else if (TARGET_MULMAC_32BY16_SET
360 && (REGNO (op) == 56 || REGNO(op) == 57))
362 else if (TARGET_MUL64_SET
363 && (REGNO (op) == 57 || REGNO(op) == 58 || REGNO(op) == 59 ))
365 else if (REGNO (op) == LP_COUNT)
368 return dest_reg_operand (op, mode);
370 /* (subreg (mem ...) ...) can occur here if the inner part was once a
371 pseudo-reg and is now a stack slot. */
372 if (GET_CODE (SUBREG_REG (op)) == MEM)
373 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
375 return dest_reg_operand (op, mode);
378 rtx addr = XEXP (op, 0);
380 if (GET_CODE (addr) == PLUS
381 && (GET_CODE (XEXP (addr, 0)) == MULT
382 || (!CONST_INT_P (XEXP (addr, 1))
383 && (TARGET_NO_SDATA_SET
384 || GET_CODE (XEXP (addr, 1)) != SYMBOL_REF
385 || !SYMBOL_REF_SMALL_P (XEXP (addr, 1))))))
387 if ((GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY)
388 && (GET_CODE (XEXP (addr, 1)) != PLUS
389 || !CONST_INT_P (XEXP (XEXP (addr, 1), 1))))
391 /* CONST_INT / CONST_DOUBLE is fine, but the PIC CONST ([..] UNSPEC))
392 constructs are effectively indexed. */
396 while (GET_CODE (ad0) == PLUS)
398 if (GET_CODE (ad0) == CONST || GET_CODE (ad0) == UNSPEC)
401 return address_operand (addr, mode);
410 ;; Return true if OP is a non-volatile non-immediate operand.
411 ;; Volatile memory refs require a special "cache-bypass" instruction
412 ;; and only the standard movXX patterns are set up to handle them.
413 (define_predicate "nonvol_nonimm_operand"
414 (and (match_code "subreg, reg, mem")
415 (match_test "(GET_CODE (op) != MEM || !MEM_VOLATILE_P (op)) && nonimmediate_operand (op, mode)"))
418 ;; Return 1 if OP is a comparison operator valid for the mode of CC.
419 ;; This allows the use of MATCH_OPERATOR to recognize all the branch insns.
421 (define_predicate "proper_comparison_operator"
422 (match_code "eq, ne, le, lt, ge, gt, leu, ltu, geu, gtu, unordered, ordered, uneq, unge, ungt, unle, unlt, ltgt")
424 enum rtx_code code = GET_CODE (op);
426 if (!COMPARISON_P (op))
429 /* After generic flag-setting insns, we can use eq / ne / pl / mi / pnz .
430 There are some creative uses for hi / ls after shifts, but these are
431 hard to understand for the compiler and could be at best the target of
433 switch (GET_MODE (XEXP (op, 0)))
436 return (code == EQ || code == NE || code == GE || code == LT
439 return code == EQ || code == NE;
441 return code == LTU || code == GEU;
443 return code == GT || code == UNLE;
445 return code == GE || code == UNLT;
446 case E_CC_FP_ORDmode:
447 return code == ORDERED || code == UNORDERED;
448 case E_CC_FP_UNEQmode:
449 return code == UNEQ || code == LTGT;
451 return (code == EQ || code == NE || code == UNEQ || code == LTGT
452 || code == ORDERED || code == UNORDERED);
456 case E_CC_FPU_UNEQmode:
460 case E_SImode: /* Used for BRcc. */
463 case E_QImode: case E_HImode: case E_DImode: case E_SFmode: case E_DFmode:
472 (define_predicate "equality_comparison_operator"
473 (match_code "eq, ne"))
475 (define_predicate "ge_lt_comparison_operator"
476 (match_code "ge, lt"))
478 (define_predicate "brcc_nolimm_operator"
479 (ior (match_test "REG_P (XEXP (op, 1))")
480 (and (match_code "eq, ne, lt, ge, ltu, geu")
481 (match_test "CONST_INT_P (XEXP (op, 1))")
482 (match_test "u6_immediate_operand (XEXP (op, 1), SImode)"))
483 (and (match_code "le, gt, leu, gtu")
484 (match_test "CONST_INT_P (XEXP (op, 1))")
485 (match_test "UNSIGNED_INT6 (INTVAL (XEXP (op, 1)) + 1)"))))
487 ;; Return TRUE if this is the condition code register, if we aren't given
488 ;; a mode, accept any CCmode register
489 (define_special_predicate "cc_register"
492 if (mode == VOIDmode)
494 mode = GET_MODE (op);
495 if (GET_MODE_CLASS (mode) != MODE_CC)
499 if (mode == GET_MODE (op) && GET_CODE (op) == REG && REGNO (op) == CC_REG)
505 ;; Return TRUE if this is the condition code register; if we aren't given
506 ;; a mode, accept any CCmode register. If we are given a mode, accept
507 ;; modes that set a subset of flags.
508 (define_special_predicate "cc_set_register"
511 machine_mode rmode = GET_MODE (op);
513 if (mode == VOIDmode)
516 if (GET_MODE_CLASS (mode) != MODE_CC)
520 if (REGNO (op) != 61)
523 || (mode == CC_ZNmode && rmode == CC_Zmode)
524 || (mode == CCmode && rmode == CC_Zmode)
525 || (mode == CCmode && rmode == CC_ZNmode)
526 || (mode == CCmode && rmode == CC_Cmode))
532 ; Accept CC_REG in modes which provide the flags needed for MODE. */
533 (define_special_predicate "cc_use_register"
536 if (REGNO (op) != CC_REG)
538 if (GET_MODE (op) == mode)
543 if (GET_MODE (op) == CC_ZNmode)
546 case E_CC_ZNmode: case E_CC_Cmode:
547 return GET_MODE (op) == CCmode;
553 (define_special_predicate "zn_compare_operator"
554 (match_code "compare")
556 return GET_MODE (op) == CC_ZNmode || GET_MODE (op) == CC_Zmode;
559 ;; Return true if OP is a shift operator.
560 (define_predicate "shift_operator"
561 (match_code "ashiftrt, lshiftrt, ashift")
564 ;; Return true if OP is a left shift operator that can be implemented in
565 ;; four insn words or less without a barrel shifter or multiplier.
566 (define_predicate "shiftl4_operator"
567 (and (match_code "ashift")
568 (match_test "const_int_operand (XEXP (op, 1), VOIDmode) ")
569 (match_test "UINTVAL (XEXP (op, 1)) <= 9U
570 || INTVAL (XEXP (op, 1)) == 29
571 || INTVAL (XEXP (op, 1)) == 30
572 || INTVAL (XEXP (op, 1)) == 31")))
574 ;; Return true if OP is a right shift operator that can be implemented in
575 ;; four insn words or less without a barrel shifter or multiplier.
576 (define_predicate "shiftr4_operator"
577 (and (match_code "ashiftrt, lshiftrt")
578 (match_test "const_int_operand (XEXP (op, 1), VOIDmode) ")
579 (match_test "UINTVAL (XEXP (op, 1)) <= 4U
580 || INTVAL (XEXP (op, 1)) == 30
581 || INTVAL (XEXP (op, 1)) == 31")))
583 ;; Return true if OP is a shift operator that can be implemented in
584 ;; four insn words or less without a barrel shifter or multiplier.
585 (define_predicate "shift4_operator"
586 (ior (match_operand 0 "shiftl4_operator")
587 (match_operand 0 "shiftr4_operator")))
589 (define_predicate "mult_operator"
590 (and (match_code "mult") (match_test "TARGET_MPY"))
593 (define_predicate "commutative_operator"
594 (ior (match_code "plus,ior,xor,and")
595 (match_operand 0 "mult_operator")
596 (and (match_code "ss_plus")
597 (match_test "TARGET_ARC700 || TARGET_EA_SET")))
600 (define_predicate "commutative_operator_sans_mult"
601 (ior (match_code "plus,ior,xor,and")
602 (and (match_code "ss_plus")
603 (match_test "TARGET_ARC700 || TARGET_EA_SET")))
606 (define_predicate "noncommutative_operator"
607 (ior (match_code "minus,ashift,ashiftrt,lshiftrt,rotatert")
608 (and (match_code "ss_minus")
609 (match_test "TARGET_ARC700 || TARGET_EA_SET")))
612 (define_predicate "unary_operator"
613 (ior (match_code "abs,neg,not,sign_extend,zero_extend")
614 (and (ior (match_code "ss_neg")
615 (and (match_code "ss_truncate")
616 (match_test "GET_MODE (XEXP (op, 0)) == HImode")))
617 (match_test "TARGET_ARC700 || TARGET_EA_SET")))
620 (define_predicate "_1_2_3_operand"
621 (and (match_code "const_int")
622 (match_test "INTVAL (op) == 1 || INTVAL (op) == 2 || INTVAL (op) == 3"))
625 (define_predicate "_2_4_8_operand"
626 (and (match_code "const_int")
627 (match_test "INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8"))
630 (define_predicate "arc_double_register_operand"
633 if ((GET_MODE (op) != mode) && (mode != VOIDmode))
636 return (GET_CODE (op) == REG
637 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
638 || REGNO_REG_CLASS (REGNO (op)) == DOUBLE_REGS));
641 (define_predicate "shouldbe_register_operand"
642 (match_code "reg,subreg,mem")
644 return ((reload_in_progress || reload_completed)
645 ? general_operand : register_operand) (op, mode);
648 (define_predicate "vector_register_operand"
651 if ((GET_MODE (op) != mode) && (mode != VOIDmode))
654 return (GET_CODE (op) == REG
655 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
656 || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS));
659 (define_predicate "vector_register_or_memory_operand"
660 ( ior (match_code "reg")
663 if ((GET_MODE (op) != mode) && (mode != VOIDmode))
666 if ((GET_CODE (op) == MEM)
667 && (mode == V8HImode)
668 && GET_CODE (XEXP (op,0)) == REG)
671 return (GET_CODE (op) == REG
672 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
673 || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS));
676 (define_predicate "arc_dpfp_operator"
677 (match_code "plus, mult,minus")
680 (define_predicate "arc_simd_dma_register_operand"
683 if ((GET_MODE (op) != mode) && (mode != VOIDmode))
686 return (GET_CODE (op) == REG
687 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
688 || REGNO_REG_CLASS (REGNO (op)) == SIMD_DMA_CONFIG_REGS));
691 (define_predicate "acc1_operand"
692 (and (match_code "reg")
693 (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 56 : 57)")))
695 (define_predicate "acc2_operand"
696 (and (match_code "reg")
697 (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 57 : 56)")))
699 (define_predicate "mlo_operand"
700 (and (match_code "reg")
701 (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 59 : 58)")))
703 (define_predicate "mhi_operand"
704 (and (match_code "reg")
705 (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 58 : 59)")))
707 (define_predicate "accl_operand"
708 (and (match_code "reg")
709 (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 59 : 58)")
710 (match_test "TARGET_V2")))
712 ; Unfortunately, we can not allow a const_int_operand before reload, because
713 ; reload needs a non-void mode to guide it how to reload the inside of a
715 (define_predicate "extend_operand"
716 (ior (match_operand 0 "register_operand")
717 (and (match_operand 0 "immediate_operand")
718 (ior (not (match_operand 0 "const_int_operand"))
719 (match_test "reload_in_progress || reload_completed")))))
721 (define_predicate "millicode_store_operation"
722 (match_code "parallel")
724 return arc_check_millicode (op, 0, 0);
727 (define_predicate "millicode_load_operation"
728 (match_code "parallel")
730 return arc_check_millicode (op, 2, 2);
733 (define_predicate "millicode_load_clob_operation"
734 (match_code "parallel")
736 return arc_check_millicode (op, 0, 1);
739 (define_special_predicate "immediate_usidi_operand"
741 (match_code "const_int")
742 (match_test "INTVAL (op) >= 0")
743 (and (match_test "const_double_operand (op, mode)")
744 (match_test "CONST_DOUBLE_HIGH (op) == 0"))))
746 (define_predicate "short_const_int_operand"
747 (and (match_operand 0 "const_int_operand")
748 (match_test "satisfies_constraint_C16 (op)")))
750 (define_predicate "mem_noofs_operand"
751 (and (match_code "mem")
752 (match_code "reg" "0")))
754 (define_predicate "any_mem_operand"
757 ; Special predicate to match even-odd double register pair
758 (define_predicate "even_register_operand"
761 if ((GET_MODE (op) != mode) && (mode != VOIDmode))
764 return (REG_P (op) && ((REGNO (op) >= FIRST_PSEUDO_REGISTER)
765 || ((REGNO (op) & 1) == 0)));
768 (define_predicate "double_register_operand"
769 (ior (match_test "even_register_operand (op, mode)")
770 (match_test "arc_double_register_operand (op, mode)")))
772 (define_predicate "cmem_address_0"
773 (and (match_code "symbol_ref")
774 (match_test "SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_CMEM")))
776 (define_predicate "cmem_address_1"
777 (and (match_code "plus")
778 (match_test "cmem_address_0 (XEXP (op, 0), SImode)")))
780 (define_predicate "cmem_address_2"
781 (and (match_code "const")
782 (match_test "cmem_address_1 (XEXP (op, 0), SImode)")))
784 (define_predicate "cmem_address"
785 (ior (match_operand:SI 0 "cmem_address_0")
786 (match_operand:SI 0 "cmem_address_1")
787 (match_operand:SI 0 "cmem_address_2")))
789 (define_predicate "short_unsigned_const_operand"
790 (and (match_code "const_int")
791 (match_test "satisfies_constraint_J16 (op)")))
793 (define_predicate "arc_short_operand"
794 (ior (match_test "register_operand (op, mode)")
795 (match_test "short_unsigned_const_operand (op, mode)")))