1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 static int bb_reload_num
;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn
*curr_insn
;
144 static rtx curr_insn_set
;
145 static basic_block curr_bb
;
146 static lra_insn_recog_data_t curr_id
;
147 static struct lra_static_insn_data
*curr_static_id
;
148 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
156 /* Start numbers for new registers and insns at the current constraints
158 static int new_regno_start
;
159 static int new_insn_uid_start
;
161 /* If LOC is nonnull, strip any outer subreg from it. */
163 strip_subreg (rtx
*loc
)
165 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
171 get_try_hard_regno (int regno
)
174 enum reg_class rclass
;
176 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
177 hard_regno
= lra_get_regno_hard_regno (regno
);
180 rclass
= lra_get_allocno_class (regno
);
181 if (rclass
== NO_REGS
)
183 return ira_class_hard_regs
[rclass
][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
191 get_hard_regno (rtx x
, bool final_p
)
198 reg
= SUBREG_REG (x
);
201 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
202 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
206 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
208 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
209 SUBREG_BYTE (x
), GET_MODE (x
));
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno
)
222 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
223 hard_regno
= lra_get_regno_hard_regno (regno
);
226 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
227 return REGNO_REG_CLASS (hard_regno
);
229 if (regno
>= new_regno_start
)
230 return lra_get_allocno_class (regno
);
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
243 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
245 enum reg_class rclass
, common_class
;
246 machine_mode reg_mode
;
247 int class_size
, hard_regno
, nregs
, i
, j
;
248 int regno
= REGNO (reg
);
250 if (new_class
!= NULL
)
251 *new_class
= NO_REGS
;
252 if (regno
< FIRST_PSEUDO_REGISTER
)
255 rtx
*final_loc
= &final_reg
;
257 lra_eliminate_reg_if_possible (final_loc
);
258 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
260 reg_mode
= GET_MODE (reg
);
261 rclass
= get_reg_class (regno
);
262 if (regno
< new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn
) >= new_insn_uid_start
269 && curr_insn_set
!= NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set
))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
272 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
278 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
279 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
280 lra_no_alloc_regs
)));
283 common_class
= ira_reg_class_subset
[rclass
][cl
];
284 if (new_class
!= NULL
)
285 *new_class
= common_class
;
286 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
289 /* Check that there are enough allocatable regs. */
290 class_size
= ira_class_hard_regs_num
[common_class
];
291 for (i
= 0; i
< class_size
; i
++)
293 hard_regno
= ira_class_hard_regs
[common_class
][i
];
294 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
297 for (j
= 0; j
< nregs
; j
++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
299 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
309 /* Return true if REGNO satisfies a memory constraint. */
313 return get_reg_class (regno
) == NO_REGS
;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
321 rtx addr
, addr_space_t as
)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as
));
325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
331 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
336 /* Temporarily eliminates registers in an address (for the lifetime of
338 class address_eliminator
{
340 address_eliminator (struct address_info
*ad
);
341 ~address_eliminator ();
344 struct address_info
*m_ad
;
352 address_eliminator::address_eliminator (struct address_info
*ad
)
354 m_base_loc (strip_subreg (ad
->base_term
)),
355 m_base_reg (NULL_RTX
),
356 m_index_loc (strip_subreg (ad
->index_term
)),
357 m_index_reg (NULL_RTX
)
359 if (m_base_loc
!= NULL
)
361 m_base_reg
= *m_base_loc
;
362 lra_eliminate_reg_if_possible (m_base_loc
);
363 if (m_ad
->base_term2
!= NULL
)
364 *m_ad
->base_term2
= *m_ad
->base_term
;
366 if (m_index_loc
!= NULL
)
368 m_index_reg
= *m_index_loc
;
369 lra_eliminate_reg_if_possible (m_index_loc
);
373 address_eliminator::~address_eliminator ()
375 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
377 *m_base_loc
= m_base_reg
;
378 if (m_ad
->base_term2
!= NULL
)
379 *m_ad
->base_term2
= *m_ad
->base_term
;
381 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
382 *m_index_loc
= m_index_reg
;
385 /* Return true if the eliminated form of AD is a legitimate target address. */
387 valid_address_p (struct address_info
*ad
)
389 address_eliminator
eliminator (ad
);
390 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
396 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
398 struct address_info ad
;
400 decompose_mem_address (&ad
, op
);
401 address_eliminator
eliminator (&ad
);
402 return constraint_satisfied_p (op
, constraint
);
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
408 satisfies_address_constraint_p (struct address_info
*ad
,
409 enum constraint_num constraint
)
411 address_eliminator
eliminator (ad
);
412 return constraint_satisfied_p (*ad
->outer
, constraint
);
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
418 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
420 struct address_info ad
;
422 decompose_lea_address (&ad
, &op
);
423 return satisfies_address_constraint_p (&ad
, constraint
);
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
430 lra_init_equiv (void)
432 ira_expand_reg_equiv ();
433 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
437 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
438 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
439 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
440 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
444 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
450 update_equiv (int regno
)
454 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
455 ira_reg_equiv
[regno
].memory
456 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
458 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].invariant
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
472 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv
[regno
].defined_p
474 || ! ira_reg_equiv
[regno
].profitable_p
475 || lra_get_regno_hard_regno (regno
) >= 0)
477 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
479 if (targetm
.cannot_substitute_mem_equiv_p (res
))
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
501 false, false, 0, true);
504 /* Set up curr_operand_mode. */
506 init_curr_operand_mode (void)
508 int nop
= curr_static_id
->n_operands
;
509 for (int i
= 0; i
< nop
; i
++)
511 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
512 if (mode
== VOIDmode
)
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
519 mode
= curr_static_id
->operand
[i
].mode
;
521 curr_operand_mode
[i
] = mode
;
527 /* The page contains code to reuse input reloads. */
529 /* Structure describes input reload of the current insns. */
532 /* True for input reload of matched operands. */
534 /* Reloaded value. */
536 /* Reload pseudo used. */
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num
;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
546 /* Initiate data concerning reuse of input reloads for the current
549 init_curr_insn_input_reloads (void)
551 curr_insn_input_reloads_num
= 0;
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
562 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
563 enum reg_class rclass
, bool in_subreg_p
,
564 const char *title
, rtx
*result_reg
)
567 enum reg_class new_class
;
568 bool unique_p
= false;
573 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original
))
579 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
581 if (! curr_insn_input_reloads
[i
].match_p
582 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
583 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
585 rtx reg
= curr_insn_input_reloads
[i
].reg
;
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg
) != mode
)
594 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg
)),
595 GET_MODE_SIZE (mode
)))
597 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
598 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
602 if (lra_dump_file
!= NULL
)
604 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
605 dump_value_slim (lra_dump_file
, original
, 1);
607 if (new_class
!= lra_get_allocno_class (regno
))
608 lra_change_class (regno
, new_class
, ", change to", false);
609 if (lra_dump_file
!= NULL
)
610 fprintf (lra_dump_file
, "\n");
613 /* If we have an input reload with a different mode, make sure it
614 will get a different hard reg. */
615 else if (REG_P (original
)
616 && REG_P (curr_insn_input_reloads
[i
].input
)
617 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
618 && (GET_MODE (original
)
619 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
622 *result_reg
= (unique_p
623 ? lra_create_new_reg_with_unique_value
624 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
625 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
626 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
627 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
628 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
634 /* The page contains code to extract memory address parts. */
636 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
638 ok_for_index_p_nonstrict (rtx reg
)
640 unsigned regno
= REGNO (reg
);
642 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
645 /* A version of regno_ok_for_base_p for use here, when all pseudos
646 should count as OK. Arguments as for regno_ok_for_base_p. */
648 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
649 enum rtx_code outer_code
, enum rtx_code index_code
)
651 unsigned regno
= REGNO (reg
);
653 if (regno
>= FIRST_PSEUDO_REGISTER
)
655 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
660 /* The page contains major code to choose the current insn alternative
661 and generate reloads for it. */
663 /* Return the offset from REGNO of the least significant register
666 This function is used to tell whether two registers satisfy
667 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
669 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
670 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
672 lra_constraint_offset (int regno
, machine_mode mode
)
674 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
676 scalar_int_mode int_mode
;
678 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
679 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
680 return hard_regno_nregs (regno
, mode
) - 1;
684 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
685 if they are the same hard reg, and has special hacks for
686 auto-increment and auto-decrement. This is specifically intended for
687 process_alt_operands to use in determining whether two operands
688 match. X is the operand whose number is the lower of the two.
690 It is supposed that X is the output operand and Y is the input
691 operand. Y_HARD_REGNO is the final hard regno of register Y or
692 register in subreg Y as we know it now. Otherwise, it is a
695 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
698 RTX_CODE code
= GET_CODE (x
);
703 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
704 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
708 i
= get_hard_regno (x
, false);
712 if ((j
= y_hard_regno
) < 0)
715 i
+= lra_constraint_offset (i
, GET_MODE (x
));
716 j
+= lra_constraint_offset (j
, GET_MODE (y
));
721 /* If two operands must match, because they are really a single
722 operand of an assembler insn, then two post-increments are invalid
723 because the assembler insn would increment only once. On the
724 other hand, a post-increment matches ordinary indexing if the
725 post-increment is the output operand. */
726 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
727 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
729 /* Two pre-increments are invalid because the assembler insn would
730 increment only once. On the other hand, a pre-increment matches
731 ordinary indexing if the pre-increment is the input operand. */
732 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
733 || GET_CODE (y
) == PRE_MODIFY
)
734 return operands_match_p (x
, XEXP (y
, 0), -1);
738 if (code
== REG
&& REG_P (y
))
739 return REGNO (x
) == REGNO (y
);
741 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
742 && x
== SUBREG_REG (y
))
744 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
745 && SUBREG_REG (x
) == y
)
748 /* Now we have disposed of all the cases in which different rtx
750 if (code
!= GET_CODE (y
))
753 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
754 if (GET_MODE (x
) != GET_MODE (y
))
763 return label_ref_label (x
) == label_ref_label (y
);
765 return XSTR (x
, 0) == XSTR (y
, 0);
771 /* Compare the elements. If any pair of corresponding elements fail
772 to match, return false for the whole things. */
774 fmt
= GET_RTX_FORMAT (code
);
775 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
781 if (XWINT (x
, i
) != XWINT (y
, i
))
786 if (XINT (x
, i
) != XINT (y
, i
))
791 if (maybe_ne (SUBREG_BYTE (x
), SUBREG_BYTE (y
)))
796 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
805 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
807 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
809 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
815 /* It is believed that rtx's at this level will never
816 contain anything but integers and other rtx's, except for
817 within LABEL_REFs and SYMBOL_REFs. */
825 /* True if X is a constant that can be forced into the constant pool.
826 MODE is the mode of the operand, or VOIDmode if not known. */
827 #define CONST_POOL_OK_P(MODE, X) \
828 ((MODE) != VOIDmode \
830 && GET_CODE (X) != HIGH \
831 && GET_MODE_SIZE (MODE).is_constant () \
832 && !targetm.cannot_force_const_mem (MODE, X))
834 /* True if C is a non-empty register class that has too few registers
835 to be safely used as a reload target class. */
836 #define SMALL_REGISTER_CLASS_P(C) \
837 (ira_class_hard_regs_num [(C)] == 1 \
838 || (ira_class_hard_regs_num [(C)] >= 1 \
839 && targetm.class_likely_spilled_p (C)))
841 /* If REG is a reload pseudo, try to make its class satisfying CL. */
843 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
845 enum reg_class rclass
;
847 /* Do not make more accurate class from reloads generated. They are
848 mostly moves with a lot of constraints. Making more accurate
849 class may results in very narrow class and impossibility of find
850 registers for several reloads of one insn. */
851 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
853 if (GET_CODE (reg
) == SUBREG
)
854 reg
= SUBREG_REG (reg
);
855 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
857 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
858 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
861 /* Searches X for any reference to a reg with the same value as REGNO,
862 returning the rtx of the reference found if any. Otherwise,
865 regno_val_use_in (unsigned int regno
, rtx x
)
871 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
874 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
875 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
879 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
882 else if (fmt
[i
] == 'E')
883 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
884 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
891 /* Return true if all current insn non-output operands except INS (it
892 has a negaitve end marker) do not use pseudos with the same value
895 check_conflict_input_operands (int regno
, signed char *ins
)
898 int n_operands
= curr_static_id
->n_operands
;
900 for (int nop
= 0; nop
< n_operands
; nop
++)
901 if (! curr_static_id
->operand
[nop
].is_operator
902 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
904 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
908 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
914 /* Generate reloads for matching OUT and INS (array of input operand
915 numbers with end marker -1) with reg class GOAL_CLASS, considering
916 output operands OUTS (similar array to INS) needing to be in different
917 registers. Add input and output reloads correspondingly to the lists
918 *BEFORE and *AFTER. OUT might be negative. In this case we generate
919 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
920 that the output operand is early clobbered for chosen alternative. */
922 match_reload (signed char out
, signed char *ins
, signed char *outs
,
923 enum reg_class goal_class
, rtx_insn
**before
,
924 rtx_insn
**after
, bool early_clobber_p
)
928 rtx new_in_reg
, new_out_reg
, reg
;
929 machine_mode inmode
, outmode
;
930 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
931 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
933 inmode
= curr_operand_mode
[ins
[0]];
934 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
935 push_to_sequence (*before
);
936 if (inmode
!= outmode
)
938 /* process_alt_operands has already checked that the mode sizes
940 if (partial_subreg_p (outmode
, inmode
))
943 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
945 if (SCALAR_INT_MODE_P (inmode
))
946 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
948 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
949 LRA_SUBREG_P (new_out_reg
) = 1;
950 /* If the input reg is dying here, we can use the same hard
951 register for REG and IN_RTX. We do it only for original
952 pseudos as reload pseudos can die although original
953 pseudos still live where reload pseudos dies. */
954 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
955 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
957 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
958 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
963 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
965 if (SCALAR_INT_MODE_P (outmode
))
966 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
968 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
969 /* NEW_IN_REG is non-paradoxical subreg. We don't want
970 NEW_OUT_REG living above. We add clobber clause for
971 this. This is just a temporary clobber. We can remove
972 it at the end of LRA work. */
973 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
974 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
975 LRA_SUBREG_P (new_in_reg
) = 1;
976 if (GET_CODE (in_rtx
) == SUBREG
)
978 rtx subreg_reg
= SUBREG_REG (in_rtx
);
980 /* If SUBREG_REG is dying here and sub-registers IN_RTX
981 and NEW_IN_REG are similar, we can use the same hard
982 register for REG and SUBREG_REG. */
983 if (REG_P (subreg_reg
)
984 && (int) REGNO (subreg_reg
) < lra_new_regno_start
985 && GET_MODE (subreg_reg
) == outmode
986 && known_eq (SUBREG_BYTE (in_rtx
), SUBREG_BYTE (new_in_reg
))
987 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
988 && (! early_clobber_p
989 || check_conflict_input_operands (REGNO (subreg_reg
),
991 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
997 /* Pseudos have values -- see comments for lra_reg_info.
998 Different pseudos with the same value do not conflict even if
999 they live in the same place. When we create a pseudo we
1000 assign value of original pseudo (if any) from which we
1001 created the new pseudo. If we create the pseudo from the
1002 input pseudo, the new pseudo will have no conflict with the
1003 input pseudo which is wrong when the input pseudo lives after
1004 the insn and as the new pseudo value is changed by the insn
1005 output. Therefore we create the new pseudo from the output
1006 except the case when we have single matched dying input
1009 We cannot reuse the current output register because we might
1010 have a situation like "a <- a op b", where the constraints
1011 force the second input operand ("b") to match the output
1012 operand ("a"). "b" must then be copied into a new register
1013 so that it doesn't clobber the current value of "a".
1015 We can not use the same value if the output pseudo is
1016 early clobbered or the input pseudo is mentioned in the
1017 output, e.g. as an address part in memory, because
1018 output reload will actually extend the pseudo liveness.
1019 We don't care about eliminable hard regs here as we are
1020 interesting only in pseudos. */
1022 /* Matching input's register value is the same as one of the other
1023 output operand. Output operands in a parallel insn must be in
1024 different registers. */
1025 out_conflict
= false;
1028 for (i
= 0; outs
[i
] >= 0; i
++)
1030 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1031 if (REG_P (other_out_rtx
)
1032 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1035 out_conflict
= true;
1041 new_in_reg
= new_out_reg
1042 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1043 && (int) REGNO (in_rtx
) < lra_new_regno_start
1044 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1045 && (! early_clobber_p
1046 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1048 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1050 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1051 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1054 /* In operand can be got from transformations before processing insn
1055 constraints. One example of such transformations is subreg
1056 reloading (see function simplify_operand_subreg). The new
1057 pseudos created by the transformations might have inaccurate
1058 class (ALL_REGS) and we should make their classes more
1060 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1061 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1062 *before
= get_insns ();
1064 /* Add the new pseudo to consider values of subsequent input reload
1066 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1067 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1068 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1069 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1070 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1073 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1074 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1075 *curr_id
->operand_loc
[in
] = new_in_reg
;
1077 lra_update_dups (curr_id
, ins
);
1080 /* See a comment for the input operand above. */
1081 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1082 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1085 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1087 *after
= get_insns ();
1090 *curr_id
->operand_loc
[out
] = new_out_reg
;
1091 lra_update_dup (curr_id
, out
);
1094 /* Return register class which is union of all reg classes in insn
1095 constraint alternative string starting with P. */
1096 static enum reg_class
1097 reg_class_from_constraints (const char *p
)
1100 enum reg_class op_class
= NO_REGS
;
1103 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1110 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1114 enum constraint_num cn
= lookup_constraint (p
);
1115 enum reg_class cl
= reg_class_for_constraint (cn
);
1118 if (insn_extra_address_constraint (cn
))
1120 = (reg_class_subunion
1121 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1122 ADDRESS
, SCRATCH
)]);
1126 op_class
= reg_class_subunion
[op_class
][cl
];
1129 while ((p
+= len
), c
);
1133 /* If OP is a register, return the class of the register as per
1134 get_reg_class, otherwise return NO_REGS. */
1135 static inline enum reg_class
1136 get_op_class (rtx op
)
1138 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1141 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1142 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1143 SUBREG for VAL to make them equal. */
1145 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1147 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1149 /* Usually size of mem_pseudo is greater than val size but in
1150 rare cases it can be less as it can be defined by target
1151 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1154 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1155 GET_CODE (val
) == SUBREG
1156 ? SUBREG_REG (val
) : val
);
1157 LRA_SUBREG_P (val
) = 1;
1161 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1162 LRA_SUBREG_P (mem_pseudo
) = 1;
1165 return to_p
? gen_move_insn (mem_pseudo
, val
)
1166 : gen_move_insn (val
, mem_pseudo
);
1169 /* Process a special case insn (register move), return true if we
1170 don't need to process it anymore. INSN should be a single set
1171 insn. Set up that RTL was changed through CHANGE_P and that hook
1172 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1175 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1178 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1180 enum reg_class dclass
, sclass
, secondary_class
;
1181 secondary_reload_info sri
;
1183 lra_assert (curr_insn_set
!= NULL_RTX
);
1184 dreg
= dest
= SET_DEST (curr_insn_set
);
1185 sreg
= src
= SET_SRC (curr_insn_set
);
1186 if (GET_CODE (dest
) == SUBREG
)
1187 dreg
= SUBREG_REG (dest
);
1188 if (GET_CODE (src
) == SUBREG
)
1189 sreg
= SUBREG_REG (src
);
1190 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1192 sclass
= dclass
= NO_REGS
;
1194 dclass
= get_reg_class (REGNO (dreg
));
1195 gcc_assert (dclass
< LIM_REG_CLASSES
);
1196 if (dclass
== ALL_REGS
)
1197 /* ALL_REGS is used for new pseudos created by transformations
1198 like reload of SUBREG_REG (see function
1199 simplify_operand_subreg). We don't know their class yet. We
1200 should figure out the class from processing the insn
1201 constraints not in this fast path function. Even if ALL_REGS
1202 were a right class for the pseudo, secondary_... hooks usually
1203 are not define for ALL_REGS. */
1206 sclass
= get_reg_class (REGNO (sreg
));
1207 gcc_assert (sclass
< LIM_REG_CLASSES
);
1208 if (sclass
== ALL_REGS
)
1209 /* See comments above. */
1211 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1213 if (targetm
.secondary_memory_needed (GET_MODE (src
), sclass
, dclass
)
1214 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1216 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1221 if (! REG_P (dreg
) || ! REG_P (sreg
))
1223 sri
.prev_sri
= NULL
;
1224 sri
.icode
= CODE_FOR_nothing
;
1226 secondary_class
= NO_REGS
;
1227 /* Set up hard register for a reload pseudo for hook
1228 secondary_reload because some targets just ignore unassigned
1229 pseudos in the hook. */
1230 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1232 dregno
= REGNO (dreg
);
1233 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1237 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1239 sregno
= REGNO (sreg
);
1240 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1244 if (sclass
!= NO_REGS
)
1246 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1247 (reg_class_t
) sclass
,
1248 GET_MODE (src
), &sri
);
1249 if (sclass
== NO_REGS
1250 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1251 && dclass
!= NO_REGS
))
1253 enum reg_class old_sclass
= secondary_class
;
1254 secondary_reload_info old_sri
= sri
;
1256 sri
.prev_sri
= NULL
;
1257 sri
.icode
= CODE_FOR_nothing
;
1260 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1261 (reg_class_t
) dclass
,
1262 GET_MODE (src
), &sri
);
1263 /* Check the target hook consistency. */
1265 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1266 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1267 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1270 reg_renumber
[sregno
] = -1;
1272 reg_renumber
[dregno
] = -1;
1273 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1277 if (secondary_class
!= NO_REGS
)
1278 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1282 if (sri
.icode
== CODE_FOR_nothing
)
1283 lra_emit_move (new_reg
, src
);
1286 enum reg_class scratch_class
;
1288 scratch_class
= (reg_class_from_constraints
1289 (insn_data
[sri
.icode
].operand
[2].constraint
));
1290 scratch_reg
= (lra_create_new_reg_with_unique_value
1291 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1292 scratch_class
, "scratch"));
1293 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1296 before
= get_insns ();
1298 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1299 if (new_reg
!= NULL_RTX
)
1300 SET_SRC (curr_insn_set
) = new_reg
;
1303 if (lra_dump_file
!= NULL
)
1305 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1306 dump_insn_slim (lra_dump_file
, curr_insn
);
1308 lra_set_insn_deleted (curr_insn
);
1314 /* The following data describe the result of process_alt_operands.
1315 The data are used in curr_insn_transform to generate reloads. */
1317 /* The chosen reg classes which should be used for the corresponding
1319 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1320 /* True if the operand should be the same as another operand and that
1321 other operand does not need a reload. */
1322 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1323 /* True if the operand does not need a reload. */
1324 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1325 /* True if the operand can be offsetable memory. */
1326 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1327 /* The number of an operand to which given operand can be matched to. */
1328 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1329 /* The number of elements in the following array. */
1330 static int goal_alt_dont_inherit_ops_num
;
1331 /* Numbers of operands whose reload pseudos should not be inherited. */
1332 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1333 /* True if the insn commutative operands should be swapped. */
1334 static bool goal_alt_swapped
;
1335 /* The chosen insn alternative. */
1336 static int goal_alt_number
;
1338 /* True if the corresponding operand is the result of an equivalence
1340 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1342 /* The following five variables are used to choose the best insn
1343 alternative. They reflect final characteristics of the best
1346 /* Number of necessary reloads and overall cost reflecting the
1347 previous value and other unpleasantness of the best alternative. */
1348 static int best_losers
, best_overall
;
1349 /* Overall number hard registers used for reloads. For example, on
1350 some targets we need 2 general registers to reload DFmode and only
1351 one floating point register. */
1352 static int best_reload_nregs
;
1353 /* Overall number reflecting distances of previous reloading the same
1354 value. The distances are counted from the current BB start. It is
1355 used to improve inheritance chances. */
1356 static int best_reload_sum
;
1358 /* True if the current insn should have no correspondingly input or
1360 static bool no_input_reloads_p
, no_output_reloads_p
;
1362 /* True if we swapped the commutative operands in the current
1364 static int curr_swapped
;
1366 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1367 register of class CL. Add any input reloads to list BEFORE. AFTER
1368 is nonnull if *LOC is an automodified value; handle that case by
1369 adding the required output reloads to list AFTER. Return true if
1370 the RTL was changed.
1372 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1373 register. Return false if the address register is correct. */
1375 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1379 enum reg_class rclass
, new_class
;
1383 bool subreg_p
, before_p
= false;
1385 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1388 reg
= SUBREG_REG (*loc
);
1389 mode
= GET_MODE (reg
);
1391 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1392 between two registers with different classes, but there normally will
1393 be "mov" which transfers element of vector register into the general
1394 register, and this normally will be a subreg which should be reloaded
1395 as a whole. This is particularly likely to be triggered when
1396 -fno-split-wide-types specified. */
1398 || in_class_p (reg
, cl
, &new_class
)
1399 || known_le (GET_MODE_SIZE (mode
), GET_MODE_SIZE (ptr_mode
)))
1400 loc
= &SUBREG_REG (*loc
);
1404 mode
= GET_MODE (reg
);
1409 /* Always reload memory in an address even if the target supports
1411 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1416 regno
= REGNO (reg
);
1417 rclass
= get_reg_class (regno
);
1419 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1421 if (lra_dump_file
!= NULL
)
1423 fprintf (lra_dump_file
,
1424 "Changing pseudo %d in address of insn %u on equiv ",
1425 REGNO (reg
), INSN_UID (curr_insn
));
1426 dump_value_slim (lra_dump_file
, *loc
, 1);
1427 fprintf (lra_dump_file
, "\n");
1429 *loc
= copy_rtx (*loc
);
1431 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1436 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1437 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1440 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1444 lra_change_class (regno
, new_class
, " Change to", true);
1452 push_to_sequence (*before
);
1453 lra_emit_move (new_reg
, reg
);
1454 *before
= get_insns ();
1461 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1463 *after
= get_insns ();
1469 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1470 the insn to be inserted before curr insn. AFTER returns the
1471 the insn to be inserted after curr insn. ORIGREG and NEWREG
1472 are the original reg and new reg for reload. */
1474 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1479 push_to_sequence (*before
);
1480 lra_emit_move (newreg
, origreg
);
1481 *before
= get_insns ();
1487 lra_emit_move (origreg
, newreg
);
1489 *after
= get_insns ();
1494 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1495 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1497 /* Make reloads for subreg in operand NOP with internal subreg mode
1498 REG_MODE, add new reloads for further processing. Return true if
1499 any change was done. */
1501 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1504 rtx_insn
*before
, *after
;
1505 machine_mode mode
, innermode
;
1507 rtx operand
= *curr_id
->operand_loc
[nop
];
1508 enum reg_class regclass
;
1511 before
= after
= NULL
;
1513 if (GET_CODE (operand
) != SUBREG
)
1516 mode
= GET_MODE (operand
);
1517 reg
= SUBREG_REG (operand
);
1518 innermode
= GET_MODE (reg
);
1519 type
= curr_static_id
->operand
[nop
].type
;
1522 const bool addr_was_valid
1523 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1524 alter_subreg (curr_id
->operand_loc
[nop
], false);
1525 rtx subst
= *curr_id
->operand_loc
[nop
];
1526 lra_assert (MEM_P (subst
));
1529 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1530 MEM_ADDR_SPACE (subst
))
1531 || ((get_constraint_type (lookup_constraint
1532 (curr_static_id
->operand
[nop
].constraint
))
1533 != CT_SPECIAL_MEMORY
)
1534 /* We still can reload address and if the address is
1535 valid, we can remove subreg without reloading its
1537 && valid_address_p (GET_MODE (subst
),
1539 [ira_class_hard_regs
1540 [base_reg_class (GET_MODE (subst
),
1541 MEM_ADDR_SPACE (subst
),
1542 ADDRESS
, SCRATCH
)][0]],
1543 MEM_ADDR_SPACE (subst
))))
1545 /* If we change the address for a paradoxical subreg of memory, the
1546 new address might violate the necessary alignment or the access
1547 might be slow; take this into consideration. We need not worry
1548 about accesses beyond allocated memory for paradoxical memory
1549 subregs as we don't substitute such equiv memory (see processing
1550 equivalences in function lra_constraints) and because for spilled
1551 pseudos we allocate stack memory enough for the biggest
1552 corresponding paradoxical subreg.
1554 However, do not blindly simplify a (subreg (mem ...)) for
1555 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1556 data into a register when the inner is narrower than outer or
1557 missing important data from memory when the inner is wider than
1558 outer. This rule only applies to modes that are no wider than
1560 if (!(maybe_ne (GET_MODE_PRECISION (mode
),
1561 GET_MODE_PRECISION (innermode
))
1562 && known_le (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
1563 && known_le (GET_MODE_SIZE (innermode
), UNITS_PER_WORD
)
1564 && WORD_REGISTER_OPERATIONS
)
1565 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1566 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1567 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1568 && targetm
.slow_unaligned_access (innermode
,
1572 *curr_id
->operand_loc
[nop
] = operand
;
1574 /* But if the address was not valid, we cannot reload the MEM without
1575 reloading the address first. */
1576 if (!addr_was_valid
)
1577 process_address (nop
, false, &before
, &after
);
1579 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1580 enum reg_class rclass
1581 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1582 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1583 reg
, rclass
, TRUE
, "slow mem", &new_reg
))
1585 bool insert_before
, insert_after
;
1586 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1588 insert_before
= (type
!= OP_OUT
1589 || partial_subreg_p (mode
, innermode
));
1590 insert_after
= type
!= OP_IN
;
1591 insert_move_for_subreg (insert_before
? &before
: NULL
,
1592 insert_after
? &after
: NULL
,
1595 SUBREG_REG (operand
) = new_reg
;
1597 /* Convert to MODE. */
1600 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1601 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1602 rclass
, TRUE
, "slow mem", &new_reg
))
1604 bool insert_before
, insert_after
;
1605 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1607 insert_before
= type
!= OP_OUT
;
1608 insert_after
= type
!= OP_IN
;
1609 insert_move_for_subreg (insert_before
? &before
: NULL
,
1610 insert_after
? &after
: NULL
,
1613 *curr_id
->operand_loc
[nop
] = new_reg
;
1614 lra_process_new_insns (curr_insn
, before
, after
,
1615 "Inserting slow mem reload");
1619 /* If the address was valid and became invalid, prefer to reload
1620 the memory. Typical case is when the index scale should
1621 correspond the memory. */
1622 *curr_id
->operand_loc
[nop
] = operand
;
1623 /* Do not return false here as the MEM_P (reg) will be processed
1624 later in this function. */
1626 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1628 alter_subreg (curr_id
->operand_loc
[nop
], false);
1631 else if (CONSTANT_P (reg
))
1633 /* Try to simplify subreg of constant. It is usually result of
1634 equivalence substitution. */
1635 if (innermode
== VOIDmode
1636 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1637 innermode
= curr_static_id
->operand
[nop
].mode
;
1638 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1639 SUBREG_BYTE (operand
))) != NULL_RTX
)
1641 *curr_id
->operand_loc
[nop
] = new_reg
;
1645 /* Put constant into memory when we have mixed modes. It generates
1646 a better code in most cases as it does not need a secondary
1647 reload memory. It also prevents LRA looping when LRA is using
1648 secondary reload memory again and again. */
1649 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1650 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1652 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1653 alter_subreg (curr_id
->operand_loc
[nop
], false);
1656 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1657 if there may be a problem accessing OPERAND in the outer
1660 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1661 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1662 /* Don't reload paradoxical subregs because we could be looping
1663 having repeatedly final regno out of hard regs range. */
1664 && (hard_regno_nregs (hard_regno
, innermode
)
1665 >= hard_regno_nregs (hard_regno
, mode
))
1666 && simplify_subreg_regno (hard_regno
, innermode
,
1667 SUBREG_BYTE (operand
), mode
) < 0
1668 /* Don't reload subreg for matching reload. It is actually
1669 valid subreg in LRA. */
1670 && ! LRA_SUBREG_P (operand
))
1671 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1673 enum reg_class rclass
;
1676 /* There is a big probability that we will get the same class
1677 for the new pseudo and we will get the same insn which
1678 means infinite looping. So spill the new pseudo. */
1681 /* The class will be defined later in curr_insn_transform. */
1683 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1685 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1686 rclass
, TRUE
, "subreg reg", &new_reg
))
1688 bool insert_before
, insert_after
;
1689 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1691 insert_before
= (type
!= OP_OUT
1692 || read_modify_subreg_p (operand
));
1693 insert_after
= (type
!= OP_IN
);
1694 insert_move_for_subreg (insert_before
? &before
: NULL
,
1695 insert_after
? &after
: NULL
,
1698 SUBREG_REG (operand
) = new_reg
;
1699 lra_process_new_insns (curr_insn
, before
, after
,
1700 "Inserting subreg reload");
1703 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1704 IRA allocates hardreg to the inner pseudo reg according to its mode
1705 instead of the outermode, so the size of the hardreg may not be enough
1706 to contain the outermode operand, in that case we may need to insert
1707 reload for the reg. For the following two types of paradoxical subreg,
1708 we need to insert reload:
1709 1. If the op_type is OP_IN, and the hardreg could not be paired with
1710 other hardreg to contain the outermode operand
1711 (checked by in_hard_reg_set_p), we need to insert the reload.
1712 2. If the op_type is OP_OUT or OP_INOUT.
1714 Here is a paradoxical subreg example showing how the reload is generated:
1716 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1717 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1719 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1720 here, if reg107 is assigned to hardreg R15, because R15 is the last
1721 hardreg, compiler cannot find another hardreg to pair with R15 to
1722 contain TImode data. So we insert a TImode reload reg180 for it.
1723 After reload is inserted:
1725 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1726 (reg:DI 107 [ __comp ])) -1
1727 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1728 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1730 Two reload hard registers will be allocated to reg180 to save TImode data
1732 else if (REG_P (reg
)
1733 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1734 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1735 && (hard_regno_nregs (hard_regno
, innermode
)
1736 < hard_regno_nregs (hard_regno
, mode
))
1737 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1739 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1742 /* The class will be defined later in curr_insn_transform. */
1743 enum reg_class rclass
1744 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1746 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1747 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1750 bool insert_before
, insert_after
;
1752 PUT_MODE (new_reg
, mode
);
1753 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1754 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1756 insert_before
= (type
!= OP_OUT
);
1757 insert_after
= (type
!= OP_IN
);
1758 insert_move_for_subreg (insert_before
? &before
: NULL
,
1759 insert_after
? &after
: NULL
,
1762 SUBREG_REG (operand
) = new_reg
;
1763 lra_process_new_insns (curr_insn
, before
, after
,
1764 "Inserting paradoxical subreg reload");
1770 /* Return TRUE if X refers for a hard register from SET. */
1772 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1774 int i
, j
, x_hard_regno
;
1781 code
= GET_CODE (x
);
1782 mode
= GET_MODE (x
);
1785 mode
= wider_subreg_mode (x
);
1787 code
= GET_CODE (x
);
1792 x_hard_regno
= get_hard_regno (x
, true);
1793 return (x_hard_regno
>= 0
1794 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1798 struct address_info ad
;
1800 decompose_mem_address (&ad
, x
);
1801 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1803 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1806 fmt
= GET_RTX_FORMAT (code
);
1807 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1811 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1814 else if (fmt
[i
] == 'E')
1816 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1817 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1824 /* Return true if OP is a spilled pseudo. */
1826 spilled_pseudo_p (rtx op
)
1829 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1832 /* Return true if X is a general constant. */
1834 general_constant_p (rtx x
)
1836 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1840 reg_in_class_p (rtx reg
, enum reg_class cl
)
1843 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1844 return in_class_p (reg
, cl
, NULL
);
1847 /* Return true if SET of RCLASS contains no hard regs which can be
1850 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1856 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1857 COPY_HARD_REG_SET (temp
, set
);
1858 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1859 return (hard_reg_set_subset_p
1860 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1864 /* Used to check validity info about small class input operands. It
1865 should be incremented at start of processing an insn
1867 static unsigned int curr_small_class_check
= 0;
1869 /* Update number of used inputs of class OP_CLASS for operand NOP.
1870 Return true if we have more such class operands than the number of
1873 update_and_check_small_class_inputs (int nop
, enum reg_class op_class
)
1875 static unsigned int small_class_check
[LIM_REG_CLASSES
];
1876 static int small_class_input_nums
[LIM_REG_CLASSES
];
1878 if (SMALL_REGISTER_CLASS_P (op_class
)
1879 /* We are interesting in classes became small because of fixing
1880 some hard regs, e.g. by an user through GCC options. */
1881 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
1883 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
1884 || curr_static_id
->operand
[nop
].early_clobber
))
1886 if (small_class_check
[op_class
] == curr_small_class_check
)
1887 small_class_input_nums
[op_class
]++;
1890 small_class_check
[op_class
] = curr_small_class_check
;
1891 small_class_input_nums
[op_class
] = 1;
1893 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
1899 /* Major function to choose the current insn alternative and what
1900 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1901 negative we should consider only this alternative. Return false if
1902 we can not choose the alternative or find how to reload the
1905 process_alt_operands (int only_alternative
)
1908 int nop
, overall
, nalt
;
1909 int n_alternatives
= curr_static_id
->n_alternatives
;
1910 int n_operands
= curr_static_id
->n_operands
;
1911 /* LOSERS counts the operands that don't fit this alternative and
1912 would require loading. */
1915 /* REJECT is a count of how undesirable this alternative says it is
1916 if any reloading is required. If the alternative matches exactly
1917 then REJECT is ignored, but otherwise it gets this much counted
1918 against it in addition to the reloading needed. */
1920 /* This is defined by '!' or '?' alternative constraint and added to
1921 reject. But in some cases it can be ignored. */
1924 /* The number of elements in the following array. */
1925 int early_clobbered_regs_num
;
1926 /* Numbers of operands which are early clobber registers. */
1927 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1928 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1929 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1930 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1931 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1932 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1933 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1934 /* The number of elements in the following array. */
1935 int curr_alt_dont_inherit_ops_num
;
1936 /* Numbers of operands whose reload pseudos should not be inherited. */
1937 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1939 /* The register when the operand is a subreg of register, otherwise the
1941 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1942 /* The register if the operand is a register or subreg of register,
1944 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1945 int hard_regno
[MAX_RECOG_OPERANDS
];
1946 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1947 int reload_nregs
, reload_sum
;
1951 /* Calculate some data common for all alternatives to speed up the
1953 for (nop
= 0; nop
< n_operands
; nop
++)
1957 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1958 /* The real hard regno of the operand after the allocation. */
1959 hard_regno
[nop
] = get_hard_regno (op
, true);
1961 operand_reg
[nop
] = reg
= op
;
1962 biggest_mode
[nop
] = GET_MODE (op
);
1963 if (GET_CODE (op
) == SUBREG
)
1965 biggest_mode
[nop
] = wider_subreg_mode (op
);
1966 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1969 operand_reg
[nop
] = NULL_RTX
;
1970 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1971 || ((int) REGNO (reg
)
1972 == lra_get_elimination_hard_regno (REGNO (reg
))))
1973 no_subreg_reg_operand
[nop
] = reg
;
1975 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1976 /* Just use natural mode for elimination result. It should
1977 be enough for extra constraints hooks. */
1978 = regno_reg_rtx
[hard_regno
[nop
]];
1981 /* The constraints are made of several alternatives. Each operand's
1982 constraint looks like foo,bar,... with commas separating the
1983 alternatives. The first alternatives for all operands go
1984 together, the second alternatives go together, etc.
1986 First loop over alternatives. */
1987 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1988 if (only_alternative
>= 0)
1989 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1991 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1993 /* Loop over operands for one constraint alternative. */
1994 if (!TEST_BIT (preferred
, nalt
))
1997 curr_small_class_check
++;
1998 overall
= losers
= addr_losers
= 0;
1999 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
2000 for (nop
= 0; nop
< n_operands
; nop
++)
2002 int inc
= (curr_static_id
2003 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
2004 if (lra_dump_file
!= NULL
&& inc
!= 0)
2005 fprintf (lra_dump_file
,
2006 " Staticly defined alt reject+=%d\n", inc
);
2007 static_reject
+= inc
;
2009 reject
+= static_reject
;
2010 early_clobbered_regs_num
= 0;
2012 for (nop
= 0; nop
< n_operands
; nop
++)
2016 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2017 bool win
, did_match
, offmemok
, early_clobber_p
;
2018 /* false => this operand can be reloaded somehow for this
2021 /* true => this operand can be reloaded if the alternative
2024 /* True if a constant forced into memory would be OK for
2027 enum reg_class this_alternative
, this_costly_alternative
;
2028 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2029 bool this_alternative_match_win
, this_alternative_win
;
2030 bool this_alternative_offmemok
;
2033 enum constraint_num cn
;
2035 opalt_num
= nalt
* n_operands
+ nop
;
2036 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2038 /* Fast track for no constraints at all. */
2039 curr_alt
[nop
] = NO_REGS
;
2040 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2041 curr_alt_win
[nop
] = true;
2042 curr_alt_match_win
[nop
] = false;
2043 curr_alt_offmemok
[nop
] = false;
2044 curr_alt_matches
[nop
] = -1;
2048 op
= no_subreg_reg_operand
[nop
];
2049 mode
= curr_operand_mode
[nop
];
2051 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2054 early_clobber_p
= false;
2055 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2057 this_costly_alternative
= this_alternative
= NO_REGS
;
2058 /* We update set of possible hard regs besides its class
2059 because reg class might be inaccurate. For example,
2060 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2061 is translated in HI_REGS because classes are merged by
2062 pairs and there is no accurate intermediate class. */
2063 CLEAR_HARD_REG_SET (this_alternative_set
);
2064 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2065 this_alternative_win
= false;
2066 this_alternative_match_win
= false;
2067 this_alternative_offmemok
= false;
2068 this_alternative_matches
= -1;
2070 /* An empty constraint should be excluded by the fast
2072 lra_assert (*p
!= 0 && *p
!= ',');
2075 /* Scan this alternative's specs for this operand; set WIN
2076 if the operand fits any letter in this alternative.
2077 Otherwise, clear BADOP if this operand could fit some
2078 letter after reloads, or set WINREG if this operand could
2079 fit after reloads provided the constraint allows some
2084 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2094 early_clobber_p
= true;
2098 op_reject
+= LRA_MAX_REJECT
;
2101 op_reject
+= LRA_LOSER_COST_FACTOR
;
2105 /* Ignore rest of this alternative. */
2109 case '0': case '1': case '2': case '3': case '4':
2110 case '5': case '6': case '7': case '8': case '9':
2115 m
= strtoul (p
, &end
, 10);
2118 lra_assert (nop
> m
);
2120 /* Reject matches if we don't know which operand is
2121 bigger. This situation would arguably be a bug in
2122 an .md pattern, but could also occur in a user asm. */
2123 if (!ordered_p (GET_MODE_SIZE (biggest_mode
[m
]),
2124 GET_MODE_SIZE (biggest_mode
[nop
])))
2127 this_alternative_matches
= m
;
2128 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2129 /* We are supposed to match a previous operand.
2130 If we do, we win if that one did. If we do
2131 not, count both of the operands as losers.
2132 (This is too conservative, since most of the
2133 time only a single reload insn will be needed
2134 to make the two operands win. As a result,
2135 this alternative may be rejected when it is
2136 actually desirable.) */
2138 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2139 *curr_id
->operand_loc
[m
], m_hregno
))
2141 /* We should reject matching of an early
2142 clobber operand if the matching operand is
2143 not dying in the insn. */
2144 if (! curr_static_id
->operand
[m
].early_clobber
2145 || operand_reg
[nop
] == NULL_RTX
2146 || (find_regno_note (curr_insn
, REG_DEAD
,
2148 || REGNO (op
) == REGNO (operand_reg
[m
])))
2153 /* If we are matching a non-offsettable
2154 address where an offsettable address was
2155 expected, then we must reject this
2156 combination, because we can't reload
2158 if (curr_alt_offmemok
[m
]
2159 && MEM_P (*curr_id
->operand_loc
[m
])
2160 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2165 /* Operands don't match. Both operands must
2166 allow a reload register, otherwise we
2167 cannot make them match. */
2168 if (curr_alt
[m
] == NO_REGS
)
2170 /* Retroactively mark the operand we had to
2171 match as a loser, if it wasn't already and
2172 it wasn't matched to a register constraint
2173 (e.g it might be matched by memory). */
2175 && (operand_reg
[m
] == NULL_RTX
2176 || hard_regno
[m
] < 0))
2180 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2181 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2184 /* Prefer matching earlyclobber alternative as
2185 it results in less hard regs required for
2186 the insn than a non-matching earlyclobber
2188 if (curr_static_id
->operand
[m
].early_clobber
)
2190 if (lra_dump_file
!= NULL
)
2193 " %d Matching earlyclobber alt:"
2198 /* Otherwise we prefer no matching
2199 alternatives because it gives more freedom
2201 else if (operand_reg
[nop
] == NULL_RTX
2202 || (find_regno_note (curr_insn
, REG_DEAD
,
2203 REGNO (operand_reg
[nop
]))
2206 if (lra_dump_file
!= NULL
)
2209 " %d Matching alt: reject+=2\n",
2214 /* If we have to reload this operand and some
2215 previous operand also had to match the same
2216 thing as this operand, we don't know how to do
2218 if (!match_p
|| !curr_alt_win
[m
])
2220 for (i
= 0; i
< nop
; i
++)
2221 if (curr_alt_matches
[i
] == m
)
2229 /* This can be fixed with reloads if the operand
2230 we are supposed to match can be fixed with
2233 this_alternative
= curr_alt
[m
];
2234 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2235 winreg
= this_alternative
!= NO_REGS
;
2241 || general_constant_p (op
)
2242 || spilled_pseudo_p (op
))
2248 cn
= lookup_constraint (p
);
2249 switch (get_constraint_type (cn
))
2252 cl
= reg_class_for_constraint (cn
);
2258 if (CONST_INT_P (op
)
2259 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2265 && satisfies_memory_constraint_p (op
, cn
))
2267 else if (spilled_pseudo_p (op
))
2270 /* If we didn't already win, we can reload constants
2271 via force_const_mem or put the pseudo value into
2272 memory, or make other memory by reloading the
2273 address like for 'o'. */
2274 if (CONST_POOL_OK_P (mode
, op
)
2275 || MEM_P (op
) || REG_P (op
)
2276 /* We can restore the equiv insn by a
2278 || equiv_substition_p
[nop
])
2285 /* If we didn't already win, we can reload the address
2286 into a base register. */
2287 if (satisfies_address_constraint_p (op
, cn
))
2289 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2295 if (constraint_satisfied_p (op
, cn
))
2299 case CT_SPECIAL_MEMORY
:
2301 && satisfies_memory_constraint_p (op
, cn
))
2303 else if (spilled_pseudo_p (op
))
2310 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2311 IOR_HARD_REG_SET (this_alternative_set
,
2312 reg_class_contents
[cl
]);
2315 this_costly_alternative
2316 = reg_class_subunion
[this_costly_alternative
][cl
];
2317 IOR_HARD_REG_SET (this_costly_alternative_set
,
2318 reg_class_contents
[cl
]);
2320 if (mode
== BLKmode
)
2325 if (hard_regno
[nop
] >= 0
2326 && in_hard_reg_set_p (this_alternative_set
,
2327 mode
, hard_regno
[nop
]))
2329 else if (hard_regno
[nop
] < 0
2330 && in_class_p (op
, this_alternative
, NULL
))
2335 if (c
!= ' ' && c
!= '\t')
2336 costly_p
= c
== '*';
2338 while ((p
+= len
), c
);
2340 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2341 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2342 /* Record which operands fit this alternative. */
2345 this_alternative_win
= true;
2346 if (operand_reg
[nop
] != NULL_RTX
)
2348 if (hard_regno
[nop
] >= 0)
2350 if (in_hard_reg_set_p (this_costly_alternative_set
,
2351 mode
, hard_regno
[nop
]))
2353 if (lra_dump_file
!= NULL
)
2354 fprintf (lra_dump_file
,
2355 " %d Costly set: reject++\n",
2362 /* Prefer won reg to spilled pseudo under other
2363 equal conditions for possibe inheritance. */
2366 if (lra_dump_file
!= NULL
)
2369 " %d Non pseudo reload: reject++\n",
2373 if (in_class_p (operand_reg
[nop
],
2374 this_costly_alternative
, NULL
))
2376 if (lra_dump_file
!= NULL
)
2379 " %d Non pseudo costly reload:"
2385 /* We simulate the behavior of old reload here.
2386 Although scratches need hard registers and it
2387 might result in spilling other pseudos, no reload
2388 insns are generated for the scratches. So it
2389 might cost something but probably less than old
2390 reload pass believes. */
2393 if (lra_dump_file
!= NULL
)
2394 fprintf (lra_dump_file
,
2395 " %d Scratch win: reject+=2\n",
2402 this_alternative_match_win
= true;
2405 int const_to_mem
= 0;
2408 reject
+= op_reject
;
2409 /* Never do output reload of stack pointer. It makes
2410 impossible to do elimination when SP is changed in
2412 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2413 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2416 /* If this alternative asks for a specific reg class, see if there
2417 is at least one allocatable register in that class. */
2419 = (this_alternative
== NO_REGS
2420 || (hard_reg_set_subset_p
2421 (reg_class_contents
[this_alternative
],
2422 lra_no_alloc_regs
)));
2424 /* For asms, verify that the class for this alternative is possible
2425 for the mode that is specified. */
2426 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2429 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2430 if (targetm
.hard_regno_mode_ok (i
, mode
)
2431 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2434 if (i
== FIRST_PSEUDO_REGISTER
)
2438 /* If this operand accepts a register, and if the
2439 register class has at least one allocatable register,
2440 then this operand can be reloaded. */
2441 if (winreg
&& !no_regs_p
)
2446 if (lra_dump_file
!= NULL
)
2447 fprintf (lra_dump_file
,
2448 " alt=%d: Bad operand -- refuse\n",
2453 if (this_alternative
!= NO_REGS
)
2455 HARD_REG_SET available_regs
;
2457 COPY_HARD_REG_SET (available_regs
,
2458 reg_class_contents
[this_alternative
]);
2459 AND_COMPL_HARD_REG_SET
2461 ira_prohibited_class_mode_regs
[this_alternative
][mode
]);
2462 AND_COMPL_HARD_REG_SET (available_regs
, lra_no_alloc_regs
);
2463 if (hard_reg_set_empty_p (available_regs
))
2465 /* There are no hard regs holding a value of given
2469 this_alternative
= NO_REGS
;
2470 if (lra_dump_file
!= NULL
)
2471 fprintf (lra_dump_file
,
2472 " %d Using memory because of"
2473 " a bad mode: reject+=2\n",
2479 if (lra_dump_file
!= NULL
)
2480 fprintf (lra_dump_file
,
2481 " alt=%d: Wrong mode -- refuse\n",
2488 /* If not assigned pseudo has a class which a subset of
2489 required reg class, it is a less costly alternative
2490 as the pseudo still can get a hard reg of necessary
2492 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2493 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2494 && ira_class_subset_p
[this_alternative
][cl
])
2496 if (lra_dump_file
!= NULL
)
2499 " %d Super set class reg: reject-=3\n", nop
);
2503 this_alternative_offmemok
= offmemok
;
2504 if (this_costly_alternative
!= NO_REGS
)
2506 if (lra_dump_file
!= NULL
)
2507 fprintf (lra_dump_file
,
2508 " %d Costly loser: reject++\n", nop
);
2511 /* If the operand is dying, has a matching constraint,
2512 and satisfies constraints of the matched operand
2513 which failed to satisfy the own constraints, most probably
2514 the reload for this operand will be gone. */
2515 if (this_alternative_matches
>= 0
2516 && !curr_alt_win
[this_alternative_matches
]
2518 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2519 && (hard_regno
[nop
] >= 0
2520 ? in_hard_reg_set_p (this_alternative_set
,
2521 mode
, hard_regno
[nop
])
2522 : in_class_p (op
, this_alternative
, NULL
)))
2524 if (lra_dump_file
!= NULL
)
2527 " %d Dying matched operand reload: reject++\n",
2533 /* Strict_low_part requires to reload the register
2534 not the sub-register. In this case we should
2535 check that a final reload hard reg can hold the
2537 if (curr_static_id
->operand
[nop
].strict_low
2539 && hard_regno
[nop
] < 0
2540 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2541 && ira_class_hard_regs_num
[this_alternative
] > 0
2542 && (!targetm
.hard_regno_mode_ok
2543 (ira_class_hard_regs
[this_alternative
][0],
2544 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2546 if (lra_dump_file
!= NULL
)
2549 " alt=%d: Strict low subreg reload -- refuse\n",
2555 if (operand_reg
[nop
] != NULL_RTX
2556 /* Output operands and matched input operands are
2557 not inherited. The following conditions do not
2558 exactly describe the previous statement but they
2559 are pretty close. */
2560 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2561 && (this_alternative_matches
< 0
2562 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2564 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2568 /* The value of reload_sum has sense only if we
2569 process insns in their order. It happens only on
2570 the first constraints sub-pass when we do most of
2572 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2573 reload_sum
+= last_reload
- bb_reload_num
;
2575 /* If this is a constant that is reloaded into the
2576 desired class by copying it to memory first, count
2577 that as another reload. This is consistent with
2578 other code and is required to avoid choosing another
2579 alternative when the constant is moved into memory.
2580 Note that the test here is precisely the same as in
2581 the code below that calls force_const_mem. */
2582 if (CONST_POOL_OK_P (mode
, op
)
2583 && ((targetm
.preferred_reload_class
2584 (op
, this_alternative
) == NO_REGS
)
2585 || no_input_reloads_p
))
2592 /* Alternative loses if it requires a type of reload not
2593 permitted for this insn. We can always reload
2594 objects with a REG_UNUSED note. */
2595 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2596 && no_output_reloads_p
2597 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2598 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2599 && no_input_reloads_p
&& ! const_to_mem
)
2600 || (this_alternative_matches
>= 0
2601 && (no_input_reloads_p
2602 || (no_output_reloads_p
2603 && (curr_static_id
->operand
2604 [this_alternative_matches
].type
!= OP_IN
)
2605 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2606 no_subreg_reg_operand
2607 [this_alternative_matches
])))))
2609 if (lra_dump_file
!= NULL
)
2612 " alt=%d: No input/otput reload -- refuse\n",
2617 /* Alternative loses if it required class pseudo can not
2618 hold value of required mode. Such insns can be
2619 described by insn definitions with mode iterators. */
2620 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2621 && ! hard_reg_set_empty_p (this_alternative_set
)
2622 /* It is common practice for constraints to use a
2623 class which does not have actually enough regs to
2624 hold the value (e.g. x86 AREG for mode requiring
2625 more one general reg). Therefore we have 2
2626 conditions to check that the reload pseudo can
2627 not hold the mode value. */
2628 && (!targetm
.hard_regno_mode_ok
2629 (ira_class_hard_regs
[this_alternative
][0],
2630 GET_MODE (*curr_id
->operand_loc
[nop
])))
2631 /* The above condition is not enough as the first
2632 reg in ira_class_hard_regs can be not aligned for
2633 multi-words mode values. */
2634 && (prohibited_class_reg_set_mode_p
2635 (this_alternative
, this_alternative_set
,
2636 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2638 if (lra_dump_file
!= NULL
)
2639 fprintf (lra_dump_file
,
2640 " alt=%d: reload pseudo for op %d "
2641 " can not hold the mode value -- refuse\n",
2646 /* Check strong discouragement of reload of non-constant
2647 into class THIS_ALTERNATIVE. */
2648 if (! CONSTANT_P (op
) && ! no_regs_p
2649 && (targetm
.preferred_reload_class
2650 (op
, this_alternative
) == NO_REGS
2651 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2652 && (targetm
.preferred_output_reload_class
2653 (op
, this_alternative
) == NO_REGS
))))
2655 if (lra_dump_file
!= NULL
)
2656 fprintf (lra_dump_file
,
2657 " %d Non-prefered reload: reject+=%d\n",
2658 nop
, LRA_MAX_REJECT
);
2659 reject
+= LRA_MAX_REJECT
;
2662 if (! (MEM_P (op
) && offmemok
)
2663 && ! (const_to_mem
&& constmemok
))
2665 /* We prefer to reload pseudos over reloading other
2666 things, since such reloads may be able to be
2667 eliminated later. So bump REJECT in other cases.
2668 Don't do this in the case where we are forcing a
2669 constant into memory and it will then win since
2670 we don't want to have a different alternative
2672 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2674 if (lra_dump_file
!= NULL
)
2677 " %d Non-pseudo reload: reject+=2\n",
2684 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2686 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2688 if (lra_dump_file
!= NULL
)
2691 " %d Small class reload: reject+=%d\n",
2692 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2693 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2697 /* We are trying to spill pseudo into memory. It is
2698 usually more costly than moving to a hard register
2699 although it might takes the same number of
2702 Non-pseudo spill may happen also. Suppose a target allows both
2703 register and memory in the operand constraint alternatives,
2704 then it's typical that an eliminable register has a substition
2705 of "base + offset" which can either be reloaded by a simple
2706 "new_reg <= base + offset" which will match the register
2707 constraint, or a similar reg addition followed by further spill
2708 to and reload from memory which will match the memory
2709 constraint, but this memory spill will be much more costly
2712 Code below increases the reject for both pseudo and non-pseudo
2715 && !(MEM_P (op
) && offmemok
)
2716 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2718 if (lra_dump_file
!= NULL
)
2721 " %d Spill %spseudo into memory: reject+=3\n",
2722 nop
, REG_P (op
) ? "" : "Non-");
2724 if (VECTOR_MODE_P (mode
))
2726 /* Spilling vectors into memory is usually more
2727 costly as they contain big values. */
2728 if (lra_dump_file
!= NULL
)
2731 " %d Spill vector pseudo: reject+=2\n",
2737 /* When we use an operand requiring memory in given
2738 alternative, the insn should write *and* read the
2739 value to/from memory it is costly in comparison with
2740 an insn alternative which does not use memory
2741 (e.g. register or immediate operand). We exclude
2742 memory operand for such case as we can satisfy the
2743 memory constraints by reloading address. */
2744 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
2746 if (lra_dump_file
!= NULL
)
2749 " Using memory insn operand %d: reject+=3\n",
2754 /* If reload requires moving value through secondary
2755 memory, it will need one more insn at least. */
2756 if (this_alternative
!= NO_REGS
2757 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2758 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2759 && targetm
.secondary_memory_needed (GET_MODE (op
), cl
,
2761 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2762 && (targetm
.secondary_memory_needed
2763 (GET_MODE (op
), this_alternative
, cl
)))))
2766 /* Input reloads can be inherited more often than output
2767 reloads can be removed, so penalize output
2769 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2771 if (lra_dump_file
!= NULL
)
2774 " %d Non input pseudo reload: reject++\n",
2779 if (MEM_P (op
) && offmemok
)
2781 else if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
2783 if (lra_dump_file
!= NULL
)
2786 " %d Input/Output reload: reject+=%d\n",
2787 nop
, LRA_LOSER_COST_FACTOR
);
2788 reject
+= LRA_LOSER_COST_FACTOR
;
2792 if (early_clobber_p
&& ! scratch_p
)
2794 if (lra_dump_file
!= NULL
)
2795 fprintf (lra_dump_file
,
2796 " %d Early clobber: reject++\n", nop
);
2799 /* ??? We check early clobbers after processing all operands
2800 (see loop below) and there we update the costs more.
2801 Should we update the cost (may be approximately) here
2802 because of early clobber register reloads or it is a rare
2803 or non-important thing to be worth to do it. */
2804 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
2805 - (addr_losers
== losers
? static_reject
: 0));
2806 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2808 if (lra_dump_file
!= NULL
)
2809 fprintf (lra_dump_file
,
2810 " alt=%d,overall=%d,losers=%d -- refuse\n",
2811 nalt
, overall
, losers
);
2815 if (update_and_check_small_class_inputs (nop
, this_alternative
))
2817 if (lra_dump_file
!= NULL
)
2818 fprintf (lra_dump_file
,
2819 " alt=%d, not enough small class regs -- refuse\n",
2823 curr_alt
[nop
] = this_alternative
;
2824 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2825 curr_alt_win
[nop
] = this_alternative_win
;
2826 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2827 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2828 curr_alt_matches
[nop
] = this_alternative_matches
;
2830 if (this_alternative_matches
>= 0
2831 && !did_match
&& !this_alternative_win
)
2832 curr_alt_win
[this_alternative_matches
] = false;
2834 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2835 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2838 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2839 /* Prevent processing non-move insns. */
2840 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2841 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2842 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2843 && REG_P (no_subreg_reg_operand
[0])
2844 && REG_P (no_subreg_reg_operand
[1])
2845 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2846 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2847 || (! curr_alt_win
[0] && curr_alt_win
[1]
2848 && REG_P (no_subreg_reg_operand
[1])
2849 /* Check that we reload memory not the memory
2851 && ! (curr_alt_offmemok
[0]
2852 && MEM_P (no_subreg_reg_operand
[0]))
2853 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2854 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2855 && REG_P (no_subreg_reg_operand
[0])
2856 /* Check that we reload memory not the memory
2858 && ! (curr_alt_offmemok
[1]
2859 && MEM_P (no_subreg_reg_operand
[1]))
2860 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2861 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2862 no_subreg_reg_operand
[1])
2863 || (targetm
.preferred_reload_class
2864 (no_subreg_reg_operand
[1],
2865 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2866 /* If it is a result of recent elimination in move
2867 insn we can transform it into an add still by
2868 using this alternative. */
2869 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
2870 /* Likewise if the source has been replaced with an
2871 equivalent value. This only happens once -- the reload
2872 will use the equivalent value instead of the register it
2873 replaces -- so there should be no danger of cycling. */
2874 && !equiv_substition_p
[1])))
2876 /* We have a move insn and a new reload insn will be similar
2877 to the current insn. We should avoid such situation as
2878 it results in LRA cycling. */
2879 if (lra_dump_file
!= NULL
)
2880 fprintf (lra_dump_file
,
2881 " Cycle danger: overall += LRA_MAX_REJECT\n");
2882 overall
+= LRA_MAX_REJECT
;
2885 curr_alt_dont_inherit_ops_num
= 0;
2886 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2888 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2889 HARD_REG_SET temp_set
;
2891 i
= early_clobbered_nops
[nop
];
2892 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2893 || hard_regno
[i
] < 0)
2895 lra_assert (operand_reg
[i
] != NULL_RTX
);
2896 clobbered_hard_regno
= hard_regno
[i
];
2897 CLEAR_HARD_REG_SET (temp_set
);
2898 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2899 first_conflict_j
= last_conflict_j
= -1;
2900 for (j
= 0; j
< n_operands
; j
++)
2902 /* We don't want process insides of match_operator and
2903 match_parallel because otherwise we would process
2904 their operands once again generating a wrong
2906 || curr_static_id
->operand
[j
].is_operator
)
2908 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2909 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2911 /* If we don't reload j-th operand, check conflicts. */
2912 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2913 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2915 if (first_conflict_j
< 0)
2916 first_conflict_j
= j
;
2917 last_conflict_j
= j
;
2919 if (last_conflict_j
< 0)
2921 /* If earlyclobber operand conflicts with another
2922 non-matching operand which is actually the same register
2923 as the earlyclobber operand, it is better to reload the
2924 another operand as an operand matching the earlyclobber
2925 operand can be also the same. */
2926 if (first_conflict_j
== last_conflict_j
2927 && operand_reg
[last_conflict_j
] != NULL_RTX
2928 && ! curr_alt_match_win
[last_conflict_j
]
2929 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2931 curr_alt_win
[last_conflict_j
] = false;
2932 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2935 /* Early clobber was already reflected in REJECT. */
2936 lra_assert (reject
> 0);
2937 if (lra_dump_file
!= NULL
)
2940 " %d Conflict early clobber reload: reject--\n",
2943 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2947 /* We need to reload early clobbered register and the
2948 matched registers. */
2949 for (j
= 0; j
< n_operands
; j
++)
2950 if (curr_alt_matches
[j
] == i
)
2952 curr_alt_match_win
[j
] = false;
2954 overall
+= LRA_LOSER_COST_FACTOR
;
2956 if (! curr_alt_match_win
[i
])
2957 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2960 /* Remember pseudos used for match reloads are never
2962 lra_assert (curr_alt_matches
[i
] >= 0);
2963 curr_alt_win
[curr_alt_matches
[i
]] = false;
2965 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2967 /* Early clobber was already reflected in REJECT. */
2968 lra_assert (reject
> 0);
2969 if (lra_dump_file
!= NULL
)
2972 " %d Matched conflict early clobber reloads: "
2976 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2979 if (lra_dump_file
!= NULL
)
2980 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2981 nalt
, overall
, losers
, reload_nregs
);
2983 /* If this alternative can be made to work by reloading, and it
2984 needs less reloading than the others checked so far, record
2985 it as the chosen goal for reloading. */
2986 if ((best_losers
!= 0 && losers
== 0)
2987 || (((best_losers
== 0 && losers
== 0)
2988 || (best_losers
!= 0 && losers
!= 0))
2989 && (best_overall
> overall
2990 || (best_overall
== overall
2991 /* If the cost of the reloads is the same,
2992 prefer alternative which requires minimal
2993 number of reload regs. */
2994 && (reload_nregs
< best_reload_nregs
2995 || (reload_nregs
== best_reload_nregs
2996 && (best_reload_sum
< reload_sum
2997 || (best_reload_sum
== reload_sum
2998 && nalt
< goal_alt_number
))))))))
3000 for (nop
= 0; nop
< n_operands
; nop
++)
3002 goal_alt_win
[nop
] = curr_alt_win
[nop
];
3003 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
3004 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
3005 goal_alt
[nop
] = curr_alt
[nop
];
3006 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
3008 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
3009 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
3010 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
3011 goal_alt_swapped
= curr_swapped
;
3012 best_overall
= overall
;
3013 best_losers
= losers
;
3014 best_reload_nregs
= reload_nregs
;
3015 best_reload_sum
= reload_sum
;
3016 goal_alt_number
= nalt
;
3019 /* Everything is satisfied. Do not process alternatives
3028 /* Make reload base reg from address AD. */
3030 base_to_reg (struct address_info
*ad
)
3034 rtx new_inner
= NULL_RTX
;
3035 rtx new_reg
= NULL_RTX
;
3037 rtx_insn
*last_insn
= get_last_insn();
3039 lra_assert (ad
->disp
== ad
->disp_term
);
3040 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3041 get_index_code (ad
));
3042 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
,
3044 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3045 ad
->disp_term
== NULL
3048 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3050 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3051 code
= recog_memoized (insn
);
3054 delete_insns_since (last_insn
);
3061 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3063 base_plus_disp_to_reg (struct address_info
*ad
, rtx disp
)
3068 lra_assert (ad
->base
== ad
->base_term
);
3069 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3070 get_index_code (ad
));
3071 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
3073 lra_emit_add (new_reg
, *ad
->base_term
, disp
);
3077 /* Make reload of index part of address AD. Return the new
3080 index_part_to_reg (struct address_info
*ad
)
3084 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3085 INDEX_REG_CLASS
, "index term");
3086 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3087 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3091 /* Return true if we can add a displacement to address AD, even if that
3092 makes the address invalid. The fix-up code requires any new address
3093 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3095 can_add_disp_p (struct address_info
*ad
)
3097 return (!ad
->autoinc_p
3098 && ad
->segment
== NULL
3099 && ad
->base
== ad
->base_term
3100 && ad
->disp
== ad
->disp_term
);
3103 /* Make equiv substitution in address AD. Return true if a substitution
3106 equiv_address_substitution (struct address_info
*ad
)
3108 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3110 HOST_WIDE_INT scale
;
3113 base_term
= strip_subreg (ad
->base_term
);
3114 if (base_term
== NULL
)
3115 base_reg
= new_base_reg
= NULL_RTX
;
3118 base_reg
= *base_term
;
3119 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3121 index_term
= strip_subreg (ad
->index_term
);
3122 if (index_term
== NULL
)
3123 index_reg
= new_index_reg
= NULL_RTX
;
3126 index_reg
= *index_term
;
3127 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3129 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3133 if (lra_dump_file
!= NULL
)
3135 fprintf (lra_dump_file
, "Changing address in insn %d ",
3136 INSN_UID (curr_insn
));
3137 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3139 if (base_reg
!= new_base_reg
)
3142 if (REG_P (new_base_reg
))
3144 *base_term
= new_base_reg
;
3147 else if (GET_CODE (new_base_reg
) == PLUS
3148 && REG_P (XEXP (new_base_reg
, 0))
3149 && poly_int_rtx_p (XEXP (new_base_reg
, 1), &offset
)
3150 && can_add_disp_p (ad
))
3153 *base_term
= XEXP (new_base_reg
, 0);
3156 if (ad
->base_term2
!= NULL
)
3157 *ad
->base_term2
= *ad
->base_term
;
3159 if (index_reg
!= new_index_reg
)
3162 if (REG_P (new_index_reg
))
3164 *index_term
= new_index_reg
;
3167 else if (GET_CODE (new_index_reg
) == PLUS
3168 && REG_P (XEXP (new_index_reg
, 0))
3169 && poly_int_rtx_p (XEXP (new_index_reg
, 1), &offset
)
3170 && can_add_disp_p (ad
)
3171 && (scale
= get_index_scale (ad
)))
3173 disp
+= offset
* scale
;
3174 *index_term
= XEXP (new_index_reg
, 0);
3178 if (maybe_ne (disp
, 0))
3180 if (ad
->disp
!= NULL
)
3181 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3184 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3185 update_address (ad
);
3189 if (lra_dump_file
!= NULL
)
3192 fprintf (lra_dump_file
, " -- no change\n");
3195 fprintf (lra_dump_file
, " on equiv ");
3196 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3197 fprintf (lra_dump_file
, "\n");
3203 /* Major function to make reloads for an address in operand NOP or
3204 check its correctness (If CHECK_ONLY_P is true). The supported
3207 1) an address that existed before LRA started, at which point it
3208 must have been valid. These addresses are subject to elimination
3209 and may have become invalid due to the elimination offset being out
3212 2) an address created by forcing a constant to memory
3213 (force_const_to_mem). The initial form of these addresses might
3214 not be valid, and it is this function's job to make them valid.
3216 3) a frame address formed from a register and a (possibly zero)
3217 constant offset. As above, these addresses might not be valid and
3218 this function must make them so.
3220 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3221 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3222 address. Return true for any RTL change.
3224 The function is a helper function which does not produce all
3225 transformations (when CHECK_ONLY_P is false) which can be
3226 necessary. It does just basic steps. To do all necessary
3227 transformations use function process_address. */
3229 process_address_1 (int nop
, bool check_only_p
,
3230 rtx_insn
**before
, rtx_insn
**after
)
3232 struct address_info ad
;
3234 HOST_WIDE_INT scale
;
3235 rtx op
= *curr_id
->operand_loc
[nop
];
3236 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3237 enum constraint_num cn
= lookup_constraint (constraint
);
3238 bool change_p
= false;
3241 && GET_MODE (op
) == BLKmode
3242 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3245 if (insn_extra_address_constraint (cn
))
3246 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3247 /* Do not attempt to decompose arbitrary addresses generated by combine
3248 for asm operands with loose constraints, e.g 'X'. */
3250 && !(INSN_CODE (curr_insn
) < 0
3251 && get_constraint_type (cn
) == CT_FIXED_FORM
3252 && constraint_satisfied_p (op
, cn
)))
3253 decompose_mem_address (&ad
, op
);
3254 else if (GET_CODE (op
) == SUBREG
3255 && MEM_P (SUBREG_REG (op
)))
3256 decompose_mem_address (&ad
, SUBREG_REG (op
));
3259 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3260 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3261 when INDEX_REG_CLASS is a single register class. */
3262 if (ad
.base_term
!= NULL
3263 && ad
.index_term
!= NULL
3264 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3265 && REG_P (*ad
.base_term
)
3266 && REG_P (*ad
.index_term
)
3267 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3268 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3270 std::swap (ad
.base
, ad
.index
);
3271 std::swap (ad
.base_term
, ad
.index_term
);
3274 change_p
= equiv_address_substitution (&ad
);
3275 if (ad
.base_term
!= NULL
3276 && (process_addr_reg
3277 (ad
.base_term
, check_only_p
, before
,
3279 && !(REG_P (*ad
.base_term
)
3280 && find_regno_note (curr_insn
, REG_DEAD
,
3281 REGNO (*ad
.base_term
)) != NULL_RTX
)
3283 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3284 get_index_code (&ad
)))))
3287 if (ad
.base_term2
!= NULL
)
3288 *ad
.base_term2
= *ad
.base_term
;
3290 if (ad
.index_term
!= NULL
3291 && process_addr_reg (ad
.index_term
, check_only_p
,
3292 before
, NULL
, INDEX_REG_CLASS
))
3295 /* Target hooks sometimes don't treat extra-constraint addresses as
3296 legitimate address_operands, so handle them specially. */
3297 if (insn_extra_address_constraint (cn
)
3298 && satisfies_address_constraint_p (&ad
, cn
))
3304 /* There are three cases where the shape of *AD.INNER may now be invalid:
3306 1) the original address was valid, but either elimination or
3307 equiv_address_substitution was applied and that made
3308 the address invalid.
3310 2) the address is an invalid symbolic address created by
3313 3) the address is a frame address with an invalid offset.
3315 4) the address is a frame address with an invalid base.
3317 All these cases involve a non-autoinc address, so there is no
3318 point revalidating other types. */
3319 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3322 /* Any index existed before LRA started, so we can assume that the
3323 presence and shape of the index is valid. */
3324 push_to_sequence (*before
);
3325 lra_assert (ad
.disp
== ad
.disp_term
);
3326 if (ad
.base
== NULL
)
3328 if (ad
.index
== NULL
)
3331 rtx_insn
*last
= get_last_insn ();
3333 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3335 rtx addr
= *ad
.inner
;
3337 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3340 /* addr => lo_sum (new_base, addr), case (2) above. */
3341 insn
= emit_insn (gen_rtx_SET
3343 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3344 code
= recog_memoized (insn
);
3347 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3348 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3350 /* Try to put lo_sum into register. */
3351 insn
= emit_insn (gen_rtx_SET
3353 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3354 code
= recog_memoized (insn
);
3357 *ad
.inner
= new_reg
;
3358 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3368 delete_insns_since (last
);
3373 /* addr => new_base, case (2) above. */
3374 lra_emit_move (new_reg
, addr
);
3376 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3378 insn
= NEXT_INSN (insn
))
3379 if (recog_memoized (insn
) < 0)
3381 if (insn
!= NULL_RTX
)
3383 /* Do nothing if we cannot generate right insns.
3384 This is analogous to reload pass behavior. */
3385 delete_insns_since (last
);
3389 *ad
.inner
= new_reg
;
3394 /* index * scale + disp => new base + index * scale,
3396 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3397 GET_CODE (*ad
.index
));
3399 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3400 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3401 lra_emit_move (new_reg
, *ad
.disp
);
3402 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3403 new_reg
, *ad
.index
);
3406 else if (ad
.index
== NULL
)
3411 rtx_insn
*insns
, *last_insn
;
3412 /* Try to reload base into register only if the base is invalid
3413 for the address but with valid offset, case (4) above. */
3415 new_reg
= base_to_reg (&ad
);
3417 /* base + disp => new base, cases (1) and (3) above. */
3418 /* Another option would be to reload the displacement into an
3419 index register. However, postreload has code to optimize
3420 address reloads that have the same base and different
3421 displacements, so reloading into an index register would
3422 not necessarily be a win. */
3423 if (new_reg
== NULL_RTX
)
3425 /* See if the target can split the displacement into a
3426 legitimate new displacement from a local anchor. */
3427 gcc_assert (ad
.disp
== ad
.disp_term
);
3428 poly_int64 orig_offset
;
3429 rtx offset1
, offset2
;
3430 if (poly_int_rtx_p (*ad
.disp
, &orig_offset
)
3431 && targetm
.legitimize_address_displacement (&offset1
, &offset2
,
3435 new_reg
= base_plus_disp_to_reg (&ad
, offset1
);
3436 new_reg
= gen_rtx_PLUS (GET_MODE (new_reg
), new_reg
, offset2
);
3439 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3441 insns
= get_insns ();
3442 last_insn
= get_last_insn ();
3443 /* If we generated at least two insns, try last insn source as
3444 an address. If we succeed, we generate one less insn. */
3446 && last_insn
!= insns
3447 && (set
= single_set (last_insn
)) != NULL_RTX
3448 && GET_CODE (SET_SRC (set
)) == PLUS
3449 && REG_P (XEXP (SET_SRC (set
), 0))
3450 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3452 *ad
.inner
= SET_SRC (set
);
3453 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3455 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3456 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3457 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3458 get_index_code (&ad
));
3459 regno
= REGNO (*ad
.base_term
);
3460 if (regno
>= FIRST_PSEUDO_REGISTER
3461 && cl
!= lra_get_allocno_class (regno
))
3462 lra_change_class (regno
, cl
, " Change to", true);
3463 new_reg
= SET_SRC (set
);
3464 delete_insns_since (PREV_INSN (last_insn
));
3469 *ad
.inner
= new_reg
;
3471 else if (ad
.disp_term
!= NULL
)
3473 /* base + scale * index + disp => new base + scale * index,
3475 gcc_assert (ad
.disp
== ad
.disp_term
);
3476 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3477 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3478 new_reg
, *ad
.index
);
3480 else if ((scale
= get_index_scale (&ad
)) == 1)
3482 /* The last transformation to one reg will be made in
3483 curr_insn_transform function. */
3487 else if (scale
!= 0)
3489 /* base + scale * index => base + new_reg,
3491 Index part of address may become invalid. For example, we
3492 changed pseudo on the equivalent memory and a subreg of the
3493 pseudo onto the memory of different mode for which the scale is
3495 new_reg
= index_part_to_reg (&ad
);
3496 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3497 *ad
.base_term
, new_reg
);
3501 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3503 rtx addr
= *ad
.inner
;
3505 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3506 /* addr => new_base. */
3507 lra_emit_move (new_reg
, addr
);
3508 *ad
.inner
= new_reg
;
3510 *before
= get_insns ();
3515 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3516 Use process_address_1 as a helper function. Return true for any
3519 If CHECK_ONLY_P is true, just check address correctness. Return
3520 false if the address correct. */
3522 process_address (int nop
, bool check_only_p
,
3523 rtx_insn
**before
, rtx_insn
**after
)
3527 while (process_address_1 (nop
, check_only_p
, before
, after
))
3536 /* Emit insns to reload VALUE into a new register. VALUE is an
3537 auto-increment or auto-decrement RTX whose operand is a register or
3538 memory location; so reloading involves incrementing that location.
3539 IN is either identical to VALUE, or some cheaper place to reload
3540 value being incremented/decremented from.
3542 INC_AMOUNT is the number to increment or decrement by (always
3543 positive and ignored for POST_MODIFY/PRE_MODIFY).
3545 Return pseudo containing the result. */
3547 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, poly_int64 inc_amount
)
3549 /* REG or MEM to be copied and incremented. */
3550 rtx incloc
= XEXP (value
, 0);
3551 /* Nonzero if increment after copying. */
3552 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3553 || GET_CODE (value
) == POST_MODIFY
);
3558 rtx real_in
= in
== value
? incloc
: in
;
3562 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3564 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3565 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3566 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3567 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3568 inc
= XEXP (XEXP (value
, 1), 1);
3572 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3573 inc_amount
= -inc_amount
;
3575 inc
= gen_int_mode (inc_amount
, GET_MODE (value
));
3578 if (! post
&& REG_P (incloc
))
3581 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3584 if (real_in
!= result
)
3586 /* First copy the location to the result register. */
3587 lra_assert (REG_P (result
));
3588 emit_insn (gen_move_insn (result
, real_in
));
3591 /* We suppose that there are insns to add/sub with the constant
3592 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3593 old reload worked with this assumption. If the assumption
3594 becomes wrong, we should use approach in function
3595 base_plus_disp_to_reg. */
3598 /* See if we can directly increment INCLOC. */
3599 last
= get_last_insn ();
3600 add_insn
= emit_insn (plus_p
3601 ? gen_add2_insn (incloc
, inc
)
3602 : gen_sub2_insn (incloc
, inc
));
3604 code
= recog_memoized (add_insn
);
3607 if (! post
&& result
!= incloc
)
3608 emit_insn (gen_move_insn (result
, incloc
));
3611 delete_insns_since (last
);
3614 /* If couldn't do the increment directly, must increment in RESULT.
3615 The way we do this depends on whether this is pre- or
3616 post-increment. For pre-increment, copy INCLOC to the reload
3617 register, increment it there, then save back. */
3620 if (real_in
!= result
)
3621 emit_insn (gen_move_insn (result
, real_in
));
3623 emit_insn (gen_add2_insn (result
, inc
));
3625 emit_insn (gen_sub2_insn (result
, inc
));
3626 if (result
!= incloc
)
3627 emit_insn (gen_move_insn (incloc
, result
));
3633 Because this might be a jump insn or a compare, and because
3634 RESULT may not be available after the insn in an input
3635 reload, we must do the incrementing before the insn being
3638 We have already copied IN to RESULT. Increment the copy in
3639 RESULT, save that back, then decrement RESULT so it has
3640 the original value. */
3642 emit_insn (gen_add2_insn (result
, inc
));
3644 emit_insn (gen_sub2_insn (result
, inc
));
3645 emit_insn (gen_move_insn (incloc
, result
));
3646 /* Restore non-modified value for the result. We prefer this
3647 way because it does not require an additional hard
3652 if (poly_int_rtx_p (inc
, &offset
))
3653 emit_insn (gen_add2_insn (result
,
3654 gen_int_mode (-offset
,
3655 GET_MODE (result
))));
3657 emit_insn (gen_sub2_insn (result
, inc
));
3660 emit_insn (gen_add2_insn (result
, inc
));
3665 /* Return true if the current move insn does not need processing as we
3666 already know that it satisfies its constraints. */
3668 simple_move_p (void)
3671 enum reg_class dclass
, sclass
;
3673 lra_assert (curr_insn_set
!= NULL_RTX
);
3674 dest
= SET_DEST (curr_insn_set
);
3675 src
= SET_SRC (curr_insn_set
);
3677 /* If the instruction has multiple sets we need to process it even if it
3678 is single_set. This can happen if one or more of the SETs are dead.
3680 if (multiple_sets (curr_insn
))
3683 return ((dclass
= get_op_class (dest
)) != NO_REGS
3684 && (sclass
= get_op_class (src
)) != NO_REGS
3685 /* The backend guarantees that register moves of cost 2
3686 never need reloads. */
3687 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3690 /* Swap operands NOP and NOP + 1. */
3692 swap_operands (int nop
)
3694 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3695 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3696 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3697 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3698 /* Swap the duplicates too. */
3699 lra_update_dup (curr_id
, nop
);
3700 lra_update_dup (curr_id
, nop
+ 1);
3703 /* Main entry point of the constraint code: search the body of the
3704 current insn to choose the best alternative. It is mimicking insn
3705 alternative cost calculation model of former reload pass. That is
3706 because machine descriptions were written to use this model. This
3707 model can be changed in future. Make commutative operand exchange
3710 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3711 constraints. Return true if any change happened during function
3714 If CHECK_ONLY_P is true then don't do any transformation. Just
3715 check that the insn satisfies all constraints. If the insn does
3716 not satisfy any constraint, return true. */
3718 curr_insn_transform (bool check_only_p
)
3725 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3726 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3727 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3728 rtx_insn
*before
, *after
;
3730 /* Flag that the insn has been changed through a transformation. */
3734 int max_regno_before
;
3735 int reused_alternative_num
;
3737 curr_insn_set
= single_set (curr_insn
);
3738 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3741 no_input_reloads_p
= no_output_reloads_p
= false;
3742 goal_alt_number
= -1;
3743 change_p
= sec_mem_p
= false;
3744 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3745 reloads; neither are insns that SET cc0. Insns that use CC0 are
3746 not allowed to have any input reloads. */
3747 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3748 no_output_reloads_p
= true;
3750 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3751 no_input_reloads_p
= true;
3752 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3753 no_output_reloads_p
= true;
3755 n_operands
= curr_static_id
->n_operands
;
3756 n_alternatives
= curr_static_id
->n_alternatives
;
3758 /* Just return "no reloads" if insn has no operands with
3760 if (n_operands
== 0 || n_alternatives
== 0)
3763 max_regno_before
= max_reg_num ();
3765 for (i
= 0; i
< n_operands
; i
++)
3767 goal_alt_matched
[i
][0] = -1;
3768 goal_alt_matches
[i
] = -1;
3771 commutative
= curr_static_id
->commutative
;
3773 /* Now see what we need for pseudos that didn't get hard regs or got
3774 the wrong kind of hard reg. For this, we must consider all the
3775 operands together against the register constraints. */
3777 best_losers
= best_overall
= INT_MAX
;
3778 best_reload_sum
= 0;
3780 curr_swapped
= false;
3781 goal_alt_swapped
= false;
3784 /* Make equivalence substitution and memory subreg elimination
3785 before address processing because an address legitimacy can
3786 depend on memory mode. */
3787 for (i
= 0; i
< n_operands
; i
++)
3790 bool op_change_p
= false;
3792 if (curr_static_id
->operand
[i
].is_operator
)
3795 old
= op
= *curr_id
->operand_loc
[i
];
3796 if (GET_CODE (old
) == SUBREG
)
3797 old
= SUBREG_REG (old
);
3798 subst
= get_equiv_with_elimination (old
, curr_insn
);
3799 original_subreg_reg_mode
[i
] = VOIDmode
;
3800 equiv_substition_p
[i
] = false;
3803 equiv_substition_p
[i
] = true;
3804 subst
= copy_rtx (subst
);
3805 lra_assert (REG_P (old
));
3806 if (GET_CODE (op
) != SUBREG
)
3807 *curr_id
->operand_loc
[i
] = subst
;
3810 SUBREG_REG (op
) = subst
;
3811 if (GET_MODE (subst
) == VOIDmode
)
3812 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3814 if (lra_dump_file
!= NULL
)
3816 fprintf (lra_dump_file
,
3817 "Changing pseudo %d in operand %i of insn %u on equiv ",
3818 REGNO (old
), i
, INSN_UID (curr_insn
));
3819 dump_value_slim (lra_dump_file
, subst
, 1);
3820 fprintf (lra_dump_file
, "\n");
3822 op_change_p
= change_p
= true;
3824 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3827 lra_update_dup (curr_id
, i
);
3831 /* Reload address registers and displacements. We do it before
3832 finding an alternative because of memory constraints. */
3833 before
= after
= NULL
;
3834 for (i
= 0; i
< n_operands
; i
++)
3835 if (! curr_static_id
->operand
[i
].is_operator
3836 && process_address (i
, check_only_p
, &before
, &after
))
3841 lra_update_dup (curr_id
, i
);
3845 /* If we've changed the instruction then any alternative that
3846 we chose previously may no longer be valid. */
3847 lra_set_used_insn_alternative (curr_insn
, -1);
3849 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3850 && check_and_process_move (&change_p
, &sec_mem_p
))
3855 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3856 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3857 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3858 reused_alternative_num
, INSN_UID (curr_insn
));
3860 if (process_alt_operands (reused_alternative_num
))
3864 return ! alt_p
|| best_losers
!= 0;
3866 /* If insn is commutative (it's safe to exchange a certain pair of
3867 operands) then we need to try each alternative twice, the second
3868 time matching those two operands as if we had exchanged them. To
3869 do this, really exchange them in operands.
3871 If we have just tried the alternatives the second time, return
3872 operands to normal and drop through. */
3874 if (reused_alternative_num
< 0 && commutative
>= 0)
3876 curr_swapped
= !curr_swapped
;
3879 swap_operands (commutative
);
3883 swap_operands (commutative
);
3886 if (! alt_p
&& ! sec_mem_p
)
3888 /* No alternative works with reloads?? */
3889 if (INSN_CODE (curr_insn
) >= 0)
3890 fatal_insn ("unable to generate reloads for:", curr_insn
);
3891 error_for_asm (curr_insn
,
3892 "inconsistent operand constraints in an %<asm%>");
3893 /* Avoid further trouble with this insn. Don't generate use
3894 pattern here as we could use the insn SP offset. */
3895 lra_set_insn_deleted (curr_insn
);
3899 /* If the best alternative is with operands 1 and 2 swapped, swap
3900 them. Update the operand numbers of any reloads already
3903 if (goal_alt_swapped
)
3905 if (lra_dump_file
!= NULL
)
3906 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3907 INSN_UID (curr_insn
));
3909 /* Swap the duplicates too. */
3910 swap_operands (commutative
);
3914 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3915 too conservatively. So we use the secondary memory only if there
3916 is no any alternative without reloads. */
3917 use_sec_mem_p
= false;
3919 use_sec_mem_p
= true;
3922 for (i
= 0; i
< n_operands
; i
++)
3923 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3925 use_sec_mem_p
= i
< n_operands
;
3930 int in
= -1, out
= -1;
3931 rtx new_reg
, src
, dest
, rld
;
3932 machine_mode sec_mode
, rld_mode
;
3934 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3935 dest
= SET_DEST (curr_insn_set
);
3936 src
= SET_SRC (curr_insn_set
);
3937 for (i
= 0; i
< n_operands
; i
++)
3938 if (*curr_id
->operand_loc
[i
] == dest
)
3940 else if (*curr_id
->operand_loc
[i
] == src
)
3942 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3943 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3944 out
= curr_static_id
->dup_num
[i
];
3945 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3946 in
= curr_static_id
->dup_num
[i
];
3947 lra_assert (out
>= 0 && in
>= 0
3948 && curr_static_id
->operand
[out
].type
== OP_OUT
3949 && curr_static_id
->operand
[in
].type
== OP_IN
);
3950 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
3951 rld_mode
= GET_MODE (rld
);
3952 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
3953 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3954 NO_REGS
, "secondary");
3955 /* If the mode is changed, it should be wider. */
3956 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
3957 if (sec_mode
!= rld_mode
)
3959 /* If the target says specifically to use another mode for
3960 secondary memory moves we can not reuse the original
3962 after
= emit_spill_move (false, new_reg
, dest
);
3963 lra_process_new_insns (curr_insn
, NULL
, after
,
3964 "Inserting the sec. move");
3965 /* We may have non null BEFORE here (e.g. after address
3967 push_to_sequence (before
);
3968 before
= emit_spill_move (true, new_reg
, src
);
3970 before
= get_insns ();
3972 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3973 lra_set_insn_deleted (curr_insn
);
3975 else if (dest
== rld
)
3977 *curr_id
->operand_loc
[out
] = new_reg
;
3978 lra_update_dup (curr_id
, out
);
3979 after
= emit_spill_move (false, new_reg
, dest
);
3980 lra_process_new_insns (curr_insn
, NULL
, after
,
3981 "Inserting the sec. move");
3985 *curr_id
->operand_loc
[in
] = new_reg
;
3986 lra_update_dup (curr_id
, in
);
3987 /* See comments above. */
3988 push_to_sequence (before
);
3989 before
= emit_spill_move (true, new_reg
, src
);
3991 before
= get_insns ();
3993 lra_process_new_insns (curr_insn
, before
, NULL
,
3994 "Inserting the sec. move");
3996 lra_update_insn_regno_info (curr_insn
);
4000 lra_assert (goal_alt_number
>= 0);
4001 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
4003 if (lra_dump_file
!= NULL
)
4007 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4008 goal_alt_number
, INSN_UID (curr_insn
));
4009 for (i
= 0; i
< n_operands
; i
++)
4011 p
= (curr_static_id
->operand_alternative
4012 [goal_alt_number
* n_operands
+ i
].constraint
);
4015 fprintf (lra_dump_file
, " (%d) ", i
);
4016 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
4017 fputc (*p
, lra_dump_file
);
4019 if (INSN_CODE (curr_insn
) >= 0
4020 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4021 fprintf (lra_dump_file
, " {%s}", p
);
4022 if (maybe_ne (curr_id
->sp_offset
, 0))
4024 fprintf (lra_dump_file
, " (sp_off=");
4025 print_dec (curr_id
->sp_offset
, lra_dump_file
);
4026 fprintf (lra_dump_file
, ")");
4028 fprintf (lra_dump_file
, "\n");
4031 /* Right now, for any pair of operands I and J that are required to
4032 match, with J < I, goal_alt_matches[I] is J. Add I to
4033 goal_alt_matched[J]. */
4035 for (i
= 0; i
< n_operands
; i
++)
4036 if ((j
= goal_alt_matches
[i
]) >= 0)
4038 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4040 /* We allow matching one output operand and several input
4043 || (curr_static_id
->operand
[j
].type
== OP_OUT
4044 && curr_static_id
->operand
[i
].type
== OP_IN
4045 && (curr_static_id
->operand
4046 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4047 goal_alt_matched
[j
][k
] = i
;
4048 goal_alt_matched
[j
][k
+ 1] = -1;
4051 for (i
= 0; i
< n_operands
; i
++)
4052 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4054 /* Any constants that aren't allowed and can't be reloaded into
4055 registers are here changed into memory references. */
4056 for (i
= 0; i
< n_operands
; i
++)
4057 if (goal_alt_win
[i
])
4060 enum reg_class new_class
;
4061 rtx reg
= *curr_id
->operand_loc
[i
];
4063 if (GET_CODE (reg
) == SUBREG
)
4064 reg
= SUBREG_REG (reg
);
4066 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4068 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4070 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4073 lra_change_class (regno
, new_class
, " Change to", true);
4079 const char *constraint
;
4081 rtx op
= *curr_id
->operand_loc
[i
];
4082 rtx subreg
= NULL_RTX
;
4083 machine_mode mode
= curr_operand_mode
[i
];
4085 if (GET_CODE (op
) == SUBREG
)
4088 op
= SUBREG_REG (op
);
4089 mode
= GET_MODE (op
);
4092 if (CONST_POOL_OK_P (mode
, op
)
4093 && ((targetm
.preferred_reload_class
4094 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4095 || no_input_reloads_p
))
4097 rtx tem
= force_const_mem (mode
, op
);
4100 if (subreg
!= NULL_RTX
)
4101 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4103 *curr_id
->operand_loc
[i
] = tem
;
4104 lra_update_dup (curr_id
, i
);
4105 process_address (i
, false, &before
, &after
);
4107 /* If the alternative accepts constant pool refs directly
4108 there will be no reload needed at all. */
4109 if (subreg
!= NULL_RTX
)
4111 /* Skip alternatives before the one requested. */
4112 constraint
= (curr_static_id
->operand_alternative
4113 [goal_alt_number
* n_operands
+ i
].constraint
);
4115 (c
= *constraint
) && c
!= ',' && c
!= '#';
4116 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4118 enum constraint_num cn
= lookup_constraint (constraint
);
4119 if ((insn_extra_memory_constraint (cn
)
4120 || insn_extra_special_memory_constraint (cn
))
4121 && satisfies_memory_constraint_p (tem
, cn
))
4124 if (c
== '\0' || c
== ',' || c
== '#')
4127 goal_alt_win
[i
] = true;
4133 for (i
= 0; i
< n_operands
; i
++)
4136 bool optional_p
= false;
4138 rtx op
= *curr_id
->operand_loc
[i
];
4140 if (goal_alt_win
[i
])
4142 if (goal_alt
[i
] == NO_REGS
4144 /* When we assign NO_REGS it means that we will not
4145 assign a hard register to the scratch pseudo by
4146 assigment pass and the scratch pseudo will be
4147 spilled. Spilled scratch pseudos are transformed
4148 back to scratches at the LRA end. */
4149 && lra_former_scratch_operand_p (curr_insn
, i
)
4150 && lra_former_scratch_p (REGNO (op
)))
4152 int regno
= REGNO (op
);
4153 lra_change_class (regno
, NO_REGS
, " Change to", true);
4154 if (lra_get_regno_hard_regno (regno
) >= 0)
4155 /* We don't have to mark all insn affected by the
4156 spilled pseudo as there is only one such insn, the
4158 reg_renumber
[regno
] = -1;
4159 lra_assert (bitmap_single_bit_set_p
4160 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4162 /* We can do an optional reload. If the pseudo got a hard
4163 reg, we might improve the code through inheritance. If
4164 it does not get a hard register we coalesce memory/memory
4165 moves later. Ignore move insns to avoid cycling. */
4167 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4168 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4169 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4170 && regno
< new_regno_start
4171 && ! lra_former_scratch_p (regno
)
4172 && reg_renumber
[regno
] < 0
4173 /* Check that the optional reload pseudo will be able to
4174 hold given mode value. */
4175 && ! (prohibited_class_reg_set_mode_p
4176 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4177 PSEUDO_REGNO_MODE (regno
)))
4178 && (curr_insn_set
== NULL_RTX
4179 || !((REG_P (SET_SRC (curr_insn_set
))
4180 || MEM_P (SET_SRC (curr_insn_set
))
4181 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4182 && (REG_P (SET_DEST (curr_insn_set
))
4183 || MEM_P (SET_DEST (curr_insn_set
))
4184 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4190 /* Operands that match previous ones have already been handled. */
4191 if (goal_alt_matches
[i
] >= 0)
4194 /* We should not have an operand with a non-offsettable address
4195 appearing where an offsettable address will do. It also may
4196 be a case when the address should be special in other words
4197 not a general one (e.g. it needs no index reg). */
4198 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4200 enum reg_class rclass
;
4201 rtx
*loc
= &XEXP (op
, 0);
4202 enum rtx_code code
= GET_CODE (*loc
);
4204 push_to_sequence (before
);
4205 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4207 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4208 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4209 /* This value does not matter for MODIFY. */
4210 GET_MODE_SIZE (GET_MODE (op
)));
4211 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4212 "offsetable address", &new_reg
))
4213 lra_emit_move (new_reg
, *loc
);
4214 before
= get_insns ();
4217 lra_update_dup (curr_id
, i
);
4219 else if (goal_alt_matched
[i
][0] == -1)
4224 enum op_type type
= curr_static_id
->operand
[i
].type
;
4226 loc
= curr_id
->operand_loc
[i
];
4227 mode
= curr_operand_mode
[i
];
4228 if (GET_CODE (*loc
) == SUBREG
)
4230 reg
= SUBREG_REG (*loc
);
4231 poly_int64 byte
= SUBREG_BYTE (*loc
);
4233 /* Strict_low_part requires reloading the register and not
4234 just the subreg. Likewise for a strict subreg no wider
4235 than a word for WORD_REGISTER_OPERATIONS targets. */
4236 && (curr_static_id
->operand
[i
].strict_low
4237 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4239 = get_try_hard_regno (REGNO (reg
))) >= 0
4240 && (simplify_subreg_regno
4242 GET_MODE (reg
), byte
, mode
) < 0)
4243 && (goal_alt
[i
] == NO_REGS
4244 || (simplify_subreg_regno
4245 (ira_class_hard_regs
[goal_alt
[i
]][0],
4246 GET_MODE (reg
), byte
, mode
) >= 0)))
4247 || (partial_subreg_p (mode
, GET_MODE (reg
))
4248 && known_le (GET_MODE_SIZE (GET_MODE (reg
)),
4250 && WORD_REGISTER_OPERATIONS
)))
4252 /* An OP_INOUT is required when reloading a subreg of a
4253 mode wider than a word to ensure that data beyond the
4254 word being reloaded is preserved. Also automatically
4255 ensure that strict_low_part reloads are made into
4256 OP_INOUT which should already be true from the backend
4259 && (curr_static_id
->operand
[i
].strict_low
4260 || read_modify_subreg_p (*loc
)))
4262 loc
= &SUBREG_REG (*loc
);
4263 mode
= GET_MODE (*loc
);
4267 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4268 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4271 push_to_sequence (before
);
4272 lra_emit_move (new_reg
, old
);
4273 before
= get_insns ();
4278 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4281 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4283 after
= get_insns ();
4287 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4288 if (goal_alt_dont_inherit_ops
[j
] == i
)
4290 lra_set_regno_unique_value (REGNO (new_reg
));
4293 lra_update_dup (curr_id
, i
);
4295 else if (curr_static_id
->operand
[i
].type
== OP_IN
4296 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4298 || (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4300 && (operands_match_p
4301 (*curr_id
->operand_loc
[i
],
4302 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4305 /* generate reloads for input and matched outputs. */
4306 match_inputs
[0] = i
;
4307 match_inputs
[1] = -1;
4308 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4309 goal_alt
[i
], &before
, &after
,
4310 curr_static_id
->operand_alternative
4311 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4314 else if ((curr_static_id
->operand
[i
].type
== OP_OUT
4315 || (curr_static_id
->operand
[i
].type
== OP_INOUT
4316 && (operands_match_p
4317 (*curr_id
->operand_loc
[i
],
4318 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4320 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4322 /* Generate reloads for output and matched inputs. */
4323 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4324 &after
, curr_static_id
->operand_alternative
4325 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4326 else if (curr_static_id
->operand
[i
].type
== OP_IN
4327 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4330 /* Generate reloads for matched inputs. */
4331 match_inputs
[0] = i
;
4332 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4333 match_inputs
[j
+ 1] = k
;
4334 match_inputs
[j
+ 1] = -1;
4335 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4339 /* We must generate code in any case when function
4340 process_alt_operands decides that it is possible. */
4343 /* Memorise processed outputs so that output remaining to be processed
4344 can avoid using the same register value (see match_reload). */
4345 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4347 outputs
[n_outputs
++] = i
;
4348 outputs
[n_outputs
] = -1;
4355 lra_assert (REG_P (reg
));
4356 regno
= REGNO (reg
);
4357 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4358 if (GET_CODE (op
) == SUBREG
)
4359 op
= SUBREG_REG (op
);
4360 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4361 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4362 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4363 if (lra_dump_file
!= NULL
)
4364 fprintf (lra_dump_file
,
4365 " Making reload reg %d for reg %d optional\n",
4369 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4370 || max_regno_before
!= max_reg_num ())
4374 lra_update_operator_dups (curr_id
);
4375 /* Something changes -- process the insn. */
4376 lra_update_insn_regno_info (curr_insn
);
4378 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4382 /* Return true if INSN satisfies all constraints. In other words, no
4383 reload insns are needed. */
4385 lra_constrain_insn (rtx_insn
*insn
)
4387 int saved_new_regno_start
= new_regno_start
;
4388 int saved_new_insn_uid_start
= new_insn_uid_start
;
4392 curr_id
= lra_get_insn_recog_data (curr_insn
);
4393 curr_static_id
= curr_id
->insn_static_data
;
4394 new_insn_uid_start
= get_max_uid ();
4395 new_regno_start
= max_reg_num ();
4396 change_p
= curr_insn_transform (true);
4397 new_regno_start
= saved_new_regno_start
;
4398 new_insn_uid_start
= saved_new_insn_uid_start
;
4402 /* Return true if X is in LIST. */
4404 in_list_p (rtx x
, rtx list
)
4406 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4407 if (XEXP (list
, 0) == x
)
4412 /* Return true if X contains an allocatable hard register (if
4413 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4415 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4421 code
= GET_CODE (x
);
4424 int regno
= REGNO (x
);
4425 HARD_REG_SET alloc_regs
;
4429 if (regno
>= FIRST_PSEUDO_REGISTER
)
4430 regno
= lra_get_regno_hard_regno (regno
);
4433 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4434 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4438 if (regno
< FIRST_PSEUDO_REGISTER
)
4442 return lra_get_regno_hard_regno (regno
) < 0;
4445 fmt
= GET_RTX_FORMAT (code
);
4446 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4450 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4453 else if (fmt
[i
] == 'E')
4455 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4456 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4463 /* Process all regs in location *LOC and change them on equivalent
4464 substitution. Return true if any change was done. */
4466 loc_equivalence_change_p (rtx
*loc
)
4468 rtx subst
, reg
, x
= *loc
;
4469 bool result
= false;
4470 enum rtx_code code
= GET_CODE (x
);
4476 reg
= SUBREG_REG (x
);
4477 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4478 && GET_MODE (subst
) == VOIDmode
)
4480 /* We cannot reload debug location. Simplify subreg here
4481 while we know the inner mode. */
4482 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4483 GET_MODE (reg
), SUBREG_BYTE (x
));
4487 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4493 /* Scan all the operand sub-expressions. */
4494 fmt
= GET_RTX_FORMAT (code
);
4495 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4498 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4499 else if (fmt
[i
] == 'E')
4500 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4502 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4507 /* Similar to loc_equivalence_change_p, but for use as
4508 simplify_replace_fn_rtx callback. DATA is insn for which the
4509 elimination is done. If it null we don't do the elimination. */
4511 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4516 rtx subst
= (data
== NULL
4517 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4524 /* Maximum number of generated reload insns per an insn. It is for
4525 preventing this pass cycling in a bug case. */
4526 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4528 /* The current iteration number of this LRA pass. */
4529 int lra_constraint_iter
;
4531 /* True if we substituted equiv which needs checking register
4532 allocation correctness because the equivalent value contains
4533 allocatable hard registers or when we restore multi-register
4535 bool lra_risky_transformations_p
;
4537 /* Return true if REGNO is referenced in more than one block. */
4539 multi_block_pseudo_p (int regno
)
4541 basic_block bb
= NULL
;
4545 if (regno
< FIRST_PSEUDO_REGISTER
)
4548 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4550 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4551 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4556 /* Return true if LIST contains a deleted insn. */
4558 contains_deleted_insn_p (rtx_insn_list
*list
)
4560 for (; list
!= NULL_RTX
; list
= list
->next ())
4561 if (NOTE_P (list
->insn ())
4562 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4567 /* Return true if X contains a pseudo dying in INSN. */
4569 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4576 return (insn
!= NULL_RTX
4577 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4578 code
= GET_CODE (x
);
4579 fmt
= GET_RTX_FORMAT (code
);
4580 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4584 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4587 else if (fmt
[i
] == 'E')
4589 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4590 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4597 /* Return true if INSN contains a dying pseudo in INSN right hand
4600 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4602 rtx set
= single_set (insn
);
4604 gcc_assert (set
!= NULL
);
4605 return dead_pseudo_p (SET_SRC (set
), insn
);
4608 /* Return true if any init insn of REGNO contains a dying pseudo in
4609 insn right hand side. */
4611 init_insn_rhs_dead_pseudo_p (int regno
)
4613 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4617 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4618 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4623 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4624 reverse only if we have one init insn with given REGNO as a
4627 reverse_equiv_p (int regno
)
4629 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4634 if (! INSN_P (insns
->insn ())
4635 || insns
->next () != NULL
)
4637 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4639 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4642 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4643 call this function only for non-reverse equivalence. */
4645 contains_reloaded_insn_p (int regno
)
4648 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4650 for (; list
!= NULL
; list
= list
->next ())
4651 if ((set
= single_set (list
->insn ())) == NULL_RTX
4652 || ! REG_P (SET_DEST (set
))
4653 || (int) REGNO (SET_DEST (set
)) != regno
)
4658 /* Entry function of LRA constraint pass. Return true if the
4659 constraint pass did change the code. */
4661 lra_constraints (bool first_p
)
4664 int i
, hard_regno
, new_insns_num
;
4665 unsigned int min_len
, new_min_len
, uid
;
4666 rtx set
, x
, reg
, dest_reg
;
4667 basic_block last_bb
;
4670 lra_constraint_iter
++;
4671 if (lra_dump_file
!= NULL
)
4672 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4673 lra_constraint_iter
);
4675 if (pic_offset_table_rtx
4676 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4677 lra_risky_transformations_p
= true;
4679 /* On the first iteration we should check IRA assignment
4680 correctness. In rare cases, the assignments can be wrong as
4681 early clobbers operands are ignored in IRA. */
4682 lra_risky_transformations_p
= first_p
;
4683 new_insn_uid_start
= get_max_uid ();
4684 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4685 /* Mark used hard regs for target stack size calulations. */
4686 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4687 if (lra_reg_info
[i
].nrefs
!= 0
4688 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4692 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
4693 for (j
= 0; j
< nregs
; j
++)
4694 df_set_regs_ever_live (hard_regno
+ j
, true);
4696 /* Do elimination before the equivalence processing as we can spill
4697 some pseudos during elimination. */
4698 lra_eliminate (false, first_p
);
4699 auto_bitmap
equiv_insn_bitmap (®_obstack
);
4700 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4701 if (lra_reg_info
[i
].nrefs
!= 0)
4703 ira_reg_equiv
[i
].profitable_p
= true;
4704 reg
= regno_reg_rtx
[i
];
4705 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4707 bool pseudo_p
= contains_reg_p (x
, false, false);
4709 /* After RTL transformation, we can not guarantee that
4710 pseudo in the substitution was not reloaded which might
4711 make equivalence invalid. For example, in reverse
4718 the memory address register was reloaded before the 2nd
4720 if ((! first_p
&& pseudo_p
)
4721 /* We don't use DF for compilation speed sake. So it
4722 is problematic to update live info when we use an
4723 equivalence containing pseudos in more than one
4725 || (pseudo_p
&& multi_block_pseudo_p (i
))
4726 /* If an init insn was deleted for some reason, cancel
4727 the equiv. We could update the equiv insns after
4728 transformations including an equiv insn deletion
4729 but it is not worthy as such cases are extremely
4731 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4732 /* If it is not a reverse equivalence, we check that a
4733 pseudo in rhs of the init insn is not dying in the
4734 insn. Otherwise, the live info at the beginning of
4735 the corresponding BB might be wrong after we
4736 removed the insn. When the equiv can be a
4737 constant, the right hand side of the init insn can
4739 || (! reverse_equiv_p (i
)
4740 && (init_insn_rhs_dead_pseudo_p (i
)
4741 /* If we reloaded the pseudo in an equivalence
4742 init insn, we can not remove the equiv init
4743 insns and the init insns might write into
4744 const memory in this case. */
4745 || contains_reloaded_insn_p (i
)))
4746 /* Prevent access beyond equivalent memory for
4747 paradoxical subregs. */
4749 && maybe_gt (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
),
4750 GET_MODE_SIZE (GET_MODE (x
))))
4751 || (pic_offset_table_rtx
4752 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4753 && (targetm
.preferred_reload_class
4754 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4755 || contains_symbol_ref_p (x
))))
4756 ira_reg_equiv
[i
].defined_p
= false;
4757 if (contains_reg_p (x
, false, true))
4758 ira_reg_equiv
[i
].profitable_p
= false;
4759 if (get_equiv (reg
) != reg
)
4760 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4763 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4765 /* We should add all insns containing pseudos which should be
4766 substituted by their equivalences. */
4767 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
4768 lra_push_insn_by_uid (uid
);
4769 min_len
= lra_insn_stack_length ();
4773 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4775 curr_insn
= lra_pop_insn ();
4777 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4778 if (curr_bb
!= last_bb
)
4781 bb_reload_num
= lra_curr_reload_num
;
4783 if (min_len
> new_min_len
)
4785 min_len
= new_min_len
;
4788 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4790 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4791 MAX_RELOAD_INSNS_NUMBER
);
4793 if (DEBUG_INSN_P (curr_insn
))
4795 /* We need to check equivalence in debug insn and change
4796 pseudo to the equivalent value if necessary. */
4797 curr_id
= lra_get_insn_recog_data (curr_insn
);
4798 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4800 rtx old
= *curr_id
->operand_loc
[0];
4801 *curr_id
->operand_loc
[0]
4802 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4803 loc_equivalence_callback
, curr_insn
);
4804 if (old
!= *curr_id
->operand_loc
[0])
4806 lra_update_insn_regno_info (curr_insn
);
4811 else if (INSN_P (curr_insn
))
4813 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4815 dest_reg
= SET_DEST (set
);
4816 /* The equivalence pseudo could be set up as SUBREG in a
4817 case when it is a call restore insn in a mode
4818 different from the pseudo mode. */
4819 if (GET_CODE (dest_reg
) == SUBREG
)
4820 dest_reg
= SUBREG_REG (dest_reg
);
4821 if ((REG_P (dest_reg
)
4822 && (x
= get_equiv (dest_reg
)) != dest_reg
4823 /* Remove insns which set up a pseudo whose value
4824 can not be changed. Such insns might be not in
4825 init_insns because we don't update equiv data
4826 during insn transformations.
4828 As an example, let suppose that a pseudo got
4829 hard register and on the 1st pass was not
4830 changed to equivalent constant. We generate an
4831 additional insn setting up the pseudo because of
4832 secondary memory movement. Then the pseudo is
4833 spilled and we use the equiv constant. In this
4834 case we should remove the additional insn and
4835 this insn is not init_insns list. */
4836 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4837 /* Check that this is actually an insn setting
4838 up the equivalence. */
4839 || in_list_p (curr_insn
,
4841 [REGNO (dest_reg
)].init_insns
)))
4842 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4843 && in_list_p (curr_insn
,
4845 [REGNO (SET_SRC (set
))].init_insns
)))
4847 /* This is equiv init insn of pseudo which did not get a
4848 hard register -- remove the insn. */
4849 if (lra_dump_file
!= NULL
)
4851 fprintf (lra_dump_file
,
4852 " Removing equiv init insn %i (freq=%d)\n",
4853 INSN_UID (curr_insn
),
4854 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4855 dump_insn_slim (lra_dump_file
, curr_insn
);
4857 if (contains_reg_p (x
, true, false))
4858 lra_risky_transformations_p
= true;
4859 lra_set_insn_deleted (curr_insn
);
4863 curr_id
= lra_get_insn_recog_data (curr_insn
);
4864 curr_static_id
= curr_id
->insn_static_data
;
4865 init_curr_insn_input_reloads ();
4866 init_curr_operand_mode ();
4867 if (curr_insn_transform (false))
4869 /* Check non-transformed insns too for equiv change as USE
4870 or CLOBBER don't need reloads but can contain pseudos
4871 being changed on their equivalences. */
4872 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
4873 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4875 lra_update_insn_regno_info (curr_insn
);
4881 /* If we used a new hard regno, changed_p should be true because the
4882 hard reg is assigned to a new pseudo. */
4883 if (flag_checking
&& !changed_p
)
4885 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4886 if (lra_reg_info
[i
].nrefs
!= 0
4887 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4889 int j
, nregs
= hard_regno_nregs (hard_regno
,
4890 PSEUDO_REGNO_MODE (i
));
4892 for (j
= 0; j
< nregs
; j
++)
4893 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4899 static void initiate_invariants (void);
4900 static void finish_invariants (void);
4902 /* Initiate the LRA constraint pass. It is done once per
4905 lra_constraints_init (void)
4907 initiate_invariants ();
4910 /* Finalize the LRA constraint pass. It is done once per
4913 lra_constraints_finish (void)
4915 finish_invariants ();
4920 /* Structure describes invariants for ineheritance. */
4921 struct lra_invariant
4923 /* The order number of the invariant. */
4925 /* The invariant RTX. */
4927 /* The origin insn of the invariant. */
4931 typedef lra_invariant invariant_t
;
4932 typedef invariant_t
*invariant_ptr_t
;
4933 typedef const invariant_t
*const_invariant_ptr_t
;
4935 /* Pointer to the inheritance invariants. */
4936 static vec
<invariant_ptr_t
> invariants
;
4938 /* Allocation pool for the invariants. */
4939 static object_allocator
<lra_invariant
> *invariants_pool
;
4941 /* Hash table for the invariants. */
4942 static htab_t invariant_table
;
4944 /* Hash function for INVARIANT. */
4946 invariant_hash (const void *invariant
)
4948 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
4949 return lra_rtx_hash (inv
);
4952 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4954 invariant_eq_p (const void *invariant1
, const void *invariant2
)
4956 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
4957 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
4959 return rtx_equal_p (inv1
, inv2
);
4962 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
4963 invariant which is in the table. */
4964 static invariant_ptr_t
4965 insert_invariant (rtx invariant_rtx
)
4968 invariant_t invariant
;
4969 invariant_ptr_t invariant_ptr
;
4971 invariant
.invariant_rtx
= invariant_rtx
;
4972 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
4973 if (*entry_ptr
== NULL
)
4975 invariant_ptr
= invariants_pool
->allocate ();
4976 invariant_ptr
->invariant_rtx
= invariant_rtx
;
4977 invariant_ptr
->insn
= NULL
;
4978 invariants
.safe_push (invariant_ptr
);
4979 *entry_ptr
= (void *) invariant_ptr
;
4981 return (invariant_ptr_t
) *entry_ptr
;
4984 /* Initiate the invariant table. */
4986 initiate_invariants (void)
4988 invariants
.create (100);
4990 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
4991 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
4994 /* Finish the invariant table. */
4996 finish_invariants (void)
4998 htab_delete (invariant_table
);
4999 delete invariants_pool
;
5000 invariants
.release ();
5003 /* Make the invariant table empty. */
5005 clear_invariants (void)
5007 htab_empty (invariant_table
);
5008 invariants_pool
->release ();
5009 invariants
.truncate (0);
5014 /* This page contains code to do inheritance/split
5017 /* Number of reloads passed so far in current EBB. */
5018 static int reloads_num
;
5020 /* Number of calls passed so far in current EBB. */
5021 static int calls_num
;
5023 /* Current reload pseudo check for validity of elements in
5025 static int curr_usage_insns_check
;
5027 /* Info about last usage of registers in EBB to do inheritance/split
5028 transformation. Inheritance transformation is done from a spilled
5029 pseudo and split transformations from a hard register or a pseudo
5030 assigned to a hard register. */
5033 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5034 value INSNS is valid. The insns is chain of optional debug insns
5035 and a finishing non-debug insn using the corresponding reg. The
5036 value is also used to mark the registers which are set up in the
5037 current insn. The negated insn uid is used for this. */
5039 /* Value of global reloads_num at the last insn in INSNS. */
5041 /* Value of global reloads_nums at the last insn in INSNS. */
5043 /* It can be true only for splitting. And it means that the restore
5044 insn should be put after insn given by the following member. */
5046 /* Next insns in the current EBB which use the original reg and the
5047 original reg value is not changed between the current insn and
5048 the next insns. In order words, e.g. for inheritance, if we need
5049 to use the original reg value again in the next insns we can try
5050 to use the value in a hard register from a reload insn of the
5055 /* Map: regno -> corresponding pseudo usage insns. */
5056 static struct usage_insns
*usage_insns
;
5059 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5061 usage_insns
[regno
].check
= curr_usage_insns_check
;
5062 usage_insns
[regno
].insns
= insn
;
5063 usage_insns
[regno
].reloads_num
= reloads_num
;
5064 usage_insns
[regno
].calls_num
= calls_num
;
5065 usage_insns
[regno
].after_p
= after_p
;
5068 /* The function is used to form list REGNO usages which consists of
5069 optional debug insns finished by a non-debug insn using REGNO.
5070 RELOADS_NUM is current number of reload insns processed so far. */
5072 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5074 rtx next_usage_insns
;
5076 if (usage_insns
[regno
].check
== curr_usage_insns_check
5077 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5078 && DEBUG_INSN_P (insn
))
5080 /* Check that we did not add the debug insn yet. */
5081 if (next_usage_insns
!= insn
5082 && (GET_CODE (next_usage_insns
) != INSN_LIST
5083 || XEXP (next_usage_insns
, 0) != insn
))
5084 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5087 else if (NONDEBUG_INSN_P (insn
))
5088 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5090 usage_insns
[regno
].check
= 0;
5093 /* Return first non-debug insn in list USAGE_INSNS. */
5095 skip_usage_debug_insns (rtx usage_insns
)
5099 /* Skip debug insns. */
5100 for (insn
= usage_insns
;
5101 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5102 insn
= XEXP (insn
, 1))
5104 return safe_as_a
<rtx_insn
*> (insn
);
5107 /* Return true if we need secondary memory moves for insn in
5108 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5111 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5112 rtx usage_insns ATTRIBUTE_UNUSED
)
5118 if (inher_cl
== ALL_REGS
5119 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5121 lra_assert (INSN_P (insn
));
5122 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5124 dest
= SET_DEST (set
);
5127 lra_assert (inher_cl
!= NO_REGS
);
5128 cl
= get_reg_class (REGNO (dest
));
5129 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5130 && targetm
.secondary_memory_needed (GET_MODE (dest
), inher_cl
, cl
));
5133 /* Registers involved in inheritance/split in the current EBB
5134 (inheritance/split pseudos and original registers). */
5135 static bitmap_head check_only_regs
;
5137 /* Reload pseudos can not be involded in invariant inheritance in the
5139 static bitmap_head invalid_invariant_regs
;
5141 /* Do inheritance transformations for insn INSN, which defines (if
5142 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5143 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5144 form as the "insns" field of usage_insns. Return true if we
5145 succeed in such transformation.
5147 The transformations look like:
5150 ... p <- i (new insn)
5152 <- ... p ... <- ... i ...
5154 ... i <- p (new insn)
5155 <- ... p ... <- ... i ...
5157 <- ... p ... <- ... i ...
5158 where p is a spilled original pseudo and i is a new inheritance pseudo.
5161 The inheritance pseudo has the smallest class of two classes CL and
5162 class of ORIGINAL REGNO. */
5164 inherit_reload_reg (bool def_p
, int original_regno
,
5165 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5167 if (optimize_function_for_size_p (cfun
))
5170 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5171 rtx original_reg
= regno_reg_rtx
[original_regno
];
5172 rtx new_reg
, usage_insn
;
5173 rtx_insn
*new_insns
;
5175 lra_assert (! usage_insns
[original_regno
].after_p
);
5176 if (lra_dump_file
!= NULL
)
5177 fprintf (lra_dump_file
,
5178 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5179 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5181 if (lra_dump_file
!= NULL
)
5183 fprintf (lra_dump_file
,
5184 " Rejecting inheritance for %d "
5185 "because of disjoint classes %s and %s\n",
5186 original_regno
, reg_class_names
[cl
],
5187 reg_class_names
[rclass
]);
5188 fprintf (lra_dump_file
,
5189 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5193 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5194 /* We don't use a subset of two classes because it can be
5195 NO_REGS. This transformation is still profitable in most
5196 cases even if the classes are not intersected as register
5197 move is probably cheaper than a memory load. */
5198 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5200 if (lra_dump_file
!= NULL
)
5201 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5202 reg_class_names
[cl
], reg_class_names
[rclass
]);
5206 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5208 /* Reject inheritance resulting in secondary memory moves.
5209 Otherwise, there is a danger in LRA cycling. Also such
5210 transformation will be unprofitable. */
5211 if (lra_dump_file
!= NULL
)
5213 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5214 rtx set
= single_set (insn
);
5216 lra_assert (set
!= NULL_RTX
);
5218 rtx dest
= SET_DEST (set
);
5220 lra_assert (REG_P (dest
));
5221 fprintf (lra_dump_file
,
5222 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5223 "as secondary mem is needed\n",
5224 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5225 original_regno
, reg_class_names
[rclass
]);
5226 fprintf (lra_dump_file
,
5227 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5231 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5232 rclass
, "inheritance");
5235 lra_emit_move (original_reg
, new_reg
);
5237 lra_emit_move (new_reg
, original_reg
);
5238 new_insns
= get_insns ();
5240 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5242 if (lra_dump_file
!= NULL
)
5244 fprintf (lra_dump_file
,
5245 " Rejecting inheritance %d->%d "
5246 "as it results in 2 or more insns:\n",
5247 original_regno
, REGNO (new_reg
));
5248 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5249 fprintf (lra_dump_file
,
5250 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5254 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5255 lra_update_insn_regno_info (insn
);
5257 /* We now have a new usage insn for original regno. */
5258 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5259 if (lra_dump_file
!= NULL
)
5260 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5261 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5262 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5263 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5264 bitmap_set_bit (&check_only_regs
, original_regno
);
5265 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5267 lra_process_new_insns (insn
, NULL
, new_insns
,
5268 "Add original<-inheritance");
5270 lra_process_new_insns (insn
, new_insns
, NULL
,
5271 "Add inheritance<-original");
5272 while (next_usage_insns
!= NULL_RTX
)
5274 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5276 usage_insn
= next_usage_insns
;
5277 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5278 next_usage_insns
= NULL
;
5282 usage_insn
= XEXP (next_usage_insns
, 0);
5283 lra_assert (DEBUG_INSN_P (usage_insn
));
5284 next_usage_insns
= XEXP (next_usage_insns
, 1);
5286 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5287 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5288 if (lra_dump_file
!= NULL
)
5290 basic_block bb
= BLOCK_FOR_INSN (usage_insn
);
5291 fprintf (lra_dump_file
,
5292 " Inheritance reuse change %d->%d (bb%d):\n",
5293 original_regno
, REGNO (new_reg
),
5294 bb
? bb
->index
: -1);
5295 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5298 if (lra_dump_file
!= NULL
)
5299 fprintf (lra_dump_file
,
5300 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5304 /* Return true if we need a caller save/restore for pseudo REGNO which
5305 was assigned to a hard register. */
5307 need_for_call_save_p (int regno
)
5309 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5310 return (usage_insns
[regno
].calls_num
< calls_num
5311 && (overlaps_hard_reg_set_p
5313 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
5314 ? lra_reg_info
[regno
].actual_call_used_reg_set
5315 : call_used_reg_set
,
5316 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
5317 || (targetm
.hard_regno_call_part_clobbered
5318 (reg_renumber
[regno
], PSEUDO_REGNO_MODE (regno
)))));
5321 /* Global registers occurring in the current EBB. */
5322 static bitmap_head ebb_global_regs
;
5324 /* Return true if we need a split for hard register REGNO or pseudo
5325 REGNO which was assigned to a hard register.
5326 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5327 used for reloads since the EBB end. It is an approximation of the
5328 used hard registers in the split range. The exact value would
5329 require expensive calculations. If we were aggressive with
5330 splitting because of the approximation, the split pseudo will save
5331 the same hard register assignment and will be removed in the undo
5332 pass. We still need the approximation because too aggressive
5333 splitting would result in too inaccurate cost calculation in the
5334 assignment pass because of too many generated moves which will be
5335 probably removed in the undo pass. */
5337 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5339 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5341 lra_assert (hard_regno
>= 0);
5342 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5343 /* Don't split eliminable hard registers, otherwise we can
5344 split hard registers like hard frame pointer, which
5345 lives on BB start/end according to DF-infrastructure,
5346 when there is a pseudo assigned to the register and
5347 living in the same BB. */
5348 && (regno
>= FIRST_PSEUDO_REGISTER
5349 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5350 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5351 /* Don't split call clobbered hard regs living through
5352 calls, otherwise we might have a check problem in the
5353 assign sub-pass as in the most cases (exception is a
5354 situation when lra_risky_transformations_p value is
5355 true) the assign pass assumes that all pseudos living
5356 through calls are assigned to call saved hard regs. */
5357 && (regno
>= FIRST_PSEUDO_REGISTER
5358 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
5359 || usage_insns
[regno
].calls_num
== calls_num
)
5360 /* We need at least 2 reloads to make pseudo splitting
5361 profitable. We should provide hard regno splitting in
5362 any case to solve 1st insn scheduling problem when
5363 moving hard register definition up might result in
5364 impossibility to find hard register for reload pseudo of
5365 small register class. */
5366 && (usage_insns
[regno
].reloads_num
5367 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5368 && (regno
< FIRST_PSEUDO_REGISTER
5369 /* For short living pseudos, spilling + inheritance can
5370 be considered a substitution for splitting.
5371 Therefore we do not splitting for local pseudos. It
5372 decreases also aggressiveness of splitting. The
5373 minimal number of references is chosen taking into
5374 account that for 2 references splitting has no sense
5375 as we can just spill the pseudo. */
5376 || (regno
>= FIRST_PSEUDO_REGISTER
5377 && lra_reg_info
[regno
].nrefs
> 3
5378 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5379 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5382 /* Return class for the split pseudo created from original pseudo with
5383 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5384 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5385 results in no secondary memory movements. */
5386 static enum reg_class
5387 choose_split_class (enum reg_class allocno_class
,
5388 int hard_regno ATTRIBUTE_UNUSED
,
5389 machine_mode mode ATTRIBUTE_UNUSED
)
5392 enum reg_class cl
, best_cl
= NO_REGS
;
5393 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5394 = REGNO_REG_CLASS (hard_regno
);
5396 if (! targetm
.secondary_memory_needed (mode
, allocno_class
, allocno_class
)
5397 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5398 return allocno_class
;
5400 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5402 if (! targetm
.secondary_memory_needed (mode
, cl
, hard_reg_class
)
5403 && ! targetm
.secondary_memory_needed (mode
, hard_reg_class
, cl
)
5404 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5405 && (best_cl
== NO_REGS
5406 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5411 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5412 It only makes sense to call this function if NEW_REGNO is always
5413 equal to ORIGINAL_REGNO. */
5416 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
)
5418 if (!ira_reg_equiv
[original_regno
].defined_p
)
5421 ira_expand_reg_equiv ();
5422 ira_reg_equiv
[new_regno
].defined_p
= true;
5423 if (ira_reg_equiv
[original_regno
].memory
)
5424 ira_reg_equiv
[new_regno
].memory
5425 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
5426 if (ira_reg_equiv
[original_regno
].constant
)
5427 ira_reg_equiv
[new_regno
].constant
5428 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
5429 if (ira_reg_equiv
[original_regno
].invariant
)
5430 ira_reg_equiv
[new_regno
].invariant
5431 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
5434 /* Do split transformations for insn INSN, which defines or uses
5435 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5436 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5437 "insns" field of usage_insns.
5439 The transformations look like:
5442 ... s <- p (new insn -- save)
5444 ... p <- s (new insn -- restore)
5445 <- ... p ... <- ... p ...
5447 <- ... p ... <- ... p ...
5448 ... s <- p (new insn -- save)
5450 ... p <- s (new insn -- restore)
5451 <- ... p ... <- ... p ...
5453 where p is an original pseudo got a hard register or a hard
5454 register and s is a new split pseudo. The save is put before INSN
5455 if BEFORE_P is true. Return true if we succeed in such
5458 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5459 rtx next_usage_insns
)
5461 enum reg_class rclass
;
5463 int hard_regno
, nregs
;
5464 rtx new_reg
, usage_insn
;
5465 rtx_insn
*restore
, *save
;
5470 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5472 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5473 hard_regno
= original_regno
;
5474 call_save_p
= false;
5476 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5477 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5478 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5479 as part of a multi-word register. In that case, or if the biggest
5480 mode was larger than a register, just use the reg_rtx. Otherwise,
5481 limit the size to that of the biggest access in the function. */
5482 if (mode
== VOIDmode
5483 || paradoxical_subreg_p (mode
, reg_rtx_mode
))
5485 original_reg
= regno_reg_rtx
[hard_regno
];
5486 mode
= reg_rtx_mode
;
5489 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5493 mode
= PSEUDO_REGNO_MODE (original_regno
);
5494 hard_regno
= reg_renumber
[original_regno
];
5495 nregs
= hard_regno_nregs (hard_regno
, mode
);
5496 rclass
= lra_get_allocno_class (original_regno
);
5497 original_reg
= regno_reg_rtx
[original_regno
];
5498 call_save_p
= need_for_call_save_p (original_regno
);
5500 lra_assert (hard_regno
>= 0);
5501 if (lra_dump_file
!= NULL
)
5502 fprintf (lra_dump_file
,
5503 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5507 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5508 hard_regno_nregs (hard_regno
, mode
),
5510 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5514 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5515 if (rclass
== NO_REGS
)
5517 if (lra_dump_file
!= NULL
)
5519 fprintf (lra_dump_file
,
5520 " Rejecting split of %d(%s): "
5521 "no good reg class for %d(%s)\n",
5523 reg_class_names
[lra_get_allocno_class (original_regno
)],
5525 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5528 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5532 /* Split_if_necessary can split hard registers used as part of a
5533 multi-register mode but splits each register individually. The
5534 mode used for each independent register may not be supported
5535 so reject the split. Splitting the wider mode should theoretically
5536 be possible but is not implemented. */
5537 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
5539 if (lra_dump_file
!= NULL
)
5541 fprintf (lra_dump_file
,
5542 " Rejecting split of %d(%s): unsuitable mode %s\n",
5544 reg_class_names
[lra_get_allocno_class (original_regno
)],
5545 GET_MODE_NAME (mode
));
5548 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5552 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5553 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5555 int new_regno
= REGNO (new_reg
);
5556 save
= emit_spill_move (true, new_reg
, original_reg
);
5557 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5559 if (lra_dump_file
!= NULL
)
5563 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5564 original_regno
, new_regno
);
5565 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5566 fprintf (lra_dump_file
,
5567 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5571 restore
= emit_spill_move (false, new_reg
, original_reg
);
5572 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5574 if (lra_dump_file
!= NULL
)
5576 fprintf (lra_dump_file
,
5577 " Rejecting split %d->%d "
5578 "resulting in > 2 restore insns:\n",
5579 original_regno
, new_regno
);
5580 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5581 fprintf (lra_dump_file
,
5582 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5586 /* Transfer equivalence information to the spill register, so that
5587 if we fail to allocate the spill register, we have the option of
5588 rematerializing the original value instead of spilling to the stack. */
5589 if (!HARD_REGISTER_NUM_P (original_regno
)
5590 && mode
== PSEUDO_REGNO_MODE (original_regno
))
5591 lra_copy_reg_equiv (new_regno
, original_regno
);
5592 after_p
= usage_insns
[original_regno
].after_p
;
5593 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
5594 bitmap_set_bit (&check_only_regs
, new_regno
);
5595 bitmap_set_bit (&check_only_regs
, original_regno
);
5596 bitmap_set_bit (&lra_split_regs
, new_regno
);
5599 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5601 usage_insn
= next_usage_insns
;
5604 usage_insn
= XEXP (next_usage_insns
, 0);
5605 lra_assert (DEBUG_INSN_P (usage_insn
));
5606 next_usage_insns
= XEXP (next_usage_insns
, 1);
5607 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5608 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5609 if (lra_dump_file
!= NULL
)
5611 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5612 original_regno
, new_regno
);
5613 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5616 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5617 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5618 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5619 after_p
? NULL
: restore
,
5620 after_p
? restore
: NULL
,
5622 ? "Add reg<-save" : "Add reg<-split");
5623 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5624 before_p
? NULL
: save
,
5626 ? "Add save<-reg" : "Add split<-reg");
5628 /* If we are trying to split multi-register. We should check
5629 conflicts on the next assignment sub-pass. IRA can allocate on
5630 sub-register levels, LRA do this on pseudos level right now and
5631 this discrepancy may create allocation conflicts after
5633 lra_risky_transformations_p
= true;
5634 if (lra_dump_file
!= NULL
)
5635 fprintf (lra_dump_file
,
5636 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5640 /* Recognize that we need a split transformation for insn INSN, which
5641 defines or uses REGNO in its insn biggest MODE (we use it only if
5642 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5643 hard registers which might be used for reloads since the EBB end.
5644 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5645 uid before starting INSN processing. Return true if we succeed in
5646 such transformation. */
5648 split_if_necessary (int regno
, machine_mode mode
,
5649 HARD_REG_SET potential_reload_hard_regs
,
5650 bool before_p
, rtx_insn
*insn
, int max_uid
)
5654 rtx next_usage_insns
;
5656 if (regno
< FIRST_PSEUDO_REGISTER
)
5657 nregs
= hard_regno_nregs (regno
, mode
);
5658 for (i
= 0; i
< nregs
; i
++)
5659 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5660 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5661 /* To avoid processing the register twice or more. */
5662 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5663 && INSN_UID (next_usage_insns
) < max_uid
)
5664 || (GET_CODE (next_usage_insns
) == INSN_LIST
5665 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5666 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5667 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5672 /* Return TRUE if rtx X is considered as an invariant for
5675 invariant_p (const_rtx x
)
5682 code
= GET_CODE (x
);
5683 mode
= GET_MODE (x
);
5687 code
= GET_CODE (x
);
5688 mode
= wider_subreg_mode (mode
, GET_MODE (x
));
5696 int i
, nregs
, regno
= REGNO (x
);
5698 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5699 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5700 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5702 nregs
= hard_regno_nregs (regno
, mode
);
5703 for (i
= 0; i
< nregs
; i
++)
5704 if (! fixed_regs
[regno
+ i
]
5705 /* A hard register may be clobbered in the current insn
5706 but we can ignore this case because if the hard
5707 register is used it should be set somewhere after the
5709 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
5712 fmt
= GET_RTX_FORMAT (code
);
5713 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5717 if (! invariant_p (XEXP (x
, i
)))
5720 else if (fmt
[i
] == 'E')
5722 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5723 if (! invariant_p (XVECEXP (x
, i
, j
)))
5730 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5731 inheritance transformation (using dest_reg instead invariant in a
5732 subsequent insn). */
5734 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
5736 invariant_ptr_t invariant_ptr
;
5737 rtx_insn
*insn
, *new_insns
;
5738 rtx insn_set
, insn_reg
, new_reg
;
5740 bool succ_p
= false;
5741 int dst_regno
= REGNO (dst_reg
);
5742 machine_mode dst_mode
= GET_MODE (dst_reg
);
5743 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
5745 invariant_ptr
= insert_invariant (invariant_rtx
);
5746 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
5748 /* We have a subsequent insn using the invariant. */
5749 insn_set
= single_set (insn
);
5750 lra_assert (insn_set
!= NULL
);
5751 insn_reg
= SET_DEST (insn_set
);
5752 lra_assert (REG_P (insn_reg
));
5753 insn_regno
= REGNO (insn_reg
);
5754 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
5756 if (dst_mode
== GET_MODE (insn_reg
)
5757 /* We should consider only result move reg insns which are
5759 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
5760 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
5762 if (lra_dump_file
!= NULL
)
5763 fprintf (lra_dump_file
,
5764 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5765 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
5766 cl
, "invariant inheritance");
5767 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5768 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5769 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
5771 lra_emit_move (new_reg
, dst_reg
);
5772 new_insns
= get_insns ();
5774 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
5775 "Add invariant inheritance<-original");
5777 lra_emit_move (SET_DEST (insn_set
), new_reg
);
5778 new_insns
= get_insns ();
5780 lra_process_new_insns (insn
, NULL
, new_insns
,
5781 "Changing reload<-inheritance");
5782 lra_set_insn_deleted (insn
);
5784 if (lra_dump_file
!= NULL
)
5786 fprintf (lra_dump_file
,
5787 " Invariant inheritance reuse change %d (bb%d):\n",
5788 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5789 dump_insn_slim (lra_dump_file
, insn
);
5790 fprintf (lra_dump_file
,
5791 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5795 invariant_ptr
->insn
= curr_insn
;
5799 /* Check only registers living at the current program point in the
5801 static bitmap_head live_regs
;
5803 /* Update live info in EBB given by its HEAD and TAIL insns after
5804 inheritance/split transformation. The function removes dead moves
5807 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5812 rtx_insn
*prev_insn
;
5815 basic_block last_bb
, prev_bb
, curr_bb
;
5817 struct lra_insn_reg
*reg
;
5821 last_bb
= BLOCK_FOR_INSN (tail
);
5823 for (curr_insn
= tail
;
5824 curr_insn
!= PREV_INSN (head
);
5825 curr_insn
= prev_insn
)
5827 prev_insn
= PREV_INSN (curr_insn
);
5828 /* We need to process empty blocks too. They contain
5829 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5830 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5832 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5833 if (curr_bb
!= prev_bb
)
5835 if (prev_bb
!= NULL
)
5837 /* Update df_get_live_in (prev_bb): */
5838 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5839 if (bitmap_bit_p (&live_regs
, j
))
5840 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5842 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5844 if (curr_bb
!= last_bb
)
5846 /* Update df_get_live_out (curr_bb): */
5847 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5849 live_p
= bitmap_bit_p (&live_regs
, j
);
5851 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5852 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5858 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5860 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5864 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5866 if (! NONDEBUG_INSN_P (curr_insn
))
5868 curr_id
= lra_get_insn_recog_data (curr_insn
);
5869 curr_static_id
= curr_id
->insn_static_data
;
5871 if ((set
= single_set (curr_insn
)) != NULL_RTX
5872 && REG_P (SET_DEST (set
))
5873 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5874 && SET_DEST (set
) != pic_offset_table_rtx
5875 && bitmap_bit_p (&check_only_regs
, regno
)
5876 && ! bitmap_bit_p (&live_regs
, regno
))
5878 /* See which defined values die here. */
5879 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5880 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5881 bitmap_clear_bit (&live_regs
, reg
->regno
);
5882 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5883 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5884 bitmap_clear_bit (&live_regs
, reg
->regno
);
5885 if (curr_id
->arg_hard_regs
!= NULL
)
5886 /* Make clobbered argument hard registers die. */
5887 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5888 if (regno
>= FIRST_PSEUDO_REGISTER
)
5889 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
5890 /* Mark each used value as live. */
5891 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5892 if (reg
->type
!= OP_OUT
5893 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5894 bitmap_set_bit (&live_regs
, reg
->regno
);
5895 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5896 if (reg
->type
!= OP_OUT
5897 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5898 bitmap_set_bit (&live_regs
, reg
->regno
);
5899 if (curr_id
->arg_hard_regs
!= NULL
)
5900 /* Make used argument hard registers live. */
5901 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5902 if (regno
< FIRST_PSEUDO_REGISTER
5903 && bitmap_bit_p (&check_only_regs
, regno
))
5904 bitmap_set_bit (&live_regs
, regno
);
5905 /* It is quite important to remove dead move insns because it
5906 means removing dead store. We don't need to process them for
5910 if (lra_dump_file
!= NULL
)
5912 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5913 dump_insn_slim (lra_dump_file
, curr_insn
);
5915 lra_set_insn_deleted (curr_insn
);
5920 /* The structure describes info to do an inheritance for the current
5921 insn. We need to collect such info first before doing the
5922 transformations because the transformations change the insn
5923 internal representation. */
5926 /* Original regno. */
5928 /* Subsequent insns which can inherit original reg value. */
5932 /* Array containing all info for doing inheritance from the current
5934 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5936 /* Number elements in the previous array. */
5937 static int to_inherit_num
;
5939 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5940 structure to_inherit. */
5942 add_to_inherit (int regno
, rtx insns
)
5946 for (i
= 0; i
< to_inherit_num
; i
++)
5947 if (to_inherit
[i
].regno
== regno
)
5949 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5950 to_inherit
[to_inherit_num
].regno
= regno
;
5951 to_inherit
[to_inherit_num
++].insns
= insns
;
5954 /* Return the last non-debug insn in basic block BB, or the block begin
5957 get_last_insertion_point (basic_block bb
)
5961 FOR_BB_INSNS_REVERSE (bb
, insn
)
5962 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5967 /* Set up RES by registers living on edges FROM except the edge (FROM,
5968 TO) or by registers set up in a jump insn in BB FROM. */
5970 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5973 struct lra_insn_reg
*reg
;
5977 lra_assert (to
!= NULL
);
5979 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5981 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5982 last
= get_last_insertion_point (from
);
5983 if (! JUMP_P (last
))
5985 curr_id
= lra_get_insn_recog_data (last
);
5986 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5987 if (reg
->type
!= OP_IN
)
5988 bitmap_set_bit (res
, reg
->regno
);
5991 /* Used as a temporary results of some bitmap calculations. */
5992 static bitmap_head temp_bitmap
;
5994 /* We split for reloads of small class of hard regs. The following
5995 defines how many hard regs the class should have to be qualified as
5996 small. The code is mostly oriented to x86/x86-64 architecture
5997 where some insns need to use only specific register or pair of
5998 registers and these register can live in RTL explicitly, e.g. for
5999 parameter passing. */
6000 static const int max_small_class_regs_num
= 2;
6002 /* Do inheritance/split transformations in EBB starting with HEAD and
6003 finishing on TAIL. We process EBB insns in the reverse order.
6004 Return true if we did any inheritance/split transformation in the
6007 We should avoid excessive splitting which results in worse code
6008 because of inaccurate cost calculations for spilling new split
6009 pseudos in such case. To achieve this we do splitting only if
6010 register pressure is high in given basic block and there are reload
6011 pseudos requiring hard registers. We could do more register
6012 pressure calculations at any given program point to avoid necessary
6013 splitting even more but it is to expensive and the current approach
6014 works well enough. */
6016 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6018 int i
, src_regno
, dst_regno
, nregs
;
6019 bool change_p
, succ_p
, update_reloads_num_p
;
6020 rtx_insn
*prev_insn
, *last_insn
;
6021 rtx next_usage_insns
, curr_set
;
6023 struct lra_insn_reg
*reg
;
6024 basic_block last_processed_bb
, curr_bb
= NULL
;
6025 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6029 bool head_p
, after_p
;
6032 curr_usage_insns_check
++;
6033 clear_invariants ();
6034 reloads_num
= calls_num
= 0;
6035 bitmap_clear (&check_only_regs
);
6036 bitmap_clear (&invalid_invariant_regs
);
6037 last_processed_bb
= NULL
;
6038 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6039 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
6040 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
6041 /* We don't process new insns generated in the loop. */
6042 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6044 prev_insn
= PREV_INSN (curr_insn
);
6045 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6046 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6047 if (last_processed_bb
!= curr_bb
)
6049 /* We are at the end of BB. Add qualified living
6050 pseudos for potential splitting. */
6051 to_process
= df_get_live_out (curr_bb
);
6052 if (last_processed_bb
!= NULL
)
6054 /* We are somewhere in the middle of EBB. */
6055 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6057 to_process
= &temp_bitmap
;
6059 last_processed_bb
= curr_bb
;
6060 last_insn
= get_last_insertion_point (curr_bb
);
6061 after_p
= (! JUMP_P (last_insn
)
6062 && (! CALL_P (last_insn
)
6063 || (find_reg_note (last_insn
,
6064 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6065 && ! SIBLING_CALL_P (last_insn
))));
6066 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6067 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6069 if ((int) j
>= lra_constraint_new_regno_start
)
6071 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6073 if (j
< FIRST_PSEUDO_REGISTER
)
6074 SET_HARD_REG_BIT (live_hard_regs
, j
);
6076 add_to_hard_reg_set (&live_hard_regs
,
6077 PSEUDO_REGNO_MODE (j
),
6079 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6083 src_regno
= dst_regno
= -1;
6084 curr_set
= single_set (curr_insn
);
6085 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6086 dst_regno
= REGNO (SET_DEST (curr_set
));
6087 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6088 src_regno
= REGNO (SET_SRC (curr_set
));
6089 update_reloads_num_p
= true;
6090 if (src_regno
< lra_constraint_new_regno_start
6091 && src_regno
>= FIRST_PSEUDO_REGISTER
6092 && reg_renumber
[src_regno
] < 0
6093 && dst_regno
>= lra_constraint_new_regno_start
6094 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6096 /* 'reload_pseudo <- original_pseudo'. */
6097 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6099 update_reloads_num_p
= false;
6101 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6102 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6103 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6104 curr_insn
, next_usage_insns
);
6108 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6109 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6110 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6111 reg_class_contents
[cl
]);
6113 else if (src_regno
< 0
6114 && dst_regno
>= lra_constraint_new_regno_start
6115 && invariant_p (SET_SRC (curr_set
))
6116 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6117 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6118 && ! bitmap_bit_p (&invalid_invariant_regs
,
6119 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6121 /* 'reload_pseudo <- invariant'. */
6122 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6124 update_reloads_num_p
= false;
6125 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6127 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6128 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6129 reg_class_contents
[cl
]);
6131 else if (src_regno
>= lra_constraint_new_regno_start
6132 && dst_regno
< lra_constraint_new_regno_start
6133 && dst_regno
>= FIRST_PSEUDO_REGISTER
6134 && reg_renumber
[dst_regno
] < 0
6135 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6136 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6137 && (next_usage_insns
6138 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6140 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6142 update_reloads_num_p
= false;
6143 /* 'original_pseudo <- reload_pseudo'. */
6144 if (! JUMP_P (curr_insn
)
6145 && inherit_reload_reg (true, dst_regno
, cl
,
6146 curr_insn
, next_usage_insns
))
6149 usage_insns
[dst_regno
].check
= 0;
6150 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6151 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6152 reg_class_contents
[cl
]);
6154 else if (INSN_P (curr_insn
))
6157 int max_uid
= get_max_uid ();
6159 curr_id
= lra_get_insn_recog_data (curr_insn
);
6160 curr_static_id
= curr_id
->insn_static_data
;
6162 /* Process insn definitions. */
6163 for (iter
= 0; iter
< 2; iter
++)
6164 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6167 if (reg
->type
!= OP_IN
6168 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6170 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6171 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6172 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6173 && (next_usage_insns
6174 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6176 struct lra_insn_reg
*r
;
6178 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6179 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6181 /* Don't do inheritance if the pseudo is also
6182 used in the insn. */
6184 /* We can not do inheritance right now
6185 because the current insn reg info (chain
6186 regs) can change after that. */
6187 add_to_inherit (dst_regno
, next_usage_insns
);
6189 /* We can not process one reg twice here because of
6190 usage_insns invalidation. */
6191 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6192 || reg_renumber
[dst_regno
] >= 0)
6193 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6197 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6198 potential_reload_hard_regs
,
6199 false, curr_insn
, max_uid
))
6201 CLEAR_HARD_REG_SET (s
);
6202 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6203 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6205 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6206 reg_renumber
[dst_regno
]);
6207 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
6209 /* We should invalidate potential inheritance or
6210 splitting for the current insn usages to the next
6211 usage insns (see code below) as the output pseudo
6213 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6214 && reg_renumber
[dst_regno
] < 0)
6215 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6216 && (dst_regno
< FIRST_PSEUDO_REGISTER
6217 || reg_renumber
[dst_regno
] >= 0)))
6219 /* Invalidate and mark definitions. */
6220 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6221 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6224 nregs
= hard_regno_nregs (dst_regno
,
6226 for (i
= 0; i
< nregs
; i
++)
6227 usage_insns
[dst_regno
+ i
].check
6228 = -(int) INSN_UID (curr_insn
);
6232 /* Process clobbered call regs. */
6233 if (curr_id
->arg_hard_regs
!= NULL
)
6234 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6235 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6236 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6237 = -(int) INSN_UID (curr_insn
);
6238 if (! JUMP_P (curr_insn
))
6239 for (i
= 0; i
< to_inherit_num
; i
++)
6240 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6241 ALL_REGS
, curr_insn
,
6242 to_inherit
[i
].insns
))
6244 if (CALL_P (curr_insn
))
6246 rtx cheap
, pat
, dest
;
6248 int regno
, hard_regno
;
6251 if ((cheap
= find_reg_note (curr_insn
,
6252 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6253 && ((cheap
= XEXP (cheap
, 0)), true)
6254 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6255 && (hard_regno
= reg_renumber
[regno
]) >= 0
6256 && usage_insns
[regno
].check
== curr_usage_insns_check
6257 /* If there are pending saves/restores, the
6258 optimization is not worth. */
6259 && usage_insns
[regno
].calls_num
== calls_num
- 1
6260 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
6262 /* Restore the pseudo from the call result as
6263 REG_RETURNED note says that the pseudo value is
6264 in the call result and the pseudo is an argument
6266 pat
= PATTERN (curr_insn
);
6267 if (GET_CODE (pat
) == PARALLEL
)
6268 pat
= XVECEXP (pat
, 0, 0);
6269 dest
= SET_DEST (pat
);
6270 /* For multiple return values dest is PARALLEL.
6271 Currently we handle only single return value case. */
6275 emit_move_insn (cheap
, copy_rtx (dest
));
6276 restore
= get_insns ();
6278 lra_process_new_insns (curr_insn
, NULL
, restore
,
6279 "Inserting call parameter restore");
6280 /* We don't need to save/restore of the pseudo from
6282 usage_insns
[regno
].calls_num
= calls_num
;
6283 bitmap_set_bit (&check_only_regs
, regno
);
6288 /* Process insn usages. */
6289 for (iter
= 0; iter
< 2; iter
++)
6290 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6293 if ((reg
->type
!= OP_OUT
6294 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6295 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6297 if (src_regno
>= FIRST_PSEUDO_REGISTER
6298 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6300 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6301 && (next_usage_insns
6302 = usage_insns
[src_regno
].insns
) != NULL_RTX
6303 && NONDEBUG_INSN_P (curr_insn
))
6304 add_to_inherit (src_regno
, next_usage_insns
);
6305 else if (usage_insns
[src_regno
].check
6306 != -(int) INSN_UID (curr_insn
))
6307 /* Add usages but only if the reg is not set up
6308 in the same insn. */
6309 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6311 else if (src_regno
< FIRST_PSEUDO_REGISTER
6312 || reg_renumber
[src_regno
] >= 0)
6315 rtx_insn
*use_insn
= curr_insn
;
6317 before_p
= (JUMP_P (curr_insn
)
6318 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6319 if (NONDEBUG_INSN_P (curr_insn
)
6320 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6321 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6322 potential_reload_hard_regs
,
6323 before_p
, curr_insn
, max_uid
))
6326 lra_risky_transformations_p
= true;
6329 usage_insns
[src_regno
].check
= 0;
6331 use_insn
= PREV_INSN (curr_insn
);
6333 if (NONDEBUG_INSN_P (curr_insn
))
6335 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6336 add_to_hard_reg_set (&live_hard_regs
,
6337 reg
->biggest_mode
, src_regno
);
6339 add_to_hard_reg_set (&live_hard_regs
,
6340 PSEUDO_REGNO_MODE (src_regno
),
6341 reg_renumber
[src_regno
]);
6343 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6346 /* Process used call regs. */
6347 if (curr_id
->arg_hard_regs
!= NULL
)
6348 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6349 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6351 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6352 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6354 for (i
= 0; i
< to_inherit_num
; i
++)
6356 src_regno
= to_inherit
[i
].regno
;
6357 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6358 curr_insn
, to_inherit
[i
].insns
))
6361 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6364 if (update_reloads_num_p
6365 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6368 if ((REG_P (SET_DEST (curr_set
))
6369 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6370 && reg_renumber
[regno
] < 0
6371 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6372 || (REG_P (SET_SRC (curr_set
))
6373 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6374 && reg_renumber
[regno
] < 0
6375 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6377 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6379 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6380 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6381 reg_class_contents
[cl
]);
6384 if (NONDEBUG_INSN_P (curr_insn
))
6388 /* Invalidate invariants with changed regs. */
6389 curr_id
= lra_get_insn_recog_data (curr_insn
);
6390 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6391 if (reg
->type
!= OP_IN
)
6393 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6394 bitmap_set_bit (&invalid_invariant_regs
,
6395 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6397 curr_static_id
= curr_id
->insn_static_data
;
6398 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6399 if (reg
->type
!= OP_IN
)
6400 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6401 if (curr_id
->arg_hard_regs
!= NULL
)
6402 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6403 if (regno
>= FIRST_PSEUDO_REGISTER
)
6404 bitmap_set_bit (&invalid_invariant_regs
,
6405 regno
- FIRST_PSEUDO_REGISTER
);
6407 /* We reached the start of the current basic block. */
6408 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6409 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6411 /* We reached the beginning of the current block -- do
6412 rest of spliting in the current BB. */
6413 to_process
= df_get_live_in (curr_bb
);
6414 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6416 /* We are somewhere in the middle of EBB. */
6417 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6418 curr_bb
, &temp_bitmap
);
6419 to_process
= &temp_bitmap
;
6422 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6424 if ((int) j
>= lra_constraint_new_regno_start
)
6426 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6427 && usage_insns
[j
].check
== curr_usage_insns_check
6428 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6430 if (need_for_split_p (potential_reload_hard_regs
, j
))
6432 if (lra_dump_file
!= NULL
&& head_p
)
6434 fprintf (lra_dump_file
,
6435 " ----------------------------------\n");
6438 if (split_reg (false, j
, bb_note (curr_bb
),
6442 usage_insns
[j
].check
= 0;
6450 /* This value affects EBB forming. If probability of edge from EBB to
6451 a BB is not greater than the following value, we don't add the BB
6453 #define EBB_PROBABILITY_CUTOFF \
6454 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6456 /* Current number of inheritance/split iteration. */
6457 int lra_inheritance_iter
;
6459 /* Entry function for inheritance/split pass. */
6461 lra_inheritance (void)
6464 basic_block bb
, start_bb
;
6467 lra_inheritance_iter
++;
6468 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6470 timevar_push (TV_LRA_INHERITANCE
);
6471 if (lra_dump_file
!= NULL
)
6472 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6473 lra_inheritance_iter
);
6474 curr_usage_insns_check
= 0;
6475 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6476 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6477 usage_insns
[i
].check
= 0;
6478 bitmap_initialize (&check_only_regs
, ®_obstack
);
6479 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6480 bitmap_initialize (&live_regs
, ®_obstack
);
6481 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6482 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6483 FOR_EACH_BB_FN (bb
, cfun
)
6486 if (lra_dump_file
!= NULL
)
6487 fprintf (lra_dump_file
, "EBB");
6488 /* Form a EBB starting with BB. */
6489 bitmap_clear (&ebb_global_regs
);
6490 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6493 if (lra_dump_file
!= NULL
)
6494 fprintf (lra_dump_file
, " %d", bb
->index
);
6495 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6496 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6498 e
= find_fallthru_edge (bb
->succs
);
6501 if (e
->probability
.initialized_p ()
6502 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
6506 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6507 if (lra_dump_file
!= NULL
)
6508 fprintf (lra_dump_file
, "\n");
6509 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6510 /* Remember that the EBB head and tail can change in
6512 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6514 bitmap_clear (&ebb_global_regs
);
6515 bitmap_clear (&temp_bitmap
);
6516 bitmap_clear (&live_regs
);
6517 bitmap_clear (&invalid_invariant_regs
);
6518 bitmap_clear (&check_only_regs
);
6521 timevar_pop (TV_LRA_INHERITANCE
);
6526 /* This page contains code to undo failed inheritance/split
6529 /* Current number of iteration undoing inheritance/split. */
6530 int lra_undo_inheritance_iter
;
6532 /* Fix BB live info LIVE after removing pseudos created on pass doing
6533 inheritance/split which are REMOVED_PSEUDOS. */
6535 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6540 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6541 if (bitmap_clear_bit (live
, regno
)
6542 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6543 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6546 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6551 if (GET_CODE (reg
) == SUBREG
)
6552 reg
= SUBREG_REG (reg
);
6558 /* Delete a move INSN with destination reg DREGNO and a previous
6559 clobber insn with the same regno. The inheritance/split code can
6560 generate moves with preceding clobber and when we delete such moves
6561 we should delete the clobber insn too to keep the correct life
6564 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6566 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6568 lra_set_insn_deleted (insn
);
6569 lra_assert (dregno
>= 0);
6570 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6571 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6572 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6573 lra_set_insn_deleted (prev_insn
);
6576 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6577 return true if we did any change. The undo transformations for
6578 inheritance looks like
6582 p <- i, i <- p, and i <- i3
6583 where p is original pseudo from which inheritance pseudo i was
6584 created, i and i3 are removed inheritance pseudos, i2 is another
6585 not removed inheritance pseudo. All split pseudos or other
6586 occurrences of removed inheritance pseudos are changed on the
6587 corresponding original pseudos.
6589 The function also schedules insns changed and created during
6590 inheritance/split pass for processing by the subsequent constraint
6593 remove_inheritance_pseudos (bitmap remove_pseudos
)
6596 int regno
, sregno
, prev_sregno
, dregno
;
6599 rtx_insn
*prev_insn
;
6600 bool change_p
, done_p
;
6602 change_p
= ! bitmap_empty_p (remove_pseudos
);
6603 /* We can not finish the function right away if CHANGE_P is true
6604 because we need to marks insns affected by previous
6605 inheritance/split pass for processing by the subsequent
6607 FOR_EACH_BB_FN (bb
, cfun
)
6609 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6610 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6611 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6613 if (! INSN_P (curr_insn
))
6616 sregno
= dregno
= -1;
6617 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6618 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6620 dregno
= get_regno (SET_DEST (set
));
6621 sregno
= get_regno (SET_SRC (set
));
6624 if (sregno
>= 0 && dregno
>= 0)
6626 if (bitmap_bit_p (remove_pseudos
, dregno
)
6627 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6629 /* invariant inheritance pseudo <- original pseudo */
6630 if (lra_dump_file
!= NULL
)
6632 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6633 dump_insn_slim (lra_dump_file
, curr_insn
);
6634 fprintf (lra_dump_file
, "\n");
6636 delete_move_and_clobber (curr_insn
, dregno
);
6639 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6640 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6642 /* reload pseudo <- invariant inheritance pseudo */
6644 /* We can not just change the source. It might be
6645 an insn different from the move. */
6646 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6647 rtx_insn
*new_insns
= get_insns ();
6649 lra_assert (single_set (new_insns
) != NULL
6650 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6651 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6652 "Changing reload<-invariant inheritance");
6653 delete_move_and_clobber (curr_insn
, dregno
);
6656 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6657 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6658 || (bitmap_bit_p (remove_pseudos
, dregno
)
6659 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6660 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6661 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6662 || (bitmap_bit_p (remove_pseudos
, dregno
)
6663 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6664 /* One of the following cases:
6665 original <- removed inheritance pseudo
6666 removed inherit pseudo <- another removed inherit pseudo
6667 removed inherit pseudo <- original pseudo
6669 removed_split_pseudo <- original_reg
6670 original_reg <- removed_split_pseudo */
6672 if (lra_dump_file
!= NULL
)
6674 fprintf (lra_dump_file
, " Removing %s:\n",
6675 bitmap_bit_p (&lra_split_regs
, sregno
)
6676 || bitmap_bit_p (&lra_split_regs
, dregno
)
6677 ? "split" : "inheritance");
6678 dump_insn_slim (lra_dump_file
, curr_insn
);
6680 delete_move_and_clobber (curr_insn
, dregno
);
6683 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6684 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6686 /* Search the following pattern:
6687 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6688 original_pseudo <- inherit_or_split_pseudo1
6689 where the 2nd insn is the current insn and
6690 inherit_or_split_pseudo2 is not removed. If it is found,
6691 change the current insn onto:
6692 original_pseudo <- inherit_or_split_pseudo2. */
6693 for (prev_insn
= PREV_INSN (curr_insn
);
6694 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6695 prev_insn
= PREV_INSN (prev_insn
))
6697 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6698 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6699 /* There should be no subregs in insn we are
6700 searching because only the original reg might
6701 be in subreg when we changed the mode of
6702 load/store for splitting. */
6703 && REG_P (SET_DEST (prev_set
))
6704 && REG_P (SET_SRC (prev_set
))
6705 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6706 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6707 >= FIRST_PSEUDO_REGISTER
)
6708 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
6710 /* As we consider chain of inheritance or
6711 splitting described in above comment we should
6712 check that sregno and prev_sregno were
6713 inheritance/split pseudos created from the
6714 same original regno. */
6715 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6716 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6717 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
6718 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6720 lra_assert (GET_MODE (SET_SRC (prev_set
))
6721 == GET_MODE (regno_reg_rtx
[sregno
]));
6722 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
6723 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
6725 SET_SRC (set
) = SET_SRC (prev_set
);
6726 /* As we are finishing with processing the insn
6727 here, check the destination too as it might
6728 inheritance pseudo for another pseudo. */
6729 if (bitmap_bit_p (remove_pseudos
, dregno
)
6730 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6732 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
6734 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6735 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
6737 SET_DEST (set
) = restore_rtx
;
6739 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6740 lra_set_used_insn_alternative_by_uid
6741 (INSN_UID (curr_insn
), -1);
6743 if (lra_dump_file
!= NULL
)
6745 fprintf (lra_dump_file
, " Change reload insn:\n");
6746 dump_insn_slim (lra_dump_file
, curr_insn
);
6753 struct lra_insn_reg
*reg
;
6754 bool restored_regs_p
= false;
6755 bool kept_regs_p
= false;
6757 curr_id
= lra_get_insn_recog_data (curr_insn
);
6758 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6761 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
6762 if (restore_rtx
!= NULL_RTX
)
6764 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6766 lra_substitute_pseudo_within_insn
6767 (curr_insn
, regno
, restore_rtx
, false);
6768 restored_regs_p
= true;
6774 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6776 /* The instruction has changed since the previous
6777 constraints pass. */
6778 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6779 lra_set_used_insn_alternative_by_uid
6780 (INSN_UID (curr_insn
), -1);
6782 else if (restored_regs_p
)
6783 /* The instruction has been restored to the form that
6784 it had during the previous constraints pass. */
6785 lra_update_insn_regno_info (curr_insn
);
6786 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6788 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6789 dump_insn_slim (lra_dump_file
, curr_insn
);
6797 /* If optional reload pseudos failed to get a hard register or was not
6798 inherited, it is better to remove optional reloads. We do this
6799 transformation after undoing inheritance to figure out necessity to
6800 remove optional reloads easier. Return true if we do any
6803 undo_optional_reloads (void)
6805 bool change_p
, keep_p
;
6806 unsigned int regno
, uid
;
6807 bitmap_iterator bi
, bi2
;
6810 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
6812 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6813 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6816 /* Keep optional reloads from previous subpasses. */
6817 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
6818 /* If the original pseudo changed its allocation, just
6819 removing the optional pseudo is dangerous as the original
6820 pseudo will have longer live range. */
6821 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
6823 else if (reg_renumber
[regno
] >= 0)
6824 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6826 insn
= lra_insn_recog_data
[uid
]->insn
;
6827 if ((set
= single_set (insn
)) == NULL_RTX
)
6829 src
= SET_SRC (set
);
6830 dest
= SET_DEST (set
);
6831 if (! REG_P (src
) || ! REG_P (dest
))
6833 if (REGNO (dest
) == regno
6834 /* Ignore insn for optional reloads itself. */
6835 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
6836 /* Check only inheritance on last inheritance pass. */
6837 && (int) REGNO (src
) >= new_regno_start
6838 /* Check that the optional reload was inherited. */
6839 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6847 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
6848 if (lra_dump_file
!= NULL
)
6849 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6852 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
6853 auto_bitmap
insn_bitmap (®_obstack
);
6854 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
6856 if (lra_dump_file
!= NULL
)
6857 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6858 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6859 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
6861 insn
= lra_insn_recog_data
[uid
]->insn
;
6862 if ((set
= single_set (insn
)) != NULL_RTX
)
6864 src
= SET_SRC (set
);
6865 dest
= SET_DEST (set
);
6866 if (REG_P (src
) && REG_P (dest
)
6867 && ((REGNO (src
) == regno
6868 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6870 || (REGNO (dest
) == regno
6871 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6874 if (lra_dump_file
!= NULL
)
6876 fprintf (lra_dump_file
, " Deleting move %u\n",
6878 dump_insn_slim (lra_dump_file
, insn
);
6880 delete_move_and_clobber (insn
, REGNO (dest
));
6883 /* We should not worry about generation memory-memory
6884 moves here as if the corresponding inheritance did
6885 not work (inheritance pseudo did not get a hard reg),
6886 we remove the inheritance pseudo and the optional
6889 lra_substitute_pseudo_within_insn
6890 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
6891 lra_update_insn_regno_info (insn
);
6892 if (lra_dump_file
!= NULL
)
6894 fprintf (lra_dump_file
,
6895 " Restoring original insn:\n");
6896 dump_insn_slim (lra_dump_file
, insn
);
6900 /* Clear restore_regnos. */
6901 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6902 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6906 /* Entry function for undoing inheritance/split transformation. Return true
6907 if we did any RTL change in this pass. */
6909 lra_undo_inheritance (void)
6913 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6918 lra_undo_inheritance_iter
++;
6919 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6921 if (lra_dump_file
!= NULL
)
6922 fprintf (lra_dump_file
,
6923 "\n********** Undoing inheritance #%d: **********\n\n",
6924 lra_undo_inheritance_iter
);
6925 auto_bitmap
remove_pseudos (®_obstack
);
6926 n_inherit
= n_all_inherit
= 0;
6927 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6928 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
6931 if (reg_renumber
[regno
] < 0
6932 /* If the original pseudo changed its allocation, just
6933 removing inheritance is dangerous as for changing
6934 allocation we used shorter live-ranges. */
6935 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
6936 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
6937 bitmap_set_bit (remove_pseudos
, regno
);
6941 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6942 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6943 n_inherit
, n_all_inherit
,
6944 (double) n_inherit
/ n_all_inherit
* 100);
6945 n_split
= n_all_split
= 0;
6946 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6947 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
6949 int restore_regno
= REGNO (restore_rtx
);
6952 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6953 ? reg_renumber
[restore_regno
] : restore_regno
);
6954 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6955 bitmap_set_bit (remove_pseudos
, regno
);
6959 if (lra_dump_file
!= NULL
)
6960 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6961 regno
, restore_regno
);
6964 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6965 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6966 n_split
, n_all_split
,
6967 (double) n_split
/ n_all_split
* 100);
6968 change_p
= remove_inheritance_pseudos (remove_pseudos
);
6969 /* Clear restore_regnos. */
6970 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6971 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6972 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6973 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6974 change_p
= undo_optional_reloads () || change_p
;