1 ; Options for the ARM port of the compiler.
3 ; Copyright (C) 2005, 2007, 2008, 2009, 2011 Free Software Foundation, Inc.
5 ; This file is part of GCC.
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
9 ; Software Foundation; either version 3, or (at your option) any later
12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ; You should have received a copy of the GNU General Public License
18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>.
25 Target RejectNegative Joined Enum(arm_abi_type) Var(arm_abi) Init(ARM_DEFAULT_ABI)
29 Name(arm_abi_type) Type(enum arm_abi_type)
30 Known ARM ABIs (for use with the -mabi= option):
33 Enum(arm_abi_type) String(apcs-gnu) Value(ARM_ABI_APCS)
36 Enum(arm_abi_type) String(atpcs) Value(ARM_ABI_ATPCS)
39 Enum(arm_abi_type) String(aapcs) Value(ARM_ABI_AAPCS)
42 Enum(arm_abi_type) String(iwmmxt) Value(ARM_ABI_IWMMXT)
45 Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX)
48 Target Report Mask(ABORT_NORETURN)
49 Generate a call to abort if a noreturn function returns
52 Target RejectNegative Mask(APCS_FRAME) MaskExists Undocumented
55 Target Report Mask(APCS_FLOAT)
56 Pass FP arguments in FP registers
59 Target Report Mask(APCS_FRAME)
60 Generate APCS conformant stack frames
63 Target Report Mask(APCS_REENT)
64 Generate re-entrant, PIC code
67 Target Report Mask(APCS_STACK) Undocumented
70 Target RejectNegative Joined Enum(arm_arch) Var(arm_arch_option)
71 Specify the name of the target architecture
74 Target Report RejectNegative InverseMask(THUMB)
75 Generate code in 32 bit ARM state.
78 Target Report RejectNegative Mask(BIG_END)
79 Assume target CPU is configured as big endian
81 mcallee-super-interworking
82 Target Report Mask(CALLEE_INTERWORKING)
83 Thumb: Assume non-static functions may be called from ARM code
85 mcaller-super-interworking
86 Target Report Mask(CALLER_INTERWORKING)
87 Thumb: Assume function pointers may go to non-Thumb aware code
89 mcirrus-fix-invalid-insns
90 Target Report Mask(CIRRUS_FIX_INVALID_INSNS)
91 Cirrus: Place NOPs to avoid invalid instruction combinations
94 Target RejectNegative Joined Enum(processor_type) Var(arm_cpu_option) Init(arm_none)
95 Specify the name of the target CPU
98 Target RejectNegative Joined Enum(float_abi_type) Var(arm_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI)
99 Specify if floating point hardware should be used
102 Name(float_abi_type) Type(enum float_abi_type)
103 Known floating-point ABIs (for use with the -mfloat-abi= option):
106 Enum(float_abi_type) String(soft) Value(ARM_FLOAT_ABI_SOFT)
109 Enum(float_abi_type) String(softfp) Value(ARM_FLOAT_ABI_SOFTFP)
112 Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD)
115 Target RejectNegative Undocumented Alias(mfpu=, fpe2)
118 Target RejectNegative Undocumented Alias(mfpu=, fpe3)
121 Target RejectNegative Joined Enum(arm_fp16_format_type) Var(arm_fp16_format) Init(ARM_FP16_FORMAT_NONE)
122 Specify the __fp16 floating-point format
125 Name(arm_fp16_format_type) Type(enum arm_fp16_format_type)
126 Known __fp16 formats (for use with the -mfp16-format= option):
129 Enum(arm_fp16_format_type) String(none) Value(ARM_FP16_FORMAT_NONE)
132 Enum(arm_fp16_format_type) String(ieee) Value(ARM_FP16_FORMAT_IEEE)
135 Enum(arm_fp16_format_type) String(alternative) Value(ARM_FP16_FORMAT_ALTERNATIVE)
139 Target RejectNegative Mask(FPE) Undocumented
142 Target RejectNegative Undocumented Alias(mfpu=, fpe2)
145 Target RejectNegative Undocumented Alias(mfpu=, fpe3)
148 Target RejectNegative Joined Var(target_fpu_name)
149 Specify the name of the target floating point hardware/format
152 Target RejectNegative Alias(mfloat-abi=, hard) Undocumented
155 Target Report RejectNegative InverseMask(BIG_END)
156 Assume target CPU is configured as little endian
159 Target Report Mask(LONG_CALLS)
160 Generate call insns as indirect calls, if necessary
163 Target RejectNegative Joined Var(arm_pic_register_string)
164 Specify the register to be used for PIC addressing
167 Target Report Mask(POKE_FUNCTION_NAME)
168 Store function names in object code
171 Target Report Mask(SCHED_PROLOG)
172 Permit scheduling of a function's prologue sequence
175 Target Report Mask(SINGLE_PIC_BASE)
176 Do not load the PIC register in function prologues
179 Target RejectNegative Alias(mfloat-abi=, soft) Undocumented
181 mstructure-size-boundary=
182 Target RejectNegative Joined UInteger Var(arm_structure_size_boundary) Init(DEFAULT_STRUCTURE_SIZE_BOUNDARY)
183 Specify the minimum bit alignment of structures
186 Target Report RejectNegative Mask(THUMB)
187 Generate code for Thumb state
190 Target Report Mask(INTERWORK)
191 Support calls between Thumb and ARM instruction sets
194 Target RejectNegative Joined Enum(arm_tp_type) Var(target_thread_pointer) Init(TP_AUTO)
195 Specify how to access the thread pointer
198 Name(arm_tp_type) Type(enum arm_tp_type)
199 Valid arguments to -mtp=:
202 Enum(arm_tp_type) String(soft) Value(TP_SOFT)
205 Enum(arm_tp_type) String(auto) Value(TP_AUTO)
208 Enum(arm_tp_type) String(cp15) Value(TP_CP15)
211 Target Report Mask(TPCS_FRAME)
212 Thumb: Generate (non-leaf) stack frames even if not needed
215 Target Report Mask(TPCS_LEAF_FRAME)
216 Thumb: Generate (leaf) stack frames even if not needed
219 Target RejectNegative Joined Enum(processor_type) Var(arm_tune_option) Init(arm_none)
220 Tune code for the given processor
223 Target Report RejectNegative Mask(LITTLE_WORDS)
224 Assume big endian bytes, little endian words
226 mvectorize-with-neon-quad
227 Target Report Mask(NEON_VECTORIZE_QUAD)
228 Use Neon quad-word (rather than double-word) registers for vectorization
231 Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
232 Only generate absolute relocations on word sized values.
235 Target Report Var(fix_cm3_ldrd) Init(2)
236 Avoid overlapping destination and address registers on LDRD instructions
237 that may trigger Cortex-M3 errata.